drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #define MODULENAME "r8169"
  36
  37 #define FIRMWARE_8168D_1        "/*(DEBLOBBED)*/"
  38 #define FIRMWARE_8168D_2        "/*(DEBLOBBED)*/"
  39 #define FIRMWARE_8168E_1        "/*(DEBLOBBED)*/"
  40 #define FIRMWARE_8168E_2        "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_8168E_3        "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_8168F_1        "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_8168F_2        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_8105E_1        "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_8402_1         "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_8411_1         "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_8411_2         "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_8106E_1        "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_8106E_2        "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_8168G_2        "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_8168G_3        "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_8168H_1        "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_8168H_2        "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_8107E_1        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_8107E_2        "/*(DEBLOBBED)*/"
  56
  57 #define R8169_MSG_DEFAULT \
  58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  59
  60 #define TX_SLOTS_AVAIL(tp) \
  61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  62
  63 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  64 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  65         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  66
  67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  68    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  69 static const int multicast_filter_limit = 32;
  70
  71 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  72 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  73
  74 #define R8169_REGS_SIZE         256
  75 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  76 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  77 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82
  83 /* write/read MMIO register */
  84 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  85 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  86 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  87 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  88 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  89 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  90
  91 enum mac_version {
  92         RTL_GIGA_MAC_VER_01 = 0,
  93         RTL_GIGA_MAC_VER_02,
  94         RTL_GIGA_MAC_VER_03,
  95         RTL_GIGA_MAC_VER_04,
  96         RTL_GIGA_MAC_VER_05,
  97         RTL_GIGA_MAC_VER_06,
  98         RTL_GIGA_MAC_VER_07,
  99         RTL_GIGA_MAC_VER_08,
 100         RTL_GIGA_MAC_VER_09,
 101         RTL_GIGA_MAC_VER_10,
 102         RTL_GIGA_MAC_VER_11,
 103         RTL_GIGA_MAC_VER_12,
 104         RTL_GIGA_MAC_VER_13,
 105         RTL_GIGA_MAC_VER_14,
 106         RTL_GIGA_MAC_VER_15,
 107         RTL_GIGA_MAC_VER_16,
 108         RTL_GIGA_MAC_VER_17,
 109         RTL_GIGA_MAC_VER_18,
 110         RTL_GIGA_MAC_VER_19,
 111         RTL_GIGA_MAC_VER_20,
 112         RTL_GIGA_MAC_VER_21,
 113         RTL_GIGA_MAC_VER_22,
 114         RTL_GIGA_MAC_VER_23,
 115         RTL_GIGA_MAC_VER_24,
 116         RTL_GIGA_MAC_VER_25,
 117         RTL_GIGA_MAC_VER_26,
 118         RTL_GIGA_MAC_VER_27,
 119         RTL_GIGA_MAC_VER_28,
 120         RTL_GIGA_MAC_VER_29,
 121         RTL_GIGA_MAC_VER_30,
 122         RTL_GIGA_MAC_VER_31,
 123         RTL_GIGA_MAC_VER_32,
 124         RTL_GIGA_MAC_VER_33,
 125         RTL_GIGA_MAC_VER_34,
 126         RTL_GIGA_MAC_VER_35,
 127         RTL_GIGA_MAC_VER_36,
 128         RTL_GIGA_MAC_VER_37,
 129         RTL_GIGA_MAC_VER_38,
 130         RTL_GIGA_MAC_VER_39,
 131         RTL_GIGA_MAC_VER_40,
 132         RTL_GIGA_MAC_VER_41,
 133         RTL_GIGA_MAC_VER_42,
 134         RTL_GIGA_MAC_VER_43,
 135         RTL_GIGA_MAC_VER_44,
 136         RTL_GIGA_MAC_VER_45,
 137         RTL_GIGA_MAC_VER_46,
 138         RTL_GIGA_MAC_VER_47,
 139         RTL_GIGA_MAC_VER_48,
 140         RTL_GIGA_MAC_VER_49,
 141         RTL_GIGA_MAC_VER_50,
 142         RTL_GIGA_MAC_VER_51,
 143         RTL_GIGA_MAC_NONE   = 0xff,
 144 };
 145
 146 #define JUMBO_1K        ETH_DATA_LEN
 147 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 148 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 149 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 150 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 151
 152 static const struct {
 153         const char *name;
 154         const char *fw_name;
 155 } rtl_chip_infos[] = {
 156         /* PCI devices. */
 157         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 158         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 159         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 160         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 161         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 162         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 163         /* PCI-E devices. */
 164         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 165         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 166         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 167         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 169         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 170         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 171         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 172         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 173         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 174         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 175         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 176         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 178         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 179         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 180         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 181         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 182         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 183         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 184         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 185         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 186         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 187         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 188         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 189         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 190         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 191         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 192         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 193         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 194         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 195         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 196         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 197         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 198         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 199         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 200         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 201         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 202         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 203         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 204         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 205         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 206         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 207         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 208         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 209 };
 210
 211 enum cfg_version {
 212         RTL_CFG_0 = 0x00,
 213         RTL_CFG_1,
 214         RTL_CFG_2
 215 };
 216
 217 static const struct pci_device_id rtl8169_pci_tbl[] = {
 218         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 219         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 220         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 221         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 222         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 223         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 224         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 225         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
 226         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 227         { PCI_VENDOR_ID_DLINK,                  0x4300,
 228                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 229         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 230         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 231         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 232         { PCI_DEVICE(PCI_VENDOR_ID_USR,         0x0116), 0, 0, RTL_CFG_0 },
 233         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 234                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 235         { 0x0001,                               0x8168,
 236                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 237         {0,},
 238 };
 239
 240 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 241
 242 static int use_dac = -1;
 243 static struct {
 244         u32 msg_enable;
 245 } debug = { -1 };
 246
 247 enum rtl_registers {
 248         MAC0            = 0,    /* Ethernet hardware address. */
 249         MAC4            = 4,
 250         MAR0            = 8,    /* Multicast filter. */
 251         CounterAddrLow          = 0x10,
 252         CounterAddrHigh         = 0x14,
 253         TxDescStartAddrLow      = 0x20,
 254         TxDescStartAddrHigh     = 0x24,
 255         TxHDescStartAddrLow     = 0x28,
 256         TxHDescStartAddrHigh    = 0x2c,
 257         FLASH           = 0x30,
 258         ERSR            = 0x36,
 259         ChipCmd         = 0x37,
 260         TxPoll          = 0x38,
 261         IntrMask        = 0x3c,
 262         IntrStatus      = 0x3e,
 263
 264         TxConfig        = 0x40,
 265 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 266 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 267
 268         RxConfig        = 0x44,
 269 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 270 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 271 #define RXCFG_FIFO_SHIFT                13
 272                                         /* No threshold before first PCI xfer */
 273 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 274 #define RX_EARLY_OFF                    (1 << 11)
 275 #define RXCFG_DMA_SHIFT                 8
 276                                         /* Unlimited maximum PCI burst. */
 277 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 278
 279         RxMissed        = 0x4c,
 280         Cfg9346         = 0x50,
 281         Config0         = 0x51,
 282         Config1         = 0x52,
 283         Config2         = 0x53,
 284 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 285
 286         Config3         = 0x54,
 287         Config4         = 0x55,
 288         Config5         = 0x56,
 289         MultiIntr       = 0x5c,
 290         PHYAR           = 0x60,
 291         PHYstatus       = 0x6c,
 292         RxMaxSize       = 0xda,
 293         CPlusCmd        = 0xe0,
 294         IntrMitigate    = 0xe2,
 295
 296 #define RTL_COALESCE_MASK       0x0f
 297 #define RTL_COALESCE_SHIFT      4
 298 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 299 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 300
 301         RxDescAddrLow   = 0xe4,
 302         RxDescAddrHigh  = 0xe8,
 303         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 304
 305 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 306
 307         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 308
 309 #define TxPacketMax     (8064 >> 7)
 310 #define EarlySize       0x27
 311
 312         FuncEvent       = 0xf0,
 313         FuncEventMask   = 0xf4,
 314         FuncPresetState = 0xf8,
 315         IBCR0           = 0xf8,
 316         IBCR2           = 0xf9,
 317         IBIMR0          = 0xfa,
 318         IBISR0          = 0xfb,
 319         FuncForceEvent  = 0xfc,
 320 };
 321
 322 enum rtl8168_8101_registers {
 323         CSIDR                   = 0x64,
 324         CSIAR                   = 0x68,
 325 #define CSIAR_FLAG                      0x80000000
 326 #define CSIAR_WRITE_CMD                 0x80000000
 327 #define CSIAR_BYTE_ENABLE               0x0000f000
 328 #define CSIAR_ADDR_MASK                 0x00000fff
 329         PMCH                    = 0x6f,
 330         EPHYAR                  = 0x80,
 331 #define EPHYAR_FLAG                     0x80000000
 332 #define EPHYAR_WRITE_CMD                0x80000000
 333 #define EPHYAR_REG_MASK                 0x1f
 334 #define EPHYAR_REG_SHIFT                16
 335 #define EPHYAR_DATA_MASK                0xffff
 336         DLLPR                   = 0xd0,
 337 #define PFM_EN                          (1 << 6)
 338 #define TX_10M_PS_EN                    (1 << 7)
 339         DBG_REG                 = 0xd1,
 340 #define FIX_NAK_1                       (1 << 4)
 341 #define FIX_NAK_2                       (1 << 3)
 342         TWSI                    = 0xd2,
 343         MCU                     = 0xd3,
 344 #define NOW_IS_OOB                      (1 << 7)
 345 #define TX_EMPTY                        (1 << 5)
 346 #define RX_EMPTY                        (1 << 4)
 347 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 348 #define EN_NDP                          (1 << 3)
 349 #define EN_OOB_RESET                    (1 << 2)
 350 #define LINK_LIST_RDY                   (1 << 1)
 351         EFUSEAR                 = 0xdc,
 352 #define EFUSEAR_FLAG                    0x80000000
 353 #define EFUSEAR_WRITE_CMD               0x80000000
 354 #define EFUSEAR_READ_CMD                0x00000000
 355 #define EFUSEAR_REG_MASK                0x03ff
 356 #define EFUSEAR_REG_SHIFT               8
 357 #define EFUSEAR_DATA_MASK               0xff
 358         MISC_1                  = 0xf2,
 359 #define PFM_D3COLD_EN                   (1 << 6)
 360 };
 361
 362 enum rtl8168_registers {
 363         LED_FREQ                = 0x1a,
 364         EEE_LED                 = 0x1b,
 365         ERIDR                   = 0x70,
 366         ERIAR                   = 0x74,
 367 #define ERIAR_FLAG                      0x80000000
 368 #define ERIAR_WRITE_CMD                 0x80000000
 369 #define ERIAR_READ_CMD                  0x00000000
 370 #define ERIAR_ADDR_BYTE_ALIGN           4
 371 #define ERIAR_TYPE_SHIFT                16
 372 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 373 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 374 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 375 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 376 #define ERIAR_MASK_SHIFT                12
 377 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 378 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 379 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 380 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 381 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 382         EPHY_RXER_NUM           = 0x7c,
 383         OCPDR                   = 0xb0, /* OCP GPHY access */
 384 #define OCPDR_WRITE_CMD                 0x80000000
 385 #define OCPDR_READ_CMD                  0x00000000
 386 #define OCPDR_REG_MASK                  0x7f
 387 #define OCPDR_GPHY_REG_SHIFT            16
 388 #define OCPDR_DATA_MASK                 0xffff
 389         OCPAR                   = 0xb4,
 390 #define OCPAR_FLAG                      0x80000000
 391 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 392 #define OCPAR_GPHY_READ_CMD             0x0000f060
 393         GPHY_OCP                = 0xb8,
 394         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 395         MISC                    = 0xf0, /* 8168e only. */
 396 #define TXPLA_RST                       (1 << 29)
 397 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 398 #define PWM_EN                          (1 << 22)
 399 #define RXDV_GATED_EN                   (1 << 19)
 400 #define EARLY_TALLY_EN                  (1 << 16)
 401 };
 402
 403 enum rtl_register_content {
 404         /* InterruptStatusBits */
 405         SYSErr          = 0x8000,
 406         PCSTimeout      = 0x4000,
 407         SWInt           = 0x0100,
 408         TxDescUnavail   = 0x0080,
 409         RxFIFOOver      = 0x0040,
 410         LinkChg         = 0x0020,
 411         RxOverflow      = 0x0010,
 412         TxErr           = 0x0008,
 413         TxOK            = 0x0004,
 414         RxErr           = 0x0002,
 415         RxOK            = 0x0001,
 416
 417         /* RxStatusDesc */
 418         RxBOVF  = (1 << 24),
 419         RxFOVF  = (1 << 23),
 420         RxRWT   = (1 << 22),
 421         RxRES   = (1 << 21),
 422         RxRUNT  = (1 << 20),
 423         RxCRC   = (1 << 19),
 424
 425         /* ChipCmdBits */
 426         StopReq         = 0x80,
 427         CmdReset        = 0x10,
 428         CmdRxEnb        = 0x08,
 429         CmdTxEnb        = 0x04,
 430         RxBufEmpty      = 0x01,
 431
 432         /* TXPoll register p.5 */
 433         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 434         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 435         FSWInt          = 0x01,         /* Forced software interrupt */
 436
 437         /* Cfg9346Bits */
 438         Cfg9346_Lock    = 0x00,
 439         Cfg9346_Unlock  = 0xc0,
 440
 441         /* rx_mode_bits */
 442         AcceptErr       = 0x20,
 443         AcceptRunt      = 0x10,
 444         AcceptBroadcast = 0x08,
 445         AcceptMulticast = 0x04,
 446         AcceptMyPhys    = 0x02,
 447         AcceptAllPhys   = 0x01,
 448 #define RX_CONFIG_ACCEPT_MASK           0x3f
 449
 450         /* TxConfigBits */
 451         TxInterFrameGapShift = 24,
 452         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 453
 454         /* Config1 register p.24 */
 455         LEDS1           = (1 << 7),
 456         LEDS0           = (1 << 6),
 457         Speed_down      = (1 << 4),
 458         MEMMAP          = (1 << 3),
 459         IOMAP           = (1 << 2),
 460         VPD             = (1 << 1),
 461         PMEnable        = (1 << 0),     /* Power Management Enable */
 462
 463         /* Config2 register p. 25 */
 464         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 465         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 466         PCI_Clock_66MHz = 0x01,
 467         PCI_Clock_33MHz = 0x00,
 468
 469         /* Config3 register p.25 */
 470         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 471         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 472         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 473         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 474         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 475
 476         /* Config4 register */
 477         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 478
 479         /* Config5 register p.27 */
 480         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 481         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 482         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 483         Spi_en          = (1 << 3),
 484         LanWake         = (1 << 1),     /* LanWake enable/disable */
 485         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 486         ASPM_en         = (1 << 0),     /* ASPM enable */
 487
 488         /* CPlusCmd p.31 */
 489         EnableBist      = (1 << 15),    // 8168 8101
 490         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 491         Normal_mode     = (1 << 13),    // unused
 492         Force_half_dup  = (1 << 12),    // 8168 8101
 493         Force_rxflow_en = (1 << 11),    // 8168 8101
 494         Force_txflow_en = (1 << 10),    // 8168 8101
 495         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 496         ASF             = (1 << 8),     // 8168 8101
 497         PktCntrDisable  = (1 << 7),     // 8168 8101
 498         Mac_dbgo_sel    = 0x001c,       // 8168
 499         RxVlan          = (1 << 6),
 500         RxChkSum        = (1 << 5),
 501         PCIDAC          = (1 << 4),
 502         PCIMulRW        = (1 << 3),
 503 #define INTT_MASK       GENMASK(1, 0)
 504         INTT_0          = 0x0000,       // 8168
 505         INTT_1          = 0x0001,       // 8168
 506         INTT_2          = 0x0002,       // 8168
 507         INTT_3          = 0x0003,       // 8168
 508
 509         /* rtl8169_PHYstatus */
 510         TBI_Enable      = 0x80,
 511         TxFlowCtrl      = 0x40,
 512         RxFlowCtrl      = 0x20,
 513         _1000bpsF       = 0x10,
 514         _100bps         = 0x08,
 515         _10bps          = 0x04,
 516         LinkStatus      = 0x02,
 517         FullDup         = 0x01,
 518
 519         /* _TBICSRBit */
 520         TBILinkOK       = 0x02000000,
 521
 522         /* ResetCounterCommand */
 523         CounterReset    = 0x1,
 524
 525         /* DumpCounterCommand */
 526         CounterDump     = 0x8,
 527
 528         /* magic enable v2 */
 529         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 530 };
 531
 532 enum rtl_desc_bit {
 533         /* First doubleword. */
 534         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 535         RingEnd         = (1 << 30), /* End of descriptor ring */
 536         FirstFrag       = (1 << 29), /* First segment of a packet */
 537         LastFrag        = (1 << 28), /* Final segment of a packet */
 538 };
 539
 540 /* Generic case. */
 541 enum rtl_tx_desc_bit {
 542         /* First doubleword. */
 543         TD_LSO          = (1 << 27),            /* Large Send Offload */
 544 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 545
 546         /* Second doubleword. */
 547         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 548 };
 549
 550 /* 8169, 8168b and 810x except 8102e. */
 551 enum rtl_tx_desc_bit_0 {
 552         /* First doubleword. */
 553 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 554         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 555         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 556         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 557 };
 558
 559 /* 8102e, 8168c and beyond. */
 560 enum rtl_tx_desc_bit_1 {
 561         /* First doubleword. */
 562         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 563         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 564 #define GTTCPHO_SHIFT                   18
 565 #define GTTCPHO_MAX                     0x7fU
 566
 567         /* Second doubleword. */
 568 #define TCPHO_SHIFT                     18
 569 #define TCPHO_MAX                       0x3ffU
 570 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 571         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 572         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 573         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 574         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 575 };
 576
 577 enum rtl_rx_desc_bit {
 578         /* Rx private */
 579         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 580         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 581
 582 #define RxProtoUDP      (PID1)
 583 #define RxProtoTCP      (PID0)
 584 #define RxProtoIP       (PID1 | PID0)
 585 #define RxProtoMask     RxProtoIP
 586
 587         IPFail          = (1 << 16), /* IP checksum failed */
 588         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 589         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 590         RxVlanTag       = (1 << 16), /* VLAN tag available */
 591 };
 592
 593 #define RsvdMask        0x3fffc000
 594 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 595
 596 struct TxDesc {
 597         __le32 opts1;
 598         __le32 opts2;
 599         __le64 addr;
 600 };
 601
 602 struct RxDesc {
 603         __le32 opts1;
 604         __le32 opts2;
 605         __le64 addr;
 606 };
 607
 608 struct ring_info {
 609         struct sk_buff  *skb;
 610         u32             len;
 611         u8              __pad[sizeof(void *) - sizeof(u32)];
 612 };
 613
 614 struct rtl8169_counters {
 615         __le64  tx_packets;
 616         __le64  rx_packets;
 617         __le64  tx_errors;
 618         __le32  rx_errors;
 619         __le16  rx_missed;
 620         __le16  align_errors;
 621         __le32  tx_one_collision;
 622         __le32  tx_multi_collision;
 623         __le64  rx_unicast;
 624         __le64  rx_broadcast;
 625         __le32  rx_multicast;
 626         __le16  tx_aborted;
 627         __le16  tx_underun;
 628 };
 629
 630 struct rtl8169_tc_offsets {
 631         bool    inited;
 632         __le64  tx_errors;
 633         __le32  tx_multi_collision;
 634         __le16  tx_aborted;
 635 };
 636
 637 enum rtl_flag {
 638         RTL_FLAG_TASK_ENABLED = 0,
 639         RTL_FLAG_TASK_SLOW_PENDING,
 640         RTL_FLAG_TASK_RESET_PENDING,
 641         RTL_FLAG_MAX
 642 };
 643
 644 struct rtl8169_stats {
 645         u64                     packets;
 646         u64                     bytes;
 647         struct u64_stats_sync   syncp;
 648 };
 649
 650 struct rtl8169_private {
 651         void __iomem *mmio_addr;        /* memory map physical address */
 652         struct pci_dev *pci_dev;
 653         struct net_device *dev;
 654         struct napi_struct napi;
 655         u32 msg_enable;
 656         u16 mac_version;
 657         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 658         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 659         u32 dirty_tx;
 660         struct rtl8169_stats rx_stats;
 661         struct rtl8169_stats tx_stats;
 662         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 663         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 664         dma_addr_t TxPhyAddr;
 665         dma_addr_t RxPhyAddr;
 666         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 667         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 668         u16 cp_cmd;
 669
 670         u16 event_slow;
 671         const struct rtl_coalesce_info *coalesce_info;
 672         struct clk *clk;
 673
 674         struct mdio_ops {
 675                 void (*write)(struct rtl8169_private *, int, int);
 676                 int (*read)(struct rtl8169_private *, int);
 677         } mdio_ops;
 678
 679         struct jumbo_ops {
 680                 void (*enable)(struct rtl8169_private *);
 681                 void (*disable)(struct rtl8169_private *);
 682         } jumbo_ops;
 683
 684         void (*hw_start)(struct rtl8169_private *tp);
 685         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 686
 687         struct {
 688                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 689                 struct mutex mutex;
 690                 struct work_struct work;
 691         } wk;
 692
 693         unsigned supports_gmii:1;
 694         struct mii_bus *mii_bus;
 695         dma_addr_t counters_phys_addr;
 696         struct rtl8169_counters *counters;
 697         struct rtl8169_tc_offsets tc_offset;
 698         u32 saved_wolopts;
 699
 700         struct rtl_fw {
 701                 const struct firmware *fw;
 702
 703 #define RTL_VER_SIZE            32
 704
 705                 char version[RTL_VER_SIZE];
 706
 707                 struct rtl_fw_phy_action {
 708                         __le32 *code;
 709                         size_t size;
 710                 } phy_action;
 711         } *rtl_fw;
 712 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 713
 714         u32 ocp_base;
 715 };
 716
 717 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 718 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 719 module_param(use_dac, int, 0);
 720 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 721 module_param_named(debug, debug.msg_enable, int, 0);
 722 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 723 MODULE_SOFTDEP("pre: realtek");
 724 MODULE_LICENSE("GPL");
 725 /*(DEBLOBBED)*/
 726
 727 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 728 {
 729         return &tp->pci_dev->dev;
 730 }
 731
 732 static void rtl_lock_work(struct rtl8169_private *tp)
 733 {
 734         mutex_lock(&tp->wk.mutex);
 735 }
 736
 737 static void rtl_unlock_work(struct rtl8169_private *tp)
 738 {
 739         mutex_unlock(&tp->wk.mutex);
 740 }
 741
 742 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 743 {
 744         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 745                                            PCI_EXP_DEVCTL_READRQ, force);
 746 }
 747
 748 struct rtl_cond {
 749         bool (*check)(struct rtl8169_private *);
 750         const char *msg;
 751 };
 752
 753 static void rtl_udelay(unsigned int d)
 754 {
 755         udelay(d);
 756 }
 757
 758 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 759                           void (*delay)(unsigned int), unsigned int d, int n,
 760                           bool high)
 761 {
 762         int i;
 763
 764         for (i = 0; i < n; i++) {
 765                 delay(d);
 766                 if (c->check(tp) == high)
 767                         return true;
 768         }
 769         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 770                   c->msg, !high, n, d);
 771         return false;
 772 }
 773
 774 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 775                                       const struct rtl_cond *c,
 776                                       unsigned int d, int n)
 777 {
 778         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 779 }
 780
 781 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 782                                      const struct rtl_cond *c,
 783                                      unsigned int d, int n)
 784 {
 785         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 786 }
 787
 788 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 789                                       const struct rtl_cond *c,
 790                                       unsigned int d, int n)
 791 {
 792         return rtl_loop_wait(tp, c, msleep, d, n, true);
 793 }
 794
 795 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 796                                      const struct rtl_cond *c,
 797                                      unsigned int d, int n)
 798 {
 799         return rtl_loop_wait(tp, c, msleep, d, n, false);
 800 }
 801
 802 #define DECLARE_RTL_COND(name)                          \
 803 static bool name ## _check(struct rtl8169_private *);   \
 804                                                         \
 805 static const struct rtl_cond name = {                   \
 806         .check  = name ## _check,                       \
 807         .msg    = #name                                 \
 808 };                                                      \
 809                                                         \
 810 static bool name ## _check(struct rtl8169_private *tp)
 811
 812 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 813 {
 814         if (reg & 0xffff0001) {
 815                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 816                 return true;
 817         }
 818         return false;
 819 }
 820
 821 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 822 {
 823         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 824 }
 825
 826 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 827 {
 828         if (rtl_ocp_reg_failure(tp, reg))
 829                 return;
 830
 831         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 832
 833         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 834 }
 835
 836 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 837 {
 838         if (rtl_ocp_reg_failure(tp, reg))
 839                 return 0;
 840
 841         RTL_W32(tp, GPHY_OCP, reg << 15);
 842
 843         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 844                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 845 }
 846
 847 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 848 {
 849         if (rtl_ocp_reg_failure(tp, reg))
 850                 return;
 851
 852         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 853 }
 854
 855 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 856 {
 857         if (rtl_ocp_reg_failure(tp, reg))
 858                 return 0;
 859
 860         RTL_W32(tp, OCPDR, reg << 15);
 861
 862         return RTL_R32(tp, OCPDR);
 863 }
 864
 865 #define OCP_STD_PHY_BASE        0xa400
 866
 867 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 868 {
 869         if (reg == 0x1f) {
 870                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 871                 return;
 872         }
 873
 874         if (tp->ocp_base != OCP_STD_PHY_BASE)
 875                 reg -= 0x10;
 876
 877         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 878 }
 879
 880 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 881 {
 882         if (tp->ocp_base != OCP_STD_PHY_BASE)
 883                 reg -= 0x10;
 884
 885         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 886 }
 887
 888 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 889 {
 890         if (reg == 0x1f) {
 891                 tp->ocp_base = value << 4;
 892                 return;
 893         }
 894
 895         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 896 }
 897
 898 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 899 {
 900         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 901 }
 902
 903 DECLARE_RTL_COND(rtl_phyar_cond)
 904 {
 905         return RTL_R32(tp, PHYAR) & 0x80000000;
 906 }
 907
 908 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 909 {
 910         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 911
 912         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 913         /*
 914          * According to hardware specs a 20us delay is required after write
 915          * complete indication, but before sending next command.
 916          */
 917         udelay(20);
 918 }
 919
 920 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 921 {
 922         int value;
 923
 924         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 925
 926         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 927                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 928
 929         /*
 930          * According to hardware specs a 20us delay is required after read
 931          * complete indication, but before sending next command.
 932          */
 933         udelay(20);
 934
 935         return value;
 936 }
 937
 938 DECLARE_RTL_COND(rtl_ocpar_cond)
 939 {
 940         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 941 }
 942
 943 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 944 {
 945         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 946         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 947         RTL_W32(tp, EPHY_RXER_NUM, 0);
 948
 949         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 950 }
 951
 952 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 953 {
 954         r8168dp_1_mdio_access(tp, reg,
 955                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 956 }
 957
 958 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 959 {
 960         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 961
 962         mdelay(1);
 963         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 964         RTL_W32(tp, EPHY_RXER_NUM, 0);
 965
 966         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 967                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 968 }
 969
 970 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 971
 972 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 973 {
 974         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 975 }
 976
 977 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 978 {
 979         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 980 }
 981
 982 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 983 {
 984         r8168dp_2_mdio_start(tp);
 985
 986         r8169_mdio_write(tp, reg, value);
 987
 988         r8168dp_2_mdio_stop(tp);
 989 }
 990
 991 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 992 {
 993         int value;
 994
 995         /* Work around issue with chip reporting wrong PHY ID */
 996         if (reg == MII_PHYSID2)
 997                 return 0xc912;
 998
 999         r8168dp_2_mdio_start(tp);
1000
1001         value = r8169_mdio_read(tp, reg);
1002
1003         r8168dp_2_mdio_stop(tp);
1004
1005         return value;
1006 }
1007
1008 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1009 {
1010         tp->mdio_ops.write(tp, location, val);
1011 }
1012
1013 static int rtl_readphy(struct rtl8169_private *tp, int location)
1014 {
1015         return tp->mdio_ops.read(tp, location);
1016 }
1017
1018 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1019 {
1020         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1021 }
1022
1023 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1024 {
1025         int val;
1026
1027         val = rtl_readphy(tp, reg_addr);
1028         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1029 }
1030
1031 DECLARE_RTL_COND(rtl_ephyar_cond)
1032 {
1033         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1034 }
1035
1036 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1037 {
1038         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1039                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1040
1041         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1042
1043         udelay(10);
1044 }
1045
1046 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1047 {
1048         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1049
1050         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1051                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1052 }
1053
1054 DECLARE_RTL_COND(rtl_eriar_cond)
1055 {
1056         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1057 }
1058
1059 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1060                           u32 val, int type)
1061 {
1062         BUG_ON((addr & 3) || (mask == 0));
1063         RTL_W32(tp, ERIDR, val);
1064         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1065
1066         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1067 }
1068
1069 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1070 {
1071         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1072
1073         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1074                 RTL_R32(tp, ERIDR) : ~0;
1075 }
1076
1077 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1078                          u32 m, int type)
1079 {
1080         u32 val;
1081
1082         val = rtl_eri_read(tp, addr, type);
1083         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1084 }
1085
1086 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1087 {
1088         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1089         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1090                 RTL_R32(tp, OCPDR) : ~0;
1091 }
1092
1093 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1094 {
1095         return rtl_eri_read(tp, reg, ERIAR_OOB);
1096 }
1097
1098 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1099 {
1100         switch (tp->mac_version) {
1101         case RTL_GIGA_MAC_VER_27:
1102         case RTL_GIGA_MAC_VER_28:
1103         case RTL_GIGA_MAC_VER_31:
1104                 return r8168dp_ocp_read(tp, mask, reg);
1105         case RTL_GIGA_MAC_VER_49:
1106         case RTL_GIGA_MAC_VER_50:
1107         case RTL_GIGA_MAC_VER_51:
1108                 return r8168ep_ocp_read(tp, mask, reg);
1109         default:
1110                 BUG();
1111                 return ~0;
1112         }
1113 }
1114
1115 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1116                               u32 data)
1117 {
1118         RTL_W32(tp, OCPDR, data);
1119         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1120         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1121 }
1122
1123 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1124                               u32 data)
1125 {
1126         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1127                       data, ERIAR_OOB);
1128 }
1129
1130 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1131 {
1132         switch (tp->mac_version) {
1133         case RTL_GIGA_MAC_VER_27:
1134         case RTL_GIGA_MAC_VER_28:
1135         case RTL_GIGA_MAC_VER_31:
1136                 r8168dp_ocp_write(tp, mask, reg, data);
1137                 break;
1138         case RTL_GIGA_MAC_VER_49:
1139         case RTL_GIGA_MAC_VER_50:
1140         case RTL_GIGA_MAC_VER_51:
1141                 r8168ep_ocp_write(tp, mask, reg, data);
1142                 break;
1143         default:
1144                 BUG();
1145                 break;
1146         }
1147 }
1148
1149 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1150 {
1151         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1152
1153         ocp_write(tp, 0x1, 0x30, 0x00000001);
1154 }
1155
1156 #define OOB_CMD_RESET           0x00
1157 #define OOB_CMD_DRIVER_START    0x05
1158 #define OOB_CMD_DRIVER_STOP     0x06
1159
1160 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1161 {
1162         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1163 }
1164
1165 DECLARE_RTL_COND(rtl_ocp_read_cond)
1166 {
1167         u16 reg;
1168
1169         reg = rtl8168_get_ocp_reg(tp);
1170
1171         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1172 }
1173
1174 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1175 {
1176         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1177 }
1178
1179 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1180 {
1181         return RTL_R8(tp, IBISR0) & 0x20;
1182 }
1183
1184 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1185 {
1186         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1187         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1188         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1189         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1190 }
1191
1192 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1193 {
1194         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1195         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1196 }
1197
1198 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1199 {
1200         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1201         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1202         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168_driver_start(struct rtl8169_private *tp)
1206 {
1207         switch (tp->mac_version) {
1208         case RTL_GIGA_MAC_VER_27:
1209         case RTL_GIGA_MAC_VER_28:
1210         case RTL_GIGA_MAC_VER_31:
1211                 rtl8168dp_driver_start(tp);
1212                 break;
1213         case RTL_GIGA_MAC_VER_49:
1214         case RTL_GIGA_MAC_VER_50:
1215         case RTL_GIGA_MAC_VER_51:
1216                 rtl8168ep_driver_start(tp);
1217                 break;
1218         default:
1219                 BUG();
1220                 break;
1221         }
1222 }
1223
1224 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1225 {
1226         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1227         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1228 }
1229
1230 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1231 {
1232         rtl8168ep_stop_cmac(tp);
1233         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1234         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1235         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1236 }
1237
1238 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1239 {
1240         switch (tp->mac_version) {
1241         case RTL_GIGA_MAC_VER_27:
1242         case RTL_GIGA_MAC_VER_28:
1243         case RTL_GIGA_MAC_VER_31:
1244                 rtl8168dp_driver_stop(tp);
1245                 break;
1246         case RTL_GIGA_MAC_VER_49:
1247         case RTL_GIGA_MAC_VER_50:
1248         case RTL_GIGA_MAC_VER_51:
1249                 rtl8168ep_driver_stop(tp);
1250                 break;
1251         default:
1252                 BUG();
1253                 break;
1254         }
1255 }
1256
1257 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1258 {
1259         u16 reg = rtl8168_get_ocp_reg(tp);
1260
1261         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1262 }
1263
1264 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1265 {
1266         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1267 }
1268
1269 static bool r8168_check_dash(struct rtl8169_private *tp)
1270 {
1271         switch (tp->mac_version) {
1272         case RTL_GIGA_MAC_VER_27:
1273         case RTL_GIGA_MAC_VER_28:
1274         case RTL_GIGA_MAC_VER_31:
1275                 return r8168dp_check_dash(tp);
1276         case RTL_GIGA_MAC_VER_49:
1277         case RTL_GIGA_MAC_VER_50:
1278         case RTL_GIGA_MAC_VER_51:
1279                 return r8168ep_check_dash(tp);
1280         default:
1281                 return false;
1282         }
1283 }
1284
1285 struct exgmac_reg {
1286         u16 addr;
1287         u16 mask;
1288         u32 val;
1289 };
1290
1291 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1292                                    const struct exgmac_reg *r, int len)
1293 {
1294         while (len-- > 0) {
1295                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1296                 r++;
1297         }
1298 }
1299
1300 DECLARE_RTL_COND(rtl_efusear_cond)
1301 {
1302         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1303 }
1304
1305 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1306 {
1307         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1308
1309         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1310                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1311 }
1312
1313 static u16 rtl_get_events(struct rtl8169_private *tp)
1314 {
1315         return RTL_R16(tp, IntrStatus);
1316 }
1317
1318 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1319 {
1320         RTL_W16(tp, IntrStatus, bits);
1321         mmiowb();
1322 }
1323
1324 static void rtl_irq_disable(struct rtl8169_private *tp)
1325 {
1326         RTL_W16(tp, IntrMask, 0);
1327         mmiowb();
1328 }
1329
1330 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1331 {
1332         RTL_W16(tp, IntrMask, bits);
1333 }
1334
1335 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1336 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1337 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1338
1339 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1340 {
1341         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1342 }
1343
1344 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1345 {
1346         rtl_irq_disable(tp);
1347         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1348         RTL_R8(tp, ChipCmd);
1349 }
1350
1351 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1352 {
1353         struct net_device *dev = tp->dev;
1354         struct phy_device *phydev = dev->phydev;
1355
1356         if (!netif_running(dev))
1357                 return;
1358
1359         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1360             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1361                 if (phydev->speed == SPEED_1000) {
1362                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1363                                       ERIAR_EXGMAC);
1364                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1365                                       ERIAR_EXGMAC);
1366                 } else if (phydev->speed == SPEED_100) {
1367                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1368                                       ERIAR_EXGMAC);
1369                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1370                                       ERIAR_EXGMAC);
1371                 } else {
1372                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1373                                       ERIAR_EXGMAC);
1374                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1375                                       ERIAR_EXGMAC);
1376                 }
1377                 /* Reset packet filter */
1378                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1379                              ERIAR_EXGMAC);
1380                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1381                              ERIAR_EXGMAC);
1382         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1383                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1384                 if (phydev->speed == SPEED_1000) {
1385                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1386                                       ERIAR_EXGMAC);
1387                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1388                                       ERIAR_EXGMAC);
1389                 } else {
1390                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1391                                       ERIAR_EXGMAC);
1392                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1393                                       ERIAR_EXGMAC);
1394                 }
1395         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1396                 if (phydev->speed == SPEED_10) {
1397                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1398                                       ERIAR_EXGMAC);
1399                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1400                                       ERIAR_EXGMAC);
1401                 } else {
1402                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1403                                       ERIAR_EXGMAC);
1404                 }
1405         }
1406 }
1407
1408 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1409
1410 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1411 {
1412         u8 options;
1413         u32 wolopts = 0;
1414
1415         options = RTL_R8(tp, Config1);
1416         if (!(options & PMEnable))
1417                 return 0;
1418
1419         options = RTL_R8(tp, Config3);
1420         if (options & LinkUp)
1421                 wolopts |= WAKE_PHY;
1422         switch (tp->mac_version) {
1423         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1424         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1425                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1426                         wolopts |= WAKE_MAGIC;
1427                 break;
1428         default:
1429                 if (options & MagicPacket)
1430                         wolopts |= WAKE_MAGIC;
1431                 break;
1432         }
1433
1434         options = RTL_R8(tp, Config5);
1435         if (options & UWF)
1436                 wolopts |= WAKE_UCAST;
1437         if (options & BWF)
1438                 wolopts |= WAKE_BCAST;
1439         if (options & MWF)
1440                 wolopts |= WAKE_MCAST;
1441
1442         return wolopts;
1443 }
1444
1445 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1446 {
1447         struct rtl8169_private *tp = netdev_priv(dev);
1448
1449         rtl_lock_work(tp);
1450         wol->supported = WAKE_ANY;
1451         wol->wolopts = tp->saved_wolopts;
1452         rtl_unlock_work(tp);
1453 }
1454
1455 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1456 {
1457         unsigned int i, tmp;
1458         static const struct {
1459                 u32 opt;
1460                 u16 reg;
1461                 u8  mask;
1462         } cfg[] = {
1463                 { WAKE_PHY,   Config3, LinkUp },
1464                 { WAKE_UCAST, Config5, UWF },
1465                 { WAKE_BCAST, Config5, BWF },
1466                 { WAKE_MCAST, Config5, MWF },
1467                 { WAKE_ANY,   Config5, LanWake },
1468                 { WAKE_MAGIC, Config3, MagicPacket }
1469         };
1470         u8 options;
1471
1472         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1473
1474         switch (tp->mac_version) {
1475         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1476         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1477                 tmp = ARRAY_SIZE(cfg) - 1;
1478                 if (wolopts & WAKE_MAGIC)
1479                         rtl_w0w1_eri(tp,
1480                                      0x0dc,
1481                                      ERIAR_MASK_0100,
1482                                      MagicPacket_v2,
1483                                      0x0000,
1484                                      ERIAR_EXGMAC);
1485                 else
1486                         rtl_w0w1_eri(tp,
1487                                      0x0dc,
1488                                      ERIAR_MASK_0100,
1489                                      0x0000,
1490                                      MagicPacket_v2,
1491                                      ERIAR_EXGMAC);
1492                 break;
1493         default:
1494                 tmp = ARRAY_SIZE(cfg);
1495                 break;
1496         }
1497
1498         for (i = 0; i < tmp; i++) {
1499                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1500                 if (wolopts & cfg[i].opt)
1501                         options |= cfg[i].mask;
1502                 RTL_W8(tp, cfg[i].reg, options);
1503         }
1504
1505         switch (tp->mac_version) {
1506         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1507                 options = RTL_R8(tp, Config1) & ~PMEnable;
1508                 if (wolopts)
1509                         options |= PMEnable;
1510                 RTL_W8(tp, Config1, options);
1511                 break;
1512         default:
1513                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1514                 if (wolopts)
1515                         options |= PME_SIGNAL;
1516                 RTL_W8(tp, Config2, options);
1517                 break;
1518         }
1519
1520         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1521
1522         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1523 }
1524
1525 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1526 {
1527         struct rtl8169_private *tp = netdev_priv(dev);
1528         struct device *d = tp_to_dev(tp);
1529
1530         if (wol->wolopts & ~WAKE_ANY)
1531                 return -EINVAL;
1532
1533         pm_runtime_get_noresume(d);
1534
1535         rtl_lock_work(tp);
1536
1537         tp->saved_wolopts = wol->wolopts;
1538
1539         if (pm_runtime_active(d))
1540                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1541
1542         rtl_unlock_work(tp);
1543
1544         pm_runtime_put_noidle(d);
1545
1546         return 0;
1547 }
1548
1549 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1550 {
1551         return rtl_chip_infos[tp->mac_version].fw_name;
1552 }
1553
1554 static void rtl8169_get_drvinfo(struct net_device *dev,
1555                                 struct ethtool_drvinfo *info)
1556 {
1557         struct rtl8169_private *tp = netdev_priv(dev);
1558         struct rtl_fw *rtl_fw = tp->rtl_fw;
1559
1560         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1561         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1562         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1563         if (!IS_ERR_OR_NULL(rtl_fw))
1564                 strlcpy(info->fw_version, rtl_fw->version,
1565                         sizeof(info->fw_version));
1566 }
1567
1568 static int rtl8169_get_regs_len(struct net_device *dev)
1569 {
1570         return R8169_REGS_SIZE;
1571 }
1572
1573 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1574         netdev_features_t features)
1575 {
1576         struct rtl8169_private *tp = netdev_priv(dev);
1577
1578         if (dev->mtu > TD_MSS_MAX)
1579                 features &= ~NETIF_F_ALL_TSO;
1580
1581         if (dev->mtu > JUMBO_1K &&
1582             tp->mac_version > RTL_GIGA_MAC_VER_06)
1583                 features &= ~NETIF_F_IP_CSUM;
1584
1585         return features;
1586 }
1587
1588 static int rtl8169_set_features(struct net_device *dev,
1589                                 netdev_features_t features)
1590 {
1591         struct rtl8169_private *tp = netdev_priv(dev);
1592         u32 rx_config;
1593
1594         rtl_lock_work(tp);
1595
1596         rx_config = RTL_R32(tp, RxConfig);
1597         if (features & NETIF_F_RXALL)
1598                 rx_config |= (AcceptErr | AcceptRunt);
1599         else
1600                 rx_config &= ~(AcceptErr | AcceptRunt);
1601
1602         RTL_W32(tp, RxConfig, rx_config);
1603
1604         if (features & NETIF_F_RXCSUM)
1605                 tp->cp_cmd |= RxChkSum;
1606         else
1607                 tp->cp_cmd &= ~RxChkSum;
1608
1609         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1610                 tp->cp_cmd |= RxVlan;
1611         else
1612                 tp->cp_cmd &= ~RxVlan;
1613
1614         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1615         RTL_R16(tp, CPlusCmd);
1616
1617         rtl_unlock_work(tp);
1618
1619         return 0;
1620 }
1621
1622 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1623 {
1624         return (skb_vlan_tag_present(skb)) ?
1625                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1626 }
1627
1628 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1629 {
1630         u32 opts2 = le32_to_cpu(desc->opts2);
1631
1632         if (opts2 & RxVlanTag)
1633                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1634 }
1635
1636 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1637                              void *p)
1638 {
1639         struct rtl8169_private *tp = netdev_priv(dev);
1640         u32 __iomem *data = tp->mmio_addr;
1641         u32 *dw = p;
1642         int i;
1643
1644         rtl_lock_work(tp);
1645         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1646                 memcpy_fromio(dw++, data++, 4);
1647         rtl_unlock_work(tp);
1648 }
1649
1650 static u32 rtl8169_get_msglevel(struct net_device *dev)
1651 {
1652         struct rtl8169_private *tp = netdev_priv(dev);
1653
1654         return tp->msg_enable;
1655 }
1656
1657 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1658 {
1659         struct rtl8169_private *tp = netdev_priv(dev);
1660
1661         tp->msg_enable = value;
1662 }
1663
1664 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1665         "tx_packets",
1666         "rx_packets",
1667         "tx_errors",
1668         "rx_errors",
1669         "rx_missed",
1670         "align_errors",
1671         "tx_single_collisions",
1672         "tx_multi_collisions",
1673         "unicast",
1674         "broadcast",
1675         "multicast",
1676         "tx_aborted",
1677         "tx_underrun",
1678 };
1679
1680 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1681 {
1682         switch (sset) {
1683         case ETH_SS_STATS:
1684                 return ARRAY_SIZE(rtl8169_gstrings);
1685         default:
1686                 return -EOPNOTSUPP;
1687         }
1688 }
1689
1690 DECLARE_RTL_COND(rtl_counters_cond)
1691 {
1692         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1693 }
1694
1695 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1696 {
1697         dma_addr_t paddr = tp->counters_phys_addr;
1698         u32 cmd;
1699
1700         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1701         RTL_R32(tp, CounterAddrHigh);
1702         cmd = (u64)paddr & DMA_BIT_MASK(32);
1703         RTL_W32(tp, CounterAddrLow, cmd);
1704         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1705
1706         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1707 }
1708
1709 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1710 {
1711         /*
1712          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1713          * tally counters.
1714          */
1715         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1716                 return true;
1717
1718         return rtl8169_do_counters(tp, CounterReset);
1719 }
1720
1721 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1722 {
1723         u8 val = RTL_R8(tp, ChipCmd);
1724
1725         /*
1726          * Some chips are unable to dump tally counters when the receiver
1727          * is disabled. If 0xff chip may be in a PCI power-save state.
1728          */
1729         if (!(val & CmdRxEnb) || val == 0xff)
1730                 return true;
1731
1732         return rtl8169_do_counters(tp, CounterDump);
1733 }
1734
1735 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1736 {
1737         struct rtl8169_counters *counters = tp->counters;
1738         bool ret = false;
1739
1740         /*
1741          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1742          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1743          * reset by a power cycle, while the counter values collected by the
1744          * driver are reset at every driver unload/load cycle.
1745          *
1746          * To make sure the HW values returned by @get_stats64 match the SW
1747          * values, we collect the initial values at first open(*) and use them
1748          * as offsets to normalize the values returned by @get_stats64.
1749          *
1750          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1751          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1752          * set at open time by rtl_hw_start.
1753          */
1754
1755         if (tp->tc_offset.inited)
1756                 return true;
1757
1758         /* If both, reset and update fail, propagate to caller. */
1759         if (rtl8169_reset_counters(tp))
1760                 ret = true;
1761
1762         if (rtl8169_update_counters(tp))
1763                 ret = true;
1764
1765         tp->tc_offset.tx_errors = counters->tx_errors;
1766         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1767         tp->tc_offset.tx_aborted = counters->tx_aborted;
1768         tp->tc_offset.inited = true;
1769
1770         return ret;
1771 }
1772
1773 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1774                                       struct ethtool_stats *stats, u64 *data)
1775 {
1776         struct rtl8169_private *tp = netdev_priv(dev);
1777         struct device *d = tp_to_dev(tp);
1778         struct rtl8169_counters *counters = tp->counters;
1779
1780         ASSERT_RTNL();
1781
1782         pm_runtime_get_noresume(d);
1783
1784         if (pm_runtime_active(d))
1785                 rtl8169_update_counters(tp);
1786
1787         pm_runtime_put_noidle(d);
1788
1789         data[0] = le64_to_cpu(counters->tx_packets);
1790         data[1] = le64_to_cpu(counters->rx_packets);
1791         data[2] = le64_to_cpu(counters->tx_errors);
1792         data[3] = le32_to_cpu(counters->rx_errors);
1793         data[4] = le16_to_cpu(counters->rx_missed);
1794         data[5] = le16_to_cpu(counters->align_errors);
1795         data[6] = le32_to_cpu(counters->tx_one_collision);
1796         data[7] = le32_to_cpu(counters->tx_multi_collision);
1797         data[8] = le64_to_cpu(counters->rx_unicast);
1798         data[9] = le64_to_cpu(counters->rx_broadcast);
1799         data[10] = le32_to_cpu(counters->rx_multicast);
1800         data[11] = le16_to_cpu(counters->tx_aborted);
1801         data[12] = le16_to_cpu(counters->tx_underun);
1802 }
1803
1804 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1805 {
1806         switch(stringset) {
1807         case ETH_SS_STATS:
1808                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1809                 break;
1810         }
1811 }
1812
1813 /*
1814  * Interrupt coalescing
1815  *
1816  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1817  * >     8169, 8168 and 810x line of chipsets
1818  *
1819  * 8169, 8168, and 8136(810x) serial chipsets support it.
1820  *
1821  * > 2 - the Tx timer unit at gigabit speed
1822  *
1823  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1824  * (0xe0) bit 1 and bit 0.
1825  *
1826  * For 8169
1827  * bit[1:0] \ speed        1000M           100M            10M
1828  * 0 0                     320ns           2.56us          40.96us
1829  * 0 1                     2.56us          20.48us         327.7us
1830  * 1 0                     5.12us          40.96us         655.4us
1831  * 1 1                     10.24us         81.92us         1.31ms
1832  *
1833  * For the other
1834  * bit[1:0] \ speed        1000M           100M            10M
1835  * 0 0                     5us             2.56us          40.96us
1836  * 0 1                     40us            20.48us         327.7us
1837  * 1 0                     80us            40.96us         655.4us
1838  * 1 1                     160us           81.92us         1.31ms
1839  */
1840
1841 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1842 struct rtl_coalesce_scale {
1843         /* Rx / Tx */
1844         u32 nsecs[2];
1845 };
1846
1847 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1848 struct rtl_coalesce_info {
1849         u32 speed;
1850         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1851 };
1852
1853 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1854 #define rxtx_x1822(r, t) {              \
1855         {{(r),          (t)}},          \
1856         {{(r)*8,        (t)*8}},        \
1857         {{(r)*8*2,      (t)*8*2}},      \
1858         {{(r)*8*2*2,    (t)*8*2*2}},    \
1859 }
1860 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1861         /* speed        delays:     rx00   tx00 */
1862         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1863         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1864         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1865         { 0 },
1866 };
1867
1868 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1869         /* speed        delays:     rx00   tx00 */
1870         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1871         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1872         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1873         { 0 },
1874 };
1875 #undef rxtx_x1822
1876
1877 /* get rx/tx scale vector corresponding to current speed */
1878 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1879 {
1880         struct rtl8169_private *tp = netdev_priv(dev);
1881         struct ethtool_link_ksettings ecmd;
1882         const struct rtl_coalesce_info *ci;
1883         int rc;
1884
1885         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1886         if (rc < 0)
1887                 return ERR_PTR(rc);
1888
1889         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1890                 if (ecmd.base.speed == ci->speed) {
1891                         return ci;
1892                 }
1893         }
1894
1895         return ERR_PTR(-ELNRNG);
1896 }
1897
1898 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         const struct rtl_coalesce_info *ci;
1902         const struct rtl_coalesce_scale *scale;
1903         struct {
1904                 u32 *max_frames;
1905                 u32 *usecs;
1906         } coal_settings [] = {
1907                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1908                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1909         }, *p = coal_settings;
1910         int i;
1911         u16 w;
1912
1913         memset(ec, 0, sizeof(*ec));
1914
1915         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1916         ci = rtl_coalesce_info(dev);
1917         if (IS_ERR(ci))
1918                 return PTR_ERR(ci);
1919
1920         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1921
1922         /* read IntrMitigate and adjust according to scale */
1923         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1924                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1925                 w >>= RTL_COALESCE_SHIFT;
1926                 *p->usecs = w & RTL_COALESCE_MASK;
1927         }
1928
1929         for (i = 0; i < 2; i++) {
1930                 p = coal_settings + i;
1931                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1932
1933                 /*
1934                  * ethtool_coalesce says it is illegal to set both usecs and
1935                  * max_frames to 0.
1936                  */
1937                 if (!*p->usecs && !*p->max_frames)
1938                         *p->max_frames = 1;
1939         }
1940
1941         return 0;
1942 }
1943
1944 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1945 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1946                         struct net_device *dev, u32 nsec, u16 *cp01)
1947 {
1948         const struct rtl_coalesce_info *ci;
1949         u16 i;
1950
1951         ci = rtl_coalesce_info(dev);
1952         if (IS_ERR(ci))
1953                 return ERR_CAST(ci);
1954
1955         for (i = 0; i < 4; i++) {
1956                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1957                                         ci->scalev[i].nsecs[1]);
1958                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1959                         *cp01 = i;
1960                         return &ci->scalev[i];
1961                 }
1962         }
1963
1964         return ERR_PTR(-EINVAL);
1965 }
1966
1967 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1968 {
1969         struct rtl8169_private *tp = netdev_priv(dev);
1970         const struct rtl_coalesce_scale *scale;
1971         struct {
1972                 u32 frames;
1973                 u32 usecs;
1974         } coal_settings [] = {
1975                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1976                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1977         }, *p = coal_settings;
1978         u16 w = 0, cp01;
1979         int i;
1980
1981         scale = rtl_coalesce_choose_scale(dev,
1982                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1983         if (IS_ERR(scale))
1984                 return PTR_ERR(scale);
1985
1986         for (i = 0; i < 2; i++, p++) {
1987                 u32 units;
1988
1989                 /*
1990                  * accept max_frames=1 we returned in rtl_get_coalesce.
1991                  * accept it not only when usecs=0 because of e.g. the following scenario:
1992                  *
1993                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1994                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1995                  * - then user does `ethtool -C eth0 rx-usecs 100`
1996                  *
1997                  * since ethtool sends to kernel whole ethtool_coalesce
1998                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1999                  * we'll reject it below in `frames % 4 != 0`.
2000                  */
2001                 if (p->frames == 1) {
2002                         p->frames = 0;
2003                 }
2004
2005                 units = p->usecs * 1000 / scale->nsecs[i];
2006                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2007                         return -EINVAL;
2008
2009                 w <<= RTL_COALESCE_SHIFT;
2010                 w |= units;
2011                 w <<= RTL_COALESCE_SHIFT;
2012                 w |= p->frames >> 2;
2013         }
2014
2015         rtl_lock_work(tp);
2016
2017         RTL_W16(tp, IntrMitigate, swab16(w));
2018
2019         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2020         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2021         RTL_R16(tp, CPlusCmd);
2022
2023         rtl_unlock_work(tp);
2024
2025         return 0;
2026 }
2027
2028 static const struct ethtool_ops rtl8169_ethtool_ops = {
2029         .get_drvinfo            = rtl8169_get_drvinfo,
2030         .get_regs_len           = rtl8169_get_regs_len,
2031         .get_link               = ethtool_op_get_link,
2032         .get_coalesce           = rtl_get_coalesce,
2033         .set_coalesce           = rtl_set_coalesce,
2034         .get_msglevel           = rtl8169_get_msglevel,
2035         .set_msglevel           = rtl8169_set_msglevel,
2036         .get_regs               = rtl8169_get_regs,
2037         .get_wol                = rtl8169_get_wol,
2038         .set_wol                = rtl8169_set_wol,
2039         .get_strings            = rtl8169_get_strings,
2040         .get_sset_count         = rtl8169_get_sset_count,
2041         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2042         .get_ts_info            = ethtool_op_get_ts_info,
2043         .nway_reset             = phy_ethtool_nway_reset,
2044         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2045         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2046 };
2047
2048 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2049                                     u8 default_version)
2050 {
2051         /*
2052          * The driver currently handles the 8168Bf and the 8168Be identically
2053          * but they can be identified more specifically through the test below
2054          * if needed:
2055          *
2056          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2057          *
2058          * Same thing for the 8101Eb and the 8101Ec:
2059          *
2060          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2061          */
2062         static const struct rtl_mac_info {
2063                 u32 mask;
2064                 u32 val;
2065                 int mac_version;
2066         } mac_info[] = {
2067                 /* 8168EP family. */
2068                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2069                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2070                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2071
2072                 /* 8168H family. */
2073                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2074                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2075
2076                 /* 8168G family. */
2077                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2078                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2079                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2080                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2081
2082                 /* 8168F family. */
2083                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2084                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2085                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2086
2087                 /* 8168E family. */
2088                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2089                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2090                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2091
2092                 /* 8168D family. */
2093                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2094                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2095
2096                 /* 8168DP family. */
2097                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2098                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2099                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2100
2101                 /* 8168C family. */
2102                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2103                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2104                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2105                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2106                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2107                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2108                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2109
2110                 /* 8168B family. */
2111                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2112                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2113                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2114
2115                 /* 8101 family. */
2116                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2117                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2118                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2119                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2120                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2121                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2122                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2123                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2124                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2125                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2126                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2127                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2128                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2129                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2130                 /* FIXME: where did these entries come from ? -- FR */
2131                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2132                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2133
2134                 /* 8110 family. */
2135                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2136                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2137                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2138                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2139                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2140                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2141
2142                 /* Catch-all */
2143                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2144         };
2145         const struct rtl_mac_info *p = mac_info;
2146         u32 reg;
2147
2148         reg = RTL_R32(tp, TxConfig);
2149         while ((reg & p->mask) != p->val)
2150                 p++;
2151         tp->mac_version = p->mac_version;
2152
2153         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2154                 dev_notice(tp_to_dev(tp),
2155                            "unknown MAC, using family default\n");
2156                 tp->mac_version = default_version;
2157         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2158                 tp->mac_version = tp->supports_gmii ?
2159                                   RTL_GIGA_MAC_VER_42 :
2160                                   RTL_GIGA_MAC_VER_43;
2161         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2162                 tp->mac_version = tp->supports_gmii ?
2163                                   RTL_GIGA_MAC_VER_45 :
2164                                   RTL_GIGA_MAC_VER_47;
2165         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2166                 tp->mac_version = tp->supports_gmii ?
2167                                   RTL_GIGA_MAC_VER_46 :
2168                                   RTL_GIGA_MAC_VER_48;
2169         }
2170 }
2171
2172 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2173 {
2174         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2175 }
2176
2177 struct phy_reg {
2178         u16 reg;
2179         u16 val;
2180 };
2181
2182 static void rtl_writephy_batch(struct rtl8169_private *tp,
2183                                const struct phy_reg *regs, int len)
2184 {
2185         while (len-- > 0) {
2186                 rtl_writephy(tp, regs->reg, regs->val);
2187                 regs++;
2188         }
2189 }
2190
2191 #define PHY_READ                0x00000000
2192 #define PHY_DATA_OR             0x10000000
2193 #define PHY_DATA_AND            0x20000000
2194 #define PHY_BJMPN               0x30000000
2195 #define PHY_MDIO_CHG            0x40000000
2196 #define PHY_CLEAR_READCOUNT     0x70000000
2197 #define PHY_WRITE               0x80000000
2198 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2199 #define PHY_COMP_EQ_SKIPN       0xa0000000
2200 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2201 #define PHY_WRITE_PREVIOUS      0xc0000000
2202 #define PHY_SKIPN               0xd0000000
2203 #define PHY_DELAY_MS            0xe0000000
2204
2205 struct fw_info {
2206         u32     magic;
2207         char    version[RTL_VER_SIZE];
2208         __le32  fw_start;
2209         __le32  fw_len;
2210         u8      chksum;
2211 } __packed;
2212
2213 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2214
2215 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2216 {
2217         const struct firmware *fw = rtl_fw->fw;
2218         struct fw_info *fw_info = (struct fw_info *)fw->data;
2219         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2220         char *version = rtl_fw->version;
2221         bool rc = false;
2222
2223         if (fw->size < FW_OPCODE_SIZE)
2224                 goto out;
2225
2226         if (!fw_info->magic) {
2227                 size_t i, size, start;
2228                 u8 checksum = 0;
2229
2230                 if (fw->size < sizeof(*fw_info))
2231                         goto out;
2232
2233                 for (i = 0; i < fw->size; i++)
2234                         checksum += fw->data[i];
2235                 if (checksum != 0)
2236                         goto out;
2237
2238                 start = le32_to_cpu(fw_info->fw_start);
2239                 if (start > fw->size)
2240                         goto out;
2241
2242                 size = le32_to_cpu(fw_info->fw_len);
2243                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2244                         goto out;
2245
2246                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2247
2248                 pa->code = (__le32 *)(fw->data + start);
2249                 pa->size = size;
2250         } else {
2251                 if (fw->size % FW_OPCODE_SIZE)
2252                         goto out;
2253
2254                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2255
2256                 pa->code = (__le32 *)fw->data;
2257                 pa->size = fw->size / FW_OPCODE_SIZE;
2258         }
2259         version[RTL_VER_SIZE - 1] = 0;
2260
2261         rc = true;
2262 out:
2263         return rc;
2264 }
2265
2266 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2267                            struct rtl_fw_phy_action *pa)
2268 {
2269         bool rc = false;
2270         size_t index;
2271
2272         for (index = 0; index < pa->size; index++) {
2273                 u32 action = le32_to_cpu(pa->code[index]);
2274                 u32 regno = (action & 0x0fff0000) >> 16;
2275
2276                 switch(action & 0xf0000000) {
2277                 case PHY_READ:
2278                 case PHY_DATA_OR:
2279                 case PHY_DATA_AND:
2280                 case PHY_MDIO_CHG:
2281                 case PHY_CLEAR_READCOUNT:
2282                 case PHY_WRITE:
2283                 case PHY_WRITE_PREVIOUS:
2284                 case PHY_DELAY_MS:
2285                         break;
2286
2287                 case PHY_BJMPN:
2288                         if (regno > index) {
2289                                 netif_err(tp, ifup, tp->dev,
2290                                           "Out of range of firmware\n");
2291                                 goto out;
2292                         }
2293                         break;
2294                 case PHY_READCOUNT_EQ_SKIP:
2295                         if (index + 2 >= pa->size) {
2296                                 netif_err(tp, ifup, tp->dev,
2297                                           "Out of range of firmware\n");
2298                                 goto out;
2299                         }
2300                         break;
2301                 case PHY_COMP_EQ_SKIPN:
2302                 case PHY_COMP_NEQ_SKIPN:
2303                 case PHY_SKIPN:
2304                         if (index + 1 + regno >= pa->size) {
2305                                 netif_err(tp, ifup, tp->dev,
2306                                           "Out of range of firmware\n");
2307                                 goto out;
2308                         }
2309                         break;
2310
2311                 default:
2312                         netif_err(tp, ifup, tp->dev,
2313                                   "Invalid action 0x%08x\n", action);
2314                         goto out;
2315                 }
2316         }
2317         rc = true;
2318 out:
2319         return rc;
2320 }
2321
2322 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2323 {
2324         struct net_device *dev = tp->dev;
2325         int rc = -EINVAL;
2326
2327         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2328                 netif_err(tp, ifup, dev, "invalid firmware\n");
2329                 goto out;
2330         }
2331
2332         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2333                 rc = 0;
2334 out:
2335         return rc;
2336 }
2337
2338 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2339 {
2340         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2341         struct mdio_ops org, *ops = &tp->mdio_ops;
2342         u32 predata, count;
2343         size_t index;
2344
2345         predata = count = 0;
2346         org.write = ops->write;
2347         org.read = ops->read;
2348
2349         for (index = 0; index < pa->size; ) {
2350                 u32 action = le32_to_cpu(pa->code[index]);
2351                 u32 data = action & 0x0000ffff;
2352                 u32 regno = (action & 0x0fff0000) >> 16;
2353
2354                 if (!action)
2355                         break;
2356
2357                 switch(action & 0xf0000000) {
2358                 case PHY_READ:
2359                         predata = rtl_readphy(tp, regno);
2360                         count++;
2361                         index++;
2362                         break;
2363                 case PHY_DATA_OR:
2364                         predata |= data;
2365                         index++;
2366                         break;
2367                 case PHY_DATA_AND:
2368                         predata &= data;
2369                         index++;
2370                         break;
2371                 case PHY_BJMPN:
2372                         index -= regno;
2373                         break;
2374                 case PHY_MDIO_CHG:
2375                         if (data == 0) {
2376                                 ops->write = org.write;
2377                                 ops->read = org.read;
2378                         } else if (data == 1) {
2379                                 ops->write = mac_mcu_write;
2380                                 ops->read = mac_mcu_read;
2381                         }
2382
2383                         index++;
2384                         break;
2385                 case PHY_CLEAR_READCOUNT:
2386                         count = 0;
2387                         index++;
2388                         break;
2389                 case PHY_WRITE:
2390                         rtl_writephy(tp, regno, data);
2391                         index++;
2392                         break;
2393                 case PHY_READCOUNT_EQ_SKIP:
2394                         index += (count == data) ? 2 : 1;
2395                         break;
2396                 case PHY_COMP_EQ_SKIPN:
2397                         if (predata == data)
2398                                 index += regno;
2399                         index++;
2400                         break;
2401                 case PHY_COMP_NEQ_SKIPN:
2402                         if (predata != data)
2403                                 index += regno;
2404                         index++;
2405                         break;
2406                 case PHY_WRITE_PREVIOUS:
2407                         rtl_writephy(tp, regno, predata);
2408                         index++;
2409                         break;
2410                 case PHY_SKIPN:
2411                         index += regno + 1;
2412                         break;
2413                 case PHY_DELAY_MS:
2414                         mdelay(data);
2415                         index++;
2416                         break;
2417
2418                 default:
2419                         BUG();
2420                 }
2421         }
2422
2423         ops->write = org.write;
2424         ops->read = org.read;
2425 }
2426
2427 static void rtl_release_firmware(struct rtl8169_private *tp)
2428 {
2429         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2430                 release_firmware(tp->rtl_fw->fw);
2431                 kfree(tp->rtl_fw);
2432         }
2433         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2434 }
2435
2436 static void rtl_apply_firmware(struct rtl8169_private *tp)
2437 {
2438         struct rtl_fw *rtl_fw = tp->rtl_fw;
2439
2440         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2441         if (!IS_ERR_OR_NULL(rtl_fw))
2442                 rtl_phy_write_fw(tp, rtl_fw);
2443 }
2444
2445 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2446 {
2447         if (rtl_readphy(tp, reg) != val)
2448                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2449         else
2450                 rtl_apply_firmware(tp);
2451 }
2452
2453 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2454 {
2455         static const struct phy_reg phy_reg_init[] = {
2456                 { 0x1f, 0x0001 },
2457                 { 0x06, 0x006e },
2458                 { 0x08, 0x0708 },
2459                 { 0x15, 0x4000 },
2460                 { 0x18, 0x65c7 },
2461
2462                 { 0x1f, 0x0001 },
2463                 { 0x03, 0x00a1 },
2464                 { 0x02, 0x0008 },
2465                 { 0x01, 0x0120 },
2466                 { 0x00, 0x1000 },
2467                 { 0x04, 0x0800 },
2468                 { 0x04, 0x0000 },
2469
2470                 { 0x03, 0xff41 },
2471                 { 0x02, 0xdf60 },
2472                 { 0x01, 0x0140 },
2473                 { 0x00, 0x0077 },
2474                 { 0x04, 0x7800 },
2475                 { 0x04, 0x7000 },
2476
2477                 { 0x03, 0x802f },
2478                 { 0x02, 0x4f02 },
2479                 { 0x01, 0x0409 },
2480                 { 0x00, 0xf0f9 },
2481                 { 0x04, 0x9800 },
2482                 { 0x04, 0x9000 },
2483
2484                 { 0x03, 0xdf01 },
2485                 { 0x02, 0xdf20 },
2486                 { 0x01, 0xff95 },
2487                 { 0x00, 0xba00 },
2488                 { 0x04, 0xa800 },
2489                 { 0x04, 0xa000 },
2490
2491                 { 0x03, 0xff41 },
2492                 { 0x02, 0xdf20 },
2493                 { 0x01, 0x0140 },
2494                 { 0x00, 0x00bb },
2495                 { 0x04, 0xb800 },
2496                 { 0x04, 0xb000 },
2497
2498                 { 0x03, 0xdf41 },
2499                 { 0x02, 0xdc60 },
2500                 { 0x01, 0x6340 },
2501                 { 0x00, 0x007d },
2502                 { 0x04, 0xd800 },
2503                 { 0x04, 0xd000 },
2504
2505                 { 0x03, 0xdf01 },
2506                 { 0x02, 0xdf20 },
2507                 { 0x01, 0x100a },
2508                 { 0x00, 0xa0ff },
2509                 { 0x04, 0xf800 },
2510                 { 0x04, 0xf000 },
2511
2512                 { 0x1f, 0x0000 },
2513                 { 0x0b, 0x0000 },
2514                 { 0x00, 0x9200 }
2515         };
2516
2517         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2518 }
2519
2520 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2521 {
2522         static const struct phy_reg phy_reg_init[] = {
2523                 { 0x1f, 0x0002 },
2524                 { 0x01, 0x90d0 },
2525                 { 0x1f, 0x0000 }
2526         };
2527
2528         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2529 }
2530
2531 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2532 {
2533         struct pci_dev *pdev = tp->pci_dev;
2534
2535         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2536             (pdev->subsystem_device != 0xe000))
2537                 return;
2538
2539         rtl_writephy(tp, 0x1f, 0x0001);
2540         rtl_writephy(tp, 0x10, 0xf01b);
2541         rtl_writephy(tp, 0x1f, 0x0000);
2542 }
2543
2544 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2545 {
2546         static const struct phy_reg phy_reg_init[] = {
2547                 { 0x1f, 0x0001 },
2548                 { 0x04, 0x0000 },
2549                 { 0x03, 0x00a1 },
2550                 { 0x02, 0x0008 },
2551                 { 0x01, 0x0120 },
2552                 { 0x00, 0x1000 },
2553                 { 0x04, 0x0800 },
2554                 { 0x04, 0x9000 },
2555                 { 0x03, 0x802f },
2556                 { 0x02, 0x4f02 },
2557                 { 0x01, 0x0409 },
2558                 { 0x00, 0xf099 },
2559                 { 0x04, 0x9800 },
2560                 { 0x04, 0xa000 },
2561                 { 0x03, 0xdf01 },
2562                 { 0x02, 0xdf20 },
2563                 { 0x01, 0xff95 },
2564                 { 0x00, 0xba00 },
2565                 { 0x04, 0xa800 },
2566                 { 0x04, 0xf000 },
2567                 { 0x03, 0xdf01 },
2568                 { 0x02, 0xdf20 },
2569                 { 0x01, 0x101a },
2570                 { 0x00, 0xa0ff },
2571                 { 0x04, 0xf800 },
2572                 { 0x04, 0x0000 },
2573                 { 0x1f, 0x0000 },
2574
2575                 { 0x1f, 0x0001 },
2576                 { 0x10, 0xf41b },
2577                 { 0x14, 0xfb54 },
2578                 { 0x18, 0xf5c7 },
2579                 { 0x1f, 0x0000 },
2580
2581                 { 0x1f, 0x0001 },
2582                 { 0x17, 0x0cc0 },
2583                 { 0x1f, 0x0000 }
2584         };
2585
2586         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2587
2588         rtl8169scd_hw_phy_config_quirk(tp);
2589 }
2590
2591 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2592 {
2593         static const struct phy_reg phy_reg_init[] = {
2594                 { 0x1f, 0x0001 },
2595                 { 0x04, 0x0000 },
2596                 { 0x03, 0x00a1 },
2597                 { 0x02, 0x0008 },
2598                 { 0x01, 0x0120 },
2599                 { 0x00, 0x1000 },
2600                 { 0x04, 0x0800 },
2601                 { 0x04, 0x9000 },
2602                 { 0x03, 0x802f },
2603                 { 0x02, 0x4f02 },
2604                 { 0x01, 0x0409 },
2605                 { 0x00, 0xf099 },
2606                 { 0x04, 0x9800 },
2607                 { 0x04, 0xa000 },
2608                 { 0x03, 0xdf01 },
2609                 { 0x02, 0xdf20 },
2610                 { 0x01, 0xff95 },
2611                 { 0x00, 0xba00 },
2612                 { 0x04, 0xa800 },
2613                 { 0x04, 0xf000 },
2614                 { 0x03, 0xdf01 },
2615                 { 0x02, 0xdf20 },
2616                 { 0x01, 0x101a },
2617                 { 0x00, 0xa0ff },
2618                 { 0x04, 0xf800 },
2619                 { 0x04, 0x0000 },
2620                 { 0x1f, 0x0000 },
2621
2622                 { 0x1f, 0x0001 },
2623                 { 0x0b, 0x8480 },
2624                 { 0x1f, 0x0000 },
2625
2626                 { 0x1f, 0x0001 },
2627                 { 0x18, 0x67c7 },
2628                 { 0x04, 0x2000 },
2629                 { 0x03, 0x002f },
2630                 { 0x02, 0x4360 },
2631                 { 0x01, 0x0109 },
2632                 { 0x00, 0x3022 },
2633                 { 0x04, 0x2800 },
2634                 { 0x1f, 0x0000 },
2635
2636                 { 0x1f, 0x0001 },
2637                 { 0x17, 0x0cc0 },
2638                 { 0x1f, 0x0000 }
2639         };
2640
2641         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642 }
2643
2644 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2645 {
2646         static const struct phy_reg phy_reg_init[] = {
2647                 { 0x10, 0xf41b },
2648                 { 0x1f, 0x0000 }
2649         };
2650
2651         rtl_writephy(tp, 0x1f, 0x0001);
2652         rtl_patchphy(tp, 0x16, 1 << 0);
2653
2654         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2655 }
2656
2657 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2658 {
2659         static const struct phy_reg phy_reg_init[] = {
2660                 { 0x1f, 0x0001 },
2661                 { 0x10, 0xf41b },
2662                 { 0x1f, 0x0000 }
2663         };
2664
2665         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2666 }
2667
2668 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670         static const struct phy_reg phy_reg_init[] = {
2671                 { 0x1f, 0x0000 },
2672                 { 0x1d, 0x0f00 },
2673                 { 0x1f, 0x0002 },
2674                 { 0x0c, 0x1ec8 },
2675                 { 0x1f, 0x0000 }
2676         };
2677
2678         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2679 }
2680
2681 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2682 {
2683         static const struct phy_reg phy_reg_init[] = {
2684                 { 0x1f, 0x0001 },
2685                 { 0x1d, 0x3d98 },
2686                 { 0x1f, 0x0000 }
2687         };
2688
2689         rtl_writephy(tp, 0x1f, 0x0000);
2690         rtl_patchphy(tp, 0x14, 1 << 5);
2691         rtl_patchphy(tp, 0x0d, 1 << 5);
2692
2693         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2694 }
2695
2696 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2697 {
2698         static const struct phy_reg phy_reg_init[] = {
2699                 { 0x1f, 0x0001 },
2700                 { 0x12, 0x2300 },
2701                 { 0x1f, 0x0002 },
2702                 { 0x00, 0x88d4 },
2703                 { 0x01, 0x82b1 },
2704                 { 0x03, 0x7002 },
2705                 { 0x08, 0x9e30 },
2706                 { 0x09, 0x01f0 },
2707                 { 0x0a, 0x5500 },
2708                 { 0x0c, 0x00c8 },
2709                 { 0x1f, 0x0003 },
2710                 { 0x12, 0xc096 },
2711                 { 0x16, 0x000a },
2712                 { 0x1f, 0x0000 },
2713                 { 0x1f, 0x0000 },
2714                 { 0x09, 0x2000 },
2715                 { 0x09, 0x0000 }
2716         };
2717
2718         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2719
2720         rtl_patchphy(tp, 0x14, 1 << 5);
2721         rtl_patchphy(tp, 0x0d, 1 << 5);
2722         rtl_writephy(tp, 0x1f, 0x0000);
2723 }
2724
2725 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2726 {
2727         static const struct phy_reg phy_reg_init[] = {
2728                 { 0x1f, 0x0001 },
2729                 { 0x12, 0x2300 },
2730                 { 0x03, 0x802f },
2731                 { 0x02, 0x4f02 },
2732                 { 0x01, 0x0409 },
2733                 { 0x00, 0xf099 },
2734                 { 0x04, 0x9800 },
2735                 { 0x04, 0x9000 },
2736                 { 0x1d, 0x3d98 },
2737                 { 0x1f, 0x0002 },
2738                 { 0x0c, 0x7eb8 },
2739                 { 0x06, 0x0761 },
2740                 { 0x1f, 0x0003 },
2741                 { 0x16, 0x0f0a },
2742                 { 0x1f, 0x0000 }
2743         };
2744
2745         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747         rtl_patchphy(tp, 0x16, 1 << 0);
2748         rtl_patchphy(tp, 0x14, 1 << 5);
2749         rtl_patchphy(tp, 0x0d, 1 << 5);
2750         rtl_writephy(tp, 0x1f, 0x0000);
2751 }
2752
2753 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2754 {
2755         static const struct phy_reg phy_reg_init[] = {
2756                 { 0x1f, 0x0001 },
2757                 { 0x12, 0x2300 },
2758                 { 0x1d, 0x3d98 },
2759                 { 0x1f, 0x0002 },
2760                 { 0x0c, 0x7eb8 },
2761                 { 0x06, 0x5461 },
2762                 { 0x1f, 0x0003 },
2763                 { 0x16, 0x0f0a },
2764                 { 0x1f, 0x0000 }
2765         };
2766
2767         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2768
2769         rtl_patchphy(tp, 0x16, 1 << 0);
2770         rtl_patchphy(tp, 0x14, 1 << 5);
2771         rtl_patchphy(tp, 0x0d, 1 << 5);
2772         rtl_writephy(tp, 0x1f, 0x0000);
2773 }
2774
2775 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2776 {
2777         rtl8168c_3_hw_phy_config(tp);
2778 }
2779
2780 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2781 {
2782         static const struct phy_reg phy_reg_init_0[] = {
2783                 /* Channel Estimation */
2784                 { 0x1f, 0x0001 },
2785                 { 0x06, 0x4064 },
2786                 { 0x07, 0x2863 },
2787                 { 0x08, 0x059c },
2788                 { 0x09, 0x26b4 },
2789                 { 0x0a, 0x6a19 },
2790                 { 0x0b, 0xdcc8 },
2791                 { 0x10, 0xf06d },
2792                 { 0x14, 0x7f68 },
2793                 { 0x18, 0x7fd9 },
2794                 { 0x1c, 0xf0ff },
2795                 { 0x1d, 0x3d9c },
2796                 { 0x1f, 0x0003 },
2797                 { 0x12, 0xf49f },
2798                 { 0x13, 0x070b },
2799                 { 0x1a, 0x05ad },
2800                 { 0x14, 0x94c0 },
2801
2802                 /*
2803                  * Tx Error Issue
2804                  * Enhance line driver power
2805                  */
2806                 { 0x1f, 0x0002 },
2807                 { 0x06, 0x5561 },
2808                 { 0x1f, 0x0005 },
2809                 { 0x05, 0x8332 },
2810                 { 0x06, 0x5561 },
2811
2812                 /*
2813                  * Can not link to 1Gbps with bad cable
2814                  * Decrease SNR threshold form 21.07dB to 19.04dB
2815                  */
2816                 { 0x1f, 0x0001 },
2817                 { 0x17, 0x0cc0 },
2818
2819                 { 0x1f, 0x0000 },
2820                 { 0x0d, 0xf880 }
2821         };
2822
2823         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2824
2825         /*
2826          * Rx Error Issue
2827          * Fine Tune Switching regulator parameter
2828          */
2829         rtl_writephy(tp, 0x1f, 0x0002);
2830         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2831         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2832
2833         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2834                 static const struct phy_reg phy_reg_init[] = {
2835                         { 0x1f, 0x0002 },
2836                         { 0x05, 0x669a },
2837                         { 0x1f, 0x0005 },
2838                         { 0x05, 0x8330 },
2839                         { 0x06, 0x669a },
2840                         { 0x1f, 0x0002 }
2841                 };
2842                 int val;
2843
2844                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2845
2846                 val = rtl_readphy(tp, 0x0d);
2847
2848                 if ((val & 0x00ff) != 0x006c) {
2849                         static const u32 set[] = {
2850                                 0x0065, 0x0066, 0x0067, 0x0068,
2851                                 0x0069, 0x006a, 0x006b, 0x006c
2852                         };
2853                         int i;
2854
2855                         rtl_writephy(tp, 0x1f, 0x0002);
2856
2857                         val &= 0xff00;
2858                         for (i = 0; i < ARRAY_SIZE(set); i++)
2859                                 rtl_writephy(tp, 0x0d, val | set[i]);
2860                 }
2861         } else {
2862                 static const struct phy_reg phy_reg_init[] = {
2863                         { 0x1f, 0x0002 },
2864                         { 0x05, 0x6662 },
2865                         { 0x1f, 0x0005 },
2866                         { 0x05, 0x8330 },
2867                         { 0x06, 0x6662 }
2868                 };
2869
2870                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2871         }
2872
2873         /* RSET couple improve */
2874         rtl_writephy(tp, 0x1f, 0x0002);
2875         rtl_patchphy(tp, 0x0d, 0x0300);
2876         rtl_patchphy(tp, 0x0f, 0x0010);
2877
2878         /* Fine tune PLL performance */
2879         rtl_writephy(tp, 0x1f, 0x0002);
2880         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2881         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2882
2883         rtl_writephy(tp, 0x1f, 0x0005);
2884         rtl_writephy(tp, 0x05, 0x001b);
2885
2886         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2887
2888         rtl_writephy(tp, 0x1f, 0x0000);
2889 }
2890
2891 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2892 {
2893         static const struct phy_reg phy_reg_init_0[] = {
2894                 /* Channel Estimation */
2895                 { 0x1f, 0x0001 },
2896                 { 0x06, 0x4064 },
2897                 { 0x07, 0x2863 },
2898                 { 0x08, 0x059c },
2899                 { 0x09, 0x26b4 },
2900                 { 0x0a, 0x6a19 },
2901                 { 0x0b, 0xdcc8 },
2902                 { 0x10, 0xf06d },
2903                 { 0x14, 0x7f68 },
2904                 { 0x18, 0x7fd9 },
2905                 { 0x1c, 0xf0ff },
2906                 { 0x1d, 0x3d9c },
2907                 { 0x1f, 0x0003 },
2908                 { 0x12, 0xf49f },
2909                 { 0x13, 0x070b },
2910                 { 0x1a, 0x05ad },
2911                 { 0x14, 0x94c0 },
2912
2913                 /*
2914                  * Tx Error Issue
2915                  * Enhance line driver power
2916                  */
2917                 { 0x1f, 0x0002 },
2918                 { 0x06, 0x5561 },
2919                 { 0x1f, 0x0005 },
2920                 { 0x05, 0x8332 },
2921                 { 0x06, 0x5561 },
2922
2923                 /*
2924                  * Can not link to 1Gbps with bad cable
2925                  * Decrease SNR threshold form 21.07dB to 19.04dB
2926                  */
2927                 { 0x1f, 0x0001 },
2928                 { 0x17, 0x0cc0 },
2929
2930                 { 0x1f, 0x0000 },
2931                 { 0x0d, 0xf880 }
2932         };
2933
2934         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2935
2936         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2937                 static const struct phy_reg phy_reg_init[] = {
2938                         { 0x1f, 0x0002 },
2939                         { 0x05, 0x669a },
2940                         { 0x1f, 0x0005 },
2941                         { 0x05, 0x8330 },
2942                         { 0x06, 0x669a },
2943
2944                         { 0x1f, 0x0002 }
2945                 };
2946                 int val;
2947
2948                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2949
2950                 val = rtl_readphy(tp, 0x0d);
2951                 if ((val & 0x00ff) != 0x006c) {
2952                         static const u32 set[] = {
2953                                 0x0065, 0x0066, 0x0067, 0x0068,
2954                                 0x0069, 0x006a, 0x006b, 0x006c
2955                         };
2956                         int i;
2957
2958                         rtl_writephy(tp, 0x1f, 0x0002);
2959
2960                         val &= 0xff00;
2961                         for (i = 0; i < ARRAY_SIZE(set); i++)
2962                                 rtl_writephy(tp, 0x0d, val | set[i]);
2963                 }
2964         } else {
2965                 static const struct phy_reg phy_reg_init[] = {
2966                         { 0x1f, 0x0002 },
2967                         { 0x05, 0x2642 },
2968                         { 0x1f, 0x0005 },
2969                         { 0x05, 0x8330 },
2970                         { 0x06, 0x2642 }
2971                 };
2972
2973                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2974         }
2975
2976         /* Fine tune PLL performance */
2977         rtl_writephy(tp, 0x1f, 0x0002);
2978         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2979         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2980
2981         /* Switching regulator Slew rate */
2982         rtl_writephy(tp, 0x1f, 0x0002);
2983         rtl_patchphy(tp, 0x0f, 0x0017);
2984
2985         rtl_writephy(tp, 0x1f, 0x0005);
2986         rtl_writephy(tp, 0x05, 0x001b);
2987
2988         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2989
2990         rtl_writephy(tp, 0x1f, 0x0000);
2991 }
2992
2993 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2994 {
2995         static const struct phy_reg phy_reg_init[] = {
2996                 { 0x1f, 0x0002 },
2997                 { 0x10, 0x0008 },
2998                 { 0x0d, 0x006c },
2999
3000                 { 0x1f, 0x0000 },
3001                 { 0x0d, 0xf880 },
3002
3003                 { 0x1f, 0x0001 },
3004                 { 0x17, 0x0cc0 },
3005
3006                 { 0x1f, 0x0001 },
3007                 { 0x0b, 0xa4d8 },
3008                 { 0x09, 0x281c },
3009                 { 0x07, 0x2883 },
3010                 { 0x0a, 0x6b35 },
3011                 { 0x1d, 0x3da4 },
3012                 { 0x1c, 0xeffd },
3013                 { 0x14, 0x7f52 },
3014                 { 0x18, 0x7fc6 },
3015                 { 0x08, 0x0601 },
3016                 { 0x06, 0x4063 },
3017                 { 0x10, 0xf074 },
3018                 { 0x1f, 0x0003 },
3019                 { 0x13, 0x0789 },
3020                 { 0x12, 0xf4bd },
3021                 { 0x1a, 0x04fd },
3022                 { 0x14, 0x84b0 },
3023                 { 0x1f, 0x0000 },
3024                 { 0x00, 0x9200 },
3025
3026                 { 0x1f, 0x0005 },
3027                 { 0x01, 0x0340 },
3028                 { 0x1f, 0x0001 },
3029                 { 0x04, 0x4000 },
3030                 { 0x03, 0x1d21 },
3031                 { 0x02, 0x0c32 },
3032                 { 0x01, 0x0200 },
3033                 { 0x00, 0x5554 },
3034                 { 0x04, 0x4800 },
3035                 { 0x04, 0x4000 },
3036                 { 0x04, 0xf000 },
3037                 { 0x03, 0xdf01 },
3038                 { 0x02, 0xdf20 },
3039                 { 0x01, 0x101a },
3040                 { 0x00, 0xa0ff },
3041                 { 0x04, 0xf800 },
3042                 { 0x04, 0xf000 },
3043                 { 0x1f, 0x0000 },
3044
3045                 { 0x1f, 0x0007 },
3046                 { 0x1e, 0x0023 },
3047                 { 0x16, 0x0000 },
3048                 { 0x1f, 0x0000 }
3049         };
3050
3051         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3052 }
3053
3054 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3055 {
3056         static const struct phy_reg phy_reg_init[] = {
3057                 { 0x1f, 0x0001 },
3058                 { 0x17, 0x0cc0 },
3059
3060                 { 0x1f, 0x0007 },
3061                 { 0x1e, 0x002d },
3062                 { 0x18, 0x0040 },
3063                 { 0x1f, 0x0000 }
3064         };
3065
3066         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3067         rtl_patchphy(tp, 0x0d, 1 << 5);
3068 }
3069
3070 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3071 {
3072         static const struct phy_reg phy_reg_init[] = {
3073                 /* Enable Delay cap */
3074                 { 0x1f, 0x0005 },
3075                 { 0x05, 0x8b80 },
3076                 { 0x06, 0xc896 },
3077                 { 0x1f, 0x0000 },
3078
3079                 /* Channel estimation fine tune */
3080                 { 0x1f, 0x0001 },
3081                 { 0x0b, 0x6c20 },
3082                 { 0x07, 0x2872 },
3083                 { 0x1c, 0xefff },
3084                 { 0x1f, 0x0003 },
3085                 { 0x14, 0x6420 },
3086                 { 0x1f, 0x0000 },
3087
3088                 /* Update PFM & 10M TX idle timer */
3089                 { 0x1f, 0x0007 },
3090                 { 0x1e, 0x002f },
3091                 { 0x15, 0x1919 },
3092                 { 0x1f, 0x0000 },
3093
3094                 { 0x1f, 0x0007 },
3095                 { 0x1e, 0x00ac },
3096                 { 0x18, 0x0006 },
3097                 { 0x1f, 0x0000 }
3098         };
3099
3100         rtl_apply_firmware(tp);
3101
3102         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3103
3104         /* DCO enable for 10M IDLE Power */
3105         rtl_writephy(tp, 0x1f, 0x0007);
3106         rtl_writephy(tp, 0x1e, 0x0023);
3107         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3108         rtl_writephy(tp, 0x1f, 0x0000);
3109
3110         /* For impedance matching */
3111         rtl_writephy(tp, 0x1f, 0x0002);
3112         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114
3115         /* PHY auto speed down */
3116         rtl_writephy(tp, 0x1f, 0x0007);
3117         rtl_writephy(tp, 0x1e, 0x002d);
3118         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3121
3122         rtl_writephy(tp, 0x1f, 0x0005);
3123         rtl_writephy(tp, 0x05, 0x8b86);
3124         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126
3127         rtl_writephy(tp, 0x1f, 0x0005);
3128         rtl_writephy(tp, 0x05, 0x8b85);
3129         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3130         rtl_writephy(tp, 0x1f, 0x0007);
3131         rtl_writephy(tp, 0x1e, 0x0020);
3132         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3133         rtl_writephy(tp, 0x1f, 0x0006);
3134         rtl_writephy(tp, 0x00, 0x5a00);
3135         rtl_writephy(tp, 0x1f, 0x0000);
3136         rtl_writephy(tp, 0x0d, 0x0007);
3137         rtl_writephy(tp, 0x0e, 0x003c);
3138         rtl_writephy(tp, 0x0d, 0x4007);
3139         rtl_writephy(tp, 0x0e, 0x0000);
3140         rtl_writephy(tp, 0x0d, 0x0000);
3141 }
3142
3143 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3144 {
3145         const u16 w[] = {
3146                 addr[0] | (addr[1] << 8),
3147                 addr[2] | (addr[3] << 8),
3148                 addr[4] | (addr[5] << 8)
3149         };
3150         const struct exgmac_reg e[] = {
3151                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3152                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3153                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3154                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3155         };
3156
3157         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3158 }
3159
3160 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3161 {
3162         static const struct phy_reg phy_reg_init[] = {
3163                 /* Enable Delay cap */
3164                 { 0x1f, 0x0004 },
3165                 { 0x1f, 0x0007 },
3166                 { 0x1e, 0x00ac },
3167                 { 0x18, 0x0006 },
3168                 { 0x1f, 0x0002 },
3169                 { 0x1f, 0x0000 },
3170                 { 0x1f, 0x0000 },
3171
3172                 /* Channel estimation fine tune */
3173                 { 0x1f, 0x0003 },
3174                 { 0x09, 0xa20f },
3175                 { 0x1f, 0x0000 },
3176                 { 0x1f, 0x0000 },
3177
3178                 /* Green Setting */
3179                 { 0x1f, 0x0005 },
3180                 { 0x05, 0x8b5b },
3181                 { 0x06, 0x9222 },
3182                 { 0x05, 0x8b6d },
3183                 { 0x06, 0x8000 },
3184                 { 0x05, 0x8b76 },
3185                 { 0x06, 0x8000 },
3186                 { 0x1f, 0x0000 }
3187         };
3188
3189         rtl_apply_firmware(tp);
3190
3191         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3192
3193         /* For 4-corner performance improve */
3194         rtl_writephy(tp, 0x1f, 0x0005);
3195         rtl_writephy(tp, 0x05, 0x8b80);
3196         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3197         rtl_writephy(tp, 0x1f, 0x0000);
3198
3199         /* PHY auto speed down */
3200         rtl_writephy(tp, 0x1f, 0x0004);
3201         rtl_writephy(tp, 0x1f, 0x0007);
3202         rtl_writephy(tp, 0x1e, 0x002d);
3203         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3204         rtl_writephy(tp, 0x1f, 0x0002);
3205         rtl_writephy(tp, 0x1f, 0x0000);
3206         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3207
3208         /* improve 10M EEE waveform */
3209         rtl_writephy(tp, 0x1f, 0x0005);
3210         rtl_writephy(tp, 0x05, 0x8b86);
3211         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3212         rtl_writephy(tp, 0x1f, 0x0000);
3213
3214         /* Improve 2-pair detection performance */
3215         rtl_writephy(tp, 0x1f, 0x0005);
3216         rtl_writephy(tp, 0x05, 0x8b85);
3217         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3218         rtl_writephy(tp, 0x1f, 0x0000);
3219
3220         /* EEE setting */
3221         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3222         rtl_writephy(tp, 0x1f, 0x0005);
3223         rtl_writephy(tp, 0x05, 0x8b85);
3224         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3225         rtl_writephy(tp, 0x1f, 0x0004);
3226         rtl_writephy(tp, 0x1f, 0x0007);
3227         rtl_writephy(tp, 0x1e, 0x0020);
3228         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3229         rtl_writephy(tp, 0x1f, 0x0002);
3230         rtl_writephy(tp, 0x1f, 0x0000);
3231         rtl_writephy(tp, 0x0d, 0x0007);
3232         rtl_writephy(tp, 0x0e, 0x003c);
3233         rtl_writephy(tp, 0x0d, 0x4007);
3234         rtl_writephy(tp, 0x0e, 0x0006);
3235         rtl_writephy(tp, 0x0d, 0x0000);
3236
3237         /* Green feature */
3238         rtl_writephy(tp, 0x1f, 0x0003);
3239         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3240         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3241         rtl_writephy(tp, 0x1f, 0x0000);
3242         rtl_writephy(tp, 0x1f, 0x0005);
3243         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3244         rtl_writephy(tp, 0x1f, 0x0000);
3245
3246         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3247         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3248 }
3249
3250 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3251 {
3252         /* For 4-corner performance improve */
3253         rtl_writephy(tp, 0x1f, 0x0005);
3254         rtl_writephy(tp, 0x05, 0x8b80);
3255         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3256         rtl_writephy(tp, 0x1f, 0x0000);
3257
3258         /* PHY auto speed down */
3259         rtl_writephy(tp, 0x1f, 0x0007);
3260         rtl_writephy(tp, 0x1e, 0x002d);
3261         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3264
3265         /* Improve 10M EEE waveform */
3266         rtl_writephy(tp, 0x1f, 0x0005);
3267         rtl_writephy(tp, 0x05, 0x8b86);
3268         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3269         rtl_writephy(tp, 0x1f, 0x0000);
3270 }
3271
3272 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3273 {
3274         static const struct phy_reg phy_reg_init[] = {
3275                 /* Channel estimation fine tune */
3276                 { 0x1f, 0x0003 },
3277                 { 0x09, 0xa20f },
3278                 { 0x1f, 0x0000 },
3279
3280                 /* Modify green table for giga & fnet */
3281                 { 0x1f, 0x0005 },
3282                 { 0x05, 0x8b55 },
3283                 { 0x06, 0x0000 },
3284                 { 0x05, 0x8b5e },
3285                 { 0x06, 0x0000 },
3286                 { 0x05, 0x8b67 },
3287                 { 0x06, 0x0000 },
3288                 { 0x05, 0x8b70 },
3289                 { 0x06, 0x0000 },
3290                 { 0x1f, 0x0000 },
3291                 { 0x1f, 0x0007 },
3292                 { 0x1e, 0x0078 },
3293                 { 0x17, 0x0000 },
3294                 { 0x19, 0x00fb },
3295                 { 0x1f, 0x0000 },
3296
3297                 /* Modify green table for 10M */
3298                 { 0x1f, 0x0005 },
3299                 { 0x05, 0x8b79 },
3300                 { 0x06, 0xaa00 },
3301                 { 0x1f, 0x0000 },
3302
3303                 /* Disable hiimpedance detection (RTCT) */
3304                 { 0x1f, 0x0003 },
3305                 { 0x01, 0x328a },
3306                 { 0x1f, 0x0000 }
3307         };
3308
3309         rtl_apply_firmware(tp);
3310
3311         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3312
3313         rtl8168f_hw_phy_config(tp);
3314
3315         /* Improve 2-pair detection performance */
3316         rtl_writephy(tp, 0x1f, 0x0005);
3317         rtl_writephy(tp, 0x05, 0x8b85);
3318         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3319         rtl_writephy(tp, 0x1f, 0x0000);
3320 }
3321
3322 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3323 {
3324         rtl_apply_firmware(tp);
3325
3326         rtl8168f_hw_phy_config(tp);
3327 }
3328
3329 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3330 {
3331         static const struct phy_reg phy_reg_init[] = {
3332                 /* Channel estimation fine tune */
3333                 { 0x1f, 0x0003 },
3334                 { 0x09, 0xa20f },
3335                 { 0x1f, 0x0000 },
3336
3337                 /* Modify green table for giga & fnet */
3338                 { 0x1f, 0x0005 },
3339                 { 0x05, 0x8b55 },
3340                 { 0x06, 0x0000 },
3341                 { 0x05, 0x8b5e },
3342                 { 0x06, 0x0000 },
3343                 { 0x05, 0x8b67 },
3344                 { 0x06, 0x0000 },
3345                 { 0x05, 0x8b70 },
3346                 { 0x06, 0x0000 },
3347                 { 0x1f, 0x0000 },
3348                 { 0x1f, 0x0007 },
3349                 { 0x1e, 0x0078 },
3350                 { 0x17, 0x0000 },
3351                 { 0x19, 0x00aa },
3352                 { 0x1f, 0x0000 },
3353
3354                 /* Modify green table for 10M */
3355                 { 0x1f, 0x0005 },
3356                 { 0x05, 0x8b79 },
3357                 { 0x06, 0xaa00 },
3358                 { 0x1f, 0x0000 },
3359
3360                 /* Disable hiimpedance detection (RTCT) */
3361                 { 0x1f, 0x0003 },
3362                 { 0x01, 0x328a },
3363                 { 0x1f, 0x0000 }
3364         };
3365
3366
3367         rtl_apply_firmware(tp);
3368
3369         rtl8168f_hw_phy_config(tp);
3370
3371         /* Improve 2-pair detection performance */
3372         rtl_writephy(tp, 0x1f, 0x0005);
3373         rtl_writephy(tp, 0x05, 0x8b85);
3374         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3375         rtl_writephy(tp, 0x1f, 0x0000);
3376
3377         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3378
3379         /* Modify green table for giga */
3380         rtl_writephy(tp, 0x1f, 0x0005);
3381         rtl_writephy(tp, 0x05, 0x8b54);
3382         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3383         rtl_writephy(tp, 0x05, 0x8b5d);
3384         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3385         rtl_writephy(tp, 0x05, 0x8a7c);
3386         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3387         rtl_writephy(tp, 0x05, 0x8a7f);
3388         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3389         rtl_writephy(tp, 0x05, 0x8a82);
3390         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3391         rtl_writephy(tp, 0x05, 0x8a85);
3392         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3393         rtl_writephy(tp, 0x05, 0x8a88);
3394         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3395         rtl_writephy(tp, 0x1f, 0x0000);
3396
3397         /* uc same-seed solution */
3398         rtl_writephy(tp, 0x1f, 0x0005);
3399         rtl_writephy(tp, 0x05, 0x8b85);
3400         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3401         rtl_writephy(tp, 0x1f, 0x0000);
3402
3403         /* eee setting */
3404         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3405         rtl_writephy(tp, 0x1f, 0x0005);
3406         rtl_writephy(tp, 0x05, 0x8b85);
3407         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3408         rtl_writephy(tp, 0x1f, 0x0004);
3409         rtl_writephy(tp, 0x1f, 0x0007);
3410         rtl_writephy(tp, 0x1e, 0x0020);
3411         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3412         rtl_writephy(tp, 0x1f, 0x0000);
3413         rtl_writephy(tp, 0x0d, 0x0007);
3414         rtl_writephy(tp, 0x0e, 0x003c);
3415         rtl_writephy(tp, 0x0d, 0x4007);
3416         rtl_writephy(tp, 0x0e, 0x0000);
3417         rtl_writephy(tp, 0x0d, 0x0000);
3418
3419         /* Green feature */
3420         rtl_writephy(tp, 0x1f, 0x0003);
3421         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3422         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3423         rtl_writephy(tp, 0x1f, 0x0000);
3424 }
3425
3426 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3427 {
3428         rtl_apply_firmware(tp);
3429
3430         rtl_writephy(tp, 0x1f, 0x0a46);
3431         if (rtl_readphy(tp, 0x10) & 0x0100) {
3432                 rtl_writephy(tp, 0x1f, 0x0bcc);
3433                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3434         } else {
3435                 rtl_writephy(tp, 0x1f, 0x0bcc);
3436                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3437         }
3438
3439         rtl_writephy(tp, 0x1f, 0x0a46);
3440         if (rtl_readphy(tp, 0x13) & 0x0100) {
3441                 rtl_writephy(tp, 0x1f, 0x0c41);
3442                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3443         } else {
3444                 rtl_writephy(tp, 0x1f, 0x0c41);
3445                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3446         }
3447
3448         /* Enable PHY auto speed down */
3449         rtl_writephy(tp, 0x1f, 0x0a44);
3450         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3451
3452         rtl_writephy(tp, 0x1f, 0x0bcc);
3453         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3454         rtl_writephy(tp, 0x1f, 0x0a44);
3455         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3456         rtl_writephy(tp, 0x1f, 0x0a43);
3457         rtl_writephy(tp, 0x13, 0x8084);
3458         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3459         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3460
3461         /* EEE auto-fallback function */
3462         rtl_writephy(tp, 0x1f, 0x0a4b);
3463         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3464
3465         /* Enable UC LPF tune function */
3466         rtl_writephy(tp, 0x1f, 0x0a43);
3467         rtl_writephy(tp, 0x13, 0x8012);
3468         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3469
3470         rtl_writephy(tp, 0x1f, 0x0c42);
3471         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3472
3473         /* Improve SWR Efficiency */
3474         rtl_writephy(tp, 0x1f, 0x0bcd);
3475         rtl_writephy(tp, 0x14, 0x5065);
3476         rtl_writephy(tp, 0x14, 0xd065);
3477         rtl_writephy(tp, 0x1f, 0x0bc8);
3478         rtl_writephy(tp, 0x11, 0x5655);
3479         rtl_writephy(tp, 0x1f, 0x0bcd);
3480         rtl_writephy(tp, 0x14, 0x1065);
3481         rtl_writephy(tp, 0x14, 0x9065);
3482         rtl_writephy(tp, 0x14, 0x1065);
3483
3484         /* Check ALDPS bit, disable it if enabled */
3485         rtl_writephy(tp, 0x1f, 0x0a43);
3486         if (rtl_readphy(tp, 0x10) & 0x0004)
3487                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3488
3489         rtl_writephy(tp, 0x1f, 0x0000);
3490 }
3491
3492 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3493 {
3494         rtl_apply_firmware(tp);
3495 }
3496
3497 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3498 {
3499         u16 dout_tapbin;
3500         u32 data;
3501
3502         rtl_apply_firmware(tp);
3503
3504         /* CHN EST parameters adjust - giga master */
3505         rtl_writephy(tp, 0x1f, 0x0a43);
3506         rtl_writephy(tp, 0x13, 0x809b);
3507         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3508         rtl_writephy(tp, 0x13, 0x80a2);
3509         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3510         rtl_writephy(tp, 0x13, 0x80a4);
3511         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3512         rtl_writephy(tp, 0x13, 0x809c);
3513         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3514         rtl_writephy(tp, 0x1f, 0x0000);
3515
3516         /* CHN EST parameters adjust - giga slave */
3517         rtl_writephy(tp, 0x1f, 0x0a43);
3518         rtl_writephy(tp, 0x13, 0x80ad);
3519         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3520         rtl_writephy(tp, 0x13, 0x80b4);
3521         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3522         rtl_writephy(tp, 0x13, 0x80ac);
3523         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3524         rtl_writephy(tp, 0x1f, 0x0000);
3525
3526         /* CHN EST parameters adjust - fnet */
3527         rtl_writephy(tp, 0x1f, 0x0a43);
3528         rtl_writephy(tp, 0x13, 0x808e);
3529         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3530         rtl_writephy(tp, 0x13, 0x8090);
3531         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3532         rtl_writephy(tp, 0x13, 0x8092);
3533         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3534         rtl_writephy(tp, 0x1f, 0x0000);
3535
3536         /* enable R-tune & PGA-retune function */
3537         dout_tapbin = 0;
3538         rtl_writephy(tp, 0x1f, 0x0a46);
3539         data = rtl_readphy(tp, 0x13);
3540         data &= 3;
3541         data <<= 2;
3542         dout_tapbin |= data;
3543         data = rtl_readphy(tp, 0x12);
3544         data &= 0xc000;
3545         data >>= 14;
3546         dout_tapbin |= data;
3547         dout_tapbin = ~(dout_tapbin^0x08);
3548         dout_tapbin <<= 12;
3549         dout_tapbin &= 0xf000;
3550         rtl_writephy(tp, 0x1f, 0x0a43);
3551         rtl_writephy(tp, 0x13, 0x827a);
3552         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3553         rtl_writephy(tp, 0x13, 0x827b);
3554         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3555         rtl_writephy(tp, 0x13, 0x827c);
3556         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3557         rtl_writephy(tp, 0x13, 0x827d);
3558         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3559
3560         rtl_writephy(tp, 0x1f, 0x0a43);
3561         rtl_writephy(tp, 0x13, 0x0811);
3562         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3563         rtl_writephy(tp, 0x1f, 0x0a42);
3564         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3565         rtl_writephy(tp, 0x1f, 0x0000);
3566
3567         /* enable GPHY 10M */
3568         rtl_writephy(tp, 0x1f, 0x0a44);
3569         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3570         rtl_writephy(tp, 0x1f, 0x0000);
3571
3572         /* SAR ADC performance */
3573         rtl_writephy(tp, 0x1f, 0x0bca);
3574         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576
3577         rtl_writephy(tp, 0x1f, 0x0a43);
3578         rtl_writephy(tp, 0x13, 0x803f);
3579         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3580         rtl_writephy(tp, 0x13, 0x8047);
3581         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3582         rtl_writephy(tp, 0x13, 0x804f);
3583         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3584         rtl_writephy(tp, 0x13, 0x8057);
3585         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3586         rtl_writephy(tp, 0x13, 0x805f);
3587         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3588         rtl_writephy(tp, 0x13, 0x8067);
3589         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3590         rtl_writephy(tp, 0x13, 0x806f);
3591         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3592         rtl_writephy(tp, 0x1f, 0x0000);
3593
3594         /* disable phy pfm mode */
3595         rtl_writephy(tp, 0x1f, 0x0a44);
3596         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3597         rtl_writephy(tp, 0x1f, 0x0000);
3598
3599         /* Check ALDPS bit, disable it if enabled */
3600         rtl_writephy(tp, 0x1f, 0x0a43);
3601         if (rtl_readphy(tp, 0x10) & 0x0004)
3602                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3603
3604         rtl_writephy(tp, 0x1f, 0x0000);
3605 }
3606
3607 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3608 {
3609         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3610         u16 rlen;
3611         u32 data;
3612
3613         rtl_apply_firmware(tp);
3614
3615         /* CHIN EST parameter update */
3616         rtl_writephy(tp, 0x1f, 0x0a43);
3617         rtl_writephy(tp, 0x13, 0x808a);
3618         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3619         rtl_writephy(tp, 0x1f, 0x0000);
3620
3621         /* enable R-tune & PGA-retune function */
3622         rtl_writephy(tp, 0x1f, 0x0a43);
3623         rtl_writephy(tp, 0x13, 0x0811);
3624         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3625         rtl_writephy(tp, 0x1f, 0x0a42);
3626         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3627         rtl_writephy(tp, 0x1f, 0x0000);
3628
3629         /* enable GPHY 10M */
3630         rtl_writephy(tp, 0x1f, 0x0a44);
3631         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3632         rtl_writephy(tp, 0x1f, 0x0000);
3633
3634         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3635         data = r8168_mac_ocp_read(tp, 0xdd02);
3636         ioffset_p3 = ((data & 0x80)>>7);
3637         ioffset_p3 <<= 3;
3638
3639         data = r8168_mac_ocp_read(tp, 0xdd00);
3640         ioffset_p3 |= ((data & (0xe000))>>13);
3641         ioffset_p2 = ((data & (0x1e00))>>9);
3642         ioffset_p1 = ((data & (0x01e0))>>5);
3643         ioffset_p0 = ((data & 0x0010)>>4);
3644         ioffset_p0 <<= 3;
3645         ioffset_p0 |= (data & (0x07));
3646         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3647
3648         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3649             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3650                 rtl_writephy(tp, 0x1f, 0x0bcf);
3651                 rtl_writephy(tp, 0x16, data);
3652                 rtl_writephy(tp, 0x1f, 0x0000);
3653         }
3654
3655         /* Modify rlen (TX LPF corner frequency) level */
3656         rtl_writephy(tp, 0x1f, 0x0bcd);
3657         data = rtl_readphy(tp, 0x16);
3658         data &= 0x000f;
3659         rlen = 0;
3660         if (data > 3)
3661                 rlen = data - 3;
3662         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3663         rtl_writephy(tp, 0x17, data);
3664         rtl_writephy(tp, 0x1f, 0x0bcd);
3665         rtl_writephy(tp, 0x1f, 0x0000);
3666
3667         /* disable phy pfm mode */
3668         rtl_writephy(tp, 0x1f, 0x0a44);
3669         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3670         rtl_writephy(tp, 0x1f, 0x0000);
3671
3672         /* Check ALDPS bit, disable it if enabled */
3673         rtl_writephy(tp, 0x1f, 0x0a43);
3674         if (rtl_readphy(tp, 0x10) & 0x0004)
3675                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3676
3677         rtl_writephy(tp, 0x1f, 0x0000);
3678 }
3679
3680 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3681 {
3682         /* Enable PHY auto speed down */
3683         rtl_writephy(tp, 0x1f, 0x0a44);
3684         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3685         rtl_writephy(tp, 0x1f, 0x0000);
3686
3687         /* patch 10M & ALDPS */
3688         rtl_writephy(tp, 0x1f, 0x0bcc);
3689         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3690         rtl_writephy(tp, 0x1f, 0x0a44);
3691         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0a43);
3693         rtl_writephy(tp, 0x13, 0x8084);
3694         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3695         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3696         rtl_writephy(tp, 0x1f, 0x0000);
3697
3698         /* Enable EEE auto-fallback function */
3699         rtl_writephy(tp, 0x1f, 0x0a4b);
3700         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3701         rtl_writephy(tp, 0x1f, 0x0000);
3702
3703         /* Enable UC LPF tune function */
3704         rtl_writephy(tp, 0x1f, 0x0a43);
3705         rtl_writephy(tp, 0x13, 0x8012);
3706         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708
3709         /* set rg_sel_sdm_rate */
3710         rtl_writephy(tp, 0x1f, 0x0c42);
3711         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3712         rtl_writephy(tp, 0x1f, 0x0000);
3713
3714         /* Check ALDPS bit, disable it if enabled */
3715         rtl_writephy(tp, 0x1f, 0x0a43);
3716         if (rtl_readphy(tp, 0x10) & 0x0004)
3717                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3718
3719         rtl_writephy(tp, 0x1f, 0x0000);
3720 }
3721
3722 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3723 {
3724         /* patch 10M & ALDPS */
3725         rtl_writephy(tp, 0x1f, 0x0bcc);
3726         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3727         rtl_writephy(tp, 0x1f, 0x0a44);
3728         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3729         rtl_writephy(tp, 0x1f, 0x0a43);
3730         rtl_writephy(tp, 0x13, 0x8084);
3731         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3732         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3733         rtl_writephy(tp, 0x1f, 0x0000);
3734
3735         /* Enable UC LPF tune function */
3736         rtl_writephy(tp, 0x1f, 0x0a43);
3737         rtl_writephy(tp, 0x13, 0x8012);
3738         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3739         rtl_writephy(tp, 0x1f, 0x0000);
3740
3741         /* Set rg_sel_sdm_rate */
3742         rtl_writephy(tp, 0x1f, 0x0c42);
3743         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3744         rtl_writephy(tp, 0x1f, 0x0000);
3745
3746         /* Channel estimation parameters */
3747         rtl_writephy(tp, 0x1f, 0x0a43);
3748         rtl_writephy(tp, 0x13, 0x80f3);
3749         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3750         rtl_writephy(tp, 0x13, 0x80f0);
3751         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3752         rtl_writephy(tp, 0x13, 0x80ef);
3753         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3754         rtl_writephy(tp, 0x13, 0x80f6);
3755         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3756         rtl_writephy(tp, 0x13, 0x80ec);
3757         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3758         rtl_writephy(tp, 0x13, 0x80ed);
3759         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3760         rtl_writephy(tp, 0x13, 0x80f2);
3761         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3762         rtl_writephy(tp, 0x13, 0x80f4);
3763         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3764         rtl_writephy(tp, 0x1f, 0x0a43);
3765         rtl_writephy(tp, 0x13, 0x8110);
3766         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3767         rtl_writephy(tp, 0x13, 0x810f);
3768         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3769         rtl_writephy(tp, 0x13, 0x8111);
3770         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3771         rtl_writephy(tp, 0x13, 0x8113);
3772         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3773         rtl_writephy(tp, 0x13, 0x8115);
3774         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3775         rtl_writephy(tp, 0x13, 0x810e);
3776         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3777         rtl_writephy(tp, 0x13, 0x810c);
3778         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3779         rtl_writephy(tp, 0x13, 0x810b);
3780         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3781         rtl_writephy(tp, 0x1f, 0x0a43);
3782         rtl_writephy(tp, 0x13, 0x80d1);
3783         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3784         rtl_writephy(tp, 0x13, 0x80cd);
3785         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3786         rtl_writephy(tp, 0x13, 0x80d3);
3787         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3788         rtl_writephy(tp, 0x13, 0x80d5);
3789         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3790         rtl_writephy(tp, 0x13, 0x80d7);
3791         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3792
3793         /* Force PWM-mode */
3794         rtl_writephy(tp, 0x1f, 0x0bcd);
3795         rtl_writephy(tp, 0x14, 0x5065);
3796         rtl_writephy(tp, 0x14, 0xd065);
3797         rtl_writephy(tp, 0x1f, 0x0bc8);
3798         rtl_writephy(tp, 0x12, 0x00ed);
3799         rtl_writephy(tp, 0x1f, 0x0bcd);
3800         rtl_writephy(tp, 0x14, 0x1065);
3801         rtl_writephy(tp, 0x14, 0x9065);
3802         rtl_writephy(tp, 0x14, 0x1065);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         /* Check ALDPS bit, disable it if enabled */
3806         rtl_writephy(tp, 0x1f, 0x0a43);
3807         if (rtl_readphy(tp, 0x10) & 0x0004)
3808                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3809
3810         rtl_writephy(tp, 0x1f, 0x0000);
3811 }
3812
3813 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3814 {
3815         static const struct phy_reg phy_reg_init[] = {
3816                 { 0x1f, 0x0003 },
3817                 { 0x08, 0x441d },
3818                 { 0x01, 0x9100 },
3819                 { 0x1f, 0x0000 }
3820         };
3821
3822         rtl_writephy(tp, 0x1f, 0x0000);
3823         rtl_patchphy(tp, 0x11, 1 << 12);
3824         rtl_patchphy(tp, 0x19, 1 << 13);
3825         rtl_patchphy(tp, 0x10, 1 << 15);
3826
3827         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3828 }
3829
3830 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3831 {
3832         static const struct phy_reg phy_reg_init[] = {
3833                 { 0x1f, 0x0005 },
3834                 { 0x1a, 0x0000 },
3835                 { 0x1f, 0x0000 },
3836
3837                 { 0x1f, 0x0004 },
3838                 { 0x1c, 0x0000 },
3839                 { 0x1f, 0x0000 },
3840
3841                 { 0x1f, 0x0001 },
3842                 { 0x15, 0x7701 },
3843                 { 0x1f, 0x0000 }
3844         };
3845
3846         /* Disable ALDPS before ram code */
3847         rtl_writephy(tp, 0x1f, 0x0000);
3848         rtl_writephy(tp, 0x18, 0x0310);
3849         msleep(100);
3850
3851         rtl_apply_firmware(tp);
3852
3853         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3854 }
3855
3856 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3857 {
3858         /* Disable ALDPS before setting firmware */
3859         rtl_writephy(tp, 0x1f, 0x0000);
3860         rtl_writephy(tp, 0x18, 0x0310);
3861         msleep(20);
3862
3863         rtl_apply_firmware(tp);
3864
3865         /* EEE setting */
3866         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3867         rtl_writephy(tp, 0x1f, 0x0004);
3868         rtl_writephy(tp, 0x10, 0x401f);
3869         rtl_writephy(tp, 0x19, 0x7030);
3870         rtl_writephy(tp, 0x1f, 0x0000);
3871 }
3872
3873 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3874 {
3875         static const struct phy_reg phy_reg_init[] = {
3876                 { 0x1f, 0x0004 },
3877                 { 0x10, 0xc07f },
3878                 { 0x19, 0x7030 },
3879                 { 0x1f, 0x0000 }
3880         };
3881
3882         /* Disable ALDPS before ram code */
3883         rtl_writephy(tp, 0x1f, 0x0000);
3884         rtl_writephy(tp, 0x18, 0x0310);
3885         msleep(100);
3886
3887         rtl_apply_firmware(tp);
3888
3889         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3890         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3891
3892         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3893 }
3894
3895 static void rtl_hw_phy_config(struct net_device *dev)
3896 {
3897         struct rtl8169_private *tp = netdev_priv(dev);
3898
3899         rtl8169_print_mac_version(tp);
3900
3901         switch (tp->mac_version) {
3902         case RTL_GIGA_MAC_VER_01:
3903                 break;
3904         case RTL_GIGA_MAC_VER_02:
3905         case RTL_GIGA_MAC_VER_03:
3906                 rtl8169s_hw_phy_config(tp);
3907                 break;
3908         case RTL_GIGA_MAC_VER_04:
3909                 rtl8169sb_hw_phy_config(tp);
3910                 break;
3911         case RTL_GIGA_MAC_VER_05:
3912                 rtl8169scd_hw_phy_config(tp);
3913                 break;
3914         case RTL_GIGA_MAC_VER_06:
3915                 rtl8169sce_hw_phy_config(tp);
3916                 break;
3917         case RTL_GIGA_MAC_VER_07:
3918         case RTL_GIGA_MAC_VER_08:
3919         case RTL_GIGA_MAC_VER_09:
3920                 rtl8102e_hw_phy_config(tp);
3921                 break;
3922         case RTL_GIGA_MAC_VER_11:
3923                 rtl8168bb_hw_phy_config(tp);
3924                 break;
3925         case RTL_GIGA_MAC_VER_12:
3926                 rtl8168bef_hw_phy_config(tp);
3927                 break;
3928         case RTL_GIGA_MAC_VER_17:
3929                 rtl8168bef_hw_phy_config(tp);
3930                 break;
3931         case RTL_GIGA_MAC_VER_18:
3932                 rtl8168cp_1_hw_phy_config(tp);
3933                 break;
3934         case RTL_GIGA_MAC_VER_19:
3935                 rtl8168c_1_hw_phy_config(tp);
3936                 break;
3937         case RTL_GIGA_MAC_VER_20:
3938                 rtl8168c_2_hw_phy_config(tp);
3939                 break;
3940         case RTL_GIGA_MAC_VER_21:
3941                 rtl8168c_3_hw_phy_config(tp);
3942                 break;
3943         case RTL_GIGA_MAC_VER_22:
3944                 rtl8168c_4_hw_phy_config(tp);
3945                 break;
3946         case RTL_GIGA_MAC_VER_23:
3947         case RTL_GIGA_MAC_VER_24:
3948                 rtl8168cp_2_hw_phy_config(tp);
3949                 break;
3950         case RTL_GIGA_MAC_VER_25:
3951                 rtl8168d_1_hw_phy_config(tp);
3952                 break;
3953         case RTL_GIGA_MAC_VER_26:
3954                 rtl8168d_2_hw_phy_config(tp);
3955                 break;
3956         case RTL_GIGA_MAC_VER_27:
3957                 rtl8168d_3_hw_phy_config(tp);
3958                 break;
3959         case RTL_GIGA_MAC_VER_28:
3960                 rtl8168d_4_hw_phy_config(tp);
3961                 break;
3962         case RTL_GIGA_MAC_VER_29:
3963         case RTL_GIGA_MAC_VER_30:
3964                 rtl8105e_hw_phy_config(tp);
3965                 break;
3966         case RTL_GIGA_MAC_VER_31:
3967                 /* None. */
3968                 break;
3969         case RTL_GIGA_MAC_VER_32:
3970         case RTL_GIGA_MAC_VER_33:
3971                 rtl8168e_1_hw_phy_config(tp);
3972                 break;
3973         case RTL_GIGA_MAC_VER_34:
3974                 rtl8168e_2_hw_phy_config(tp);
3975                 break;
3976         case RTL_GIGA_MAC_VER_35:
3977                 rtl8168f_1_hw_phy_config(tp);
3978                 break;
3979         case RTL_GIGA_MAC_VER_36:
3980                 rtl8168f_2_hw_phy_config(tp);
3981                 break;
3982
3983         case RTL_GIGA_MAC_VER_37:
3984                 rtl8402_hw_phy_config(tp);
3985                 break;
3986
3987         case RTL_GIGA_MAC_VER_38:
3988                 rtl8411_hw_phy_config(tp);
3989                 break;
3990
3991         case RTL_GIGA_MAC_VER_39:
3992                 rtl8106e_hw_phy_config(tp);
3993                 break;
3994
3995         case RTL_GIGA_MAC_VER_40:
3996                 rtl8168g_1_hw_phy_config(tp);
3997                 break;
3998         case RTL_GIGA_MAC_VER_42:
3999         case RTL_GIGA_MAC_VER_43:
4000         case RTL_GIGA_MAC_VER_44:
4001                 rtl8168g_2_hw_phy_config(tp);
4002                 break;
4003         case RTL_GIGA_MAC_VER_45:
4004         case RTL_GIGA_MAC_VER_47:
4005                 rtl8168h_1_hw_phy_config(tp);
4006                 break;
4007         case RTL_GIGA_MAC_VER_46:
4008         case RTL_GIGA_MAC_VER_48:
4009                 rtl8168h_2_hw_phy_config(tp);
4010                 break;
4011
4012         case RTL_GIGA_MAC_VER_49:
4013                 rtl8168ep_1_hw_phy_config(tp);
4014                 break;
4015         case RTL_GIGA_MAC_VER_50:
4016         case RTL_GIGA_MAC_VER_51:
4017                 rtl8168ep_2_hw_phy_config(tp);
4018                 break;
4019
4020         case RTL_GIGA_MAC_VER_41:
4021         default:
4022                 break;
4023         }
4024 }
4025
4026 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4027 {
4028         if (!test_and_set_bit(flag, tp->wk.flags))
4029                 schedule_work(&tp->wk.work);
4030 }
4031
4032 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4033 {
4034         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4035                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4036 }
4037
4038 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4039 {
4040         rtl_hw_phy_config(dev);
4041
4042         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4043                 netif_dbg(tp, drv, dev,
4044                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4045                 RTL_W8(tp, 0x82, 0x01);
4046         }
4047
4048         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4049
4050         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4051                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4052
4053         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4054                 netif_dbg(tp, drv, dev,
4055                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4056                 RTL_W8(tp, 0x82, 0x01);
4057                 netif_dbg(tp, drv, dev,
4058                           "Set PHY Reg 0x0bh = 0x00h\n");
4059                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4060         }
4061
4062         /* We may have called phy_speed_down before */
4063         phy_speed_up(dev->phydev);
4064
4065         genphy_soft_reset(dev->phydev);
4066
4067         /* It was reported that several chips end up with 10MBit/Half on a
4068          * 1GBit link after resuming from S3. For whatever reason the PHY on
4069          * these chips doesn't properly start a renegotiation when soft-reset.
4070          * Explicitly requesting a renegotiation fixes this.
4071          */
4072         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4073                 phy_restart_aneg(dev->phydev);
4074 }
4075
4076 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4077 {
4078         rtl_lock_work(tp);
4079
4080         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4081
4082         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4083         RTL_R32(tp, MAC4);
4084
4085         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4086         RTL_R32(tp, MAC0);
4087
4088         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4089                 rtl_rar_exgmac_set(tp, addr);
4090
4091         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4092
4093         rtl_unlock_work(tp);
4094 }
4095
4096 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4097 {
4098         switch (tp->mac_version) {
4099         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4100         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4101                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4102                 break;
4103         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4104         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4105         case RTL_GIGA_MAC_VER_38:
4106                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4107                 break;
4108         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4109                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4110                 break;
4111         default:
4112                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4113                 break;
4114         }
4115 }
4116
4117 static int rtl_set_mac_address(struct net_device *dev, void *p)
4118 {
4119         struct rtl8169_private *tp = netdev_priv(dev);
4120         struct device *d = tp_to_dev(tp);
4121         int ret;
4122
4123         ret = eth_mac_addr(dev, p);
4124         if (ret)
4125                 return ret;
4126
4127         pm_runtime_get_noresume(d);
4128
4129         if (pm_runtime_active(d))
4130                 rtl_rar_set(tp, dev->dev_addr);
4131
4132         pm_runtime_put_noidle(d);
4133
4134         /* Reportedly at least Asus X453MA truncates packets otherwise */
4135         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4136                 rtl_init_rxcfg(tp);
4137
4138         return 0;
4139 }
4140
4141 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4142 {
4143         if (!netif_running(dev))
4144                 return -ENODEV;
4145
4146         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4147 }
4148
4149 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4150 {
4151         struct mdio_ops *ops = &tp->mdio_ops;
4152
4153         switch (tp->mac_version) {
4154         case RTL_GIGA_MAC_VER_27:
4155                 ops->write      = r8168dp_1_mdio_write;
4156                 ops->read       = r8168dp_1_mdio_read;
4157                 break;
4158         case RTL_GIGA_MAC_VER_28:
4159         case RTL_GIGA_MAC_VER_31:
4160                 ops->write      = r8168dp_2_mdio_write;
4161                 ops->read       = r8168dp_2_mdio_read;
4162                 break;
4163         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4164                 ops->write      = r8168g_mdio_write;
4165                 ops->read       = r8168g_mdio_read;
4166                 break;
4167         default:
4168                 ops->write      = r8169_mdio_write;
4169                 ops->read       = r8169_mdio_read;
4170                 break;
4171         }
4172 }
4173
4174 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4175 {
4176         switch (tp->mac_version) {
4177         case RTL_GIGA_MAC_VER_25:
4178         case RTL_GIGA_MAC_VER_26:
4179         case RTL_GIGA_MAC_VER_29:
4180         case RTL_GIGA_MAC_VER_30:
4181         case RTL_GIGA_MAC_VER_32:
4182         case RTL_GIGA_MAC_VER_33:
4183         case RTL_GIGA_MAC_VER_34:
4184         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4185                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4186                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4187                 break;
4188         default:
4189                 break;
4190         }
4191 }
4192
4193 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4194 {
4195         struct phy_device *phydev;
4196
4197         if (!__rtl8169_get_wol(tp))
4198                 return false;
4199
4200         /* phydev may not be attached to netdevice */
4201         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4202
4203         phy_speed_down(phydev, false);
4204         rtl_wol_suspend_quirk(tp);
4205
4206         return true;
4207 }
4208
4209 static void r8168_pll_power_down(struct rtl8169_private *tp)
4210 {
4211         if (r8168_check_dash(tp))
4212                 return;
4213
4214         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4215             tp->mac_version == RTL_GIGA_MAC_VER_33)
4216                 rtl_ephy_write(tp, 0x19, 0xff64);
4217
4218         if (rtl_wol_pll_power_down(tp))
4219                 return;
4220
4221         switch (tp->mac_version) {
4222         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
4223         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
4224         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
4225         case RTL_GIGA_MAC_VER_37:
4226         case RTL_GIGA_MAC_VER_39:
4227         case RTL_GIGA_MAC_VER_43:
4228         case RTL_GIGA_MAC_VER_44:
4229         case RTL_GIGA_MAC_VER_45:
4230         case RTL_GIGA_MAC_VER_46:
4231         case RTL_GIGA_MAC_VER_47:
4232         case RTL_GIGA_MAC_VER_48:
4233         case RTL_GIGA_MAC_VER_50:
4234         case RTL_GIGA_MAC_VER_51:
4235                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4236                 break;
4237         case RTL_GIGA_MAC_VER_40:
4238         case RTL_GIGA_MAC_VER_41:
4239         case RTL_GIGA_MAC_VER_49:
4240                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4241                              0xfc000000, ERIAR_EXGMAC);
4242                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4243                 break;
4244         }
4245 }
4246
4247 static void r8168_pll_power_up(struct rtl8169_private *tp)
4248 {
4249         switch (tp->mac_version) {
4250         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
4251         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
4252         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
4253         case RTL_GIGA_MAC_VER_37:
4254         case RTL_GIGA_MAC_VER_39:
4255         case RTL_GIGA_MAC_VER_43:
4256                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4257                 break;
4258         case RTL_GIGA_MAC_VER_44:
4259         case RTL_GIGA_MAC_VER_45:
4260         case RTL_GIGA_MAC_VER_46:
4261         case RTL_GIGA_MAC_VER_47:
4262         case RTL_GIGA_MAC_VER_48:
4263         case RTL_GIGA_MAC_VER_50:
4264         case RTL_GIGA_MAC_VER_51:
4265                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4266                 break;
4267         case RTL_GIGA_MAC_VER_40:
4268         case RTL_GIGA_MAC_VER_41:
4269         case RTL_GIGA_MAC_VER_49:
4270                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4271                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4272                              0x00000000, ERIAR_EXGMAC);
4273                 break;
4274         }
4275
4276         phy_resume(tp->dev->phydev);
4277         /* give MAC/PHY some time to resume */
4278         msleep(20);
4279 }
4280
4281 static void rtl_pll_power_down(struct rtl8169_private *tp)
4282 {
4283         switch (tp->mac_version) {
4284         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4285         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4286                 break;
4287         default:
4288                 r8168_pll_power_down(tp);
4289         }
4290 }
4291
4292 static void rtl_pll_power_up(struct rtl8169_private *tp)
4293 {
4294         switch (tp->mac_version) {
4295         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4296         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4297                 break;
4298         default:
4299                 r8168_pll_power_up(tp);
4300         }
4301 }
4302
4303 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4304 {
4305         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4306 }
4307
4308 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4309 {
4310         if (tp->jumbo_ops.enable) {
4311                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4312                 tp->jumbo_ops.enable(tp);
4313                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4314         }
4315 }
4316
4317 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4318 {
4319         if (tp->jumbo_ops.disable) {
4320                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4321                 tp->jumbo_ops.disable(tp);
4322                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4323         }
4324 }
4325
4326 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4327 {
4328         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4329         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4330         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4331 }
4332
4333 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4334 {
4335         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4336         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4337         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4338 }
4339
4340 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4341 {
4342         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4343 }
4344
4345 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4346 {
4347         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4348 }
4349
4350 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4351 {
4352         RTL_W8(tp, MaxTxPacketSize, 0x24);
4353         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4354         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4355         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4356 }
4357
4358 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4359 {
4360         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4361         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4362         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4363         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4364 }
4365
4366 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4367 {
4368         rtl_tx_performance_tweak(tp,
4369                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4370 }
4371
4372 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4373 {
4374         rtl_tx_performance_tweak(tp,
4375                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4376 }
4377
4378 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4379 {
4380         r8168b_0_hw_jumbo_enable(tp);
4381
4382         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4383 }
4384
4385 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4386 {
4387         r8168b_0_hw_jumbo_disable(tp);
4388
4389         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4390 }
4391
4392 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4393 {
4394         struct jumbo_ops *ops = &tp->jumbo_ops;
4395
4396         switch (tp->mac_version) {
4397         case RTL_GIGA_MAC_VER_11:
4398                 ops->disable    = r8168b_0_hw_jumbo_disable;
4399                 ops->enable     = r8168b_0_hw_jumbo_enable;
4400                 break;
4401         case RTL_GIGA_MAC_VER_12:
4402         case RTL_GIGA_MAC_VER_17:
4403                 ops->disable    = r8168b_1_hw_jumbo_disable;
4404                 ops->enable     = r8168b_1_hw_jumbo_enable;
4405                 break;
4406         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4407         case RTL_GIGA_MAC_VER_19:
4408         case RTL_GIGA_MAC_VER_20:
4409         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4410         case RTL_GIGA_MAC_VER_22:
4411         case RTL_GIGA_MAC_VER_23:
4412         case RTL_GIGA_MAC_VER_24:
4413         case RTL_GIGA_MAC_VER_25:
4414         case RTL_GIGA_MAC_VER_26:
4415                 ops->disable    = r8168c_hw_jumbo_disable;
4416                 ops->enable     = r8168c_hw_jumbo_enable;
4417                 break;
4418         case RTL_GIGA_MAC_VER_27:
4419         case RTL_GIGA_MAC_VER_28:
4420                 ops->disable    = r8168dp_hw_jumbo_disable;
4421                 ops->enable     = r8168dp_hw_jumbo_enable;
4422                 break;
4423         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4424         case RTL_GIGA_MAC_VER_32:
4425         case RTL_GIGA_MAC_VER_33:
4426         case RTL_GIGA_MAC_VER_34:
4427                 ops->disable    = r8168e_hw_jumbo_disable;
4428                 ops->enable     = r8168e_hw_jumbo_enable;
4429                 break;
4430
4431         /*
4432          * No action needed for jumbo frames with 8169.
4433          * No jumbo for 810x at all.
4434          */
4435         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4436         default:
4437                 ops->disable    = NULL;
4438                 ops->enable     = NULL;
4439                 break;
4440         }
4441 }
4442
4443 DECLARE_RTL_COND(rtl_chipcmd_cond)
4444 {
4445         return RTL_R8(tp, ChipCmd) & CmdReset;
4446 }
4447
4448 static void rtl_hw_reset(struct rtl8169_private *tp)
4449 {
4450         RTL_W8(tp, ChipCmd, CmdReset);
4451
4452         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4453 }
4454
4455 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4456 {
4457         struct rtl_fw *rtl_fw;
4458         const char *name;
4459         int rc = -ENOMEM;
4460
4461         name = rtl_lookup_firmware_name(tp);
4462         if (!name)
4463                 goto out_no_firmware;
4464
4465         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4466         if (!rtl_fw)
4467                 goto err_warn;
4468
4469         rc = reject_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4470         if (rc < 0)
4471                 goto err_free;
4472
4473         rc = rtl_check_firmware(tp, rtl_fw);
4474         if (rc < 0)
4475                 goto err_release_firmware;
4476
4477         tp->rtl_fw = rtl_fw;
4478 out:
4479         return;
4480
4481 err_release_firmware:
4482         release_firmware(rtl_fw->fw);
4483 err_free:
4484         kfree(rtl_fw);
4485 err_warn:
4486         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4487                    name, rc);
4488 out_no_firmware:
4489         tp->rtl_fw = NULL;
4490         goto out;
4491 }
4492
4493 static void rtl_request_firmware(struct rtl8169_private *tp)
4494 {
4495         if (IS_ERR(tp->rtl_fw))
4496                 rtl_request_uncached_firmware(tp);
4497 }
4498
4499 static void rtl_rx_close(struct rtl8169_private *tp)
4500 {
4501         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4502 }
4503
4504 DECLARE_RTL_COND(rtl_npq_cond)
4505 {
4506         return RTL_R8(tp, TxPoll) & NPQ;
4507 }
4508
4509 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4510 {
4511         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4512 }
4513
4514 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4515 {
4516         /* Disable interrupts */
4517         rtl8169_irq_mask_and_ack(tp);
4518
4519         rtl_rx_close(tp);
4520
4521         switch (tp->mac_version) {
4522         case RTL_GIGA_MAC_VER_27:
4523         case RTL_GIGA_MAC_VER_28:
4524         case RTL_GIGA_MAC_VER_31:
4525                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4526                 break;
4527         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4528         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4529                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4530                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4531                 break;
4532         default:
4533                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4534                 udelay(100);
4535                 break;
4536         }
4537
4538         rtl_hw_reset(tp);
4539 }
4540
4541 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4542 {
4543         u32 val = TX_DMA_BURST << TxDMAShift |
4544                   InterFrameGap << TxInterFrameGapShift;
4545
4546         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4547             tp->mac_version != RTL_GIGA_MAC_VER_39)
4548                 val |= TXCFG_AUTO_FIFO;
4549
4550         RTL_W32(tp, TxConfig, val);
4551 }
4552
4553 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4554 {
4555         /* Low hurts. Let's disable the filtering. */
4556         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4557 }
4558
4559 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4560 {
4561         /*
4562          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4563          * register to be written before TxDescAddrLow to work.
4564          * Switching from MMIO to I/O access fixes the issue as well.
4565          */
4566         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4567         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4568         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4569         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4570 }
4571
4572 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4573 {
4574         static const struct rtl_cfg2_info {
4575                 u32 mac_version;
4576                 u32 clk;
4577                 u32 val;
4578         } cfg2_info [] = {
4579                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4580                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4581                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4582                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4583         };
4584         const struct rtl_cfg2_info *p = cfg2_info;
4585         unsigned int i;
4586         u32 clk;
4587
4588         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4589         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4590                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4591                         RTL_W32(tp, 0x7c, p->val);
4592                         break;
4593                 }
4594         }
4595 }
4596
4597 static void rtl_set_rx_mode(struct net_device *dev)
4598 {
4599         struct rtl8169_private *tp = netdev_priv(dev);
4600         u32 mc_filter[2];       /* Multicast hash filter */
4601         int rx_mode;
4602         u32 tmp = 0;
4603
4604         if (dev->flags & IFF_PROMISC) {
4605                 /* Unconditionally log net taps. */
4606                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4607                 rx_mode =
4608                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4609                     AcceptAllPhys;
4610                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4611         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4612                    (dev->flags & IFF_ALLMULTI)) {
4613                 /* Too many to filter perfectly -- accept all multicasts. */
4614                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4615                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4616         } else {
4617                 struct netdev_hw_addr *ha;
4618
4619                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4620                 mc_filter[1] = mc_filter[0] = 0;
4621                 netdev_for_each_mc_addr(ha, dev) {
4622                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4623                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4624                         rx_mode |= AcceptMulticast;
4625                 }
4626         }
4627
4628         if (dev->features & NETIF_F_RXALL)
4629                 rx_mode |= (AcceptErr | AcceptRunt);
4630
4631         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4632
4633         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4634                 u32 data = mc_filter[0];
4635
4636                 mc_filter[0] = swab32(mc_filter[1]);
4637                 mc_filter[1] = swab32(data);
4638         }
4639
4640         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4641                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4642
4643         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4644         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4645
4646         RTL_W32(tp, RxConfig, tmp);
4647 }
4648
4649 static void rtl_hw_start(struct  rtl8169_private *tp)
4650 {
4651         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4652
4653         tp->hw_start(tp);
4654
4655         rtl_set_rx_max_size(tp);
4656         rtl_set_rx_tx_desc_registers(tp);
4657         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4658
4659         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4660         RTL_R8(tp, IntrMask);
4661         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4662         rtl_init_rxcfg(tp);
4663         rtl_set_tx_config_registers(tp);
4664
4665         rtl_set_rx_mode(tp->dev);
4666         /* no early-rx interrupts */
4667         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4668         rtl_irq_enable_all(tp);
4669 }
4670
4671 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4672 {
4673         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4674                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4675
4676         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4677
4678         tp->cp_cmd |= PCIMulRW;
4679
4680         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4681             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4682                 netif_dbg(tp, drv, tp->dev,
4683                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4684                 tp->cp_cmd |= (1 << 14);
4685         }
4686
4687         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4688
4689         rtl8169_set_magic_reg(tp, tp->mac_version);
4690
4691         /*
4692          * Undocumented corner. Supposedly:
4693          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4694          */
4695         RTL_W16(tp, IntrMitigate, 0x0000);
4696
4697         RTL_W32(tp, RxMissed, 0);
4698 }
4699
4700 DECLARE_RTL_COND(rtl_csiar_cond)
4701 {
4702         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4703 }
4704
4705 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4706 {
4707         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4708
4709         RTL_W32(tp, CSIDR, value);
4710         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4711                 CSIAR_BYTE_ENABLE | func << 16);
4712
4713         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4714 }
4715
4716 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4717 {
4718         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4719
4720         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4721                 CSIAR_BYTE_ENABLE);
4722
4723         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4724                 RTL_R32(tp, CSIDR) : ~0;
4725 }
4726
4727 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4728 {
4729         struct pci_dev *pdev = tp->pci_dev;
4730         u32 csi;
4731
4732         /* According to Realtek the value at config space address 0x070f
4733          * controls the L0s/L1 entrance latency. We try standard ECAM access
4734          * first and if it fails fall back to CSI.
4735          */
4736         if (pdev->cfg_size > 0x070f &&
4737             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4738                 return;
4739
4740         netdev_notice_once(tp->dev,
4741                 "No native access to PCI extended config space, falling back to CSI\n");
4742         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4743         rtl_csi_write(tp, 0x070c, csi | val << 24);
4744 }
4745
4746 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4747 {
4748         rtl_csi_access_enable(tp, 0x27);
4749 }
4750
4751 struct ephy_info {
4752         unsigned int offset;
4753         u16 mask;
4754         u16 bits;
4755 };
4756
4757 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4758                           int len)
4759 {
4760         u16 w;
4761
4762         while (len-- > 0) {
4763                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4764                 rtl_ephy_write(tp, e->offset, w);
4765                 e++;
4766         }
4767 }
4768
4769 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4770 {
4771         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4772                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4773 }
4774
4775 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4776 {
4777         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4778                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4779 }
4780
4781 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4782 {
4783         u8 data;
4784
4785         data = RTL_R8(tp, Config3);
4786
4787         if (enable)
4788                 data |= Rdy_to_L23;
4789         else
4790                 data &= ~Rdy_to_L23;
4791
4792         RTL_W8(tp, Config3, data);
4793 }
4794
4795 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4796 {
4797         if (enable) {
4798                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4799                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4800         } else {
4801                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4802                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4803         }
4804
4805         udelay(10);
4806 }
4807
4808 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4809 {
4810         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4811
4812         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4813         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4814
4815         if (tp->dev->mtu <= ETH_DATA_LEN) {
4816                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4817                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4818         }
4819 }
4820
4821 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4822 {
4823         rtl_hw_start_8168bb(tp);
4824
4825         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4826
4827         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4828 }
4829
4830 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4831 {
4832         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4833
4834         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4835
4836         if (tp->dev->mtu <= ETH_DATA_LEN)
4837                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4838
4839         rtl_disable_clock_request(tp);
4840
4841         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4842         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4843 }
4844
4845 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4846 {
4847         static const struct ephy_info e_info_8168cp[] = {
4848                 { 0x01, 0,      0x0001 },
4849                 { 0x02, 0x0800, 0x1000 },
4850                 { 0x03, 0,      0x0042 },
4851                 { 0x06, 0x0080, 0x0000 },
4852                 { 0x07, 0,      0x2000 }
4853         };
4854
4855         rtl_set_def_aspm_entry_latency(tp);
4856
4857         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4858
4859         __rtl_hw_start_8168cp(tp);
4860 }
4861
4862 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4863 {
4864         rtl_set_def_aspm_entry_latency(tp);
4865
4866         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4867
4868         if (tp->dev->mtu <= ETH_DATA_LEN)
4869                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4870
4871         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4872         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4873 }
4874
4875 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4876 {
4877         rtl_set_def_aspm_entry_latency(tp);
4878
4879         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4880
4881         /* Magic. */
4882         RTL_W8(tp, DBG_REG, 0x20);
4883
4884         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4885
4886         if (tp->dev->mtu <= ETH_DATA_LEN)
4887                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4888
4889         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4890         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4891 }
4892
4893 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4894 {
4895         static const struct ephy_info e_info_8168c_1[] = {
4896                 { 0x02, 0x0800, 0x1000 },
4897                 { 0x03, 0,      0x0002 },
4898                 { 0x06, 0x0080, 0x0000 }
4899         };
4900
4901         rtl_set_def_aspm_entry_latency(tp);
4902
4903         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4904
4905         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4906
4907         __rtl_hw_start_8168cp(tp);
4908 }
4909
4910 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4911 {
4912         static const struct ephy_info e_info_8168c_2[] = {
4913                 { 0x01, 0,      0x0001 },
4914                 { 0x03, 0x0400, 0x0220 }
4915         };
4916
4917         rtl_set_def_aspm_entry_latency(tp);
4918
4919         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4920
4921         __rtl_hw_start_8168cp(tp);
4922 }
4923
4924 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4925 {
4926         rtl_hw_start_8168c_2(tp);
4927 }
4928
4929 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4930 {
4931         rtl_set_def_aspm_entry_latency(tp);
4932
4933         __rtl_hw_start_8168cp(tp);
4934 }
4935
4936 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4937 {
4938         rtl_set_def_aspm_entry_latency(tp);
4939
4940         rtl_disable_clock_request(tp);
4941
4942         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4943
4944         if (tp->dev->mtu <= ETH_DATA_LEN)
4945                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4946
4947         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4948         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4949 }
4950
4951 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4952 {
4953         rtl_set_def_aspm_entry_latency(tp);
4954
4955         if (tp->dev->mtu <= ETH_DATA_LEN)
4956                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4957
4958         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4959
4960         rtl_disable_clock_request(tp);
4961 }
4962
4963 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4964 {
4965         static const struct ephy_info e_info_8168d_4[] = {
4966                 { 0x0b, 0x0000, 0x0048 },
4967                 { 0x19, 0x0020, 0x0050 },
4968                 { 0x0c, 0x0100, 0x0020 }
4969         };
4970
4971         rtl_set_def_aspm_entry_latency(tp);
4972
4973         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4974
4975         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4976
4977         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4978
4979         rtl_enable_clock_request(tp);
4980 }
4981
4982 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4983 {
4984         static const struct ephy_info e_info_8168e_1[] = {
4985                 { 0x00, 0x0200, 0x0100 },
4986                 { 0x00, 0x0000, 0x0004 },
4987                 { 0x06, 0x0002, 0x0001 },
4988                 { 0x06, 0x0000, 0x0030 },
4989                 { 0x07, 0x0000, 0x2000 },
4990                 { 0x00, 0x0000, 0x0020 },
4991                 { 0x03, 0x5800, 0x2000 },
4992                 { 0x03, 0x0000, 0x0001 },
4993                 { 0x01, 0x0800, 0x1000 },
4994                 { 0x07, 0x0000, 0x4000 },
4995                 { 0x1e, 0x0000, 0x2000 },
4996                 { 0x19, 0xffff, 0xfe6c },
4997                 { 0x0a, 0x0000, 0x0040 }
4998         };
4999
5000         rtl_set_def_aspm_entry_latency(tp);
5001
5002         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5003
5004         if (tp->dev->mtu <= ETH_DATA_LEN)
5005                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5006
5007         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5008
5009         rtl_disable_clock_request(tp);
5010
5011         /* Reset tx FIFO pointer */
5012         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5013         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5014
5015         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5016 }
5017
5018 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5019 {
5020         static const struct ephy_info e_info_8168e_2[] = {
5021                 { 0x09, 0x0000, 0x0080 },
5022                 { 0x19, 0x0000, 0x0224 }
5023         };
5024
5025         rtl_set_def_aspm_entry_latency(tp);
5026
5027         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5028
5029         if (tp->dev->mtu <= ETH_DATA_LEN)
5030                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5031
5032         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5033         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5034         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5035         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5036         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5037         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5038         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5039         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5040
5041         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5042
5043         rtl_disable_clock_request(tp);
5044
5045         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5046
5047         /* Adjust EEE LED frequency */
5048         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5049
5050         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5051         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5052         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5053
5054         rtl_hw_aspm_clkreq_enable(tp, true);
5055 }
5056
5057 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5058 {
5059         rtl_set_def_aspm_entry_latency(tp);
5060
5061         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5062
5063         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5064         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5065         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5066         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5067         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5068         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5069         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5070         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5071         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5072         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5073
5074         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5075
5076         rtl_disable_clock_request(tp);
5077
5078         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5079         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5080         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5081         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5082 }
5083
5084 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5085 {
5086         static const struct ephy_info e_info_8168f_1[] = {
5087                 { 0x06, 0x00c0, 0x0020 },
5088                 { 0x08, 0x0001, 0x0002 },
5089                 { 0x09, 0x0000, 0x0080 },
5090                 { 0x19, 0x0000, 0x0224 }
5091         };
5092
5093         rtl_hw_start_8168f(tp);
5094
5095         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5096
5097         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5098
5099         /* Adjust EEE LED frequency */
5100         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5101 }
5102
5103 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5104 {
5105         static const struct ephy_info e_info_8168f_1[] = {
5106                 { 0x06, 0x00c0, 0x0020 },
5107                 { 0x0f, 0xffff, 0x5200 },
5108                 { 0x1e, 0x0000, 0x4000 },
5109                 { 0x19, 0x0000, 0x0224 }
5110         };
5111
5112         rtl_hw_start_8168f(tp);
5113         rtl_pcie_state_l2l3_enable(tp, false);
5114
5115         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5116
5117         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5118 }
5119
5120 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5121 {
5122         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5123         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5124         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5125         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5126
5127         rtl_set_def_aspm_entry_latency(tp);
5128
5129         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5130
5131         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5132         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5133         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5134
5135         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5136         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5137
5138         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5139         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5140
5141         /* Adjust EEE LED frequency */
5142         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5143
5144         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5145         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5146
5147         rtl_pcie_state_l2l3_enable(tp, false);
5148 }
5149
5150 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5151 {
5152         static const struct ephy_info e_info_8168g_1[] = {
5153                 { 0x00, 0x0000, 0x0008 },
5154                 { 0x0c, 0x37d0, 0x0820 },
5155                 { 0x1e, 0x0000, 0x0001 },
5156                 { 0x19, 0x8000, 0x0000 }
5157         };
5158
5159         rtl_hw_start_8168g(tp);
5160
5161         /* disable aspm and clock request before access ephy */
5162         rtl_hw_aspm_clkreq_enable(tp, false);
5163         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5164         rtl_hw_aspm_clkreq_enable(tp, true);
5165 }
5166
5167 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5168 {
5169         static const struct ephy_info e_info_8168g_2[] = {
5170                 { 0x00, 0x0000, 0x0008 },
5171                 { 0x0c, 0x3df0, 0x0200 },
5172                 { 0x19, 0xffff, 0xfc00 },
5173                 { 0x1e, 0xffff, 0x20eb }
5174         };
5175
5176         rtl_hw_start_8168g(tp);
5177
5178         /* disable aspm and clock request before access ephy */
5179         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5180         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5181         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5182 }
5183
5184 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5185 {
5186         static const struct ephy_info e_info_8411_2[] = {
5187                 { 0x00, 0x0000, 0x0008 },
5188                 { 0x0c, 0x3df0, 0x0200 },
5189                 { 0x0f, 0xffff, 0x5200 },
5190                 { 0x19, 0x0020, 0x0000 },
5191                 { 0x1e, 0x0000, 0x2000 }
5192         };
5193
5194         rtl_hw_start_8168g(tp);
5195
5196         /* disable aspm and clock request before access ephy */
5197         rtl_hw_aspm_clkreq_enable(tp, false);
5198         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5199
5200         /* The following Realtek-provided magic fixes an issue with the RX unit
5201          * getting confused after the PHY having been powered-down.
5202          */
5203         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
5204         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
5205         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
5206         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
5207         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
5208         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
5209         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
5210         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
5211         mdelay(3);
5212         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
5213
5214         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
5215         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
5216         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
5217         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
5218         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
5219         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
5220         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
5221         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
5222         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
5223         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
5224         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
5225         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
5226         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
5227         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
5228         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
5229         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
5230         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
5231         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
5232         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
5233         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
5234         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
5235         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
5236         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
5237         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
5238         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
5239         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
5240         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
5241         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
5242         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
5243         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
5244         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
5245         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
5246         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
5247         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
5248         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
5249         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
5250         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
5251         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
5252         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
5253         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
5254         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
5255         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
5256         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
5257         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
5258         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
5259         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
5260         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
5261         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
5262         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
5263         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
5264         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
5265         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
5266         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
5267         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
5268         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
5269         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
5270         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
5271         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
5272         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
5273         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
5274         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
5275         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
5276         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
5277         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
5278         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
5279         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
5280         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
5281         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
5282         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
5283         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
5284         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
5285         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
5286         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
5287         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
5288         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
5289         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
5290         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
5291         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
5292         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
5293         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
5294         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
5295         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
5296         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
5297         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
5298         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
5299         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
5300         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
5301         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
5302         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
5303         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
5304         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
5305         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
5306         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
5307         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
5308         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
5309         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
5310         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
5311         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
5312         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
5313         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
5314         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
5315         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
5316         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
5317         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
5318         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
5319         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
5320         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
5321         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
5322         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
5323         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
5324         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
5325
5326         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
5327
5328         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
5329         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
5330         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
5331         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
5332         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
5333         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
5334         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
5335
5336         rtl_hw_aspm_clkreq_enable(tp, true);
5337 }
5338
5339 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5340 {
5341         int rg_saw_cnt;
5342         u32 data;
5343         static const struct ephy_info e_info_8168h_1[] = {
5344                 { 0x1e, 0x0800, 0x0001 },
5345                 { 0x1d, 0x0000, 0x0800 },
5346                 { 0x05, 0xffff, 0x2089 },
5347                 { 0x06, 0xffff, 0x5881 },
5348                 { 0x04, 0xffff, 0x154a },
5349                 { 0x01, 0xffff, 0x068b }
5350         };
5351
5352         /* disable aspm and clock request before access ephy */
5353         rtl_hw_aspm_clkreq_enable(tp, false);
5354         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5355
5356         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5357         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5358         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5359         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5360
5361         rtl_set_def_aspm_entry_latency(tp);
5362
5363         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5364
5365         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5366         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5367
5368         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5369
5370         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5371
5372         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5373
5374         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5375         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5376
5377         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5378         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5379
5380         /* Adjust EEE LED frequency */
5381         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5382
5383         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5384         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5385
5386         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5387
5388         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5389
5390         rtl_pcie_state_l2l3_enable(tp, false);
5391
5392         rtl_writephy(tp, 0x1f, 0x0c42);
5393         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5394         rtl_writephy(tp, 0x1f, 0x0000);
5395         if (rg_saw_cnt > 0) {
5396                 u16 sw_cnt_1ms_ini;
5397
5398                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5399                 sw_cnt_1ms_ini &= 0x0fff;
5400                 data = r8168_mac_ocp_read(tp, 0xd412);
5401                 data &= ~0x0fff;
5402                 data |= sw_cnt_1ms_ini;
5403                 r8168_mac_ocp_write(tp, 0xd412, data);
5404         }
5405
5406         data = r8168_mac_ocp_read(tp, 0xe056);
5407         data &= ~0xf0;
5408         data |= 0x70;
5409         r8168_mac_ocp_write(tp, 0xe056, data);
5410
5411         data = r8168_mac_ocp_read(tp, 0xe052);
5412         data &= ~0x6000;
5413         data |= 0x8008;
5414         r8168_mac_ocp_write(tp, 0xe052, data);
5415
5416         data = r8168_mac_ocp_read(tp, 0xe0d6);
5417         data &= ~0x01ff;
5418         data |= 0x017f;
5419         r8168_mac_ocp_write(tp, 0xe0d6, data);
5420
5421         data = r8168_mac_ocp_read(tp, 0xd420);
5422         data &= ~0x0fff;
5423         data |= 0x047f;
5424         r8168_mac_ocp_write(tp, 0xd420, data);
5425
5426         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5427         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5428         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5429         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5430
5431         rtl_hw_aspm_clkreq_enable(tp, true);
5432 }
5433
5434 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5435 {
5436         rtl8168ep_stop_cmac(tp);
5437
5438         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5439         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5440         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5441         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5442
5443         rtl_set_def_aspm_entry_latency(tp);
5444
5445         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5446
5447         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5448         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5449
5450         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5451
5452         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5453
5454         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5455         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5456
5457         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5458         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5459
5460         /* Adjust EEE LED frequency */
5461         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5462
5463         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5464
5465         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5466
5467         rtl_pcie_state_l2l3_enable(tp, false);
5468 }
5469
5470 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5471 {
5472         static const struct ephy_info e_info_8168ep_1[] = {
5473                 { 0x00, 0xffff, 0x10ab },
5474                 { 0x06, 0xffff, 0xf030 },
5475                 { 0x08, 0xffff, 0x2006 },
5476                 { 0x0d, 0xffff, 0x1666 },
5477                 { 0x0c, 0x3ff0, 0x0000 }
5478         };
5479
5480         /* disable aspm and clock request before access ephy */
5481         rtl_hw_aspm_clkreq_enable(tp, false);
5482         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5483
5484         rtl_hw_start_8168ep(tp);
5485
5486         rtl_hw_aspm_clkreq_enable(tp, true);
5487 }
5488
5489 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5490 {
5491         static const struct ephy_info e_info_8168ep_2[] = {
5492                 { 0x00, 0xffff, 0x10a3 },
5493                 { 0x19, 0xffff, 0xfc00 },
5494                 { 0x1e, 0xffff, 0x20ea }
5495         };
5496
5497         /* disable aspm and clock request before access ephy */
5498         rtl_hw_aspm_clkreq_enable(tp, false);
5499         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5500
5501         rtl_hw_start_8168ep(tp);
5502
5503         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5504         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5505
5506         rtl_hw_aspm_clkreq_enable(tp, true);
5507 }
5508
5509 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5510 {
5511         u32 data;
5512         static const struct ephy_info e_info_8168ep_3[] = {
5513                 { 0x00, 0xffff, 0x10a3 },
5514                 { 0x19, 0xffff, 0x7c00 },
5515                 { 0x1e, 0xffff, 0x20eb },
5516                 { 0x0d, 0xffff, 0x1666 }
5517         };
5518
5519         /* disable aspm and clock request before access ephy */
5520         rtl_hw_aspm_clkreq_enable(tp, false);
5521         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5522
5523         rtl_hw_start_8168ep(tp);
5524
5525         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5526         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5527
5528         data = r8168_mac_ocp_read(tp, 0xd3e2);
5529         data &= 0xf000;
5530         data |= 0x0271;
5531         r8168_mac_ocp_write(tp, 0xd3e2, data);
5532
5533         data = r8168_mac_ocp_read(tp, 0xd3e4);
5534         data &= 0xff00;
5535         r8168_mac_ocp_write(tp, 0xd3e4, data);
5536
5537         data = r8168_mac_ocp_read(tp, 0xe860);
5538         data |= 0x0080;
5539         r8168_mac_ocp_write(tp, 0xe860, data);
5540
5541         rtl_hw_aspm_clkreq_enable(tp, true);
5542 }
5543
5544 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5545 {
5546         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5547
5548         tp->cp_cmd &= ~INTT_MASK;
5549         tp->cp_cmd |= PktCntrDisable | INTT_1;
5550         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5551
5552         RTL_W16(tp, IntrMitigate, 0x5100);
5553
5554         /* Work around for RxFIFO overflow. */
5555         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5556                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5557                 tp->event_slow &= ~RxOverflow;
5558         }
5559
5560         switch (tp->mac_version) {
5561         case RTL_GIGA_MAC_VER_11:
5562                 rtl_hw_start_8168bb(tp);
5563                 break;
5564
5565         case RTL_GIGA_MAC_VER_12:
5566         case RTL_GIGA_MAC_VER_17:
5567                 rtl_hw_start_8168bef(tp);
5568                 break;
5569
5570         case RTL_GIGA_MAC_VER_18:
5571                 rtl_hw_start_8168cp_1(tp);
5572                 break;
5573
5574         case RTL_GIGA_MAC_VER_19:
5575                 rtl_hw_start_8168c_1(tp);
5576                 break;
5577
5578         case RTL_GIGA_MAC_VER_20:
5579                 rtl_hw_start_8168c_2(tp);
5580                 break;
5581
5582         case RTL_GIGA_MAC_VER_21:
5583                 rtl_hw_start_8168c_3(tp);
5584                 break;
5585
5586         case RTL_GIGA_MAC_VER_22:
5587                 rtl_hw_start_8168c_4(tp);
5588                 break;
5589
5590         case RTL_GIGA_MAC_VER_23:
5591                 rtl_hw_start_8168cp_2(tp);
5592                 break;
5593
5594         case RTL_GIGA_MAC_VER_24:
5595                 rtl_hw_start_8168cp_3(tp);
5596                 break;
5597
5598         case RTL_GIGA_MAC_VER_25:
5599         case RTL_GIGA_MAC_VER_26:
5600         case RTL_GIGA_MAC_VER_27:
5601                 rtl_hw_start_8168d(tp);
5602                 break;
5603
5604         case RTL_GIGA_MAC_VER_28:
5605                 rtl_hw_start_8168d_4(tp);
5606                 break;
5607
5608         case RTL_GIGA_MAC_VER_31:
5609                 rtl_hw_start_8168dp(tp);
5610                 break;
5611
5612         case RTL_GIGA_MAC_VER_32:
5613         case RTL_GIGA_MAC_VER_33:
5614                 rtl_hw_start_8168e_1(tp);
5615                 break;
5616         case RTL_GIGA_MAC_VER_34:
5617                 rtl_hw_start_8168e_2(tp);
5618                 break;
5619
5620         case RTL_GIGA_MAC_VER_35:
5621         case RTL_GIGA_MAC_VER_36:
5622                 rtl_hw_start_8168f_1(tp);
5623                 break;
5624
5625         case RTL_GIGA_MAC_VER_38:
5626                 rtl_hw_start_8411(tp);
5627                 break;
5628
5629         case RTL_GIGA_MAC_VER_40:
5630         case RTL_GIGA_MAC_VER_41:
5631                 rtl_hw_start_8168g_1(tp);
5632                 break;
5633         case RTL_GIGA_MAC_VER_42:
5634                 rtl_hw_start_8168g_2(tp);
5635                 break;
5636
5637         case RTL_GIGA_MAC_VER_44:
5638                 rtl_hw_start_8411_2(tp);
5639                 break;
5640
5641         case RTL_GIGA_MAC_VER_45:
5642         case RTL_GIGA_MAC_VER_46:
5643                 rtl_hw_start_8168h_1(tp);
5644                 break;
5645
5646         case RTL_GIGA_MAC_VER_49:
5647                 rtl_hw_start_8168ep_1(tp);
5648                 break;
5649
5650         case RTL_GIGA_MAC_VER_50:
5651                 rtl_hw_start_8168ep_2(tp);
5652                 break;
5653
5654         case RTL_GIGA_MAC_VER_51:
5655                 rtl_hw_start_8168ep_3(tp);
5656                 break;
5657
5658         default:
5659                 netif_err(tp, drv, tp->dev,
5660                           "unknown chipset (mac_version = %d)\n",
5661                           tp->mac_version);
5662                 break;
5663         }
5664 }
5665
5666 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5667 {
5668         static const struct ephy_info e_info_8102e_1[] = {
5669                 { 0x01, 0, 0x6e65 },
5670                 { 0x02, 0, 0x091f },
5671                 { 0x03, 0, 0xc2f9 },
5672                 { 0x06, 0, 0xafb5 },
5673                 { 0x07, 0, 0x0e00 },
5674                 { 0x19, 0, 0xec80 },
5675                 { 0x01, 0, 0x2e65 },
5676                 { 0x01, 0, 0x6e65 }
5677         };
5678         u8 cfg1;
5679
5680         rtl_set_def_aspm_entry_latency(tp);
5681
5682         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5683
5684         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5685
5686         RTL_W8(tp, Config1,
5687                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5688         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5689
5690         cfg1 = RTL_R8(tp, Config1);
5691         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5692                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5693
5694         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5695 }
5696
5697 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5698 {
5699         rtl_set_def_aspm_entry_latency(tp);
5700
5701         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5702
5703         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5704         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5705 }
5706
5707 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5708 {
5709         rtl_hw_start_8102e_2(tp);
5710
5711         rtl_ephy_write(tp, 0x03, 0xc2f9);
5712 }
5713
5714 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5715 {
5716         static const struct ephy_info e_info_8105e_1[] = {
5717                 { 0x07, 0, 0x4000 },
5718                 { 0x19, 0, 0x0200 },
5719                 { 0x19, 0, 0x0020 },
5720                 { 0x1e, 0, 0x2000 },
5721                 { 0x03, 0, 0x0001 },
5722                 { 0x19, 0, 0x0100 },
5723                 { 0x19, 0, 0x0004 },
5724                 { 0x0a, 0, 0x0020 }
5725         };
5726
5727         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5728         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5729
5730         /* Disable Early Tally Counter */
5731         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5732
5733         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5734         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5735
5736         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5737
5738         rtl_pcie_state_l2l3_enable(tp, false);
5739 }
5740
5741 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5742 {
5743         rtl_hw_start_8105e_1(tp);
5744         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5745 }
5746
5747 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5748 {
5749         static const struct ephy_info e_info_8402[] = {
5750                 { 0x19, 0xffff, 0xff64 },
5751                 { 0x1e, 0, 0x4000 }
5752         };
5753
5754         rtl_set_def_aspm_entry_latency(tp);
5755
5756         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5757         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5758
5759         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5760
5761         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5762
5763         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5764
5765         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5766         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5767         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5768         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5769         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5770         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5771         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5772
5773         rtl_pcie_state_l2l3_enable(tp, false);
5774 }
5775
5776 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5777 {
5778         rtl_hw_aspm_clkreq_enable(tp, false);
5779
5780         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5781         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5782
5783         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5784         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5785         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5786
5787         rtl_pcie_state_l2l3_enable(tp, false);
5788         rtl_hw_aspm_clkreq_enable(tp, true);
5789 }
5790
5791 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5792 {
5793         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5794                 tp->event_slow &= ~RxFIFOOver;
5795
5796         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5797             tp->mac_version == RTL_GIGA_MAC_VER_16)
5798                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5799                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5800
5801         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5802
5803         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5804         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5805
5806         switch (tp->mac_version) {
5807         case RTL_GIGA_MAC_VER_07:
5808                 rtl_hw_start_8102e_1(tp);
5809                 break;
5810
5811         case RTL_GIGA_MAC_VER_08:
5812                 rtl_hw_start_8102e_3(tp);
5813                 break;
5814
5815         case RTL_GIGA_MAC_VER_09:
5816                 rtl_hw_start_8102e_2(tp);
5817                 break;
5818
5819         case RTL_GIGA_MAC_VER_29:
5820                 rtl_hw_start_8105e_1(tp);
5821                 break;
5822         case RTL_GIGA_MAC_VER_30:
5823                 rtl_hw_start_8105e_2(tp);
5824                 break;
5825
5826         case RTL_GIGA_MAC_VER_37:
5827                 rtl_hw_start_8402(tp);
5828                 break;
5829
5830         case RTL_GIGA_MAC_VER_39:
5831                 rtl_hw_start_8106(tp);
5832                 break;
5833         case RTL_GIGA_MAC_VER_43:
5834                 rtl_hw_start_8168g_2(tp);
5835                 break;
5836         case RTL_GIGA_MAC_VER_47:
5837         case RTL_GIGA_MAC_VER_48:
5838                 rtl_hw_start_8168h_1(tp);
5839                 break;
5840         }
5841
5842         RTL_W16(tp, IntrMitigate, 0x0000);
5843 }
5844
5845 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5846 {
5847         struct rtl8169_private *tp = netdev_priv(dev);
5848
5849         if (new_mtu > ETH_DATA_LEN)
5850                 rtl_hw_jumbo_enable(tp);
5851         else
5852                 rtl_hw_jumbo_disable(tp);
5853
5854         dev->mtu = new_mtu;
5855         netdev_update_features(dev);
5856
5857         return 0;
5858 }
5859
5860 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5861 {
5862         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5863         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5864 }
5865
5866 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5867                                      void **data_buff, struct RxDesc *desc)
5868 {
5869         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5870                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5871
5872         kfree(*data_buff);
5873         *data_buff = NULL;
5874         rtl8169_make_unusable_by_asic(desc);
5875 }
5876
5877 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5878 {
5879         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5880
5881         /* Force memory writes to complete before releasing descriptor */
5882         dma_wmb();
5883
5884         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5885 }
5886
5887 static inline void *rtl8169_align(void *data)
5888 {
5889         return (void *)ALIGN((long)data, 16);
5890 }
5891
5892 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5893                                              struct RxDesc *desc)
5894 {
5895         void *data;
5896         dma_addr_t mapping;
5897         struct device *d = tp_to_dev(tp);
5898         int node = dev_to_node(d);
5899
5900         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5901         if (!data)
5902                 return NULL;
5903
5904         if (rtl8169_align(data) != data) {
5905                 kfree(data);
5906                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5907                 if (!data)
5908                         return NULL;
5909         }
5910
5911         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5912                                  DMA_FROM_DEVICE);
5913         if (unlikely(dma_mapping_error(d, mapping))) {
5914                 if (net_ratelimit())
5915                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5916                 goto err_out;
5917         }
5918
5919         desc->addr = cpu_to_le64(mapping);
5920         rtl8169_mark_to_asic(desc);
5921         return data;
5922
5923 err_out:
5924         kfree(data);
5925         return NULL;
5926 }
5927
5928 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5929 {
5930         unsigned int i;
5931
5932         for (i = 0; i < NUM_RX_DESC; i++) {
5933                 if (tp->Rx_databuff[i]) {
5934                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5935                                             tp->RxDescArray + i);
5936                 }
5937         }
5938 }
5939
5940 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5941 {
5942         desc->opts1 |= cpu_to_le32(RingEnd);
5943 }
5944
5945 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5946 {
5947         unsigned int i;
5948
5949         for (i = 0; i < NUM_RX_DESC; i++) {
5950                 void *data;
5951
5952                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5953                 if (!data) {
5954                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5955                         goto err_out;
5956                 }
5957                 tp->Rx_databuff[i] = data;
5958         }
5959
5960         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5961         return 0;
5962
5963 err_out:
5964         rtl8169_rx_clear(tp);
5965         return -ENOMEM;
5966 }
5967
5968 static int rtl8169_init_ring(struct rtl8169_private *tp)
5969 {
5970         rtl8169_init_ring_indexes(tp);
5971
5972         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5973         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5974
5975         return rtl8169_rx_fill(tp);
5976 }
5977
5978 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5979                                  struct TxDesc *desc)
5980 {
5981         unsigned int len = tx_skb->len;
5982
5983         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5984
5985         desc->opts1 = 0x00;
5986         desc->opts2 = 0x00;
5987         desc->addr = 0x00;
5988         tx_skb->len = 0;
5989 }
5990
5991 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5992                                    unsigned int n)
5993 {
5994         unsigned int i;
5995
5996         for (i = 0; i < n; i++) {
5997                 unsigned int entry = (start + i) % NUM_TX_DESC;
5998                 struct ring_info *tx_skb = tp->tx_skb + entry;
5999                 unsigned int len = tx_skb->len;
6000
6001                 if (len) {
6002                         struct sk_buff *skb = tx_skb->skb;
6003
6004                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6005                                              tp->TxDescArray + entry);
6006                         if (skb) {
6007                                 dev_consume_skb_any(skb);
6008                                 tx_skb->skb = NULL;
6009                         }
6010                 }
6011         }
6012 }
6013
6014 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6015 {
6016         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6017         tp->cur_tx = tp->dirty_tx = 0;
6018 }
6019
6020 static void rtl_reset_work(struct rtl8169_private *tp)
6021 {
6022         struct net_device *dev = tp->dev;
6023         int i;
6024
6025         napi_disable(&tp->napi);
6026         netif_stop_queue(dev);
6027         synchronize_sched();
6028
6029         rtl8169_hw_reset(tp);
6030
6031         for (i = 0; i < NUM_RX_DESC; i++)
6032                 rtl8169_mark_to_asic(tp->RxDescArray + i);
6033
6034         rtl8169_tx_clear(tp);
6035         rtl8169_init_ring_indexes(tp);
6036
6037         napi_enable(&tp->napi);
6038         rtl_hw_start(tp);
6039         netif_wake_queue(dev);
6040 }
6041
6042 static void rtl8169_tx_timeout(struct net_device *dev)
6043 {
6044         struct rtl8169_private *tp = netdev_priv(dev);
6045
6046         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6047 }
6048
6049 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6050                               u32 *opts)
6051 {
6052         struct skb_shared_info *info = skb_shinfo(skb);
6053         unsigned int cur_frag, entry;
6054         struct TxDesc *uninitialized_var(txd);
6055         struct device *d = tp_to_dev(tp);
6056
6057         entry = tp->cur_tx;
6058         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6059                 const skb_frag_t *frag = info->frags + cur_frag;
6060                 dma_addr_t mapping;
6061                 u32 status, len;
6062                 void *addr;
6063
6064                 entry = (entry + 1) % NUM_TX_DESC;
6065
6066                 txd = tp->TxDescArray + entry;
6067                 len = skb_frag_size(frag);
6068                 addr = skb_frag_address(frag);
6069                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6070                 if (unlikely(dma_mapping_error(d, mapping))) {
6071                         if (net_ratelimit())
6072                                 netif_err(tp, drv, tp->dev,
6073                                           "Failed to map TX fragments DMA!\n");
6074                         goto err_out;
6075                 }
6076
6077                 /* Anti gcc 2.95.3 bugware (sic) */
6078                 status = opts[0] | len |
6079                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6080
6081                 txd->opts1 = cpu_to_le32(status);
6082                 txd->opts2 = cpu_to_le32(opts[1]);
6083                 txd->addr = cpu_to_le64(mapping);
6084
6085                 tp->tx_skb[entry].len = len;
6086         }
6087
6088         if (cur_frag) {
6089                 tp->tx_skb[entry].skb = skb;
6090                 txd->opts1 |= cpu_to_le32(LastFrag);
6091         }
6092
6093         return cur_frag;
6094
6095 err_out:
6096         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6097         return -EIO;
6098 }
6099
6100 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6101 {
6102         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6103 }
6104
6105 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6106                                       struct net_device *dev);
6107 /* r8169_csum_workaround()
6108  * The hw limites the value the transport offset. When the offset is out of the
6109  * range, calculate the checksum by sw.
6110  */
6111 static void r8169_csum_workaround(struct rtl8169_private *tp,
6112                                   struct sk_buff *skb)
6113 {
6114         if (skb_shinfo(skb)->gso_size) {
6115                 netdev_features_t features = tp->dev->features;
6116                 struct sk_buff *segs, *nskb;
6117
6118                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6119                 segs = skb_gso_segment(skb, features);
6120                 if (IS_ERR(segs) || !segs)
6121                         goto drop;
6122
6123                 do {
6124                         nskb = segs;
6125                         segs = segs->next;
6126                         nskb->next = NULL;
6127                         rtl8169_start_xmit(nskb, tp->dev);
6128                 } while (segs);
6129
6130                 dev_consume_skb_any(skb);
6131         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6132                 if (skb_checksum_help(skb) < 0)
6133                         goto drop;
6134
6135                 rtl8169_start_xmit(skb, tp->dev);
6136         } else {
6137                 struct net_device_stats *stats;
6138
6139 drop:
6140                 stats = &tp->dev->stats;
6141                 stats->tx_dropped++;
6142                 dev_kfree_skb_any(skb);
6143         }
6144 }
6145
6146 /* msdn_giant_send_check()
6147  * According to the document of microsoft, the TCP Pseudo Header excludes the
6148  * packet length for IPv6 TCP large packets.
6149  */
6150 static int msdn_giant_send_check(struct sk_buff *skb)
6151 {
6152         const struct ipv6hdr *ipv6h;
6153         struct tcphdr *th;
6154         int ret;
6155
6156         ret = skb_cow_head(skb, 0);
6157         if (ret)
6158                 return ret;
6159
6160         ipv6h = ipv6_hdr(skb);
6161         th = tcp_hdr(skb);
6162
6163         th->check = 0;
6164         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6165
6166         return ret;
6167 }
6168
6169 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6170                                 struct sk_buff *skb, u32 *opts)
6171 {
6172         u32 mss = skb_shinfo(skb)->gso_size;
6173
6174         if (mss) {
6175                 opts[0] |= TD_LSO;
6176                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6177         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6178                 const struct iphdr *ip = ip_hdr(skb);
6179
6180                 if (ip->protocol == IPPROTO_TCP)
6181                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6182                 else if (ip->protocol == IPPROTO_UDP)
6183                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6184                 else
6185                         WARN_ON_ONCE(1);
6186         }
6187
6188         return true;
6189 }
6190
6191 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6192                                 struct sk_buff *skb, u32 *opts)
6193 {
6194         u32 transport_offset = (u32)skb_transport_offset(skb);
6195         u32 mss = skb_shinfo(skb)->gso_size;
6196
6197         if (mss) {
6198                 if (transport_offset > GTTCPHO_MAX) {
6199                         netif_warn(tp, tx_err, tp->dev,
6200                                    "Invalid transport offset 0x%x for TSO\n",
6201                                    transport_offset);
6202                         return false;
6203                 }
6204
6205                 switch (vlan_get_protocol(skb)) {
6206                 case htons(ETH_P_IP):
6207                         opts[0] |= TD1_GTSENV4;
6208                         break;
6209
6210                 case htons(ETH_P_IPV6):
6211                         if (msdn_giant_send_check(skb))
6212                                 return false;
6213
6214                         opts[0] |= TD1_GTSENV6;
6215                         break;
6216
6217                 default:
6218                         WARN_ON_ONCE(1);
6219                         break;
6220                 }
6221
6222                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6223                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6224         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6225                 u8 ip_protocol;
6226
6227                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6228                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6229
6230                 if (transport_offset > TCPHO_MAX) {
6231                         netif_warn(tp, tx_err, tp->dev,
6232                                    "Invalid transport offset 0x%x\n",
6233                                    transport_offset);
6234                         return false;
6235                 }
6236
6237                 switch (vlan_get_protocol(skb)) {
6238                 case htons(ETH_P_IP):
6239                         opts[1] |= TD1_IPv4_CS;
6240                         ip_protocol = ip_hdr(skb)->protocol;
6241                         break;
6242
6243                 case htons(ETH_P_IPV6):
6244                         opts[1] |= TD1_IPv6_CS;
6245                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6246                         break;
6247
6248                 default:
6249                         ip_protocol = IPPROTO_RAW;
6250                         break;
6251                 }
6252
6253                 if (ip_protocol == IPPROTO_TCP)
6254                         opts[1] |= TD1_TCP_CS;
6255                 else if (ip_protocol == IPPROTO_UDP)
6256                         opts[1] |= TD1_UDP_CS;
6257                 else
6258                         WARN_ON_ONCE(1);
6259
6260                 opts[1] |= transport_offset << TCPHO_SHIFT;
6261         } else {
6262                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6263                         /* eth_skb_pad would free the skb on error */
6264                         return !__skb_put_padto(skb, ETH_ZLEN, false);
6265         }
6266
6267         return true;
6268 }
6269
6270 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6271                                       struct net_device *dev)
6272 {
6273         struct rtl8169_private *tp = netdev_priv(dev);
6274         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6275         struct TxDesc *txd = tp->TxDescArray + entry;
6276         struct device *d = tp_to_dev(tp);
6277         dma_addr_t mapping;
6278         u32 status, len;
6279         u32 opts[2];
6280         int frags;
6281
6282         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6283                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6284                 goto err_stop_0;
6285         }
6286
6287         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6288                 goto err_stop_0;
6289
6290         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6291         opts[0] = DescOwn;
6292
6293         if (!tp->tso_csum(tp, skb, opts)) {
6294                 r8169_csum_workaround(tp, skb);
6295                 return NETDEV_TX_OK;
6296         }
6297
6298         len = skb_headlen(skb);
6299         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6300         if (unlikely(dma_mapping_error(d, mapping))) {
6301                 if (net_ratelimit())
6302                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6303                 goto err_dma_0;
6304         }
6305
6306         tp->tx_skb[entry].len = len;
6307         txd->addr = cpu_to_le64(mapping);
6308
6309         frags = rtl8169_xmit_frags(tp, skb, opts);
6310         if (frags < 0)
6311                 goto err_dma_1;
6312         else if (frags)
6313                 opts[0] |= FirstFrag;
6314         else {
6315                 opts[0] |= FirstFrag | LastFrag;
6316                 tp->tx_skb[entry].skb = skb;
6317         }
6318
6319         txd->opts2 = cpu_to_le32(opts[1]);
6320
6321         skb_tx_timestamp(skb);
6322
6323         /* Force memory writes to complete before releasing descriptor */
6324         dma_wmb();
6325
6326         /* Anti gcc 2.95.3 bugware (sic) */
6327         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6328         txd->opts1 = cpu_to_le32(status);
6329
6330         /* Force all memory writes to complete before notifying device */
6331         wmb();
6332
6333         tp->cur_tx += frags + 1;
6334
6335         RTL_W8(tp, TxPoll, NPQ);
6336
6337         mmiowb();
6338
6339         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6340                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6341                  * not miss a ring update when it notices a stopped queue.
6342                  */
6343                 smp_wmb();
6344                 netif_stop_queue(dev);
6345                 /* Sync with rtl_tx:
6346                  * - publish queue status and cur_tx ring index (write barrier)
6347                  * - refresh dirty_tx ring index (read barrier).
6348                  * May the current thread have a pessimistic view of the ring
6349                  * status and forget to wake up queue, a racing rtl_tx thread
6350                  * can't.
6351                  */
6352                 smp_mb();
6353                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6354                         netif_wake_queue(dev);
6355         }
6356
6357         return NETDEV_TX_OK;
6358
6359 err_dma_1:
6360         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6361 err_dma_0:
6362         dev_kfree_skb_any(skb);
6363         dev->stats.tx_dropped++;
6364         return NETDEV_TX_OK;
6365
6366 err_stop_0:
6367         netif_stop_queue(dev);
6368         dev->stats.tx_dropped++;
6369         return NETDEV_TX_BUSY;
6370 }
6371
6372 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6373 {
6374         struct rtl8169_private *tp = netdev_priv(dev);
6375         struct pci_dev *pdev = tp->pci_dev;
6376         u16 pci_status, pci_cmd;
6377
6378         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6379         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6380
6381         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6382                   pci_cmd, pci_status);
6383
6384         /*
6385          * The recovery sequence below admits a very elaborated explanation:
6386          * - it seems to work;
6387          * - I did not see what else could be done;
6388          * - it makes iop3xx happy.
6389          *
6390          * Feel free to adjust to your needs.
6391          */
6392         if (pdev->broken_parity_status)
6393                 pci_cmd &= ~PCI_COMMAND_PARITY;
6394         else
6395                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6396
6397         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6398
6399         pci_write_config_word(pdev, PCI_STATUS,
6400                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6401                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6402                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6403
6404         /* The infamous DAC f*ckup only happens at boot time */
6405         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6406                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6407                 tp->cp_cmd &= ~PCIDAC;
6408                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6409                 dev->features &= ~NETIF_F_HIGHDMA;
6410         }
6411
6412         rtl8169_hw_reset(tp);
6413
6414         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6415 }
6416
6417 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6418 {
6419         unsigned int dirty_tx, tx_left;
6420
6421         dirty_tx = tp->dirty_tx;
6422         smp_rmb();
6423         tx_left = tp->cur_tx - dirty_tx;
6424
6425         while (tx_left > 0) {
6426                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6427                 struct ring_info *tx_skb = tp->tx_skb + entry;
6428                 u32 status;
6429
6430                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6431                 if (status & DescOwn)
6432                         break;
6433
6434                 /* This barrier is needed to keep us from reading
6435                  * any other fields out of the Tx descriptor until
6436                  * we know the status of DescOwn
6437                  */
6438                 dma_rmb();
6439
6440                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6441                                      tp->TxDescArray + entry);
6442                 if (status & LastFrag) {
6443                         u64_stats_update_begin(&tp->tx_stats.syncp);
6444                         tp->tx_stats.packets++;
6445                         tp->tx_stats.bytes += tx_skb->skb->len;
6446                         u64_stats_update_end(&tp->tx_stats.syncp);
6447                         dev_consume_skb_any(tx_skb->skb);
6448                         tx_skb->skb = NULL;
6449                 }
6450                 dirty_tx++;
6451                 tx_left--;
6452         }
6453
6454         if (tp->dirty_tx != dirty_tx) {
6455                 tp->dirty_tx = dirty_tx;
6456                 /* Sync with rtl8169_start_xmit:
6457                  * - publish dirty_tx ring index (write barrier)
6458                  * - refresh cur_tx ring index and queue status (read barrier)
6459                  * May the current thread miss the stopped queue condition,
6460                  * a racing xmit thread can only have a right view of the
6461                  * ring status.
6462                  */
6463                 smp_mb();
6464                 if (netif_queue_stopped(dev) &&
6465                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6466                         netif_wake_queue(dev);
6467                 }
6468                 /*
6469                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6470                  * too close. Let's kick an extra TxPoll request when a burst
6471                  * of start_xmit activity is detected (if it is not detected,
6472                  * it is slow enough). -- FR
6473                  */
6474                 if (tp->cur_tx != dirty_tx)
6475                         RTL_W8(tp, TxPoll, NPQ);
6476         }
6477 }
6478
6479 static inline int rtl8169_fragmented_frame(u32 status)
6480 {
6481         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6482 }
6483
6484 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6485 {
6486         u32 status = opts1 & RxProtoMask;
6487
6488         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6489             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6490                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6491         else
6492                 skb_checksum_none_assert(skb);
6493 }
6494
6495 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6496                                            struct rtl8169_private *tp,
6497                                            int pkt_size,
6498                                            dma_addr_t addr)
6499 {
6500         struct sk_buff *skb;
6501         struct device *d = tp_to_dev(tp);
6502
6503         data = rtl8169_align(data);
6504         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6505         prefetch(data);
6506         skb = napi_alloc_skb(&tp->napi, pkt_size);
6507         if (skb)
6508                 skb_copy_to_linear_data(skb, data, pkt_size);
6509         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6510
6511         return skb;
6512 }
6513
6514 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6515 {
6516         unsigned int cur_rx, rx_left;
6517         unsigned int count;
6518
6519         cur_rx = tp->cur_rx;
6520
6521         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6522                 unsigned int entry = cur_rx % NUM_RX_DESC;
6523                 struct RxDesc *desc = tp->RxDescArray + entry;
6524                 u32 status;
6525
6526                 status = le32_to_cpu(desc->opts1);
6527                 if (status & DescOwn)
6528                         break;
6529
6530                 /* This barrier is needed to keep us from reading
6531                  * any other fields out of the Rx descriptor until
6532                  * we know the status of DescOwn
6533                  */
6534                 dma_rmb();
6535
6536                 if (unlikely(status & RxRES)) {
6537                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6538                                    status);
6539                         dev->stats.rx_errors++;
6540                         if (status & (RxRWT | RxRUNT))
6541                                 dev->stats.rx_length_errors++;
6542                         if (status & RxCRC)
6543                                 dev->stats.rx_crc_errors++;
6544                         /* RxFOVF is a reserved bit on later chip versions */
6545                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6546                             status & RxFOVF) {
6547                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6548                                 dev->stats.rx_fifo_errors++;
6549                         } else if (status & (RxRUNT | RxCRC) &&
6550                                    !(status & RxRWT) &&
6551                                    dev->features & NETIF_F_RXALL) {
6552                                 goto process_pkt;
6553                         }
6554                 } else {
6555                         struct sk_buff *skb;
6556                         dma_addr_t addr;
6557                         int pkt_size;
6558
6559 process_pkt:
6560                         addr = le64_to_cpu(desc->addr);
6561                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6562                                 pkt_size = (status & 0x00003fff) - 4;
6563                         else
6564                                 pkt_size = status & 0x00003fff;
6565
6566                         /*
6567                          * The driver does not support incoming fragmented
6568                          * frames. They are seen as a symptom of over-mtu
6569                          * sized frames.
6570                          */
6571                         if (unlikely(rtl8169_fragmented_frame(status))) {
6572                                 dev->stats.rx_dropped++;
6573                                 dev->stats.rx_length_errors++;
6574                                 goto release_descriptor;
6575                         }
6576
6577                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6578                                                   tp, pkt_size, addr);
6579                         if (!skb) {
6580                                 dev->stats.rx_dropped++;
6581                                 goto release_descriptor;
6582                         }
6583
6584                         rtl8169_rx_csum(skb, status);
6585                         skb_put(skb, pkt_size);
6586                         skb->protocol = eth_type_trans(skb, dev);
6587
6588                         rtl8169_rx_vlan_tag(desc, skb);
6589
6590                         if (skb->pkt_type == PACKET_MULTICAST)
6591                                 dev->stats.multicast++;
6592
6593                         napi_gro_receive(&tp->napi, skb);
6594
6595                         u64_stats_update_begin(&tp->rx_stats.syncp);
6596                         tp->rx_stats.packets++;
6597                         tp->rx_stats.bytes += pkt_size;
6598                         u64_stats_update_end(&tp->rx_stats.syncp);
6599                 }
6600 release_descriptor:
6601                 desc->opts2 = 0;
6602                 rtl8169_mark_to_asic(desc);
6603         }
6604
6605         count = cur_rx - tp->cur_rx;
6606         tp->cur_rx = cur_rx;
6607
6608         return count;
6609 }
6610
6611 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6612 {
6613         struct rtl8169_private *tp = dev_instance;
6614         u16 status = rtl_get_events(tp);
6615
6616         if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6617                 return IRQ_NONE;
6618
6619         rtl_irq_disable(tp);
6620         napi_schedule(&tp->napi);
6621
6622         return IRQ_HANDLED;
6623 }
6624
6625 /*
6626  * Workqueue context.
6627  */
6628 static void rtl_slow_event_work(struct rtl8169_private *tp)
6629 {
6630         struct net_device *dev = tp->dev;
6631         u16 status;
6632
6633         status = rtl_get_events(tp) & tp->event_slow;
6634         rtl_ack_events(tp, status);
6635
6636         if (unlikely(status & RxFIFOOver)) {
6637                 switch (tp->mac_version) {
6638                 /* Work around for rx fifo overflow */
6639                 case RTL_GIGA_MAC_VER_11:
6640                         netif_stop_queue(dev);
6641                         /* XXX - Hack alert. See rtl_task(). */
6642                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6643                 default:
6644                         break;
6645                 }
6646         }
6647
6648         if (unlikely(status & SYSErr))
6649                 rtl8169_pcierr_interrupt(dev);
6650
6651         if (status & LinkChg)
6652                 phy_mac_interrupt(dev->phydev);
6653
6654         rtl_irq_enable_all(tp);
6655 }
6656
6657 static void rtl_task(struct work_struct *work)
6658 {
6659         static const struct {
6660                 int bitnr;
6661                 void (*action)(struct rtl8169_private *);
6662         } rtl_work[] = {
6663                 /* XXX - keep rtl_slow_event_work() as first element. */
6664                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6665                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6666         };
6667         struct rtl8169_private *tp =
6668                 container_of(work, struct rtl8169_private, wk.work);
6669         struct net_device *dev = tp->dev;
6670         int i;
6671
6672         rtl_lock_work(tp);
6673
6674         if (!netif_running(dev) ||
6675             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6676                 goto out_unlock;
6677
6678         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6679                 bool pending;
6680
6681                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6682                 if (pending)
6683                         rtl_work[i].action(tp);
6684         }
6685
6686 out_unlock:
6687         rtl_unlock_work(tp);
6688 }
6689
6690 static int rtl8169_poll(struct napi_struct *napi, int budget)
6691 {
6692         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6693         struct net_device *dev = tp->dev;
6694         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6695         int work_done;
6696         u16 status;
6697
6698         status = rtl_get_events(tp);
6699         rtl_ack_events(tp, status & ~tp->event_slow);
6700
6701         work_done = rtl_rx(dev, tp, (u32) budget);
6702
6703         rtl_tx(dev, tp);
6704
6705         if (status & tp->event_slow) {
6706                 enable_mask &= ~tp->event_slow;
6707
6708                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6709         }
6710
6711         if (work_done < budget) {
6712                 napi_complete_done(napi, work_done);
6713
6714                 rtl_irq_enable(tp, enable_mask);
6715                 mmiowb();
6716         }
6717
6718         return work_done;
6719 }
6720
6721 static void rtl8169_rx_missed(struct net_device *dev)
6722 {
6723         struct rtl8169_private *tp = netdev_priv(dev);
6724
6725         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6726                 return;
6727
6728         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6729         RTL_W32(tp, RxMissed, 0);
6730 }
6731
6732 static void r8169_phylink_handler(struct net_device *ndev)
6733 {
6734         struct rtl8169_private *tp = netdev_priv(ndev);
6735
6736         if (netif_carrier_ok(ndev)) {
6737                 rtl_link_chg_patch(tp);
6738                 pm_request_resume(&tp->pci_dev->dev);
6739         } else {
6740                 pm_runtime_idle(&tp->pci_dev->dev);
6741         }
6742
6743         if (net_ratelimit())
6744                 phy_print_status(ndev->phydev);
6745 }
6746
6747 static int r8169_phy_connect(struct rtl8169_private *tp)
6748 {
6749         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6750         phy_interface_t phy_mode;
6751         int ret;
6752
6753         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6754                    PHY_INTERFACE_MODE_MII;
6755
6756         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6757                                  phy_mode);
6758         if (ret)
6759                 return ret;
6760
6761         if (!tp->supports_gmii)
6762                 phy_set_max_speed(phydev, SPEED_100);
6763
6764         /* Ensure to advertise everything, incl. pause */
6765         phydev->advertising = phydev->supported;
6766
6767         phy_attached_info(phydev);
6768
6769         return 0;
6770 }
6771
6772 static void rtl8169_down(struct net_device *dev)
6773 {
6774         struct rtl8169_private *tp = netdev_priv(dev);
6775
6776         phy_stop(dev->phydev);
6777
6778         napi_disable(&tp->napi);
6779         netif_stop_queue(dev);
6780
6781         rtl8169_hw_reset(tp);
6782         /*
6783          * At this point device interrupts can not be enabled in any function,
6784          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6785          * and napi is disabled (rtl8169_poll).
6786          */
6787         rtl8169_rx_missed(dev);
6788
6789         /* Give a racing hard_start_xmit a few cycles to complete. */
6790         synchronize_sched();
6791
6792         rtl8169_tx_clear(tp);
6793
6794         rtl8169_rx_clear(tp);
6795
6796         rtl_pll_power_down(tp);
6797 }
6798
6799 static int rtl8169_close(struct net_device *dev)
6800 {
6801         struct rtl8169_private *tp = netdev_priv(dev);
6802         struct pci_dev *pdev = tp->pci_dev;
6803
6804         pm_runtime_get_sync(&pdev->dev);
6805
6806         /* Update counters before going down */
6807         rtl8169_update_counters(tp);
6808
6809         rtl_lock_work(tp);
6810         /* Clear all task flags */
6811         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6812
6813         rtl8169_down(dev);
6814         rtl_unlock_work(tp);
6815
6816         cancel_work_sync(&tp->wk.work);
6817
6818         phy_disconnect(dev->phydev);
6819
6820         free_irq(pci_irq_vector(pdev, 0), tp);
6821
6822         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6823                           tp->RxPhyAddr);
6824         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6825                           tp->TxPhyAddr);
6826         tp->TxDescArray = NULL;
6827         tp->RxDescArray = NULL;
6828
6829         pm_runtime_put_sync(&pdev->dev);
6830
6831         return 0;
6832 }
6833
6834 #ifdef CONFIG_NET_POLL_CONTROLLER
6835 static void rtl8169_netpoll(struct net_device *dev)
6836 {
6837         struct rtl8169_private *tp = netdev_priv(dev);
6838
6839         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6840 }
6841 #endif
6842
6843 static int rtl_open(struct net_device *dev)
6844 {
6845         struct rtl8169_private *tp = netdev_priv(dev);
6846         struct pci_dev *pdev = tp->pci_dev;
6847         int retval = -ENOMEM;
6848
6849         pm_runtime_get_sync(&pdev->dev);
6850
6851         /*
6852          * Rx and Tx descriptors needs 256 bytes alignment.
6853          * dma_alloc_coherent provides more.
6854          */
6855         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6856                                              &tp->TxPhyAddr, GFP_KERNEL);
6857         if (!tp->TxDescArray)
6858                 goto err_pm_runtime_put;
6859
6860         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6861                                              &tp->RxPhyAddr, GFP_KERNEL);
6862         if (!tp->RxDescArray)
6863                 goto err_free_tx_0;
6864
6865         retval = rtl8169_init_ring(tp);
6866         if (retval < 0)
6867                 goto err_free_rx_1;
6868
6869         INIT_WORK(&tp->wk.work, rtl_task);
6870
6871         smp_mb();
6872
6873         rtl_request_firmware(tp);
6874
6875         retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
6876                              IRQF_SHARED, dev->name, tp);
6877         if (retval < 0)
6878                 goto err_release_fw_2;
6879
6880         retval = r8169_phy_connect(tp);
6881         if (retval)
6882                 goto err_free_irq;
6883
6884         rtl_lock_work(tp);
6885
6886         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6887
6888         napi_enable(&tp->napi);
6889
6890         rtl8169_init_phy(dev, tp);
6891
6892         rtl_pll_power_up(tp);
6893
6894         rtl_hw_start(tp);
6895
6896         if (!rtl8169_init_counter_offsets(tp))
6897                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6898
6899         phy_start(dev->phydev);
6900         netif_start_queue(dev);
6901
6902         rtl_unlock_work(tp);
6903
6904         pm_runtime_put_sync(&pdev->dev);
6905 out:
6906         return retval;
6907
6908 err_free_irq:
6909         free_irq(pci_irq_vector(pdev, 0), tp);
6910 err_release_fw_2:
6911         rtl_release_firmware(tp);
6912         rtl8169_rx_clear(tp);
6913 err_free_rx_1:
6914         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6915                           tp->RxPhyAddr);
6916         tp->RxDescArray = NULL;
6917 err_free_tx_0:
6918         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6919                           tp->TxPhyAddr);
6920         tp->TxDescArray = NULL;
6921 err_pm_runtime_put:
6922         pm_runtime_put_noidle(&pdev->dev);
6923         goto out;
6924 }
6925
6926 static void
6927 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6928 {
6929         struct rtl8169_private *tp = netdev_priv(dev);
6930         struct pci_dev *pdev = tp->pci_dev;
6931         struct rtl8169_counters *counters = tp->counters;
6932         unsigned int start;
6933
6934         pm_runtime_get_noresume(&pdev->dev);
6935
6936         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6937                 rtl8169_rx_missed(dev);
6938
6939         do {
6940                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6941                 stats->rx_packets = tp->rx_stats.packets;
6942                 stats->rx_bytes = tp->rx_stats.bytes;
6943         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6944
6945         do {
6946                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6947                 stats->tx_packets = tp->tx_stats.packets;
6948                 stats->tx_bytes = tp->tx_stats.bytes;
6949         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6950
6951         stats->rx_dropped       = dev->stats.rx_dropped;
6952         stats->tx_dropped       = dev->stats.tx_dropped;
6953         stats->rx_length_errors = dev->stats.rx_length_errors;
6954         stats->rx_errors        = dev->stats.rx_errors;
6955         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6956         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6957         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6958         stats->multicast        = dev->stats.multicast;
6959
6960         /*
6961          * Fetch additonal counter values missing in stats collected by driver
6962          * from tally counters.
6963          */
6964         if (pm_runtime_active(&pdev->dev))
6965                 rtl8169_update_counters(tp);
6966
6967         /*
6968          * Subtract values fetched during initalization.
6969          * See rtl8169_init_counter_offsets for a description why we do that.
6970          */
6971         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6972                 le64_to_cpu(tp->tc_offset.tx_errors);
6973         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6974                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6975         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6976                 le16_to_cpu(tp->tc_offset.tx_aborted);
6977
6978         pm_runtime_put_noidle(&pdev->dev);
6979 }
6980
6981 static void rtl8169_net_suspend(struct net_device *dev)
6982 {
6983         struct rtl8169_private *tp = netdev_priv(dev);
6984
6985         if (!netif_running(dev))
6986                 return;
6987
6988         phy_stop(dev->phydev);
6989         netif_device_detach(dev);
6990         netif_stop_queue(dev);
6991
6992         rtl_lock_work(tp);
6993         napi_disable(&tp->napi);
6994         /* Clear all task flags */
6995         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6996
6997         rtl_unlock_work(tp);
6998
6999         rtl_pll_power_down(tp);
7000 }
7001
7002 #ifdef CONFIG_PM
7003
7004 static int rtl8169_suspend(struct device *device)
7005 {
7006         struct pci_dev *pdev = to_pci_dev(device);
7007         struct net_device *dev = pci_get_drvdata(pdev);
7008         struct rtl8169_private *tp = netdev_priv(dev);
7009
7010         rtl8169_net_suspend(dev);
7011         clk_disable_unprepare(tp->clk);
7012
7013         return 0;
7014 }
7015
7016 static void __rtl8169_resume(struct net_device *dev)
7017 {
7018         struct rtl8169_private *tp = netdev_priv(dev);
7019
7020         netif_device_attach(dev);
7021
7022         rtl_pll_power_up(tp);
7023         rtl8169_init_phy(dev, tp);
7024
7025         phy_start(tp->dev->phydev);
7026
7027         rtl_lock_work(tp);
7028         napi_enable(&tp->napi);
7029         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7030         rtl_unlock_work(tp);
7031
7032         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7033 }
7034
7035 static int rtl8169_resume(struct device *device)
7036 {
7037         struct pci_dev *pdev = to_pci_dev(device);
7038         struct net_device *dev = pci_get_drvdata(pdev);
7039         struct rtl8169_private *tp = netdev_priv(dev);
7040
7041         clk_prepare_enable(tp->clk);
7042
7043         if (netif_running(dev))
7044                 __rtl8169_resume(dev);
7045
7046         return 0;
7047 }
7048
7049 static int rtl8169_runtime_suspend(struct device *device)
7050 {
7051         struct pci_dev *pdev = to_pci_dev(device);
7052         struct net_device *dev = pci_get_drvdata(pdev);
7053         struct rtl8169_private *tp = netdev_priv(dev);
7054
7055         if (!tp->TxDescArray)
7056                 return 0;
7057
7058         rtl_lock_work(tp);
7059         __rtl8169_set_wol(tp, WAKE_ANY);
7060         rtl_unlock_work(tp);
7061
7062         rtl8169_net_suspend(dev);
7063
7064         /* Update counters before going runtime suspend */
7065         rtl8169_rx_missed(dev);
7066         rtl8169_update_counters(tp);
7067
7068         return 0;
7069 }
7070
7071 static int rtl8169_runtime_resume(struct device *device)
7072 {
7073         struct pci_dev *pdev = to_pci_dev(device);
7074         struct net_device *dev = pci_get_drvdata(pdev);
7075         struct rtl8169_private *tp = netdev_priv(dev);
7076         rtl_rar_set(tp, dev->dev_addr);
7077
7078         if (!tp->TxDescArray)
7079                 return 0;
7080
7081         rtl_lock_work(tp);
7082         __rtl8169_set_wol(tp, tp->saved_wolopts);
7083         rtl_unlock_work(tp);
7084
7085         __rtl8169_resume(dev);
7086
7087         return 0;
7088 }
7089
7090 static int rtl8169_runtime_idle(struct device *device)
7091 {
7092         struct pci_dev *pdev = to_pci_dev(device);
7093         struct net_device *dev = pci_get_drvdata(pdev);
7094
7095         if (!netif_running(dev) || !netif_carrier_ok(dev))
7096                 pm_schedule_suspend(device, 10000);
7097
7098         return -EBUSY;
7099 }
7100
7101 static const struct dev_pm_ops rtl8169_pm_ops = {
7102         .suspend                = rtl8169_suspend,
7103         .resume                 = rtl8169_resume,
7104         .freeze                 = rtl8169_suspend,
7105         .thaw                   = rtl8169_resume,
7106         .poweroff               = rtl8169_suspend,
7107         .restore                = rtl8169_resume,
7108         .runtime_suspend        = rtl8169_runtime_suspend,
7109         .runtime_resume         = rtl8169_runtime_resume,
7110         .runtime_idle           = rtl8169_runtime_idle,
7111 };
7112
7113 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7114
7115 #else /* !CONFIG_PM */
7116
7117 #define RTL8169_PM_OPS  NULL
7118
7119 #endif /* !CONFIG_PM */
7120
7121 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7122 {
7123         /* WoL fails with 8168b when the receiver is disabled. */
7124         switch (tp->mac_version) {
7125         case RTL_GIGA_MAC_VER_11:
7126         case RTL_GIGA_MAC_VER_12:
7127         case RTL_GIGA_MAC_VER_17:
7128                 pci_clear_master(tp->pci_dev);
7129
7130                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7131                 /* PCI commit */
7132                 RTL_R8(tp, ChipCmd);
7133                 break;
7134         default:
7135                 break;
7136         }
7137 }
7138
7139 static void rtl_shutdown(struct pci_dev *pdev)
7140 {
7141         struct net_device *dev = pci_get_drvdata(pdev);
7142         struct rtl8169_private *tp = netdev_priv(dev);
7143
7144         rtl8169_net_suspend(dev);
7145
7146         /* Restore original MAC address */
7147         rtl_rar_set(tp, dev->perm_addr);
7148
7149         rtl8169_hw_reset(tp);
7150
7151         if (system_state == SYSTEM_POWER_OFF) {
7152                 if (tp->saved_wolopts) {
7153                         rtl_wol_suspend_quirk(tp);
7154                         rtl_wol_shutdown_quirk(tp);
7155                 }
7156
7157                 pci_wake_from_d3(pdev, true);
7158                 pci_set_power_state(pdev, PCI_D3hot);
7159         }
7160 }
7161
7162 static void rtl_remove_one(struct pci_dev *pdev)
7163 {
7164         struct net_device *dev = pci_get_drvdata(pdev);
7165         struct rtl8169_private *tp = netdev_priv(dev);
7166
7167         if (r8168_check_dash(tp))
7168                 rtl8168_driver_stop(tp);
7169
7170         netif_napi_del(&tp->napi);
7171
7172         unregister_netdev(dev);
7173         mdiobus_unregister(tp->mii_bus);
7174
7175         rtl_release_firmware(tp);
7176
7177         if (pci_dev_run_wake(pdev))
7178                 pm_runtime_get_noresume(&pdev->dev);
7179
7180         /* restore original MAC address */
7181         rtl_rar_set(tp, dev->perm_addr);
7182 }
7183
7184 static const struct net_device_ops rtl_netdev_ops = {
7185         .ndo_open               = rtl_open,
7186         .ndo_stop               = rtl8169_close,
7187         .ndo_get_stats64        = rtl8169_get_stats64,
7188         .ndo_start_xmit         = rtl8169_start_xmit,
7189         .ndo_tx_timeout         = rtl8169_tx_timeout,
7190         .ndo_validate_addr      = eth_validate_addr,
7191         .ndo_change_mtu         = rtl8169_change_mtu,
7192         .ndo_fix_features       = rtl8169_fix_features,
7193         .ndo_set_features       = rtl8169_set_features,
7194         .ndo_set_mac_address    = rtl_set_mac_address,
7195         .ndo_do_ioctl           = rtl8169_ioctl,
7196         .ndo_set_rx_mode        = rtl_set_rx_mode,
7197 #ifdef CONFIG_NET_POLL_CONTROLLER
7198         .ndo_poll_controller    = rtl8169_netpoll,
7199 #endif
7200
7201 };
7202
7203 static const struct rtl_cfg_info {
7204         void (*hw_start)(struct rtl8169_private *tp);
7205         u16 event_slow;
7206         unsigned int has_gmii:1;
7207         const struct rtl_coalesce_info *coalesce_info;
7208         u8 default_ver;
7209 } rtl_cfg_infos [] = {
7210         [RTL_CFG_0] = {
7211                 .hw_start       = rtl_hw_start_8169,
7212                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7213                 .has_gmii       = 1,
7214                 .coalesce_info  = rtl_coalesce_info_8169,
7215                 .default_ver    = RTL_GIGA_MAC_VER_01,
7216         },
7217         [RTL_CFG_1] = {
7218                 .hw_start       = rtl_hw_start_8168,
7219                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7220                 .has_gmii       = 1,
7221                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7222                 .default_ver    = RTL_GIGA_MAC_VER_11,
7223         },
7224         [RTL_CFG_2] = {
7225                 .hw_start       = rtl_hw_start_8101,
7226                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7227                                   PCSTimeout,
7228                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7229                 .default_ver    = RTL_GIGA_MAC_VER_13,
7230         }
7231 };
7232
7233 static int rtl_alloc_irq(struct rtl8169_private *tp)
7234 {
7235         unsigned int flags;
7236
7237         switch (tp->mac_version) {
7238         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7239                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7240                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7241                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7242                 /* fall through */
7243         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
7244                 flags = PCI_IRQ_LEGACY;
7245                 break;
7246         default:
7247                 flags = PCI_IRQ_ALL_TYPES;
7248                 break;
7249         }
7250
7251         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7252 }
7253
7254 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7255 {
7256         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7257 }
7258
7259 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7260 {
7261         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7262 }
7263
7264 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7265 {
7266         struct rtl8169_private *tp = mii_bus->priv;
7267
7268         if (phyaddr > 0)
7269                 return -ENODEV;
7270
7271         return rtl_readphy(tp, phyreg);
7272 }
7273
7274 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7275                                 int phyreg, u16 val)
7276 {
7277         struct rtl8169_private *tp = mii_bus->priv;
7278
7279         if (phyaddr > 0)
7280                 return -ENODEV;
7281
7282         rtl_writephy(tp, phyreg, val);
7283
7284         return 0;
7285 }
7286
7287 static int r8169_mdio_register(struct rtl8169_private *tp)
7288 {
7289         struct pci_dev *pdev = tp->pci_dev;
7290         struct phy_device *phydev;
7291         struct mii_bus *new_bus;
7292         int ret;
7293
7294         new_bus = devm_mdiobus_alloc(&pdev->dev);
7295         if (!new_bus)
7296                 return -ENOMEM;
7297
7298         new_bus->name = "r8169";
7299         new_bus->priv = tp;
7300         new_bus->parent = &pdev->dev;
7301         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7302         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7303                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7304
7305         new_bus->read = r8169_mdio_read_reg;
7306         new_bus->write = r8169_mdio_write_reg;
7307
7308         ret = mdiobus_register(new_bus);
7309         if (ret)
7310                 return ret;
7311
7312         phydev = mdiobus_get_phy(new_bus, 0);
7313         if (!phydev) {
7314                 mdiobus_unregister(new_bus);
7315                 return -ENODEV;
7316         }
7317
7318         /* PHY will be woken up in rtl_open() */
7319         phy_suspend(phydev);
7320
7321         tp->mii_bus = new_bus;
7322
7323         return 0;
7324 }
7325
7326 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7327 {
7328         u32 data;
7329
7330         tp->ocp_base = OCP_STD_PHY_BASE;
7331
7332         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7333
7334         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7335                 return;
7336
7337         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7338                 return;
7339
7340         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7341         msleep(1);
7342         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7343
7344         data = r8168_mac_ocp_read(tp, 0xe8de);
7345         data &= ~(1 << 14);
7346         r8168_mac_ocp_write(tp, 0xe8de, data);
7347
7348         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7349                 return;
7350
7351         data = r8168_mac_ocp_read(tp, 0xe8de);
7352         data |= (1 << 15);
7353         r8168_mac_ocp_write(tp, 0xe8de, data);
7354
7355         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7356                 return;
7357 }
7358
7359 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7360 {
7361         rtl8168ep_stop_cmac(tp);
7362         rtl_hw_init_8168g(tp);
7363 }
7364
7365 static void rtl_hw_initialize(struct rtl8169_private *tp)
7366 {
7367         switch (tp->mac_version) {
7368         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7369                 rtl_hw_init_8168g(tp);
7370                 break;
7371         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7372                 rtl_hw_init_8168ep(tp);
7373                 break;
7374         default:
7375                 break;
7376         }
7377 }
7378
7379 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7380 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7381 {
7382         switch (tp->mac_version) {
7383         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7384         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7385                 return false;
7386         default:
7387                 return true;
7388         }
7389 }
7390
7391 static int rtl_jumbo_max(struct rtl8169_private *tp)
7392 {
7393         /* Non-GBit versions don't support jumbo frames */
7394         if (!tp->supports_gmii)
7395                 return JUMBO_1K;
7396
7397         switch (tp->mac_version) {
7398         /* RTL8169 */
7399         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7400                 return JUMBO_7K;
7401         /* RTL8168b */
7402         case RTL_GIGA_MAC_VER_11:
7403         case RTL_GIGA_MAC_VER_12:
7404         case RTL_GIGA_MAC_VER_17:
7405                 return JUMBO_4K;
7406         /* RTL8168c */
7407         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7408                 return JUMBO_6K;
7409         default:
7410                 return JUMBO_9K;
7411         }
7412 }
7413
7414 static void rtl_disable_clk(void *data)
7415 {
7416         clk_disable_unprepare(data);
7417 }
7418
7419 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7420 {
7421         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7422         struct rtl8169_private *tp;
7423         struct net_device *dev;
7424         int chipset, region, i;
7425         int jumbo_max, rc;
7426
7427         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7428         if (!dev)
7429                 return -ENOMEM;
7430
7431         SET_NETDEV_DEV(dev, &pdev->dev);
7432         dev->netdev_ops = &rtl_netdev_ops;
7433         tp = netdev_priv(dev);
7434         tp->dev = dev;
7435         tp->pci_dev = pdev;
7436         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7437         tp->supports_gmii = cfg->has_gmii;
7438
7439         /* Get the *optional* external "ether_clk" used on some boards */
7440         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7441         if (IS_ERR(tp->clk)) {
7442                 rc = PTR_ERR(tp->clk);
7443                 if (rc == -ENOENT) {
7444                         /* clk-core allows NULL (for suspend / resume) */
7445                         tp->clk = NULL;
7446                 } else if (rc == -EPROBE_DEFER) {
7447                         return rc;
7448                 } else {
7449                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7450                         return rc;
7451                 }
7452         } else {
7453                 rc = clk_prepare_enable(tp->clk);
7454                 if (rc) {
7455                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7456                         return rc;
7457                 }
7458
7459                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7460                                               tp->clk);
7461                 if (rc)
7462                         return rc;
7463         }
7464
7465         /* Disable ASPM completely as that cause random device stop working
7466          * problems as well as full system hangs for some PCIe devices users.
7467          */
7468         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7469
7470         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7471         rc = pcim_enable_device(pdev);
7472         if (rc < 0) {
7473                 dev_err(&pdev->dev, "enable failure\n");
7474                 return rc;
7475         }
7476
7477         if (pcim_set_mwi(pdev) < 0)
7478                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7479
7480         /* use first MMIO region */
7481         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7482         if (region < 0) {
7483                 dev_err(&pdev->dev, "no MMIO resource found\n");
7484                 return -ENODEV;
7485         }
7486
7487         /* check for weird/broken PCI region reporting */
7488         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7489                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7490                 return -ENODEV;
7491         }
7492
7493         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7494         if (rc < 0) {
7495                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7496                 return rc;
7497         }
7498
7499         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7500
7501         if (!pci_is_pcie(pdev))
7502                 dev_info(&pdev->dev, "not PCI Express\n");
7503
7504         /* Identify chip attached to board */
7505         rtl8169_get_mac_version(tp, cfg->default_ver);
7506
7507         if (rtl_tbi_enabled(tp)) {
7508                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7509                 return -ENODEV;
7510         }
7511
7512         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7513
7514         if ((sizeof(dma_addr_t) > 4) &&
7515             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7516                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7517             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7518             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7519
7520                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7521                 if (!pci_is_pcie(pdev))
7522                         tp->cp_cmd |= PCIDAC;
7523                 dev->features |= NETIF_F_HIGHDMA;
7524         } else {
7525                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7526                 if (rc < 0) {
7527                         dev_err(&pdev->dev, "DMA configuration failed\n");
7528                         return rc;
7529                 }
7530         }
7531
7532         rtl_init_rxcfg(tp);
7533
7534         rtl_irq_disable(tp);
7535
7536         rtl_hw_initialize(tp);
7537
7538         rtl_hw_reset(tp);
7539
7540         rtl_ack_events(tp, 0xffff);
7541
7542         pci_set_master(pdev);
7543
7544         rtl_init_mdio_ops(tp);
7545         rtl_init_jumbo_ops(tp);
7546
7547         rtl8169_print_mac_version(tp);
7548
7549         chipset = tp->mac_version;
7550
7551         rc = rtl_alloc_irq(tp);
7552         if (rc < 0) {
7553                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7554                 return rc;
7555         }
7556
7557         tp->saved_wolopts = __rtl8169_get_wol(tp);
7558
7559         mutex_init(&tp->wk.mutex);
7560         u64_stats_init(&tp->rx_stats.syncp);
7561         u64_stats_init(&tp->tx_stats.syncp);
7562
7563         /* Get MAC address */
7564         switch (tp->mac_version) {
7565                 u8 mac_addr[ETH_ALEN] __aligned(4);
7566         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7567         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7568                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7569                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7570
7571                 if (is_valid_ether_addr(mac_addr))
7572                         rtl_rar_set(tp, mac_addr);
7573                 break;
7574         default:
7575                 break;
7576         }
7577         for (i = 0; i < ETH_ALEN; i++)
7578                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7579
7580         dev->ethtool_ops = &rtl8169_ethtool_ops;
7581         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7582
7583         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7584
7585         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7586          * properly for all devices */
7587         dev->features |= NETIF_F_RXCSUM |
7588                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7589
7590         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7591                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7592                 NETIF_F_HW_VLAN_CTAG_RX;
7593         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7594                 NETIF_F_HIGHDMA;
7595         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7596
7597         tp->cp_cmd |= RxChkSum | RxVlan;
7598
7599         /*
7600          * Pretend we are using VLANs; This bypasses a nasty bug where
7601          * Interrupts stop flowing on high load on 8110SCd controllers.
7602          */
7603         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7604                 /* Disallow toggling */
7605                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7606
7607         if (rtl_chip_supports_csum_v2(tp)) {
7608                 tp->tso_csum = rtl8169_tso_csum_v2;
7609                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7610         } else {
7611                 tp->tso_csum = rtl8169_tso_csum_v1;
7612         }
7613
7614         dev->hw_features |= NETIF_F_RXALL;
7615         dev->hw_features |= NETIF_F_RXFCS;
7616
7617         /* MTU range: 60 - hw-specific max */
7618         dev->min_mtu = ETH_ZLEN;
7619         jumbo_max = rtl_jumbo_max(tp);
7620         dev->max_mtu = jumbo_max;
7621
7622         tp->hw_start = cfg->hw_start;
7623         tp->event_slow = cfg->event_slow;
7624         tp->coalesce_info = cfg->coalesce_info;
7625
7626         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7627
7628         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7629                                             &tp->counters_phys_addr,
7630                                             GFP_KERNEL);
7631         if (!tp->counters)
7632                 return -ENOMEM;
7633
7634         pci_set_drvdata(pdev, dev);
7635
7636         rc = r8169_mdio_register(tp);
7637         if (rc)
7638                 return rc;
7639
7640         /* chip gets powered up in rtl_open() */
7641         rtl_pll_power_down(tp);
7642
7643         rc = register_netdev(dev);
7644         if (rc)
7645                 goto err_mdio_unregister;
7646
7647         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7648                    rtl_chip_infos[chipset].name, dev->dev_addr,
7649                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7650                    pci_irq_vector(pdev, 0));
7651
7652         if (jumbo_max > JUMBO_1K)
7653                 netif_info(tp, probe, dev,
7654                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7655                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7656                            "ok" : "ko");
7657
7658         if (r8168_check_dash(tp))
7659                 rtl8168_driver_start(tp);
7660
7661         if (pci_dev_run_wake(pdev))
7662                 pm_runtime_put_sync(&pdev->dev);
7663
7664         return 0;
7665
7666 err_mdio_unregister:
7667         mdiobus_unregister(tp->mii_bus);
7668         return rc;
7669 }
7670
7671 static struct pci_driver rtl8169_pci_driver = {
7672         .name           = MODULENAME,
7673         .id_table       = rtl8169_pci_tbl,
7674         .probe          = rtl_init_one,
7675         .remove         = rtl_remove_one,
7676         .shutdown       = rtl_shutdown,
7677         .driver.pm      = RTL8169_PM_OPS,
7678 };
7679
7680 module_pci_driver(rtl8169_pci_driver);