drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_8168D_2        "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_8168E_1        "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_8168E_2        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_8168E_3        "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_8168F_1        "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_8168F_2        "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_8105E_1        "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_8402_1         "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_8411_1         "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_8411_2         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_8106E_1        "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_8106E_2        "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_8168G_2        "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_8168G_3        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_8168H_1        "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_8168H_2        "/*(DEBLOBBED)*/"
  57 #define FIRMWARE_8107E_1        "/*(DEBLOBBED)*/"
  58 #define FIRMWARE_8107E_2        "/*(DEBLOBBED)*/"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 328         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 333         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 336         { PCI_VENDOR_ID_DLINK,                  0x4300,
 337                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 338         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 339         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 340         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 341         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 342         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 343                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 344         { 0x0001,                               0x8168,
 345                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 346         {0,},
 347 };
 348
 349 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 350
 351 static int rx_buf_sz = 16383;
 352 static int use_dac = -1;
 353 static struct {
 354         u32 msg_enable;
 355 } debug = { -1 };
 356
 357 enum rtl_registers {
 358         MAC0            = 0,    /* Ethernet hardware address. */
 359         MAC4            = 4,
 360         MAR0            = 8,    /* Multicast filter. */
 361         CounterAddrLow          = 0x10,
 362         CounterAddrHigh         = 0x14,
 363         TxDescStartAddrLow      = 0x20,
 364         TxDescStartAddrHigh     = 0x24,
 365         TxHDescStartAddrLow     = 0x28,
 366         TxHDescStartAddrHigh    = 0x2c,
 367         FLASH           = 0x30,
 368         ERSR            = 0x36,
 369         ChipCmd         = 0x37,
 370         TxPoll          = 0x38,
 371         IntrMask        = 0x3c,
 372         IntrStatus      = 0x3e,
 373
 374         TxConfig        = 0x40,
 375 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 376 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 377
 378         RxConfig        = 0x44,
 379 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 380 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 381 #define RXCFG_FIFO_SHIFT                13
 382                                         /* No threshold before first PCI xfer */
 383 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 384 #define RX_EARLY_OFF                    (1 << 11)
 385 #define RXCFG_DMA_SHIFT                 8
 386                                         /* Unlimited maximum PCI burst. */
 387 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 388
 389         RxMissed        = 0x4c,
 390         Cfg9346         = 0x50,
 391         Config0         = 0x51,
 392         Config1         = 0x52,
 393         Config2         = 0x53,
 394 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 395
 396         Config3         = 0x54,
 397         Config4         = 0x55,
 398         Config5         = 0x56,
 399         MultiIntr       = 0x5c,
 400         PHYAR           = 0x60,
 401         PHYstatus       = 0x6c,
 402         RxMaxSize       = 0xda,
 403         CPlusCmd        = 0xe0,
 404         IntrMitigate    = 0xe2,
 405         RxDescAddrLow   = 0xe4,
 406         RxDescAddrHigh  = 0xe8,
 407         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 408
 409 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 410
 411         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 412
 413 #define TxPacketMax     (8064 >> 7)
 414 #define EarlySize       0x27
 415
 416         FuncEvent       = 0xf0,
 417         FuncEventMask   = 0xf4,
 418         FuncPresetState = 0xf8,
 419         IBCR0           = 0xf8,
 420         IBCR2           = 0xf9,
 421         IBIMR0          = 0xfa,
 422         IBISR0          = 0xfb,
 423         FuncForceEvent  = 0xfc,
 424 };
 425
 426 enum rtl8110_registers {
 427         TBICSR                  = 0x64,
 428         TBI_ANAR                = 0x68,
 429         TBI_LPAR                = 0x6a,
 430 };
 431
 432 enum rtl8168_8101_registers {
 433         CSIDR                   = 0x64,
 434         CSIAR                   = 0x68,
 435 #define CSIAR_FLAG                      0x80000000
 436 #define CSIAR_WRITE_CMD                 0x80000000
 437 #define CSIAR_BYTE_ENABLE               0x0f
 438 #define CSIAR_BYTE_ENABLE_SHIFT         12
 439 #define CSIAR_ADDR_MASK                 0x0fff
 440 #define CSIAR_FUNC_CARD                 0x00000000
 441 #define CSIAR_FUNC_SDIO                 0x00010000
 442 #define CSIAR_FUNC_NIC                  0x00020000
 443 #define CSIAR_FUNC_NIC2                 0x00010000
 444         PMCH                    = 0x6f,
 445         EPHYAR                  = 0x80,
 446 #define EPHYAR_FLAG                     0x80000000
 447 #define EPHYAR_WRITE_CMD                0x80000000
 448 #define EPHYAR_REG_MASK                 0x1f
 449 #define EPHYAR_REG_SHIFT                16
 450 #define EPHYAR_DATA_MASK                0xffff
 451         DLLPR                   = 0xd0,
 452 #define PFM_EN                          (1 << 6)
 453 #define TX_10M_PS_EN                    (1 << 7)
 454         DBG_REG                 = 0xd1,
 455 #define FIX_NAK_1                       (1 << 4)
 456 #define FIX_NAK_2                       (1 << 3)
 457         TWSI                    = 0xd2,
 458         MCU                     = 0xd3,
 459 #define NOW_IS_OOB                      (1 << 7)
 460 #define TX_EMPTY                        (1 << 5)
 461 #define RX_EMPTY                        (1 << 4)
 462 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 463 #define EN_NDP                          (1 << 3)
 464 #define EN_OOB_RESET                    (1 << 2)
 465 #define LINK_LIST_RDY                   (1 << 1)
 466         EFUSEAR                 = 0xdc,
 467 #define EFUSEAR_FLAG                    0x80000000
 468 #define EFUSEAR_WRITE_CMD               0x80000000
 469 #define EFUSEAR_READ_CMD                0x00000000
 470 #define EFUSEAR_REG_MASK                0x03ff
 471 #define EFUSEAR_REG_SHIFT               8
 472 #define EFUSEAR_DATA_MASK               0xff
 473         MISC_1                  = 0xf2,
 474 #define PFM_D3COLD_EN                   (1 << 6)
 475 };
 476
 477 enum rtl8168_registers {
 478         LED_FREQ                = 0x1a,
 479         EEE_LED                 = 0x1b,
 480         ERIDR                   = 0x70,
 481         ERIAR                   = 0x74,
 482 #define ERIAR_FLAG                      0x80000000
 483 #define ERIAR_WRITE_CMD                 0x80000000
 484 #define ERIAR_READ_CMD                  0x00000000
 485 #define ERIAR_ADDR_BYTE_ALIGN           4
 486 #define ERIAR_TYPE_SHIFT                16
 487 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 488 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 489 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 490 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_MASK_SHIFT                12
 492 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 493 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 494 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 495 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 497         EPHY_RXER_NUM           = 0x7c,
 498         OCPDR                   = 0xb0, /* OCP GPHY access */
 499 #define OCPDR_WRITE_CMD                 0x80000000
 500 #define OCPDR_READ_CMD                  0x00000000
 501 #define OCPDR_REG_MASK                  0x7f
 502 #define OCPDR_GPHY_REG_SHIFT            16
 503 #define OCPDR_DATA_MASK                 0xffff
 504         OCPAR                   = 0xb4,
 505 #define OCPAR_FLAG                      0x80000000
 506 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 507 #define OCPAR_GPHY_READ_CMD             0x0000f060
 508         GPHY_OCP                = 0xb8,
 509         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 510         MISC                    = 0xf0, /* 8168e only. */
 511 #define TXPLA_RST                       (1 << 29)
 512 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 513 #define PWM_EN                          (1 << 22)
 514 #define RXDV_GATED_EN                   (1 << 19)
 515 #define EARLY_TALLY_EN                  (1 << 16)
 516 };
 517
 518 enum rtl_register_content {
 519         /* InterruptStatusBits */
 520         SYSErr          = 0x8000,
 521         PCSTimeout      = 0x4000,
 522         SWInt           = 0x0100,
 523         TxDescUnavail   = 0x0080,
 524         RxFIFOOver      = 0x0040,
 525         LinkChg         = 0x0020,
 526         RxOverflow      = 0x0010,
 527         TxErr           = 0x0008,
 528         TxOK            = 0x0004,
 529         RxErr           = 0x0002,
 530         RxOK            = 0x0001,
 531
 532         /* RxStatusDesc */
 533         RxBOVF  = (1 << 24),
 534         RxFOVF  = (1 << 23),
 535         RxRWT   = (1 << 22),
 536         RxRES   = (1 << 21),
 537         RxRUNT  = (1 << 20),
 538         RxCRC   = (1 << 19),
 539
 540         /* ChipCmdBits */
 541         StopReq         = 0x80,
 542         CmdReset        = 0x10,
 543         CmdRxEnb        = 0x08,
 544         CmdTxEnb        = 0x04,
 545         RxBufEmpty      = 0x01,
 546
 547         /* TXPoll register p.5 */
 548         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 549         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 550         FSWInt          = 0x01,         /* Forced software interrupt */
 551
 552         /* Cfg9346Bits */
 553         Cfg9346_Lock    = 0x00,
 554         Cfg9346_Unlock  = 0xc0,
 555
 556         /* rx_mode_bits */
 557         AcceptErr       = 0x20,
 558         AcceptRunt      = 0x10,
 559         AcceptBroadcast = 0x08,
 560         AcceptMulticast = 0x04,
 561         AcceptMyPhys    = 0x02,
 562         AcceptAllPhys   = 0x01,
 563 #define RX_CONFIG_ACCEPT_MASK           0x3f
 564
 565         /* TxConfigBits */
 566         TxInterFrameGapShift = 24,
 567         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 568
 569         /* Config1 register p.24 */
 570         LEDS1           = (1 << 7),
 571         LEDS0           = (1 << 6),
 572         Speed_down      = (1 << 4),
 573         MEMMAP          = (1 << 3),
 574         IOMAP           = (1 << 2),
 575         VPD             = (1 << 1),
 576         PMEnable        = (1 << 0),     /* Power Management Enable */
 577
 578         /* Config2 register p. 25 */
 579         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 580         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 581         PCI_Clock_66MHz = 0x01,
 582         PCI_Clock_33MHz = 0x00,
 583
 584         /* Config3 register p.25 */
 585         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 586         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 587         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 588         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 589         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 590
 591         /* Config4 register */
 592         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 593
 594         /* Config5 register p.27 */
 595         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 596         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 597         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 598         Spi_en          = (1 << 3),
 599         LanWake         = (1 << 1),     /* LanWake enable/disable */
 600         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 601         ASPM_en         = (1 << 0),     /* ASPM enable */
 602
 603         /* TBICSR p.28 */
 604         TBIReset        = 0x80000000,
 605         TBILoopback     = 0x40000000,
 606         TBINwEnable     = 0x20000000,
 607         TBINwRestart    = 0x10000000,
 608         TBILinkOk       = 0x02000000,
 609         TBINwComplete   = 0x01000000,
 610
 611         /* CPlusCmd p.31 */
 612         EnableBist      = (1 << 15),    // 8168 8101
 613         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 614         Normal_mode     = (1 << 13),    // unused
 615         Force_half_dup  = (1 << 12),    // 8168 8101
 616         Force_rxflow_en = (1 << 11),    // 8168 8101
 617         Force_txflow_en = (1 << 10),    // 8168 8101
 618         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 619         ASF             = (1 << 8),     // 8168 8101
 620         PktCntrDisable  = (1 << 7),     // 8168 8101
 621         Mac_dbgo_sel    = 0x001c,       // 8168
 622         RxVlan          = (1 << 6),
 623         RxChkSum        = (1 << 5),
 624         PCIDAC          = (1 << 4),
 625         PCIMulRW        = (1 << 3),
 626         INTT_0          = 0x0000,       // 8168
 627         INTT_1          = 0x0001,       // 8168
 628         INTT_2          = 0x0002,       // 8168
 629         INTT_3          = 0x0003,       // 8168
 630
 631         /* rtl8169_PHYstatus */
 632         TBI_Enable      = 0x80,
 633         TxFlowCtrl      = 0x40,
 634         RxFlowCtrl      = 0x20,
 635         _1000bpsF       = 0x10,
 636         _100bps         = 0x08,
 637         _10bps          = 0x04,
 638         LinkStatus      = 0x02,
 639         FullDup         = 0x01,
 640
 641         /* _TBICSRBit */
 642         TBILinkOK       = 0x02000000,
 643
 644         /* ResetCounterCommand */
 645         CounterReset    = 0x1,
 646
 647         /* DumpCounterCommand */
 648         CounterDump     = 0x8,
 649
 650         /* magic enable v2 */
 651         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 652 };
 653
 654 enum rtl_desc_bit {
 655         /* First doubleword. */
 656         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 657         RingEnd         = (1 << 30), /* End of descriptor ring */
 658         FirstFrag       = (1 << 29), /* First segment of a packet */
 659         LastFrag        = (1 << 28), /* Final segment of a packet */
 660 };
 661
 662 /* Generic case. */
 663 enum rtl_tx_desc_bit {
 664         /* First doubleword. */
 665         TD_LSO          = (1 << 27),            /* Large Send Offload */
 666 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 667
 668         /* Second doubleword. */
 669         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 670 };
 671
 672 /* 8169, 8168b and 810x except 8102e. */
 673 enum rtl_tx_desc_bit_0 {
 674         /* First doubleword. */
 675 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 676         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 677         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 678         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 679 };
 680
 681 /* 8102e, 8168c and beyond. */
 682 enum rtl_tx_desc_bit_1 {
 683         /* First doubleword. */
 684         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 685         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 686 #define GTTCPHO_SHIFT                   18
 687 #define GTTCPHO_MAX                     0x7fU
 688
 689         /* Second doubleword. */
 690 #define TCPHO_SHIFT                     18
 691 #define TCPHO_MAX                       0x3ffU
 692 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 693         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 694         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 695         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 696         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 697 };
 698
 699 enum rtl_rx_desc_bit {
 700         /* Rx private */
 701         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 702         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 703
 704 #define RxProtoUDP      (PID1)
 705 #define RxProtoTCP      (PID0)
 706 #define RxProtoIP       (PID1 | PID0)
 707 #define RxProtoMask     RxProtoIP
 708
 709         IPFail          = (1 << 16), /* IP checksum failed */
 710         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 711         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 712         RxVlanTag       = (1 << 16), /* VLAN tag available */
 713 };
 714
 715 #define RsvdMask        0x3fffc000
 716
 717 struct TxDesc {
 718         __le32 opts1;
 719         __le32 opts2;
 720         __le64 addr;
 721 };
 722
 723 struct RxDesc {
 724         __le32 opts1;
 725         __le32 opts2;
 726         __le64 addr;
 727 };
 728
 729 struct ring_info {
 730         struct sk_buff  *skb;
 731         u32             len;
 732         u8              __pad[sizeof(void *) - sizeof(u32)];
 733 };
 734
 735 enum features {
 736         RTL_FEATURE_WOL         = (1 << 0),
 737         RTL_FEATURE_MSI         = (1 << 1),
 738         RTL_FEATURE_GMII        = (1 << 2),
 739 };
 740
 741 struct rtl8169_counters {
 742         __le64  tx_packets;
 743         __le64  rx_packets;
 744         __le64  tx_errors;
 745         __le32  rx_errors;
 746         __le16  rx_missed;
 747         __le16  align_errors;
 748         __le32  tx_one_collision;
 749         __le32  tx_multi_collision;
 750         __le64  rx_unicast;
 751         __le64  rx_broadcast;
 752         __le32  rx_multicast;
 753         __le16  tx_aborted;
 754         __le16  tx_underun;
 755 };
 756
 757 struct rtl8169_tc_offsets {
 758         bool    inited;
 759         __le64  tx_errors;
 760         __le32  tx_multi_collision;
 761         __le16  tx_aborted;
 762 };
 763
 764 enum rtl_flag {
 765         RTL_FLAG_TASK_ENABLED = 0,
 766         RTL_FLAG_TASK_SLOW_PENDING,
 767         RTL_FLAG_TASK_RESET_PENDING,
 768         RTL_FLAG_TASK_PHY_PENDING,
 769         RTL_FLAG_MAX
 770 };
 771
 772 struct rtl8169_stats {
 773         u64                     packets;
 774         u64                     bytes;
 775         struct u64_stats_sync   syncp;
 776 };
 777
 778 struct rtl8169_private {
 779         void __iomem *mmio_addr;        /* memory map physical address */
 780         struct pci_dev *pci_dev;
 781         struct net_device *dev;
 782         struct napi_struct napi;
 783         u32 msg_enable;
 784         u16 txd_version;
 785         u16 mac_version;
 786         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 787         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 788         u32 dirty_tx;
 789         struct rtl8169_stats rx_stats;
 790         struct rtl8169_stats tx_stats;
 791         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 792         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 793         dma_addr_t TxPhyAddr;
 794         dma_addr_t RxPhyAddr;
 795         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 796         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 797         struct timer_list timer;
 798         u16 cp_cmd;
 799
 800         u16 event_slow;
 801
 802         struct mdio_ops {
 803                 void (*write)(struct rtl8169_private *, int, int);
 804                 int (*read)(struct rtl8169_private *, int);
 805         } mdio_ops;
 806
 807         struct pll_power_ops {
 808                 void (*down)(struct rtl8169_private *);
 809                 void (*up)(struct rtl8169_private *);
 810         } pll_power_ops;
 811
 812         struct jumbo_ops {
 813                 void (*enable)(struct rtl8169_private *);
 814                 void (*disable)(struct rtl8169_private *);
 815         } jumbo_ops;
 816
 817         struct csi_ops {
 818                 void (*write)(struct rtl8169_private *, int, int);
 819                 u32 (*read)(struct rtl8169_private *, int);
 820         } csi_ops;
 821
 822         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 823         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 824         void (*phy_reset_enable)(struct rtl8169_private *tp);
 825         void (*hw_start)(struct net_device *);
 826         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 827         unsigned int (*link_ok)(void __iomem *);
 828         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 829         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 830
 831         struct {
 832                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 833                 struct mutex mutex;
 834                 struct work_struct work;
 835         } wk;
 836
 837         unsigned features;
 838
 839         struct mii_if_info mii;
 840         dma_addr_t counters_phys_addr;
 841         struct rtl8169_counters *counters;
 842         struct rtl8169_tc_offsets tc_offset;
 843         u32 saved_wolopts;
 844         u32 opts1_mask;
 845
 846         struct rtl_fw {
 847                 const struct firmware *fw;
 848
 849 #define RTL_VER_SIZE            32
 850
 851                 char version[RTL_VER_SIZE];
 852
 853                 struct rtl_fw_phy_action {
 854                         __le32 *code;
 855                         size_t size;
 856                 } phy_action;
 857         } *rtl_fw;
 858 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 859
 860         u32 ocp_base;
 861 };
 862
 863 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 864 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 865 module_param(use_dac, int, 0);
 866 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 867 module_param_named(debug, debug.msg_enable, int, 0);
 868 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 869 MODULE_LICENSE("GPL");
 870 MODULE_VERSION(RTL8169_VERSION);
 871 /*(DEBLOBBED)*/
 872
 873 static void rtl_lock_work(struct rtl8169_private *tp)
 874 {
 875         mutex_lock(&tp->wk.mutex);
 876 }
 877
 878 static void rtl_unlock_work(struct rtl8169_private *tp)
 879 {
 880         mutex_unlock(&tp->wk.mutex);
 881 }
 882
 883 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 884 {
 885         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 886                                            PCI_EXP_DEVCTL_READRQ, force);
 887 }
 888
 889 struct rtl_cond {
 890         bool (*check)(struct rtl8169_private *);
 891         const char *msg;
 892 };
 893
 894 static void rtl_udelay(unsigned int d)
 895 {
 896         udelay(d);
 897 }
 898
 899 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 900                           void (*delay)(unsigned int), unsigned int d, int n,
 901                           bool high)
 902 {
 903         int i;
 904
 905         for (i = 0; i < n; i++) {
 906                 delay(d);
 907                 if (c->check(tp) == high)
 908                         return true;
 909         }
 910         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 911                   c->msg, !high, n, d);
 912         return false;
 913 }
 914
 915 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 916                                       const struct rtl_cond *c,
 917                                       unsigned int d, int n)
 918 {
 919         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 920 }
 921
 922 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 923                                      const struct rtl_cond *c,
 924                                      unsigned int d, int n)
 925 {
 926         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 927 }
 928
 929 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 930                                       const struct rtl_cond *c,
 931                                       unsigned int d, int n)
 932 {
 933         return rtl_loop_wait(tp, c, msleep, d, n, true);
 934 }
 935
 936 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 937                                      const struct rtl_cond *c,
 938                                      unsigned int d, int n)
 939 {
 940         return rtl_loop_wait(tp, c, msleep, d, n, false);
 941 }
 942
 943 #define DECLARE_RTL_COND(name)                          \
 944 static bool name ## _check(struct rtl8169_private *);   \
 945                                                         \
 946 static const struct rtl_cond name = {                   \
 947         .check  = name ## _check,                       \
 948         .msg    = #name                                 \
 949 };                                                      \
 950                                                         \
 951 static bool name ## _check(struct rtl8169_private *tp)
 952
 953 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 954 {
 955         if (reg & 0xffff0001) {
 956                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 957                 return true;
 958         }
 959         return false;
 960 }
 961
 962 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 963 {
 964         void __iomem *ioaddr = tp->mmio_addr;
 965
 966         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 967 }
 968
 969 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 970 {
 971         void __iomem *ioaddr = tp->mmio_addr;
 972
 973         if (rtl_ocp_reg_failure(tp, reg))
 974                 return;
 975
 976         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 977
 978         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 979 }
 980
 981 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 982 {
 983         void __iomem *ioaddr = tp->mmio_addr;
 984
 985         if (rtl_ocp_reg_failure(tp, reg))
 986                 return 0;
 987
 988         RTL_W32(GPHY_OCP, reg << 15);
 989
 990         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 991                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 992 }
 993
 994 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 995 {
 996         void __iomem *ioaddr = tp->mmio_addr;
 997
 998         if (rtl_ocp_reg_failure(tp, reg))
 999                 return;
1000
1001         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1002 }
1003
1004 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1005 {
1006         void __iomem *ioaddr = tp->mmio_addr;
1007
1008         if (rtl_ocp_reg_failure(tp, reg))
1009                 return 0;
1010
1011         RTL_W32(OCPDR, reg << 15);
1012
1013         return RTL_R32(OCPDR);
1014 }
1015
1016 #define OCP_STD_PHY_BASE        0xa400
1017
1018 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1019 {
1020         if (reg == 0x1f) {
1021                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1022                 return;
1023         }
1024
1025         if (tp->ocp_base != OCP_STD_PHY_BASE)
1026                 reg -= 0x10;
1027
1028         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1029 }
1030
1031 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1032 {
1033         if (tp->ocp_base != OCP_STD_PHY_BASE)
1034                 reg -= 0x10;
1035
1036         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1037 }
1038
1039 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1040 {
1041         if (reg == 0x1f) {
1042                 tp->ocp_base = value << 4;
1043                 return;
1044         }
1045
1046         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1047 }
1048
1049 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1050 {
1051         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1052 }
1053
1054 DECLARE_RTL_COND(rtl_phyar_cond)
1055 {
1056         void __iomem *ioaddr = tp->mmio_addr;
1057
1058         return RTL_R32(PHYAR) & 0x80000000;
1059 }
1060
1061 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1062 {
1063         void __iomem *ioaddr = tp->mmio_addr;
1064
1065         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1066
1067         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1068         /*
1069          * According to hardware specs a 20us delay is required after write
1070          * complete indication, but before sending next command.
1071          */
1072         udelay(20);
1073 }
1074
1075 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1076 {
1077         void __iomem *ioaddr = tp->mmio_addr;
1078         int value;
1079
1080         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1081
1082         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1083                 RTL_R32(PHYAR) & 0xffff : ~0;
1084
1085         /*
1086          * According to hardware specs a 20us delay is required after read
1087          * complete indication, but before sending next command.
1088          */
1089         udelay(20);
1090
1091         return value;
1092 }
1093
1094 DECLARE_RTL_COND(rtl_ocpar_cond)
1095 {
1096         void __iomem *ioaddr = tp->mmio_addr;
1097
1098         return RTL_R32(OCPAR) & OCPAR_FLAG;
1099 }
1100
1101 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1102 {
1103         void __iomem *ioaddr = tp->mmio_addr;
1104
1105         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1106         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1107         RTL_W32(EPHY_RXER_NUM, 0);
1108
1109         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1110 }
1111
1112 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1113 {
1114         r8168dp_1_mdio_access(tp, reg,
1115                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1116 }
1117
1118 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1119 {
1120         void __iomem *ioaddr = tp->mmio_addr;
1121
1122         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1123
1124         mdelay(1);
1125         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1126         RTL_W32(EPHY_RXER_NUM, 0);
1127
1128         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1129                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1130 }
1131
1132 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1133
1134 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1135 {
1136         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1137 }
1138
1139 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1140 {
1141         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1142 }
1143
1144 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1145 {
1146         void __iomem *ioaddr = tp->mmio_addr;
1147
1148         r8168dp_2_mdio_start(ioaddr);
1149
1150         r8169_mdio_write(tp, reg, value);
1151
1152         r8168dp_2_mdio_stop(ioaddr);
1153 }
1154
1155 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1156 {
1157         void __iomem *ioaddr = tp->mmio_addr;
1158         int value;
1159
1160         r8168dp_2_mdio_start(ioaddr);
1161
1162         value = r8169_mdio_read(tp, reg);
1163
1164         r8168dp_2_mdio_stop(ioaddr);
1165
1166         return value;
1167 }
1168
1169 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1170 {
1171         tp->mdio_ops.write(tp, location, val);
1172 }
1173
1174 static int rtl_readphy(struct rtl8169_private *tp, int location)
1175 {
1176         return tp->mdio_ops.read(tp, location);
1177 }
1178
1179 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1180 {
1181         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1182 }
1183
1184 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1185 {
1186         int val;
1187
1188         val = rtl_readphy(tp, reg_addr);
1189         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1190 }
1191
1192 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1193                            int val)
1194 {
1195         struct rtl8169_private *tp = netdev_priv(dev);
1196
1197         rtl_writephy(tp, location, val);
1198 }
1199
1200 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1201 {
1202         struct rtl8169_private *tp = netdev_priv(dev);
1203
1204         return rtl_readphy(tp, location);
1205 }
1206
1207 DECLARE_RTL_COND(rtl_ephyar_cond)
1208 {
1209         void __iomem *ioaddr = tp->mmio_addr;
1210
1211         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1212 }
1213
1214 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1215 {
1216         void __iomem *ioaddr = tp->mmio_addr;
1217
1218         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1219                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1220
1221         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1222
1223         udelay(10);
1224 }
1225
1226 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1227 {
1228         void __iomem *ioaddr = tp->mmio_addr;
1229
1230         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1231
1232         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1233                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1234 }
1235
1236 DECLARE_RTL_COND(rtl_eriar_cond)
1237 {
1238         void __iomem *ioaddr = tp->mmio_addr;
1239
1240         return RTL_R32(ERIAR) & ERIAR_FLAG;
1241 }
1242
1243 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1244                           u32 val, int type)
1245 {
1246         void __iomem *ioaddr = tp->mmio_addr;
1247
1248         BUG_ON((addr & 3) || (mask == 0));
1249         RTL_W32(ERIDR, val);
1250         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1251
1252         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1253 }
1254
1255 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1256 {
1257         void __iomem *ioaddr = tp->mmio_addr;
1258
1259         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1260
1261         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1262                 RTL_R32(ERIDR) : ~0;
1263 }
1264
1265 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1266                          u32 m, int type)
1267 {
1268         u32 val;
1269
1270         val = rtl_eri_read(tp, addr, type);
1271         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1272 }
1273
1274 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1275 {
1276         void __iomem *ioaddr = tp->mmio_addr;
1277
1278         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1279         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1280                 RTL_R32(OCPDR) : ~0;
1281 }
1282
1283 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1284 {
1285         return rtl_eri_read(tp, reg, ERIAR_OOB);
1286 }
1287
1288 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289 {
1290         switch (tp->mac_version) {
1291         case RTL_GIGA_MAC_VER_27:
1292         case RTL_GIGA_MAC_VER_28:
1293         case RTL_GIGA_MAC_VER_31:
1294                 return r8168dp_ocp_read(tp, mask, reg);
1295         case RTL_GIGA_MAC_VER_49:
1296         case RTL_GIGA_MAC_VER_50:
1297         case RTL_GIGA_MAC_VER_51:
1298                 return r8168ep_ocp_read(tp, mask, reg);
1299         default:
1300                 BUG();
1301                 return ~0;
1302         }
1303 }
1304
1305 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1306                               u32 data)
1307 {
1308         void __iomem *ioaddr = tp->mmio_addr;
1309
1310         RTL_W32(OCPDR, data);
1311         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1312         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1313 }
1314
1315 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1316                               u32 data)
1317 {
1318         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1319                       data, ERIAR_OOB);
1320 }
1321
1322 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1323 {
1324         switch (tp->mac_version) {
1325         case RTL_GIGA_MAC_VER_27:
1326         case RTL_GIGA_MAC_VER_28:
1327         case RTL_GIGA_MAC_VER_31:
1328                 r8168dp_ocp_write(tp, mask, reg, data);
1329                 break;
1330         case RTL_GIGA_MAC_VER_49:
1331         case RTL_GIGA_MAC_VER_50:
1332         case RTL_GIGA_MAC_VER_51:
1333                 r8168ep_ocp_write(tp, mask, reg, data);
1334                 break;
1335         default:
1336                 BUG();
1337                 break;
1338         }
1339 }
1340
1341 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1342 {
1343         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1344
1345         ocp_write(tp, 0x1, 0x30, 0x00000001);
1346 }
1347
1348 #define OOB_CMD_RESET           0x00
1349 #define OOB_CMD_DRIVER_START    0x05
1350 #define OOB_CMD_DRIVER_STOP     0x06
1351
1352 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1353 {
1354         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1355 }
1356
1357 DECLARE_RTL_COND(rtl_ocp_read_cond)
1358 {
1359         u16 reg;
1360
1361         reg = rtl8168_get_ocp_reg(tp);
1362
1363         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1364 }
1365
1366 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1367 {
1368         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1369 }
1370
1371 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1372 {
1373         void __iomem *ioaddr = tp->mmio_addr;
1374
1375         return RTL_R8(IBISR0) & 0x20;
1376 }
1377
1378 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1379 {
1380         void __iomem *ioaddr = tp->mmio_addr;
1381
1382         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1383         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1384         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1385         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1386 }
1387
1388 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1389 {
1390         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1391         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1392 }
1393
1394 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1395 {
1396         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1397         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1398         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1399 }
1400
1401 static void rtl8168_driver_start(struct rtl8169_private *tp)
1402 {
1403         switch (tp->mac_version) {
1404         case RTL_GIGA_MAC_VER_27:
1405         case RTL_GIGA_MAC_VER_28:
1406         case RTL_GIGA_MAC_VER_31:
1407                 rtl8168dp_driver_start(tp);
1408                 break;
1409         case RTL_GIGA_MAC_VER_49:
1410         case RTL_GIGA_MAC_VER_50:
1411         case RTL_GIGA_MAC_VER_51:
1412                 rtl8168ep_driver_start(tp);
1413                 break;
1414         default:
1415                 BUG();
1416                 break;
1417         }
1418 }
1419
1420 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1421 {
1422         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1423         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1424 }
1425
1426 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1427 {
1428         rtl8168ep_stop_cmac(tp);
1429         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1430         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1431         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1432 }
1433
1434 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1435 {
1436         switch (tp->mac_version) {
1437         case RTL_GIGA_MAC_VER_27:
1438         case RTL_GIGA_MAC_VER_28:
1439         case RTL_GIGA_MAC_VER_31:
1440                 rtl8168dp_driver_stop(tp);
1441                 break;
1442         case RTL_GIGA_MAC_VER_49:
1443         case RTL_GIGA_MAC_VER_50:
1444         case RTL_GIGA_MAC_VER_51:
1445                 rtl8168ep_driver_stop(tp);
1446                 break;
1447         default:
1448                 BUG();
1449                 break;
1450         }
1451 }
1452
1453 static int r8168dp_check_dash(struct rtl8169_private *tp)
1454 {
1455         u16 reg = rtl8168_get_ocp_reg(tp);
1456
1457         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1458 }
1459
1460 static int r8168ep_check_dash(struct rtl8169_private *tp)
1461 {
1462         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1463 }
1464
1465 static int r8168_check_dash(struct rtl8169_private *tp)
1466 {
1467         switch (tp->mac_version) {
1468         case RTL_GIGA_MAC_VER_27:
1469         case RTL_GIGA_MAC_VER_28:
1470         case RTL_GIGA_MAC_VER_31:
1471                 return r8168dp_check_dash(tp);
1472         case RTL_GIGA_MAC_VER_49:
1473         case RTL_GIGA_MAC_VER_50:
1474         case RTL_GIGA_MAC_VER_51:
1475                 return r8168ep_check_dash(tp);
1476         default:
1477                 return 0;
1478         }
1479 }
1480
1481 struct exgmac_reg {
1482         u16 addr;
1483         u16 mask;
1484         u32 val;
1485 };
1486
1487 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1488                                    const struct exgmac_reg *r, int len)
1489 {
1490         while (len-- > 0) {
1491                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1492                 r++;
1493         }
1494 }
1495
1496 DECLARE_RTL_COND(rtl_efusear_cond)
1497 {
1498         void __iomem *ioaddr = tp->mmio_addr;
1499
1500         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1501 }
1502
1503 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1504 {
1505         void __iomem *ioaddr = tp->mmio_addr;
1506
1507         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1508
1509         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1510                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1511 }
1512
1513 static u16 rtl_get_events(struct rtl8169_private *tp)
1514 {
1515         void __iomem *ioaddr = tp->mmio_addr;
1516
1517         return RTL_R16(IntrStatus);
1518 }
1519
1520 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1521 {
1522         void __iomem *ioaddr = tp->mmio_addr;
1523
1524         RTL_W16(IntrStatus, bits);
1525         mmiowb();
1526 }
1527
1528 static void rtl_irq_disable(struct rtl8169_private *tp)
1529 {
1530         void __iomem *ioaddr = tp->mmio_addr;
1531
1532         RTL_W16(IntrMask, 0);
1533         mmiowb();
1534 }
1535
1536 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1537 {
1538         void __iomem *ioaddr = tp->mmio_addr;
1539
1540         RTL_W16(IntrMask, bits);
1541 }
1542
1543 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1544 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1545 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1546
1547 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1548 {
1549         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1550 }
1551
1552 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1553 {
1554         void __iomem *ioaddr = tp->mmio_addr;
1555
1556         rtl_irq_disable(tp);
1557         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1558         RTL_R8(ChipCmd);
1559 }
1560
1561 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1562 {
1563         void __iomem *ioaddr = tp->mmio_addr;
1564
1565         return RTL_R32(TBICSR) & TBIReset;
1566 }
1567
1568 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1569 {
1570         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1571 }
1572
1573 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1574 {
1575         return RTL_R32(TBICSR) & TBILinkOk;
1576 }
1577
1578 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1579 {
1580         return RTL_R8(PHYstatus) & LinkStatus;
1581 }
1582
1583 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1584 {
1585         void __iomem *ioaddr = tp->mmio_addr;
1586
1587         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1588 }
1589
1590 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1591 {
1592         unsigned int val;
1593
1594         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1595         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1596 }
1597
1598 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1599 {
1600         void __iomem *ioaddr = tp->mmio_addr;
1601         struct net_device *dev = tp->dev;
1602
1603         if (!netif_running(dev))
1604                 return;
1605
1606         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1607             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1608                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1609                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1610                                       ERIAR_EXGMAC);
1611                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1612                                       ERIAR_EXGMAC);
1613                 } else if (RTL_R8(PHYstatus) & _100bps) {
1614                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1615                                       ERIAR_EXGMAC);
1616                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1617                                       ERIAR_EXGMAC);
1618                 } else {
1619                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1620                                       ERIAR_EXGMAC);
1621                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1622                                       ERIAR_EXGMAC);
1623                 }
1624                 /* Reset packet filter */
1625                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1626                              ERIAR_EXGMAC);
1627                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1628                              ERIAR_EXGMAC);
1629         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1630                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1631                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1632                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1633                                       ERIAR_EXGMAC);
1634                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1635                                       ERIAR_EXGMAC);
1636                 } else {
1637                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1638                                       ERIAR_EXGMAC);
1639                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1640                                       ERIAR_EXGMAC);
1641                 }
1642         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1643                 if (RTL_R8(PHYstatus) & _10bps) {
1644                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1645                                       ERIAR_EXGMAC);
1646                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1647                                       ERIAR_EXGMAC);
1648                 } else {
1649                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1650                                       ERIAR_EXGMAC);
1651                 }
1652         }
1653 }
1654
1655 static void __rtl8169_check_link_status(struct net_device *dev,
1656                                         struct rtl8169_private *tp,
1657                                         void __iomem *ioaddr, bool pm)
1658 {
1659         if (tp->link_ok(ioaddr)) {
1660                 rtl_link_chg_patch(tp);
1661                 /* This is to cancel a scheduled suspend if there's one. */
1662                 if (pm)
1663                         pm_request_resume(&tp->pci_dev->dev);
1664                 netif_carrier_on(dev);
1665                 if (net_ratelimit())
1666                         netif_info(tp, ifup, dev, "link up\n");
1667         } else {
1668                 netif_carrier_off(dev);
1669                 netif_info(tp, ifdown, dev, "link down\n");
1670                 if (pm)
1671                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1672         }
1673 }
1674
1675 static void rtl8169_check_link_status(struct net_device *dev,
1676                                       struct rtl8169_private *tp,
1677                                       void __iomem *ioaddr)
1678 {
1679         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1680 }
1681
1682 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1683
1684 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1685 {
1686         void __iomem *ioaddr = tp->mmio_addr;
1687         u8 options;
1688         u32 wolopts = 0;
1689
1690         options = RTL_R8(Config1);
1691         if (!(options & PMEnable))
1692                 return 0;
1693
1694         options = RTL_R8(Config3);
1695         if (options & LinkUp)
1696                 wolopts |= WAKE_PHY;
1697         switch (tp->mac_version) {
1698         case RTL_GIGA_MAC_VER_34:
1699         case RTL_GIGA_MAC_VER_35:
1700         case RTL_GIGA_MAC_VER_36:
1701         case RTL_GIGA_MAC_VER_37:
1702         case RTL_GIGA_MAC_VER_38:
1703         case RTL_GIGA_MAC_VER_40:
1704         case RTL_GIGA_MAC_VER_41:
1705         case RTL_GIGA_MAC_VER_42:
1706         case RTL_GIGA_MAC_VER_43:
1707         case RTL_GIGA_MAC_VER_44:
1708         case RTL_GIGA_MAC_VER_45:
1709         case RTL_GIGA_MAC_VER_46:
1710         case RTL_GIGA_MAC_VER_47:
1711         case RTL_GIGA_MAC_VER_48:
1712         case RTL_GIGA_MAC_VER_49:
1713         case RTL_GIGA_MAC_VER_50:
1714         case RTL_GIGA_MAC_VER_51:
1715                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1716                         wolopts |= WAKE_MAGIC;
1717                 break;
1718         default:
1719                 if (options & MagicPacket)
1720                         wolopts |= WAKE_MAGIC;
1721                 break;
1722         }
1723
1724         options = RTL_R8(Config5);
1725         if (options & UWF)
1726                 wolopts |= WAKE_UCAST;
1727         if (options & BWF)
1728                 wolopts |= WAKE_BCAST;
1729         if (options & MWF)
1730                 wolopts |= WAKE_MCAST;
1731
1732         return wolopts;
1733 }
1734
1735 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738         struct device *d = &tp->pci_dev->dev;
1739
1740         pm_runtime_get_noresume(d);
1741
1742         rtl_lock_work(tp);
1743
1744         wol->supported = WAKE_ANY;
1745         if (pm_runtime_active(d))
1746                 wol->wolopts = __rtl8169_get_wol(tp);
1747         else
1748                 wol->wolopts = tp->saved_wolopts;
1749
1750         rtl_unlock_work(tp);
1751
1752         pm_runtime_put_noidle(d);
1753 }
1754
1755 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1756 {
1757         void __iomem *ioaddr = tp->mmio_addr;
1758         unsigned int i, tmp;
1759         static const struct {
1760                 u32 opt;
1761                 u16 reg;
1762                 u8  mask;
1763         } cfg[] = {
1764                 { WAKE_PHY,   Config3, LinkUp },
1765                 { WAKE_UCAST, Config5, UWF },
1766                 { WAKE_BCAST, Config5, BWF },
1767                 { WAKE_MCAST, Config5, MWF },
1768                 { WAKE_ANY,   Config5, LanWake },
1769                 { WAKE_MAGIC, Config3, MagicPacket }
1770         };
1771         u8 options;
1772
1773         RTL_W8(Cfg9346, Cfg9346_Unlock);
1774
1775         switch (tp->mac_version) {
1776         case RTL_GIGA_MAC_VER_34:
1777         case RTL_GIGA_MAC_VER_35:
1778         case RTL_GIGA_MAC_VER_36:
1779         case RTL_GIGA_MAC_VER_37:
1780         case RTL_GIGA_MAC_VER_38:
1781         case RTL_GIGA_MAC_VER_40:
1782         case RTL_GIGA_MAC_VER_41:
1783         case RTL_GIGA_MAC_VER_42:
1784         case RTL_GIGA_MAC_VER_43:
1785         case RTL_GIGA_MAC_VER_44:
1786         case RTL_GIGA_MAC_VER_45:
1787         case RTL_GIGA_MAC_VER_46:
1788         case RTL_GIGA_MAC_VER_47:
1789         case RTL_GIGA_MAC_VER_48:
1790         case RTL_GIGA_MAC_VER_49:
1791         case RTL_GIGA_MAC_VER_50:
1792         case RTL_GIGA_MAC_VER_51:
1793                 tmp = ARRAY_SIZE(cfg) - 1;
1794                 if (wolopts & WAKE_MAGIC)
1795                         rtl_w0w1_eri(tp,
1796                                      0x0dc,
1797                                      ERIAR_MASK_0100,
1798                                      MagicPacket_v2,
1799                                      0x0000,
1800                                      ERIAR_EXGMAC);
1801                 else
1802                         rtl_w0w1_eri(tp,
1803                                      0x0dc,
1804                                      ERIAR_MASK_0100,
1805                                      0x0000,
1806                                      MagicPacket_v2,
1807                                      ERIAR_EXGMAC);
1808                 break;
1809         default:
1810                 tmp = ARRAY_SIZE(cfg);
1811                 break;
1812         }
1813
1814         for (i = 0; i < tmp; i++) {
1815                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1816                 if (wolopts & cfg[i].opt)
1817                         options |= cfg[i].mask;
1818                 RTL_W8(cfg[i].reg, options);
1819         }
1820
1821         switch (tp->mac_version) {
1822         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1823                 options = RTL_R8(Config1) & ~PMEnable;
1824                 if (wolopts)
1825                         options |= PMEnable;
1826                 RTL_W8(Config1, options);
1827                 break;
1828         default:
1829                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1830                 if (wolopts)
1831                         options |= PME_SIGNAL;
1832                 RTL_W8(Config2, options);
1833                 break;
1834         }
1835
1836         RTL_W8(Cfg9346, Cfg9346_Lock);
1837 }
1838
1839 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1840 {
1841         struct rtl8169_private *tp = netdev_priv(dev);
1842         struct device *d = &tp->pci_dev->dev;
1843
1844         pm_runtime_get_noresume(d);
1845
1846         rtl_lock_work(tp);
1847
1848         if (wol->wolopts)
1849                 tp->features |= RTL_FEATURE_WOL;
1850         else
1851                 tp->features &= ~RTL_FEATURE_WOL;
1852         if (pm_runtime_active(d))
1853                 __rtl8169_set_wol(tp, wol->wolopts);
1854         else
1855                 tp->saved_wolopts = wol->wolopts;
1856
1857         rtl_unlock_work(tp);
1858
1859         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1860
1861         pm_runtime_put_noidle(d);
1862
1863         return 0;
1864 }
1865
1866 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1867 {
1868         return rtl_chip_infos[tp->mac_version].fw_name;
1869 }
1870
1871 static void rtl8169_get_drvinfo(struct net_device *dev,
1872                                 struct ethtool_drvinfo *info)
1873 {
1874         struct rtl8169_private *tp = netdev_priv(dev);
1875         struct rtl_fw *rtl_fw = tp->rtl_fw;
1876
1877         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1878         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1879         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1880         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1881         if (!IS_ERR_OR_NULL(rtl_fw))
1882                 strlcpy(info->fw_version, rtl_fw->version,
1883                         sizeof(info->fw_version));
1884 }
1885
1886 static int rtl8169_get_regs_len(struct net_device *dev)
1887 {
1888         return R8169_REGS_SIZE;
1889 }
1890
1891 static int rtl8169_set_speed_tbi(struct net_device *dev,
1892                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1893 {
1894         struct rtl8169_private *tp = netdev_priv(dev);
1895         void __iomem *ioaddr = tp->mmio_addr;
1896         int ret = 0;
1897         u32 reg;
1898
1899         reg = RTL_R32(TBICSR);
1900         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1901             (duplex == DUPLEX_FULL)) {
1902                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1903         } else if (autoneg == AUTONEG_ENABLE)
1904                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1905         else {
1906                 netif_warn(tp, link, dev,
1907                            "incorrect speed setting refused in TBI mode\n");
1908                 ret = -EOPNOTSUPP;
1909         }
1910
1911         return ret;
1912 }
1913
1914 static int rtl8169_set_speed_xmii(struct net_device *dev,
1915                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1916 {
1917         struct rtl8169_private *tp = netdev_priv(dev);
1918         int giga_ctrl, bmcr;
1919         int rc = -EINVAL;
1920
1921         rtl_writephy(tp, 0x1f, 0x0000);
1922
1923         if (autoneg == AUTONEG_ENABLE) {
1924                 int auto_nego;
1925
1926                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1927                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1928                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1929
1930                 if (adv & ADVERTISED_10baseT_Half)
1931                         auto_nego |= ADVERTISE_10HALF;
1932                 if (adv & ADVERTISED_10baseT_Full)
1933                         auto_nego |= ADVERTISE_10FULL;
1934                 if (adv & ADVERTISED_100baseT_Half)
1935                         auto_nego |= ADVERTISE_100HALF;
1936                 if (adv & ADVERTISED_100baseT_Full)
1937                         auto_nego |= ADVERTISE_100FULL;
1938
1939                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1940
1941                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1942                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1943
1944                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1945                 if (tp->mii.supports_gmii) {
1946                         if (adv & ADVERTISED_1000baseT_Half)
1947                                 giga_ctrl |= ADVERTISE_1000HALF;
1948                         if (adv & ADVERTISED_1000baseT_Full)
1949                                 giga_ctrl |= ADVERTISE_1000FULL;
1950                 } else if (adv & (ADVERTISED_1000baseT_Half |
1951                                   ADVERTISED_1000baseT_Full)) {
1952                         netif_info(tp, link, dev,
1953                                    "PHY does not support 1000Mbps\n");
1954                         goto out;
1955                 }
1956
1957                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1958
1959                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1960                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1961         } else {
1962                 giga_ctrl = 0;
1963
1964                 if (speed == SPEED_10)
1965                         bmcr = 0;
1966                 else if (speed == SPEED_100)
1967                         bmcr = BMCR_SPEED100;
1968                 else
1969                         goto out;
1970
1971                 if (duplex == DUPLEX_FULL)
1972                         bmcr |= BMCR_FULLDPLX;
1973         }
1974
1975         rtl_writephy(tp, MII_BMCR, bmcr);
1976
1977         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1978             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1979                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1980                         rtl_writephy(tp, 0x17, 0x2138);
1981                         rtl_writephy(tp, 0x0e, 0x0260);
1982                 } else {
1983                         rtl_writephy(tp, 0x17, 0x2108);
1984                         rtl_writephy(tp, 0x0e, 0x0000);
1985                 }
1986         }
1987
1988         rc = 0;
1989 out:
1990         return rc;
1991 }
1992
1993 static int rtl8169_set_speed(struct net_device *dev,
1994                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1995 {
1996         struct rtl8169_private *tp = netdev_priv(dev);
1997         int ret;
1998
1999         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2000         if (ret < 0)
2001                 goto out;
2002
2003         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2004             (advertising & ADVERTISED_1000baseT_Full) &&
2005             !pci_is_pcie(tp->pci_dev)) {
2006                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2007         }
2008 out:
2009         return ret;
2010 }
2011
2012 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2013 {
2014         struct rtl8169_private *tp = netdev_priv(dev);
2015         int ret;
2016
2017         del_timer_sync(&tp->timer);
2018
2019         rtl_lock_work(tp);
2020         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2021                                 cmd->duplex, cmd->advertising);
2022         rtl_unlock_work(tp);
2023
2024         return ret;
2025 }
2026
2027 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2028         netdev_features_t features)
2029 {
2030         struct rtl8169_private *tp = netdev_priv(dev);
2031
2032         if (dev->mtu > TD_MSS_MAX)
2033                 features &= ~NETIF_F_ALL_TSO;
2034
2035         if (dev->mtu > JUMBO_1K &&
2036             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2037                 features &= ~NETIF_F_IP_CSUM;
2038
2039         return features;
2040 }
2041
2042 static void __rtl8169_set_features(struct net_device *dev,
2043                                    netdev_features_t features)
2044 {
2045         struct rtl8169_private *tp = netdev_priv(dev);
2046         void __iomem *ioaddr = tp->mmio_addr;
2047         u32 rx_config;
2048
2049         rx_config = RTL_R32(RxConfig);
2050         if (features & NETIF_F_RXALL)
2051                 rx_config |= (AcceptErr | AcceptRunt);
2052         else
2053                 rx_config &= ~(AcceptErr | AcceptRunt);
2054
2055         RTL_W32(RxConfig, rx_config);
2056
2057         if (features & NETIF_F_RXCSUM)
2058                 tp->cp_cmd |= RxChkSum;
2059         else
2060                 tp->cp_cmd &= ~RxChkSum;
2061
2062         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2063                 tp->cp_cmd |= RxVlan;
2064         else
2065                 tp->cp_cmd &= ~RxVlan;
2066
2067         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2068
2069         RTL_W16(CPlusCmd, tp->cp_cmd);
2070         RTL_R16(CPlusCmd);
2071 }
2072
2073 static int rtl8169_set_features(struct net_device *dev,
2074                                 netdev_features_t features)
2075 {
2076         struct rtl8169_private *tp = netdev_priv(dev);
2077
2078         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2079
2080         rtl_lock_work(tp);
2081         if (features ^ dev->features)
2082                 __rtl8169_set_features(dev, features);
2083         rtl_unlock_work(tp);
2084
2085         return 0;
2086 }
2087
2088
2089 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2090 {
2091         return (skb_vlan_tag_present(skb)) ?
2092                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2093 }
2094
2095 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2096 {
2097         u32 opts2 = le32_to_cpu(desc->opts2);
2098
2099         if (opts2 & RxVlanTag)
2100                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2101 }
2102
2103 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2104 {
2105         struct rtl8169_private *tp = netdev_priv(dev);
2106         void __iomem *ioaddr = tp->mmio_addr;
2107         u32 status;
2108
2109         cmd->supported =
2110                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2111         cmd->port = PORT_FIBRE;
2112         cmd->transceiver = XCVR_INTERNAL;
2113
2114         status = RTL_R32(TBICSR);
2115         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2116         cmd->autoneg = !!(status & TBINwEnable);
2117
2118         ethtool_cmd_speed_set(cmd, SPEED_1000);
2119         cmd->duplex = DUPLEX_FULL; /* Always set */
2120
2121         return 0;
2122 }
2123
2124 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2125 {
2126         struct rtl8169_private *tp = netdev_priv(dev);
2127
2128         return mii_ethtool_gset(&tp->mii, cmd);
2129 }
2130
2131 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2132 {
2133         struct rtl8169_private *tp = netdev_priv(dev);
2134         int rc;
2135
2136         rtl_lock_work(tp);
2137         rc = tp->get_settings(dev, cmd);
2138         rtl_unlock_work(tp);
2139
2140         return rc;
2141 }
2142
2143 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2144                              void *p)
2145 {
2146         struct rtl8169_private *tp = netdev_priv(dev);
2147         u32 __iomem *data = tp->mmio_addr;
2148         u32 *dw = p;
2149         int i;
2150
2151         rtl_lock_work(tp);
2152         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2153                 memcpy_fromio(dw++, data++, 4);
2154         rtl_unlock_work(tp);
2155 }
2156
2157 static u32 rtl8169_get_msglevel(struct net_device *dev)
2158 {
2159         struct rtl8169_private *tp = netdev_priv(dev);
2160
2161         return tp->msg_enable;
2162 }
2163
2164 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2165 {
2166         struct rtl8169_private *tp = netdev_priv(dev);
2167
2168         tp->msg_enable = value;
2169 }
2170
2171 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2172         "tx_packets",
2173         "rx_packets",
2174         "tx_errors",
2175         "rx_errors",
2176         "rx_missed",
2177         "align_errors",
2178         "tx_single_collisions",
2179         "tx_multi_collisions",
2180         "unicast",
2181         "broadcast",
2182         "multicast",
2183         "tx_aborted",
2184         "tx_underrun",
2185 };
2186
2187 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2188 {
2189         switch (sset) {
2190         case ETH_SS_STATS:
2191                 return ARRAY_SIZE(rtl8169_gstrings);
2192         default:
2193                 return -EOPNOTSUPP;
2194         }
2195 }
2196
2197 DECLARE_RTL_COND(rtl_counters_cond)
2198 {
2199         void __iomem *ioaddr = tp->mmio_addr;
2200
2201         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2202 }
2203
2204 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2205 {
2206         struct rtl8169_private *tp = netdev_priv(dev);
2207         void __iomem *ioaddr = tp->mmio_addr;
2208         dma_addr_t paddr = tp->counters_phys_addr;
2209         u32 cmd;
2210
2211         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2212         RTL_R32(CounterAddrHigh);
2213         cmd = (u64)paddr & DMA_BIT_MASK(32);
2214         RTL_W32(CounterAddrLow, cmd);
2215         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2216
2217         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2218 }
2219
2220 static bool rtl8169_reset_counters(struct net_device *dev)
2221 {
2222         struct rtl8169_private *tp = netdev_priv(dev);
2223
2224         /*
2225          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2226          * tally counters.
2227          */
2228         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2229                 return true;
2230
2231         return rtl8169_do_counters(dev, CounterReset);
2232 }
2233
2234 static bool rtl8169_update_counters(struct net_device *dev)
2235 {
2236         struct rtl8169_private *tp = netdev_priv(dev);
2237         void __iomem *ioaddr = tp->mmio_addr;
2238
2239         /*
2240          * Some chips are unable to dump tally counters when the receiver
2241          * is disabled.
2242          */
2243         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2244                 return true;
2245
2246         return rtl8169_do_counters(dev, CounterDump);
2247 }
2248
2249 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2250 {
2251         struct rtl8169_private *tp = netdev_priv(dev);
2252         struct rtl8169_counters *counters = tp->counters;
2253         bool ret = false;
2254
2255         /*
2256          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2257          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2258          * reset by a power cycle, while the counter values collected by the
2259          * driver are reset at every driver unload/load cycle.
2260          *
2261          * To make sure the HW values returned by @get_stats64 match the SW
2262          * values, we collect the initial values at first open(*) and use them
2263          * as offsets to normalize the values returned by @get_stats64.
2264          *
2265          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2266          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2267          * set at open time by rtl_hw_start.
2268          */
2269
2270         if (tp->tc_offset.inited)
2271                 return true;
2272
2273         /* If both, reset and update fail, propagate to caller. */
2274         if (rtl8169_reset_counters(dev))
2275                 ret = true;
2276
2277         if (rtl8169_update_counters(dev))
2278                 ret = true;
2279
2280         tp->tc_offset.tx_errors = counters->tx_errors;
2281         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2282         tp->tc_offset.tx_aborted = counters->tx_aborted;
2283         tp->tc_offset.inited = true;
2284
2285         return ret;
2286 }
2287
2288 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2289                                       struct ethtool_stats *stats, u64 *data)
2290 {
2291         struct rtl8169_private *tp = netdev_priv(dev);
2292         struct device *d = &tp->pci_dev->dev;
2293         struct rtl8169_counters *counters = tp->counters;
2294
2295         ASSERT_RTNL();
2296
2297         pm_runtime_get_noresume(d);
2298
2299         if (pm_runtime_active(d))
2300                 rtl8169_update_counters(dev);
2301
2302         pm_runtime_put_noidle(d);
2303
2304         data[0] = le64_to_cpu(counters->tx_packets);
2305         data[1] = le64_to_cpu(counters->rx_packets);
2306         data[2] = le64_to_cpu(counters->tx_errors);
2307         data[3] = le32_to_cpu(counters->rx_errors);
2308         data[4] = le16_to_cpu(counters->rx_missed);
2309         data[5] = le16_to_cpu(counters->align_errors);
2310         data[6] = le32_to_cpu(counters->tx_one_collision);
2311         data[7] = le32_to_cpu(counters->tx_multi_collision);
2312         data[8] = le64_to_cpu(counters->rx_unicast);
2313         data[9] = le64_to_cpu(counters->rx_broadcast);
2314         data[10] = le32_to_cpu(counters->rx_multicast);
2315         data[11] = le16_to_cpu(counters->tx_aborted);
2316         data[12] = le16_to_cpu(counters->tx_underun);
2317 }
2318
2319 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2320 {
2321         switch(stringset) {
2322         case ETH_SS_STATS:
2323                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
2324                 break;
2325         }
2326 }
2327
2328 static const struct ethtool_ops rtl8169_ethtool_ops = {
2329         .get_drvinfo            = rtl8169_get_drvinfo,
2330         .get_regs_len           = rtl8169_get_regs_len,
2331         .get_link               = ethtool_op_get_link,
2332         .get_settings           = rtl8169_get_settings,
2333         .set_settings           = rtl8169_set_settings,
2334         .get_msglevel           = rtl8169_get_msglevel,
2335         .set_msglevel           = rtl8169_set_msglevel,
2336         .get_regs               = rtl8169_get_regs,
2337         .get_wol                = rtl8169_get_wol,
2338         .set_wol                = rtl8169_set_wol,
2339         .get_strings            = rtl8169_get_strings,
2340         .get_sset_count         = rtl8169_get_sset_count,
2341         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2342         .get_ts_info            = ethtool_op_get_ts_info,
2343 };
2344
2345 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2346                                     struct net_device *dev, u8 default_version)
2347 {
2348         void __iomem *ioaddr = tp->mmio_addr;
2349         /*
2350          * The driver currently handles the 8168Bf and the 8168Be identically
2351          * but they can be identified more specifically through the test below
2352          * if needed:
2353          *
2354          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2355          *
2356          * Same thing for the 8101Eb and the 8101Ec:
2357          *
2358          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2359          */
2360         static const struct rtl_mac_info {
2361                 u32 mask;
2362                 u32 val;
2363                 int mac_version;
2364         } mac_info[] = {
2365                 /* 8168EP family. */
2366                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2367                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2368                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2369
2370                 /* 8168H family. */
2371                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2372                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2373
2374                 /* 8168G family. */
2375                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2376                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2377                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2378                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2379
2380                 /* 8168F family. */
2381                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2382                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2383                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2384
2385                 /* 8168E family. */
2386                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2387                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2388                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2389                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2390
2391                 /* 8168D family. */
2392                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2393                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2394                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2395
2396                 /* 8168DP family. */
2397                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2398                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2399                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2400
2401                 /* 8168C family. */
2402                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2403                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2404                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2405                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2406                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2407                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2408                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2409                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2410                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2411
2412                 /* 8168B family. */
2413                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2414                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2415                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2416                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2417
2418                 /* 8101 family. */
2419                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2420                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2421                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2422                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2423                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2424                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2425                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2426                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2427                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2428                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2429                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2430                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2431                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2432                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2433                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2434                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2435                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2436                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2437                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2438                 /* FIXME: where did these entries come from ? -- FR */
2439                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2440                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2441
2442                 /* 8110 family. */
2443                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2444                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2445                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2446                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2447                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2448                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2449
2450                 /* Catch-all */
2451                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2452         };
2453         const struct rtl_mac_info *p = mac_info;
2454         u32 reg;
2455
2456         reg = RTL_R32(TxConfig);
2457         while ((reg & p->mask) != p->val)
2458                 p++;
2459         tp->mac_version = p->mac_version;
2460
2461         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2462                 netif_notice(tp, probe, dev,
2463                              "unknown MAC, using family default\n");
2464                 tp->mac_version = default_version;
2465         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2466                 tp->mac_version = tp->mii.supports_gmii ?
2467                                   RTL_GIGA_MAC_VER_42 :
2468                                   RTL_GIGA_MAC_VER_43;
2469         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2470                 tp->mac_version = tp->mii.supports_gmii ?
2471                                   RTL_GIGA_MAC_VER_45 :
2472                                   RTL_GIGA_MAC_VER_47;
2473         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2474                 tp->mac_version = tp->mii.supports_gmii ?
2475                                   RTL_GIGA_MAC_VER_46 :
2476                                   RTL_GIGA_MAC_VER_48;
2477         }
2478 }
2479
2480 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2481 {
2482         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2483 }
2484
2485 struct phy_reg {
2486         u16 reg;
2487         u16 val;
2488 };
2489
2490 static void rtl_writephy_batch(struct rtl8169_private *tp,
2491                                const struct phy_reg *regs, int len)
2492 {
2493         while (len-- > 0) {
2494                 rtl_writephy(tp, regs->reg, regs->val);
2495                 regs++;
2496         }
2497 }
2498
2499 #define PHY_READ                0x00000000
2500 #define PHY_DATA_OR             0x10000000
2501 #define PHY_DATA_AND            0x20000000
2502 #define PHY_BJMPN               0x30000000
2503 #define PHY_MDIO_CHG            0x40000000
2504 #define PHY_CLEAR_READCOUNT     0x70000000
2505 #define PHY_WRITE               0x80000000
2506 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2507 #define PHY_COMP_EQ_SKIPN       0xa0000000
2508 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2509 #define PHY_WRITE_PREVIOUS      0xc0000000
2510 #define PHY_SKIPN               0xd0000000
2511 #define PHY_DELAY_MS            0xe0000000
2512
2513 struct fw_info {
2514         u32     magic;
2515         char    version[RTL_VER_SIZE];
2516         __le32  fw_start;
2517         __le32  fw_len;
2518         u8      chksum;
2519 } __packed;
2520
2521 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2522
2523 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2524 {
2525         const struct firmware *fw = rtl_fw->fw;
2526         struct fw_info *fw_info = (struct fw_info *)fw->data;
2527         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2528         char *version = rtl_fw->version;
2529         bool rc = false;
2530
2531         if (fw->size < FW_OPCODE_SIZE)
2532                 goto out;
2533
2534         if (!fw_info->magic) {
2535                 size_t i, size, start;
2536                 u8 checksum = 0;
2537
2538                 if (fw->size < sizeof(*fw_info))
2539                         goto out;
2540
2541                 for (i = 0; i < fw->size; i++)
2542                         checksum += fw->data[i];
2543                 if (checksum != 0)
2544                         goto out;
2545
2546                 start = le32_to_cpu(fw_info->fw_start);
2547                 if (start > fw->size)
2548                         goto out;
2549
2550                 size = le32_to_cpu(fw_info->fw_len);
2551                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2552                         goto out;
2553
2554                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2555
2556                 pa->code = (__le32 *)(fw->data + start);
2557                 pa->size = size;
2558         } else {
2559                 if (fw->size % FW_OPCODE_SIZE)
2560                         goto out;
2561
2562                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2563
2564                 pa->code = (__le32 *)fw->data;
2565                 pa->size = fw->size / FW_OPCODE_SIZE;
2566         }
2567         version[RTL_VER_SIZE - 1] = 0;
2568
2569         rc = true;
2570 out:
2571         return rc;
2572 }
2573
2574 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2575                            struct rtl_fw_phy_action *pa)
2576 {
2577         bool rc = false;
2578         size_t index;
2579
2580         for (index = 0; index < pa->size; index++) {
2581                 u32 action = le32_to_cpu(pa->code[index]);
2582                 u32 regno = (action & 0x0fff0000) >> 16;
2583
2584                 switch(action & 0xf0000000) {
2585                 case PHY_READ:
2586                 case PHY_DATA_OR:
2587                 case PHY_DATA_AND:
2588                 case PHY_MDIO_CHG:
2589                 case PHY_CLEAR_READCOUNT:
2590                 case PHY_WRITE:
2591                 case PHY_WRITE_PREVIOUS:
2592                 case PHY_DELAY_MS:
2593                         break;
2594
2595                 case PHY_BJMPN:
2596                         if (regno > index) {
2597                                 netif_err(tp, ifup, tp->dev,
2598                                           "Out of range of firmware\n");
2599                                 goto out;
2600                         }
2601                         break;
2602                 case PHY_READCOUNT_EQ_SKIP:
2603                         if (index + 2 >= pa->size) {
2604                                 netif_err(tp, ifup, tp->dev,
2605                                           "Out of range of firmware\n");
2606                                 goto out;
2607                         }
2608                         break;
2609                 case PHY_COMP_EQ_SKIPN:
2610                 case PHY_COMP_NEQ_SKIPN:
2611                 case PHY_SKIPN:
2612                         if (index + 1 + regno >= pa->size) {
2613                                 netif_err(tp, ifup, tp->dev,
2614                                           "Out of range of firmware\n");
2615                                 goto out;
2616                         }
2617                         break;
2618
2619                 default:
2620                         netif_err(tp, ifup, tp->dev,
2621                                   "Invalid action 0x%08x\n", action);
2622                         goto out;
2623                 }
2624         }
2625         rc = true;
2626 out:
2627         return rc;
2628 }
2629
2630 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2631 {
2632         struct net_device *dev = tp->dev;
2633         int rc = -EINVAL;
2634
2635         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2636                 netif_err(tp, ifup, dev, "invalid firmware\n");
2637                 goto out;
2638         }
2639
2640         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2641                 rc = 0;
2642 out:
2643         return rc;
2644 }
2645
2646 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2647 {
2648         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2649         struct mdio_ops org, *ops = &tp->mdio_ops;
2650         u32 predata, count;
2651         size_t index;
2652
2653         predata = count = 0;
2654         org.write = ops->write;
2655         org.read = ops->read;
2656
2657         for (index = 0; index < pa->size; ) {
2658                 u32 action = le32_to_cpu(pa->code[index]);
2659                 u32 data = action & 0x0000ffff;
2660                 u32 regno = (action & 0x0fff0000) >> 16;
2661
2662                 if (!action)
2663                         break;
2664
2665                 switch(action & 0xf0000000) {
2666                 case PHY_READ:
2667                         predata = rtl_readphy(tp, regno);
2668                         count++;
2669                         index++;
2670                         break;
2671                 case PHY_DATA_OR:
2672                         predata |= data;
2673                         index++;
2674                         break;
2675                 case PHY_DATA_AND:
2676                         predata &= data;
2677                         index++;
2678                         break;
2679                 case PHY_BJMPN:
2680                         index -= regno;
2681                         break;
2682                 case PHY_MDIO_CHG:
2683                         if (data == 0) {
2684                                 ops->write = org.write;
2685                                 ops->read = org.read;
2686                         } else if (data == 1) {
2687                                 ops->write = mac_mcu_write;
2688                                 ops->read = mac_mcu_read;
2689                         }
2690
2691                         index++;
2692                         break;
2693                 case PHY_CLEAR_READCOUNT:
2694                         count = 0;
2695                         index++;
2696                         break;
2697                 case PHY_WRITE:
2698                         rtl_writephy(tp, regno, data);
2699                         index++;
2700                         break;
2701                 case PHY_READCOUNT_EQ_SKIP:
2702                         index += (count == data) ? 2 : 1;
2703                         break;
2704                 case PHY_COMP_EQ_SKIPN:
2705                         if (predata == data)
2706                                 index += regno;
2707                         index++;
2708                         break;
2709                 case PHY_COMP_NEQ_SKIPN:
2710                         if (predata != data)
2711                                 index += regno;
2712                         index++;
2713                         break;
2714                 case PHY_WRITE_PREVIOUS:
2715                         rtl_writephy(tp, regno, predata);
2716                         index++;
2717                         break;
2718                 case PHY_SKIPN:
2719                         index += regno + 1;
2720                         break;
2721                 case PHY_DELAY_MS:
2722                         mdelay(data);
2723                         index++;
2724                         break;
2725
2726                 default:
2727                         BUG();
2728                 }
2729         }
2730
2731         ops->write = org.write;
2732         ops->read = org.read;
2733 }
2734
2735 static void rtl_release_firmware(struct rtl8169_private *tp)
2736 {
2737         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2738                 release_firmware(tp->rtl_fw->fw);
2739                 kfree(tp->rtl_fw);
2740         }
2741         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2742 }
2743
2744 static void rtl_apply_firmware(struct rtl8169_private *tp)
2745 {
2746         struct rtl_fw *rtl_fw = tp->rtl_fw;
2747
2748         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2749         if (!IS_ERR_OR_NULL(rtl_fw))
2750                 rtl_phy_write_fw(tp, rtl_fw);
2751 }
2752
2753 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2754 {
2755         if (rtl_readphy(tp, reg) != val)
2756                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2757         else
2758                 rtl_apply_firmware(tp);
2759 }
2760
2761 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2762 {
2763         static const struct phy_reg phy_reg_init[] = {
2764                 { 0x1f, 0x0001 },
2765                 { 0x06, 0x006e },
2766                 { 0x08, 0x0708 },
2767                 { 0x15, 0x4000 },
2768                 { 0x18, 0x65c7 },
2769
2770                 { 0x1f, 0x0001 },
2771                 { 0x03, 0x00a1 },
2772                 { 0x02, 0x0008 },
2773                 { 0x01, 0x0120 },
2774                 { 0x00, 0x1000 },
2775                 { 0x04, 0x0800 },
2776                 { 0x04, 0x0000 },
2777
2778                 { 0x03, 0xff41 },
2779                 { 0x02, 0xdf60 },
2780                 { 0x01, 0x0140 },
2781                 { 0x00, 0x0077 },
2782                 { 0x04, 0x7800 },
2783                 { 0x04, 0x7000 },
2784
2785                 { 0x03, 0x802f },
2786                 { 0x02, 0x4f02 },
2787                 { 0x01, 0x0409 },
2788                 { 0x00, 0xf0f9 },
2789                 { 0x04, 0x9800 },
2790                 { 0x04, 0x9000 },
2791
2792                 { 0x03, 0xdf01 },
2793                 { 0x02, 0xdf20 },
2794                 { 0x01, 0xff95 },
2795                 { 0x00, 0xba00 },
2796                 { 0x04, 0xa800 },
2797                 { 0x04, 0xa000 },
2798
2799                 { 0x03, 0xff41 },
2800                 { 0x02, 0xdf20 },
2801                 { 0x01, 0x0140 },
2802                 { 0x00, 0x00bb },
2803                 { 0x04, 0xb800 },
2804                 { 0x04, 0xb000 },
2805
2806                 { 0x03, 0xdf41 },
2807                 { 0x02, 0xdc60 },
2808                 { 0x01, 0x6340 },
2809                 { 0x00, 0x007d },
2810                 { 0x04, 0xd800 },
2811                 { 0x04, 0xd000 },
2812
2813                 { 0x03, 0xdf01 },
2814                 { 0x02, 0xdf20 },
2815                 { 0x01, 0x100a },
2816                 { 0x00, 0xa0ff },
2817                 { 0x04, 0xf800 },
2818                 { 0x04, 0xf000 },
2819
2820                 { 0x1f, 0x0000 },
2821                 { 0x0b, 0x0000 },
2822                 { 0x00, 0x9200 }
2823         };
2824
2825         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2826 }
2827
2828 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2829 {
2830         static const struct phy_reg phy_reg_init[] = {
2831                 { 0x1f, 0x0002 },
2832                 { 0x01, 0x90d0 },
2833                 { 0x1f, 0x0000 }
2834         };
2835
2836         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2837 }
2838
2839 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2840 {
2841         struct pci_dev *pdev = tp->pci_dev;
2842
2843         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2844             (pdev->subsystem_device != 0xe000))
2845                 return;
2846
2847         rtl_writephy(tp, 0x1f, 0x0001);
2848         rtl_writephy(tp, 0x10, 0xf01b);
2849         rtl_writephy(tp, 0x1f, 0x0000);
2850 }
2851
2852 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2853 {
2854         static const struct phy_reg phy_reg_init[] = {
2855                 { 0x1f, 0x0001 },
2856                 { 0x04, 0x0000 },
2857                 { 0x03, 0x00a1 },
2858                 { 0x02, 0x0008 },
2859                 { 0x01, 0x0120 },
2860                 { 0x00, 0x1000 },
2861                 { 0x04, 0x0800 },
2862                 { 0x04, 0x9000 },
2863                 { 0x03, 0x802f },
2864                 { 0x02, 0x4f02 },
2865                 { 0x01, 0x0409 },
2866                 { 0x00, 0xf099 },
2867                 { 0x04, 0x9800 },
2868                 { 0x04, 0xa000 },
2869                 { 0x03, 0xdf01 },
2870                 { 0x02, 0xdf20 },
2871                 { 0x01, 0xff95 },
2872                 { 0x00, 0xba00 },
2873                 { 0x04, 0xa800 },
2874                 { 0x04, 0xf000 },
2875                 { 0x03, 0xdf01 },
2876                 { 0x02, 0xdf20 },
2877                 { 0x01, 0x101a },
2878                 { 0x00, 0xa0ff },
2879                 { 0x04, 0xf800 },
2880                 { 0x04, 0x0000 },
2881                 { 0x1f, 0x0000 },
2882
2883                 { 0x1f, 0x0001 },
2884                 { 0x10, 0xf41b },
2885                 { 0x14, 0xfb54 },
2886                 { 0x18, 0xf5c7 },
2887                 { 0x1f, 0x0000 },
2888
2889                 { 0x1f, 0x0001 },
2890                 { 0x17, 0x0cc0 },
2891                 { 0x1f, 0x0000 }
2892         };
2893
2894         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2895
2896         rtl8169scd_hw_phy_config_quirk(tp);
2897 }
2898
2899 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         static const struct phy_reg phy_reg_init[] = {
2902                 { 0x1f, 0x0001 },
2903                 { 0x04, 0x0000 },
2904                 { 0x03, 0x00a1 },
2905                 { 0x02, 0x0008 },
2906                 { 0x01, 0x0120 },
2907                 { 0x00, 0x1000 },
2908                 { 0x04, 0x0800 },
2909                 { 0x04, 0x9000 },
2910                 { 0x03, 0x802f },
2911                 { 0x02, 0x4f02 },
2912                 { 0x01, 0x0409 },
2913                 { 0x00, 0xf099 },
2914                 { 0x04, 0x9800 },
2915                 { 0x04, 0xa000 },
2916                 { 0x03, 0xdf01 },
2917                 { 0x02, 0xdf20 },
2918                 { 0x01, 0xff95 },
2919                 { 0x00, 0xba00 },
2920                 { 0x04, 0xa800 },
2921                 { 0x04, 0xf000 },
2922                 { 0x03, 0xdf01 },
2923                 { 0x02, 0xdf20 },
2924                 { 0x01, 0x101a },
2925                 { 0x00, 0xa0ff },
2926                 { 0x04, 0xf800 },
2927                 { 0x04, 0x0000 },
2928                 { 0x1f, 0x0000 },
2929
2930                 { 0x1f, 0x0001 },
2931                 { 0x0b, 0x8480 },
2932                 { 0x1f, 0x0000 },
2933
2934                 { 0x1f, 0x0001 },
2935                 { 0x18, 0x67c7 },
2936                 { 0x04, 0x2000 },
2937                 { 0x03, 0x002f },
2938                 { 0x02, 0x4360 },
2939                 { 0x01, 0x0109 },
2940                 { 0x00, 0x3022 },
2941                 { 0x04, 0x2800 },
2942                 { 0x1f, 0x0000 },
2943
2944                 { 0x1f, 0x0001 },
2945                 { 0x17, 0x0cc0 },
2946                 { 0x1f, 0x0000 }
2947         };
2948
2949         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2950 }
2951
2952 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2953 {
2954         static const struct phy_reg phy_reg_init[] = {
2955                 { 0x10, 0xf41b },
2956                 { 0x1f, 0x0000 }
2957         };
2958
2959         rtl_writephy(tp, 0x1f, 0x0001);
2960         rtl_patchphy(tp, 0x16, 1 << 0);
2961
2962         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2963 }
2964
2965 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2966 {
2967         static const struct phy_reg phy_reg_init[] = {
2968                 { 0x1f, 0x0001 },
2969                 { 0x10, 0xf41b },
2970                 { 0x1f, 0x0000 }
2971         };
2972
2973         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2974 }
2975
2976 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2977 {
2978         static const struct phy_reg phy_reg_init[] = {
2979                 { 0x1f, 0x0000 },
2980                 { 0x1d, 0x0f00 },
2981                 { 0x1f, 0x0002 },
2982                 { 0x0c, 0x1ec8 },
2983                 { 0x1f, 0x0000 }
2984         };
2985
2986         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2987 }
2988
2989 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2990 {
2991         static const struct phy_reg phy_reg_init[] = {
2992                 { 0x1f, 0x0001 },
2993                 { 0x1d, 0x3d98 },
2994                 { 0x1f, 0x0000 }
2995         };
2996
2997         rtl_writephy(tp, 0x1f, 0x0000);
2998         rtl_patchphy(tp, 0x14, 1 << 5);
2999         rtl_patchphy(tp, 0x0d, 1 << 5);
3000
3001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002 }
3003
3004 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3005 {
3006         static const struct phy_reg phy_reg_init[] = {
3007                 { 0x1f, 0x0001 },
3008                 { 0x12, 0x2300 },
3009                 { 0x1f, 0x0002 },
3010                 { 0x00, 0x88d4 },
3011                 { 0x01, 0x82b1 },
3012                 { 0x03, 0x7002 },
3013                 { 0x08, 0x9e30 },
3014                 { 0x09, 0x01f0 },
3015                 { 0x0a, 0x5500 },
3016                 { 0x0c, 0x00c8 },
3017                 { 0x1f, 0x0003 },
3018                 { 0x12, 0xc096 },
3019                 { 0x16, 0x000a },
3020                 { 0x1f, 0x0000 },
3021                 { 0x1f, 0x0000 },
3022                 { 0x09, 0x2000 },
3023                 { 0x09, 0x0000 }
3024         };
3025
3026         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3027
3028         rtl_patchphy(tp, 0x14, 1 << 5);
3029         rtl_patchphy(tp, 0x0d, 1 << 5);
3030         rtl_writephy(tp, 0x1f, 0x0000);
3031 }
3032
3033 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3034 {
3035         static const struct phy_reg phy_reg_init[] = {
3036                 { 0x1f, 0x0001 },
3037                 { 0x12, 0x2300 },
3038                 { 0x03, 0x802f },
3039                 { 0x02, 0x4f02 },
3040                 { 0x01, 0x0409 },
3041                 { 0x00, 0xf099 },
3042                 { 0x04, 0x9800 },
3043                 { 0x04, 0x9000 },
3044                 { 0x1d, 0x3d98 },
3045                 { 0x1f, 0x0002 },
3046                 { 0x0c, 0x7eb8 },
3047                 { 0x06, 0x0761 },
3048                 { 0x1f, 0x0003 },
3049                 { 0x16, 0x0f0a },
3050                 { 0x1f, 0x0000 }
3051         };
3052
3053         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3054
3055         rtl_patchphy(tp, 0x16, 1 << 0);
3056         rtl_patchphy(tp, 0x14, 1 << 5);
3057         rtl_patchphy(tp, 0x0d, 1 << 5);
3058         rtl_writephy(tp, 0x1f, 0x0000);
3059 }
3060
3061 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3062 {
3063         static const struct phy_reg phy_reg_init[] = {
3064                 { 0x1f, 0x0001 },
3065                 { 0x12, 0x2300 },
3066                 { 0x1d, 0x3d98 },
3067                 { 0x1f, 0x0002 },
3068                 { 0x0c, 0x7eb8 },
3069                 { 0x06, 0x5461 },
3070                 { 0x1f, 0x0003 },
3071                 { 0x16, 0x0f0a },
3072                 { 0x1f, 0x0000 }
3073         };
3074
3075         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3076
3077         rtl_patchphy(tp, 0x16, 1 << 0);
3078         rtl_patchphy(tp, 0x14, 1 << 5);
3079         rtl_patchphy(tp, 0x0d, 1 << 5);
3080         rtl_writephy(tp, 0x1f, 0x0000);
3081 }
3082
3083 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3084 {
3085         rtl8168c_3_hw_phy_config(tp);
3086 }
3087
3088 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3089 {
3090         static const struct phy_reg phy_reg_init_0[] = {
3091                 /* Channel Estimation */
3092                 { 0x1f, 0x0001 },
3093                 { 0x06, 0x4064 },
3094                 { 0x07, 0x2863 },
3095                 { 0x08, 0x059c },
3096                 { 0x09, 0x26b4 },
3097                 { 0x0a, 0x6a19 },
3098                 { 0x0b, 0xdcc8 },
3099                 { 0x10, 0xf06d },
3100                 { 0x14, 0x7f68 },
3101                 { 0x18, 0x7fd9 },
3102                 { 0x1c, 0xf0ff },
3103                 { 0x1d, 0x3d9c },
3104                 { 0x1f, 0x0003 },
3105                 { 0x12, 0xf49f },
3106                 { 0x13, 0x070b },
3107                 { 0x1a, 0x05ad },
3108                 { 0x14, 0x94c0 },
3109
3110                 /*
3111                  * Tx Error Issue
3112                  * Enhance line driver power
3113                  */
3114                 { 0x1f, 0x0002 },
3115                 { 0x06, 0x5561 },
3116                 { 0x1f, 0x0005 },
3117                 { 0x05, 0x8332 },
3118                 { 0x06, 0x5561 },
3119
3120                 /*
3121                  * Can not link to 1Gbps with bad cable
3122                  * Decrease SNR threshold form 21.07dB to 19.04dB
3123                  */
3124                 { 0x1f, 0x0001 },
3125                 { 0x17, 0x0cc0 },
3126
3127                 { 0x1f, 0x0000 },
3128                 { 0x0d, 0xf880 }
3129         };
3130
3131         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3132
3133         /*
3134          * Rx Error Issue
3135          * Fine Tune Switching regulator parameter
3136          */
3137         rtl_writephy(tp, 0x1f, 0x0002);
3138         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3139         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3140
3141         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3142                 static const struct phy_reg phy_reg_init[] = {
3143                         { 0x1f, 0x0002 },
3144                         { 0x05, 0x669a },
3145                         { 0x1f, 0x0005 },
3146                         { 0x05, 0x8330 },
3147                         { 0x06, 0x669a },
3148                         { 0x1f, 0x0002 }
3149                 };
3150                 int val;
3151
3152                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153
3154                 val = rtl_readphy(tp, 0x0d);
3155
3156                 if ((val & 0x00ff) != 0x006c) {
3157                         static const u32 set[] = {
3158                                 0x0065, 0x0066, 0x0067, 0x0068,
3159                                 0x0069, 0x006a, 0x006b, 0x006c
3160                         };
3161                         int i;
3162
3163                         rtl_writephy(tp, 0x1f, 0x0002);
3164
3165                         val &= 0xff00;
3166                         for (i = 0; i < ARRAY_SIZE(set); i++)
3167                                 rtl_writephy(tp, 0x0d, val | set[i]);
3168                 }
3169         } else {
3170                 static const struct phy_reg phy_reg_init[] = {
3171                         { 0x1f, 0x0002 },
3172                         { 0x05, 0x6662 },
3173                         { 0x1f, 0x0005 },
3174                         { 0x05, 0x8330 },
3175                         { 0x06, 0x6662 }
3176                 };
3177
3178                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3179         }
3180
3181         /* RSET couple improve */
3182         rtl_writephy(tp, 0x1f, 0x0002);
3183         rtl_patchphy(tp, 0x0d, 0x0300);
3184         rtl_patchphy(tp, 0x0f, 0x0010);
3185
3186         /* Fine tune PLL performance */
3187         rtl_writephy(tp, 0x1f, 0x0002);
3188         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3189         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3190
3191         rtl_writephy(tp, 0x1f, 0x0005);
3192         rtl_writephy(tp, 0x05, 0x001b);
3193
3194         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3195
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197 }
3198
3199 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3200 {
3201         static const struct phy_reg phy_reg_init_0[] = {
3202                 /* Channel Estimation */
3203                 { 0x1f, 0x0001 },
3204                 { 0x06, 0x4064 },
3205                 { 0x07, 0x2863 },
3206                 { 0x08, 0x059c },
3207                 { 0x09, 0x26b4 },
3208                 { 0x0a, 0x6a19 },
3209                 { 0x0b, 0xdcc8 },
3210                 { 0x10, 0xf06d },
3211                 { 0x14, 0x7f68 },
3212                 { 0x18, 0x7fd9 },
3213                 { 0x1c, 0xf0ff },
3214                 { 0x1d, 0x3d9c },
3215                 { 0x1f, 0x0003 },
3216                 { 0x12, 0xf49f },
3217                 { 0x13, 0x070b },
3218                 { 0x1a, 0x05ad },
3219                 { 0x14, 0x94c0 },
3220
3221                 /*
3222                  * Tx Error Issue
3223                  * Enhance line driver power
3224                  */
3225                 { 0x1f, 0x0002 },
3226                 { 0x06, 0x5561 },
3227                 { 0x1f, 0x0005 },
3228                 { 0x05, 0x8332 },
3229                 { 0x06, 0x5561 },
3230
3231                 /*
3232                  * Can not link to 1Gbps with bad cable
3233                  * Decrease SNR threshold form 21.07dB to 19.04dB
3234                  */
3235                 { 0x1f, 0x0001 },
3236                 { 0x17, 0x0cc0 },
3237
3238                 { 0x1f, 0x0000 },
3239                 { 0x0d, 0xf880 }
3240         };
3241
3242         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3243
3244         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3245                 static const struct phy_reg phy_reg_init[] = {
3246                         { 0x1f, 0x0002 },
3247                         { 0x05, 0x669a },
3248                         { 0x1f, 0x0005 },
3249                         { 0x05, 0x8330 },
3250                         { 0x06, 0x669a },
3251
3252                         { 0x1f, 0x0002 }
3253                 };
3254                 int val;
3255
3256                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3257
3258                 val = rtl_readphy(tp, 0x0d);
3259                 if ((val & 0x00ff) != 0x006c) {
3260                         static const u32 set[] = {
3261                                 0x0065, 0x0066, 0x0067, 0x0068,
3262                                 0x0069, 0x006a, 0x006b, 0x006c
3263                         };
3264                         int i;
3265
3266                         rtl_writephy(tp, 0x1f, 0x0002);
3267
3268                         val &= 0xff00;
3269                         for (i = 0; i < ARRAY_SIZE(set); i++)
3270                                 rtl_writephy(tp, 0x0d, val | set[i]);
3271                 }
3272         } else {
3273                 static const struct phy_reg phy_reg_init[] = {
3274                         { 0x1f, 0x0002 },
3275                         { 0x05, 0x2642 },
3276                         { 0x1f, 0x0005 },
3277                         { 0x05, 0x8330 },
3278                         { 0x06, 0x2642 }
3279                 };
3280
3281                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3282         }
3283
3284         /* Fine tune PLL performance */
3285         rtl_writephy(tp, 0x1f, 0x0002);
3286         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3287         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3288
3289         /* Switching regulator Slew rate */
3290         rtl_writephy(tp, 0x1f, 0x0002);
3291         rtl_patchphy(tp, 0x0f, 0x0017);
3292
3293         rtl_writephy(tp, 0x1f, 0x0005);
3294         rtl_writephy(tp, 0x05, 0x001b);
3295
3296         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3297
3298         rtl_writephy(tp, 0x1f, 0x0000);
3299 }
3300
3301 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3302 {
3303         static const struct phy_reg phy_reg_init[] = {
3304                 { 0x1f, 0x0002 },
3305                 { 0x10, 0x0008 },
3306                 { 0x0d, 0x006c },
3307
3308                 { 0x1f, 0x0000 },
3309                 { 0x0d, 0xf880 },
3310
3311                 { 0x1f, 0x0001 },
3312                 { 0x17, 0x0cc0 },
3313
3314                 { 0x1f, 0x0001 },
3315                 { 0x0b, 0xa4d8 },
3316                 { 0x09, 0x281c },
3317                 { 0x07, 0x2883 },
3318                 { 0x0a, 0x6b35 },
3319                 { 0x1d, 0x3da4 },
3320                 { 0x1c, 0xeffd },
3321                 { 0x14, 0x7f52 },
3322                 { 0x18, 0x7fc6 },
3323                 { 0x08, 0x0601 },
3324                 { 0x06, 0x4063 },
3325                 { 0x10, 0xf074 },
3326                 { 0x1f, 0x0003 },
3327                 { 0x13, 0x0789 },
3328                 { 0x12, 0xf4bd },
3329                 { 0x1a, 0x04fd },
3330                 { 0x14, 0x84b0 },
3331                 { 0x1f, 0x0000 },
3332                 { 0x00, 0x9200 },
3333
3334                 { 0x1f, 0x0005 },
3335                 { 0x01, 0x0340 },
3336                 { 0x1f, 0x0001 },
3337                 { 0x04, 0x4000 },
3338                 { 0x03, 0x1d21 },
3339                 { 0x02, 0x0c32 },
3340                 { 0x01, 0x0200 },
3341                 { 0x00, 0x5554 },
3342                 { 0x04, 0x4800 },
3343                 { 0x04, 0x4000 },
3344                 { 0x04, 0xf000 },
3345                 { 0x03, 0xdf01 },
3346                 { 0x02, 0xdf20 },
3347                 { 0x01, 0x101a },
3348                 { 0x00, 0xa0ff },
3349                 { 0x04, 0xf800 },
3350                 { 0x04, 0xf000 },
3351                 { 0x1f, 0x0000 },
3352
3353                 { 0x1f, 0x0007 },
3354                 { 0x1e, 0x0023 },
3355                 { 0x16, 0x0000 },
3356                 { 0x1f, 0x0000 }
3357         };
3358
3359         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3360 }
3361
3362 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3363 {
3364         static const struct phy_reg phy_reg_init[] = {
3365                 { 0x1f, 0x0001 },
3366                 { 0x17, 0x0cc0 },
3367
3368                 { 0x1f, 0x0007 },
3369                 { 0x1e, 0x002d },
3370                 { 0x18, 0x0040 },
3371                 { 0x1f, 0x0000 }
3372         };
3373
3374         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3375         rtl_patchphy(tp, 0x0d, 1 << 5);
3376 }
3377
3378 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3379 {
3380         static const struct phy_reg phy_reg_init[] = {
3381                 /* Enable Delay cap */
3382                 { 0x1f, 0x0005 },
3383                 { 0x05, 0x8b80 },
3384                 { 0x06, 0xc896 },
3385                 { 0x1f, 0x0000 },
3386
3387                 /* Channel estimation fine tune */
3388                 { 0x1f, 0x0001 },
3389                 { 0x0b, 0x6c20 },
3390                 { 0x07, 0x2872 },
3391                 { 0x1c, 0xefff },
3392                 { 0x1f, 0x0003 },
3393                 { 0x14, 0x6420 },
3394                 { 0x1f, 0x0000 },
3395
3396                 /* Update PFM & 10M TX idle timer */
3397                 { 0x1f, 0x0007 },
3398                 { 0x1e, 0x002f },
3399                 { 0x15, 0x1919 },
3400                 { 0x1f, 0x0000 },
3401
3402                 { 0x1f, 0x0007 },
3403                 { 0x1e, 0x00ac },
3404                 { 0x18, 0x0006 },
3405                 { 0x1f, 0x0000 }
3406         };
3407
3408         rtl_apply_firmware(tp);
3409
3410         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3411
3412         /* DCO enable for 10M IDLE Power */
3413         rtl_writephy(tp, 0x1f, 0x0007);
3414         rtl_writephy(tp, 0x1e, 0x0023);
3415         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3416         rtl_writephy(tp, 0x1f, 0x0000);
3417
3418         /* For impedance matching */
3419         rtl_writephy(tp, 0x1f, 0x0002);
3420         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3421         rtl_writephy(tp, 0x1f, 0x0000);
3422
3423         /* PHY auto speed down */
3424         rtl_writephy(tp, 0x1f, 0x0007);
3425         rtl_writephy(tp, 0x1e, 0x002d);
3426         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3427         rtl_writephy(tp, 0x1f, 0x0000);
3428         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3429
3430         rtl_writephy(tp, 0x1f, 0x0005);
3431         rtl_writephy(tp, 0x05, 0x8b86);
3432         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3433         rtl_writephy(tp, 0x1f, 0x0000);
3434
3435         rtl_writephy(tp, 0x1f, 0x0005);
3436         rtl_writephy(tp, 0x05, 0x8b85);
3437         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3438         rtl_writephy(tp, 0x1f, 0x0007);
3439         rtl_writephy(tp, 0x1e, 0x0020);
3440         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3441         rtl_writephy(tp, 0x1f, 0x0006);
3442         rtl_writephy(tp, 0x00, 0x5a00);
3443         rtl_writephy(tp, 0x1f, 0x0000);
3444         rtl_writephy(tp, 0x0d, 0x0007);
3445         rtl_writephy(tp, 0x0e, 0x003c);
3446         rtl_writephy(tp, 0x0d, 0x4007);
3447         rtl_writephy(tp, 0x0e, 0x0000);
3448         rtl_writephy(tp, 0x0d, 0x0000);
3449 }
3450
3451 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3452 {
3453         const u16 w[] = {
3454                 addr[0] | (addr[1] << 8),
3455                 addr[2] | (addr[3] << 8),
3456                 addr[4] | (addr[5] << 8)
3457         };
3458         const struct exgmac_reg e[] = {
3459                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3460                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3461                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3462                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3463         };
3464
3465         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3466 }
3467
3468 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3469 {
3470         static const struct phy_reg phy_reg_init[] = {
3471                 /* Enable Delay cap */
3472                 { 0x1f, 0x0004 },
3473                 { 0x1f, 0x0007 },
3474                 { 0x1e, 0x00ac },
3475                 { 0x18, 0x0006 },
3476                 { 0x1f, 0x0002 },
3477                 { 0x1f, 0x0000 },
3478                 { 0x1f, 0x0000 },
3479
3480                 /* Channel estimation fine tune */
3481                 { 0x1f, 0x0003 },
3482                 { 0x09, 0xa20f },
3483                 { 0x1f, 0x0000 },
3484                 { 0x1f, 0x0000 },
3485
3486                 /* Green Setting */
3487                 { 0x1f, 0x0005 },
3488                 { 0x05, 0x8b5b },
3489                 { 0x06, 0x9222 },
3490                 { 0x05, 0x8b6d },
3491                 { 0x06, 0x8000 },
3492                 { 0x05, 0x8b76 },
3493                 { 0x06, 0x8000 },
3494                 { 0x1f, 0x0000 }
3495         };
3496
3497         rtl_apply_firmware(tp);
3498
3499         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3500
3501         /* For 4-corner performance improve */
3502         rtl_writephy(tp, 0x1f, 0x0005);
3503         rtl_writephy(tp, 0x05, 0x8b80);
3504         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3505         rtl_writephy(tp, 0x1f, 0x0000);
3506
3507         /* PHY auto speed down */
3508         rtl_writephy(tp, 0x1f, 0x0004);
3509         rtl_writephy(tp, 0x1f, 0x0007);
3510         rtl_writephy(tp, 0x1e, 0x002d);
3511         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3512         rtl_writephy(tp, 0x1f, 0x0002);
3513         rtl_writephy(tp, 0x1f, 0x0000);
3514         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3515
3516         /* improve 10M EEE waveform */
3517         rtl_writephy(tp, 0x1f, 0x0005);
3518         rtl_writephy(tp, 0x05, 0x8b86);
3519         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3520         rtl_writephy(tp, 0x1f, 0x0000);
3521
3522         /* Improve 2-pair detection performance */
3523         rtl_writephy(tp, 0x1f, 0x0005);
3524         rtl_writephy(tp, 0x05, 0x8b85);
3525         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3526         rtl_writephy(tp, 0x1f, 0x0000);
3527
3528         /* EEE setting */
3529         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3530         rtl_writephy(tp, 0x1f, 0x0005);
3531         rtl_writephy(tp, 0x05, 0x8b85);
3532         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3533         rtl_writephy(tp, 0x1f, 0x0004);
3534         rtl_writephy(tp, 0x1f, 0x0007);
3535         rtl_writephy(tp, 0x1e, 0x0020);
3536         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3537         rtl_writephy(tp, 0x1f, 0x0002);
3538         rtl_writephy(tp, 0x1f, 0x0000);
3539         rtl_writephy(tp, 0x0d, 0x0007);
3540         rtl_writephy(tp, 0x0e, 0x003c);
3541         rtl_writephy(tp, 0x0d, 0x4007);
3542         rtl_writephy(tp, 0x0e, 0x0000);
3543         rtl_writephy(tp, 0x0d, 0x0000);
3544
3545         /* Green feature */
3546         rtl_writephy(tp, 0x1f, 0x0003);
3547         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3548         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3549         rtl_writephy(tp, 0x1f, 0x0000);
3550
3551         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3552         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3553 }
3554
3555 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3556 {
3557         /* For 4-corner performance improve */
3558         rtl_writephy(tp, 0x1f, 0x0005);
3559         rtl_writephy(tp, 0x05, 0x8b80);
3560         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3561         rtl_writephy(tp, 0x1f, 0x0000);
3562
3563         /* PHY auto speed down */
3564         rtl_writephy(tp, 0x1f, 0x0007);
3565         rtl_writephy(tp, 0x1e, 0x002d);
3566         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3567         rtl_writephy(tp, 0x1f, 0x0000);
3568         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3569
3570         /* Improve 10M EEE waveform */
3571         rtl_writephy(tp, 0x1f, 0x0005);
3572         rtl_writephy(tp, 0x05, 0x8b86);
3573         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3574         rtl_writephy(tp, 0x1f, 0x0000);
3575 }
3576
3577 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3578 {
3579         static const struct phy_reg phy_reg_init[] = {
3580                 /* Channel estimation fine tune */
3581                 { 0x1f, 0x0003 },
3582                 { 0x09, 0xa20f },
3583                 { 0x1f, 0x0000 },
3584
3585                 /* Modify green table for giga & fnet */
3586                 { 0x1f, 0x0005 },
3587                 { 0x05, 0x8b55 },
3588                 { 0x06, 0x0000 },
3589                 { 0x05, 0x8b5e },
3590                 { 0x06, 0x0000 },
3591                 { 0x05, 0x8b67 },
3592                 { 0x06, 0x0000 },
3593                 { 0x05, 0x8b70 },
3594                 { 0x06, 0x0000 },
3595                 { 0x1f, 0x0000 },
3596                 { 0x1f, 0x0007 },
3597                 { 0x1e, 0x0078 },
3598                 { 0x17, 0x0000 },
3599                 { 0x19, 0x00fb },
3600                 { 0x1f, 0x0000 },
3601
3602                 /* Modify green table for 10M */
3603                 { 0x1f, 0x0005 },
3604                 { 0x05, 0x8b79 },
3605                 { 0x06, 0xaa00 },
3606                 { 0x1f, 0x0000 },
3607
3608                 /* Disable hiimpedance detection (RTCT) */
3609                 { 0x1f, 0x0003 },
3610                 { 0x01, 0x328a },
3611                 { 0x1f, 0x0000 }
3612         };
3613
3614         rtl_apply_firmware(tp);
3615
3616         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3617
3618         rtl8168f_hw_phy_config(tp);
3619
3620         /* Improve 2-pair detection performance */
3621         rtl_writephy(tp, 0x1f, 0x0005);
3622         rtl_writephy(tp, 0x05, 0x8b85);
3623         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3624         rtl_writephy(tp, 0x1f, 0x0000);
3625 }
3626
3627 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3628 {
3629         rtl_apply_firmware(tp);
3630
3631         rtl8168f_hw_phy_config(tp);
3632 }
3633
3634 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3635 {
3636         static const struct phy_reg phy_reg_init[] = {
3637                 /* Channel estimation fine tune */
3638                 { 0x1f, 0x0003 },
3639                 { 0x09, 0xa20f },
3640                 { 0x1f, 0x0000 },
3641
3642                 /* Modify green table for giga & fnet */
3643                 { 0x1f, 0x0005 },
3644                 { 0x05, 0x8b55 },
3645                 { 0x06, 0x0000 },
3646                 { 0x05, 0x8b5e },
3647                 { 0x06, 0x0000 },
3648                 { 0x05, 0x8b67 },
3649                 { 0x06, 0x0000 },
3650                 { 0x05, 0x8b70 },
3651                 { 0x06, 0x0000 },
3652                 { 0x1f, 0x0000 },
3653                 { 0x1f, 0x0007 },
3654                 { 0x1e, 0x0078 },
3655                 { 0x17, 0x0000 },
3656                 { 0x19, 0x00aa },
3657                 { 0x1f, 0x0000 },
3658
3659                 /* Modify green table for 10M */
3660                 { 0x1f, 0x0005 },
3661                 { 0x05, 0x8b79 },
3662                 { 0x06, 0xaa00 },
3663                 { 0x1f, 0x0000 },
3664
3665                 /* Disable hiimpedance detection (RTCT) */
3666                 { 0x1f, 0x0003 },
3667                 { 0x01, 0x328a },
3668                 { 0x1f, 0x0000 }
3669         };
3670
3671
3672         rtl_apply_firmware(tp);
3673
3674         rtl8168f_hw_phy_config(tp);
3675
3676         /* Improve 2-pair detection performance */
3677         rtl_writephy(tp, 0x1f, 0x0005);
3678         rtl_writephy(tp, 0x05, 0x8b85);
3679         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3680         rtl_writephy(tp, 0x1f, 0x0000);
3681
3682         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3683
3684         /* Modify green table for giga */
3685         rtl_writephy(tp, 0x1f, 0x0005);
3686         rtl_writephy(tp, 0x05, 0x8b54);
3687         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3688         rtl_writephy(tp, 0x05, 0x8b5d);
3689         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3690         rtl_writephy(tp, 0x05, 0x8a7c);
3691         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3692         rtl_writephy(tp, 0x05, 0x8a7f);
3693         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3694         rtl_writephy(tp, 0x05, 0x8a82);
3695         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3696         rtl_writephy(tp, 0x05, 0x8a85);
3697         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3698         rtl_writephy(tp, 0x05, 0x8a88);
3699         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3700         rtl_writephy(tp, 0x1f, 0x0000);
3701
3702         /* uc same-seed solution */
3703         rtl_writephy(tp, 0x1f, 0x0005);
3704         rtl_writephy(tp, 0x05, 0x8b85);
3705         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3706         rtl_writephy(tp, 0x1f, 0x0000);
3707
3708         /* eee setting */
3709         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3710         rtl_writephy(tp, 0x1f, 0x0005);
3711         rtl_writephy(tp, 0x05, 0x8b85);
3712         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3713         rtl_writephy(tp, 0x1f, 0x0004);
3714         rtl_writephy(tp, 0x1f, 0x0007);
3715         rtl_writephy(tp, 0x1e, 0x0020);
3716         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3717         rtl_writephy(tp, 0x1f, 0x0000);
3718         rtl_writephy(tp, 0x0d, 0x0007);
3719         rtl_writephy(tp, 0x0e, 0x003c);
3720         rtl_writephy(tp, 0x0d, 0x4007);
3721         rtl_writephy(tp, 0x0e, 0x0000);
3722         rtl_writephy(tp, 0x0d, 0x0000);
3723
3724         /* Green feature */
3725         rtl_writephy(tp, 0x1f, 0x0003);
3726         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3727         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3728         rtl_writephy(tp, 0x1f, 0x0000);
3729 }
3730
3731 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3732 {
3733         rtl_apply_firmware(tp);
3734
3735         rtl_writephy(tp, 0x1f, 0x0a46);
3736         if (rtl_readphy(tp, 0x10) & 0x0100) {
3737                 rtl_writephy(tp, 0x1f, 0x0bcc);
3738                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3739         } else {
3740                 rtl_writephy(tp, 0x1f, 0x0bcc);
3741                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3742         }
3743
3744         rtl_writephy(tp, 0x1f, 0x0a46);
3745         if (rtl_readphy(tp, 0x13) & 0x0100) {
3746                 rtl_writephy(tp, 0x1f, 0x0c41);
3747                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3748         } else {
3749                 rtl_writephy(tp, 0x1f, 0x0c41);
3750                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3751         }
3752
3753         /* Enable PHY auto speed down */
3754         rtl_writephy(tp, 0x1f, 0x0a44);
3755         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3756
3757         rtl_writephy(tp, 0x1f, 0x0bcc);
3758         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3759         rtl_writephy(tp, 0x1f, 0x0a44);
3760         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3761         rtl_writephy(tp, 0x1f, 0x0a43);
3762         rtl_writephy(tp, 0x13, 0x8084);
3763         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3764         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3765
3766         /* EEE auto-fallback function */
3767         rtl_writephy(tp, 0x1f, 0x0a4b);
3768         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3769
3770         /* Enable UC LPF tune function */
3771         rtl_writephy(tp, 0x1f, 0x0a43);
3772         rtl_writephy(tp, 0x13, 0x8012);
3773         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3774
3775         rtl_writephy(tp, 0x1f, 0x0c42);
3776         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3777
3778         /* Improve SWR Efficiency */
3779         rtl_writephy(tp, 0x1f, 0x0bcd);
3780         rtl_writephy(tp, 0x14, 0x5065);
3781         rtl_writephy(tp, 0x14, 0xd065);
3782         rtl_writephy(tp, 0x1f, 0x0bc8);
3783         rtl_writephy(tp, 0x11, 0x5655);
3784         rtl_writephy(tp, 0x1f, 0x0bcd);
3785         rtl_writephy(tp, 0x14, 0x1065);
3786         rtl_writephy(tp, 0x14, 0x9065);
3787         rtl_writephy(tp, 0x14, 0x1065);
3788
3789         /* Check ALDPS bit, disable it if enabled */
3790         rtl_writephy(tp, 0x1f, 0x0a43);
3791         if (rtl_readphy(tp, 0x10) & 0x0004)
3792                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3793
3794         rtl_writephy(tp, 0x1f, 0x0000);
3795 }
3796
3797 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3798 {
3799         rtl_apply_firmware(tp);
3800 }
3801
3802 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3803 {
3804         u16 dout_tapbin;
3805         u32 data;
3806
3807         rtl_apply_firmware(tp);
3808
3809         /* CHN EST parameters adjust - giga master */
3810         rtl_writephy(tp, 0x1f, 0x0a43);
3811         rtl_writephy(tp, 0x13, 0x809b);
3812         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3813         rtl_writephy(tp, 0x13, 0x80a2);
3814         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3815         rtl_writephy(tp, 0x13, 0x80a4);
3816         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3817         rtl_writephy(tp, 0x13, 0x809c);
3818         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3819         rtl_writephy(tp, 0x1f, 0x0000);
3820
3821         /* CHN EST parameters adjust - giga slave */
3822         rtl_writephy(tp, 0x1f, 0x0a43);
3823         rtl_writephy(tp, 0x13, 0x80ad);
3824         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3825         rtl_writephy(tp, 0x13, 0x80b4);
3826         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3827         rtl_writephy(tp, 0x13, 0x80ac);
3828         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3829         rtl_writephy(tp, 0x1f, 0x0000);
3830
3831         /* CHN EST parameters adjust - fnet */
3832         rtl_writephy(tp, 0x1f, 0x0a43);
3833         rtl_writephy(tp, 0x13, 0x808e);
3834         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3835         rtl_writephy(tp, 0x13, 0x8090);
3836         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3837         rtl_writephy(tp, 0x13, 0x8092);
3838         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3839         rtl_writephy(tp, 0x1f, 0x0000);
3840
3841         /* enable R-tune & PGA-retune function */
3842         dout_tapbin = 0;
3843         rtl_writephy(tp, 0x1f, 0x0a46);
3844         data = rtl_readphy(tp, 0x13);
3845         data &= 3;
3846         data <<= 2;
3847         dout_tapbin |= data;
3848         data = rtl_readphy(tp, 0x12);
3849         data &= 0xc000;
3850         data >>= 14;
3851         dout_tapbin |= data;
3852         dout_tapbin = ~(dout_tapbin^0x08);
3853         dout_tapbin <<= 12;
3854         dout_tapbin &= 0xf000;
3855         rtl_writephy(tp, 0x1f, 0x0a43);
3856         rtl_writephy(tp, 0x13, 0x827a);
3857         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3858         rtl_writephy(tp, 0x13, 0x827b);
3859         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3860         rtl_writephy(tp, 0x13, 0x827c);
3861         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3862         rtl_writephy(tp, 0x13, 0x827d);
3863         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3864
3865         rtl_writephy(tp, 0x1f, 0x0a43);
3866         rtl_writephy(tp, 0x13, 0x0811);
3867         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3868         rtl_writephy(tp, 0x1f, 0x0a42);
3869         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3870         rtl_writephy(tp, 0x1f, 0x0000);
3871
3872         /* enable GPHY 10M */
3873         rtl_writephy(tp, 0x1f, 0x0a44);
3874         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876
3877         /* SAR ADC performance */
3878         rtl_writephy(tp, 0x1f, 0x0bca);
3879         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3880         rtl_writephy(tp, 0x1f, 0x0000);
3881
3882         rtl_writephy(tp, 0x1f, 0x0a43);
3883         rtl_writephy(tp, 0x13, 0x803f);
3884         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3885         rtl_writephy(tp, 0x13, 0x8047);
3886         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3887         rtl_writephy(tp, 0x13, 0x804f);
3888         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3889         rtl_writephy(tp, 0x13, 0x8057);
3890         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3891         rtl_writephy(tp, 0x13, 0x805f);
3892         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3893         rtl_writephy(tp, 0x13, 0x8067);
3894         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3895         rtl_writephy(tp, 0x13, 0x806f);
3896         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3897         rtl_writephy(tp, 0x1f, 0x0000);
3898
3899         /* disable phy pfm mode */
3900         rtl_writephy(tp, 0x1f, 0x0a44);
3901         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3902         rtl_writephy(tp, 0x1f, 0x0000);
3903
3904         /* Check ALDPS bit, disable it if enabled */
3905         rtl_writephy(tp, 0x1f, 0x0a43);
3906         if (rtl_readphy(tp, 0x10) & 0x0004)
3907                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3908
3909         rtl_writephy(tp, 0x1f, 0x0000);
3910 }
3911
3912 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3913 {
3914         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3915         u16 rlen;
3916         u32 data;
3917
3918         rtl_apply_firmware(tp);
3919
3920         /* CHIN EST parameter update */
3921         rtl_writephy(tp, 0x1f, 0x0a43);
3922         rtl_writephy(tp, 0x13, 0x808a);
3923         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3924         rtl_writephy(tp, 0x1f, 0x0000);
3925
3926         /* enable R-tune & PGA-retune function */
3927         rtl_writephy(tp, 0x1f, 0x0a43);
3928         rtl_writephy(tp, 0x13, 0x0811);
3929         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3930         rtl_writephy(tp, 0x1f, 0x0a42);
3931         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3932         rtl_writephy(tp, 0x1f, 0x0000);
3933
3934         /* enable GPHY 10M */
3935         rtl_writephy(tp, 0x1f, 0x0a44);
3936         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3937         rtl_writephy(tp, 0x1f, 0x0000);
3938
3939         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3940         data = r8168_mac_ocp_read(tp, 0xdd02);
3941         ioffset_p3 = ((data & 0x80)>>7);
3942         ioffset_p3 <<= 3;
3943
3944         data = r8168_mac_ocp_read(tp, 0xdd00);
3945         ioffset_p3 |= ((data & (0xe000))>>13);
3946         ioffset_p2 = ((data & (0x1e00))>>9);
3947         ioffset_p1 = ((data & (0x01e0))>>5);
3948         ioffset_p0 = ((data & 0x0010)>>4);
3949         ioffset_p0 <<= 3;
3950         ioffset_p0 |= (data & (0x07));
3951         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3952
3953         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3954             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3955                 rtl_writephy(tp, 0x1f, 0x0bcf);
3956                 rtl_writephy(tp, 0x16, data);
3957                 rtl_writephy(tp, 0x1f, 0x0000);
3958         }
3959
3960         /* Modify rlen (TX LPF corner frequency) level */
3961         rtl_writephy(tp, 0x1f, 0x0bcd);
3962         data = rtl_readphy(tp, 0x16);
3963         data &= 0x000f;
3964         rlen = 0;
3965         if (data > 3)
3966                 rlen = data - 3;
3967         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3968         rtl_writephy(tp, 0x17, data);
3969         rtl_writephy(tp, 0x1f, 0x0bcd);
3970         rtl_writephy(tp, 0x1f, 0x0000);
3971
3972         /* disable phy pfm mode */
3973         rtl_writephy(tp, 0x1f, 0x0a44);
3974         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3975         rtl_writephy(tp, 0x1f, 0x0000);
3976
3977         /* Check ALDPS bit, disable it if enabled */
3978         rtl_writephy(tp, 0x1f, 0x0a43);
3979         if (rtl_readphy(tp, 0x10) & 0x0004)
3980                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3981
3982         rtl_writephy(tp, 0x1f, 0x0000);
3983 }
3984
3985 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3986 {
3987         /* Enable PHY auto speed down */
3988         rtl_writephy(tp, 0x1f, 0x0a44);
3989         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3990         rtl_writephy(tp, 0x1f, 0x0000);
3991
3992         /* patch 10M & ALDPS */
3993         rtl_writephy(tp, 0x1f, 0x0bcc);
3994         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3995         rtl_writephy(tp, 0x1f, 0x0a44);
3996         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3997         rtl_writephy(tp, 0x1f, 0x0a43);
3998         rtl_writephy(tp, 0x13, 0x8084);
3999         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4000         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4001         rtl_writephy(tp, 0x1f, 0x0000);
4002
4003         /* Enable EEE auto-fallback function */
4004         rtl_writephy(tp, 0x1f, 0x0a4b);
4005         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4006         rtl_writephy(tp, 0x1f, 0x0000);
4007
4008         /* Enable UC LPF tune function */
4009         rtl_writephy(tp, 0x1f, 0x0a43);
4010         rtl_writephy(tp, 0x13, 0x8012);
4011         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4012         rtl_writephy(tp, 0x1f, 0x0000);
4013
4014         /* set rg_sel_sdm_rate */
4015         rtl_writephy(tp, 0x1f, 0x0c42);
4016         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4017         rtl_writephy(tp, 0x1f, 0x0000);
4018
4019         /* Check ALDPS bit, disable it if enabled */
4020         rtl_writephy(tp, 0x1f, 0x0a43);
4021         if (rtl_readphy(tp, 0x10) & 0x0004)
4022                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4023
4024         rtl_writephy(tp, 0x1f, 0x0000);
4025 }
4026
4027 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4028 {
4029         /* patch 10M & ALDPS */
4030         rtl_writephy(tp, 0x1f, 0x0bcc);
4031         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4032         rtl_writephy(tp, 0x1f, 0x0a44);
4033         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         rtl_writephy(tp, 0x13, 0x8084);
4036         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4037         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4038         rtl_writephy(tp, 0x1f, 0x0000);
4039
4040         /* Enable UC LPF tune function */
4041         rtl_writephy(tp, 0x1f, 0x0a43);
4042         rtl_writephy(tp, 0x13, 0x8012);
4043         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4044         rtl_writephy(tp, 0x1f, 0x0000);
4045
4046         /* Set rg_sel_sdm_rate */
4047         rtl_writephy(tp, 0x1f, 0x0c42);
4048         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4049         rtl_writephy(tp, 0x1f, 0x0000);
4050
4051         /* Channel estimation parameters */
4052         rtl_writephy(tp, 0x1f, 0x0a43);
4053         rtl_writephy(tp, 0x13, 0x80f3);
4054         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4055         rtl_writephy(tp, 0x13, 0x80f0);
4056         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4057         rtl_writephy(tp, 0x13, 0x80ef);
4058         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4059         rtl_writephy(tp, 0x13, 0x80f6);
4060         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4061         rtl_writephy(tp, 0x13, 0x80ec);
4062         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4063         rtl_writephy(tp, 0x13, 0x80ed);
4064         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4065         rtl_writephy(tp, 0x13, 0x80f2);
4066         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4067         rtl_writephy(tp, 0x13, 0x80f4);
4068         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4069         rtl_writephy(tp, 0x1f, 0x0a43);
4070         rtl_writephy(tp, 0x13, 0x8110);
4071         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4072         rtl_writephy(tp, 0x13, 0x810f);
4073         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4074         rtl_writephy(tp, 0x13, 0x8111);
4075         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4076         rtl_writephy(tp, 0x13, 0x8113);
4077         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4078         rtl_writephy(tp, 0x13, 0x8115);
4079         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4080         rtl_writephy(tp, 0x13, 0x810e);
4081         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4082         rtl_writephy(tp, 0x13, 0x810c);
4083         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4084         rtl_writephy(tp, 0x13, 0x810b);
4085         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4086         rtl_writephy(tp, 0x1f, 0x0a43);
4087         rtl_writephy(tp, 0x13, 0x80d1);
4088         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4089         rtl_writephy(tp, 0x13, 0x80cd);
4090         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4091         rtl_writephy(tp, 0x13, 0x80d3);
4092         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4093         rtl_writephy(tp, 0x13, 0x80d5);
4094         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4095         rtl_writephy(tp, 0x13, 0x80d7);
4096         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4097
4098         /* Force PWM-mode */
4099         rtl_writephy(tp, 0x1f, 0x0bcd);
4100         rtl_writephy(tp, 0x14, 0x5065);
4101         rtl_writephy(tp, 0x14, 0xd065);
4102         rtl_writephy(tp, 0x1f, 0x0bc8);
4103         rtl_writephy(tp, 0x12, 0x00ed);
4104         rtl_writephy(tp, 0x1f, 0x0bcd);
4105         rtl_writephy(tp, 0x14, 0x1065);
4106         rtl_writephy(tp, 0x14, 0x9065);
4107         rtl_writephy(tp, 0x14, 0x1065);
4108         rtl_writephy(tp, 0x1f, 0x0000);
4109
4110         /* Check ALDPS bit, disable it if enabled */
4111         rtl_writephy(tp, 0x1f, 0x0a43);
4112         if (rtl_readphy(tp, 0x10) & 0x0004)
4113                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4114
4115         rtl_writephy(tp, 0x1f, 0x0000);
4116 }
4117
4118 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4119 {
4120         static const struct phy_reg phy_reg_init[] = {
4121                 { 0x1f, 0x0003 },
4122                 { 0x08, 0x441d },
4123                 { 0x01, 0x9100 },
4124                 { 0x1f, 0x0000 }
4125         };
4126
4127         rtl_writephy(tp, 0x1f, 0x0000);
4128         rtl_patchphy(tp, 0x11, 1 << 12);
4129         rtl_patchphy(tp, 0x19, 1 << 13);
4130         rtl_patchphy(tp, 0x10, 1 << 15);
4131
4132         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4133 }
4134
4135 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4136 {
4137         static const struct phy_reg phy_reg_init[] = {
4138                 { 0x1f, 0x0005 },
4139                 { 0x1a, 0x0000 },
4140                 { 0x1f, 0x0000 },
4141
4142                 { 0x1f, 0x0004 },
4143                 { 0x1c, 0x0000 },
4144                 { 0x1f, 0x0000 },
4145
4146                 { 0x1f, 0x0001 },
4147                 { 0x15, 0x7701 },
4148                 { 0x1f, 0x0000 }
4149         };
4150
4151         /* Disable ALDPS before ram code */
4152         rtl_writephy(tp, 0x1f, 0x0000);
4153         rtl_writephy(tp, 0x18, 0x0310);
4154         msleep(100);
4155
4156         rtl_apply_firmware(tp);
4157
4158         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4159 }
4160
4161 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4162 {
4163         /* Disable ALDPS before setting firmware */
4164         rtl_writephy(tp, 0x1f, 0x0000);
4165         rtl_writephy(tp, 0x18, 0x0310);
4166         msleep(20);
4167
4168         rtl_apply_firmware(tp);
4169
4170         /* EEE setting */
4171         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4172         rtl_writephy(tp, 0x1f, 0x0004);
4173         rtl_writephy(tp, 0x10, 0x401f);
4174         rtl_writephy(tp, 0x19, 0x7030);
4175         rtl_writephy(tp, 0x1f, 0x0000);
4176 }
4177
4178 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4179 {
4180         static const struct phy_reg phy_reg_init[] = {
4181                 { 0x1f, 0x0004 },
4182                 { 0x10, 0xc07f },
4183                 { 0x19, 0x7030 },
4184                 { 0x1f, 0x0000 }
4185         };
4186
4187         /* Disable ALDPS before ram code */
4188         rtl_writephy(tp, 0x1f, 0x0000);
4189         rtl_writephy(tp, 0x18, 0x0310);
4190         msleep(100);
4191
4192         rtl_apply_firmware(tp);
4193
4194         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4195         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4196
4197         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4198 }
4199
4200 static void rtl_hw_phy_config(struct net_device *dev)
4201 {
4202         struct rtl8169_private *tp = netdev_priv(dev);
4203
4204         rtl8169_print_mac_version(tp);
4205
4206         switch (tp->mac_version) {
4207         case RTL_GIGA_MAC_VER_01:
4208                 break;
4209         case RTL_GIGA_MAC_VER_02:
4210         case RTL_GIGA_MAC_VER_03:
4211                 rtl8169s_hw_phy_config(tp);
4212                 break;
4213         case RTL_GIGA_MAC_VER_04:
4214                 rtl8169sb_hw_phy_config(tp);
4215                 break;
4216         case RTL_GIGA_MAC_VER_05:
4217                 rtl8169scd_hw_phy_config(tp);
4218                 break;
4219         case RTL_GIGA_MAC_VER_06:
4220                 rtl8169sce_hw_phy_config(tp);
4221                 break;
4222         case RTL_GIGA_MAC_VER_07:
4223         case RTL_GIGA_MAC_VER_08:
4224         case RTL_GIGA_MAC_VER_09:
4225                 rtl8102e_hw_phy_config(tp);
4226                 break;
4227         case RTL_GIGA_MAC_VER_11:
4228                 rtl8168bb_hw_phy_config(tp);
4229                 break;
4230         case RTL_GIGA_MAC_VER_12:
4231                 rtl8168bef_hw_phy_config(tp);
4232                 break;
4233         case RTL_GIGA_MAC_VER_17:
4234                 rtl8168bef_hw_phy_config(tp);
4235                 break;
4236         case RTL_GIGA_MAC_VER_18:
4237                 rtl8168cp_1_hw_phy_config(tp);
4238                 break;
4239         case RTL_GIGA_MAC_VER_19:
4240                 rtl8168c_1_hw_phy_config(tp);
4241                 break;
4242         case RTL_GIGA_MAC_VER_20:
4243                 rtl8168c_2_hw_phy_config(tp);
4244                 break;
4245         case RTL_GIGA_MAC_VER_21:
4246                 rtl8168c_3_hw_phy_config(tp);
4247                 break;
4248         case RTL_GIGA_MAC_VER_22:
4249                 rtl8168c_4_hw_phy_config(tp);
4250                 break;
4251         case RTL_GIGA_MAC_VER_23:
4252         case RTL_GIGA_MAC_VER_24:
4253                 rtl8168cp_2_hw_phy_config(tp);
4254                 break;
4255         case RTL_GIGA_MAC_VER_25:
4256                 rtl8168d_1_hw_phy_config(tp);
4257                 break;
4258         case RTL_GIGA_MAC_VER_26:
4259                 rtl8168d_2_hw_phy_config(tp);
4260                 break;
4261         case RTL_GIGA_MAC_VER_27:
4262                 rtl8168d_3_hw_phy_config(tp);
4263                 break;
4264         case RTL_GIGA_MAC_VER_28:
4265                 rtl8168d_4_hw_phy_config(tp);
4266                 break;
4267         case RTL_GIGA_MAC_VER_29:
4268         case RTL_GIGA_MAC_VER_30:
4269                 rtl8105e_hw_phy_config(tp);
4270                 break;
4271         case RTL_GIGA_MAC_VER_31:
4272                 /* None. */
4273                 break;
4274         case RTL_GIGA_MAC_VER_32:
4275         case RTL_GIGA_MAC_VER_33:
4276                 rtl8168e_1_hw_phy_config(tp);
4277                 break;
4278         case RTL_GIGA_MAC_VER_34:
4279                 rtl8168e_2_hw_phy_config(tp);
4280                 break;
4281         case RTL_GIGA_MAC_VER_35:
4282                 rtl8168f_1_hw_phy_config(tp);
4283                 break;
4284         case RTL_GIGA_MAC_VER_36:
4285                 rtl8168f_2_hw_phy_config(tp);
4286                 break;
4287
4288         case RTL_GIGA_MAC_VER_37:
4289                 rtl8402_hw_phy_config(tp);
4290                 break;
4291
4292         case RTL_GIGA_MAC_VER_38:
4293                 rtl8411_hw_phy_config(tp);
4294                 break;
4295
4296         case RTL_GIGA_MAC_VER_39:
4297                 rtl8106e_hw_phy_config(tp);
4298                 break;
4299
4300         case RTL_GIGA_MAC_VER_40:
4301                 rtl8168g_1_hw_phy_config(tp);
4302                 break;
4303         case RTL_GIGA_MAC_VER_42:
4304         case RTL_GIGA_MAC_VER_43:
4305         case RTL_GIGA_MAC_VER_44:
4306                 rtl8168g_2_hw_phy_config(tp);
4307                 break;
4308         case RTL_GIGA_MAC_VER_45:
4309         case RTL_GIGA_MAC_VER_47:
4310                 rtl8168h_1_hw_phy_config(tp);
4311                 break;
4312         case RTL_GIGA_MAC_VER_46:
4313         case RTL_GIGA_MAC_VER_48:
4314                 rtl8168h_2_hw_phy_config(tp);
4315                 break;
4316
4317         case RTL_GIGA_MAC_VER_49:
4318                 rtl8168ep_1_hw_phy_config(tp);
4319                 break;
4320         case RTL_GIGA_MAC_VER_50:
4321         case RTL_GIGA_MAC_VER_51:
4322                 rtl8168ep_2_hw_phy_config(tp);
4323                 break;
4324
4325         case RTL_GIGA_MAC_VER_41:
4326         default:
4327                 break;
4328         }
4329 }
4330
4331 static void rtl_phy_work(struct rtl8169_private *tp)
4332 {
4333         struct timer_list *timer = &tp->timer;
4334         void __iomem *ioaddr = tp->mmio_addr;
4335         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4336
4337         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4338
4339         if (tp->phy_reset_pending(tp)) {
4340                 /*
4341                  * A busy loop could burn quite a few cycles on nowadays CPU.
4342                  * Let's delay the execution of the timer for a few ticks.
4343                  */
4344                 timeout = HZ/10;
4345                 goto out_mod_timer;
4346         }
4347
4348         if (tp->link_ok(ioaddr))
4349                 return;
4350
4351         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4352
4353         tp->phy_reset_enable(tp);
4354
4355 out_mod_timer:
4356         mod_timer(timer, jiffies + timeout);
4357 }
4358
4359 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4360 {
4361         if (!test_and_set_bit(flag, tp->wk.flags))
4362                 schedule_work(&tp->wk.work);
4363 }
4364
4365 static void rtl8169_phy_timer(unsigned long __opaque)
4366 {
4367         struct net_device *dev = (struct net_device *)__opaque;
4368         struct rtl8169_private *tp = netdev_priv(dev);
4369
4370         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4371 }
4372
4373 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4374                                   void __iomem *ioaddr)
4375 {
4376         iounmap(ioaddr);
4377         pci_release_regions(pdev);
4378         pci_clear_mwi(pdev);
4379         pci_disable_device(pdev);
4380         free_netdev(dev);
4381 }
4382
4383 DECLARE_RTL_COND(rtl_phy_reset_cond)
4384 {
4385         return tp->phy_reset_pending(tp);
4386 }
4387
4388 static void rtl8169_phy_reset(struct net_device *dev,
4389                               struct rtl8169_private *tp)
4390 {
4391         tp->phy_reset_enable(tp);
4392         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4393 }
4394
4395 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4396 {
4397         void __iomem *ioaddr = tp->mmio_addr;
4398
4399         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4400             (RTL_R8(PHYstatus) & TBI_Enable);
4401 }
4402
4403 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4404 {
4405         void __iomem *ioaddr = tp->mmio_addr;
4406
4407         rtl_hw_phy_config(dev);
4408
4409         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4410                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4411                 RTL_W8(0x82, 0x01);
4412         }
4413
4414         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4415
4416         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4417                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4418
4419         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4420                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4421                 RTL_W8(0x82, 0x01);
4422                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4423                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4424         }
4425
4426         rtl8169_phy_reset(dev, tp);
4427
4428         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4429                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4430                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4431                           (tp->mii.supports_gmii ?
4432                            ADVERTISED_1000baseT_Half |
4433                            ADVERTISED_1000baseT_Full : 0));
4434
4435         if (rtl_tbi_enabled(tp))
4436                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4437 }
4438
4439 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4440 {
4441         void __iomem *ioaddr = tp->mmio_addr;
4442
4443         rtl_lock_work(tp);
4444
4445         RTL_W8(Cfg9346, Cfg9346_Unlock);
4446
4447         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4448         RTL_R32(MAC4);
4449
4450         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4451         RTL_R32(MAC0);
4452
4453         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4454                 rtl_rar_exgmac_set(tp, addr);
4455
4456         RTL_W8(Cfg9346, Cfg9346_Lock);
4457
4458         rtl_unlock_work(tp);
4459 }
4460
4461 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4462 {
4463         void __iomem *ioaddr = tp->mmio_addr;
4464
4465         switch (tp->mac_version) {
4466         case RTL_GIGA_MAC_VER_01:
4467         case RTL_GIGA_MAC_VER_02:
4468         case RTL_GIGA_MAC_VER_03:
4469         case RTL_GIGA_MAC_VER_04:
4470         case RTL_GIGA_MAC_VER_05:
4471         case RTL_GIGA_MAC_VER_06:
4472         case RTL_GIGA_MAC_VER_10:
4473         case RTL_GIGA_MAC_VER_11:
4474         case RTL_GIGA_MAC_VER_12:
4475         case RTL_GIGA_MAC_VER_13:
4476         case RTL_GIGA_MAC_VER_14:
4477         case RTL_GIGA_MAC_VER_15:
4478         case RTL_GIGA_MAC_VER_16:
4479         case RTL_GIGA_MAC_VER_17:
4480                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4481                 break;
4482         case RTL_GIGA_MAC_VER_18:
4483         case RTL_GIGA_MAC_VER_19:
4484         case RTL_GIGA_MAC_VER_20:
4485         case RTL_GIGA_MAC_VER_21:
4486         case RTL_GIGA_MAC_VER_22:
4487         case RTL_GIGA_MAC_VER_23:
4488         case RTL_GIGA_MAC_VER_24:
4489         case RTL_GIGA_MAC_VER_34:
4490         case RTL_GIGA_MAC_VER_35:
4491                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4492                 break;
4493         case RTL_GIGA_MAC_VER_40:
4494         case RTL_GIGA_MAC_VER_41:
4495         case RTL_GIGA_MAC_VER_42:
4496         case RTL_GIGA_MAC_VER_43:
4497         case RTL_GIGA_MAC_VER_44:
4498         case RTL_GIGA_MAC_VER_45:
4499         case RTL_GIGA_MAC_VER_46:
4500         case RTL_GIGA_MAC_VER_47:
4501         case RTL_GIGA_MAC_VER_48:
4502         case RTL_GIGA_MAC_VER_49:
4503         case RTL_GIGA_MAC_VER_50:
4504         case RTL_GIGA_MAC_VER_51:
4505                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4506                 break;
4507         default:
4508                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4509                 break;
4510         }
4511 }
4512
4513 static int rtl_set_mac_address(struct net_device *dev, void *p)
4514 {
4515         struct rtl8169_private *tp = netdev_priv(dev);
4516         struct device *d = &tp->pci_dev->dev;
4517         struct sockaddr *addr = p;
4518
4519         if (!is_valid_ether_addr(addr->sa_data))
4520                 return -EADDRNOTAVAIL;
4521
4522         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4523
4524         pm_runtime_get_noresume(d);
4525
4526         if (pm_runtime_active(d))
4527                 rtl_rar_set(tp, dev->dev_addr);
4528
4529         pm_runtime_put_noidle(d);
4530
4531         /* Reportedly at least Asus X453MA truncates packets otherwise */
4532         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4533                 rtl_init_rxcfg(tp);
4534
4535         return 0;
4536 }
4537
4538 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4539 {
4540         struct rtl8169_private *tp = netdev_priv(dev);
4541         struct mii_ioctl_data *data = if_mii(ifr);
4542
4543         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4544 }
4545
4546 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4547                           struct mii_ioctl_data *data, int cmd)
4548 {
4549         switch (cmd) {
4550         case SIOCGMIIPHY:
4551                 data->phy_id = 32; /* Internal PHY */
4552                 return 0;
4553
4554         case SIOCGMIIREG:
4555                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4556                 return 0;
4557
4558         case SIOCSMIIREG:
4559                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4560                 return 0;
4561         }
4562         return -EOPNOTSUPP;
4563 }
4564
4565 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4566 {
4567         return -EOPNOTSUPP;
4568 }
4569
4570 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4571 {
4572         if (tp->features & RTL_FEATURE_MSI) {
4573                 pci_disable_msi(pdev);
4574                 tp->features &= ~RTL_FEATURE_MSI;
4575         }
4576 }
4577
4578 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4579 {
4580         struct mdio_ops *ops = &tp->mdio_ops;
4581
4582         switch (tp->mac_version) {
4583         case RTL_GIGA_MAC_VER_27:
4584                 ops->write      = r8168dp_1_mdio_write;
4585                 ops->read       = r8168dp_1_mdio_read;
4586                 break;
4587         case RTL_GIGA_MAC_VER_28:
4588         case RTL_GIGA_MAC_VER_31:
4589                 ops->write      = r8168dp_2_mdio_write;
4590                 ops->read       = r8168dp_2_mdio_read;
4591                 break;
4592         case RTL_GIGA_MAC_VER_40:
4593         case RTL_GIGA_MAC_VER_41:
4594         case RTL_GIGA_MAC_VER_42:
4595         case RTL_GIGA_MAC_VER_43:
4596         case RTL_GIGA_MAC_VER_44:
4597         case RTL_GIGA_MAC_VER_45:
4598         case RTL_GIGA_MAC_VER_46:
4599         case RTL_GIGA_MAC_VER_47:
4600         case RTL_GIGA_MAC_VER_48:
4601         case RTL_GIGA_MAC_VER_49:
4602         case RTL_GIGA_MAC_VER_50:
4603         case RTL_GIGA_MAC_VER_51:
4604                 ops->write      = r8168g_mdio_write;
4605                 ops->read       = r8168g_mdio_read;
4606                 break;
4607         default:
4608                 ops->write      = r8169_mdio_write;
4609                 ops->read       = r8169_mdio_read;
4610                 break;
4611         }
4612 }
4613
4614 static void rtl_speed_down(struct rtl8169_private *tp)
4615 {
4616         u32 adv;
4617         int lpa;
4618
4619         rtl_writephy(tp, 0x1f, 0x0000);
4620         lpa = rtl_readphy(tp, MII_LPA);
4621
4622         if (lpa & (LPA_10HALF | LPA_10FULL))
4623                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4624         else if (lpa & (LPA_100HALF | LPA_100FULL))
4625                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4626                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4627         else
4628                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4629                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4630                       (tp->mii.supports_gmii ?
4631                        ADVERTISED_1000baseT_Half |
4632                        ADVERTISED_1000baseT_Full : 0);
4633
4634         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4635                           adv);
4636 }
4637
4638 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4639 {
4640         void __iomem *ioaddr = tp->mmio_addr;
4641
4642         switch (tp->mac_version) {
4643         case RTL_GIGA_MAC_VER_25:
4644         case RTL_GIGA_MAC_VER_26:
4645         case RTL_GIGA_MAC_VER_29:
4646         case RTL_GIGA_MAC_VER_30:
4647         case RTL_GIGA_MAC_VER_32:
4648         case RTL_GIGA_MAC_VER_33:
4649         case RTL_GIGA_MAC_VER_34:
4650         case RTL_GIGA_MAC_VER_37:
4651         case RTL_GIGA_MAC_VER_38:
4652         case RTL_GIGA_MAC_VER_39:
4653         case RTL_GIGA_MAC_VER_40:
4654         case RTL_GIGA_MAC_VER_41:
4655         case RTL_GIGA_MAC_VER_42:
4656         case RTL_GIGA_MAC_VER_43:
4657         case RTL_GIGA_MAC_VER_44:
4658         case RTL_GIGA_MAC_VER_45:
4659         case RTL_GIGA_MAC_VER_46:
4660         case RTL_GIGA_MAC_VER_47:
4661         case RTL_GIGA_MAC_VER_48:
4662         case RTL_GIGA_MAC_VER_49:
4663         case RTL_GIGA_MAC_VER_50:
4664         case RTL_GIGA_MAC_VER_51:
4665                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4666                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4667                 break;
4668         default:
4669                 break;
4670         }
4671 }
4672
4673 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4674 {
4675         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4676                 return false;
4677
4678         rtl_speed_down(tp);
4679         rtl_wol_suspend_quirk(tp);
4680
4681         return true;
4682 }
4683
4684 static void r810x_phy_power_down(struct rtl8169_private *tp)
4685 {
4686         rtl_writephy(tp, 0x1f, 0x0000);
4687         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4688 }
4689
4690 static void r810x_phy_power_up(struct rtl8169_private *tp)
4691 {
4692         rtl_writephy(tp, 0x1f, 0x0000);
4693         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4694 }
4695
4696 static void r810x_pll_power_down(struct rtl8169_private *tp)
4697 {
4698         void __iomem *ioaddr = tp->mmio_addr;
4699
4700         if (rtl_wol_pll_power_down(tp))
4701                 return;
4702
4703         r810x_phy_power_down(tp);
4704
4705         switch (tp->mac_version) {
4706         case RTL_GIGA_MAC_VER_07:
4707         case RTL_GIGA_MAC_VER_08:
4708         case RTL_GIGA_MAC_VER_09:
4709         case RTL_GIGA_MAC_VER_10:
4710         case RTL_GIGA_MAC_VER_13:
4711         case RTL_GIGA_MAC_VER_16:
4712                 break;
4713         default:
4714                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4715                 break;
4716         }
4717 }
4718
4719 static void r810x_pll_power_up(struct rtl8169_private *tp)
4720 {
4721         void __iomem *ioaddr = tp->mmio_addr;
4722
4723         r810x_phy_power_up(tp);
4724
4725         switch (tp->mac_version) {
4726         case RTL_GIGA_MAC_VER_07:
4727         case RTL_GIGA_MAC_VER_08:
4728         case RTL_GIGA_MAC_VER_09:
4729         case RTL_GIGA_MAC_VER_10:
4730         case RTL_GIGA_MAC_VER_13:
4731         case RTL_GIGA_MAC_VER_16:
4732                 break;
4733         case RTL_GIGA_MAC_VER_47:
4734         case RTL_GIGA_MAC_VER_48:
4735                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4736                 break;
4737         default:
4738                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4739                 break;
4740         }
4741 }
4742
4743 static void r8168_phy_power_up(struct rtl8169_private *tp)
4744 {
4745         rtl_writephy(tp, 0x1f, 0x0000);
4746         switch (tp->mac_version) {
4747         case RTL_GIGA_MAC_VER_11:
4748         case RTL_GIGA_MAC_VER_12:
4749         case RTL_GIGA_MAC_VER_17:
4750         case RTL_GIGA_MAC_VER_18:
4751         case RTL_GIGA_MAC_VER_19:
4752         case RTL_GIGA_MAC_VER_20:
4753         case RTL_GIGA_MAC_VER_21:
4754         case RTL_GIGA_MAC_VER_22:
4755         case RTL_GIGA_MAC_VER_23:
4756         case RTL_GIGA_MAC_VER_24:
4757         case RTL_GIGA_MAC_VER_25:
4758         case RTL_GIGA_MAC_VER_26:
4759         case RTL_GIGA_MAC_VER_27:
4760         case RTL_GIGA_MAC_VER_28:
4761         case RTL_GIGA_MAC_VER_31:
4762                 rtl_writephy(tp, 0x0e, 0x0000);
4763                 break;
4764         default:
4765                 break;
4766         }
4767         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4768 }
4769
4770 static void r8168_phy_power_down(struct rtl8169_private *tp)
4771 {
4772         rtl_writephy(tp, 0x1f, 0x0000);
4773         switch (tp->mac_version) {
4774         case RTL_GIGA_MAC_VER_32:
4775         case RTL_GIGA_MAC_VER_33:
4776         case RTL_GIGA_MAC_VER_40:
4777         case RTL_GIGA_MAC_VER_41:
4778                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4779                 break;
4780
4781         case RTL_GIGA_MAC_VER_11:
4782         case RTL_GIGA_MAC_VER_12:
4783         case RTL_GIGA_MAC_VER_17:
4784         case RTL_GIGA_MAC_VER_18:
4785         case RTL_GIGA_MAC_VER_19:
4786         case RTL_GIGA_MAC_VER_20:
4787         case RTL_GIGA_MAC_VER_21:
4788         case RTL_GIGA_MAC_VER_22:
4789         case RTL_GIGA_MAC_VER_23:
4790         case RTL_GIGA_MAC_VER_24:
4791         case RTL_GIGA_MAC_VER_25:
4792         case RTL_GIGA_MAC_VER_26:
4793         case RTL_GIGA_MAC_VER_27:
4794         case RTL_GIGA_MAC_VER_28:
4795         case RTL_GIGA_MAC_VER_31:
4796                 rtl_writephy(tp, 0x0e, 0x0200);
4797         default:
4798                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4799                 break;
4800         }
4801 }
4802
4803 static void r8168_pll_power_down(struct rtl8169_private *tp)
4804 {
4805         void __iomem *ioaddr = tp->mmio_addr;
4806
4807         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4808              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4809              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4810              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4811              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4812              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4813             r8168_check_dash(tp)) {
4814                 return;
4815         }
4816
4817         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4818              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4819             (RTL_R16(CPlusCmd) & ASF)) {
4820                 return;
4821         }
4822
4823         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4824             tp->mac_version == RTL_GIGA_MAC_VER_33)
4825                 rtl_ephy_write(tp, 0x19, 0xff64);
4826
4827         if (rtl_wol_pll_power_down(tp))
4828                 return;
4829
4830         r8168_phy_power_down(tp);
4831
4832         switch (tp->mac_version) {
4833         case RTL_GIGA_MAC_VER_25:
4834         case RTL_GIGA_MAC_VER_26:
4835         case RTL_GIGA_MAC_VER_27:
4836         case RTL_GIGA_MAC_VER_28:
4837         case RTL_GIGA_MAC_VER_31:
4838         case RTL_GIGA_MAC_VER_32:
4839         case RTL_GIGA_MAC_VER_33:
4840         case RTL_GIGA_MAC_VER_44:
4841         case RTL_GIGA_MAC_VER_45:
4842         case RTL_GIGA_MAC_VER_46:
4843         case RTL_GIGA_MAC_VER_50:
4844         case RTL_GIGA_MAC_VER_51:
4845                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4846                 break;
4847         case RTL_GIGA_MAC_VER_40:
4848         case RTL_GIGA_MAC_VER_41:
4849         case RTL_GIGA_MAC_VER_49:
4850                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4851                              0xfc000000, ERIAR_EXGMAC);
4852                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4853                 break;
4854         }
4855 }
4856
4857 static void r8168_pll_power_up(struct rtl8169_private *tp)
4858 {
4859         void __iomem *ioaddr = tp->mmio_addr;
4860
4861         switch (tp->mac_version) {
4862         case RTL_GIGA_MAC_VER_25:
4863         case RTL_GIGA_MAC_VER_26:
4864         case RTL_GIGA_MAC_VER_27:
4865         case RTL_GIGA_MAC_VER_28:
4866         case RTL_GIGA_MAC_VER_31:
4867         case RTL_GIGA_MAC_VER_32:
4868         case RTL_GIGA_MAC_VER_33:
4869                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4870                 break;
4871         case RTL_GIGA_MAC_VER_44:
4872         case RTL_GIGA_MAC_VER_45:
4873         case RTL_GIGA_MAC_VER_46:
4874         case RTL_GIGA_MAC_VER_50:
4875         case RTL_GIGA_MAC_VER_51:
4876                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4877                 break;
4878         case RTL_GIGA_MAC_VER_40:
4879         case RTL_GIGA_MAC_VER_41:
4880         case RTL_GIGA_MAC_VER_49:
4881                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4882                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4883                              0x00000000, ERIAR_EXGMAC);
4884                 break;
4885         }
4886
4887         r8168_phy_power_up(tp);
4888 }
4889
4890 static void rtl_generic_op(struct rtl8169_private *tp,
4891                            void (*op)(struct rtl8169_private *))
4892 {
4893         if (op)
4894                 op(tp);
4895 }
4896
4897 static void rtl_pll_power_down(struct rtl8169_private *tp)
4898 {
4899         rtl_generic_op(tp, tp->pll_power_ops.down);
4900 }
4901
4902 static void rtl_pll_power_up(struct rtl8169_private *tp)
4903 {
4904         rtl_generic_op(tp, tp->pll_power_ops.up);
4905
4906         /* give MAC/PHY some time to resume */
4907         msleep(20);
4908 }
4909
4910 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4911 {
4912         struct pll_power_ops *ops = &tp->pll_power_ops;
4913
4914         switch (tp->mac_version) {
4915         case RTL_GIGA_MAC_VER_07:
4916         case RTL_GIGA_MAC_VER_08:
4917         case RTL_GIGA_MAC_VER_09:
4918         case RTL_GIGA_MAC_VER_10:
4919         case RTL_GIGA_MAC_VER_16:
4920         case RTL_GIGA_MAC_VER_29:
4921         case RTL_GIGA_MAC_VER_30:
4922         case RTL_GIGA_MAC_VER_37:
4923         case RTL_GIGA_MAC_VER_39:
4924         case RTL_GIGA_MAC_VER_43:
4925         case RTL_GIGA_MAC_VER_47:
4926         case RTL_GIGA_MAC_VER_48:
4927                 ops->down       = r810x_pll_power_down;
4928                 ops->up         = r810x_pll_power_up;
4929                 break;
4930
4931         case RTL_GIGA_MAC_VER_11:
4932         case RTL_GIGA_MAC_VER_12:
4933         case RTL_GIGA_MAC_VER_17:
4934         case RTL_GIGA_MAC_VER_18:
4935         case RTL_GIGA_MAC_VER_19:
4936         case RTL_GIGA_MAC_VER_20:
4937         case RTL_GIGA_MAC_VER_21:
4938         case RTL_GIGA_MAC_VER_22:
4939         case RTL_GIGA_MAC_VER_23:
4940         case RTL_GIGA_MAC_VER_24:
4941         case RTL_GIGA_MAC_VER_25:
4942         case RTL_GIGA_MAC_VER_26:
4943         case RTL_GIGA_MAC_VER_27:
4944         case RTL_GIGA_MAC_VER_28:
4945         case RTL_GIGA_MAC_VER_31:
4946         case RTL_GIGA_MAC_VER_32:
4947         case RTL_GIGA_MAC_VER_33:
4948         case RTL_GIGA_MAC_VER_34:
4949         case RTL_GIGA_MAC_VER_35:
4950         case RTL_GIGA_MAC_VER_36:
4951         case RTL_GIGA_MAC_VER_38:
4952         case RTL_GIGA_MAC_VER_40:
4953         case RTL_GIGA_MAC_VER_41:
4954         case RTL_GIGA_MAC_VER_42:
4955         case RTL_GIGA_MAC_VER_44:
4956         case RTL_GIGA_MAC_VER_45:
4957         case RTL_GIGA_MAC_VER_46:
4958         case RTL_GIGA_MAC_VER_49:
4959         case RTL_GIGA_MAC_VER_50:
4960         case RTL_GIGA_MAC_VER_51:
4961                 ops->down       = r8168_pll_power_down;
4962                 ops->up         = r8168_pll_power_up;
4963                 break;
4964
4965         default:
4966                 ops->down       = NULL;
4967                 ops->up         = NULL;
4968                 break;
4969         }
4970 }
4971
4972 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4973 {
4974         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4975 }
4976
4977 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4978 {
4979         void __iomem *ioaddr = tp->mmio_addr;
4980
4981         RTL_W8(Cfg9346, Cfg9346_Unlock);
4982         rtl_generic_op(tp, tp->jumbo_ops.enable);
4983         RTL_W8(Cfg9346, Cfg9346_Lock);
4984 }
4985
4986 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4987 {
4988         void __iomem *ioaddr = tp->mmio_addr;
4989
4990         RTL_W8(Cfg9346, Cfg9346_Unlock);
4991         rtl_generic_op(tp, tp->jumbo_ops.disable);
4992         RTL_W8(Cfg9346, Cfg9346_Lock);
4993 }
4994
4995 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4996 {
4997         void __iomem *ioaddr = tp->mmio_addr;
4998
4999         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5000         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5001         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5002 }
5003
5004 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5005 {
5006         void __iomem *ioaddr = tp->mmio_addr;
5007
5008         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5009         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5010         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5011 }
5012
5013 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5014 {
5015         void __iomem *ioaddr = tp->mmio_addr;
5016
5017         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5018 }
5019
5020 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5021 {
5022         void __iomem *ioaddr = tp->mmio_addr;
5023
5024         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5025 }
5026
5027 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5028 {
5029         void __iomem *ioaddr = tp->mmio_addr;
5030
5031         RTL_W8(MaxTxPacketSize, 0x3f);
5032         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5033         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5034         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5035 }
5036
5037 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5038 {
5039         void __iomem *ioaddr = tp->mmio_addr;
5040
5041         RTL_W8(MaxTxPacketSize, 0x0c);
5042         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5043         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5044         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5045 }
5046
5047 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5048 {
5049         rtl_tx_performance_tweak(tp->pci_dev,
5050                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5051 }
5052
5053 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5054 {
5055         rtl_tx_performance_tweak(tp->pci_dev,
5056                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5057 }
5058
5059 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5060 {
5061         void __iomem *ioaddr = tp->mmio_addr;
5062
5063         r8168b_0_hw_jumbo_enable(tp);
5064
5065         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5066 }
5067
5068 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5069 {
5070         void __iomem *ioaddr = tp->mmio_addr;
5071
5072         r8168b_0_hw_jumbo_disable(tp);
5073
5074         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5075 }
5076
5077 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5078 {
5079         struct jumbo_ops *ops = &tp->jumbo_ops;
5080
5081         switch (tp->mac_version) {
5082         case RTL_GIGA_MAC_VER_11:
5083                 ops->disable    = r8168b_0_hw_jumbo_disable;
5084                 ops->enable     = r8168b_0_hw_jumbo_enable;
5085                 break;
5086         case RTL_GIGA_MAC_VER_12:
5087         case RTL_GIGA_MAC_VER_17:
5088                 ops->disable    = r8168b_1_hw_jumbo_disable;
5089                 ops->enable     = r8168b_1_hw_jumbo_enable;
5090                 break;
5091         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5092         case RTL_GIGA_MAC_VER_19:
5093         case RTL_GIGA_MAC_VER_20:
5094         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5095         case RTL_GIGA_MAC_VER_22:
5096         case RTL_GIGA_MAC_VER_23:
5097         case RTL_GIGA_MAC_VER_24:
5098         case RTL_GIGA_MAC_VER_25:
5099         case RTL_GIGA_MAC_VER_26:
5100                 ops->disable    = r8168c_hw_jumbo_disable;
5101                 ops->enable     = r8168c_hw_jumbo_enable;
5102                 break;
5103         case RTL_GIGA_MAC_VER_27:
5104         case RTL_GIGA_MAC_VER_28:
5105                 ops->disable    = r8168dp_hw_jumbo_disable;
5106                 ops->enable     = r8168dp_hw_jumbo_enable;
5107                 break;
5108         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5109         case RTL_GIGA_MAC_VER_32:
5110         case RTL_GIGA_MAC_VER_33:
5111         case RTL_GIGA_MAC_VER_34:
5112                 ops->disable    = r8168e_hw_jumbo_disable;
5113                 ops->enable     = r8168e_hw_jumbo_enable;
5114                 break;
5115
5116         /*
5117          * No action needed for jumbo frames with 8169.
5118          * No jumbo for 810x at all.
5119          */
5120         case RTL_GIGA_MAC_VER_40:
5121         case RTL_GIGA_MAC_VER_41:
5122         case RTL_GIGA_MAC_VER_42:
5123         case RTL_GIGA_MAC_VER_43:
5124         case RTL_GIGA_MAC_VER_44:
5125         case RTL_GIGA_MAC_VER_45:
5126         case RTL_GIGA_MAC_VER_46:
5127         case RTL_GIGA_MAC_VER_47:
5128         case RTL_GIGA_MAC_VER_48:
5129         case RTL_GIGA_MAC_VER_49:
5130         case RTL_GIGA_MAC_VER_50:
5131         case RTL_GIGA_MAC_VER_51:
5132         default:
5133                 ops->disable    = NULL;
5134                 ops->enable     = NULL;
5135                 break;
5136         }
5137 }
5138
5139 DECLARE_RTL_COND(rtl_chipcmd_cond)
5140 {
5141         void __iomem *ioaddr = tp->mmio_addr;
5142
5143         return RTL_R8(ChipCmd) & CmdReset;
5144 }
5145
5146 static void rtl_hw_reset(struct rtl8169_private *tp)
5147 {
5148         void __iomem *ioaddr = tp->mmio_addr;
5149
5150         RTL_W8(ChipCmd, CmdReset);
5151
5152         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5153 }
5154
5155 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5156 {
5157         struct rtl_fw *rtl_fw;
5158         const char *name;
5159         int rc = -ENOMEM;
5160
5161         name = rtl_lookup_firmware_name(tp);
5162         if (!name)
5163                 goto out_no_firmware;
5164
5165         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5166         if (!rtl_fw)
5167                 goto err_warn;
5168
5169         rc = reject_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5170         if (rc < 0)
5171                 goto err_free;
5172
5173         rc = rtl_check_firmware(tp, rtl_fw);
5174         if (rc < 0)
5175                 goto err_release_firmware;
5176
5177         tp->rtl_fw = rtl_fw;
5178 out:
5179         return;
5180
5181 err_release_firmware:
5182         release_firmware(rtl_fw->fw);
5183 err_free:
5184         kfree(rtl_fw);
5185 err_warn:
5186         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5187                    name, rc);
5188 out_no_firmware:
5189         tp->rtl_fw = NULL;
5190         goto out;
5191 }
5192
5193 static void rtl_request_firmware(struct rtl8169_private *tp)
5194 {
5195         if (IS_ERR(tp->rtl_fw))
5196                 rtl_request_uncached_firmware(tp);
5197 }
5198
5199 static void rtl_rx_close(struct rtl8169_private *tp)
5200 {
5201         void __iomem *ioaddr = tp->mmio_addr;
5202
5203         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5204 }
5205
5206 DECLARE_RTL_COND(rtl_npq_cond)
5207 {
5208         void __iomem *ioaddr = tp->mmio_addr;
5209
5210         return RTL_R8(TxPoll) & NPQ;
5211 }
5212
5213 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5214 {
5215         void __iomem *ioaddr = tp->mmio_addr;
5216
5217         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5218 }
5219
5220 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5221 {
5222         void __iomem *ioaddr = tp->mmio_addr;
5223
5224         /* Disable interrupts */
5225         rtl8169_irq_mask_and_ack(tp);
5226
5227         rtl_rx_close(tp);
5228
5229         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5230             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5231             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5232                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5233         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5234                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5235                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5236                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5237                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5238                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5239                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5240                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5241                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5242                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5243                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5244                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5245                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5246                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5247                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5248                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5249                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5250                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5251                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5252         } else {
5253                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5254                 udelay(100);
5255         }
5256
5257         rtl_hw_reset(tp);
5258 }
5259
5260 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5261 {
5262         void __iomem *ioaddr = tp->mmio_addr;
5263
5264         /* Set DMA burst size and Interframe Gap Time */
5265         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5266                 (InterFrameGap << TxInterFrameGapShift));
5267 }
5268
5269 static void rtl_hw_start(struct net_device *dev)
5270 {
5271         struct rtl8169_private *tp = netdev_priv(dev);
5272
5273         tp->hw_start(dev);
5274
5275         rtl_irq_enable_all(tp);
5276 }
5277
5278 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5279                                          void __iomem *ioaddr)
5280 {
5281         /*
5282          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5283          * register to be written before TxDescAddrLow to work.
5284          * Switching from MMIO to I/O access fixes the issue as well.
5285          */
5286         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5287         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5288         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5289         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5290 }
5291
5292 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5293 {
5294         u16 cmd;
5295
5296         cmd = RTL_R16(CPlusCmd);
5297         RTL_W16(CPlusCmd, cmd);
5298         return cmd;
5299 }
5300
5301 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5302 {
5303         /* Low hurts. Let's disable the filtering. */
5304         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5305 }
5306
5307 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5308 {
5309         static const struct rtl_cfg2_info {
5310                 u32 mac_version;
5311                 u32 clk;
5312                 u32 val;
5313         } cfg2_info [] = {
5314                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5315                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5316                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5317                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5318         };
5319         const struct rtl_cfg2_info *p = cfg2_info;
5320         unsigned int i;
5321         u32 clk;
5322
5323         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5324         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5325                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5326                         RTL_W32(0x7c, p->val);
5327                         break;
5328                 }
5329         }
5330 }
5331
5332 static void rtl_set_rx_mode(struct net_device *dev)
5333 {
5334         struct rtl8169_private *tp = netdev_priv(dev);
5335         void __iomem *ioaddr = tp->mmio_addr;
5336         u32 mc_filter[2];       /* Multicast hash filter */
5337         int rx_mode;
5338         u32 tmp = 0;
5339
5340         if (dev->flags & IFF_PROMISC) {
5341                 /* Unconditionally log net taps. */
5342                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5343                 rx_mode =
5344                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5345                     AcceptAllPhys;
5346                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5347         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5348                    (dev->flags & IFF_ALLMULTI)) {
5349                 /* Too many to filter perfectly -- accept all multicasts. */
5350                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5351                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5352         } else {
5353                 struct netdev_hw_addr *ha;
5354
5355                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5356                 mc_filter[1] = mc_filter[0] = 0;
5357                 netdev_for_each_mc_addr(ha, dev) {
5358                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5359                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5360                         rx_mode |= AcceptMulticast;
5361                 }
5362         }
5363
5364         if (dev->features & NETIF_F_RXALL)
5365                 rx_mode |= (AcceptErr | AcceptRunt);
5366
5367         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5368
5369         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5370                 u32 data = mc_filter[0];
5371
5372                 mc_filter[0] = swab32(mc_filter[1]);
5373                 mc_filter[1] = swab32(data);
5374         }
5375
5376         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5377                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5378
5379         RTL_W32(MAR0 + 4, mc_filter[1]);
5380         RTL_W32(MAR0 + 0, mc_filter[0]);
5381
5382         RTL_W32(RxConfig, tmp);
5383 }
5384
5385 static void rtl_hw_start_8169(struct net_device *dev)
5386 {
5387         struct rtl8169_private *tp = netdev_priv(dev);
5388         void __iomem *ioaddr = tp->mmio_addr;
5389         struct pci_dev *pdev = tp->pci_dev;
5390
5391         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5392                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5393                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5394         }
5395
5396         RTL_W8(Cfg9346, Cfg9346_Unlock);
5397         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5398             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5399             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5400             tp->mac_version == RTL_GIGA_MAC_VER_04)
5401                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5402
5403         rtl_init_rxcfg(tp);
5404
5405         RTL_W8(EarlyTxThres, NoEarlyTx);
5406
5407         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5408
5409         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5410             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5411             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5412             tp->mac_version == RTL_GIGA_MAC_VER_04)
5413                 rtl_set_rx_tx_config_registers(tp);
5414
5415         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5416
5417         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5418             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5419                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5420                         "Bit-3 and bit-14 MUST be 1\n");
5421                 tp->cp_cmd |= (1 << 14);
5422         }
5423
5424         RTL_W16(CPlusCmd, tp->cp_cmd);
5425
5426         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5427
5428         /*
5429          * Undocumented corner. Supposedly:
5430          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5431          */
5432         RTL_W16(IntrMitigate, 0x0000);
5433
5434         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5435
5436         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5437             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5438             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5439             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5440                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5441                 rtl_set_rx_tx_config_registers(tp);
5442         }
5443
5444         RTL_W8(Cfg9346, Cfg9346_Lock);
5445
5446         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5447         RTL_R8(IntrMask);
5448
5449         RTL_W32(RxMissed, 0);
5450
5451         rtl_set_rx_mode(dev);
5452
5453         /* no early-rx interrupts */
5454         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5455 }
5456
5457 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5458 {
5459         if (tp->csi_ops.write)
5460                 tp->csi_ops.write(tp, addr, value);
5461 }
5462
5463 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5464 {
5465         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5466 }
5467
5468 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5469 {
5470         u32 csi;
5471
5472         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5473         rtl_csi_write(tp, 0x070c, csi | bits);
5474 }
5475
5476 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5477 {
5478         rtl_csi_access_enable(tp, 0x17000000);
5479 }
5480
5481 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5482 {
5483         rtl_csi_access_enable(tp, 0x27000000);
5484 }
5485
5486 DECLARE_RTL_COND(rtl_csiar_cond)
5487 {
5488         void __iomem *ioaddr = tp->mmio_addr;
5489
5490         return RTL_R32(CSIAR) & CSIAR_FLAG;
5491 }
5492
5493 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5494 {
5495         void __iomem *ioaddr = tp->mmio_addr;
5496
5497         RTL_W32(CSIDR, value);
5498         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5499                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5500
5501         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5502 }
5503
5504 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5505 {
5506         void __iomem *ioaddr = tp->mmio_addr;
5507
5508         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5509                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5510
5511         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5512                 RTL_R32(CSIDR) : ~0;
5513 }
5514
5515 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5516 {
5517         void __iomem *ioaddr = tp->mmio_addr;
5518
5519         RTL_W32(CSIDR, value);
5520         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5521                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5522                 CSIAR_FUNC_NIC);
5523
5524         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5525 }
5526
5527 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5528 {
5529         void __iomem *ioaddr = tp->mmio_addr;
5530
5531         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5532                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5533
5534         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5535                 RTL_R32(CSIDR) : ~0;
5536 }
5537
5538 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5539 {
5540         void __iomem *ioaddr = tp->mmio_addr;
5541
5542         RTL_W32(CSIDR, value);
5543         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5544                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5545                 CSIAR_FUNC_NIC2);
5546
5547         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5548 }
5549
5550 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5551 {
5552         void __iomem *ioaddr = tp->mmio_addr;
5553
5554         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5555                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5556
5557         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5558                 RTL_R32(CSIDR) : ~0;
5559 }
5560
5561 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5562 {
5563         struct csi_ops *ops = &tp->csi_ops;
5564
5565         switch (tp->mac_version) {
5566         case RTL_GIGA_MAC_VER_01:
5567         case RTL_GIGA_MAC_VER_02:
5568         case RTL_GIGA_MAC_VER_03:
5569         case RTL_GIGA_MAC_VER_04:
5570         case RTL_GIGA_MAC_VER_05:
5571         case RTL_GIGA_MAC_VER_06:
5572         case RTL_GIGA_MAC_VER_10:
5573         case RTL_GIGA_MAC_VER_11:
5574         case RTL_GIGA_MAC_VER_12:
5575         case RTL_GIGA_MAC_VER_13:
5576         case RTL_GIGA_MAC_VER_14:
5577         case RTL_GIGA_MAC_VER_15:
5578         case RTL_GIGA_MAC_VER_16:
5579         case RTL_GIGA_MAC_VER_17:
5580                 ops->write      = NULL;
5581                 ops->read       = NULL;
5582                 break;
5583
5584         case RTL_GIGA_MAC_VER_37:
5585         case RTL_GIGA_MAC_VER_38:
5586                 ops->write      = r8402_csi_write;
5587                 ops->read       = r8402_csi_read;
5588                 break;
5589
5590         case RTL_GIGA_MAC_VER_44:
5591                 ops->write      = r8411_csi_write;
5592                 ops->read       = r8411_csi_read;
5593                 break;
5594
5595         default:
5596                 ops->write      = r8169_csi_write;
5597                 ops->read       = r8169_csi_read;
5598                 break;
5599         }
5600 }
5601
5602 struct ephy_info {
5603         unsigned int offset;
5604         u16 mask;
5605         u16 bits;
5606 };
5607
5608 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5609                           int len)
5610 {
5611         u16 w;
5612
5613         while (len-- > 0) {
5614                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5615                 rtl_ephy_write(tp, e->offset, w);
5616                 e++;
5617         }
5618 }
5619
5620 static void rtl_disable_clock_request(struct pci_dev *pdev)
5621 {
5622         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5623                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5624 }
5625
5626 static void rtl_enable_clock_request(struct pci_dev *pdev)
5627 {
5628         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5629                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5630 }
5631
5632 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5633 {
5634         void __iomem *ioaddr = tp->mmio_addr;
5635         u8 data;
5636
5637         data = RTL_R8(Config3);
5638
5639         if (enable)
5640                 data |= Rdy_to_L23;
5641         else
5642                 data &= ~Rdy_to_L23;
5643
5644         RTL_W8(Config3, data);
5645 }
5646
5647 #define R8168_CPCMD_QUIRK_MASK (\
5648         EnableBist | \
5649         Mac_dbgo_oe | \
5650         Force_half_dup | \
5651         Force_rxflow_en | \
5652         Force_txflow_en | \
5653         Cxpl_dbg_sel | \
5654         ASF | \
5655         PktCntrDisable | \
5656         Mac_dbgo_sel)
5657
5658 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5659 {
5660         void __iomem *ioaddr = tp->mmio_addr;
5661         struct pci_dev *pdev = tp->pci_dev;
5662
5663         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5664
5665         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5666
5667         if (tp->dev->mtu <= ETH_DATA_LEN) {
5668                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5669                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5670         }
5671 }
5672
5673 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5674 {
5675         void __iomem *ioaddr = tp->mmio_addr;
5676
5677         rtl_hw_start_8168bb(tp);
5678
5679         RTL_W8(MaxTxPacketSize, TxPacketMax);
5680
5681         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5682 }
5683
5684 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5685 {
5686         void __iomem *ioaddr = tp->mmio_addr;
5687         struct pci_dev *pdev = tp->pci_dev;
5688
5689         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5690
5691         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5692
5693         if (tp->dev->mtu <= ETH_DATA_LEN)
5694                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5695
5696         rtl_disable_clock_request(pdev);
5697
5698         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5699 }
5700
5701 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5702 {
5703         static const struct ephy_info e_info_8168cp[] = {
5704                 { 0x01, 0,      0x0001 },
5705                 { 0x02, 0x0800, 0x1000 },
5706                 { 0x03, 0,      0x0042 },
5707                 { 0x06, 0x0080, 0x0000 },
5708                 { 0x07, 0,      0x2000 }
5709         };
5710
5711         rtl_csi_access_enable_2(tp);
5712
5713         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5714
5715         __rtl_hw_start_8168cp(tp);
5716 }
5717
5718 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5719 {
5720         void __iomem *ioaddr = tp->mmio_addr;
5721         struct pci_dev *pdev = tp->pci_dev;
5722
5723         rtl_csi_access_enable_2(tp);
5724
5725         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5726
5727         if (tp->dev->mtu <= ETH_DATA_LEN)
5728                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5729
5730         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5731 }
5732
5733 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5734 {
5735         void __iomem *ioaddr = tp->mmio_addr;
5736         struct pci_dev *pdev = tp->pci_dev;
5737
5738         rtl_csi_access_enable_2(tp);
5739
5740         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5741
5742         /* Magic. */
5743         RTL_W8(DBG_REG, 0x20);
5744
5745         RTL_W8(MaxTxPacketSize, TxPacketMax);
5746
5747         if (tp->dev->mtu <= ETH_DATA_LEN)
5748                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5749
5750         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5751 }
5752
5753 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5754 {
5755         void __iomem *ioaddr = tp->mmio_addr;
5756         static const struct ephy_info e_info_8168c_1[] = {
5757                 { 0x02, 0x0800, 0x1000 },
5758                 { 0x03, 0,      0x0002 },
5759                 { 0x06, 0x0080, 0x0000 }
5760         };
5761
5762         rtl_csi_access_enable_2(tp);
5763
5764         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5765
5766         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5767
5768         __rtl_hw_start_8168cp(tp);
5769 }
5770
5771 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5772 {
5773         static const struct ephy_info e_info_8168c_2[] = {
5774                 { 0x01, 0,      0x0001 },
5775                 { 0x03, 0x0400, 0x0220 }
5776         };
5777
5778         rtl_csi_access_enable_2(tp);
5779
5780         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5781
5782         __rtl_hw_start_8168cp(tp);
5783 }
5784
5785 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5786 {
5787         rtl_hw_start_8168c_2(tp);
5788 }
5789
5790 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5791 {
5792         rtl_csi_access_enable_2(tp);
5793
5794         __rtl_hw_start_8168cp(tp);
5795 }
5796
5797 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5798 {
5799         void __iomem *ioaddr = tp->mmio_addr;
5800         struct pci_dev *pdev = tp->pci_dev;
5801
5802         rtl_csi_access_enable_2(tp);
5803
5804         rtl_disable_clock_request(pdev);
5805
5806         RTL_W8(MaxTxPacketSize, TxPacketMax);
5807
5808         if (tp->dev->mtu <= ETH_DATA_LEN)
5809                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5810
5811         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5812 }
5813
5814 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5815 {
5816         void __iomem *ioaddr = tp->mmio_addr;
5817         struct pci_dev *pdev = tp->pci_dev;
5818
5819         rtl_csi_access_enable_1(tp);
5820
5821         if (tp->dev->mtu <= ETH_DATA_LEN)
5822                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5823
5824         RTL_W8(MaxTxPacketSize, TxPacketMax);
5825
5826         rtl_disable_clock_request(pdev);
5827 }
5828
5829 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5830 {
5831         void __iomem *ioaddr = tp->mmio_addr;
5832         struct pci_dev *pdev = tp->pci_dev;
5833         static const struct ephy_info e_info_8168d_4[] = {
5834                 { 0x0b, 0x0000, 0x0048 },
5835                 { 0x19, 0x0020, 0x0050 },
5836                 { 0x0c, 0x0100, 0x0020 }
5837         };
5838
5839         rtl_csi_access_enable_1(tp);
5840
5841         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5842
5843         RTL_W8(MaxTxPacketSize, TxPacketMax);
5844
5845         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5846
5847         rtl_enable_clock_request(pdev);
5848 }
5849
5850 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5851 {
5852         void __iomem *ioaddr = tp->mmio_addr;
5853         struct pci_dev *pdev = tp->pci_dev;
5854         static const struct ephy_info e_info_8168e_1[] = {
5855                 { 0x00, 0x0200, 0x0100 },
5856                 { 0x00, 0x0000, 0x0004 },
5857                 { 0x06, 0x0002, 0x0001 },
5858                 { 0x06, 0x0000, 0x0030 },
5859                 { 0x07, 0x0000, 0x2000 },
5860                 { 0x00, 0x0000, 0x0020 },
5861                 { 0x03, 0x5800, 0x2000 },
5862                 { 0x03, 0x0000, 0x0001 },
5863                 { 0x01, 0x0800, 0x1000 },
5864                 { 0x07, 0x0000, 0x4000 },
5865                 { 0x1e, 0x0000, 0x2000 },
5866                 { 0x19, 0xffff, 0xfe6c },
5867                 { 0x0a, 0x0000, 0x0040 }
5868         };
5869
5870         rtl_csi_access_enable_2(tp);
5871
5872         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5873
5874         if (tp->dev->mtu <= ETH_DATA_LEN)
5875                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5876
5877         RTL_W8(MaxTxPacketSize, TxPacketMax);
5878
5879         rtl_disable_clock_request(pdev);
5880
5881         /* Reset tx FIFO pointer */
5882         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5883         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5884
5885         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5886 }
5887
5888 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5889 {
5890         void __iomem *ioaddr = tp->mmio_addr;
5891         struct pci_dev *pdev = tp->pci_dev;
5892         static const struct ephy_info e_info_8168e_2[] = {
5893                 { 0x09, 0x0000, 0x0080 },
5894                 { 0x19, 0x0000, 0x0224 }
5895         };
5896
5897         rtl_csi_access_enable_1(tp);
5898
5899         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5900
5901         if (tp->dev->mtu <= ETH_DATA_LEN)
5902                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5903
5904         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5905         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5906         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5907         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5908         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5909         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5910         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5911         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5912
5913         RTL_W8(MaxTxPacketSize, EarlySize);
5914
5915         rtl_disable_clock_request(pdev);
5916
5917         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5918         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5919
5920         /* Adjust EEE LED frequency */
5921         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5922
5923         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5924         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5925         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5926 }
5927
5928 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5929 {
5930         void __iomem *ioaddr = tp->mmio_addr;
5931         struct pci_dev *pdev = tp->pci_dev;
5932
5933         rtl_csi_access_enable_2(tp);
5934
5935         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5936
5937         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5938         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5939         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5940         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5941         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5942         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5943         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5944         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5945         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5946         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5947
5948         RTL_W8(MaxTxPacketSize, EarlySize);
5949
5950         rtl_disable_clock_request(pdev);
5951
5952         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5953         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5954         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5955         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5956         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5957 }
5958
5959 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5960 {
5961         void __iomem *ioaddr = tp->mmio_addr;
5962         static const struct ephy_info e_info_8168f_1[] = {
5963                 { 0x06, 0x00c0, 0x0020 },
5964                 { 0x08, 0x0001, 0x0002 },
5965                 { 0x09, 0x0000, 0x0080 },
5966                 { 0x19, 0x0000, 0x0224 }
5967         };
5968
5969         rtl_hw_start_8168f(tp);
5970
5971         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5972
5973         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5974
5975         /* Adjust EEE LED frequency */
5976         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5977 }
5978
5979 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5980 {
5981         static const struct ephy_info e_info_8168f_1[] = {
5982                 { 0x06, 0x00c0, 0x0020 },
5983                 { 0x0f, 0xffff, 0x5200 },
5984                 { 0x1e, 0x0000, 0x4000 },
5985                 { 0x19, 0x0000, 0x0224 }
5986         };
5987
5988         rtl_hw_start_8168f(tp);
5989         rtl_pcie_state_l2l3_enable(tp, false);
5990
5991         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5992
5993         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5994 }
5995
5996 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5997 {
5998         void __iomem *ioaddr = tp->mmio_addr;
5999         struct pci_dev *pdev = tp->pci_dev;
6000
6001         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6002
6003         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6004         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6005         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6006         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6007
6008         rtl_csi_access_enable_1(tp);
6009
6010         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6011
6012         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6013         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6014         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6015
6016         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6017         RTL_W8(MaxTxPacketSize, EarlySize);
6018
6019         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6020         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6021
6022         /* Adjust EEE LED frequency */
6023         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6024
6025         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6026         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6027
6028         rtl_pcie_state_l2l3_enable(tp, false);
6029 }
6030
6031 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6032 {
6033         void __iomem *ioaddr = tp->mmio_addr;
6034         static const struct ephy_info e_info_8168g_1[] = {
6035                 { 0x00, 0x0000, 0x0008 },
6036                 { 0x0c, 0x37d0, 0x0820 },
6037                 { 0x1e, 0x0000, 0x0001 },
6038                 { 0x19, 0x8000, 0x0000 }
6039         };
6040
6041         rtl_hw_start_8168g(tp);
6042
6043         /* disable aspm and clock request before access ephy */
6044         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6045         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6046         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6047 }
6048
6049 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6050 {
6051         void __iomem *ioaddr = tp->mmio_addr;
6052         static const struct ephy_info e_info_8168g_2[] = {
6053                 { 0x00, 0x0000, 0x0008 },
6054                 { 0x0c, 0x3df0, 0x0200 },
6055                 { 0x19, 0xffff, 0xfc00 },
6056                 { 0x1e, 0xffff, 0x20eb }
6057         };
6058
6059         rtl_hw_start_8168g(tp);
6060
6061         /* disable aspm and clock request before access ephy */
6062         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6063         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6064         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6065 }
6066
6067 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6068 {
6069         void __iomem *ioaddr = tp->mmio_addr;
6070         static const struct ephy_info e_info_8411_2[] = {
6071                 { 0x00, 0x0000, 0x0008 },
6072                 { 0x0c, 0x3df0, 0x0200 },
6073                 { 0x0f, 0xffff, 0x5200 },
6074                 { 0x19, 0x0020, 0x0000 },
6075                 { 0x1e, 0x0000, 0x2000 }
6076         };
6077
6078         rtl_hw_start_8168g(tp);
6079
6080         /* disable aspm and clock request before access ephy */
6081         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6082         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6083         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6084 }
6085
6086 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6087 {
6088         void __iomem *ioaddr = tp->mmio_addr;
6089         struct pci_dev *pdev = tp->pci_dev;
6090         int rg_saw_cnt;
6091         u32 data;
6092         static const struct ephy_info e_info_8168h_1[] = {
6093                 { 0x1e, 0x0800, 0x0001 },
6094                 { 0x1d, 0x0000, 0x0800 },
6095                 { 0x05, 0xffff, 0x2089 },
6096                 { 0x06, 0xffff, 0x5881 },
6097                 { 0x04, 0xffff, 0x154a },
6098                 { 0x01, 0xffff, 0x068b }
6099         };
6100
6101         /* disable aspm and clock request before access ephy */
6102         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6103         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6104         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6105
6106         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6107
6108         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6109         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6110         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6111         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6112
6113         rtl_csi_access_enable_1(tp);
6114
6115         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6116
6117         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6118         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6119
6120         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6121
6122         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6123
6124         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6125
6126         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6127         RTL_W8(MaxTxPacketSize, EarlySize);
6128
6129         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6130         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6131
6132         /* Adjust EEE LED frequency */
6133         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6134
6135         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6136         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6137
6138         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6139
6140         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6141
6142         rtl_pcie_state_l2l3_enable(tp, false);
6143
6144         rtl_writephy(tp, 0x1f, 0x0c42);
6145         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6146         rtl_writephy(tp, 0x1f, 0x0000);
6147         if (rg_saw_cnt > 0) {
6148                 u16 sw_cnt_1ms_ini;
6149
6150                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6151                 sw_cnt_1ms_ini &= 0x0fff;
6152                 data = r8168_mac_ocp_read(tp, 0xd412);
6153                 data &= ~0x0fff;
6154                 data |= sw_cnt_1ms_ini;
6155                 r8168_mac_ocp_write(tp, 0xd412, data);
6156         }
6157
6158         data = r8168_mac_ocp_read(tp, 0xe056);
6159         data &= ~0xf0;
6160         data |= 0x70;
6161         r8168_mac_ocp_write(tp, 0xe056, data);
6162
6163         data = r8168_mac_ocp_read(tp, 0xe052);
6164         data &= ~0x6000;
6165         data |= 0x8008;
6166         r8168_mac_ocp_write(tp, 0xe052, data);
6167
6168         data = r8168_mac_ocp_read(tp, 0xe0d6);
6169         data &= ~0x01ff;
6170         data |= 0x017f;
6171         r8168_mac_ocp_write(tp, 0xe0d6, data);
6172
6173         data = r8168_mac_ocp_read(tp, 0xd420);
6174         data &= ~0x0fff;
6175         data |= 0x047f;
6176         r8168_mac_ocp_write(tp, 0xd420, data);
6177
6178         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6179         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6180         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6181         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6182 }
6183
6184 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6185 {
6186         void __iomem *ioaddr = tp->mmio_addr;
6187         struct pci_dev *pdev = tp->pci_dev;
6188
6189         rtl8168ep_stop_cmac(tp);
6190
6191         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6192
6193         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6194         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6195         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6196         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6197
6198         rtl_csi_access_enable_1(tp);
6199
6200         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6201
6202         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6203         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6204
6205         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6206
6207         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6208
6209         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6210         RTL_W8(MaxTxPacketSize, EarlySize);
6211
6212         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6213         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6214
6215         /* Adjust EEE LED frequency */
6216         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6217
6218         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6219
6220         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6221
6222         rtl_pcie_state_l2l3_enable(tp, false);
6223 }
6224
6225 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6226 {
6227         void __iomem *ioaddr = tp->mmio_addr;
6228         static const struct ephy_info e_info_8168ep_1[] = {
6229                 { 0x00, 0xffff, 0x10ab },
6230                 { 0x06, 0xffff, 0xf030 },
6231                 { 0x08, 0xffff, 0x2006 },
6232                 { 0x0d, 0xffff, 0x1666 },
6233                 { 0x0c, 0x3ff0, 0x0000 }
6234         };
6235
6236         /* disable aspm and clock request before access ephy */
6237         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6238         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6239         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6240
6241         rtl_hw_start_8168ep(tp);
6242 }
6243
6244 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6245 {
6246         void __iomem *ioaddr = tp->mmio_addr;
6247         static const struct ephy_info e_info_8168ep_2[] = {
6248                 { 0x00, 0xffff, 0x10a3 },
6249                 { 0x19, 0xffff, 0xfc00 },
6250                 { 0x1e, 0xffff, 0x20ea }
6251         };
6252
6253         /* disable aspm and clock request before access ephy */
6254         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6255         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6256         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6257
6258         rtl_hw_start_8168ep(tp);
6259
6260         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6261         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6262 }
6263
6264 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6265 {
6266         void __iomem *ioaddr = tp->mmio_addr;
6267         u32 data;
6268         static const struct ephy_info e_info_8168ep_3[] = {
6269                 { 0x00, 0xffff, 0x10a3 },
6270                 { 0x19, 0xffff, 0x7c00 },
6271                 { 0x1e, 0xffff, 0x20eb },
6272                 { 0x0d, 0xffff, 0x1666 }
6273         };
6274
6275         /* disable aspm and clock request before access ephy */
6276         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6277         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6278         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6279
6280         rtl_hw_start_8168ep(tp);
6281
6282         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6283         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6284
6285         data = r8168_mac_ocp_read(tp, 0xd3e2);
6286         data &= 0xf000;
6287         data |= 0x0271;
6288         r8168_mac_ocp_write(tp, 0xd3e2, data);
6289
6290         data = r8168_mac_ocp_read(tp, 0xd3e4);
6291         data &= 0xff00;
6292         r8168_mac_ocp_write(tp, 0xd3e4, data);
6293
6294         data = r8168_mac_ocp_read(tp, 0xe860);
6295         data |= 0x0080;
6296         r8168_mac_ocp_write(tp, 0xe860, data);
6297 }
6298
6299 static void rtl_hw_start_8168(struct net_device *dev)
6300 {
6301         struct rtl8169_private *tp = netdev_priv(dev);
6302         void __iomem *ioaddr = tp->mmio_addr;
6303
6304         RTL_W8(Cfg9346, Cfg9346_Unlock);
6305
6306         RTL_W8(MaxTxPacketSize, TxPacketMax);
6307
6308         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6309
6310         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6311
6312         RTL_W16(CPlusCmd, tp->cp_cmd);
6313
6314         RTL_W16(IntrMitigate, 0x5151);
6315
6316         /* Work around for RxFIFO overflow. */
6317         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6318                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6319                 tp->event_slow &= ~RxOverflow;
6320         }
6321
6322         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6323
6324         rtl_set_rx_tx_config_registers(tp);
6325
6326         RTL_R8(IntrMask);
6327
6328         switch (tp->mac_version) {
6329         case RTL_GIGA_MAC_VER_11:
6330                 rtl_hw_start_8168bb(tp);
6331                 break;
6332
6333         case RTL_GIGA_MAC_VER_12:
6334         case RTL_GIGA_MAC_VER_17:
6335                 rtl_hw_start_8168bef(tp);
6336                 break;
6337
6338         case RTL_GIGA_MAC_VER_18:
6339                 rtl_hw_start_8168cp_1(tp);
6340                 break;
6341
6342         case RTL_GIGA_MAC_VER_19:
6343                 rtl_hw_start_8168c_1(tp);
6344                 break;
6345
6346         case RTL_GIGA_MAC_VER_20:
6347                 rtl_hw_start_8168c_2(tp);
6348                 break;
6349
6350         case RTL_GIGA_MAC_VER_21:
6351                 rtl_hw_start_8168c_3(tp);
6352                 break;
6353
6354         case RTL_GIGA_MAC_VER_22:
6355                 rtl_hw_start_8168c_4(tp);
6356                 break;
6357
6358         case RTL_GIGA_MAC_VER_23:
6359                 rtl_hw_start_8168cp_2(tp);
6360                 break;
6361
6362         case RTL_GIGA_MAC_VER_24:
6363                 rtl_hw_start_8168cp_3(tp);
6364                 break;
6365
6366         case RTL_GIGA_MAC_VER_25:
6367         case RTL_GIGA_MAC_VER_26:
6368         case RTL_GIGA_MAC_VER_27:
6369                 rtl_hw_start_8168d(tp);
6370                 break;
6371
6372         case RTL_GIGA_MAC_VER_28:
6373                 rtl_hw_start_8168d_4(tp);
6374                 break;
6375
6376         case RTL_GIGA_MAC_VER_31:
6377                 rtl_hw_start_8168dp(tp);
6378                 break;
6379
6380         case RTL_GIGA_MAC_VER_32:
6381         case RTL_GIGA_MAC_VER_33:
6382                 rtl_hw_start_8168e_1(tp);
6383                 break;
6384         case RTL_GIGA_MAC_VER_34:
6385                 rtl_hw_start_8168e_2(tp);
6386                 break;
6387
6388         case RTL_GIGA_MAC_VER_35:
6389         case RTL_GIGA_MAC_VER_36:
6390                 rtl_hw_start_8168f_1(tp);
6391                 break;
6392
6393         case RTL_GIGA_MAC_VER_38:
6394                 rtl_hw_start_8411(tp);
6395                 break;
6396
6397         case RTL_GIGA_MAC_VER_40:
6398         case RTL_GIGA_MAC_VER_41:
6399                 rtl_hw_start_8168g_1(tp);
6400                 break;
6401         case RTL_GIGA_MAC_VER_42:
6402                 rtl_hw_start_8168g_2(tp);
6403                 break;
6404
6405         case RTL_GIGA_MAC_VER_44:
6406                 rtl_hw_start_8411_2(tp);
6407                 break;
6408
6409         case RTL_GIGA_MAC_VER_45:
6410         case RTL_GIGA_MAC_VER_46:
6411                 rtl_hw_start_8168h_1(tp);
6412                 break;
6413
6414         case RTL_GIGA_MAC_VER_49:
6415                 rtl_hw_start_8168ep_1(tp);
6416                 break;
6417
6418         case RTL_GIGA_MAC_VER_50:
6419                 rtl_hw_start_8168ep_2(tp);
6420                 break;
6421
6422         case RTL_GIGA_MAC_VER_51:
6423                 rtl_hw_start_8168ep_3(tp);
6424                 break;
6425
6426         default:
6427                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6428                         dev->name, tp->mac_version);
6429                 break;
6430         }
6431
6432         RTL_W8(Cfg9346, Cfg9346_Lock);
6433
6434         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6435
6436         rtl_set_rx_mode(dev);
6437
6438         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6439 }
6440
6441 #define R810X_CPCMD_QUIRK_MASK (\
6442         EnableBist | \
6443         Mac_dbgo_oe | \
6444         Force_half_dup | \
6445         Force_rxflow_en | \
6446         Force_txflow_en | \
6447         Cxpl_dbg_sel | \
6448         ASF | \
6449         PktCntrDisable | \
6450         Mac_dbgo_sel)
6451
6452 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6453 {
6454         void __iomem *ioaddr = tp->mmio_addr;
6455         struct pci_dev *pdev = tp->pci_dev;
6456         static const struct ephy_info e_info_8102e_1[] = {
6457                 { 0x01, 0, 0x6e65 },
6458                 { 0x02, 0, 0x091f },
6459                 { 0x03, 0, 0xc2f9 },
6460                 { 0x06, 0, 0xafb5 },
6461                 { 0x07, 0, 0x0e00 },
6462                 { 0x19, 0, 0xec80 },
6463                 { 0x01, 0, 0x2e65 },
6464                 { 0x01, 0, 0x6e65 }
6465         };
6466         u8 cfg1;
6467
6468         rtl_csi_access_enable_2(tp);
6469
6470         RTL_W8(DBG_REG, FIX_NAK_1);
6471
6472         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6473
6474         RTL_W8(Config1,
6475                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6476         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6477
6478         cfg1 = RTL_R8(Config1);
6479         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6480                 RTL_W8(Config1, cfg1 & ~LEDS0);
6481
6482         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6483 }
6484
6485 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6486 {
6487         void __iomem *ioaddr = tp->mmio_addr;
6488         struct pci_dev *pdev = tp->pci_dev;
6489
6490         rtl_csi_access_enable_2(tp);
6491
6492         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6493
6494         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6495         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6496 }
6497
6498 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6499 {
6500         rtl_hw_start_8102e_2(tp);
6501
6502         rtl_ephy_write(tp, 0x03, 0xc2f9);
6503 }
6504
6505 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6506 {
6507         void __iomem *ioaddr = tp->mmio_addr;
6508         static const struct ephy_info e_info_8105e_1[] = {
6509                 { 0x07, 0, 0x4000 },
6510                 { 0x19, 0, 0x0200 },
6511                 { 0x19, 0, 0x0020 },
6512                 { 0x1e, 0, 0x2000 },
6513                 { 0x03, 0, 0x0001 },
6514                 { 0x19, 0, 0x0100 },
6515                 { 0x19, 0, 0x0004 },
6516                 { 0x0a, 0, 0x0020 }
6517         };
6518
6519         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6520         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6521
6522         /* Disable Early Tally Counter */
6523         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6524
6525         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6526         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6527
6528         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6529
6530         rtl_pcie_state_l2l3_enable(tp, false);
6531 }
6532
6533 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6534 {
6535         rtl_hw_start_8105e_1(tp);
6536         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6537 }
6538
6539 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6540 {
6541         void __iomem *ioaddr = tp->mmio_addr;
6542         static const struct ephy_info e_info_8402[] = {
6543                 { 0x19, 0xffff, 0xff64 },
6544                 { 0x1e, 0, 0x4000 }
6545         };
6546
6547         rtl_csi_access_enable_2(tp);
6548
6549         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6550         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6551
6552         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6553         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6554
6555         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6556
6557         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6558
6559         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6560         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6561         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6562         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6563         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6564         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6565         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6566
6567         rtl_pcie_state_l2l3_enable(tp, false);
6568 }
6569
6570 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6571 {
6572         void __iomem *ioaddr = tp->mmio_addr;
6573
6574         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6575         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6576
6577         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6578         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6579         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6580
6581         rtl_pcie_state_l2l3_enable(tp, false);
6582 }
6583
6584 static void rtl_hw_start_8101(struct net_device *dev)
6585 {
6586         struct rtl8169_private *tp = netdev_priv(dev);
6587         void __iomem *ioaddr = tp->mmio_addr;
6588         struct pci_dev *pdev = tp->pci_dev;
6589
6590         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6591                 tp->event_slow &= ~RxFIFOOver;
6592
6593         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6594             tp->mac_version == RTL_GIGA_MAC_VER_16)
6595                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6596                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6597
6598         RTL_W8(Cfg9346, Cfg9346_Unlock);
6599
6600         RTL_W8(MaxTxPacketSize, TxPacketMax);
6601
6602         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6603
6604         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6605         RTL_W16(CPlusCmd, tp->cp_cmd);
6606
6607         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6608
6609         rtl_set_rx_tx_config_registers(tp);
6610
6611         switch (tp->mac_version) {
6612         case RTL_GIGA_MAC_VER_07:
6613                 rtl_hw_start_8102e_1(tp);
6614                 break;
6615
6616         case RTL_GIGA_MAC_VER_08:
6617                 rtl_hw_start_8102e_3(tp);
6618                 break;
6619
6620         case RTL_GIGA_MAC_VER_09:
6621                 rtl_hw_start_8102e_2(tp);
6622                 break;
6623
6624         case RTL_GIGA_MAC_VER_29:
6625                 rtl_hw_start_8105e_1(tp);
6626                 break;
6627         case RTL_GIGA_MAC_VER_30:
6628                 rtl_hw_start_8105e_2(tp);
6629                 break;
6630
6631         case RTL_GIGA_MAC_VER_37:
6632                 rtl_hw_start_8402(tp);
6633                 break;
6634
6635         case RTL_GIGA_MAC_VER_39:
6636                 rtl_hw_start_8106(tp);
6637                 break;
6638         case RTL_GIGA_MAC_VER_43:
6639                 rtl_hw_start_8168g_2(tp);
6640                 break;
6641         case RTL_GIGA_MAC_VER_47:
6642         case RTL_GIGA_MAC_VER_48:
6643                 rtl_hw_start_8168h_1(tp);
6644                 break;
6645         }
6646
6647         RTL_W8(Cfg9346, Cfg9346_Lock);
6648
6649         RTL_W16(IntrMitigate, 0x0000);
6650
6651         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6652
6653         rtl_set_rx_mode(dev);
6654
6655         RTL_R8(IntrMask);
6656
6657         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6658 }
6659
6660 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6661 {
6662         struct rtl8169_private *tp = netdev_priv(dev);
6663
6664         if (new_mtu < ETH_ZLEN ||
6665             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6666                 return -EINVAL;
6667
6668         if (new_mtu > ETH_DATA_LEN)
6669                 rtl_hw_jumbo_enable(tp);
6670         else
6671                 rtl_hw_jumbo_disable(tp);
6672
6673         dev->mtu = new_mtu;
6674         netdev_update_features(dev);
6675
6676         return 0;
6677 }
6678
6679 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6680 {
6681         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6682         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6683 }
6684
6685 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6686                                      void **data_buff, struct RxDesc *desc)
6687 {
6688         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6689                          DMA_FROM_DEVICE);
6690
6691         kfree(*data_buff);
6692         *data_buff = NULL;
6693         rtl8169_make_unusable_by_asic(desc);
6694 }
6695
6696 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6697 {
6698         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6699
6700         /* Force memory writes to complete before releasing descriptor */
6701         dma_wmb();
6702
6703         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6704 }
6705
6706 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6707                                        u32 rx_buf_sz)
6708 {
6709         desc->addr = cpu_to_le64(mapping);
6710         rtl8169_mark_to_asic(desc, rx_buf_sz);
6711 }
6712
6713 static inline void *rtl8169_align(void *data)
6714 {
6715         return (void *)ALIGN((long)data, 16);
6716 }
6717
6718 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6719                                              struct RxDesc *desc)
6720 {
6721         void *data;
6722         dma_addr_t mapping;
6723         struct device *d = &tp->pci_dev->dev;
6724         struct net_device *dev = tp->dev;
6725         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6726
6727         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6728         if (!data)
6729                 return NULL;
6730
6731         if (rtl8169_align(data) != data) {
6732                 kfree(data);
6733                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6734                 if (!data)
6735                         return NULL;
6736         }
6737
6738         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6739                                  DMA_FROM_DEVICE);
6740         if (unlikely(dma_mapping_error(d, mapping))) {
6741                 if (net_ratelimit())
6742                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6743                 goto err_out;
6744         }
6745
6746         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6747         return data;
6748
6749 err_out:
6750         kfree(data);
6751         return NULL;
6752 }
6753
6754 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6755 {
6756         unsigned int i;
6757
6758         for (i = 0; i < NUM_RX_DESC; i++) {
6759                 if (tp->Rx_databuff[i]) {
6760                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6761                                             tp->RxDescArray + i);
6762                 }
6763         }
6764 }
6765
6766 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6767 {
6768         desc->opts1 |= cpu_to_le32(RingEnd);
6769 }
6770
6771 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6772 {
6773         unsigned int i;
6774
6775         for (i = 0; i < NUM_RX_DESC; i++) {
6776                 void *data;
6777
6778                 if (tp->Rx_databuff[i])
6779                         continue;
6780
6781                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6782                 if (!data) {
6783                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6784                         goto err_out;
6785                 }
6786                 tp->Rx_databuff[i] = data;
6787         }
6788
6789         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6790         return 0;
6791
6792 err_out:
6793         rtl8169_rx_clear(tp);
6794         return -ENOMEM;
6795 }
6796
6797 static int rtl8169_init_ring(struct net_device *dev)
6798 {
6799         struct rtl8169_private *tp = netdev_priv(dev);
6800
6801         rtl8169_init_ring_indexes(tp);
6802
6803         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6804         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6805
6806         return rtl8169_rx_fill(tp);
6807 }
6808
6809 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6810                                  struct TxDesc *desc)
6811 {
6812         unsigned int len = tx_skb->len;
6813
6814         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6815
6816         desc->opts1 = 0x00;
6817         desc->opts2 = 0x00;
6818         desc->addr = 0x00;
6819         tx_skb->len = 0;
6820 }
6821
6822 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6823                                    unsigned int n)
6824 {
6825         unsigned int i;
6826
6827         for (i = 0; i < n; i++) {
6828                 unsigned int entry = (start + i) % NUM_TX_DESC;
6829                 struct ring_info *tx_skb = tp->tx_skb + entry;
6830                 unsigned int len = tx_skb->len;
6831
6832                 if (len) {
6833                         struct sk_buff *skb = tx_skb->skb;
6834
6835                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6836                                              tp->TxDescArray + entry);
6837                         if (skb) {
6838                                 tp->dev->stats.tx_dropped++;
6839                                 dev_kfree_skb_any(skb);
6840                                 tx_skb->skb = NULL;
6841                         }
6842                 }
6843         }
6844 }
6845
6846 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6847 {
6848         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6849         tp->cur_tx = tp->dirty_tx = 0;
6850 }
6851
6852 static void rtl_reset_work(struct rtl8169_private *tp)
6853 {
6854         struct net_device *dev = tp->dev;
6855         int i;
6856
6857         napi_disable(&tp->napi);
6858         netif_stop_queue(dev);
6859         synchronize_sched();
6860
6861         rtl8169_hw_reset(tp);
6862
6863         for (i = 0; i < NUM_RX_DESC; i++)
6864                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6865
6866         rtl8169_tx_clear(tp);
6867         rtl8169_init_ring_indexes(tp);
6868
6869         napi_enable(&tp->napi);
6870         rtl_hw_start(dev);
6871         netif_wake_queue(dev);
6872         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6873 }
6874
6875 static void rtl8169_tx_timeout(struct net_device *dev)
6876 {
6877         struct rtl8169_private *tp = netdev_priv(dev);
6878
6879         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6880 }
6881
6882 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6883                               u32 *opts)
6884 {
6885         struct skb_shared_info *info = skb_shinfo(skb);
6886         unsigned int cur_frag, entry;
6887         struct TxDesc *uninitialized_var(txd);
6888         struct device *d = &tp->pci_dev->dev;
6889
6890         entry = tp->cur_tx;
6891         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6892                 const skb_frag_t *frag = info->frags + cur_frag;
6893                 dma_addr_t mapping;
6894                 u32 status, len;
6895                 void *addr;
6896
6897                 entry = (entry + 1) % NUM_TX_DESC;
6898
6899                 txd = tp->TxDescArray + entry;
6900                 len = skb_frag_size(frag);
6901                 addr = skb_frag_address(frag);
6902                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6903                 if (unlikely(dma_mapping_error(d, mapping))) {
6904                         if (net_ratelimit())
6905                                 netif_err(tp, drv, tp->dev,
6906                                           "Failed to map TX fragments DMA!\n");
6907                         goto err_out;
6908                 }
6909
6910                 /* Anti gcc 2.95.3 bugware (sic) */
6911                 status = opts[0] | len |
6912                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6913
6914                 txd->opts1 = cpu_to_le32(status);
6915                 txd->opts2 = cpu_to_le32(opts[1]);
6916                 txd->addr = cpu_to_le64(mapping);
6917
6918                 tp->tx_skb[entry].len = len;
6919         }
6920
6921         if (cur_frag) {
6922                 tp->tx_skb[entry].skb = skb;
6923                 txd->opts1 |= cpu_to_le32(LastFrag);
6924         }
6925
6926         return cur_frag;
6927
6928 err_out:
6929         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6930         return -EIO;
6931 }
6932
6933 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6934 {
6935         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6936 }
6937
6938 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6939                                       struct net_device *dev);
6940 /* r8169_csum_workaround()
6941  * The hw limites the value the transport offset. When the offset is out of the
6942  * range, calculate the checksum by sw.
6943  */
6944 static void r8169_csum_workaround(struct rtl8169_private *tp,
6945                                   struct sk_buff *skb)
6946 {
6947         if (skb_shinfo(skb)->gso_size) {
6948                 netdev_features_t features = tp->dev->features;
6949                 struct sk_buff *segs, *nskb;
6950
6951                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6952                 segs = skb_gso_segment(skb, features);
6953                 if (IS_ERR(segs) || !segs)
6954                         goto drop;
6955
6956                 do {
6957                         nskb = segs;
6958                         segs = segs->next;
6959                         nskb->next = NULL;
6960                         rtl8169_start_xmit(nskb, tp->dev);
6961                 } while (segs);
6962
6963                 dev_consume_skb_any(skb);
6964         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6965                 if (skb_checksum_help(skb) < 0)
6966                         goto drop;
6967
6968                 rtl8169_start_xmit(skb, tp->dev);
6969         } else {
6970                 struct net_device_stats *stats;
6971
6972 drop:
6973                 stats = &tp->dev->stats;
6974                 stats->tx_dropped++;
6975                 dev_kfree_skb_any(skb);
6976         }
6977 }
6978
6979 /* msdn_giant_send_check()
6980  * According to the document of microsoft, the TCP Pseudo Header excludes the
6981  * packet length for IPv6 TCP large packets.
6982  */
6983 static int msdn_giant_send_check(struct sk_buff *skb)
6984 {
6985         const struct ipv6hdr *ipv6h;
6986         struct tcphdr *th;
6987         int ret;
6988
6989         ret = skb_cow_head(skb, 0);
6990         if (ret)
6991                 return ret;
6992
6993         ipv6h = ipv6_hdr(skb);
6994         th = tcp_hdr(skb);
6995
6996         th->check = 0;
6997         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6998
6999         return ret;
7000 }
7001
7002 static inline __be16 get_protocol(struct sk_buff *skb)
7003 {
7004         __be16 protocol;
7005
7006         if (skb->protocol == htons(ETH_P_8021Q))
7007                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7008         else
7009                 protocol = skb->protocol;
7010
7011         return protocol;
7012 }
7013
7014 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7015                                 struct sk_buff *skb, u32 *opts)
7016 {
7017         u32 mss = skb_shinfo(skb)->gso_size;
7018
7019         if (mss) {
7020                 opts[0] |= TD_LSO;
7021                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7022         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7023                 const struct iphdr *ip = ip_hdr(skb);
7024
7025                 if (ip->protocol == IPPROTO_TCP)
7026                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7027                 else if (ip->protocol == IPPROTO_UDP)
7028                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7029                 else
7030                         WARN_ON_ONCE(1);
7031         }
7032
7033         return true;
7034 }
7035
7036 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7037                                 struct sk_buff *skb, u32 *opts)
7038 {
7039         u32 transport_offset = (u32)skb_transport_offset(skb);
7040         u32 mss = skb_shinfo(skb)->gso_size;
7041
7042         if (mss) {
7043                 if (transport_offset > GTTCPHO_MAX) {
7044                         netif_warn(tp, tx_err, tp->dev,
7045                                    "Invalid transport offset 0x%x for TSO\n",
7046                                    transport_offset);
7047                         return false;
7048                 }
7049
7050                 switch (get_protocol(skb)) {
7051                 case htons(ETH_P_IP):
7052                         opts[0] |= TD1_GTSENV4;
7053                         break;
7054
7055                 case htons(ETH_P_IPV6):
7056                         if (msdn_giant_send_check(skb))
7057                                 return false;
7058
7059                         opts[0] |= TD1_GTSENV6;
7060                         break;
7061
7062                 default:
7063                         WARN_ON_ONCE(1);
7064                         break;
7065                 }
7066
7067                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7068                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7069         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7070                 u8 ip_protocol;
7071
7072                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7073                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7074
7075                 if (transport_offset > TCPHO_MAX) {
7076                         netif_warn(tp, tx_err, tp->dev,
7077                                    "Invalid transport offset 0x%x\n",
7078                                    transport_offset);
7079                         return false;
7080                 }
7081
7082                 switch (get_protocol(skb)) {
7083                 case htons(ETH_P_IP):
7084                         opts[1] |= TD1_IPv4_CS;
7085                         ip_protocol = ip_hdr(skb)->protocol;
7086                         break;
7087
7088                 case htons(ETH_P_IPV6):
7089                         opts[1] |= TD1_IPv6_CS;
7090                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7091                         break;
7092
7093                 default:
7094                         ip_protocol = IPPROTO_RAW;
7095                         break;
7096                 }
7097
7098                 if (ip_protocol == IPPROTO_TCP)
7099                         opts[1] |= TD1_TCP_CS;
7100                 else if (ip_protocol == IPPROTO_UDP)
7101                         opts[1] |= TD1_UDP_CS;
7102                 else
7103                         WARN_ON_ONCE(1);
7104
7105                 opts[1] |= transport_offset << TCPHO_SHIFT;
7106         } else {
7107                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7108                         return !eth_skb_pad(skb);
7109         }
7110
7111         return true;
7112 }
7113
7114 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7115                                       struct net_device *dev)
7116 {
7117         struct rtl8169_private *tp = netdev_priv(dev);
7118         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7119         struct TxDesc *txd = tp->TxDescArray + entry;
7120         void __iomem *ioaddr = tp->mmio_addr;
7121         struct device *d = &tp->pci_dev->dev;
7122         dma_addr_t mapping;
7123         u32 status, len;
7124         u32 opts[2];
7125         int frags;
7126
7127         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7128                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7129                 goto err_stop_0;
7130         }
7131
7132         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7133                 goto err_stop_0;
7134
7135         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7136         opts[0] = DescOwn;
7137
7138         if (!tp->tso_csum(tp, skb, opts)) {
7139                 r8169_csum_workaround(tp, skb);
7140                 return NETDEV_TX_OK;
7141         }
7142
7143         len = skb_headlen(skb);
7144         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7145         if (unlikely(dma_mapping_error(d, mapping))) {
7146                 if (net_ratelimit())
7147                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7148                 goto err_dma_0;
7149         }
7150
7151         tp->tx_skb[entry].len = len;
7152         txd->addr = cpu_to_le64(mapping);
7153
7154         frags = rtl8169_xmit_frags(tp, skb, opts);
7155         if (frags < 0)
7156                 goto err_dma_1;
7157         else if (frags)
7158                 opts[0] |= FirstFrag;
7159         else {
7160                 opts[0] |= FirstFrag | LastFrag;
7161                 tp->tx_skb[entry].skb = skb;
7162         }
7163
7164         txd->opts2 = cpu_to_le32(opts[1]);
7165
7166         skb_tx_timestamp(skb);
7167
7168         /* Force memory writes to complete before releasing descriptor */
7169         dma_wmb();
7170
7171         /* Anti gcc 2.95.3 bugware (sic) */
7172         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7173         txd->opts1 = cpu_to_le32(status);
7174
7175         /* Force all memory writes to complete before notifying device */
7176         wmb();
7177
7178         tp->cur_tx += frags + 1;
7179
7180         RTL_W8(TxPoll, NPQ);
7181
7182         mmiowb();
7183
7184         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7185                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7186                  * not miss a ring update when it notices a stopped queue.
7187                  */
7188                 smp_wmb();
7189                 netif_stop_queue(dev);
7190                 /* Sync with rtl_tx:
7191                  * - publish queue status and cur_tx ring index (write barrier)
7192                  * - refresh dirty_tx ring index (read barrier).
7193                  * May the current thread have a pessimistic view of the ring
7194                  * status and forget to wake up queue, a racing rtl_tx thread
7195                  * can't.
7196                  */
7197                 smp_mb();
7198                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7199                         netif_wake_queue(dev);
7200         }
7201
7202         return NETDEV_TX_OK;
7203
7204 err_dma_1:
7205         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7206 err_dma_0:
7207         dev_kfree_skb_any(skb);
7208         dev->stats.tx_dropped++;
7209         return NETDEV_TX_OK;
7210
7211 err_stop_0:
7212         netif_stop_queue(dev);
7213         dev->stats.tx_dropped++;
7214         return NETDEV_TX_BUSY;
7215 }
7216
7217 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7218 {
7219         struct rtl8169_private *tp = netdev_priv(dev);
7220         struct pci_dev *pdev = tp->pci_dev;
7221         u16 pci_status, pci_cmd;
7222
7223         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7224         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7225
7226         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7227                   pci_cmd, pci_status);
7228
7229         /*
7230          * The recovery sequence below admits a very elaborated explanation:
7231          * - it seems to work;
7232          * - I did not see what else could be done;
7233          * - it makes iop3xx happy.
7234          *
7235          * Feel free to adjust to your needs.
7236          */
7237         if (pdev->broken_parity_status)
7238                 pci_cmd &= ~PCI_COMMAND_PARITY;
7239         else
7240                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7241
7242         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7243
7244         pci_write_config_word(pdev, PCI_STATUS,
7245                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7246                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7247                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7248
7249         /* The infamous DAC f*ckup only happens at boot time */
7250         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7251                 void __iomem *ioaddr = tp->mmio_addr;
7252
7253                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7254                 tp->cp_cmd &= ~PCIDAC;
7255                 RTL_W16(CPlusCmd, tp->cp_cmd);
7256                 dev->features &= ~NETIF_F_HIGHDMA;
7257         }
7258
7259         rtl8169_hw_reset(tp);
7260
7261         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7262 }
7263
7264 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7265 {
7266         unsigned int dirty_tx, tx_left;
7267
7268         dirty_tx = tp->dirty_tx;
7269         smp_rmb();
7270         tx_left = tp->cur_tx - dirty_tx;
7271
7272         while (tx_left > 0) {
7273                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7274                 struct ring_info *tx_skb = tp->tx_skb + entry;
7275                 u32 status;
7276
7277                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7278                 if (status & DescOwn)
7279                         break;
7280
7281                 /* This barrier is needed to keep us from reading
7282                  * any other fields out of the Tx descriptor until
7283                  * we know the status of DescOwn
7284                  */
7285                 dma_rmb();
7286
7287                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7288                                      tp->TxDescArray + entry);
7289                 if (status & LastFrag) {
7290                         u64_stats_update_begin(&tp->tx_stats.syncp);
7291                         tp->tx_stats.packets++;
7292                         tp->tx_stats.bytes += tx_skb->skb->len;
7293                         u64_stats_update_end(&tp->tx_stats.syncp);
7294                         dev_kfree_skb_any(tx_skb->skb);
7295                         tx_skb->skb = NULL;
7296                 }
7297                 dirty_tx++;
7298                 tx_left--;
7299         }
7300
7301         if (tp->dirty_tx != dirty_tx) {
7302                 tp->dirty_tx = dirty_tx;
7303                 /* Sync with rtl8169_start_xmit:
7304                  * - publish dirty_tx ring index (write barrier)
7305                  * - refresh cur_tx ring index and queue status (read barrier)
7306                  * May the current thread miss the stopped queue condition,
7307                  * a racing xmit thread can only have a right view of the
7308                  * ring status.
7309                  */
7310                 smp_mb();
7311                 if (netif_queue_stopped(dev) &&
7312                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7313                         netif_wake_queue(dev);
7314                 }
7315                 /*
7316                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7317                  * too close. Let's kick an extra TxPoll request when a burst
7318                  * of start_xmit activity is detected (if it is not detected,
7319                  * it is slow enough). -- FR
7320                  */
7321                 if (tp->cur_tx != dirty_tx) {
7322                         void __iomem *ioaddr = tp->mmio_addr;
7323
7324                         RTL_W8(TxPoll, NPQ);
7325                 }
7326         }
7327 }
7328
7329 static inline int rtl8169_fragmented_frame(u32 status)
7330 {
7331         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7332 }
7333
7334 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7335 {
7336         u32 status = opts1 & RxProtoMask;
7337
7338         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7339             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7340                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7341         else
7342                 skb_checksum_none_assert(skb);
7343 }
7344
7345 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7346                                            struct rtl8169_private *tp,
7347                                            int pkt_size,
7348                                            dma_addr_t addr)
7349 {
7350         struct sk_buff *skb;
7351         struct device *d = &tp->pci_dev->dev;
7352
7353         data = rtl8169_align(data);
7354         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7355         prefetch(data);
7356         skb = napi_alloc_skb(&tp->napi, pkt_size);
7357         if (skb)
7358                 memcpy(skb->data, data, pkt_size);
7359         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7360
7361         return skb;
7362 }
7363
7364 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7365 {
7366         unsigned int cur_rx, rx_left;
7367         unsigned int count;
7368
7369         cur_rx = tp->cur_rx;
7370
7371         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7372                 unsigned int entry = cur_rx % NUM_RX_DESC;
7373                 struct RxDesc *desc = tp->RxDescArray + entry;
7374                 u32 status;
7375
7376                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7377                 if (status & DescOwn)
7378                         break;
7379
7380                 /* This barrier is needed to keep us from reading
7381                  * any other fields out of the Rx descriptor until
7382                  * we know the status of DescOwn
7383                  */
7384                 dma_rmb();
7385
7386                 if (unlikely(status & RxRES)) {
7387                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7388                                    status);
7389                         dev->stats.rx_errors++;
7390                         if (status & (RxRWT | RxRUNT))
7391                                 dev->stats.rx_length_errors++;
7392                         if (status & RxCRC)
7393                                 dev->stats.rx_crc_errors++;
7394                         if (status & RxFOVF) {
7395                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7396                                 dev->stats.rx_fifo_errors++;
7397                         }
7398                         if ((status & (RxRUNT | RxCRC)) &&
7399                             !(status & (RxRWT | RxFOVF)) &&
7400                             (dev->features & NETIF_F_RXALL))
7401                                 goto process_pkt;
7402                 } else {
7403                         struct sk_buff *skb;
7404                         dma_addr_t addr;
7405                         int pkt_size;
7406
7407 process_pkt:
7408                         addr = le64_to_cpu(desc->addr);
7409                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7410                                 pkt_size = (status & 0x00003fff) - 4;
7411                         else
7412                                 pkt_size = status & 0x00003fff;
7413
7414                         /*
7415                          * The driver does not support incoming fragmented
7416                          * frames. They are seen as a symptom of over-mtu
7417                          * sized frames.
7418                          */
7419                         if (unlikely(rtl8169_fragmented_frame(status))) {
7420                                 dev->stats.rx_dropped++;
7421                                 dev->stats.rx_length_errors++;
7422                                 goto release_descriptor;
7423                         }
7424
7425                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7426                                                   tp, pkt_size, addr);
7427                         if (!skb) {
7428                                 dev->stats.rx_dropped++;
7429                                 goto release_descriptor;
7430                         }
7431
7432                         rtl8169_rx_csum(skb, status);
7433                         skb_put(skb, pkt_size);
7434                         skb->protocol = eth_type_trans(skb, dev);
7435
7436                         rtl8169_rx_vlan_tag(desc, skb);
7437
7438                         if (skb->pkt_type == PACKET_MULTICAST)
7439                                 dev->stats.multicast++;
7440
7441                         napi_gro_receive(&tp->napi, skb);
7442
7443                         u64_stats_update_begin(&tp->rx_stats.syncp);
7444                         tp->rx_stats.packets++;
7445                         tp->rx_stats.bytes += pkt_size;
7446                         u64_stats_update_end(&tp->rx_stats.syncp);
7447                 }
7448 release_descriptor:
7449                 desc->opts2 = 0;
7450                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7451         }
7452
7453         count = cur_rx - tp->cur_rx;
7454         tp->cur_rx = cur_rx;
7455
7456         return count;
7457 }
7458
7459 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7460 {
7461         struct net_device *dev = dev_instance;
7462         struct rtl8169_private *tp = netdev_priv(dev);
7463         int handled = 0;
7464         u16 status;
7465
7466         status = rtl_get_events(tp);
7467         if (status && status != 0xffff) {
7468                 status &= RTL_EVENT_NAPI | tp->event_slow;
7469                 if (status) {
7470                         handled = 1;
7471
7472                         rtl_irq_disable(tp);
7473                         napi_schedule(&tp->napi);
7474                 }
7475         }
7476         return IRQ_RETVAL(handled);
7477 }
7478
7479 /*
7480  * Workqueue context.
7481  */
7482 static void rtl_slow_event_work(struct rtl8169_private *tp)
7483 {
7484         struct net_device *dev = tp->dev;
7485         u16 status;
7486
7487         status = rtl_get_events(tp) & tp->event_slow;
7488         rtl_ack_events(tp, status);
7489
7490         if (unlikely(status & RxFIFOOver)) {
7491                 switch (tp->mac_version) {
7492                 /* Work around for rx fifo overflow */
7493                 case RTL_GIGA_MAC_VER_11:
7494                         netif_stop_queue(dev);
7495                         /* XXX - Hack alert. See rtl_task(). */
7496                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7497                 default:
7498                         break;
7499                 }
7500         }
7501
7502         if (unlikely(status & SYSErr))
7503                 rtl8169_pcierr_interrupt(dev);
7504
7505         if (status & LinkChg)
7506                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7507
7508         rtl_irq_enable_all(tp);
7509 }
7510
7511 static void rtl_task(struct work_struct *work)
7512 {
7513         static const struct {
7514                 int bitnr;
7515                 void (*action)(struct rtl8169_private *);
7516         } rtl_work[] = {
7517                 /* XXX - keep rtl_slow_event_work() as first element. */
7518                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7519                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7520                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7521         };
7522         struct rtl8169_private *tp =
7523                 container_of(work, struct rtl8169_private, wk.work);
7524         struct net_device *dev = tp->dev;
7525         int i;
7526
7527         rtl_lock_work(tp);
7528
7529         if (!netif_running(dev) ||
7530             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7531                 goto out_unlock;
7532
7533         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7534                 bool pending;
7535
7536                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7537                 if (pending)
7538                         rtl_work[i].action(tp);
7539         }
7540
7541 out_unlock:
7542         rtl_unlock_work(tp);
7543 }
7544
7545 static int rtl8169_poll(struct napi_struct *napi, int budget)
7546 {
7547         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7548         struct net_device *dev = tp->dev;
7549         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7550         int work_done;
7551         u16 status;
7552
7553         status = rtl_get_events(tp);
7554         rtl_ack_events(tp, status & ~tp->event_slow);
7555
7556         work_done = rtl_rx(dev, tp, (u32) budget);
7557
7558         rtl_tx(dev, tp);
7559
7560         if (status & tp->event_slow) {
7561                 enable_mask &= ~tp->event_slow;
7562
7563                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7564         }
7565
7566         if (work_done < budget) {
7567                 napi_complete(napi);
7568
7569                 rtl_irq_enable(tp, enable_mask);
7570                 mmiowb();
7571         }
7572
7573         return work_done;
7574 }
7575
7576 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7577 {
7578         struct rtl8169_private *tp = netdev_priv(dev);
7579
7580         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7581                 return;
7582
7583         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7584         RTL_W32(RxMissed, 0);
7585 }
7586
7587 static void rtl8169_down(struct net_device *dev)
7588 {
7589         struct rtl8169_private *tp = netdev_priv(dev);
7590         void __iomem *ioaddr = tp->mmio_addr;
7591
7592         del_timer_sync(&tp->timer);
7593
7594         napi_disable(&tp->napi);
7595         netif_stop_queue(dev);
7596
7597         rtl8169_hw_reset(tp);
7598         /*
7599          * At this point device interrupts can not be enabled in any function,
7600          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7601          * and napi is disabled (rtl8169_poll).
7602          */
7603         rtl8169_rx_missed(dev, ioaddr);
7604
7605         /* Give a racing hard_start_xmit a few cycles to complete. */
7606         synchronize_sched();
7607
7608         rtl8169_tx_clear(tp);
7609
7610         rtl8169_rx_clear(tp);
7611
7612         rtl_pll_power_down(tp);
7613 }
7614
7615 static int rtl8169_close(struct net_device *dev)
7616 {
7617         struct rtl8169_private *tp = netdev_priv(dev);
7618         struct pci_dev *pdev = tp->pci_dev;
7619
7620         pm_runtime_get_sync(&pdev->dev);
7621
7622         /* Update counters before going down */
7623         rtl8169_update_counters(dev);
7624
7625         rtl_lock_work(tp);
7626         /* Clear all task flags */
7627         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7628
7629         rtl8169_down(dev);
7630         rtl_unlock_work(tp);
7631
7632         cancel_work_sync(&tp->wk.work);
7633
7634         free_irq(pdev->irq, dev);
7635
7636         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7637                           tp->RxPhyAddr);
7638         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7639                           tp->TxPhyAddr);
7640         tp->TxDescArray = NULL;
7641         tp->RxDescArray = NULL;
7642
7643         pm_runtime_put_sync(&pdev->dev);
7644
7645         return 0;
7646 }
7647
7648 #ifdef CONFIG_NET_POLL_CONTROLLER
7649 static void rtl8169_netpoll(struct net_device *dev)
7650 {
7651         struct rtl8169_private *tp = netdev_priv(dev);
7652
7653         rtl8169_interrupt(tp->pci_dev->irq, dev);
7654 }
7655 #endif
7656
7657 static int rtl_open(struct net_device *dev)
7658 {
7659         struct rtl8169_private *tp = netdev_priv(dev);
7660         void __iomem *ioaddr = tp->mmio_addr;
7661         struct pci_dev *pdev = tp->pci_dev;
7662         int retval = -ENOMEM;
7663
7664         pm_runtime_get_sync(&pdev->dev);
7665
7666         /*
7667          * Rx and Tx descriptors needs 256 bytes alignment.
7668          * dma_alloc_coherent provides more.
7669          */
7670         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7671                                              &tp->TxPhyAddr, GFP_KERNEL);
7672         if (!tp->TxDescArray)
7673                 goto err_pm_runtime_put;
7674
7675         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7676                                              &tp->RxPhyAddr, GFP_KERNEL);
7677         if (!tp->RxDescArray)
7678                 goto err_free_tx_0;
7679
7680         retval = rtl8169_init_ring(dev);
7681         if (retval < 0)
7682                 goto err_free_rx_1;
7683
7684         INIT_WORK(&tp->wk.work, rtl_task);
7685
7686         smp_mb();
7687
7688         rtl_request_firmware(tp);
7689
7690         retval = request_irq(pdev->irq, rtl8169_interrupt,
7691                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7692                              dev->name, dev);
7693         if (retval < 0)
7694                 goto err_release_fw_2;
7695
7696         rtl_lock_work(tp);
7697
7698         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7699
7700         napi_enable(&tp->napi);
7701
7702         rtl8169_init_phy(dev, tp);
7703
7704         __rtl8169_set_features(dev, dev->features);
7705
7706         rtl_pll_power_up(tp);
7707
7708         rtl_hw_start(dev);
7709
7710         if (!rtl8169_init_counter_offsets(dev))
7711                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7712
7713         netif_start_queue(dev);
7714
7715         rtl_unlock_work(tp);
7716
7717         tp->saved_wolopts = 0;
7718         pm_runtime_put_noidle(&pdev->dev);
7719
7720         rtl8169_check_link_status(dev, tp, ioaddr);
7721 out:
7722         return retval;
7723
7724 err_release_fw_2:
7725         rtl_release_firmware(tp);
7726         rtl8169_rx_clear(tp);
7727 err_free_rx_1:
7728         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7729                           tp->RxPhyAddr);
7730         tp->RxDescArray = NULL;
7731 err_free_tx_0:
7732         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7733                           tp->TxPhyAddr);
7734         tp->TxDescArray = NULL;
7735 err_pm_runtime_put:
7736         pm_runtime_put_noidle(&pdev->dev);
7737         goto out;
7738 }
7739
7740 static struct rtnl_link_stats64 *
7741 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7742 {
7743         struct rtl8169_private *tp = netdev_priv(dev);
7744         void __iomem *ioaddr = tp->mmio_addr;
7745         struct pci_dev *pdev = tp->pci_dev;
7746         struct rtl8169_counters *counters = tp->counters;
7747         unsigned int start;
7748
7749         pm_runtime_get_noresume(&pdev->dev);
7750
7751         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7752                 rtl8169_rx_missed(dev, ioaddr);
7753
7754         do {
7755                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7756                 stats->rx_packets = tp->rx_stats.packets;
7757                 stats->rx_bytes = tp->rx_stats.bytes;
7758         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7759
7760         do {
7761                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7762                 stats->tx_packets = tp->tx_stats.packets;
7763                 stats->tx_bytes = tp->tx_stats.bytes;
7764         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7765
7766         stats->rx_dropped       = dev->stats.rx_dropped;
7767         stats->tx_dropped       = dev->stats.tx_dropped;
7768         stats->rx_length_errors = dev->stats.rx_length_errors;
7769         stats->rx_errors        = dev->stats.rx_errors;
7770         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7771         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7772         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7773         stats->multicast        = dev->stats.multicast;
7774
7775         /*
7776          * Fetch additonal counter values missing in stats collected by driver
7777          * from tally counters.
7778          */
7779         if (pm_runtime_active(&pdev->dev))
7780                 rtl8169_update_counters(dev);
7781
7782         /*
7783          * Subtract values fetched during initalization.
7784          * See rtl8169_init_counter_offsets for a description why we do that.
7785          */
7786         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7787                 le64_to_cpu(tp->tc_offset.tx_errors);
7788         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7789                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7790         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7791                 le16_to_cpu(tp->tc_offset.tx_aborted);
7792
7793         pm_runtime_put_noidle(&pdev->dev);
7794
7795         return stats;
7796 }
7797
7798 static void rtl8169_net_suspend(struct net_device *dev)
7799 {
7800         struct rtl8169_private *tp = netdev_priv(dev);
7801
7802         if (!netif_running(dev))
7803                 return;
7804
7805         netif_device_detach(dev);
7806         netif_stop_queue(dev);
7807
7808         rtl_lock_work(tp);
7809         napi_disable(&tp->napi);
7810         /* Clear all task flags */
7811         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7812
7813         rtl_unlock_work(tp);
7814
7815         rtl_pll_power_down(tp);
7816 }
7817
7818 #ifdef CONFIG_PM
7819
7820 static int rtl8169_suspend(struct device *device)
7821 {
7822         struct pci_dev *pdev = to_pci_dev(device);
7823         struct net_device *dev = pci_get_drvdata(pdev);
7824
7825         rtl8169_net_suspend(dev);
7826
7827         return 0;
7828 }
7829
7830 static void __rtl8169_resume(struct net_device *dev)
7831 {
7832         struct rtl8169_private *tp = netdev_priv(dev);
7833
7834         netif_device_attach(dev);
7835
7836         rtl_pll_power_up(tp);
7837
7838         rtl_lock_work(tp);
7839         napi_enable(&tp->napi);
7840         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7841         rtl_unlock_work(tp);
7842
7843         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7844 }
7845
7846 static int rtl8169_resume(struct device *device)
7847 {
7848         struct pci_dev *pdev = to_pci_dev(device);
7849         struct net_device *dev = pci_get_drvdata(pdev);
7850         struct rtl8169_private *tp = netdev_priv(dev);
7851
7852         rtl8169_init_phy(dev, tp);
7853
7854         if (netif_running(dev))
7855                 __rtl8169_resume(dev);
7856
7857         return 0;
7858 }
7859
7860 static int rtl8169_runtime_suspend(struct device *device)
7861 {
7862         struct pci_dev *pdev = to_pci_dev(device);
7863         struct net_device *dev = pci_get_drvdata(pdev);
7864         struct rtl8169_private *tp = netdev_priv(dev);
7865
7866         if (!tp->TxDescArray)
7867                 return 0;
7868
7869         rtl_lock_work(tp);
7870         tp->saved_wolopts = __rtl8169_get_wol(tp);
7871         __rtl8169_set_wol(tp, WAKE_ANY);
7872         rtl_unlock_work(tp);
7873
7874         rtl8169_net_suspend(dev);
7875
7876         /* Update counters before going runtime suspend */
7877         rtl8169_rx_missed(dev, tp->mmio_addr);
7878         rtl8169_update_counters(dev);
7879
7880         return 0;
7881 }
7882
7883 static int rtl8169_runtime_resume(struct device *device)
7884 {
7885         struct pci_dev *pdev = to_pci_dev(device);
7886         struct net_device *dev = pci_get_drvdata(pdev);
7887         struct rtl8169_private *tp = netdev_priv(dev);
7888         rtl_rar_set(tp, dev->dev_addr);
7889
7890         if (!tp->TxDescArray)
7891                 return 0;
7892
7893         rtl_lock_work(tp);
7894         __rtl8169_set_wol(tp, tp->saved_wolopts);
7895         tp->saved_wolopts = 0;
7896         rtl_unlock_work(tp);
7897
7898         rtl8169_init_phy(dev, tp);
7899
7900         __rtl8169_resume(dev);
7901
7902         return 0;
7903 }
7904
7905 static int rtl8169_runtime_idle(struct device *device)
7906 {
7907         struct pci_dev *pdev = to_pci_dev(device);
7908         struct net_device *dev = pci_get_drvdata(pdev);
7909         struct rtl8169_private *tp = netdev_priv(dev);
7910
7911         return tp->TxDescArray ? -EBUSY : 0;
7912 }
7913
7914 static const struct dev_pm_ops rtl8169_pm_ops = {
7915         .suspend                = rtl8169_suspend,
7916         .resume                 = rtl8169_resume,
7917         .freeze                 = rtl8169_suspend,
7918         .thaw                   = rtl8169_resume,
7919         .poweroff               = rtl8169_suspend,
7920         .restore                = rtl8169_resume,
7921         .runtime_suspend        = rtl8169_runtime_suspend,
7922         .runtime_resume         = rtl8169_runtime_resume,
7923         .runtime_idle           = rtl8169_runtime_idle,
7924 };
7925
7926 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7927
7928 #else /* !CONFIG_PM */
7929
7930 #define RTL8169_PM_OPS  NULL
7931
7932 #endif /* !CONFIG_PM */
7933
7934 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7935 {
7936         void __iomem *ioaddr = tp->mmio_addr;
7937
7938         /* WoL fails with 8168b when the receiver is disabled. */
7939         switch (tp->mac_version) {
7940         case RTL_GIGA_MAC_VER_11:
7941         case RTL_GIGA_MAC_VER_12:
7942         case RTL_GIGA_MAC_VER_17:
7943                 pci_clear_master(tp->pci_dev);
7944
7945                 RTL_W8(ChipCmd, CmdRxEnb);
7946                 /* PCI commit */
7947                 RTL_R8(ChipCmd);
7948                 break;
7949         default:
7950                 break;
7951         }
7952 }
7953
7954 static void rtl_shutdown(struct pci_dev *pdev)
7955 {
7956         struct net_device *dev = pci_get_drvdata(pdev);
7957         struct rtl8169_private *tp = netdev_priv(dev);
7958         struct device *d = &pdev->dev;
7959
7960         pm_runtime_get_sync(d);
7961
7962         rtl8169_net_suspend(dev);
7963
7964         /* Restore original MAC address */
7965         rtl_rar_set(tp, dev->perm_addr);
7966
7967         rtl8169_hw_reset(tp);
7968
7969         if (system_state == SYSTEM_POWER_OFF) {
7970                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7971                         rtl_wol_suspend_quirk(tp);
7972                         rtl_wol_shutdown_quirk(tp);
7973                 }
7974
7975                 pci_wake_from_d3(pdev, true);
7976                 pci_set_power_state(pdev, PCI_D3hot);
7977         }
7978
7979         pm_runtime_put_noidle(d);
7980 }
7981
7982 static void rtl_remove_one(struct pci_dev *pdev)
7983 {
7984         struct net_device *dev = pci_get_drvdata(pdev);
7985         struct rtl8169_private *tp = netdev_priv(dev);
7986
7987         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7988              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7989              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7990              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7991              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7992              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7993             r8168_check_dash(tp)) {
7994                 rtl8168_driver_stop(tp);
7995         }
7996
7997         netif_napi_del(&tp->napi);
7998
7999         unregister_netdev(dev);
8000
8001         dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8002                           tp->counters, tp->counters_phys_addr);
8003
8004         rtl_release_firmware(tp);
8005
8006         if (pci_dev_run_wake(pdev))
8007                 pm_runtime_get_noresume(&pdev->dev);
8008
8009         /* restore original MAC address */
8010         rtl_rar_set(tp, dev->perm_addr);
8011
8012         rtl_disable_msi(pdev, tp);
8013         rtl8169_release_board(pdev, dev, tp->mmio_addr);
8014 }
8015
8016 static const struct net_device_ops rtl_netdev_ops = {
8017         .ndo_open               = rtl_open,
8018         .ndo_stop               = rtl8169_close,
8019         .ndo_get_stats64        = rtl8169_get_stats64,
8020         .ndo_start_xmit         = rtl8169_start_xmit,
8021         .ndo_tx_timeout         = rtl8169_tx_timeout,
8022         .ndo_validate_addr      = eth_validate_addr,
8023         .ndo_change_mtu         = rtl8169_change_mtu,
8024         .ndo_fix_features       = rtl8169_fix_features,
8025         .ndo_set_features       = rtl8169_set_features,
8026         .ndo_set_mac_address    = rtl_set_mac_address,
8027         .ndo_do_ioctl           = rtl8169_ioctl,
8028         .ndo_set_rx_mode        = rtl_set_rx_mode,
8029 #ifdef CONFIG_NET_POLL_CONTROLLER
8030         .ndo_poll_controller    = rtl8169_netpoll,
8031 #endif
8032
8033 };
8034
8035 static const struct rtl_cfg_info {
8036         void (*hw_start)(struct net_device *);
8037         unsigned int region;
8038         unsigned int align;
8039         u16 event_slow;
8040         unsigned features;
8041         u8 default_ver;
8042 } rtl_cfg_infos [] = {
8043         [RTL_CFG_0] = {
8044                 .hw_start       = rtl_hw_start_8169,
8045                 .region         = 1,
8046                 .align          = 0,
8047                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8048                 .features       = RTL_FEATURE_GMII,
8049                 .default_ver    = RTL_GIGA_MAC_VER_01,
8050         },
8051         [RTL_CFG_1] = {
8052                 .hw_start       = rtl_hw_start_8168,
8053                 .region         = 2,
8054                 .align          = 8,
8055                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8056                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8057                 .default_ver    = RTL_GIGA_MAC_VER_11,
8058         },
8059         [RTL_CFG_2] = {
8060                 .hw_start       = rtl_hw_start_8101,
8061                 .region         = 2,
8062                 .align          = 8,
8063                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8064                                   PCSTimeout,
8065                 .features       = RTL_FEATURE_MSI,
8066                 .default_ver    = RTL_GIGA_MAC_VER_13,
8067         }
8068 };
8069
8070 /* Cfg9346_Unlock assumed. */
8071 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8072                             const struct rtl_cfg_info *cfg)
8073 {
8074         void __iomem *ioaddr = tp->mmio_addr;
8075         unsigned msi = 0;
8076         u8 cfg2;
8077
8078         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8079         if (cfg->features & RTL_FEATURE_MSI) {
8080                 if (pci_enable_msi(tp->pci_dev)) {
8081                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8082                 } else {
8083                         cfg2 |= MSIEnable;
8084                         msi = RTL_FEATURE_MSI;
8085                 }
8086         }
8087         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8088                 RTL_W8(Config2, cfg2);
8089         return msi;
8090 }
8091
8092 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8093 {
8094         void __iomem *ioaddr = tp->mmio_addr;
8095
8096         return RTL_R8(MCU) & LINK_LIST_RDY;
8097 }
8098
8099 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8100 {
8101         void __iomem *ioaddr = tp->mmio_addr;
8102
8103         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8104 }
8105
8106 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8107 {
8108         void __iomem *ioaddr = tp->mmio_addr;
8109         u32 data;
8110
8111         tp->ocp_base = OCP_STD_PHY_BASE;
8112
8113         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8114
8115         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8116                 return;
8117
8118         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8119                 return;
8120
8121         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8122         msleep(1);
8123         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8124
8125         data = r8168_mac_ocp_read(tp, 0xe8de);
8126         data &= ~(1 << 14);
8127         r8168_mac_ocp_write(tp, 0xe8de, data);
8128
8129         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8130                 return;
8131
8132         data = r8168_mac_ocp_read(tp, 0xe8de);
8133         data |= (1 << 15);
8134         r8168_mac_ocp_write(tp, 0xe8de, data);
8135
8136         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8137                 return;
8138 }
8139
8140 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8141 {
8142         rtl8168ep_stop_cmac(tp);
8143         rtl_hw_init_8168g(tp);
8144 }
8145
8146 static void rtl_hw_initialize(struct rtl8169_private *tp)
8147 {
8148         switch (tp->mac_version) {
8149         case RTL_GIGA_MAC_VER_40:
8150         case RTL_GIGA_MAC_VER_41:
8151         case RTL_GIGA_MAC_VER_42:
8152         case RTL_GIGA_MAC_VER_43:
8153         case RTL_GIGA_MAC_VER_44:
8154         case RTL_GIGA_MAC_VER_45:
8155         case RTL_GIGA_MAC_VER_46:
8156         case RTL_GIGA_MAC_VER_47:
8157         case RTL_GIGA_MAC_VER_48:
8158                 rtl_hw_init_8168g(tp);
8159                 break;
8160         case RTL_GIGA_MAC_VER_49:
8161         case RTL_GIGA_MAC_VER_50:
8162         case RTL_GIGA_MAC_VER_51:
8163                 rtl_hw_init_8168ep(tp);
8164                 break;
8165         default:
8166                 break;
8167         }
8168 }
8169
8170 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8171 {
8172         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8173         const unsigned int region = cfg->region;
8174         struct rtl8169_private *tp;
8175         struct mii_if_info *mii;
8176         struct net_device *dev;
8177         void __iomem *ioaddr;
8178         int chipset, i;
8179         int rc;
8180
8181         if (netif_msg_drv(&debug)) {
8182                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8183                        MODULENAME, RTL8169_VERSION);
8184         }
8185
8186         dev = alloc_etherdev(sizeof (*tp));
8187         if (!dev) {
8188                 rc = -ENOMEM;
8189                 goto out;
8190         }
8191
8192         SET_NETDEV_DEV(dev, &pdev->dev);
8193         dev->netdev_ops = &rtl_netdev_ops;
8194         tp = netdev_priv(dev);
8195         tp->dev = dev;
8196         tp->pci_dev = pdev;
8197         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8198
8199         mii = &tp->mii;
8200         mii->dev = dev;
8201         mii->mdio_read = rtl_mdio_read;
8202         mii->mdio_write = rtl_mdio_write;
8203         mii->phy_id_mask = 0x1f;
8204         mii->reg_num_mask = 0x1f;
8205         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8206
8207         /* disable ASPM completely as that cause random device stop working
8208          * problems as well as full system hangs for some PCIe devices users */
8209         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8210                                      PCIE_LINK_STATE_CLKPM);
8211
8212         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8213         rc = pci_enable_device(pdev);
8214         if (rc < 0) {
8215                 netif_err(tp, probe, dev, "enable failure\n");
8216                 goto err_out_free_dev_1;
8217         }
8218
8219         if (pci_set_mwi(pdev) < 0)
8220                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8221
8222         /* make sure PCI base addr 1 is MMIO */
8223         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8224                 netif_err(tp, probe, dev,
8225                           "region #%d not an MMIO resource, aborting\n",
8226                           region);
8227                 rc = -ENODEV;
8228                 goto err_out_mwi_2;
8229         }
8230
8231         /* check for weird/broken PCI region reporting */
8232         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8233                 netif_err(tp, probe, dev,
8234                           "Invalid PCI region size(s), aborting\n");
8235                 rc = -ENODEV;
8236                 goto err_out_mwi_2;
8237         }
8238
8239         rc = pci_request_regions(pdev, MODULENAME);
8240         if (rc < 0) {
8241                 netif_err(tp, probe, dev, "could not request regions\n");
8242                 goto err_out_mwi_2;
8243         }
8244
8245         /* ioremap MMIO region */
8246         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8247         if (!ioaddr) {
8248                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8249                 rc = -EIO;
8250                 goto err_out_free_res_3;
8251         }
8252         tp->mmio_addr = ioaddr;
8253
8254         if (!pci_is_pcie(pdev))
8255                 netif_info(tp, probe, dev, "not PCI Express\n");
8256
8257         /* Identify chip attached to board */
8258         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8259
8260         tp->cp_cmd = 0;
8261
8262         if ((sizeof(dma_addr_t) > 4) &&
8263             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8264                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8265             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8266             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8267
8268                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8269                 if (!pci_is_pcie(pdev))
8270                         tp->cp_cmd |= PCIDAC;
8271                 dev->features |= NETIF_F_HIGHDMA;
8272         } else {
8273                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8274                 if (rc < 0) {
8275                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8276                         goto err_out_unmap_4;
8277                 }
8278         }
8279
8280         rtl_init_rxcfg(tp);
8281
8282         rtl_irq_disable(tp);
8283
8284         rtl_hw_initialize(tp);
8285
8286         rtl_hw_reset(tp);
8287
8288         rtl_ack_events(tp, 0xffff);
8289
8290         pci_set_master(pdev);
8291
8292         rtl_init_mdio_ops(tp);
8293         rtl_init_pll_power_ops(tp);
8294         rtl_init_jumbo_ops(tp);
8295         rtl_init_csi_ops(tp);
8296
8297         rtl8169_print_mac_version(tp);
8298
8299         chipset = tp->mac_version;
8300         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8301
8302         RTL_W8(Cfg9346, Cfg9346_Unlock);
8303         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8304         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8305         switch (tp->mac_version) {
8306         case RTL_GIGA_MAC_VER_34:
8307         case RTL_GIGA_MAC_VER_35:
8308         case RTL_GIGA_MAC_VER_36:
8309         case RTL_GIGA_MAC_VER_37:
8310         case RTL_GIGA_MAC_VER_38:
8311         case RTL_GIGA_MAC_VER_40:
8312         case RTL_GIGA_MAC_VER_41:
8313         case RTL_GIGA_MAC_VER_42:
8314         case RTL_GIGA_MAC_VER_43:
8315         case RTL_GIGA_MAC_VER_44:
8316         case RTL_GIGA_MAC_VER_45:
8317         case RTL_GIGA_MAC_VER_46:
8318         case RTL_GIGA_MAC_VER_47:
8319         case RTL_GIGA_MAC_VER_48:
8320         case RTL_GIGA_MAC_VER_49:
8321         case RTL_GIGA_MAC_VER_50:
8322         case RTL_GIGA_MAC_VER_51:
8323                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8324                         tp->features |= RTL_FEATURE_WOL;
8325                 if ((RTL_R8(Config3) & LinkUp) != 0)
8326                         tp->features |= RTL_FEATURE_WOL;
8327                 break;
8328         default:
8329                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8330                         tp->features |= RTL_FEATURE_WOL;
8331                 break;
8332         }
8333         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8334                 tp->features |= RTL_FEATURE_WOL;
8335         tp->features |= rtl_try_msi(tp, cfg);
8336         RTL_W8(Cfg9346, Cfg9346_Lock);
8337
8338         if (rtl_tbi_enabled(tp)) {
8339                 tp->set_speed = rtl8169_set_speed_tbi;
8340                 tp->get_settings = rtl8169_gset_tbi;
8341                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8342                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8343                 tp->link_ok = rtl8169_tbi_link_ok;
8344                 tp->do_ioctl = rtl_tbi_ioctl;
8345         } else {
8346                 tp->set_speed = rtl8169_set_speed_xmii;
8347                 tp->get_settings = rtl8169_gset_xmii;
8348                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8349                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8350                 tp->link_ok = rtl8169_xmii_link_ok;
8351                 tp->do_ioctl = rtl_xmii_ioctl;
8352         }
8353
8354         mutex_init(&tp->wk.mutex);
8355         u64_stats_init(&tp->rx_stats.syncp);
8356         u64_stats_init(&tp->tx_stats.syncp);
8357
8358         /* Get MAC address */
8359         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8360             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8361             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8362             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8363             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8364             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8365             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8366             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8367             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8368             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8369             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8370             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8371             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8372             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8373             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8374             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8375                 u16 mac_addr[3];
8376
8377                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8378                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8379
8380                 if (is_valid_ether_addr((u8 *)mac_addr))
8381                         rtl_rar_set(tp, (u8 *)mac_addr);
8382         }
8383         for (i = 0; i < ETH_ALEN; i++)
8384                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8385
8386         dev->ethtool_ops = &rtl8169_ethtool_ops;
8387         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8388
8389         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8390
8391         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8392          * properly for all devices */
8393         dev->features |= NETIF_F_RXCSUM |
8394                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8395
8396         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8397                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8398                 NETIF_F_HW_VLAN_CTAG_RX;
8399         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8400                 NETIF_F_HIGHDMA;
8401
8402         tp->cp_cmd |= RxChkSum | RxVlan;
8403
8404         /*
8405          * Pretend we are using VLANs; This bypasses a nasty bug where
8406          * Interrupts stop flowing on high load on 8110SCd controllers.
8407          */
8408         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8409                 /* Disallow toggling */
8410                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8411
8412         if (tp->txd_version == RTL_TD_0)
8413                 tp->tso_csum = rtl8169_tso_csum_v1;
8414         else if (tp->txd_version == RTL_TD_1) {
8415                 tp->tso_csum = rtl8169_tso_csum_v2;
8416                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8417         } else
8418                 WARN_ON_ONCE(1);
8419
8420         dev->hw_features |= NETIF_F_RXALL;
8421         dev->hw_features |= NETIF_F_RXFCS;
8422
8423         tp->hw_start = cfg->hw_start;
8424         tp->event_slow = cfg->event_slow;
8425
8426         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8427                 ~(RxBOVF | RxFOVF) : ~0;
8428
8429         init_timer(&tp->timer);
8430         tp->timer.data = (unsigned long) dev;
8431         tp->timer.function = rtl8169_phy_timer;
8432
8433         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8434
8435         tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8436                                            &tp->counters_phys_addr, GFP_KERNEL);
8437         if (!tp->counters) {
8438                 rc = -ENOMEM;
8439                 goto err_out_msi_5;
8440         }
8441
8442         pci_set_drvdata(pdev, dev);
8443
8444         rc = register_netdev(dev);
8445         if (rc < 0)
8446                 goto err_out_cnt_6;
8447
8448         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8449                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8450                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8451         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8452                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8453                            "tx checksumming: %s]\n",
8454                            rtl_chip_infos[chipset].jumbo_max,
8455                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8456         }
8457
8458         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8459              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8460              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8461              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8462              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8463              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8464             r8168_check_dash(tp)) {
8465                 rtl8168_driver_start(tp);
8466         }
8467
8468         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8469
8470         if (pci_dev_run_wake(pdev))
8471                 pm_runtime_put_noidle(&pdev->dev);
8472
8473         netif_carrier_off(dev);
8474
8475 out:
8476         return rc;
8477
8478 err_out_cnt_6:
8479         dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8480                           tp->counters_phys_addr);
8481 err_out_msi_5:
8482         netif_napi_del(&tp->napi);
8483         rtl_disable_msi(pdev, tp);
8484 err_out_unmap_4:
8485         iounmap(ioaddr);
8486 err_out_free_res_3:
8487         pci_release_regions(pdev);
8488 err_out_mwi_2:
8489         pci_clear_mwi(pdev);
8490         pci_disable_device(pdev);
8491 err_out_free_dev_1:
8492         free_netdev(dev);
8493         goto out;
8494 }
8495
8496 static struct pci_driver rtl8169_pci_driver = {
8497         .name           = MODULENAME,
8498         .id_table       = rtl8169_pci_tbl,
8499         .probe          = rtl_init_one,
8500         .remove         = rtl_remove_one,
8501         .shutdown       = rtl_shutdown,
8502         .driver.pm      = RTL8169_PM_OPS,
8503 };
8504
8505 module_pci_driver(rtl8169_pci_driver);