drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014 Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_FWSLC]     = 0x0038,
 205         [TSU_VTAG0]     = 0x0058,
 206         [TSU_ADSBSY]    = 0x0060,
 207         [TSU_TEN]       = 0x0064,
 208         [TSU_POST1]     = 0x0070,
 209         [TSU_POST2]     = 0x0074,
 210         [TSU_POST3]     = 0x0078,
 211         [TSU_POST4]     = 0x007c,
 212         [TSU_ADRH0]     = 0x0100,
 213
 214         [TXNLCR0]       = 0x0080,
 215         [TXALCR0]       = 0x0084,
 216         [RXNLCR0]       = 0x0088,
 217         [RXALCR0]       = 0x008C,
 218 };
 219
 220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 221         SH_ETH_OFFSET_DEFAULTS,
 222
 223         [ECMR]          = 0x0300,
 224         [RFLR]          = 0x0308,
 225         [ECSR]          = 0x0310,
 226         [ECSIPR]        = 0x0318,
 227         [PIR]           = 0x0320,
 228         [PSR]           = 0x0328,
 229         [RDMLR]         = 0x0340,
 230         [IPGR]          = 0x0350,
 231         [APR]           = 0x0354,
 232         [MPR]           = 0x0358,
 233         [RFCF]          = 0x0360,
 234         [TPAUSER]       = 0x0364,
 235         [TPAUSECR]      = 0x0368,
 236         [MAHR]          = 0x03c0,
 237         [MALR]          = 0x03c8,
 238         [TROCR]         = 0x03d0,
 239         [CDCR]          = 0x03d4,
 240         [LCCR]          = 0x03d8,
 241         [CNDCR]         = 0x03dc,
 242         [CEFCR]         = 0x03e4,
 243         [FRECR]         = 0x03e8,
 244         [TSFRCR]        = 0x03ec,
 245         [TLFRCR]        = 0x03f0,
 246         [RFCR]          = 0x03f4,
 247         [MAFCR]         = 0x03f8,
 248
 249         [EDMR]          = 0x0200,
 250         [EDTRR]         = 0x0208,
 251         [EDRRR]         = 0x0210,
 252         [TDLAR]         = 0x0218,
 253         [RDLAR]         = 0x0220,
 254         [EESR]          = 0x0228,
 255         [EESIPR]        = 0x0230,
 256         [TRSCER]        = 0x0238,
 257         [RMFCR]         = 0x0240,
 258         [TFTR]          = 0x0248,
 259         [FDR]           = 0x0250,
 260         [RMCR]          = 0x0258,
 261         [TFUCR]         = 0x0264,
 262         [RFOCR]         = 0x0268,
 263         [RMIIMODE]      = 0x026c,
 264         [FCFTR]         = 0x0270,
 265         [TRIMD]         = 0x027c,
 266 };
 267
 268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 269         SH_ETH_OFFSET_DEFAULTS,
 270
 271         [ECMR]          = 0x0100,
 272         [RFLR]          = 0x0108,
 273         [ECSR]          = 0x0110,
 274         [ECSIPR]        = 0x0118,
 275         [PIR]           = 0x0120,
 276         [PSR]           = 0x0128,
 277         [RDMLR]         = 0x0140,
 278         [IPGR]          = 0x0150,
 279         [APR]           = 0x0154,
 280         [MPR]           = 0x0158,
 281         [TPAUSER]       = 0x0164,
 282         [RFCF]          = 0x0160,
 283         [TPAUSECR]      = 0x0168,
 284         [BCFRR]         = 0x016c,
 285         [MAHR]          = 0x01c0,
 286         [MALR]          = 0x01c8,
 287         [TROCR]         = 0x01d0,
 288         [CDCR]          = 0x01d4,
 289         [LCCR]          = 0x01d8,
 290         [CNDCR]         = 0x01dc,
 291         [CEFCR]         = 0x01e4,
 292         [FRECR]         = 0x01e8,
 293         [TSFRCR]        = 0x01ec,
 294         [TLFRCR]        = 0x01f0,
 295         [RFCR]          = 0x01f4,
 296         [MAFCR]         = 0x01f8,
 297         [RTRATE]        = 0x01fc,
 298
 299         [EDMR]          = 0x0000,
 300         [EDTRR]         = 0x0008,
 301         [EDRRR]         = 0x0010,
 302         [TDLAR]         = 0x0018,
 303         [RDLAR]         = 0x0020,
 304         [EESR]          = 0x0028,
 305         [EESIPR]        = 0x0030,
 306         [TRSCER]        = 0x0038,
 307         [RMFCR]         = 0x0040,
 308         [TFTR]          = 0x0048,
 309         [FDR]           = 0x0050,
 310         [RMCR]          = 0x0058,
 311         [TFUCR]         = 0x0064,
 312         [RFOCR]         = 0x0068,
 313         [FCFTR]         = 0x0070,
 314         [RPADIR]        = 0x0078,
 315         [TRIMD]         = 0x007c,
 316         [RBWAR]         = 0x00c8,
 317         [RDFAR]         = 0x00cc,
 318         [TBRAR]         = 0x00d4,
 319         [TDFAR]         = 0x00d8,
 320 };
 321
 322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 323         SH_ETH_OFFSET_DEFAULTS,
 324
 325         [EDMR]          = 0x0000,
 326         [EDTRR]         = 0x0004,
 327         [EDRRR]         = 0x0008,
 328         [TDLAR]         = 0x000c,
 329         [RDLAR]         = 0x0010,
 330         [EESR]          = 0x0014,
 331         [EESIPR]        = 0x0018,
 332         [TRSCER]        = 0x001c,
 333         [RMFCR]         = 0x0020,
 334         [TFTR]          = 0x0024,
 335         [FDR]           = 0x0028,
 336         [RMCR]          = 0x002c,
 337         [EDOCR]         = 0x0030,
 338         [FCFTR]         = 0x0034,
 339         [RPADIR]        = 0x0038,
 340         [TRIMD]         = 0x003c,
 341         [RBWAR]         = 0x0040,
 342         [RDFAR]         = 0x0044,
 343         [TBRAR]         = 0x004c,
 344         [TDFAR]         = 0x0050,
 345
 346         [ECMR]          = 0x0160,
 347         [ECSR]          = 0x0164,
 348         [ECSIPR]        = 0x0168,
 349         [PIR]           = 0x016c,
 350         [MAHR]          = 0x0170,
 351         [MALR]          = 0x0174,
 352         [RFLR]          = 0x0178,
 353         [PSR]           = 0x017c,
 354         [TROCR]         = 0x0180,
 355         [CDCR]          = 0x0184,
 356         [LCCR]          = 0x0188,
 357         [CNDCR]         = 0x018c,
 358         [CEFCR]         = 0x0194,
 359         [FRECR]         = 0x0198,
 360         [TSFRCR]        = 0x019c,
 361         [TLFRCR]        = 0x01a0,
 362         [RFCR]          = 0x01a4,
 363         [MAFCR]         = 0x01a8,
 364         [IPGR]          = 0x01b4,
 365         [APR]           = 0x01b8,
 366         [MPR]           = 0x01bc,
 367         [TPAUSER]       = 0x01c4,
 368         [BCFR]          = 0x01cc,
 369
 370         [ARSTR]         = 0x0000,
 371         [TSU_CTRST]     = 0x0004,
 372         [TSU_FWEN0]     = 0x0010,
 373         [TSU_FWEN1]     = 0x0014,
 374         [TSU_FCM]       = 0x0018,
 375         [TSU_BSYSL0]    = 0x0020,
 376         [TSU_BSYSL1]    = 0x0024,
 377         [TSU_PRISL0]    = 0x0028,
 378         [TSU_PRISL1]    = 0x002c,
 379         [TSU_FWSL0]     = 0x0030,
 380         [TSU_FWSL1]     = 0x0034,
 381         [TSU_FWSLC]     = 0x0038,
 382         [TSU_QTAGM0]    = 0x0040,
 383         [TSU_QTAGM1]    = 0x0044,
 384         [TSU_ADQT0]     = 0x0048,
 385         [TSU_ADQT1]     = 0x004c,
 386         [TSU_FWSR]      = 0x0050,
 387         [TSU_FWINMK]    = 0x0054,
 388         [TSU_ADSBSY]    = 0x0060,
 389         [TSU_TEN]       = 0x0064,
 390         [TSU_POST1]     = 0x0070,
 391         [TSU_POST2]     = 0x0074,
 392         [TSU_POST3]     = 0x0078,
 393         [TSU_POST4]     = 0x007c,
 394
 395         [TXNLCR0]       = 0x0080,
 396         [TXALCR0]       = 0x0084,
 397         [RXNLCR0]       = 0x0088,
 398         [RXALCR0]       = 0x008c,
 399         [FWNLCR0]       = 0x0090,
 400         [FWALCR0]       = 0x0094,
 401         [TXNLCR1]       = 0x00a0,
 402         [TXALCR1]       = 0x00a0,
 403         [RXNLCR1]       = 0x00a8,
 404         [RXALCR1]       = 0x00ac,
 405         [FWNLCR1]       = 0x00b0,
 406         [FWALCR1]       = 0x00b4,
 407
 408         [TSU_ADRH0]     = 0x0100,
 409 };
 410
 411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 413
 414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 415 {
 416         struct sh_eth_private *mdp = netdev_priv(ndev);
 417         u16 offset = mdp->reg_offset[enum_index];
 418
 419         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 420                 return;
 421
 422         iowrite32(data, mdp->addr + offset);
 423 }
 424
 425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 426 {
 427         struct sh_eth_private *mdp = netdev_priv(ndev);
 428         u16 offset = mdp->reg_offset[enum_index];
 429
 430         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 431                 return ~0U;
 432
 433         return ioread32(mdp->addr + offset);
 434 }
 435
 436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 437                           u32 set)
 438 {
 439         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 440                      enum_index);
 441 }
 442
 443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_gigabit;
 446 }
 447
 448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 449 {
 450         return mdp->reg_offset == sh_eth_offset_fast_rz;
 451 }
 452
 453 static void sh_eth_select_mii(struct net_device *ndev)
 454 {
 455         struct sh_eth_private *mdp = netdev_priv(ndev);
 456         u32 value;
 457
 458         switch (mdp->phy_interface) {
 459         case PHY_INTERFACE_MODE_GMII:
 460                 value = 0x2;
 461                 break;
 462         case PHY_INTERFACE_MODE_MII:
 463                 value = 0x1;
 464                 break;
 465         case PHY_INTERFACE_MODE_RMII:
 466                 value = 0x0;
 467                 break;
 468         default:
 469                 netdev_warn(ndev,
 470                             "PHY interface mode was not setup. Set to MII.\n");
 471                 value = 0x1;
 472                 break;
 473         }
 474
 475         sh_eth_write(ndev, value, RMII_MII);
 476 }
 477
 478 static void sh_eth_set_duplex(struct net_device *ndev)
 479 {
 480         struct sh_eth_private *mdp = netdev_priv(ndev);
 481
 482         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 483 }
 484
 485 static void sh_eth_chip_reset(struct net_device *ndev)
 486 {
 487         struct sh_eth_private *mdp = netdev_priv(ndev);
 488
 489         /* reset device */
 490         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 491         mdelay(1);
 492 }
 493
 494 static void sh_eth_set_rate_gether(struct net_device *ndev)
 495 {
 496         struct sh_eth_private *mdp = netdev_priv(ndev);
 497
 498         switch (mdp->speed) {
 499         case 10: /* 10BASE */
 500                 sh_eth_write(ndev, GECMR_10, GECMR);
 501                 break;
 502         case 100:/* 100BASE */
 503                 sh_eth_write(ndev, GECMR_100, GECMR);
 504                 break;
 505         case 1000: /* 1000BASE */
 506                 sh_eth_write(ndev, GECMR_1000, GECMR);
 507                 break;
 508         }
 509 }
 510
 511 #ifdef CONFIG_OF
 512 /* R7S72100 */
 513 static struct sh_eth_cpu_data r7s72100_data = {
 514         .chip_reset     = sh_eth_chip_reset,
 515         .set_duplex     = sh_eth_set_duplex,
 516
 517         .register_type  = SH_ETH_REG_FAST_RZ,
 518
 519         .ecsr_value     = ECSR_ICD,
 520         .ecsipr_value   = ECSIPR_ICDIP,
 521         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 522                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 523                           EESIPR_ECIIP |
 524                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 525                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 526                           EESIPR_RMAFIP | EESIPR_RRFIP |
 527                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 528                           EESIPR_PREIP | EESIPR_CERFIP,
 529
 530         .tx_check       = EESR_TC1 | EESR_FTC,
 531         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 532                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 533                           EESR_TDE,
 534         .fdr_value      = 0x0000070f,
 535
 536         .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
 537
 538         .no_psr         = 1,
 539         .apr            = 1,
 540         .mpr            = 1,
 541         .tpauser        = 1,
 542         .hw_swap        = 1,
 543         .rpadir         = 1,
 544         .rpadir_value   = 2 << 16,
 545         .no_trimd       = 1,
 546         .no_ade         = 1,
 547         .hw_checksum    = 1,
 548         .tsu            = 1,
 549 };
 550
 551 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 552 {
 553         sh_eth_chip_reset(ndev);
 554
 555         sh_eth_select_mii(ndev);
 556 }
 557
 558 /* R8A7740 */
 559 static struct sh_eth_cpu_data r8a7740_data = {
 560         .chip_reset     = sh_eth_chip_reset_r8a7740,
 561         .set_duplex     = sh_eth_set_duplex,
 562         .set_rate       = sh_eth_set_rate_gether,
 563
 564         .register_type  = SH_ETH_REG_GIGABIT,
 565
 566         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 567         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 568         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 569                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 570                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 571                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 572                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 573                           EESIPR_CEEFIP | EESIPR_CELFIP |
 574                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 575                           EESIPR_PREIP | EESIPR_CERFIP,
 576
 577         .tx_check       = EESR_TC1 | EESR_FTC,
 578         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 579                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 580                           EESR_TDE,
 581         .fdr_value      = 0x0000070f,
 582
 583         .apr            = 1,
 584         .mpr            = 1,
 585         .tpauser        = 1,
 586         .bculr          = 1,
 587         .hw_swap        = 1,
 588         .rpadir         = 1,
 589         .rpadir_value   = 2 << 16,
 590         .no_trimd       = 1,
 591         .no_ade         = 1,
 592         .hw_checksum    = 1,
 593         .tsu            = 1,
 594         .select_mii     = 1,
 595         .magic          = 1,
 596 };
 597
 598 /* There is CPU dependent code */
 599 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 600 {
 601         struct sh_eth_private *mdp = netdev_priv(ndev);
 602
 603         switch (mdp->speed) {
 604         case 10: /* 10BASE */
 605                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 606                 break;
 607         case 100:/* 100BASE */
 608                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 609                 break;
 610         }
 611 }
 612
 613 /* R8A7778/9 */
 614 static struct sh_eth_cpu_data r8a777x_data = {
 615         .set_duplex     = sh_eth_set_duplex,
 616         .set_rate       = sh_eth_set_rate_r8a777x,
 617
 618         .register_type  = SH_ETH_REG_FAST_RCAR,
 619
 620         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 621         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 622         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 623                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 624                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 625                           EESIPR_RMAFIP | EESIPR_RRFIP |
 626                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 627                           EESIPR_PREIP | EESIPR_CERFIP,
 628
 629         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 630         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 631                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 632         .fdr_value      = 0x00000f0f,
 633
 634         .apr            = 1,
 635         .mpr            = 1,
 636         .tpauser        = 1,
 637         .hw_swap        = 1,
 638 };
 639
 640 /* R8A7790/1 */
 641 static struct sh_eth_cpu_data r8a779x_data = {
 642         .set_duplex     = sh_eth_set_duplex,
 643         .set_rate       = sh_eth_set_rate_r8a777x,
 644
 645         .register_type  = SH_ETH_REG_FAST_RCAR,
 646
 647         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 648         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 649                           ECSIPR_MPDIP,
 650         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 651                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 652                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 653                           EESIPR_RMAFIP | EESIPR_RRFIP |
 654                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 655                           EESIPR_PREIP | EESIPR_CERFIP,
 656
 657         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 658         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 659                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 660         .fdr_value      = 0x00000f0f,
 661
 662         .trscer_err_mask = DESC_I_RINT8,
 663
 664         .apr            = 1,
 665         .mpr            = 1,
 666         .tpauser        = 1,
 667         .hw_swap        = 1,
 668         .rmiimode       = 1,
 669         .magic          = 1,
 670 };
 671 #endif /* CONFIG_OF */
 672
 673 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 674 {
 675         struct sh_eth_private *mdp = netdev_priv(ndev);
 676
 677         switch (mdp->speed) {
 678         case 10: /* 10BASE */
 679                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 680                 break;
 681         case 100:/* 100BASE */
 682                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 683                 break;
 684         }
 685 }
 686
 687 /* SH7724 */
 688 static struct sh_eth_cpu_data sh7724_data = {
 689         .set_duplex     = sh_eth_set_duplex,
 690         .set_rate       = sh_eth_set_rate_sh7724,
 691
 692         .register_type  = SH_ETH_REG_FAST_SH4,
 693
 694         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 695         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 696         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 697                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 698                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 699                           EESIPR_RMAFIP | EESIPR_RRFIP |
 700                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 701                           EESIPR_PREIP | EESIPR_CERFIP,
 702
 703         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 704         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 705                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 706
 707         .apr            = 1,
 708         .mpr            = 1,
 709         .tpauser        = 1,
 710         .hw_swap        = 1,
 711         .rpadir         = 1,
 712         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 713 };
 714
 715 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 716 {
 717         struct sh_eth_private *mdp = netdev_priv(ndev);
 718
 719         switch (mdp->speed) {
 720         case 10: /* 10BASE */
 721                 sh_eth_write(ndev, 0, RTRATE);
 722                 break;
 723         case 100:/* 100BASE */
 724                 sh_eth_write(ndev, 1, RTRATE);
 725                 break;
 726         }
 727 }
 728
 729 /* SH7757 */
 730 static struct sh_eth_cpu_data sh7757_data = {
 731         .set_duplex     = sh_eth_set_duplex,
 732         .set_rate       = sh_eth_set_rate_sh7757,
 733
 734         .register_type  = SH_ETH_REG_FAST_SH4,
 735
 736         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 737                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 738                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 739                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 740                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 741                           EESIPR_CEEFIP | EESIPR_CELFIP |
 742                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 743                           EESIPR_PREIP | EESIPR_CERFIP,
 744
 745         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 746         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 747                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 748
 749         .irq_flags      = IRQF_SHARED,
 750         .apr            = 1,
 751         .mpr            = 1,
 752         .tpauser        = 1,
 753         .hw_swap        = 1,
 754         .no_ade         = 1,
 755         .rpadir         = 1,
 756         .rpadir_value   = 2 << 16,
 757         .rtrate         = 1,
 758         .dual_port      = 1,
 759 };
 760
 761 #define SH_GIGA_ETH_BASE        0xfee00000UL
 762 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 763 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 764 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 765 {
 766         u32 mahr[2], malr[2];
 767         int i;
 768
 769         /* save MAHR and MALR */
 770         for (i = 0; i < 2; i++) {
 771                 malr[i] = ioread32((void *)GIGA_MALR(i));
 772                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 773         }
 774
 775         sh_eth_chip_reset(ndev);
 776
 777         /* restore MAHR and MALR */
 778         for (i = 0; i < 2; i++) {
 779                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 780                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 781         }
 782 }
 783
 784 static void sh_eth_set_rate_giga(struct net_device *ndev)
 785 {
 786         struct sh_eth_private *mdp = netdev_priv(ndev);
 787
 788         switch (mdp->speed) {
 789         case 10: /* 10BASE */
 790                 sh_eth_write(ndev, 0x00000000, GECMR);
 791                 break;
 792         case 100:/* 100BASE */
 793                 sh_eth_write(ndev, 0x00000010, GECMR);
 794                 break;
 795         case 1000: /* 1000BASE */
 796                 sh_eth_write(ndev, 0x00000020, GECMR);
 797                 break;
 798         }
 799 }
 800
 801 /* SH7757(GETHERC) */
 802 static struct sh_eth_cpu_data sh7757_data_giga = {
 803         .chip_reset     = sh_eth_chip_reset_giga,
 804         .set_duplex     = sh_eth_set_duplex,
 805         .set_rate       = sh_eth_set_rate_giga,
 806
 807         .register_type  = SH_ETH_REG_GIGABIT,
 808
 809         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 810         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 811         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 812                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 813                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 814                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 815                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 816                           EESIPR_CEEFIP | EESIPR_CELFIP |
 817                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 818                           EESIPR_PREIP | EESIPR_CERFIP,
 819
 820         .tx_check       = EESR_TC1 | EESR_FTC,
 821         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 822                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 823                           EESR_TDE,
 824         .fdr_value      = 0x0000072f,
 825
 826         .irq_flags      = IRQF_SHARED,
 827         .apr            = 1,
 828         .mpr            = 1,
 829         .tpauser        = 1,
 830         .bculr          = 1,
 831         .hw_swap        = 1,
 832         .rpadir         = 1,
 833         .rpadir_value   = 2 << 16,
 834         .no_trimd       = 1,
 835         .no_ade         = 1,
 836         .tsu            = 1,
 837         .dual_port      = 1,
 838 };
 839
 840 /* SH7734 */
 841 static struct sh_eth_cpu_data sh7734_data = {
 842         .chip_reset     = sh_eth_chip_reset,
 843         .set_duplex     = sh_eth_set_duplex,
 844         .set_rate       = sh_eth_set_rate_gether,
 845
 846         .register_type  = SH_ETH_REG_GIGABIT,
 847
 848         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 849         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 850         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 851                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 852                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 853                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 854                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
 855                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 856                           EESIPR_PREIP | EESIPR_CERFIP,
 857
 858         .tx_check       = EESR_TC1 | EESR_FTC,
 859         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 860                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 861                           EESR_TDE,
 862
 863         .apr            = 1,
 864         .mpr            = 1,
 865         .tpauser        = 1,
 866         .bculr          = 1,
 867         .hw_swap        = 1,
 868         .no_trimd       = 1,
 869         .no_ade         = 1,
 870         .tsu            = 1,
 871         .hw_checksum    = 1,
 872         .select_mii     = 1,
 873         .magic          = 1,
 874 };
 875
 876 /* SH7763 */
 877 static struct sh_eth_cpu_data sh7763_data = {
 878         .chip_reset     = sh_eth_chip_reset,
 879         .set_duplex     = sh_eth_set_duplex,
 880         .set_rate       = sh_eth_set_rate_gether,
 881
 882         .register_type  = SH_ETH_REG_GIGABIT,
 883
 884         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 885         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 886         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 887                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 888                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 889                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 890                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
 891                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 892                           EESIPR_PREIP | EESIPR_CERFIP,
 893
 894         .tx_check       = EESR_TC1 | EESR_FTC,
 895         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 896                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 897
 898         .apr            = 1,
 899         .mpr            = 1,
 900         .tpauser        = 1,
 901         .bculr          = 1,
 902         .hw_swap        = 1,
 903         .no_trimd       = 1,
 904         .no_ade         = 1,
 905         .tsu            = 1,
 906         .irq_flags      = IRQF_SHARED,
 907         .magic          = 1,
 908         .dual_port      = 1,
 909 };
 910
 911 static struct sh_eth_cpu_data sh7619_data = {
 912         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 913
 914         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 915                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 916                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 917                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 918                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 919                           EESIPR_CEEFIP | EESIPR_CELFIP |
 920                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 921                           EESIPR_PREIP | EESIPR_CERFIP,
 922
 923         .apr            = 1,
 924         .mpr            = 1,
 925         .tpauser        = 1,
 926         .hw_swap        = 1,
 927 };
 928
 929 static struct sh_eth_cpu_data sh771x_data = {
 930         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 931
 932         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 933                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 934                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 935                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 936                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 937                           EESIPR_CEEFIP | EESIPR_CELFIP |
 938                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 939                           EESIPR_PREIP | EESIPR_CERFIP,
 940
 941         .trscer_err_mask = DESC_I_RINT8,
 942
 943         .tsu            = 1,
 944         .dual_port      = 1,
 945 };
 946
 947 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 948 {
 949         if (!cd->ecsr_value)
 950                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 951
 952         if (!cd->ecsipr_value)
 953                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 954
 955         if (!cd->fcftr_value)
 956                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 957                                   DEFAULT_FIFO_F_D_RFD;
 958
 959         if (!cd->fdr_value)
 960                 cd->fdr_value = DEFAULT_FDR_INIT;
 961
 962         if (!cd->tx_check)
 963                 cd->tx_check = DEFAULT_TX_CHECK;
 964
 965         if (!cd->eesr_err_check)
 966                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 967
 968         if (!cd->trscer_err_mask)
 969                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 970 }
 971
 972 static int sh_eth_check_reset(struct net_device *ndev)
 973 {
 974         int ret = 0;
 975         int cnt = 100;
 976
 977         while (cnt > 0) {
 978                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 979                         break;
 980                 mdelay(1);
 981                 cnt--;
 982         }
 983         if (cnt <= 0) {
 984                 netdev_err(ndev, "Device reset failed\n");
 985                 ret = -ETIMEDOUT;
 986         }
 987         return ret;
 988 }
 989
 990 static int sh_eth_reset(struct net_device *ndev)
 991 {
 992         struct sh_eth_private *mdp = netdev_priv(ndev);
 993         int ret = 0;
 994
 995         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 996                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 997                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 998
 999                 ret = sh_eth_check_reset(ndev);
1000                 if (ret)
1001                         return ret;
1002
1003                 /* Table Init */
1004                 sh_eth_write(ndev, 0x0, TDLAR);
1005                 sh_eth_write(ndev, 0x0, TDFAR);
1006                 sh_eth_write(ndev, 0x0, TDFXR);
1007                 sh_eth_write(ndev, 0x0, TDFFR);
1008                 sh_eth_write(ndev, 0x0, RDLAR);
1009                 sh_eth_write(ndev, 0x0, RDFAR);
1010                 sh_eth_write(ndev, 0x0, RDFXR);
1011                 sh_eth_write(ndev, 0x0, RDFFR);
1012
1013                 /* Reset HW CRC register */
1014                 if (mdp->cd->hw_checksum)
1015                         sh_eth_write(ndev, 0x0, CSMR);
1016
1017                 /* Select MII mode */
1018                 if (mdp->cd->select_mii)
1019                         sh_eth_select_mii(ndev);
1020         } else {
1021                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
1022                 mdelay(3);
1023                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
1024         }
1025
1026         return ret;
1027 }
1028
1029 static void sh_eth_set_receive_align(struct sk_buff *skb)
1030 {
1031         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1032
1033         if (reserve)
1034                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1035 }
1036
1037 /* Program the hardware MAC address from dev->dev_addr. */
1038 static void update_mac_address(struct net_device *ndev)
1039 {
1040         sh_eth_write(ndev,
1041                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1042                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1043         sh_eth_write(ndev,
1044                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1045 }
1046
1047 /* Get MAC address from SuperH MAC address register
1048  *
1049  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1050  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1051  * When you want use this device, you must set MAC address in bootloader.
1052  *
1053  */
1054 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1055 {
1056         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1057                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1058         } else {
1059                 u32 mahr = sh_eth_read(ndev, MAHR);
1060                 u32 malr = sh_eth_read(ndev, MALR);
1061
1062                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1063                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1064                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1065                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1066                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1067                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1068         }
1069 }
1070
1071 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1072 {
1073         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1074                 return EDTRR_TRNS_GETHER;
1075         else
1076                 return EDTRR_TRNS_ETHER;
1077 }
1078
1079 struct bb_info {
1080         void (*set_gate)(void *addr);
1081         struct mdiobb_ctrl ctrl;
1082         void *addr;
1083 };
1084
1085 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1086 {
1087         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1088         u32 pir;
1089
1090         if (bitbang->set_gate)
1091                 bitbang->set_gate(bitbang->addr);
1092
1093         pir = ioread32(bitbang->addr);
1094         if (set)
1095                 pir |=  mask;
1096         else
1097                 pir &= ~mask;
1098         iowrite32(pir, bitbang->addr);
1099 }
1100
1101 /* Data I/O pin control */
1102 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1103 {
1104         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1105 }
1106
1107 /* Set bit data*/
1108 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1109 {
1110         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1111 }
1112
1113 /* Get bit data*/
1114 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1115 {
1116         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1117
1118         if (bitbang->set_gate)
1119                 bitbang->set_gate(bitbang->addr);
1120
1121         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1122 }
1123
1124 /* MDC pin control */
1125 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1126 {
1127         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1128 }
1129
1130 /* mdio bus control struct */
1131 static struct mdiobb_ops bb_ops = {
1132         .owner = THIS_MODULE,
1133         .set_mdc = sh_mdc_ctrl,
1134         .set_mdio_dir = sh_mmd_ctrl,
1135         .set_mdio_data = sh_set_mdio,
1136         .get_mdio_data = sh_get_mdio,
1137 };
1138
1139 /* free Tx skb function */
1140 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1141 {
1142         struct sh_eth_private *mdp = netdev_priv(ndev);
1143         struct sh_eth_txdesc *txdesc;
1144         int free_num = 0;
1145         int entry;
1146         bool sent;
1147
1148         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1149                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1150                 txdesc = &mdp->tx_ring[entry];
1151                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1152                 if (sent_only && !sent)
1153                         break;
1154                 /* TACT bit must be checked before all the following reads */
1155                 dma_rmb();
1156                 netif_info(mdp, tx_done, ndev,
1157                            "tx entry %d status 0x%08x\n",
1158                            entry, le32_to_cpu(txdesc->status));
1159                 /* Free the original skb. */
1160                 if (mdp->tx_skbuff[entry]) {
1161                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1162                                          le32_to_cpu(txdesc->len) >> 16,
1163                                          DMA_TO_DEVICE);
1164                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1165                         mdp->tx_skbuff[entry] = NULL;
1166                         free_num++;
1167                 }
1168                 txdesc->status = cpu_to_le32(TD_TFP);
1169                 if (entry >= mdp->num_tx_ring - 1)
1170                         txdesc->status |= cpu_to_le32(TD_TDLE);
1171
1172                 if (sent) {
1173                         ndev->stats.tx_packets++;
1174                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1175                 }
1176         }
1177         return free_num;
1178 }
1179
1180 /* free skb and descriptor buffer */
1181 static void sh_eth_ring_free(struct net_device *ndev)
1182 {
1183         struct sh_eth_private *mdp = netdev_priv(ndev);
1184         int ringsize, i;
1185
1186         if (mdp->rx_ring) {
1187                 for (i = 0; i < mdp->num_rx_ring; i++) {
1188                         if (mdp->rx_skbuff[i]) {
1189                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1190
1191                                 dma_unmap_single(&ndev->dev,
1192                                                  le32_to_cpu(rxdesc->addr),
1193                                                  ALIGN(mdp->rx_buf_sz, 32),
1194                                                  DMA_FROM_DEVICE);
1195                         }
1196                 }
1197                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1198                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1199                                   mdp->rx_desc_dma);
1200                 mdp->rx_ring = NULL;
1201         }
1202
1203         /* Free Rx skb ringbuffer */
1204         if (mdp->rx_skbuff) {
1205                 for (i = 0; i < mdp->num_rx_ring; i++)
1206                         dev_kfree_skb(mdp->rx_skbuff[i]);
1207         }
1208         kfree(mdp->rx_skbuff);
1209         mdp->rx_skbuff = NULL;
1210
1211         if (mdp->tx_ring) {
1212                 sh_eth_tx_free(ndev, false);
1213
1214                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1215                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1216                                   mdp->tx_desc_dma);
1217                 mdp->tx_ring = NULL;
1218         }
1219
1220         /* Free Tx skb ringbuffer */
1221         kfree(mdp->tx_skbuff);
1222         mdp->tx_skbuff = NULL;
1223 }
1224
1225 /* format skb and descriptor buffer */
1226 static void sh_eth_ring_format(struct net_device *ndev)
1227 {
1228         struct sh_eth_private *mdp = netdev_priv(ndev);
1229         int i;
1230         struct sk_buff *skb;
1231         struct sh_eth_rxdesc *rxdesc = NULL;
1232         struct sh_eth_txdesc *txdesc = NULL;
1233         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1234         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1235         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1236         dma_addr_t dma_addr;
1237         u32 buf_len;
1238
1239         mdp->cur_rx = 0;
1240         mdp->cur_tx = 0;
1241         mdp->dirty_rx = 0;
1242         mdp->dirty_tx = 0;
1243
1244         memset(mdp->rx_ring, 0, rx_ringsize);
1245
1246         /* build Rx ring buffer */
1247         for (i = 0; i < mdp->num_rx_ring; i++) {
1248                 /* skb */
1249                 mdp->rx_skbuff[i] = NULL;
1250                 skb = netdev_alloc_skb(ndev, skbuff_size);
1251                 if (skb == NULL)
1252                         break;
1253                 sh_eth_set_receive_align(skb);
1254
1255                 /* The size of the buffer is a multiple of 32 bytes. */
1256                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1257                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1258                                           DMA_FROM_DEVICE);
1259                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1260                         kfree_skb(skb);
1261                         break;
1262                 }
1263                 mdp->rx_skbuff[i] = skb;
1264
1265                 /* RX descriptor */
1266                 rxdesc = &mdp->rx_ring[i];
1267                 rxdesc->len = cpu_to_le32(buf_len << 16);
1268                 rxdesc->addr = cpu_to_le32(dma_addr);
1269                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1270
1271                 /* Rx descriptor address set */
1272                 if (i == 0) {
1273                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1274                         if (sh_eth_is_gether(mdp) ||
1275                             sh_eth_is_rz_fast_ether(mdp))
1276                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1277                 }
1278         }
1279
1280         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1281
1282         /* Mark the last entry as wrapping the ring. */
1283         if (rxdesc)
1284                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1285
1286         memset(mdp->tx_ring, 0, tx_ringsize);
1287
1288         /* build Tx ring buffer */
1289         for (i = 0; i < mdp->num_tx_ring; i++) {
1290                 mdp->tx_skbuff[i] = NULL;
1291                 txdesc = &mdp->tx_ring[i];
1292                 txdesc->status = cpu_to_le32(TD_TFP);
1293                 txdesc->len = cpu_to_le32(0);
1294                 if (i == 0) {
1295                         /* Tx descriptor address set */
1296                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1297                         if (sh_eth_is_gether(mdp) ||
1298                             sh_eth_is_rz_fast_ether(mdp))
1299                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1300                 }
1301         }
1302
1303         txdesc->status |= cpu_to_le32(TD_TDLE);
1304 }
1305
1306 /* Get skb and descriptor buffer */
1307 static int sh_eth_ring_init(struct net_device *ndev)
1308 {
1309         struct sh_eth_private *mdp = netdev_priv(ndev);
1310         int rx_ringsize, tx_ringsize;
1311
1312         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1313          * card needs room to do 8 byte alignment, +2 so we can reserve
1314          * the first 2 bytes, and +16 gets room for the status word from the
1315          * card.
1316          */
1317         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1318                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1319         if (mdp->cd->rpadir)
1320                 mdp->rx_buf_sz += NET_IP_ALIGN;
1321
1322         /* Allocate RX and TX skb rings */
1323         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1324                                  GFP_KERNEL);
1325         if (!mdp->rx_skbuff)
1326                 return -ENOMEM;
1327
1328         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1329                                  GFP_KERNEL);
1330         if (!mdp->tx_skbuff)
1331                 goto ring_free;
1332
1333         /* Allocate all Rx descriptors. */
1334         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1335         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1336                                           GFP_KERNEL);
1337         if (!mdp->rx_ring)
1338                 goto ring_free;
1339
1340         mdp->dirty_rx = 0;
1341
1342         /* Allocate all Tx descriptors. */
1343         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1344         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1345                                           GFP_KERNEL);
1346         if (!mdp->tx_ring)
1347                 goto ring_free;
1348         return 0;
1349
1350 ring_free:
1351         /* Free Rx and Tx skb ring buffer and DMA buffer */
1352         sh_eth_ring_free(ndev);
1353
1354         return -ENOMEM;
1355 }
1356
1357 static int sh_eth_dev_init(struct net_device *ndev)
1358 {
1359         struct sh_eth_private *mdp = netdev_priv(ndev);
1360         int ret;
1361
1362         /* Soft Reset */
1363         ret = sh_eth_reset(ndev);
1364         if (ret)
1365                 return ret;
1366
1367         if (mdp->cd->rmiimode)
1368                 sh_eth_write(ndev, 0x1, RMIIMODE);
1369
1370         /* Descriptor format */
1371         sh_eth_ring_format(ndev);
1372         if (mdp->cd->rpadir)
1373                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1374
1375         /* all sh_eth int mask */
1376         sh_eth_write(ndev, 0, EESIPR);
1377
1378 #if defined(__LITTLE_ENDIAN)
1379         if (mdp->cd->hw_swap)
1380                 sh_eth_write(ndev, EDMR_EL, EDMR);
1381         else
1382 #endif
1383                 sh_eth_write(ndev, 0, EDMR);
1384
1385         /* FIFO size set */
1386         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1387         sh_eth_write(ndev, 0, TFTR);
1388
1389         /* Frame recv control (enable multiple-packets per rx irq) */
1390         sh_eth_write(ndev, RMCR_RNC, RMCR);
1391
1392         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1393
1394         if (mdp->cd->bculr)
1395                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1396
1397         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1398
1399         if (!mdp->cd->no_trimd)
1400                 sh_eth_write(ndev, 0, TRIMD);
1401
1402         /* Recv frame limit set register */
1403         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1404                      RFLR);
1405
1406         sh_eth_modify(ndev, EESR, 0, 0);
1407         mdp->irq_enabled = true;
1408         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1409
1410         /* PAUSE Prohibition */
1411         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1412                      ECMR_TE | ECMR_RE, ECMR);
1413
1414         if (mdp->cd->set_rate)
1415                 mdp->cd->set_rate(ndev);
1416
1417         /* E-MAC Status Register clear */
1418         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1419
1420         /* E-MAC Interrupt Enable register */
1421         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1422
1423         /* Set MAC address */
1424         update_mac_address(ndev);
1425
1426         /* mask reset */
1427         if (mdp->cd->apr)
1428                 sh_eth_write(ndev, APR_AP, APR);
1429         if (mdp->cd->mpr)
1430                 sh_eth_write(ndev, MPR_MP, MPR);
1431         if (mdp->cd->tpauser)
1432                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1433
1434         /* Setting the Rx mode will start the Rx process. */
1435         sh_eth_write(ndev, EDRRR_R, EDRRR);
1436
1437         return ret;
1438 }
1439
1440 static void sh_eth_dev_exit(struct net_device *ndev)
1441 {
1442         struct sh_eth_private *mdp = netdev_priv(ndev);
1443         int i;
1444
1445         /* Deactivate all TX descriptors, so DMA should stop at next
1446          * packet boundary if it's currently running
1447          */
1448         for (i = 0; i < mdp->num_tx_ring; i++)
1449                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1450
1451         /* Disable TX FIFO egress to MAC */
1452         sh_eth_rcv_snd_disable(ndev);
1453
1454         /* Stop RX DMA at next packet boundary */
1455         sh_eth_write(ndev, 0, EDRRR);
1456
1457         /* Aside from TX DMA, we can't tell when the hardware is
1458          * really stopped, so we need to reset to make sure.
1459          * Before doing that, wait for long enough to *probably*
1460          * finish transmitting the last packet and poll stats.
1461          */
1462         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1463         sh_eth_get_stats(ndev);
1464         sh_eth_reset(ndev);
1465
1466         /* Set the RMII mode again if required */
1467         if (mdp->cd->rmiimode)
1468                 sh_eth_write(ndev, 0x1, RMIIMODE);
1469
1470         /* Set MAC address again */
1471         update_mac_address(ndev);
1472 }
1473
1474 /* Packet receive function */
1475 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1476 {
1477         struct sh_eth_private *mdp = netdev_priv(ndev);
1478         struct sh_eth_rxdesc *rxdesc;
1479
1480         int entry = mdp->cur_rx % mdp->num_rx_ring;
1481         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1482         int limit;
1483         struct sk_buff *skb;
1484         u32 desc_status;
1485         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1486         dma_addr_t dma_addr;
1487         u16 pkt_len;
1488         u32 buf_len;
1489
1490         boguscnt = min(boguscnt, *quota);
1491         limit = boguscnt;
1492         rxdesc = &mdp->rx_ring[entry];
1493         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1494                 /* RACT bit must be checked before all the following reads */
1495                 dma_rmb();
1496                 desc_status = le32_to_cpu(rxdesc->status);
1497                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1498
1499                 if (--boguscnt < 0)
1500                         break;
1501
1502                 netif_info(mdp, rx_status, ndev,
1503                            "rx entry %d status 0x%08x len %d\n",
1504                            entry, desc_status, pkt_len);
1505
1506                 if (!(desc_status & RDFEND))
1507                         ndev->stats.rx_length_errors++;
1508
1509                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1510                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1511                  * bit 0. However, in case of the R8A7740 and R7S72100
1512                  * the RFS bits are from bit 25 to bit 16. So, the
1513                  * driver needs right shifting by 16.
1514                  */
1515                 if (mdp->cd->hw_checksum)
1516                         desc_status >>= 16;
1517
1518                 skb = mdp->rx_skbuff[entry];
1519                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1520                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1521                         ndev->stats.rx_errors++;
1522                         if (desc_status & RD_RFS1)
1523                                 ndev->stats.rx_crc_errors++;
1524                         if (desc_status & RD_RFS2)
1525                                 ndev->stats.rx_frame_errors++;
1526                         if (desc_status & RD_RFS3)
1527                                 ndev->stats.rx_length_errors++;
1528                         if (desc_status & RD_RFS4)
1529                                 ndev->stats.rx_length_errors++;
1530                         if (desc_status & RD_RFS6)
1531                                 ndev->stats.rx_missed_errors++;
1532                         if (desc_status & RD_RFS10)
1533                                 ndev->stats.rx_over_errors++;
1534                 } else  if (skb) {
1535                         dma_addr = le32_to_cpu(rxdesc->addr);
1536                         if (!mdp->cd->hw_swap)
1537                                 sh_eth_soft_swap(
1538                                         phys_to_virt(ALIGN(dma_addr, 4)),
1539                                         pkt_len + 2);
1540                         mdp->rx_skbuff[entry] = NULL;
1541                         if (mdp->cd->rpadir)
1542                                 skb_reserve(skb, NET_IP_ALIGN);
1543                         dma_unmap_single(&ndev->dev, dma_addr,
1544                                          ALIGN(mdp->rx_buf_sz, 32),
1545                                          DMA_FROM_DEVICE);
1546                         skb_put(skb, pkt_len);
1547                         skb->protocol = eth_type_trans(skb, ndev);
1548                         netif_receive_skb(skb);
1549                         ndev->stats.rx_packets++;
1550                         ndev->stats.rx_bytes += pkt_len;
1551                         if (desc_status & RD_RFS8)
1552                                 ndev->stats.multicast++;
1553                 }
1554                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1555                 rxdesc = &mdp->rx_ring[entry];
1556         }
1557
1558         /* Refill the Rx ring buffers. */
1559         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1560                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1561                 rxdesc = &mdp->rx_ring[entry];
1562                 /* The size of the buffer is 32 byte boundary. */
1563                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1564                 rxdesc->len = cpu_to_le32(buf_len << 16);
1565
1566                 if (mdp->rx_skbuff[entry] == NULL) {
1567                         skb = netdev_alloc_skb(ndev, skbuff_size);
1568                         if (skb == NULL)
1569                                 break;  /* Better luck next round. */
1570                         sh_eth_set_receive_align(skb);
1571                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1572                                                   buf_len, DMA_FROM_DEVICE);
1573                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1574                                 kfree_skb(skb);
1575                                 break;
1576                         }
1577                         mdp->rx_skbuff[entry] = skb;
1578
1579                         skb_checksum_none_assert(skb);
1580                         rxdesc->addr = cpu_to_le32(dma_addr);
1581                 }
1582                 dma_wmb(); /* RACT bit must be set after all the above writes */
1583                 if (entry >= mdp->num_rx_ring - 1)
1584                         rxdesc->status |=
1585                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1586                 else
1587                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1588         }
1589
1590         /* Restart Rx engine if stopped. */
1591         /* If we don't need to check status, don't. -KDU */
1592         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1593                 /* fix the values for the next receiving if RDE is set */
1594                 if (intr_status & EESR_RDE &&
1595                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1596                         u32 count = (sh_eth_read(ndev, RDFAR) -
1597                                      sh_eth_read(ndev, RDLAR)) >> 4;
1598
1599                         mdp->cur_rx = count;
1600                         mdp->dirty_rx = count;
1601                 }
1602                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1603         }
1604
1605         *quota -= limit - boguscnt - 1;
1606
1607         return *quota <= 0;
1608 }
1609
1610 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1611 {
1612         /* disable tx and rx */
1613         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1614 }
1615
1616 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1617 {
1618         /* enable tx and rx */
1619         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1620 }
1621
1622 /* E-MAC interrupt handler */
1623 static void sh_eth_emac_interrupt(struct net_device *ndev)
1624 {
1625         struct sh_eth_private *mdp = netdev_priv(ndev);
1626         u32 felic_stat;
1627         u32 link_stat;
1628
1629         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1630         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1631         if (felic_stat & ECSR_ICD)
1632                 ndev->stats.tx_carrier_errors++;
1633         if (felic_stat & ECSR_MPD)
1634                 pm_wakeup_event(&mdp->pdev->dev, 0);
1635         if (felic_stat & ECSR_LCHNG) {
1636                 /* Link Changed */
1637                 if (mdp->cd->no_psr || mdp->no_ether_link)
1638                         return;
1639                 link_stat = sh_eth_read(ndev, PSR);
1640                 if (mdp->ether_link_active_low)
1641                         link_stat = ~link_stat;
1642                 if (!(link_stat & PHY_ST_LINK)) {
1643                         sh_eth_rcv_snd_disable(ndev);
1644                 } else {
1645                         /* Link Up */
1646                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1647                         /* clear int */
1648                         sh_eth_modify(ndev, ECSR, 0, 0);
1649                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1650                         /* enable tx and rx */
1651                         sh_eth_rcv_snd_enable(ndev);
1652                 }
1653         }
1654 }
1655
1656 /* error control function */
1657 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1658 {
1659         struct sh_eth_private *mdp = netdev_priv(ndev);
1660         u32 mask;
1661
1662         if (intr_status & EESR_TWB) {
1663                 /* Unused write back interrupt */
1664                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1665                         ndev->stats.tx_aborted_errors++;
1666                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1667                 }
1668         }
1669
1670         if (intr_status & EESR_RABT) {
1671                 /* Receive Abort int */
1672                 if (intr_status & EESR_RFRMER) {
1673                         /* Receive Frame Overflow int */
1674                         ndev->stats.rx_frame_errors++;
1675                 }
1676         }
1677
1678         if (intr_status & EESR_TDE) {
1679                 /* Transmit Descriptor Empty int */
1680                 ndev->stats.tx_fifo_errors++;
1681                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1682         }
1683
1684         if (intr_status & EESR_TFE) {
1685                 /* FIFO under flow */
1686                 ndev->stats.tx_fifo_errors++;
1687                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1688         }
1689
1690         if (intr_status & EESR_RDE) {
1691                 /* Receive Descriptor Empty int */
1692                 ndev->stats.rx_over_errors++;
1693         }
1694
1695         if (intr_status & EESR_RFE) {
1696                 /* Receive FIFO Overflow int */
1697                 ndev->stats.rx_fifo_errors++;
1698         }
1699
1700         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1701                 /* Address Error */
1702                 ndev->stats.tx_fifo_errors++;
1703                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1704         }
1705
1706         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1707         if (mdp->cd->no_ade)
1708                 mask &= ~EESR_ADE;
1709         if (intr_status & mask) {
1710                 /* Tx error */
1711                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1712
1713                 /* dmesg */
1714                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1715                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1716                            (u32)ndev->state, edtrr);
1717                 /* dirty buffer free */
1718                 sh_eth_tx_free(ndev, true);
1719
1720                 /* SH7712 BUG */
1721                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1722                         /* tx dma start */
1723                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1724                 }
1725                 /* wakeup */
1726                 netif_wake_queue(ndev);
1727         }
1728 }
1729
1730 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1731 {
1732         struct net_device *ndev = netdev;
1733         struct sh_eth_private *mdp = netdev_priv(ndev);
1734         struct sh_eth_cpu_data *cd = mdp->cd;
1735         irqreturn_t ret = IRQ_NONE;
1736         u32 intr_status, intr_enable;
1737
1738         spin_lock(&mdp->lock);
1739
1740         /* Get interrupt status */
1741         intr_status = sh_eth_read(ndev, EESR);
1742         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1743          * enabled since it's the one that  comes  thru regardless of the mask,
1744          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1745          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1746          * bit...
1747          */
1748         intr_enable = sh_eth_read(ndev, EESIPR);
1749         intr_status &= intr_enable | EESIPR_ECIIP;
1750         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1751                            cd->eesr_err_check))
1752                 ret = IRQ_HANDLED;
1753         else
1754                 goto out;
1755
1756         if (unlikely(!mdp->irq_enabled)) {
1757                 sh_eth_write(ndev, 0, EESIPR);
1758                 goto out;
1759         }
1760
1761         if (intr_status & EESR_RX_CHECK) {
1762                 if (napi_schedule_prep(&mdp->napi)) {
1763                         /* Mask Rx interrupts */
1764                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1765                                      EESIPR);
1766                         __napi_schedule(&mdp->napi);
1767                 } else {
1768                         netdev_warn(ndev,
1769                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1770                                     intr_status, intr_enable);
1771                 }
1772         }
1773
1774         /* Tx Check */
1775         if (intr_status & cd->tx_check) {
1776                 /* Clear Tx interrupts */
1777                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1778
1779                 sh_eth_tx_free(ndev, true);
1780                 netif_wake_queue(ndev);
1781         }
1782
1783         /* E-MAC interrupt */
1784         if (intr_status & EESR_ECI)
1785                 sh_eth_emac_interrupt(ndev);
1786
1787         if (intr_status & cd->eesr_err_check) {
1788                 /* Clear error interrupts */
1789                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1790
1791                 sh_eth_error(ndev, intr_status);
1792         }
1793
1794 out:
1795         spin_unlock(&mdp->lock);
1796
1797         return ret;
1798 }
1799
1800 static int sh_eth_poll(struct napi_struct *napi, int budget)
1801 {
1802         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1803                                                   napi);
1804         struct net_device *ndev = napi->dev;
1805         int quota = budget;
1806         u32 intr_status;
1807
1808         for (;;) {
1809                 intr_status = sh_eth_read(ndev, EESR);
1810                 if (!(intr_status & EESR_RX_CHECK))
1811                         break;
1812                 /* Clear Rx interrupts */
1813                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1814
1815                 if (sh_eth_rx(ndev, intr_status, &quota))
1816                         goto out;
1817         }
1818
1819         napi_complete(napi);
1820
1821         /* Reenable Rx interrupts */
1822         if (mdp->irq_enabled)
1823                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1824 out:
1825         return budget - quota;
1826 }
1827
1828 /* PHY state control function */
1829 static void sh_eth_adjust_link(struct net_device *ndev)
1830 {
1831         struct sh_eth_private *mdp = netdev_priv(ndev);
1832         struct phy_device *phydev = ndev->phydev;
1833         unsigned long flags;
1834         int new_state = 0;
1835
1836         spin_lock_irqsave(&mdp->lock, flags);
1837
1838         /* Disable TX and RX right over here, if E-MAC change is ignored */
1839         if (mdp->cd->no_psr || mdp->no_ether_link)
1840                 sh_eth_rcv_snd_disable(ndev);
1841
1842         if (phydev->link) {
1843                 if (phydev->duplex != mdp->duplex) {
1844                         new_state = 1;
1845                         mdp->duplex = phydev->duplex;
1846                         if (mdp->cd->set_duplex)
1847                                 mdp->cd->set_duplex(ndev);
1848                 }
1849
1850                 if (phydev->speed != mdp->speed) {
1851                         new_state = 1;
1852                         mdp->speed = phydev->speed;
1853                         if (mdp->cd->set_rate)
1854                                 mdp->cd->set_rate(ndev);
1855                 }
1856                 if (!mdp->link) {
1857                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1858                         new_state = 1;
1859                         mdp->link = phydev->link;
1860                 }
1861         } else if (mdp->link) {
1862                 new_state = 1;
1863                 mdp->link = 0;
1864                 mdp->speed = 0;
1865                 mdp->duplex = -1;
1866         }
1867
1868         /* Enable TX and RX right over here, if E-MAC change is ignored */
1869         if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1870                 sh_eth_rcv_snd_enable(ndev);
1871
1872         mmiowb();
1873         spin_unlock_irqrestore(&mdp->lock, flags);
1874
1875         if (new_state && netif_msg_link(mdp))
1876                 phy_print_status(phydev);
1877 }
1878
1879 /* PHY init function */
1880 static int sh_eth_phy_init(struct net_device *ndev)
1881 {
1882         struct device_node *np = ndev->dev.parent->of_node;
1883         struct sh_eth_private *mdp = netdev_priv(ndev);
1884         struct phy_device *phydev;
1885
1886         mdp->link = 0;
1887         mdp->speed = 0;
1888         mdp->duplex = -1;
1889
1890         /* Try connect to PHY */
1891         if (np) {
1892                 struct device_node *pn;
1893
1894                 pn = of_parse_phandle(np, "phy-handle", 0);
1895                 phydev = of_phy_connect(ndev, pn,
1896                                         sh_eth_adjust_link, 0,
1897                                         mdp->phy_interface);
1898
1899                 of_node_put(pn);
1900                 if (!phydev)
1901                         phydev = ERR_PTR(-ENOENT);
1902         } else {
1903                 char phy_id[MII_BUS_ID_SIZE + 3];
1904
1905                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1906                          mdp->mii_bus->id, mdp->phy_id);
1907
1908                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1909                                      mdp->phy_interface);
1910         }
1911
1912         if (IS_ERR(phydev)) {
1913                 netdev_err(ndev, "failed to connect PHY\n");
1914                 return PTR_ERR(phydev);
1915         }
1916
1917         phy_attached_info(phydev);
1918
1919         return 0;
1920 }
1921
1922 /* PHY control start function */
1923 static int sh_eth_phy_start(struct net_device *ndev)
1924 {
1925         int ret;
1926
1927         ret = sh_eth_phy_init(ndev);
1928         if (ret)
1929                 return ret;
1930
1931         phy_start(ndev->phydev);
1932
1933         return 0;
1934 }
1935
1936 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1937                                      struct ethtool_link_ksettings *cmd)
1938 {
1939         struct sh_eth_private *mdp = netdev_priv(ndev);
1940         unsigned long flags;
1941
1942         if (!ndev->phydev)
1943                 return -ENODEV;
1944
1945         spin_lock_irqsave(&mdp->lock, flags);
1946         phy_ethtool_ksettings_get(ndev->phydev, cmd);
1947         spin_unlock_irqrestore(&mdp->lock, flags);
1948
1949         return 0;
1950 }
1951
1952 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1953                                      const struct ethtool_link_ksettings *cmd)
1954 {
1955         if (!ndev->phydev)
1956                 return -ENODEV;
1957
1958         return phy_ethtool_ksettings_set(ndev->phydev, cmd);
1959 }
1960
1961 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1962  * version must be bumped as well.  Just adding registers up to that
1963  * limit is fine, as long as the existing register indices don't
1964  * change.
1965  */
1966 #define SH_ETH_REG_DUMP_VERSION         1
1967 #define SH_ETH_REG_DUMP_MAX_REGS        256
1968
1969 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1970 {
1971         struct sh_eth_private *mdp = netdev_priv(ndev);
1972         struct sh_eth_cpu_data *cd = mdp->cd;
1973         u32 *valid_map;
1974         size_t len;
1975
1976         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1977
1978         /* Dump starts with a bitmap that tells ethtool which
1979          * registers are defined for this chip.
1980          */
1981         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1982         if (buf) {
1983                 valid_map = buf;
1984                 buf += len;
1985         } else {
1986                 valid_map = NULL;
1987         }
1988
1989         /* Add a register to the dump, if it has a defined offset.
1990          * This automatically skips most undefined registers, but for
1991          * some it is also necessary to check a capability flag in
1992          * struct sh_eth_cpu_data.
1993          */
1994 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1995 #define add_reg_from(reg, read_expr) do {                               \
1996                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1997                         if (buf) {                                      \
1998                                 mark_reg_valid(reg);                    \
1999                                 *buf++ = read_expr;                     \
2000                         }                                               \
2001                         ++len;                                          \
2002                 }                                                       \
2003         } while (0)
2004 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2005 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2006
2007         add_reg(EDSR);
2008         add_reg(EDMR);
2009         add_reg(EDTRR);
2010         add_reg(EDRRR);
2011         add_reg(EESR);
2012         add_reg(EESIPR);
2013         add_reg(TDLAR);
2014         add_reg(TDFAR);
2015         add_reg(TDFXR);
2016         add_reg(TDFFR);
2017         add_reg(RDLAR);
2018         add_reg(RDFAR);
2019         add_reg(RDFXR);
2020         add_reg(RDFFR);
2021         add_reg(TRSCER);
2022         add_reg(RMFCR);
2023         add_reg(TFTR);
2024         add_reg(FDR);
2025         add_reg(RMCR);
2026         add_reg(TFUCR);
2027         add_reg(RFOCR);
2028         if (cd->rmiimode)
2029                 add_reg(RMIIMODE);
2030         add_reg(FCFTR);
2031         if (cd->rpadir)
2032                 add_reg(RPADIR);
2033         if (!cd->no_trimd)
2034                 add_reg(TRIMD);
2035         add_reg(ECMR);
2036         add_reg(ECSR);
2037         add_reg(ECSIPR);
2038         add_reg(PIR);
2039         if (!cd->no_psr)
2040                 add_reg(PSR);
2041         add_reg(RDMLR);
2042         add_reg(RFLR);
2043         add_reg(IPGR);
2044         if (cd->apr)
2045                 add_reg(APR);
2046         if (cd->mpr)
2047                 add_reg(MPR);
2048         add_reg(RFCR);
2049         add_reg(RFCF);
2050         if (cd->tpauser)
2051                 add_reg(TPAUSER);
2052         add_reg(TPAUSECR);
2053         add_reg(GECMR);
2054         if (cd->bculr)
2055                 add_reg(BCULR);
2056         add_reg(MAHR);
2057         add_reg(MALR);
2058         add_reg(TROCR);
2059         add_reg(CDCR);
2060         add_reg(LCCR);
2061         add_reg(CNDCR);
2062         add_reg(CEFCR);
2063         add_reg(FRECR);
2064         add_reg(TSFRCR);
2065         add_reg(TLFRCR);
2066         add_reg(CERCR);
2067         add_reg(CEECR);
2068         add_reg(MAFCR);
2069         if (cd->rtrate)
2070                 add_reg(RTRATE);
2071         if (cd->hw_checksum)
2072                 add_reg(CSMR);
2073         if (cd->select_mii)
2074                 add_reg(RMII_MII);
2075         add_reg(ARSTR);
2076         if (cd->tsu) {
2077                 add_tsu_reg(TSU_CTRST);
2078                 add_tsu_reg(TSU_FWEN0);
2079                 add_tsu_reg(TSU_FWEN1);
2080                 add_tsu_reg(TSU_FCM);
2081                 add_tsu_reg(TSU_BSYSL0);
2082                 add_tsu_reg(TSU_BSYSL1);
2083                 add_tsu_reg(TSU_PRISL0);
2084                 add_tsu_reg(TSU_PRISL1);
2085                 add_tsu_reg(TSU_FWSL0);
2086                 add_tsu_reg(TSU_FWSL1);
2087                 add_tsu_reg(TSU_FWSLC);
2088                 add_tsu_reg(TSU_QTAG0);
2089                 add_tsu_reg(TSU_QTAG1);
2090                 add_tsu_reg(TSU_QTAGM0);
2091                 add_tsu_reg(TSU_QTAGM1);
2092                 add_tsu_reg(TSU_FWSR);
2093                 add_tsu_reg(TSU_FWINMK);
2094                 add_tsu_reg(TSU_ADQT0);
2095                 add_tsu_reg(TSU_ADQT1);
2096                 add_tsu_reg(TSU_VTAG0);
2097                 add_tsu_reg(TSU_VTAG1);
2098                 add_tsu_reg(TSU_ADSBSY);
2099                 add_tsu_reg(TSU_TEN);
2100                 add_tsu_reg(TSU_POST1);
2101                 add_tsu_reg(TSU_POST2);
2102                 add_tsu_reg(TSU_POST3);
2103                 add_tsu_reg(TSU_POST4);
2104                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2105                         /* This is the start of a table, not just a single
2106                          * register.
2107                          */
2108                         if (buf) {
2109                                 unsigned int i;
2110
2111                                 mark_reg_valid(TSU_ADRH0);
2112                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2113                                         *buf++ = ioread32(
2114                                                 mdp->tsu_addr +
2115                                                 mdp->reg_offset[TSU_ADRH0] +
2116                                                 i * 4);
2117                         }
2118                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2119                 }
2120         }
2121
2122 #undef mark_reg_valid
2123 #undef add_reg_from
2124 #undef add_reg
2125 #undef add_tsu_reg
2126
2127         return len * 4;
2128 }
2129
2130 static int sh_eth_get_regs_len(struct net_device *ndev)
2131 {
2132         return __sh_eth_get_regs(ndev, NULL);
2133 }
2134
2135 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2136                             void *buf)
2137 {
2138         struct sh_eth_private *mdp = netdev_priv(ndev);
2139
2140         regs->version = SH_ETH_REG_DUMP_VERSION;
2141
2142         pm_runtime_get_sync(&mdp->pdev->dev);
2143         __sh_eth_get_regs(ndev, buf);
2144         pm_runtime_put_sync(&mdp->pdev->dev);
2145 }
2146
2147 static int sh_eth_nway_reset(struct net_device *ndev)
2148 {
2149         if (!ndev->phydev)
2150                 return -ENODEV;
2151
2152         return phy_start_aneg(ndev->phydev);
2153 }
2154
2155 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2156 {
2157         struct sh_eth_private *mdp = netdev_priv(ndev);
2158         return mdp->msg_enable;
2159 }
2160
2161 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2162 {
2163         struct sh_eth_private *mdp = netdev_priv(ndev);
2164         mdp->msg_enable = value;
2165 }
2166
2167 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2168         "rx_current", "tx_current",
2169         "rx_dirty", "tx_dirty",
2170 };
2171 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2172
2173 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2174 {
2175         switch (sset) {
2176         case ETH_SS_STATS:
2177                 return SH_ETH_STATS_LEN;
2178         default:
2179                 return -EOPNOTSUPP;
2180         }
2181 }
2182
2183 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2184                                      struct ethtool_stats *stats, u64 *data)
2185 {
2186         struct sh_eth_private *mdp = netdev_priv(ndev);
2187         int i = 0;
2188
2189         /* device-specific stats */
2190         data[i++] = mdp->cur_rx;
2191         data[i++] = mdp->cur_tx;
2192         data[i++] = mdp->dirty_rx;
2193         data[i++] = mdp->dirty_tx;
2194 }
2195
2196 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2197 {
2198         switch (stringset) {
2199         case ETH_SS_STATS:
2200                 memcpy(data, sh_eth_gstrings_stats,
2201                        sizeof(sh_eth_gstrings_stats));
2202                 break;
2203         }
2204 }
2205
2206 static void sh_eth_get_ringparam(struct net_device *ndev,
2207                                  struct ethtool_ringparam *ring)
2208 {
2209         struct sh_eth_private *mdp = netdev_priv(ndev);
2210
2211         ring->rx_max_pending = RX_RING_MAX;
2212         ring->tx_max_pending = TX_RING_MAX;
2213         ring->rx_pending = mdp->num_rx_ring;
2214         ring->tx_pending = mdp->num_tx_ring;
2215 }
2216
2217 static int sh_eth_set_ringparam(struct net_device *ndev,
2218                                 struct ethtool_ringparam *ring)
2219 {
2220         struct sh_eth_private *mdp = netdev_priv(ndev);
2221         int ret;
2222
2223         if (ring->tx_pending > TX_RING_MAX ||
2224             ring->rx_pending > RX_RING_MAX ||
2225             ring->tx_pending < TX_RING_MIN ||
2226             ring->rx_pending < RX_RING_MIN)
2227                 return -EINVAL;
2228         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2229                 return -EINVAL;
2230
2231         if (netif_running(ndev)) {
2232                 netif_device_detach(ndev);
2233                 netif_tx_disable(ndev);
2234
2235                 /* Serialise with the interrupt handler and NAPI, then
2236                  * disable interrupts.  We have to clear the
2237                  * irq_enabled flag first to ensure that interrupts
2238                  * won't be re-enabled.
2239                  */
2240                 mdp->irq_enabled = false;
2241                 synchronize_irq(ndev->irq);
2242                 napi_synchronize(&mdp->napi);
2243                 sh_eth_write(ndev, 0x0000, EESIPR);
2244
2245                 sh_eth_dev_exit(ndev);
2246
2247                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2248                 sh_eth_ring_free(ndev);
2249         }
2250
2251         /* Set new parameters */
2252         mdp->num_rx_ring = ring->rx_pending;
2253         mdp->num_tx_ring = ring->tx_pending;
2254
2255         if (netif_running(ndev)) {
2256                 ret = sh_eth_ring_init(ndev);
2257                 if (ret < 0) {
2258                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2259                                    __func__);
2260                         return ret;
2261                 }
2262                 ret = sh_eth_dev_init(ndev);
2263                 if (ret < 0) {
2264                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2265                                    __func__);
2266                         return ret;
2267                 }
2268
2269                 netif_device_attach(ndev);
2270         }
2271
2272         return 0;
2273 }
2274
2275 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2276 {
2277         struct sh_eth_private *mdp = netdev_priv(ndev);
2278
2279         wol->supported = 0;
2280         wol->wolopts = 0;
2281
2282         if (mdp->cd->magic && mdp->clk) {
2283                 wol->supported = WAKE_MAGIC;
2284                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2285         }
2286 }
2287
2288 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2289 {
2290         struct sh_eth_private *mdp = netdev_priv(ndev);
2291
2292         if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2293                 return -EOPNOTSUPP;
2294
2295         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2296
2297         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2298
2299         return 0;
2300 }
2301
2302 static const struct ethtool_ops sh_eth_ethtool_ops = {
2303         .get_regs_len   = sh_eth_get_regs_len,
2304         .get_regs       = sh_eth_get_regs,
2305         .nway_reset     = sh_eth_nway_reset,
2306         .get_msglevel   = sh_eth_get_msglevel,
2307         .set_msglevel   = sh_eth_set_msglevel,
2308         .get_link       = ethtool_op_get_link,
2309         .get_strings    = sh_eth_get_strings,
2310         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2311         .get_sset_count     = sh_eth_get_sset_count,
2312         .get_ringparam  = sh_eth_get_ringparam,
2313         .set_ringparam  = sh_eth_set_ringparam,
2314         .get_link_ksettings = sh_eth_get_link_ksettings,
2315         .set_link_ksettings = sh_eth_set_link_ksettings,
2316         .get_wol        = sh_eth_get_wol,
2317         .set_wol        = sh_eth_set_wol,
2318 };
2319
2320 /* network device open function */
2321 static int sh_eth_open(struct net_device *ndev)
2322 {
2323         struct sh_eth_private *mdp = netdev_priv(ndev);
2324         int ret;
2325
2326         pm_runtime_get_sync(&mdp->pdev->dev);
2327
2328         napi_enable(&mdp->napi);
2329
2330         ret = request_irq(ndev->irq, sh_eth_interrupt,
2331                           mdp->cd->irq_flags, ndev->name, ndev);
2332         if (ret) {
2333                 netdev_err(ndev, "Can not assign IRQ number\n");
2334                 goto out_napi_off;
2335         }
2336
2337         /* Descriptor set */
2338         ret = sh_eth_ring_init(ndev);
2339         if (ret)
2340                 goto out_free_irq;
2341
2342         /* device init */
2343         ret = sh_eth_dev_init(ndev);
2344         if (ret)
2345                 goto out_free_irq;
2346
2347         /* PHY control start*/
2348         ret = sh_eth_phy_start(ndev);
2349         if (ret)
2350                 goto out_free_irq;
2351
2352         netif_start_queue(ndev);
2353
2354         mdp->is_opened = 1;
2355
2356         return ret;
2357
2358 out_free_irq:
2359         free_irq(ndev->irq, ndev);
2360 out_napi_off:
2361         napi_disable(&mdp->napi);
2362         pm_runtime_put_sync(&mdp->pdev->dev);
2363         return ret;
2364 }
2365
2366 /* Timeout function */
2367 static void sh_eth_tx_timeout(struct net_device *ndev)
2368 {
2369         struct sh_eth_private *mdp = netdev_priv(ndev);
2370         struct sh_eth_rxdesc *rxdesc;
2371         int i;
2372
2373         netif_stop_queue(ndev);
2374
2375         netif_err(mdp, timer, ndev,
2376                   "transmit timed out, status %8.8x, resetting...\n",
2377                   sh_eth_read(ndev, EESR));
2378
2379         /* tx_errors count up */
2380         ndev->stats.tx_errors++;
2381
2382         /* Free all the skbuffs in the Rx queue. */
2383         for (i = 0; i < mdp->num_rx_ring; i++) {
2384                 rxdesc = &mdp->rx_ring[i];
2385                 rxdesc->status = cpu_to_le32(0);
2386                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2387                 dev_kfree_skb(mdp->rx_skbuff[i]);
2388                 mdp->rx_skbuff[i] = NULL;
2389         }
2390         for (i = 0; i < mdp->num_tx_ring; i++) {
2391                 dev_kfree_skb(mdp->tx_skbuff[i]);
2392                 mdp->tx_skbuff[i] = NULL;
2393         }
2394
2395         /* device init */
2396         sh_eth_dev_init(ndev);
2397
2398         netif_start_queue(ndev);
2399 }
2400
2401 /* Packet transmit function */
2402 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2403 {
2404         struct sh_eth_private *mdp = netdev_priv(ndev);
2405         struct sh_eth_txdesc *txdesc;
2406         dma_addr_t dma_addr;
2407         u32 entry;
2408         unsigned long flags;
2409
2410         spin_lock_irqsave(&mdp->lock, flags);
2411         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2412                 if (!sh_eth_tx_free(ndev, true)) {
2413                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2414                         netif_stop_queue(ndev);
2415                         spin_unlock_irqrestore(&mdp->lock, flags);
2416                         return NETDEV_TX_BUSY;
2417                 }
2418         }
2419         spin_unlock_irqrestore(&mdp->lock, flags);
2420
2421         if (skb_put_padto(skb, ETH_ZLEN))
2422                 return NETDEV_TX_OK;
2423
2424         entry = mdp->cur_tx % mdp->num_tx_ring;
2425         mdp->tx_skbuff[entry] = skb;
2426         txdesc = &mdp->tx_ring[entry];
2427         /* soft swap. */
2428         if (!mdp->cd->hw_swap)
2429                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2430         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2431                                   DMA_TO_DEVICE);
2432         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2433                 kfree_skb(skb);
2434                 return NETDEV_TX_OK;
2435         }
2436         txdesc->addr = cpu_to_le32(dma_addr);
2437         txdesc->len  = cpu_to_le32(skb->len << 16);
2438
2439         dma_wmb(); /* TACT bit must be set after all the above writes */
2440         if (entry >= mdp->num_tx_ring - 1)
2441                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2442         else
2443                 txdesc->status |= cpu_to_le32(TD_TACT);
2444
2445         wmb(); /* cur_tx must be incremented after TACT bit was set */
2446         mdp->cur_tx++;
2447
2448         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2449                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2450
2451         return NETDEV_TX_OK;
2452 }
2453
2454 /* The statistics registers have write-clear behaviour, which means we
2455  * will lose any increment between the read and write.  We mitigate
2456  * this by only clearing when we read a non-zero value, so we will
2457  * never falsely report a total of zero.
2458  */
2459 static void
2460 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2461 {
2462         u32 delta = sh_eth_read(ndev, reg);
2463
2464         if (delta) {
2465                 *stat += delta;
2466                 sh_eth_write(ndev, 0, reg);
2467         }
2468 }
2469
2470 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2471 {
2472         struct sh_eth_private *mdp = netdev_priv(ndev);
2473
2474         if (sh_eth_is_rz_fast_ether(mdp))
2475                 return &ndev->stats;
2476
2477         if (!mdp->is_opened)
2478                 return &ndev->stats;
2479
2480         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2481         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2482         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2483
2484         if (sh_eth_is_gether(mdp)) {
2485                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2486                                    CERCR);
2487                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2488                                    CEECR);
2489         } else {
2490                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2491                                    CNDCR);
2492         }
2493
2494         return &ndev->stats;
2495 }
2496
2497 /* device close function */
2498 static int sh_eth_close(struct net_device *ndev)
2499 {
2500         struct sh_eth_private *mdp = netdev_priv(ndev);
2501
2502         netif_stop_queue(ndev);
2503
2504         /* Serialise with the interrupt handler and NAPI, then disable
2505          * interrupts.  We have to clear the irq_enabled flag first to
2506          * ensure that interrupts won't be re-enabled.
2507          */
2508         mdp->irq_enabled = false;
2509         synchronize_irq(ndev->irq);
2510         napi_disable(&mdp->napi);
2511         sh_eth_write(ndev, 0x0000, EESIPR);
2512
2513         sh_eth_dev_exit(ndev);
2514
2515         /* PHY Disconnect */
2516         if (ndev->phydev) {
2517                 phy_stop(ndev->phydev);
2518                 phy_disconnect(ndev->phydev);
2519         }
2520
2521         free_irq(ndev->irq, ndev);
2522
2523         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2524         sh_eth_ring_free(ndev);
2525
2526         mdp->is_opened = 0;
2527
2528         pm_runtime_put(&mdp->pdev->dev);
2529
2530         return 0;
2531 }
2532
2533 /* ioctl to device function */
2534 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2535 {
2536         struct phy_device *phydev = ndev->phydev;
2537
2538         if (!netif_running(ndev))
2539                 return -EINVAL;
2540
2541         if (!phydev)
2542                 return -ENODEV;
2543
2544         return phy_mii_ioctl(phydev, rq, cmd);
2545 }
2546
2547 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2548 {
2549         if (netif_running(ndev))
2550                 return -EBUSY;
2551
2552         ndev->mtu = new_mtu;
2553         netdev_update_features(ndev);
2554
2555         return 0;
2556 }
2557
2558 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2559 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2560                                             int entry)
2561 {
2562         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2563 }
2564
2565 static u32 sh_eth_tsu_get_post_mask(int entry)
2566 {
2567         return 0x0f << (28 - ((entry % 8) * 4));
2568 }
2569
2570 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2571 {
2572         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2573 }
2574
2575 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2576                                              int entry)
2577 {
2578         struct sh_eth_private *mdp = netdev_priv(ndev);
2579         u32 tmp;
2580         void *reg_offset;
2581
2582         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2583         tmp = ioread32(reg_offset);
2584         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2585 }
2586
2587 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2588                                               int entry)
2589 {
2590         struct sh_eth_private *mdp = netdev_priv(ndev);
2591         u32 post_mask, ref_mask, tmp;
2592         void *reg_offset;
2593
2594         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2595         post_mask = sh_eth_tsu_get_post_mask(entry);
2596         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2597
2598         tmp = ioread32(reg_offset);
2599         iowrite32(tmp & ~post_mask, reg_offset);
2600
2601         /* If other port enables, the function returns "true" */
2602         return tmp & ref_mask;
2603 }
2604
2605 static int sh_eth_tsu_busy(struct net_device *ndev)
2606 {
2607         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2608         struct sh_eth_private *mdp = netdev_priv(ndev);
2609
2610         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2611                 udelay(10);
2612                 timeout--;
2613                 if (timeout <= 0) {
2614                         netdev_err(ndev, "%s: timeout\n", __func__);
2615                         return -ETIMEDOUT;
2616                 }
2617         }
2618
2619         return 0;
2620 }
2621
2622 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2623                                   const u8 *addr)
2624 {
2625         u32 val;
2626
2627         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2628         iowrite32(val, reg);
2629         if (sh_eth_tsu_busy(ndev) < 0)
2630                 return -EBUSY;
2631
2632         val = addr[4] << 8 | addr[5];
2633         iowrite32(val, reg + 4);
2634         if (sh_eth_tsu_busy(ndev) < 0)
2635                 return -EBUSY;
2636
2637         return 0;
2638 }
2639
2640 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2641 {
2642         u32 val;
2643
2644         val = ioread32(reg);
2645         addr[0] = (val >> 24) & 0xff;
2646         addr[1] = (val >> 16) & 0xff;
2647         addr[2] = (val >> 8) & 0xff;
2648         addr[3] = val & 0xff;
2649         val = ioread32(reg + 4);
2650         addr[4] = (val >> 8) & 0xff;
2651         addr[5] = val & 0xff;
2652 }
2653
2654
2655 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2656 {
2657         struct sh_eth_private *mdp = netdev_priv(ndev);
2658         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2659         int i;
2660         u8 c_addr[ETH_ALEN];
2661
2662         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2663                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2664                 if (ether_addr_equal(addr, c_addr))
2665                         return i;
2666         }
2667
2668         return -ENOENT;
2669 }
2670
2671 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2672 {
2673         u8 blank[ETH_ALEN];
2674         int entry;
2675
2676         memset(blank, 0, sizeof(blank));
2677         entry = sh_eth_tsu_find_entry(ndev, blank);
2678         return (entry < 0) ? -ENOMEM : entry;
2679 }
2680
2681 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2682                                               int entry)
2683 {
2684         struct sh_eth_private *mdp = netdev_priv(ndev);
2685         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2686         int ret;
2687         u8 blank[ETH_ALEN];
2688
2689         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2690                          ~(1 << (31 - entry)), TSU_TEN);
2691
2692         memset(blank, 0, sizeof(blank));
2693         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2694         if (ret < 0)
2695                 return ret;
2696         return 0;
2697 }
2698
2699 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2700 {
2701         struct sh_eth_private *mdp = netdev_priv(ndev);
2702         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2703         int i, ret;
2704
2705         if (!mdp->cd->tsu)
2706                 return 0;
2707
2708         i = sh_eth_tsu_find_entry(ndev, addr);
2709         if (i < 0) {
2710                 /* No entry found, create one */
2711                 i = sh_eth_tsu_find_empty(ndev);
2712                 if (i < 0)
2713                         return -ENOMEM;
2714                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2715                 if (ret < 0)
2716                         return ret;
2717
2718                 /* Enable the entry */
2719                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2720                                  (1 << (31 - i)), TSU_TEN);
2721         }
2722
2723         /* Entry found or created, enable POST */
2724         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2725
2726         return 0;
2727 }
2728
2729 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2730 {
2731         struct sh_eth_private *mdp = netdev_priv(ndev);
2732         int i, ret;
2733
2734         if (!mdp->cd->tsu)
2735                 return 0;
2736
2737         i = sh_eth_tsu_find_entry(ndev, addr);
2738         if (i) {
2739                 /* Entry found */
2740                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2741                         goto done;
2742
2743                 /* Disable the entry if both ports was disabled */
2744                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2745                 if (ret < 0)
2746                         return ret;
2747         }
2748 done:
2749         return 0;
2750 }
2751
2752 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2753 {
2754         struct sh_eth_private *mdp = netdev_priv(ndev);
2755         int i, ret;
2756
2757         if (!mdp->cd->tsu)
2758                 return 0;
2759
2760         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2761                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2762                         continue;
2763
2764                 /* Disable the entry if both ports was disabled */
2765                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2766                 if (ret < 0)
2767                         return ret;
2768         }
2769
2770         return 0;
2771 }
2772
2773 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2774 {
2775         struct sh_eth_private *mdp = netdev_priv(ndev);
2776         u8 addr[ETH_ALEN];
2777         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2778         int i;
2779
2780         if (!mdp->cd->tsu)
2781                 return;
2782
2783         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2784                 sh_eth_tsu_read_entry(reg_offset, addr);
2785                 if (is_multicast_ether_addr(addr))
2786                         sh_eth_tsu_del_entry(ndev, addr);
2787         }
2788 }
2789
2790 /* Update promiscuous flag and multicast filter */
2791 static void sh_eth_set_rx_mode(struct net_device *ndev)
2792 {
2793         struct sh_eth_private *mdp = netdev_priv(ndev);
2794         u32 ecmr_bits;
2795         int mcast_all = 0;
2796         unsigned long flags;
2797
2798         spin_lock_irqsave(&mdp->lock, flags);
2799         /* Initial condition is MCT = 1, PRM = 0.
2800          * Depending on ndev->flags, set PRM or clear MCT
2801          */
2802         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2803         if (mdp->cd->tsu)
2804                 ecmr_bits |= ECMR_MCT;
2805
2806         if (!(ndev->flags & IFF_MULTICAST)) {
2807                 sh_eth_tsu_purge_mcast(ndev);
2808                 mcast_all = 1;
2809         }
2810         if (ndev->flags & IFF_ALLMULTI) {
2811                 sh_eth_tsu_purge_mcast(ndev);
2812                 ecmr_bits &= ~ECMR_MCT;
2813                 mcast_all = 1;
2814         }
2815
2816         if (ndev->flags & IFF_PROMISC) {
2817                 sh_eth_tsu_purge_all(ndev);
2818                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2819         } else if (mdp->cd->tsu) {
2820                 struct netdev_hw_addr *ha;
2821                 netdev_for_each_mc_addr(ha, ndev) {
2822                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2823                                 continue;
2824
2825                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2826                                 if (!mcast_all) {
2827                                         sh_eth_tsu_purge_mcast(ndev);
2828                                         ecmr_bits &= ~ECMR_MCT;
2829                                         mcast_all = 1;
2830                                 }
2831                         }
2832                 }
2833         }
2834
2835         /* update the ethernet mode */
2836         sh_eth_write(ndev, ecmr_bits, ECMR);
2837
2838         spin_unlock_irqrestore(&mdp->lock, flags);
2839 }
2840
2841 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2842 {
2843         if (!mdp->port)
2844                 return TSU_VTAG0;
2845         else
2846                 return TSU_VTAG1;
2847 }
2848
2849 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2850                                   __be16 proto, u16 vid)
2851 {
2852         struct sh_eth_private *mdp = netdev_priv(ndev);
2853         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2854
2855         if (unlikely(!mdp->cd->tsu))
2856                 return -EPERM;
2857
2858         /* No filtering if vid = 0 */
2859         if (!vid)
2860                 return 0;
2861
2862         mdp->vlan_num_ids++;
2863
2864         /* The controller has one VLAN tag HW filter. So, if the filter is
2865          * already enabled, the driver disables it and the filte
2866          */
2867         if (mdp->vlan_num_ids > 1) {
2868                 /* disable VLAN filter */
2869                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2870                 return 0;
2871         }
2872
2873         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2874                          vtag_reg_index);
2875
2876         return 0;
2877 }
2878
2879 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2880                                    __be16 proto, u16 vid)
2881 {
2882         struct sh_eth_private *mdp = netdev_priv(ndev);
2883         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2884
2885         if (unlikely(!mdp->cd->tsu))
2886                 return -EPERM;
2887
2888         /* No filtering if vid = 0 */
2889         if (!vid)
2890                 return 0;
2891
2892         mdp->vlan_num_ids--;
2893         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2894
2895         return 0;
2896 }
2897
2898 /* SuperH's TSU register init function */
2899 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2900 {
2901         if (!mdp->cd->dual_port) {
2902                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2903                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2904                                  TSU_FWSLC);    /* Enable POST registers */
2905                 return;
2906         }
2907
2908         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2909         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2910         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2911         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2912         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2913         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2914         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2915         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2916         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2917         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2918         if (sh_eth_is_gether(mdp)) {
2919                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2920                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2921         } else {
2922                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2923                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2924         }
2925         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2926         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2927         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2928         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2929         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2930         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2931         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2932 }
2933
2934 /* MDIO bus release function */
2935 static int sh_mdio_release(struct sh_eth_private *mdp)
2936 {
2937         /* unregister mdio bus */
2938         mdiobus_unregister(mdp->mii_bus);
2939
2940         /* free bitbang info */
2941         free_mdio_bitbang(mdp->mii_bus);
2942
2943         return 0;
2944 }
2945
2946 /* MDIO bus init function */
2947 static int sh_mdio_init(struct sh_eth_private *mdp,
2948                         struct sh_eth_plat_data *pd)
2949 {
2950         int ret;
2951         struct bb_info *bitbang;
2952         struct platform_device *pdev = mdp->pdev;
2953         struct device *dev = &mdp->pdev->dev;
2954
2955         /* create bit control struct for PHY */
2956         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2957         if (!bitbang)
2958                 return -ENOMEM;
2959
2960         /* bitbang init */
2961         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2962         bitbang->set_gate = pd->set_mdio_gate;
2963         bitbang->ctrl.ops = &bb_ops;
2964
2965         /* MII controller setting */
2966         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2967         if (!mdp->mii_bus)
2968                 return -ENOMEM;
2969
2970         /* Hook up MII support for ethtool */
2971         mdp->mii_bus->name = "sh_mii";
2972         mdp->mii_bus->parent = dev;
2973         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2974                  pdev->name, pdev->id);
2975
2976         /* register MDIO bus */
2977         if (dev->of_node) {
2978                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2979         } else {
2980                 if (pd->phy_irq > 0)
2981                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2982
2983                 ret = mdiobus_register(mdp->mii_bus);
2984         }
2985
2986         if (ret)
2987                 goto out_free_bus;
2988
2989         return 0;
2990
2991 out_free_bus:
2992         free_mdio_bitbang(mdp->mii_bus);
2993         return ret;
2994 }
2995
2996 static const u16 *sh_eth_get_register_offset(int register_type)
2997 {
2998         const u16 *reg_offset = NULL;
2999
3000         switch (register_type) {
3001         case SH_ETH_REG_GIGABIT:
3002                 reg_offset = sh_eth_offset_gigabit;
3003                 break;
3004         case SH_ETH_REG_FAST_RZ:
3005                 reg_offset = sh_eth_offset_fast_rz;
3006                 break;
3007         case SH_ETH_REG_FAST_RCAR:
3008                 reg_offset = sh_eth_offset_fast_rcar;
3009                 break;
3010         case SH_ETH_REG_FAST_SH4:
3011                 reg_offset = sh_eth_offset_fast_sh4;
3012                 break;
3013         case SH_ETH_REG_FAST_SH3_SH2:
3014                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3015                 break;
3016         }
3017
3018         return reg_offset;
3019 }
3020
3021 static const struct net_device_ops sh_eth_netdev_ops = {
3022         .ndo_open               = sh_eth_open,
3023         .ndo_stop               = sh_eth_close,
3024         .ndo_start_xmit         = sh_eth_start_xmit,
3025         .ndo_get_stats          = sh_eth_get_stats,
3026         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3027         .ndo_tx_timeout         = sh_eth_tx_timeout,
3028         .ndo_do_ioctl           = sh_eth_do_ioctl,
3029         .ndo_change_mtu         = sh_eth_change_mtu,
3030         .ndo_validate_addr      = eth_validate_addr,
3031         .ndo_set_mac_address    = eth_mac_addr,
3032 };
3033
3034 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3035         .ndo_open               = sh_eth_open,
3036         .ndo_stop               = sh_eth_close,
3037         .ndo_start_xmit         = sh_eth_start_xmit,
3038         .ndo_get_stats          = sh_eth_get_stats,
3039         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3040         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3041         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3042         .ndo_tx_timeout         = sh_eth_tx_timeout,
3043         .ndo_do_ioctl           = sh_eth_do_ioctl,
3044         .ndo_change_mtu         = sh_eth_change_mtu,
3045         .ndo_validate_addr      = eth_validate_addr,
3046         .ndo_set_mac_address    = eth_mac_addr,
3047 };
3048
3049 #ifdef CONFIG_OF
3050 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3051 {
3052         struct device_node *np = dev->of_node;
3053         struct sh_eth_plat_data *pdata;
3054         const char *mac_addr;
3055         int ret;
3056
3057         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3058         if (!pdata)
3059                 return NULL;
3060
3061         ret = of_get_phy_mode(np);
3062         if (ret < 0)
3063                 return NULL;
3064         pdata->phy_interface = ret;
3065
3066         mac_addr = of_get_mac_address(np);
3067         if (mac_addr)
3068                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3069
3070         pdata->no_ether_link =
3071                 of_property_read_bool(np, "renesas,no-ether-link");
3072         pdata->ether_link_active_low =
3073                 of_property_read_bool(np, "renesas,ether-link-active-low");
3074
3075         return pdata;
3076 }
3077
3078 static const struct of_device_id sh_eth_match_table[] = {
3079         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3080         { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
3081         { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
3082         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3083         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3084         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3085         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3086         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3087         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3088         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3089         { }
3090 };
3091 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3092 #else
3093 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3094 {
3095         return NULL;
3096 }
3097 #endif
3098
3099 static int sh_eth_drv_probe(struct platform_device *pdev)
3100 {
3101         struct resource *res;
3102         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3103         const struct platform_device_id *id = platform_get_device_id(pdev);
3104         struct sh_eth_private *mdp;
3105         struct net_device *ndev;
3106         int ret, devno;
3107
3108         /* get base addr */
3109         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3110
3111         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3112         if (!ndev)
3113                 return -ENOMEM;
3114
3115         pm_runtime_enable(&pdev->dev);
3116         pm_runtime_get_sync(&pdev->dev);
3117
3118         devno = pdev->id;
3119         if (devno < 0)
3120                 devno = 0;
3121
3122         ret = platform_get_irq(pdev, 0);
3123         if (ret < 0)
3124                 goto out_release;
3125         ndev->irq = ret;
3126
3127         SET_NETDEV_DEV(ndev, &pdev->dev);
3128
3129         mdp = netdev_priv(ndev);
3130         mdp->num_tx_ring = TX_RING_SIZE;
3131         mdp->num_rx_ring = RX_RING_SIZE;
3132         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3133         if (IS_ERR(mdp->addr)) {
3134                 ret = PTR_ERR(mdp->addr);
3135                 goto out_release;
3136         }
3137
3138         /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3139         mdp->clk = devm_clk_get(&pdev->dev, NULL);
3140         if (IS_ERR(mdp->clk))
3141                 mdp->clk = NULL;
3142
3143         ndev->base_addr = res->start;
3144
3145         spin_lock_init(&mdp->lock);
3146         mdp->pdev = pdev;
3147
3148         if (pdev->dev.of_node)
3149                 pd = sh_eth_parse_dt(&pdev->dev);
3150         if (!pd) {
3151                 dev_err(&pdev->dev, "no platform data\n");
3152                 ret = -EINVAL;
3153                 goto out_release;
3154         }
3155
3156         /* get PHY ID */
3157         mdp->phy_id = pd->phy;
3158         mdp->phy_interface = pd->phy_interface;
3159         mdp->no_ether_link = pd->no_ether_link;
3160         mdp->ether_link_active_low = pd->ether_link_active_low;
3161
3162         /* set cpu data */
3163         if (id)
3164                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3165         else
3166                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3167
3168         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3169         if (!mdp->reg_offset) {
3170                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3171                         mdp->cd->register_type);
3172                 ret = -EINVAL;
3173                 goto out_release;
3174         }
3175         sh_eth_set_default_cpu_data(mdp->cd);
3176
3177         /* User's manual states max MTU should be 2048 but due to the
3178          * alignment calculations in sh_eth_ring_init() the practical
3179          * MTU is a bit less. Maybe this can be optimized some more.
3180          */
3181         ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3182         ndev->min_mtu = ETH_MIN_MTU;
3183
3184         /* set function */
3185         if (mdp->cd->tsu)
3186                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3187         else
3188                 ndev->netdev_ops = &sh_eth_netdev_ops;
3189         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3190         ndev->watchdog_timeo = TX_TIMEOUT;
3191
3192         /* debug message level */
3193         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3194
3195         /* read and set MAC address */
3196         read_mac_address(ndev, pd->mac_addr);
3197         if (!is_valid_ether_addr(ndev->dev_addr)) {
3198                 dev_warn(&pdev->dev,
3199                          "no valid MAC address supplied, using a random one.\n");
3200                 eth_hw_addr_random(ndev);
3201         }
3202
3203         /* ioremap the TSU registers */
3204         if (mdp->cd->tsu) {
3205                 struct resource *rtsu;
3206
3207                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3208                 if (!rtsu) {
3209                         dev_err(&pdev->dev, "no TSU resource\n");
3210                         ret = -ENODEV;
3211                         goto out_release;
3212                 }
3213                 /* We can only request the  TSU region  for the first port
3214                  * of the two  sharing this TSU for the probe to succeed...
3215                  */
3216                 if (devno % 2 == 0 &&
3217                     !devm_request_mem_region(&pdev->dev, rtsu->start,
3218                                              resource_size(rtsu),
3219                                              dev_name(&pdev->dev))) {
3220                         dev_err(&pdev->dev, "can't request TSU resource.\n");
3221                         ret = -EBUSY;
3222                         goto out_release;
3223                 }
3224                 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3225                                              resource_size(rtsu));
3226                 if (!mdp->tsu_addr) {
3227                         dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3228                         ret = -ENOMEM;
3229                         goto out_release;
3230                 }
3231                 mdp->port = devno % 2;
3232                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3233         }
3234
3235         /* Need to init only the first port of the two sharing a TSU */
3236         if (devno % 2 == 0) {
3237                 if (mdp->cd->chip_reset)
3238                         mdp->cd->chip_reset(ndev);
3239
3240                 if (mdp->cd->tsu) {
3241                         /* TSU init (Init only)*/
3242                         sh_eth_tsu_init(mdp);
3243                 }
3244         }
3245
3246         if (mdp->cd->rmiimode)
3247                 sh_eth_write(ndev, 0x1, RMIIMODE);
3248
3249         /* MDIO bus init */
3250         ret = sh_mdio_init(mdp, pd);
3251         if (ret) {
3252                 if (ret != -EPROBE_DEFER)
3253                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3254                 goto out_release;
3255         }
3256
3257         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3258
3259         /* network device register */
3260         ret = register_netdev(ndev);
3261         if (ret)
3262                 goto out_napi_del;
3263
3264         if (mdp->cd->magic && mdp->clk)
3265                 device_set_wakeup_capable(&pdev->dev, 1);
3266
3267         /* print device information */
3268         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3269                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3270
3271         pm_runtime_put(&pdev->dev);
3272         platform_set_drvdata(pdev, ndev);
3273
3274         return ret;
3275
3276 out_napi_del:
3277         netif_napi_del(&mdp->napi);
3278         sh_mdio_release(mdp);
3279
3280 out_release:
3281         /* net_dev free */
3282         if (ndev)
3283                 free_netdev(ndev);
3284
3285         pm_runtime_put(&pdev->dev);
3286         pm_runtime_disable(&pdev->dev);
3287         return ret;
3288 }
3289
3290 static int sh_eth_drv_remove(struct platform_device *pdev)
3291 {
3292         struct net_device *ndev = platform_get_drvdata(pdev);
3293         struct sh_eth_private *mdp = netdev_priv(ndev);
3294
3295         unregister_netdev(ndev);
3296         netif_napi_del(&mdp->napi);
3297         sh_mdio_release(mdp);
3298         pm_runtime_disable(&pdev->dev);
3299         free_netdev(ndev);
3300
3301         return 0;
3302 }
3303
3304 #ifdef CONFIG_PM
3305 #ifdef CONFIG_PM_SLEEP
3306 static int sh_eth_wol_setup(struct net_device *ndev)
3307 {
3308         struct sh_eth_private *mdp = netdev_priv(ndev);
3309
3310         /* Only allow ECI interrupts */
3311         synchronize_irq(ndev->irq);
3312         napi_disable(&mdp->napi);
3313         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3314
3315         /* Enable MagicPacket */
3316         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3317
3318         /* Increased clock usage so device won't be suspended */
3319         clk_enable(mdp->clk);
3320
3321         return enable_irq_wake(ndev->irq);
3322 }
3323
3324 static int sh_eth_wol_restore(struct net_device *ndev)
3325 {
3326         struct sh_eth_private *mdp = netdev_priv(ndev);
3327         int ret;
3328
3329         napi_enable(&mdp->napi);
3330
3331         /* Disable MagicPacket */
3332         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3333
3334         /* The device needs to be reset to restore MagicPacket logic
3335          * for next wakeup. If we close and open the device it will
3336          * both be reset and all registers restored. This is what
3337          * happens during suspend and resume without WoL enabled.
3338          */
3339         ret = sh_eth_close(ndev);
3340         if (ret < 0)
3341                 return ret;
3342         ret = sh_eth_open(ndev);
3343         if (ret < 0)
3344                 return ret;
3345
3346         /* Restore clock usage count */
3347         clk_disable(mdp->clk);
3348
3349         return disable_irq_wake(ndev->irq);
3350 }
3351
3352 static int sh_eth_suspend(struct device *dev)
3353 {
3354         struct net_device *ndev = dev_get_drvdata(dev);
3355         struct sh_eth_private *mdp = netdev_priv(ndev);
3356         int ret = 0;
3357
3358         if (!netif_running(ndev))
3359                 return 0;
3360
3361         netif_device_detach(ndev);
3362
3363         if (mdp->wol_enabled)
3364                 ret = sh_eth_wol_setup(ndev);
3365         else
3366                 ret = sh_eth_close(ndev);
3367
3368         return ret;
3369 }
3370
3371 static int sh_eth_resume(struct device *dev)
3372 {
3373         struct net_device *ndev = dev_get_drvdata(dev);
3374         struct sh_eth_private *mdp = netdev_priv(ndev);
3375         int ret = 0;
3376
3377         if (!netif_running(ndev))
3378                 return 0;
3379
3380         if (mdp->wol_enabled)
3381                 ret = sh_eth_wol_restore(ndev);
3382         else
3383                 ret = sh_eth_open(ndev);
3384
3385         if (ret < 0)
3386                 return ret;
3387
3388         netif_device_attach(ndev);
3389
3390         return ret;
3391 }
3392 #endif
3393
3394 static int sh_eth_runtime_nop(struct device *dev)
3395 {
3396         /* Runtime PM callback shared between ->runtime_suspend()
3397          * and ->runtime_resume(). Simply returns success.
3398          *
3399          * This driver re-initializes all registers after
3400          * pm_runtime_get_sync() anyway so there is no need
3401          * to save and restore registers here.
3402          */
3403         return 0;
3404 }
3405
3406 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3407         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3408         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3409 };
3410 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3411 #else
3412 #define SH_ETH_PM_OPS NULL
3413 #endif
3414
3415 static const struct platform_device_id sh_eth_id_table[] = {
3416         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3417         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3418         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3419         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3420         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3421         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3422         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3423         { }
3424 };
3425 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3426
3427 static struct platform_driver sh_eth_driver = {
3428         .probe = sh_eth_drv_probe,
3429         .remove = sh_eth_drv_remove,
3430         .id_table = sh_eth_id_table,
3431         .driver = {
3432                    .name = CARDNAME,
3433                    .pm = SH_ETH_PM_OPS,
3434                    .of_match_table = of_match_ptr(sh_eth_match_table),
3435         },
3436 };
3437
3438 module_platform_driver(sh_eth_driver);
3439
3440 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3441 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3442 MODULE_LICENSE("GPL v2");