drivers/net/ethernet/renesas/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2014 Renesas Electronics Corporation
   5  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   6  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   7  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   8  *  Copyright (C) 2014 Codethink Limited
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mdio-bitbang.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_net.h>
  25 #include <linux/phy.h>
  26 #include <linux/cache.h>
  27 #include <linux/io.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/slab.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/sh_eth.h>
  33 #include <linux/of_mdio.h>
  34
  35 #include "sh_eth.h"
  36
  37 #define SH_ETH_DEF_MSG_ENABLE \
  38                 (NETIF_MSG_LINK | \
  39                 NETIF_MSG_TIMER | \
  40                 NETIF_MSG_RX_ERR| \
  41                 NETIF_MSG_TX_ERR)
  42
  43 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  44
  45 #define SH_ETH_OFFSET_DEFAULTS                  \
  46         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  47
  48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  49         SH_ETH_OFFSET_DEFAULTS,
  50
  51         [EDSR]          = 0x0000,
  52         [EDMR]          = 0x0400,
  53         [EDTRR]         = 0x0408,
  54         [EDRRR]         = 0x0410,
  55         [EESR]          = 0x0428,
  56         [EESIPR]        = 0x0430,
  57         [TDLAR]         = 0x0010,
  58         [TDFAR]         = 0x0014,
  59         [TDFXR]         = 0x0018,
  60         [TDFFR]         = 0x001c,
  61         [RDLAR]         = 0x0030,
  62         [RDFAR]         = 0x0034,
  63         [RDFXR]         = 0x0038,
  64         [RDFFR]         = 0x003c,
  65         [TRSCER]        = 0x0438,
  66         [RMFCR]         = 0x0440,
  67         [TFTR]          = 0x0448,
  68         [FDR]           = 0x0450,
  69         [RMCR]          = 0x0458,
  70         [RPADIR]        = 0x0460,
  71         [FCFTR]         = 0x0468,
  72         [CSMR]          = 0x04E4,
  73
  74         [ECMR]          = 0x0500,
  75         [ECSR]          = 0x0510,
  76         [ECSIPR]        = 0x0518,
  77         [PIR]           = 0x0520,
  78         [PSR]           = 0x0528,
  79         [PIPR]          = 0x052c,
  80         [RFLR]          = 0x0508,
  81         [APR]           = 0x0554,
  82         [MPR]           = 0x0558,
  83         [PFTCR]         = 0x055c,
  84         [PFRCR]         = 0x0560,
  85         [TPAUSER]       = 0x0564,
  86         [GECMR]         = 0x05b0,
  87         [BCULR]         = 0x05b4,
  88         [MAHR]          = 0x05c0,
  89         [MALR]          = 0x05c8,
  90         [TROCR]         = 0x0700,
  91         [CDCR]          = 0x0708,
  92         [LCCR]          = 0x0710,
  93         [CEFCR]         = 0x0740,
  94         [FRECR]         = 0x0748,
  95         [TSFRCR]        = 0x0750,
  96         [TLFRCR]        = 0x0758,
  97         [RFCR]          = 0x0760,
  98         [CERCR]         = 0x0768,
  99         [CEECR]         = 0x0770,
 100         [MAFCR]         = 0x0778,
 101         [RMII_MII]      = 0x0790,
 102
 103         [ARSTR]         = 0x0000,
 104         [TSU_CTRST]     = 0x0004,
 105         [TSU_FWEN0]     = 0x0010,
 106         [TSU_FWEN1]     = 0x0014,
 107         [TSU_FCM]       = 0x0018,
 108         [TSU_BSYSL0]    = 0x0020,
 109         [TSU_BSYSL1]    = 0x0024,
 110         [TSU_PRISL0]    = 0x0028,
 111         [TSU_PRISL1]    = 0x002c,
 112         [TSU_FWSL0]     = 0x0030,
 113         [TSU_FWSL1]     = 0x0034,
 114         [TSU_FWSLC]     = 0x0038,
 115         [TSU_QTAGM0]    = 0x0040,
 116         [TSU_QTAGM1]    = 0x0044,
 117         [TSU_FWSR]      = 0x0050,
 118         [TSU_FWINMK]    = 0x0054,
 119         [TSU_ADQT0]     = 0x0048,
 120         [TSU_ADQT1]     = 0x004c,
 121         [TSU_VTAG0]     = 0x0058,
 122         [TSU_VTAG1]     = 0x005c,
 123         [TSU_ADSBSY]    = 0x0060,
 124         [TSU_TEN]       = 0x0064,
 125         [TSU_POST1]     = 0x0070,
 126         [TSU_POST2]     = 0x0074,
 127         [TSU_POST3]     = 0x0078,
 128         [TSU_POST4]     = 0x007c,
 129         [TSU_ADRH0]     = 0x0100,
 130
 131         [TXNLCR0]       = 0x0080,
 132         [TXALCR0]       = 0x0084,
 133         [RXNLCR0]       = 0x0088,
 134         [RXALCR0]       = 0x008c,
 135         [FWNLCR0]       = 0x0090,
 136         [FWALCR0]       = 0x0094,
 137         [TXNLCR1]       = 0x00a0,
 138         [TXALCR1]       = 0x00a4,
 139         [RXNLCR1]       = 0x00a8,
 140         [RXALCR1]       = 0x00ac,
 141         [FWNLCR1]       = 0x00b0,
 142         [FWALCR1]       = 0x00b4,
 143 };
 144
 145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 146         SH_ETH_OFFSET_DEFAULTS,
 147
 148         [EDSR]          = 0x0000,
 149         [EDMR]          = 0x0400,
 150         [EDTRR]         = 0x0408,
 151         [EDRRR]         = 0x0410,
 152         [EESR]          = 0x0428,
 153         [EESIPR]        = 0x0430,
 154         [TDLAR]         = 0x0010,
 155         [TDFAR]         = 0x0014,
 156         [TDFXR]         = 0x0018,
 157         [TDFFR]         = 0x001c,
 158         [RDLAR]         = 0x0030,
 159         [RDFAR]         = 0x0034,
 160         [RDFXR]         = 0x0038,
 161         [RDFFR]         = 0x003c,
 162         [TRSCER]        = 0x0438,
 163         [RMFCR]         = 0x0440,
 164         [TFTR]          = 0x0448,
 165         [FDR]           = 0x0450,
 166         [RMCR]          = 0x0458,
 167         [RPADIR]        = 0x0460,
 168         [FCFTR]         = 0x0468,
 169         [CSMR]          = 0x04E4,
 170
 171         [ECMR]          = 0x0500,
 172         [RFLR]          = 0x0508,
 173         [ECSR]          = 0x0510,
 174         [ECSIPR]        = 0x0518,
 175         [PIR]           = 0x0520,
 176         [APR]           = 0x0554,
 177         [MPR]           = 0x0558,
 178         [PFTCR]         = 0x055c,
 179         [PFRCR]         = 0x0560,
 180         [TPAUSER]       = 0x0564,
 181         [MAHR]          = 0x05c0,
 182         [MALR]          = 0x05c8,
 183         [CEFCR]         = 0x0740,
 184         [FRECR]         = 0x0748,
 185         [TSFRCR]        = 0x0750,
 186         [TLFRCR]        = 0x0758,
 187         [RFCR]          = 0x0760,
 188         [MAFCR]         = 0x0778,
 189
 190         [ARSTR]         = 0x0000,
 191         [TSU_CTRST]     = 0x0004,
 192         [TSU_FWSLC]     = 0x0038,
 193         [TSU_VTAG0]     = 0x0058,
 194         [TSU_ADSBSY]    = 0x0060,
 195         [TSU_TEN]       = 0x0064,
 196         [TSU_POST1]     = 0x0070,
 197         [TSU_POST2]     = 0x0074,
 198         [TSU_POST3]     = 0x0078,
 199         [TSU_POST4]     = 0x007c,
 200         [TSU_ADRH0]     = 0x0100,
 201
 202         [TXNLCR0]       = 0x0080,
 203         [TXALCR0]       = 0x0084,
 204         [RXNLCR0]       = 0x0088,
 205         [RXALCR0]       = 0x008C,
 206 };
 207
 208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 209         SH_ETH_OFFSET_DEFAULTS,
 210
 211         [ECMR]          = 0x0300,
 212         [RFLR]          = 0x0308,
 213         [ECSR]          = 0x0310,
 214         [ECSIPR]        = 0x0318,
 215         [PIR]           = 0x0320,
 216         [PSR]           = 0x0328,
 217         [RDMLR]         = 0x0340,
 218         [IPGR]          = 0x0350,
 219         [APR]           = 0x0354,
 220         [MPR]           = 0x0358,
 221         [RFCF]          = 0x0360,
 222         [TPAUSER]       = 0x0364,
 223         [TPAUSECR]      = 0x0368,
 224         [MAHR]          = 0x03c0,
 225         [MALR]          = 0x03c8,
 226         [TROCR]         = 0x03d0,
 227         [CDCR]          = 0x03d4,
 228         [LCCR]          = 0x03d8,
 229         [CNDCR]         = 0x03dc,
 230         [CEFCR]         = 0x03e4,
 231         [FRECR]         = 0x03e8,
 232         [TSFRCR]        = 0x03ec,
 233         [TLFRCR]        = 0x03f0,
 234         [RFCR]          = 0x03f4,
 235         [MAFCR]         = 0x03f8,
 236
 237         [EDMR]          = 0x0200,
 238         [EDTRR]         = 0x0208,
 239         [EDRRR]         = 0x0210,
 240         [TDLAR]         = 0x0218,
 241         [RDLAR]         = 0x0220,
 242         [EESR]          = 0x0228,
 243         [EESIPR]        = 0x0230,
 244         [TRSCER]        = 0x0238,
 245         [RMFCR]         = 0x0240,
 246         [TFTR]          = 0x0248,
 247         [FDR]           = 0x0250,
 248         [RMCR]          = 0x0258,
 249         [TFUCR]         = 0x0264,
 250         [RFOCR]         = 0x0268,
 251         [RMIIMODE]      = 0x026c,
 252         [FCFTR]         = 0x0270,
 253         [TRIMD]         = 0x027c,
 254 };
 255
 256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 257         SH_ETH_OFFSET_DEFAULTS,
 258
 259         [ECMR]          = 0x0100,
 260         [RFLR]          = 0x0108,
 261         [ECSR]          = 0x0110,
 262         [ECSIPR]        = 0x0118,
 263         [PIR]           = 0x0120,
 264         [PSR]           = 0x0128,
 265         [RDMLR]         = 0x0140,
 266         [IPGR]          = 0x0150,
 267         [APR]           = 0x0154,
 268         [MPR]           = 0x0158,
 269         [TPAUSER]       = 0x0164,
 270         [RFCF]          = 0x0160,
 271         [TPAUSECR]      = 0x0168,
 272         [BCFRR]         = 0x016c,
 273         [MAHR]          = 0x01c0,
 274         [MALR]          = 0x01c8,
 275         [TROCR]         = 0x01d0,
 276         [CDCR]          = 0x01d4,
 277         [LCCR]          = 0x01d8,
 278         [CNDCR]         = 0x01dc,
 279         [CEFCR]         = 0x01e4,
 280         [FRECR]         = 0x01e8,
 281         [TSFRCR]        = 0x01ec,
 282         [TLFRCR]        = 0x01f0,
 283         [RFCR]          = 0x01f4,
 284         [MAFCR]         = 0x01f8,
 285         [RTRATE]        = 0x01fc,
 286
 287         [EDMR]          = 0x0000,
 288         [EDTRR]         = 0x0008,
 289         [EDRRR]         = 0x0010,
 290         [TDLAR]         = 0x0018,
 291         [RDLAR]         = 0x0020,
 292         [EESR]          = 0x0028,
 293         [EESIPR]        = 0x0030,
 294         [TRSCER]        = 0x0038,
 295         [RMFCR]         = 0x0040,
 296         [TFTR]          = 0x0048,
 297         [FDR]           = 0x0050,
 298         [RMCR]          = 0x0058,
 299         [TFUCR]         = 0x0064,
 300         [RFOCR]         = 0x0068,
 301         [FCFTR]         = 0x0070,
 302         [RPADIR]        = 0x0078,
 303         [TRIMD]         = 0x007c,
 304         [RBWAR]         = 0x00c8,
 305         [RDFAR]         = 0x00cc,
 306         [TBRAR]         = 0x00d4,
 307         [TDFAR]         = 0x00d8,
 308 };
 309
 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 311         SH_ETH_OFFSET_DEFAULTS,
 312
 313         [EDMR]          = 0x0000,
 314         [EDTRR]         = 0x0004,
 315         [EDRRR]         = 0x0008,
 316         [TDLAR]         = 0x000c,
 317         [RDLAR]         = 0x0010,
 318         [EESR]          = 0x0014,
 319         [EESIPR]        = 0x0018,
 320         [TRSCER]        = 0x001c,
 321         [RMFCR]         = 0x0020,
 322         [TFTR]          = 0x0024,
 323         [FDR]           = 0x0028,
 324         [RMCR]          = 0x002c,
 325         [EDOCR]         = 0x0030,
 326         [FCFTR]         = 0x0034,
 327         [RPADIR]        = 0x0038,
 328         [TRIMD]         = 0x003c,
 329         [RBWAR]         = 0x0040,
 330         [RDFAR]         = 0x0044,
 331         [TBRAR]         = 0x004c,
 332         [TDFAR]         = 0x0050,
 333
 334         [ECMR]          = 0x0160,
 335         [ECSR]          = 0x0164,
 336         [ECSIPR]        = 0x0168,
 337         [PIR]           = 0x016c,
 338         [MAHR]          = 0x0170,
 339         [MALR]          = 0x0174,
 340         [RFLR]          = 0x0178,
 341         [PSR]           = 0x017c,
 342         [TROCR]         = 0x0180,
 343         [CDCR]          = 0x0184,
 344         [LCCR]          = 0x0188,
 345         [CNDCR]         = 0x018c,
 346         [CEFCR]         = 0x0194,
 347         [FRECR]         = 0x0198,
 348         [TSFRCR]        = 0x019c,
 349         [TLFRCR]        = 0x01a0,
 350         [RFCR]          = 0x01a4,
 351         [MAFCR]         = 0x01a8,
 352         [IPGR]          = 0x01b4,
 353         [APR]           = 0x01b8,
 354         [MPR]           = 0x01bc,
 355         [TPAUSER]       = 0x01c4,
 356         [BCFR]          = 0x01cc,
 357
 358         [ARSTR]         = 0x0000,
 359         [TSU_CTRST]     = 0x0004,
 360         [TSU_FWEN0]     = 0x0010,
 361         [TSU_FWEN1]     = 0x0014,
 362         [TSU_FCM]       = 0x0018,
 363         [TSU_BSYSL0]    = 0x0020,
 364         [TSU_BSYSL1]    = 0x0024,
 365         [TSU_PRISL0]    = 0x0028,
 366         [TSU_PRISL1]    = 0x002c,
 367         [TSU_FWSL0]     = 0x0030,
 368         [TSU_FWSL1]     = 0x0034,
 369         [TSU_FWSLC]     = 0x0038,
 370         [TSU_QTAGM0]    = 0x0040,
 371         [TSU_QTAGM1]    = 0x0044,
 372         [TSU_ADQT0]     = 0x0048,
 373         [TSU_ADQT1]     = 0x004c,
 374         [TSU_FWSR]      = 0x0050,
 375         [TSU_FWINMK]    = 0x0054,
 376         [TSU_ADSBSY]    = 0x0060,
 377         [TSU_TEN]       = 0x0064,
 378         [TSU_POST1]     = 0x0070,
 379         [TSU_POST2]     = 0x0074,
 380         [TSU_POST3]     = 0x0078,
 381         [TSU_POST4]     = 0x007c,
 382
 383         [TXNLCR0]       = 0x0080,
 384         [TXALCR0]       = 0x0084,
 385         [RXNLCR0]       = 0x0088,
 386         [RXALCR0]       = 0x008c,
 387         [FWNLCR0]       = 0x0090,
 388         [FWALCR0]       = 0x0094,
 389         [TXNLCR1]       = 0x00a0,
 390         [TXALCR1]       = 0x00a4,
 391         [RXNLCR1]       = 0x00a8,
 392         [RXALCR1]       = 0x00ac,
 393         [FWNLCR1]       = 0x00b0,
 394         [FWALCR1]       = 0x00b4,
 395
 396         [TSU_ADRH0]     = 0x0100,
 397 };
 398
 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 401
 402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 403 {
 404         struct sh_eth_private *mdp = netdev_priv(ndev);
 405         u16 offset = mdp->reg_offset[enum_index];
 406
 407         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 408                 return;
 409
 410         iowrite32(data, mdp->addr + offset);
 411 }
 412
 413 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 414 {
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416         u16 offset = mdp->reg_offset[enum_index];
 417
 418         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 419                 return ~0U;
 420
 421         return ioread32(mdp->addr + offset);
 422 }
 423
 424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 425                           u32 set)
 426 {
 427         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 428                      enum_index);
 429 }
 430
 431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
 432 {
 433         return mdp->reg_offset[enum_index];
 434 }
 435
 436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
 437                              int enum_index)
 438 {
 439         u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
 440
 441         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 442                 return;
 443
 444         iowrite32(data, mdp->tsu_addr + offset);
 445 }
 446
 447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
 448 {
 449         u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
 450
 451         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 452                 return ~0U;
 453
 454         return ioread32(mdp->tsu_addr + offset);
 455 }
 456
 457 static void sh_eth_soft_swap(char *src, int len)
 458 {
 459 #ifdef __LITTLE_ENDIAN
 460         u32 *p = (u32 *)src;
 461         u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
 462
 463         for (; p < maxp; p++)
 464                 *p = swab32(*p);
 465 #endif
 466 }
 467
 468 static void sh_eth_select_mii(struct net_device *ndev)
 469 {
 470         struct sh_eth_private *mdp = netdev_priv(ndev);
 471         u32 value;
 472
 473         switch (mdp->phy_interface) {
 474         case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
 475                 value = 0x3;
 476                 break;
 477         case PHY_INTERFACE_MODE_GMII:
 478                 value = 0x2;
 479                 break;
 480         case PHY_INTERFACE_MODE_MII:
 481                 value = 0x1;
 482                 break;
 483         case PHY_INTERFACE_MODE_RMII:
 484                 value = 0x0;
 485                 break;
 486         default:
 487                 netdev_warn(ndev,
 488                             "PHY interface mode was not setup. Set to MII.\n");
 489                 value = 0x1;
 490                 break;
 491         }
 492
 493         sh_eth_write(ndev, value, RMII_MII);
 494 }
 495
 496 static void sh_eth_set_duplex(struct net_device *ndev)
 497 {
 498         struct sh_eth_private *mdp = netdev_priv(ndev);
 499
 500         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 501 }
 502
 503 static void sh_eth_chip_reset(struct net_device *ndev)
 504 {
 505         struct sh_eth_private *mdp = netdev_priv(ndev);
 506
 507         /* reset device */
 508         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 509         mdelay(1);
 510 }
 511
 512 static int sh_eth_soft_reset(struct net_device *ndev)
 513 {
 514         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 515         mdelay(3);
 516         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 517
 518         return 0;
 519 }
 520
 521 static int sh_eth_check_soft_reset(struct net_device *ndev)
 522 {
 523         int cnt;
 524
 525         for (cnt = 100; cnt > 0; cnt--) {
 526                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 527                         return 0;
 528                 mdelay(1);
 529         }
 530
 531         netdev_err(ndev, "Device reset failed\n");
 532         return -ETIMEDOUT;
 533 }
 534
 535 static int sh_eth_soft_reset_gether(struct net_device *ndev)
 536 {
 537         struct sh_eth_private *mdp = netdev_priv(ndev);
 538         int ret;
 539
 540         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 541         sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 542
 543         ret = sh_eth_check_soft_reset(ndev);
 544         if (ret)
 545                 return ret;
 546
 547         /* Table Init */
 548         sh_eth_write(ndev, 0, TDLAR);
 549         sh_eth_write(ndev, 0, TDFAR);
 550         sh_eth_write(ndev, 0, TDFXR);
 551         sh_eth_write(ndev, 0, TDFFR);
 552         sh_eth_write(ndev, 0, RDLAR);
 553         sh_eth_write(ndev, 0, RDFAR);
 554         sh_eth_write(ndev, 0, RDFXR);
 555         sh_eth_write(ndev, 0, RDFFR);
 556
 557         /* Reset HW CRC register */
 558         if (mdp->cd->hw_checksum)
 559                 sh_eth_write(ndev, 0, CSMR);
 560
 561         /* Select MII mode */
 562         if (mdp->cd->select_mii)
 563                 sh_eth_select_mii(ndev);
 564
 565         return ret;
 566 }
 567
 568 static void sh_eth_set_rate_gether(struct net_device *ndev)
 569 {
 570         struct sh_eth_private *mdp = netdev_priv(ndev);
 571
 572         switch (mdp->speed) {
 573         case 10: /* 10BASE */
 574                 sh_eth_write(ndev, GECMR_10, GECMR);
 575                 break;
 576         case 100:/* 100BASE */
 577                 sh_eth_write(ndev, GECMR_100, GECMR);
 578                 break;
 579         case 1000: /* 1000BASE */
 580                 sh_eth_write(ndev, GECMR_1000, GECMR);
 581                 break;
 582         }
 583 }
 584
 585 #ifdef CONFIG_OF
 586 /* R7S72100 */
 587 static struct sh_eth_cpu_data r7s72100_data = {
 588         .soft_reset     = sh_eth_soft_reset_gether,
 589
 590         .chip_reset     = sh_eth_chip_reset,
 591         .set_duplex     = sh_eth_set_duplex,
 592
 593         .register_type  = SH_ETH_REG_FAST_RZ,
 594
 595         .edtrr_trns     = EDTRR_TRNS_GETHER,
 596         .ecsr_value     = ECSR_ICD,
 597         .ecsipr_value   = ECSIPR_ICDIP,
 598         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 599                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 600                           EESIPR_ECIIP |
 601                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 602                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 603                           EESIPR_RMAFIP | EESIPR_RRFIP |
 604                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 605                           EESIPR_PREIP | EESIPR_CERFIP,
 606
 607         .tx_check       = EESR_TC1 | EESR_FTC,
 608         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 609                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 610                           EESR_TDE,
 611         .fdr_value      = 0x0000070f,
 612
 613         .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
 614
 615         .no_psr         = 1,
 616         .apr            = 1,
 617         .mpr            = 1,
 618         .tpauser        = 1,
 619         .hw_swap        = 1,
 620         .rpadir         = 1,
 621         .no_trimd       = 1,
 622         .no_ade         = 1,
 623         .xdfar_rw       = 1,
 624         .hw_checksum    = 1,
 625         .tsu            = 1,
 626         .no_tx_cntrs    = 1,
 627 };
 628
 629 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 630 {
 631         sh_eth_chip_reset(ndev);
 632
 633         sh_eth_select_mii(ndev);
 634 }
 635
 636 /* R8A7740 */
 637 static struct sh_eth_cpu_data r8a7740_data = {
 638         .soft_reset     = sh_eth_soft_reset_gether,
 639
 640         .chip_reset     = sh_eth_chip_reset_r8a7740,
 641         .set_duplex     = sh_eth_set_duplex,
 642         .set_rate       = sh_eth_set_rate_gether,
 643
 644         .register_type  = SH_ETH_REG_GIGABIT,
 645
 646         .edtrr_trns     = EDTRR_TRNS_GETHER,
 647         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 648         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 649         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 650                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 651                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 652                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 653                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 654                           EESIPR_CEEFIP | EESIPR_CELFIP |
 655                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 656                           EESIPR_PREIP | EESIPR_CERFIP,
 657
 658         .tx_check       = EESR_TC1 | EESR_FTC,
 659         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 660                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 661                           EESR_TDE,
 662         .fdr_value      = 0x0000070f,
 663
 664         .apr            = 1,
 665         .mpr            = 1,
 666         .tpauser        = 1,
 667         .bculr          = 1,
 668         .hw_swap        = 1,
 669         .rpadir         = 1,
 670         .no_trimd       = 1,
 671         .no_ade         = 1,
 672         .xdfar_rw       = 1,
 673         .hw_checksum    = 1,
 674         .tsu            = 1,
 675         .select_mii     = 1,
 676         .magic          = 1,
 677         .cexcr          = 1,
 678 };
 679
 680 /* There is CPU dependent code */
 681 static void sh_eth_set_rate_rcar(struct net_device *ndev)
 682 {
 683         struct sh_eth_private *mdp = netdev_priv(ndev);
 684
 685         switch (mdp->speed) {
 686         case 10: /* 10BASE */
 687                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 688                 break;
 689         case 100:/* 100BASE */
 690                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 691                 break;
 692         }
 693 }
 694
 695 /* R-Car Gen1 */
 696 static struct sh_eth_cpu_data rcar_gen1_data = {
 697         .soft_reset     = sh_eth_soft_reset,
 698
 699         .set_duplex     = sh_eth_set_duplex,
 700         .set_rate       = sh_eth_set_rate_rcar,
 701
 702         .register_type  = SH_ETH_REG_FAST_RCAR,
 703
 704         .edtrr_trns     = EDTRR_TRNS_ETHER,
 705         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 706         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 707         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 708                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 709                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 710                           EESIPR_RMAFIP | EESIPR_RRFIP |
 711                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 712                           EESIPR_PREIP | EESIPR_CERFIP,
 713
 714         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 715         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 716                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 717         .fdr_value      = 0x00000f0f,
 718
 719         .apr            = 1,
 720         .mpr            = 1,
 721         .tpauser        = 1,
 722         .hw_swap        = 1,
 723         .no_xdfar       = 1,
 724 };
 725
 726 /* R-Car Gen2 and RZ/G1 */
 727 static struct sh_eth_cpu_data rcar_gen2_data = {
 728         .soft_reset     = sh_eth_soft_reset,
 729
 730         .set_duplex     = sh_eth_set_duplex,
 731         .set_rate       = sh_eth_set_rate_rcar,
 732
 733         .register_type  = SH_ETH_REG_FAST_RCAR,
 734
 735         .edtrr_trns     = EDTRR_TRNS_ETHER,
 736         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 737         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 738                           ECSIPR_MPDIP,
 739         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 740                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 741                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 742                           EESIPR_RMAFIP | EESIPR_RRFIP |
 743                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 744                           EESIPR_PREIP | EESIPR_CERFIP,
 745
 746         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 747         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 748                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 749         .fdr_value      = 0x00000f0f,
 750
 751         .trscer_err_mask = DESC_I_RINT8,
 752
 753         .apr            = 1,
 754         .mpr            = 1,
 755         .tpauser        = 1,
 756         .hw_swap        = 1,
 757         .no_xdfar       = 1,
 758         .rmiimode       = 1,
 759         .magic          = 1,
 760 };
 761
 762 /* R8A77980 */
 763 static struct sh_eth_cpu_data r8a77980_data = {
 764         .soft_reset     = sh_eth_soft_reset_gether,
 765
 766         .set_duplex     = sh_eth_set_duplex,
 767         .set_rate       = sh_eth_set_rate_gether,
 768
 769         .register_type  = SH_ETH_REG_GIGABIT,
 770
 771         .edtrr_trns     = EDTRR_TRNS_GETHER,
 772         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 773         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 774                           ECSIPR_MPDIP,
 775         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 776                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 777                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 778                           EESIPR_RMAFIP | EESIPR_RRFIP |
 779                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 780                           EESIPR_PREIP | EESIPR_CERFIP,
 781
 782         .tx_check       = EESR_FTC | EESR_CD | EESR_TRO,
 783         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 784                           EESR_RFE | EESR_RDE | EESR_RFRMER |
 785                           EESR_TFE | EESR_TDE | EESR_ECI,
 786         .fdr_value      = 0x0000070f,
 787
 788         .apr            = 1,
 789         .mpr            = 1,
 790         .tpauser        = 1,
 791         .bculr          = 1,
 792         .hw_swap        = 1,
 793         .nbst           = 1,
 794         .rpadir         = 1,
 795         .no_trimd       = 1,
 796         .no_ade         = 1,
 797         .xdfar_rw       = 1,
 798         .hw_checksum    = 1,
 799         .select_mii     = 1,
 800         .magic          = 1,
 801         .cexcr          = 1,
 802 };
 803
 804 /* R7S9210 */
 805 static struct sh_eth_cpu_data r7s9210_data = {
 806         .soft_reset     = sh_eth_soft_reset,
 807
 808         .set_duplex     = sh_eth_set_duplex,
 809         .set_rate       = sh_eth_set_rate_rcar,
 810
 811         .register_type  = SH_ETH_REG_FAST_SH4,
 812
 813         .edtrr_trns     = EDTRR_TRNS_ETHER,
 814         .ecsr_value     = ECSR_ICD,
 815         .ecsipr_value   = ECSIPR_ICDIP,
 816         .eesipr_value   = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
 817                           EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
 818                           EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
 819                           EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
 820                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 821                           EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
 822                           EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
 823
 824         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 825         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 826                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 827
 828         .fdr_value      = 0x0000070f,
 829
 830         .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
 831
 832         .apr            = 1,
 833         .mpr            = 1,
 834         .tpauser        = 1,
 835         .hw_swap        = 1,
 836         .rpadir         = 1,
 837         .no_ade         = 1,
 838         .xdfar_rw       = 1,
 839 };
 840 #endif /* CONFIG_OF */
 841
 842 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 843 {
 844         struct sh_eth_private *mdp = netdev_priv(ndev);
 845
 846         switch (mdp->speed) {
 847         case 10: /* 10BASE */
 848                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 849                 break;
 850         case 100:/* 100BASE */
 851                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 852                 break;
 853         }
 854 }
 855
 856 /* SH7724 */
 857 static struct sh_eth_cpu_data sh7724_data = {
 858         .soft_reset     = sh_eth_soft_reset,
 859
 860         .set_duplex     = sh_eth_set_duplex,
 861         .set_rate       = sh_eth_set_rate_sh7724,
 862
 863         .register_type  = SH_ETH_REG_FAST_SH4,
 864
 865         .edtrr_trns     = EDTRR_TRNS_ETHER,
 866         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 867         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 868         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 869                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 870                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 871                           EESIPR_RMAFIP | EESIPR_RRFIP |
 872                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 873                           EESIPR_PREIP | EESIPR_CERFIP,
 874
 875         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 876         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 877                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 878
 879         .apr            = 1,
 880         .mpr            = 1,
 881         .tpauser        = 1,
 882         .hw_swap        = 1,
 883         .rpadir         = 1,
 884 };
 885
 886 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 887 {
 888         struct sh_eth_private *mdp = netdev_priv(ndev);
 889
 890         switch (mdp->speed) {
 891         case 10: /* 10BASE */
 892                 sh_eth_write(ndev, 0, RTRATE);
 893                 break;
 894         case 100:/* 100BASE */
 895                 sh_eth_write(ndev, 1, RTRATE);
 896                 break;
 897         }
 898 }
 899
 900 /* SH7757 */
 901 static struct sh_eth_cpu_data sh7757_data = {
 902         .soft_reset     = sh_eth_soft_reset,
 903
 904         .set_duplex     = sh_eth_set_duplex,
 905         .set_rate       = sh_eth_set_rate_sh7757,
 906
 907         .register_type  = SH_ETH_REG_FAST_SH4,
 908
 909         .edtrr_trns     = EDTRR_TRNS_ETHER,
 910         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 911                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 912                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 913                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 914                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 915                           EESIPR_CEEFIP | EESIPR_CELFIP |
 916                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 917                           EESIPR_PREIP | EESIPR_CERFIP,
 918
 919         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 920         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 921                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 922
 923         .irq_flags      = IRQF_SHARED,
 924         .apr            = 1,
 925         .mpr            = 1,
 926         .tpauser        = 1,
 927         .hw_swap        = 1,
 928         .no_ade         = 1,
 929         .rpadir         = 1,
 930         .rtrate         = 1,
 931         .dual_port      = 1,
 932 };
 933
 934 #define SH_GIGA_ETH_BASE        0xfee00000UL
 935 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 936 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 937 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 938 {
 939         u32 mahr[2], malr[2];
 940         int i;
 941
 942         /* save MAHR and MALR */
 943         for (i = 0; i < 2; i++) {
 944                 malr[i] = ioread32((void *)GIGA_MALR(i));
 945                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 946         }
 947
 948         sh_eth_chip_reset(ndev);
 949
 950         /* restore MAHR and MALR */
 951         for (i = 0; i < 2; i++) {
 952                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 953                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 954         }
 955 }
 956
 957 static void sh_eth_set_rate_giga(struct net_device *ndev)
 958 {
 959         struct sh_eth_private *mdp = netdev_priv(ndev);
 960
 961         switch (mdp->speed) {
 962         case 10: /* 10BASE */
 963                 sh_eth_write(ndev, 0x00000000, GECMR);
 964                 break;
 965         case 100:/* 100BASE */
 966                 sh_eth_write(ndev, 0x00000010, GECMR);
 967                 break;
 968         case 1000: /* 1000BASE */
 969                 sh_eth_write(ndev, 0x00000020, GECMR);
 970                 break;
 971         }
 972 }
 973
 974 /* SH7757(GETHERC) */
 975 static struct sh_eth_cpu_data sh7757_data_giga = {
 976         .soft_reset     = sh_eth_soft_reset_gether,
 977
 978         .chip_reset     = sh_eth_chip_reset_giga,
 979         .set_duplex     = sh_eth_set_duplex,
 980         .set_rate       = sh_eth_set_rate_giga,
 981
 982         .register_type  = SH_ETH_REG_GIGABIT,
 983
 984         .edtrr_trns     = EDTRR_TRNS_GETHER,
 985         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 986         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 987         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 988                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 989                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 990                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 991                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 992                           EESIPR_CEEFIP | EESIPR_CELFIP |
 993                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 994                           EESIPR_PREIP | EESIPR_CERFIP,
 995
 996         .tx_check       = EESR_TC1 | EESR_FTC,
 997         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 998                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 999                           EESR_TDE,
1000         .fdr_value      = 0x0000072f,
1001
1002         .irq_flags      = IRQF_SHARED,
1003         .apr            = 1,
1004         .mpr            = 1,
1005         .tpauser        = 1,
1006         .bculr          = 1,
1007         .hw_swap        = 1,
1008         .rpadir         = 1,
1009         .no_trimd       = 1,
1010         .no_ade         = 1,
1011         .xdfar_rw       = 1,
1012         .tsu            = 1,
1013         .cexcr          = 1,
1014         .dual_port      = 1,
1015 };
1016
1017 /* SH7734 */
1018 static struct sh_eth_cpu_data sh7734_data = {
1019         .soft_reset     = sh_eth_soft_reset_gether,
1020
1021         .chip_reset     = sh_eth_chip_reset,
1022         .set_duplex     = sh_eth_set_duplex,
1023         .set_rate       = sh_eth_set_rate_gether,
1024
1025         .register_type  = SH_ETH_REG_GIGABIT,
1026
1027         .edtrr_trns     = EDTRR_TRNS_GETHER,
1028         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1029         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1030         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1031                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1032                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1033                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1034                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1035                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1036                           EESIPR_PREIP | EESIPR_CERFIP,
1037
1038         .tx_check       = EESR_TC1 | EESR_FTC,
1039         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1040                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1041                           EESR_TDE,
1042
1043         .apr            = 1,
1044         .mpr            = 1,
1045         .tpauser        = 1,
1046         .bculr          = 1,
1047         .hw_swap        = 1,
1048         .no_trimd       = 1,
1049         .no_ade         = 1,
1050         .xdfar_rw       = 1,
1051         .tsu            = 1,
1052         .hw_checksum    = 1,
1053         .select_mii     = 1,
1054         .magic          = 1,
1055         .cexcr          = 1,
1056 };
1057
1058 /* SH7763 */
1059 static struct sh_eth_cpu_data sh7763_data = {
1060         .soft_reset     = sh_eth_soft_reset_gether,
1061
1062         .chip_reset     = sh_eth_chip_reset,
1063         .set_duplex     = sh_eth_set_duplex,
1064         .set_rate       = sh_eth_set_rate_gether,
1065
1066         .register_type  = SH_ETH_REG_GIGABIT,
1067
1068         .edtrr_trns     = EDTRR_TRNS_GETHER,
1069         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1070         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1071         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1075                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1076                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1077                           EESIPR_PREIP | EESIPR_CERFIP,
1078
1079         .tx_check       = EESR_TC1 | EESR_FTC,
1080         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1081                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1082
1083         .apr            = 1,
1084         .mpr            = 1,
1085         .tpauser        = 1,
1086         .bculr          = 1,
1087         .hw_swap        = 1,
1088         .no_trimd       = 1,
1089         .no_ade         = 1,
1090         .xdfar_rw       = 1,
1091         .tsu            = 1,
1092         .irq_flags      = IRQF_SHARED,
1093         .magic          = 1,
1094         .cexcr          = 1,
1095         .dual_port      = 1,
1096 };
1097
1098 static struct sh_eth_cpu_data sh7619_data = {
1099         .soft_reset     = sh_eth_soft_reset,
1100
1101         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1102
1103         .edtrr_trns     = EDTRR_TRNS_ETHER,
1104         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1105                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1106                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1107                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1108                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1109                           EESIPR_CEEFIP | EESIPR_CELFIP |
1110                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1111                           EESIPR_PREIP | EESIPR_CERFIP,
1112
1113         .apr            = 1,
1114         .mpr            = 1,
1115         .tpauser        = 1,
1116         .hw_swap        = 1,
1117 };
1118
1119 static struct sh_eth_cpu_data sh771x_data = {
1120         .soft_reset     = sh_eth_soft_reset,
1121
1122         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1123
1124         .edtrr_trns     = EDTRR_TRNS_ETHER,
1125         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1126                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1127                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1128                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1129                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1130                           EESIPR_CEEFIP | EESIPR_CELFIP |
1131                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1132                           EESIPR_PREIP | EESIPR_CERFIP,
1133
1134         .trscer_err_mask = DESC_I_RINT8,
1135
1136         .tsu            = 1,
1137         .dual_port      = 1,
1138 };
1139
1140 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1141 {
1142         if (!cd->ecsr_value)
1143                 cd->ecsr_value = DEFAULT_ECSR_INIT;
1144
1145         if (!cd->ecsipr_value)
1146                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1147
1148         if (!cd->fcftr_value)
1149                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1150                                   DEFAULT_FIFO_F_D_RFD;
1151
1152         if (!cd->fdr_value)
1153                 cd->fdr_value = DEFAULT_FDR_INIT;
1154
1155         if (!cd->tx_check)
1156                 cd->tx_check = DEFAULT_TX_CHECK;
1157
1158         if (!cd->eesr_err_check)
1159                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1160
1161         if (!cd->trscer_err_mask)
1162                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1163 }
1164
1165 static void sh_eth_set_receive_align(struct sk_buff *skb)
1166 {
1167         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1168
1169         if (reserve)
1170                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1171 }
1172
1173 /* Program the hardware MAC address from dev->dev_addr. */
1174 static void update_mac_address(struct net_device *ndev)
1175 {
1176         sh_eth_write(ndev,
1177                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1178                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1179         sh_eth_write(ndev,
1180                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1181 }
1182
1183 /* Get MAC address from SuperH MAC address register
1184  *
1185  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1186  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1187  * When you want use this device, you must set MAC address in bootloader.
1188  *
1189  */
1190 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1191 {
1192         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1193                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1194         } else {
1195                 u32 mahr = sh_eth_read(ndev, MAHR);
1196                 u32 malr = sh_eth_read(ndev, MALR);
1197
1198                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1199                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1200                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1201                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1202                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1203                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1204         }
1205 }
1206
1207 struct bb_info {
1208         void (*set_gate)(void *addr);
1209         struct mdiobb_ctrl ctrl;
1210         void *addr;
1211 };
1212
1213 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1214 {
1215         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1216         u32 pir;
1217
1218         if (bitbang->set_gate)
1219                 bitbang->set_gate(bitbang->addr);
1220
1221         pir = ioread32(bitbang->addr);
1222         if (set)
1223                 pir |=  mask;
1224         else
1225                 pir &= ~mask;
1226         iowrite32(pir, bitbang->addr);
1227 }
1228
1229 /* Data I/O pin control */
1230 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1231 {
1232         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1233 }
1234
1235 /* Set bit data*/
1236 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1237 {
1238         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1239 }
1240
1241 /* Get bit data*/
1242 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1243 {
1244         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1245
1246         if (bitbang->set_gate)
1247                 bitbang->set_gate(bitbang->addr);
1248
1249         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1250 }
1251
1252 /* MDC pin control */
1253 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1254 {
1255         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1256 }
1257
1258 /* mdio bus control struct */
1259 static struct mdiobb_ops bb_ops = {
1260         .owner = THIS_MODULE,
1261         .set_mdc = sh_mdc_ctrl,
1262         .set_mdio_dir = sh_mmd_ctrl,
1263         .set_mdio_data = sh_set_mdio,
1264         .get_mdio_data = sh_get_mdio,
1265 };
1266
1267 /* free Tx skb function */
1268 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1269 {
1270         struct sh_eth_private *mdp = netdev_priv(ndev);
1271         struct sh_eth_txdesc *txdesc;
1272         int free_num = 0;
1273         int entry;
1274         bool sent;
1275
1276         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1277                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1278                 txdesc = &mdp->tx_ring[entry];
1279                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1280                 if (sent_only && !sent)
1281                         break;
1282                 /* TACT bit must be checked before all the following reads */
1283                 dma_rmb();
1284                 netif_info(mdp, tx_done, ndev,
1285                            "tx entry %d status 0x%08x\n",
1286                            entry, le32_to_cpu(txdesc->status));
1287                 /* Free the original skb. */
1288                 if (mdp->tx_skbuff[entry]) {
1289                         dma_unmap_single(&mdp->pdev->dev,
1290                                          le32_to_cpu(txdesc->addr),
1291                                          le32_to_cpu(txdesc->len) >> 16,
1292                                          DMA_TO_DEVICE);
1293                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1294                         mdp->tx_skbuff[entry] = NULL;
1295                         free_num++;
1296                 }
1297                 txdesc->status = cpu_to_le32(TD_TFP);
1298                 if (entry >= mdp->num_tx_ring - 1)
1299                         txdesc->status |= cpu_to_le32(TD_TDLE);
1300
1301                 if (sent) {
1302                         ndev->stats.tx_packets++;
1303                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1304                 }
1305         }
1306         return free_num;
1307 }
1308
1309 /* free skb and descriptor buffer */
1310 static void sh_eth_ring_free(struct net_device *ndev)
1311 {
1312         struct sh_eth_private *mdp = netdev_priv(ndev);
1313         int ringsize, i;
1314
1315         if (mdp->rx_ring) {
1316                 for (i = 0; i < mdp->num_rx_ring; i++) {
1317                         if (mdp->rx_skbuff[i]) {
1318                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1319
1320                                 dma_unmap_single(&mdp->pdev->dev,
1321                                                  le32_to_cpu(rxdesc->addr),
1322                                                  ALIGN(mdp->rx_buf_sz, 32),
1323                                                  DMA_FROM_DEVICE);
1324                         }
1325                 }
1326                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1327                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1328                                   mdp->rx_desc_dma);
1329                 mdp->rx_ring = NULL;
1330         }
1331
1332         /* Free Rx skb ringbuffer */
1333         if (mdp->rx_skbuff) {
1334                 for (i = 0; i < mdp->num_rx_ring; i++)
1335                         dev_kfree_skb(mdp->rx_skbuff[i]);
1336         }
1337         kfree(mdp->rx_skbuff);
1338         mdp->rx_skbuff = NULL;
1339
1340         if (mdp->tx_ring) {
1341                 sh_eth_tx_free(ndev, false);
1342
1343                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1344                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1345                                   mdp->tx_desc_dma);
1346                 mdp->tx_ring = NULL;
1347         }
1348
1349         /* Free Tx skb ringbuffer */
1350         kfree(mdp->tx_skbuff);
1351         mdp->tx_skbuff = NULL;
1352 }
1353
1354 /* format skb and descriptor buffer */
1355 static void sh_eth_ring_format(struct net_device *ndev)
1356 {
1357         struct sh_eth_private *mdp = netdev_priv(ndev);
1358         int i;
1359         struct sk_buff *skb;
1360         struct sh_eth_rxdesc *rxdesc = NULL;
1361         struct sh_eth_txdesc *txdesc = NULL;
1362         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1363         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1364         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1365         dma_addr_t dma_addr;
1366         u32 buf_len;
1367
1368         mdp->cur_rx = 0;
1369         mdp->cur_tx = 0;
1370         mdp->dirty_rx = 0;
1371         mdp->dirty_tx = 0;
1372
1373         memset(mdp->rx_ring, 0, rx_ringsize);
1374
1375         /* build Rx ring buffer */
1376         for (i = 0; i < mdp->num_rx_ring; i++) {
1377                 /* skb */
1378                 mdp->rx_skbuff[i] = NULL;
1379                 skb = netdev_alloc_skb(ndev, skbuff_size);
1380                 if (skb == NULL)
1381                         break;
1382                 sh_eth_set_receive_align(skb);
1383
1384                 /* The size of the buffer is a multiple of 32 bytes. */
1385                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1386                 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1387                                           DMA_FROM_DEVICE);
1388                 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1389                         kfree_skb(skb);
1390                         break;
1391                 }
1392                 mdp->rx_skbuff[i] = skb;
1393
1394                 /* RX descriptor */
1395                 rxdesc = &mdp->rx_ring[i];
1396                 rxdesc->len = cpu_to_le32(buf_len << 16);
1397                 rxdesc->addr = cpu_to_le32(dma_addr);
1398                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1399
1400                 /* Rx descriptor address set */
1401                 if (i == 0) {
1402                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1403                         if (mdp->cd->xdfar_rw)
1404                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1405                 }
1406         }
1407
1408         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1409
1410         /* Mark the last entry as wrapping the ring. */
1411         if (rxdesc)
1412                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1413
1414         memset(mdp->tx_ring, 0, tx_ringsize);
1415
1416         /* build Tx ring buffer */
1417         for (i = 0; i < mdp->num_tx_ring; i++) {
1418                 mdp->tx_skbuff[i] = NULL;
1419                 txdesc = &mdp->tx_ring[i];
1420                 txdesc->status = cpu_to_le32(TD_TFP);
1421                 txdesc->len = cpu_to_le32(0);
1422                 if (i == 0) {
1423                         /* Tx descriptor address set */
1424                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1425                         if (mdp->cd->xdfar_rw)
1426                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1427                 }
1428         }
1429
1430         txdesc->status |= cpu_to_le32(TD_TDLE);
1431 }
1432
1433 /* Get skb and descriptor buffer */
1434 static int sh_eth_ring_init(struct net_device *ndev)
1435 {
1436         struct sh_eth_private *mdp = netdev_priv(ndev);
1437         int rx_ringsize, tx_ringsize;
1438
1439         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1440          * card needs room to do 8 byte alignment, +2 so we can reserve
1441          * the first 2 bytes, and +16 gets room for the status word from the
1442          * card.
1443          */
1444         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1445                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1446         if (mdp->cd->rpadir)
1447                 mdp->rx_buf_sz += NET_IP_ALIGN;
1448
1449         /* Allocate RX and TX skb rings */
1450         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1451                                  GFP_KERNEL);
1452         if (!mdp->rx_skbuff)
1453                 return -ENOMEM;
1454
1455         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1456                                  GFP_KERNEL);
1457         if (!mdp->tx_skbuff)
1458                 goto ring_free;
1459
1460         /* Allocate all Rx descriptors. */
1461         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1462         mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1463                                           &mdp->rx_desc_dma, GFP_KERNEL);
1464         if (!mdp->rx_ring)
1465                 goto ring_free;
1466
1467         mdp->dirty_rx = 0;
1468
1469         /* Allocate all Tx descriptors. */
1470         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1471         mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1472                                           &mdp->tx_desc_dma, GFP_KERNEL);
1473         if (!mdp->tx_ring)
1474                 goto ring_free;
1475         return 0;
1476
1477 ring_free:
1478         /* Free Rx and Tx skb ring buffer and DMA buffer */
1479         sh_eth_ring_free(ndev);
1480
1481         return -ENOMEM;
1482 }
1483
1484 static int sh_eth_dev_init(struct net_device *ndev)
1485 {
1486         struct sh_eth_private *mdp = netdev_priv(ndev);
1487         int ret;
1488
1489         /* Soft Reset */
1490         ret = mdp->cd->soft_reset(ndev);
1491         if (ret)
1492                 return ret;
1493
1494         if (mdp->cd->rmiimode)
1495                 sh_eth_write(ndev, 0x1, RMIIMODE);
1496
1497         /* Descriptor format */
1498         sh_eth_ring_format(ndev);
1499         if (mdp->cd->rpadir)
1500                 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1501
1502         /* all sh_eth int mask */
1503         sh_eth_write(ndev, 0, EESIPR);
1504
1505 #if defined(__LITTLE_ENDIAN)
1506         if (mdp->cd->hw_swap)
1507                 sh_eth_write(ndev, EDMR_EL, EDMR);
1508         else
1509 #endif
1510                 sh_eth_write(ndev, 0, EDMR);
1511
1512         /* FIFO size set */
1513         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1514         sh_eth_write(ndev, 0, TFTR);
1515
1516         /* Frame recv control (enable multiple-packets per rx irq) */
1517         sh_eth_write(ndev, RMCR_RNC, RMCR);
1518
1519         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1520
1521         /* DMA transfer burst mode */
1522         if (mdp->cd->nbst)
1523                 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1524
1525         /* Burst cycle count upper-limit */
1526         if (mdp->cd->bculr)
1527                 sh_eth_write(ndev, 0x800, BCULR);
1528
1529         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1530
1531         if (!mdp->cd->no_trimd)
1532                 sh_eth_write(ndev, 0, TRIMD);
1533
1534         /* Recv frame limit set register */
1535         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1536                      RFLR);
1537
1538         sh_eth_modify(ndev, EESR, 0, 0);
1539         mdp->irq_enabled = true;
1540         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1541
1542         /* PAUSE Prohibition */
1543         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1544                      ECMR_TE | ECMR_RE, ECMR);
1545
1546         if (mdp->cd->set_rate)
1547                 mdp->cd->set_rate(ndev);
1548
1549         /* E-MAC Status Register clear */
1550         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1551
1552         /* E-MAC Interrupt Enable register */
1553         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1554
1555         /* Set MAC address */
1556         update_mac_address(ndev);
1557
1558         /* mask reset */
1559         if (mdp->cd->apr)
1560                 sh_eth_write(ndev, 1, APR);
1561         if (mdp->cd->mpr)
1562                 sh_eth_write(ndev, 1, MPR);
1563         if (mdp->cd->tpauser)
1564                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1565
1566         /* Setting the Rx mode will start the Rx process. */
1567         sh_eth_write(ndev, EDRRR_R, EDRRR);
1568
1569         return ret;
1570 }
1571
1572 static void sh_eth_dev_exit(struct net_device *ndev)
1573 {
1574         struct sh_eth_private *mdp = netdev_priv(ndev);
1575         int i;
1576
1577         /* Deactivate all TX descriptors, so DMA should stop at next
1578          * packet boundary if it's currently running
1579          */
1580         for (i = 0; i < mdp->num_tx_ring; i++)
1581                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1582
1583         /* Disable TX FIFO egress to MAC */
1584         sh_eth_rcv_snd_disable(ndev);
1585
1586         /* Stop RX DMA at next packet boundary */
1587         sh_eth_write(ndev, 0, EDRRR);
1588
1589         /* Aside from TX DMA, we can't tell when the hardware is
1590          * really stopped, so we need to reset to make sure.
1591          * Before doing that, wait for long enough to *probably*
1592          * finish transmitting the last packet and poll stats.
1593          */
1594         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1595         sh_eth_get_stats(ndev);
1596         mdp->cd->soft_reset(ndev);
1597
1598         /* Set the RMII mode again if required */
1599         if (mdp->cd->rmiimode)
1600                 sh_eth_write(ndev, 0x1, RMIIMODE);
1601
1602         /* Set MAC address again */
1603         update_mac_address(ndev);
1604 }
1605
1606 /* Packet receive function */
1607 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1608 {
1609         struct sh_eth_private *mdp = netdev_priv(ndev);
1610         struct sh_eth_rxdesc *rxdesc;
1611
1612         int entry = mdp->cur_rx % mdp->num_rx_ring;
1613         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1614         int limit;
1615         struct sk_buff *skb;
1616         u32 desc_status;
1617         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1618         dma_addr_t dma_addr;
1619         u16 pkt_len;
1620         u32 buf_len;
1621
1622         boguscnt = min(boguscnt, *quota);
1623         limit = boguscnt;
1624         rxdesc = &mdp->rx_ring[entry];
1625         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1626                 /* RACT bit must be checked before all the following reads */
1627                 dma_rmb();
1628                 desc_status = le32_to_cpu(rxdesc->status);
1629                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1630
1631                 if (--boguscnt < 0)
1632                         break;
1633
1634                 netif_info(mdp, rx_status, ndev,
1635                            "rx entry %d status 0x%08x len %d\n",
1636                            entry, desc_status, pkt_len);
1637
1638                 if (!(desc_status & RDFEND))
1639                         ndev->stats.rx_length_errors++;
1640
1641                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1642                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1643                  * bit 0. However, in case of the R8A7740 and R7S72100
1644                  * the RFS bits are from bit 25 to bit 16. So, the
1645                  * driver needs right shifting by 16.
1646                  */
1647                 if (mdp->cd->hw_checksum)
1648                         desc_status >>= 16;
1649
1650                 skb = mdp->rx_skbuff[entry];
1651                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1652                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1653                         ndev->stats.rx_errors++;
1654                         if (desc_status & RD_RFS1)
1655                                 ndev->stats.rx_crc_errors++;
1656                         if (desc_status & RD_RFS2)
1657                                 ndev->stats.rx_frame_errors++;
1658                         if (desc_status & RD_RFS3)
1659                                 ndev->stats.rx_length_errors++;
1660                         if (desc_status & RD_RFS4)
1661                                 ndev->stats.rx_length_errors++;
1662                         if (desc_status & RD_RFS6)
1663                                 ndev->stats.rx_missed_errors++;
1664                         if (desc_status & RD_RFS10)
1665                                 ndev->stats.rx_over_errors++;
1666                 } else  if (skb) {
1667                         dma_addr = le32_to_cpu(rxdesc->addr);
1668                         if (!mdp->cd->hw_swap)
1669                                 sh_eth_soft_swap(
1670                                         phys_to_virt(ALIGN(dma_addr, 4)),
1671                                         pkt_len + 2);
1672                         mdp->rx_skbuff[entry] = NULL;
1673                         if (mdp->cd->rpadir)
1674                                 skb_reserve(skb, NET_IP_ALIGN);
1675                         dma_unmap_single(&mdp->pdev->dev, dma_addr,
1676                                          ALIGN(mdp->rx_buf_sz, 32),
1677                                          DMA_FROM_DEVICE);
1678                         skb_put(skb, pkt_len);
1679                         skb->protocol = eth_type_trans(skb, ndev);
1680                         netif_receive_skb(skb);
1681                         ndev->stats.rx_packets++;
1682                         ndev->stats.rx_bytes += pkt_len;
1683                         if (desc_status & RD_RFS8)
1684                                 ndev->stats.multicast++;
1685                 }
1686                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1687                 rxdesc = &mdp->rx_ring[entry];
1688         }
1689
1690         /* Refill the Rx ring buffers. */
1691         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1692                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1693                 rxdesc = &mdp->rx_ring[entry];
1694                 /* The size of the buffer is 32 byte boundary. */
1695                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1696                 rxdesc->len = cpu_to_le32(buf_len << 16);
1697
1698                 if (mdp->rx_skbuff[entry] == NULL) {
1699                         skb = netdev_alloc_skb(ndev, skbuff_size);
1700                         if (skb == NULL)
1701                                 break;  /* Better luck next round. */
1702                         sh_eth_set_receive_align(skb);
1703                         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1704                                                   buf_len, DMA_FROM_DEVICE);
1705                         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1706                                 kfree_skb(skb);
1707                                 break;
1708                         }
1709                         mdp->rx_skbuff[entry] = skb;
1710
1711                         skb_checksum_none_assert(skb);
1712                         rxdesc->addr = cpu_to_le32(dma_addr);
1713                 }
1714                 dma_wmb(); /* RACT bit must be set after all the above writes */
1715                 if (entry >= mdp->num_rx_ring - 1)
1716                         rxdesc->status |=
1717                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1718                 else
1719                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1720         }
1721
1722         /* Restart Rx engine if stopped. */
1723         /* If we don't need to check status, don't. -KDU */
1724         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1725                 /* fix the values for the next receiving if RDE is set */
1726                 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1727                         u32 count = (sh_eth_read(ndev, RDFAR) -
1728                                      sh_eth_read(ndev, RDLAR)) >> 4;
1729
1730                         mdp->cur_rx = count;
1731                         mdp->dirty_rx = count;
1732                 }
1733                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1734         }
1735
1736         *quota -= limit - boguscnt - 1;
1737
1738         return *quota <= 0;
1739 }
1740
1741 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1742 {
1743         /* disable tx and rx */
1744         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1745 }
1746
1747 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1748 {
1749         /* enable tx and rx */
1750         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1751 }
1752
1753 /* E-MAC interrupt handler */
1754 static void sh_eth_emac_interrupt(struct net_device *ndev)
1755 {
1756         struct sh_eth_private *mdp = netdev_priv(ndev);
1757         u32 felic_stat;
1758         u32 link_stat;
1759
1760         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1761         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1762         if (felic_stat & ECSR_ICD)
1763                 ndev->stats.tx_carrier_errors++;
1764         if (felic_stat & ECSR_MPD)
1765                 pm_wakeup_event(&mdp->pdev->dev, 0);
1766         if (felic_stat & ECSR_LCHNG) {
1767                 /* Link Changed */
1768                 if (mdp->cd->no_psr || mdp->no_ether_link)
1769                         return;
1770                 link_stat = sh_eth_read(ndev, PSR);
1771                 if (mdp->ether_link_active_low)
1772                         link_stat = ~link_stat;
1773                 if (!(link_stat & PHY_ST_LINK)) {
1774                         sh_eth_rcv_snd_disable(ndev);
1775                 } else {
1776                         /* Link Up */
1777                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1778                         /* clear int */
1779                         sh_eth_modify(ndev, ECSR, 0, 0);
1780                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1781                         /* enable tx and rx */
1782                         sh_eth_rcv_snd_enable(ndev);
1783                 }
1784         }
1785 }
1786
1787 /* error control function */
1788 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1789 {
1790         struct sh_eth_private *mdp = netdev_priv(ndev);
1791         u32 mask;
1792
1793         if (intr_status & EESR_TWB) {
1794                 /* Unused write back interrupt */
1795                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1796                         ndev->stats.tx_aborted_errors++;
1797                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1798                 }
1799         }
1800
1801         if (intr_status & EESR_RABT) {
1802                 /* Receive Abort int */
1803                 if (intr_status & EESR_RFRMER) {
1804                         /* Receive Frame Overflow int */
1805                         ndev->stats.rx_frame_errors++;
1806                 }
1807         }
1808
1809         if (intr_status & EESR_TDE) {
1810                 /* Transmit Descriptor Empty int */
1811                 ndev->stats.tx_fifo_errors++;
1812                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1813         }
1814
1815         if (intr_status & EESR_TFE) {
1816                 /* FIFO under flow */
1817                 ndev->stats.tx_fifo_errors++;
1818                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1819         }
1820
1821         if (intr_status & EESR_RDE) {
1822                 /* Receive Descriptor Empty int */
1823                 ndev->stats.rx_over_errors++;
1824         }
1825
1826         if (intr_status & EESR_RFE) {
1827                 /* Receive FIFO Overflow int */
1828                 ndev->stats.rx_fifo_errors++;
1829         }
1830
1831         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1832                 /* Address Error */
1833                 ndev->stats.tx_fifo_errors++;
1834                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1835         }
1836
1837         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1838         if (mdp->cd->no_ade)
1839                 mask &= ~EESR_ADE;
1840         if (intr_status & mask) {
1841                 /* Tx error */
1842                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1843
1844                 /* dmesg */
1845                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1846                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1847                            (u32)ndev->state, edtrr);
1848                 /* dirty buffer free */
1849                 sh_eth_tx_free(ndev, true);
1850
1851                 /* SH7712 BUG */
1852                 if (edtrr ^ mdp->cd->edtrr_trns) {
1853                         /* tx dma start */
1854                         sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1855                 }
1856                 /* wakeup */
1857                 netif_wake_queue(ndev);
1858         }
1859 }
1860
1861 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1862 {
1863         struct net_device *ndev = netdev;
1864         struct sh_eth_private *mdp = netdev_priv(ndev);
1865         struct sh_eth_cpu_data *cd = mdp->cd;
1866         irqreturn_t ret = IRQ_NONE;
1867         u32 intr_status, intr_enable;
1868
1869         spin_lock(&mdp->lock);
1870
1871         /* Get interrupt status */
1872         intr_status = sh_eth_read(ndev, EESR);
1873         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1874          * enabled since it's the one that  comes  thru regardless of the mask,
1875          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1876          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1877          * bit...
1878          */
1879         intr_enable = sh_eth_read(ndev, EESIPR);
1880         intr_status &= intr_enable | EESIPR_ECIIP;
1881         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1882                            cd->eesr_err_check))
1883                 ret = IRQ_HANDLED;
1884         else
1885                 goto out;
1886
1887         if (unlikely(!mdp->irq_enabled)) {
1888                 sh_eth_write(ndev, 0, EESIPR);
1889                 goto out;
1890         }
1891
1892         if (intr_status & EESR_RX_CHECK) {
1893                 if (napi_schedule_prep(&mdp->napi)) {
1894                         /* Mask Rx interrupts */
1895                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1896                                      EESIPR);
1897                         __napi_schedule(&mdp->napi);
1898                 } else {
1899                         netdev_warn(ndev,
1900                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1901                                     intr_status, intr_enable);
1902                 }
1903         }
1904
1905         /* Tx Check */
1906         if (intr_status & cd->tx_check) {
1907                 /* Clear Tx interrupts */
1908                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1909
1910                 sh_eth_tx_free(ndev, true);
1911                 netif_wake_queue(ndev);
1912         }
1913
1914         /* E-MAC interrupt */
1915         if (intr_status & EESR_ECI)
1916                 sh_eth_emac_interrupt(ndev);
1917
1918         if (intr_status & cd->eesr_err_check) {
1919                 /* Clear error interrupts */
1920                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1921
1922                 sh_eth_error(ndev, intr_status);
1923         }
1924
1925 out:
1926         spin_unlock(&mdp->lock);
1927
1928         return ret;
1929 }
1930
1931 static int sh_eth_poll(struct napi_struct *napi, int budget)
1932 {
1933         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1934                                                   napi);
1935         struct net_device *ndev = napi->dev;
1936         int quota = budget;
1937         u32 intr_status;
1938
1939         for (;;) {
1940                 intr_status = sh_eth_read(ndev, EESR);
1941                 if (!(intr_status & EESR_RX_CHECK))
1942                         break;
1943                 /* Clear Rx interrupts */
1944                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1945
1946                 if (sh_eth_rx(ndev, intr_status, &quota))
1947                         goto out;
1948         }
1949
1950         napi_complete(napi);
1951
1952         /* Reenable Rx interrupts */
1953         if (mdp->irq_enabled)
1954                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1955 out:
1956         return budget - quota;
1957 }
1958
1959 /* PHY state control function */
1960 static void sh_eth_adjust_link(struct net_device *ndev)
1961 {
1962         struct sh_eth_private *mdp = netdev_priv(ndev);
1963         struct phy_device *phydev = ndev->phydev;
1964         unsigned long flags;
1965         int new_state = 0;
1966
1967         spin_lock_irqsave(&mdp->lock, flags);
1968
1969         /* Disable TX and RX right over here, if E-MAC change is ignored */
1970         if (mdp->cd->no_psr || mdp->no_ether_link)
1971                 sh_eth_rcv_snd_disable(ndev);
1972
1973         if (phydev->link) {
1974                 if (phydev->duplex != mdp->duplex) {
1975                         new_state = 1;
1976                         mdp->duplex = phydev->duplex;
1977                         if (mdp->cd->set_duplex)
1978                                 mdp->cd->set_duplex(ndev);
1979                 }
1980
1981                 if (phydev->speed != mdp->speed) {
1982                         new_state = 1;
1983                         mdp->speed = phydev->speed;
1984                         if (mdp->cd->set_rate)
1985                                 mdp->cd->set_rate(ndev);
1986                 }
1987                 if (!mdp->link) {
1988                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1989                         new_state = 1;
1990                         mdp->link = phydev->link;
1991                 }
1992         } else if (mdp->link) {
1993                 new_state = 1;
1994                 mdp->link = 0;
1995                 mdp->speed = 0;
1996                 mdp->duplex = -1;
1997         }
1998
1999         /* Enable TX and RX right over here, if E-MAC change is ignored */
2000         if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2001                 sh_eth_rcv_snd_enable(ndev);
2002
2003         mmiowb();
2004         spin_unlock_irqrestore(&mdp->lock, flags);
2005
2006         if (new_state && netif_msg_link(mdp))
2007                 phy_print_status(phydev);
2008 }
2009
2010 /* PHY init function */
2011 static int sh_eth_phy_init(struct net_device *ndev)
2012 {
2013         struct device_node *np = ndev->dev.parent->of_node;
2014         struct sh_eth_private *mdp = netdev_priv(ndev);
2015         struct phy_device *phydev;
2016
2017         mdp->link = 0;
2018         mdp->speed = 0;
2019         mdp->duplex = -1;
2020
2021         /* Try connect to PHY */
2022         if (np) {
2023                 struct device_node *pn;
2024
2025                 pn = of_parse_phandle(np, "phy-handle", 0);
2026                 phydev = of_phy_connect(ndev, pn,
2027                                         sh_eth_adjust_link, 0,
2028                                         mdp->phy_interface);
2029
2030                 of_node_put(pn);
2031                 if (!phydev)
2032                         phydev = ERR_PTR(-ENOENT);
2033         } else {
2034                 char phy_id[MII_BUS_ID_SIZE + 3];
2035
2036                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2037                          mdp->mii_bus->id, mdp->phy_id);
2038
2039                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2040                                      mdp->phy_interface);
2041         }
2042
2043         if (IS_ERR(phydev)) {
2044                 netdev_err(ndev, "failed to connect PHY\n");
2045                 return PTR_ERR(phydev);
2046         }
2047
2048         /* mask with MAC supported features */
2049         if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2050                 int err = phy_set_max_speed(phydev, SPEED_100);
2051                 if (err) {
2052                         netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2053                         phy_disconnect(phydev);
2054                         return err;
2055                 }
2056         }
2057
2058         phy_attached_info(phydev);
2059
2060         return 0;
2061 }
2062
2063 /* PHY control start function */
2064 static int sh_eth_phy_start(struct net_device *ndev)
2065 {
2066         int ret;
2067
2068         ret = sh_eth_phy_init(ndev);
2069         if (ret)
2070                 return ret;
2071
2072         phy_start(ndev->phydev);
2073
2074         return 0;
2075 }
2076
2077 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2078  * version must be bumped as well.  Just adding registers up to that
2079  * limit is fine, as long as the existing register indices don't
2080  * change.
2081  */
2082 #define SH_ETH_REG_DUMP_VERSION         1
2083 #define SH_ETH_REG_DUMP_MAX_REGS        256
2084
2085 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2086 {
2087         struct sh_eth_private *mdp = netdev_priv(ndev);
2088         struct sh_eth_cpu_data *cd = mdp->cd;
2089         u32 *valid_map;
2090         size_t len;
2091
2092         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2093
2094         /* Dump starts with a bitmap that tells ethtool which
2095          * registers are defined for this chip.
2096          */
2097         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2098         if (buf) {
2099                 valid_map = buf;
2100                 buf += len;
2101         } else {
2102                 valid_map = NULL;
2103         }
2104
2105         /* Add a register to the dump, if it has a defined offset.
2106          * This automatically skips most undefined registers, but for
2107          * some it is also necessary to check a capability flag in
2108          * struct sh_eth_cpu_data.
2109          */
2110 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2111 #define add_reg_from(reg, read_expr) do {                               \
2112                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
2113                         if (buf) {                                      \
2114                                 mark_reg_valid(reg);                    \
2115                                 *buf++ = read_expr;                     \
2116                         }                                               \
2117                         ++len;                                          \
2118                 }                                                       \
2119         } while (0)
2120 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2121 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2122
2123         add_reg(EDSR);
2124         add_reg(EDMR);
2125         add_reg(EDTRR);
2126         add_reg(EDRRR);
2127         add_reg(EESR);
2128         add_reg(EESIPR);
2129         add_reg(TDLAR);
2130         add_reg(TDFAR);
2131         add_reg(TDFXR);
2132         add_reg(TDFFR);
2133         add_reg(RDLAR);
2134         add_reg(RDFAR);
2135         add_reg(RDFXR);
2136         add_reg(RDFFR);
2137         add_reg(TRSCER);
2138         add_reg(RMFCR);
2139         add_reg(TFTR);
2140         add_reg(FDR);
2141         add_reg(RMCR);
2142         add_reg(TFUCR);
2143         add_reg(RFOCR);
2144         if (cd->rmiimode)
2145                 add_reg(RMIIMODE);
2146         add_reg(FCFTR);
2147         if (cd->rpadir)
2148                 add_reg(RPADIR);
2149         if (!cd->no_trimd)
2150                 add_reg(TRIMD);
2151         add_reg(ECMR);
2152         add_reg(ECSR);
2153         add_reg(ECSIPR);
2154         add_reg(PIR);
2155         if (!cd->no_psr)
2156                 add_reg(PSR);
2157         add_reg(RDMLR);
2158         add_reg(RFLR);
2159         add_reg(IPGR);
2160         if (cd->apr)
2161                 add_reg(APR);
2162         if (cd->mpr)
2163                 add_reg(MPR);
2164         add_reg(RFCR);
2165         add_reg(RFCF);
2166         if (cd->tpauser)
2167                 add_reg(TPAUSER);
2168         add_reg(TPAUSECR);
2169         add_reg(GECMR);
2170         if (cd->bculr)
2171                 add_reg(BCULR);
2172         add_reg(MAHR);
2173         add_reg(MALR);
2174         add_reg(TROCR);
2175         add_reg(CDCR);
2176         add_reg(LCCR);
2177         add_reg(CNDCR);
2178         add_reg(CEFCR);
2179         add_reg(FRECR);
2180         add_reg(TSFRCR);
2181         add_reg(TLFRCR);
2182         add_reg(CERCR);
2183         add_reg(CEECR);
2184         add_reg(MAFCR);
2185         if (cd->rtrate)
2186                 add_reg(RTRATE);
2187         if (cd->hw_checksum)
2188                 add_reg(CSMR);
2189         if (cd->select_mii)
2190                 add_reg(RMII_MII);
2191         if (cd->tsu) {
2192                 add_tsu_reg(ARSTR);
2193                 add_tsu_reg(TSU_CTRST);
2194                 if (cd->dual_port) {
2195                         add_tsu_reg(TSU_FWEN0);
2196                         add_tsu_reg(TSU_FWEN1);
2197                         add_tsu_reg(TSU_FCM);
2198                         add_tsu_reg(TSU_BSYSL0);
2199                         add_tsu_reg(TSU_BSYSL1);
2200                         add_tsu_reg(TSU_PRISL0);
2201                         add_tsu_reg(TSU_PRISL1);
2202                         add_tsu_reg(TSU_FWSL0);
2203                         add_tsu_reg(TSU_FWSL1);
2204                 }
2205                 add_tsu_reg(TSU_FWSLC);
2206                 if (cd->dual_port) {
2207                         add_tsu_reg(TSU_QTAGM0);
2208                         add_tsu_reg(TSU_QTAGM1);
2209                         add_tsu_reg(TSU_FWSR);
2210                         add_tsu_reg(TSU_FWINMK);
2211                         add_tsu_reg(TSU_ADQT0);
2212                         add_tsu_reg(TSU_ADQT1);
2213                         add_tsu_reg(TSU_VTAG0);
2214                         add_tsu_reg(TSU_VTAG1);
2215                 }
2216                 add_tsu_reg(TSU_ADSBSY);
2217                 add_tsu_reg(TSU_TEN);
2218                 add_tsu_reg(TSU_POST1);
2219                 add_tsu_reg(TSU_POST2);
2220                 add_tsu_reg(TSU_POST3);
2221                 add_tsu_reg(TSU_POST4);
2222                 /* This is the start of a table, not just a single register. */
2223                 if (buf) {
2224                         unsigned int i;
2225
2226                         mark_reg_valid(TSU_ADRH0);
2227                         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2228                                 *buf++ = ioread32(mdp->tsu_addr +
2229                                                   mdp->reg_offset[TSU_ADRH0] +
2230                                                   i * 4);
2231                 }
2232                 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2233         }
2234
2235 #undef mark_reg_valid
2236 #undef add_reg_from
2237 #undef add_reg
2238 #undef add_tsu_reg
2239
2240         return len * 4;
2241 }
2242
2243 static int sh_eth_get_regs_len(struct net_device *ndev)
2244 {
2245         return __sh_eth_get_regs(ndev, NULL);
2246 }
2247
2248 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2249                             void *buf)
2250 {
2251         struct sh_eth_private *mdp = netdev_priv(ndev);
2252
2253         regs->version = SH_ETH_REG_DUMP_VERSION;
2254
2255         pm_runtime_get_sync(&mdp->pdev->dev);
2256         __sh_eth_get_regs(ndev, buf);
2257         pm_runtime_put_sync(&mdp->pdev->dev);
2258 }
2259
2260 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2261 {
2262         struct sh_eth_private *mdp = netdev_priv(ndev);
2263         return mdp->msg_enable;
2264 }
2265
2266 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2267 {
2268         struct sh_eth_private *mdp = netdev_priv(ndev);
2269         mdp->msg_enable = value;
2270 }
2271
2272 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2273         "rx_current", "tx_current",
2274         "rx_dirty", "tx_dirty",
2275 };
2276 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2277
2278 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2279 {
2280         switch (sset) {
2281         case ETH_SS_STATS:
2282                 return SH_ETH_STATS_LEN;
2283         default:
2284                 return -EOPNOTSUPP;
2285         }
2286 }
2287
2288 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2289                                      struct ethtool_stats *stats, u64 *data)
2290 {
2291         struct sh_eth_private *mdp = netdev_priv(ndev);
2292         int i = 0;
2293
2294         /* device-specific stats */
2295         data[i++] = mdp->cur_rx;
2296         data[i++] = mdp->cur_tx;
2297         data[i++] = mdp->dirty_rx;
2298         data[i++] = mdp->dirty_tx;
2299 }
2300
2301 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2302 {
2303         switch (stringset) {
2304         case ETH_SS_STATS:
2305                 memcpy(data, sh_eth_gstrings_stats,
2306                        sizeof(sh_eth_gstrings_stats));
2307                 break;
2308         }
2309 }
2310
2311 static void sh_eth_get_ringparam(struct net_device *ndev,
2312                                  struct ethtool_ringparam *ring)
2313 {
2314         struct sh_eth_private *mdp = netdev_priv(ndev);
2315
2316         ring->rx_max_pending = RX_RING_MAX;
2317         ring->tx_max_pending = TX_RING_MAX;
2318         ring->rx_pending = mdp->num_rx_ring;
2319         ring->tx_pending = mdp->num_tx_ring;
2320 }
2321
2322 static int sh_eth_set_ringparam(struct net_device *ndev,
2323                                 struct ethtool_ringparam *ring)
2324 {
2325         struct sh_eth_private *mdp = netdev_priv(ndev);
2326         int ret;
2327
2328         if (ring->tx_pending > TX_RING_MAX ||
2329             ring->rx_pending > RX_RING_MAX ||
2330             ring->tx_pending < TX_RING_MIN ||
2331             ring->rx_pending < RX_RING_MIN)
2332                 return -EINVAL;
2333         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2334                 return -EINVAL;
2335
2336         if (netif_running(ndev)) {
2337                 netif_device_detach(ndev);
2338                 netif_tx_disable(ndev);
2339
2340                 /* Serialise with the interrupt handler and NAPI, then
2341                  * disable interrupts.  We have to clear the
2342                  * irq_enabled flag first to ensure that interrupts
2343                  * won't be re-enabled.
2344                  */
2345                 mdp->irq_enabled = false;
2346                 synchronize_irq(ndev->irq);
2347                 napi_synchronize(&mdp->napi);
2348                 sh_eth_write(ndev, 0x0000, EESIPR);
2349
2350                 sh_eth_dev_exit(ndev);
2351
2352                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2353                 sh_eth_ring_free(ndev);
2354         }
2355
2356         /* Set new parameters */
2357         mdp->num_rx_ring = ring->rx_pending;
2358         mdp->num_tx_ring = ring->tx_pending;
2359
2360         if (netif_running(ndev)) {
2361                 ret = sh_eth_ring_init(ndev);
2362                 if (ret < 0) {
2363                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2364                                    __func__);
2365                         return ret;
2366                 }
2367                 ret = sh_eth_dev_init(ndev);
2368                 if (ret < 0) {
2369                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2370                                    __func__);
2371                         return ret;
2372                 }
2373
2374                 netif_device_attach(ndev);
2375         }
2376
2377         return 0;
2378 }
2379
2380 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2381 {
2382         struct sh_eth_private *mdp = netdev_priv(ndev);
2383
2384         wol->supported = 0;
2385         wol->wolopts = 0;
2386
2387         if (mdp->cd->magic) {
2388                 wol->supported = WAKE_MAGIC;
2389                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2390         }
2391 }
2392
2393 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2394 {
2395         struct sh_eth_private *mdp = netdev_priv(ndev);
2396
2397         if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2398                 return -EOPNOTSUPP;
2399
2400         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2401
2402         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2403
2404         return 0;
2405 }
2406
2407 static const struct ethtool_ops sh_eth_ethtool_ops = {
2408         .get_regs_len   = sh_eth_get_regs_len,
2409         .get_regs       = sh_eth_get_regs,
2410         .nway_reset     = phy_ethtool_nway_reset,
2411         .get_msglevel   = sh_eth_get_msglevel,
2412         .set_msglevel   = sh_eth_set_msglevel,
2413         .get_link       = ethtool_op_get_link,
2414         .get_strings    = sh_eth_get_strings,
2415         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2416         .get_sset_count     = sh_eth_get_sset_count,
2417         .get_ringparam  = sh_eth_get_ringparam,
2418         .set_ringparam  = sh_eth_set_ringparam,
2419         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2420         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2421         .get_wol        = sh_eth_get_wol,
2422         .set_wol        = sh_eth_set_wol,
2423 };
2424
2425 /* network device open function */
2426 static int sh_eth_open(struct net_device *ndev)
2427 {
2428         struct sh_eth_private *mdp = netdev_priv(ndev);
2429         int ret;
2430
2431         pm_runtime_get_sync(&mdp->pdev->dev);
2432
2433         napi_enable(&mdp->napi);
2434
2435         ret = request_irq(ndev->irq, sh_eth_interrupt,
2436                           mdp->cd->irq_flags, ndev->name, ndev);
2437         if (ret) {
2438                 netdev_err(ndev, "Can not assign IRQ number\n");
2439                 goto out_napi_off;
2440         }
2441
2442         /* Descriptor set */
2443         ret = sh_eth_ring_init(ndev);
2444         if (ret)
2445                 goto out_free_irq;
2446
2447         /* device init */
2448         ret = sh_eth_dev_init(ndev);
2449         if (ret)
2450                 goto out_free_irq;
2451
2452         /* PHY control start*/
2453         ret = sh_eth_phy_start(ndev);
2454         if (ret)
2455                 goto out_free_irq;
2456
2457         netif_start_queue(ndev);
2458
2459         mdp->is_opened = 1;
2460
2461         return ret;
2462
2463 out_free_irq:
2464         free_irq(ndev->irq, ndev);
2465 out_napi_off:
2466         napi_disable(&mdp->napi);
2467         pm_runtime_put_sync(&mdp->pdev->dev);
2468         return ret;
2469 }
2470
2471 /* Timeout function */
2472 static void sh_eth_tx_timeout(struct net_device *ndev)
2473 {
2474         struct sh_eth_private *mdp = netdev_priv(ndev);
2475         struct sh_eth_rxdesc *rxdesc;
2476         int i;
2477
2478         netif_stop_queue(ndev);
2479
2480         netif_err(mdp, timer, ndev,
2481                   "transmit timed out, status %8.8x, resetting...\n",
2482                   sh_eth_read(ndev, EESR));
2483
2484         /* tx_errors count up */
2485         ndev->stats.tx_errors++;
2486
2487         /* Free all the skbuffs in the Rx queue. */
2488         for (i = 0; i < mdp->num_rx_ring; i++) {
2489                 rxdesc = &mdp->rx_ring[i];
2490                 rxdesc->status = cpu_to_le32(0);
2491                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2492                 dev_kfree_skb(mdp->rx_skbuff[i]);
2493                 mdp->rx_skbuff[i] = NULL;
2494         }
2495         for (i = 0; i < mdp->num_tx_ring; i++) {
2496                 dev_kfree_skb(mdp->tx_skbuff[i]);
2497                 mdp->tx_skbuff[i] = NULL;
2498         }
2499
2500         /* device init */
2501         sh_eth_dev_init(ndev);
2502
2503         netif_start_queue(ndev);
2504 }
2505
2506 /* Packet transmit function */
2507 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2508 {
2509         struct sh_eth_private *mdp = netdev_priv(ndev);
2510         struct sh_eth_txdesc *txdesc;
2511         dma_addr_t dma_addr;
2512         u32 entry;
2513         unsigned long flags;
2514
2515         spin_lock_irqsave(&mdp->lock, flags);
2516         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2517                 if (!sh_eth_tx_free(ndev, true)) {
2518                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2519                         netif_stop_queue(ndev);
2520                         spin_unlock_irqrestore(&mdp->lock, flags);
2521                         return NETDEV_TX_BUSY;
2522                 }
2523         }
2524         spin_unlock_irqrestore(&mdp->lock, flags);
2525
2526         if (skb_put_padto(skb, ETH_ZLEN))
2527                 return NETDEV_TX_OK;
2528
2529         entry = mdp->cur_tx % mdp->num_tx_ring;
2530         mdp->tx_skbuff[entry] = skb;
2531         txdesc = &mdp->tx_ring[entry];
2532         /* soft swap. */
2533         if (!mdp->cd->hw_swap)
2534                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2535         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2536                                   DMA_TO_DEVICE);
2537         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2538                 kfree_skb(skb);
2539                 return NETDEV_TX_OK;
2540         }
2541         txdesc->addr = cpu_to_le32(dma_addr);
2542         txdesc->len  = cpu_to_le32(skb->len << 16);
2543
2544         dma_wmb(); /* TACT bit must be set after all the above writes */
2545         if (entry >= mdp->num_tx_ring - 1)
2546                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2547         else
2548                 txdesc->status |= cpu_to_le32(TD_TACT);
2549
2550         wmb(); /* cur_tx must be incremented after TACT bit was set */
2551         mdp->cur_tx++;
2552
2553         if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2554                 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2555
2556         return NETDEV_TX_OK;
2557 }
2558
2559 /* The statistics registers have write-clear behaviour, which means we
2560  * will lose any increment between the read and write.  We mitigate
2561  * this by only clearing when we read a non-zero value, so we will
2562  * never falsely report a total of zero.
2563  */
2564 static void
2565 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2566 {
2567         u32 delta = sh_eth_read(ndev, reg);
2568
2569         if (delta) {
2570                 *stat += delta;
2571                 sh_eth_write(ndev, 0, reg);
2572         }
2573 }
2574
2575 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2576 {
2577         struct sh_eth_private *mdp = netdev_priv(ndev);
2578
2579         if (mdp->cd->no_tx_cntrs)
2580                 return &ndev->stats;
2581
2582         if (!mdp->is_opened)
2583                 return &ndev->stats;
2584
2585         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2586         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2587         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2588
2589         if (mdp->cd->cexcr) {
2590                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2591                                    CERCR);
2592                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2593                                    CEECR);
2594         } else {
2595                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2596                                    CNDCR);
2597         }
2598
2599         return &ndev->stats;
2600 }
2601
2602 /* device close function */
2603 static int sh_eth_close(struct net_device *ndev)
2604 {
2605         struct sh_eth_private *mdp = netdev_priv(ndev);
2606
2607         netif_stop_queue(ndev);
2608
2609         /* Serialise with the interrupt handler and NAPI, then disable
2610          * interrupts.  We have to clear the irq_enabled flag first to
2611          * ensure that interrupts won't be re-enabled.
2612          */
2613         mdp->irq_enabled = false;
2614         synchronize_irq(ndev->irq);
2615         napi_disable(&mdp->napi);
2616         sh_eth_write(ndev, 0x0000, EESIPR);
2617
2618         sh_eth_dev_exit(ndev);
2619
2620         /* PHY Disconnect */
2621         if (ndev->phydev) {
2622                 phy_stop(ndev->phydev);
2623                 phy_disconnect(ndev->phydev);
2624         }
2625
2626         free_irq(ndev->irq, ndev);
2627
2628         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2629         sh_eth_ring_free(ndev);
2630
2631         mdp->is_opened = 0;
2632
2633         pm_runtime_put(&mdp->pdev->dev);
2634
2635         return 0;
2636 }
2637
2638 /* ioctl to device function */
2639 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2640 {
2641         struct phy_device *phydev = ndev->phydev;
2642
2643         if (!netif_running(ndev))
2644                 return -EINVAL;
2645
2646         if (!phydev)
2647                 return -ENODEV;
2648
2649         return phy_mii_ioctl(phydev, rq, cmd);
2650 }
2651
2652 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2653 {
2654         if (netif_running(ndev))
2655                 return -EBUSY;
2656
2657         ndev->mtu = new_mtu;
2658         netdev_update_features(ndev);
2659
2660         return 0;
2661 }
2662
2663 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2664 static u32 sh_eth_tsu_get_post_mask(int entry)
2665 {
2666         return 0x0f << (28 - ((entry % 8) * 4));
2667 }
2668
2669 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2670 {
2671         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2672 }
2673
2674 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2675                                              int entry)
2676 {
2677         struct sh_eth_private *mdp = netdev_priv(ndev);
2678         int reg = TSU_POST1 + entry / 8;
2679         u32 tmp;
2680
2681         tmp = sh_eth_tsu_read(mdp, reg);
2682         sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2683 }
2684
2685 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2686                                               int entry)
2687 {
2688         struct sh_eth_private *mdp = netdev_priv(ndev);
2689         int reg = TSU_POST1 + entry / 8;
2690         u32 post_mask, ref_mask, tmp;
2691
2692         post_mask = sh_eth_tsu_get_post_mask(entry);
2693         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2694
2695         tmp = sh_eth_tsu_read(mdp, reg);
2696         sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2697
2698         /* If other port enables, the function returns "true" */
2699         return tmp & ref_mask;
2700 }
2701
2702 static int sh_eth_tsu_busy(struct net_device *ndev)
2703 {
2704         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2705         struct sh_eth_private *mdp = netdev_priv(ndev);
2706
2707         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2708                 udelay(10);
2709                 timeout--;
2710                 if (timeout <= 0) {
2711                         netdev_err(ndev, "%s: timeout\n", __func__);
2712                         return -ETIMEDOUT;
2713                 }
2714         }
2715
2716         return 0;
2717 }
2718
2719 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2720                                   const u8 *addr)
2721 {
2722         struct sh_eth_private *mdp = netdev_priv(ndev);
2723         u32 val;
2724
2725         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2726         iowrite32(val, mdp->tsu_addr + offset);
2727         if (sh_eth_tsu_busy(ndev) < 0)
2728                 return -EBUSY;
2729
2730         val = addr[4] << 8 | addr[5];
2731         iowrite32(val, mdp->tsu_addr + offset + 4);
2732         if (sh_eth_tsu_busy(ndev) < 0)
2733                 return -EBUSY;
2734
2735         return 0;
2736 }
2737
2738 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2739 {
2740         struct sh_eth_private *mdp = netdev_priv(ndev);
2741         u32 val;
2742
2743         val = ioread32(mdp->tsu_addr + offset);
2744         addr[0] = (val >> 24) & 0xff;
2745         addr[1] = (val >> 16) & 0xff;
2746         addr[2] = (val >> 8) & 0xff;
2747         addr[3] = val & 0xff;
2748         val = ioread32(mdp->tsu_addr + offset + 4);
2749         addr[4] = (val >> 8) & 0xff;
2750         addr[5] = val & 0xff;
2751 }
2752
2753
2754 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2755 {
2756         struct sh_eth_private *mdp = netdev_priv(ndev);
2757         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2758         int i;
2759         u8 c_addr[ETH_ALEN];
2760
2761         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2762                 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2763                 if (ether_addr_equal(addr, c_addr))
2764                         return i;
2765         }
2766
2767         return -ENOENT;
2768 }
2769
2770 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2771 {
2772         u8 blank[ETH_ALEN];
2773         int entry;
2774
2775         memset(blank, 0, sizeof(blank));
2776         entry = sh_eth_tsu_find_entry(ndev, blank);
2777         return (entry < 0) ? -ENOMEM : entry;
2778 }
2779
2780 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2781                                               int entry)
2782 {
2783         struct sh_eth_private *mdp = netdev_priv(ndev);
2784         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2785         int ret;
2786         u8 blank[ETH_ALEN];
2787
2788         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2789                          ~(1 << (31 - entry)), TSU_TEN);
2790
2791         memset(blank, 0, sizeof(blank));
2792         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2793         if (ret < 0)
2794                 return ret;
2795         return 0;
2796 }
2797
2798 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2799 {
2800         struct sh_eth_private *mdp = netdev_priv(ndev);
2801         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2802         int i, ret;
2803
2804         if (!mdp->cd->tsu)
2805                 return 0;
2806
2807         i = sh_eth_tsu_find_entry(ndev, addr);
2808         if (i < 0) {
2809                 /* No entry found, create one */
2810                 i = sh_eth_tsu_find_empty(ndev);
2811                 if (i < 0)
2812                         return -ENOMEM;
2813                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2814                 if (ret < 0)
2815                         return ret;
2816
2817                 /* Enable the entry */
2818                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2819                                  (1 << (31 - i)), TSU_TEN);
2820         }
2821
2822         /* Entry found or created, enable POST */
2823         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2824
2825         return 0;
2826 }
2827
2828 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2829 {
2830         struct sh_eth_private *mdp = netdev_priv(ndev);
2831         int i, ret;
2832
2833         if (!mdp->cd->tsu)
2834                 return 0;
2835
2836         i = sh_eth_tsu_find_entry(ndev, addr);
2837         if (i) {
2838                 /* Entry found */
2839                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2840                         goto done;
2841
2842                 /* Disable the entry if both ports was disabled */
2843                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2844                 if (ret < 0)
2845                         return ret;
2846         }
2847 done:
2848         return 0;
2849 }
2850
2851 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2852 {
2853         struct sh_eth_private *mdp = netdev_priv(ndev);
2854         int i, ret;
2855
2856         if (!mdp->cd->tsu)
2857                 return 0;
2858
2859         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2860                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2861                         continue;
2862
2863                 /* Disable the entry if both ports was disabled */
2864                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2865                 if (ret < 0)
2866                         return ret;
2867         }
2868
2869         return 0;
2870 }
2871
2872 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2873 {
2874         struct sh_eth_private *mdp = netdev_priv(ndev);
2875         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2876         u8 addr[ETH_ALEN];
2877         int i;
2878
2879         if (!mdp->cd->tsu)
2880                 return;
2881
2882         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2883                 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2884                 if (is_multicast_ether_addr(addr))
2885                         sh_eth_tsu_del_entry(ndev, addr);
2886         }
2887 }
2888
2889 /* Update promiscuous flag and multicast filter */
2890 static void sh_eth_set_rx_mode(struct net_device *ndev)
2891 {
2892         struct sh_eth_private *mdp = netdev_priv(ndev);
2893         u32 ecmr_bits;
2894         int mcast_all = 0;
2895         unsigned long flags;
2896
2897         spin_lock_irqsave(&mdp->lock, flags);
2898         /* Initial condition is MCT = 1, PRM = 0.
2899          * Depending on ndev->flags, set PRM or clear MCT
2900          */
2901         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2902         if (mdp->cd->tsu)
2903                 ecmr_bits |= ECMR_MCT;
2904
2905         if (!(ndev->flags & IFF_MULTICAST)) {
2906                 sh_eth_tsu_purge_mcast(ndev);
2907                 mcast_all = 1;
2908         }
2909         if (ndev->flags & IFF_ALLMULTI) {
2910                 sh_eth_tsu_purge_mcast(ndev);
2911                 ecmr_bits &= ~ECMR_MCT;
2912                 mcast_all = 1;
2913         }
2914
2915         if (ndev->flags & IFF_PROMISC) {
2916                 sh_eth_tsu_purge_all(ndev);
2917                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2918         } else if (mdp->cd->tsu) {
2919                 struct netdev_hw_addr *ha;
2920                 netdev_for_each_mc_addr(ha, ndev) {
2921                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2922                                 continue;
2923
2924                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2925                                 if (!mcast_all) {
2926                                         sh_eth_tsu_purge_mcast(ndev);
2927                                         ecmr_bits &= ~ECMR_MCT;
2928                                         mcast_all = 1;
2929                                 }
2930                         }
2931                 }
2932         }
2933
2934         /* update the ethernet mode */
2935         sh_eth_write(ndev, ecmr_bits, ECMR);
2936
2937         spin_unlock_irqrestore(&mdp->lock, flags);
2938 }
2939
2940 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2941 {
2942         if (!mdp->port)
2943                 return TSU_VTAG0;
2944         else
2945                 return TSU_VTAG1;
2946 }
2947
2948 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2949                                   __be16 proto, u16 vid)
2950 {
2951         struct sh_eth_private *mdp = netdev_priv(ndev);
2952         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2953
2954         if (unlikely(!mdp->cd->tsu))
2955                 return -EPERM;
2956
2957         /* No filtering if vid = 0 */
2958         if (!vid)
2959                 return 0;
2960
2961         mdp->vlan_num_ids++;
2962
2963         /* The controller has one VLAN tag HW filter. So, if the filter is
2964          * already enabled, the driver disables it and the filte
2965          */
2966         if (mdp->vlan_num_ids > 1) {
2967                 /* disable VLAN filter */
2968                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2969                 return 0;
2970         }
2971
2972         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2973                          vtag_reg_index);
2974
2975         return 0;
2976 }
2977
2978 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2979                                    __be16 proto, u16 vid)
2980 {
2981         struct sh_eth_private *mdp = netdev_priv(ndev);
2982         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2983
2984         if (unlikely(!mdp->cd->tsu))
2985                 return -EPERM;
2986
2987         /* No filtering if vid = 0 */
2988         if (!vid)
2989                 return 0;
2990
2991         mdp->vlan_num_ids--;
2992         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2993
2994         return 0;
2995 }
2996
2997 /* SuperH's TSU register init function */
2998 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2999 {
3000         if (!mdp->cd->dual_port) {
3001                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3002                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3003                                  TSU_FWSLC);    /* Enable POST registers */
3004                 return;
3005         }
3006
3007         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
3008         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
3009         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
3010         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3011         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3012         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3013         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3014         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3015         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3016         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3017         sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
3018         sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
3019         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
3020         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
3021         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
3022         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
3023         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
3024         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
3025         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
3026 }
3027
3028 /* MDIO bus release function */
3029 static int sh_mdio_release(struct sh_eth_private *mdp)
3030 {
3031         /* unregister mdio bus */
3032         mdiobus_unregister(mdp->mii_bus);
3033
3034         /* free bitbang info */
3035         free_mdio_bitbang(mdp->mii_bus);
3036
3037         return 0;
3038 }
3039
3040 /* MDIO bus init function */
3041 static int sh_mdio_init(struct sh_eth_private *mdp,
3042                         struct sh_eth_plat_data *pd)
3043 {
3044         int ret;
3045         struct bb_info *bitbang;
3046         struct platform_device *pdev = mdp->pdev;
3047         struct device *dev = &mdp->pdev->dev;
3048
3049         /* create bit control struct for PHY */
3050         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3051         if (!bitbang)
3052                 return -ENOMEM;
3053
3054         /* bitbang init */
3055         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3056         bitbang->set_gate = pd->set_mdio_gate;
3057         bitbang->ctrl.ops = &bb_ops;
3058
3059         /* MII controller setting */
3060         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3061         if (!mdp->mii_bus)
3062                 return -ENOMEM;
3063
3064         /* Hook up MII support for ethtool */
3065         mdp->mii_bus->name = "sh_mii";
3066         mdp->mii_bus->parent = dev;
3067         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3068                  pdev->name, pdev->id);
3069
3070         /* register MDIO bus */
3071         if (pd->phy_irq > 0)
3072                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3073
3074         ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3075         if (ret)
3076                 goto out_free_bus;
3077
3078         return 0;
3079
3080 out_free_bus:
3081         free_mdio_bitbang(mdp->mii_bus);
3082         return ret;
3083 }
3084
3085 static const u16 *sh_eth_get_register_offset(int register_type)
3086 {
3087         const u16 *reg_offset = NULL;
3088
3089         switch (register_type) {
3090         case SH_ETH_REG_GIGABIT:
3091                 reg_offset = sh_eth_offset_gigabit;
3092                 break;
3093         case SH_ETH_REG_FAST_RZ:
3094                 reg_offset = sh_eth_offset_fast_rz;
3095                 break;
3096         case SH_ETH_REG_FAST_RCAR:
3097                 reg_offset = sh_eth_offset_fast_rcar;
3098                 break;
3099         case SH_ETH_REG_FAST_SH4:
3100                 reg_offset = sh_eth_offset_fast_sh4;
3101                 break;
3102         case SH_ETH_REG_FAST_SH3_SH2:
3103                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3104                 break;
3105         }
3106
3107         return reg_offset;
3108 }
3109
3110 static const struct net_device_ops sh_eth_netdev_ops = {
3111         .ndo_open               = sh_eth_open,
3112         .ndo_stop               = sh_eth_close,
3113         .ndo_start_xmit         = sh_eth_start_xmit,
3114         .ndo_get_stats          = sh_eth_get_stats,
3115         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3116         .ndo_tx_timeout         = sh_eth_tx_timeout,
3117         .ndo_do_ioctl           = sh_eth_do_ioctl,
3118         .ndo_change_mtu         = sh_eth_change_mtu,
3119         .ndo_validate_addr      = eth_validate_addr,
3120         .ndo_set_mac_address    = eth_mac_addr,
3121 };
3122
3123 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3124         .ndo_open               = sh_eth_open,
3125         .ndo_stop               = sh_eth_close,
3126         .ndo_start_xmit         = sh_eth_start_xmit,
3127         .ndo_get_stats          = sh_eth_get_stats,
3128         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3129         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3130         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3131         .ndo_tx_timeout         = sh_eth_tx_timeout,
3132         .ndo_do_ioctl           = sh_eth_do_ioctl,
3133         .ndo_change_mtu         = sh_eth_change_mtu,
3134         .ndo_validate_addr      = eth_validate_addr,
3135         .ndo_set_mac_address    = eth_mac_addr,
3136 };
3137
3138 #ifdef CONFIG_OF
3139 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3140 {
3141         struct device_node *np = dev->of_node;
3142         struct sh_eth_plat_data *pdata;
3143         const char *mac_addr;
3144         int ret;
3145
3146         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3147         if (!pdata)
3148                 return NULL;
3149
3150         ret = of_get_phy_mode(np);
3151         if (ret < 0)
3152                 return NULL;
3153         pdata->phy_interface = ret;
3154
3155         mac_addr = of_get_mac_address(np);
3156         if (mac_addr)
3157                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3158
3159         pdata->no_ether_link =
3160                 of_property_read_bool(np, "renesas,no-ether-link");
3161         pdata->ether_link_active_low =
3162                 of_property_read_bool(np, "renesas,ether-link-active-low");
3163
3164         return pdata;
3165 }
3166
3167 static const struct of_device_id sh_eth_match_table[] = {
3168         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3169         { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3170         { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3171         { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3172         { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3173         { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3174         { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3175         { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3176         { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3177         { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3178         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3179         { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3180         { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3181         { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3182         { }
3183 };
3184 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3185 #else
3186 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3187 {
3188         return NULL;
3189 }
3190 #endif
3191
3192 static int sh_eth_drv_probe(struct platform_device *pdev)
3193 {
3194         struct resource *res;
3195         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3196         const struct platform_device_id *id = platform_get_device_id(pdev);
3197         struct sh_eth_private *mdp;
3198         struct net_device *ndev;
3199         int ret;
3200
3201         /* get base addr */
3202         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3203
3204         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3205         if (!ndev)
3206                 return -ENOMEM;
3207
3208         pm_runtime_enable(&pdev->dev);
3209         pm_runtime_get_sync(&pdev->dev);
3210
3211         ret = platform_get_irq(pdev, 0);
3212         if (ret < 0)
3213                 goto out_release;
3214         ndev->irq = ret;
3215
3216         SET_NETDEV_DEV(ndev, &pdev->dev);
3217
3218         mdp = netdev_priv(ndev);
3219         mdp->num_tx_ring = TX_RING_SIZE;
3220         mdp->num_rx_ring = RX_RING_SIZE;
3221         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3222         if (IS_ERR(mdp->addr)) {
3223                 ret = PTR_ERR(mdp->addr);
3224                 goto out_release;
3225         }
3226
3227         ndev->base_addr = res->start;
3228
3229         spin_lock_init(&mdp->lock);
3230         mdp->pdev = pdev;
3231
3232         if (pdev->dev.of_node)
3233                 pd = sh_eth_parse_dt(&pdev->dev);
3234         if (!pd) {
3235                 dev_err(&pdev->dev, "no platform data\n");
3236                 ret = -EINVAL;
3237                 goto out_release;
3238         }
3239
3240         /* get PHY ID */
3241         mdp->phy_id = pd->phy;
3242         mdp->phy_interface = pd->phy_interface;
3243         mdp->no_ether_link = pd->no_ether_link;
3244         mdp->ether_link_active_low = pd->ether_link_active_low;
3245
3246         /* set cpu data */
3247         if (id)
3248                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3249         else
3250                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3251
3252         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3253         if (!mdp->reg_offset) {
3254                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3255                         mdp->cd->register_type);
3256                 ret = -EINVAL;
3257                 goto out_release;
3258         }
3259         sh_eth_set_default_cpu_data(mdp->cd);
3260
3261         /* User's manual states max MTU should be 2048 but due to the
3262          * alignment calculations in sh_eth_ring_init() the practical
3263          * MTU is a bit less. Maybe this can be optimized some more.
3264          */
3265         ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3266         ndev->min_mtu = ETH_MIN_MTU;
3267
3268         /* set function */
3269         if (mdp->cd->tsu)
3270                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3271         else
3272                 ndev->netdev_ops = &sh_eth_netdev_ops;
3273         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3274         ndev->watchdog_timeo = TX_TIMEOUT;
3275
3276         /* debug message level */
3277         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3278
3279         /* read and set MAC address */
3280         read_mac_address(ndev, pd->mac_addr);
3281         if (!is_valid_ether_addr(ndev->dev_addr)) {
3282                 dev_warn(&pdev->dev,
3283                          "no valid MAC address supplied, using a random one.\n");
3284                 eth_hw_addr_random(ndev);
3285         }
3286
3287         if (mdp->cd->tsu) {
3288                 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3289                 struct resource *rtsu;
3290
3291                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3292                 if (!rtsu) {
3293                         dev_err(&pdev->dev, "no TSU resource\n");
3294                         ret = -ENODEV;
3295                         goto out_release;
3296                 }
3297                 /* We can only request the  TSU region  for the first port
3298                  * of the two  sharing this TSU for the probe to succeed...
3299                  */
3300                 if (port == 0 &&
3301                     !devm_request_mem_region(&pdev->dev, rtsu->start,
3302                                              resource_size(rtsu),
3303                                              dev_name(&pdev->dev))) {
3304                         dev_err(&pdev->dev, "can't request TSU resource.\n");
3305                         ret = -EBUSY;
3306                         goto out_release;
3307                 }
3308                 /* ioremap the TSU registers */
3309                 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3310                                              resource_size(rtsu));
3311                 if (!mdp->tsu_addr) {
3312                         dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3313                         ret = -ENOMEM;
3314                         goto out_release;
3315                 }
3316                 mdp->port = port;
3317                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3318
3319                 /* Need to init only the first port of the two sharing a TSU */
3320                 if (port == 0) {
3321                         if (mdp->cd->chip_reset)
3322                                 mdp->cd->chip_reset(ndev);
3323
3324                         /* TSU init (Init only)*/
3325                         sh_eth_tsu_init(mdp);
3326                 }
3327         }
3328
3329         if (mdp->cd->rmiimode)
3330                 sh_eth_write(ndev, 0x1, RMIIMODE);
3331
3332         /* MDIO bus init */
3333         ret = sh_mdio_init(mdp, pd);
3334         if (ret) {
3335                 if (ret != -EPROBE_DEFER)
3336                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3337                 goto out_release;
3338         }
3339
3340         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3341
3342         /* network device register */
3343         ret = register_netdev(ndev);
3344         if (ret)
3345                 goto out_napi_del;
3346
3347         if (mdp->cd->magic)
3348                 device_set_wakeup_capable(&pdev->dev, 1);
3349
3350         /* print device information */
3351         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3352                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3353
3354         pm_runtime_put(&pdev->dev);
3355         platform_set_drvdata(pdev, ndev);
3356
3357         return ret;
3358
3359 out_napi_del:
3360         netif_napi_del(&mdp->napi);
3361         sh_mdio_release(mdp);
3362
3363 out_release:
3364         /* net_dev free */
3365         free_netdev(ndev);
3366
3367         pm_runtime_put(&pdev->dev);
3368         pm_runtime_disable(&pdev->dev);
3369         return ret;
3370 }
3371
3372 static int sh_eth_drv_remove(struct platform_device *pdev)
3373 {
3374         struct net_device *ndev = platform_get_drvdata(pdev);
3375         struct sh_eth_private *mdp = netdev_priv(ndev);
3376
3377         unregister_netdev(ndev);
3378         netif_napi_del(&mdp->napi);
3379         sh_mdio_release(mdp);
3380         pm_runtime_disable(&pdev->dev);
3381         free_netdev(ndev);
3382
3383         return 0;
3384 }
3385
3386 #ifdef CONFIG_PM
3387 #ifdef CONFIG_PM_SLEEP
3388 static int sh_eth_wol_setup(struct net_device *ndev)
3389 {
3390         struct sh_eth_private *mdp = netdev_priv(ndev);
3391
3392         /* Only allow ECI interrupts */
3393         synchronize_irq(ndev->irq);
3394         napi_disable(&mdp->napi);
3395         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3396
3397         /* Enable MagicPacket */
3398         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3399
3400         return enable_irq_wake(ndev->irq);
3401 }
3402
3403 static int sh_eth_wol_restore(struct net_device *ndev)
3404 {
3405         struct sh_eth_private *mdp = netdev_priv(ndev);
3406         int ret;
3407
3408         napi_enable(&mdp->napi);
3409
3410         /* Disable MagicPacket */
3411         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3412
3413         /* The device needs to be reset to restore MagicPacket logic
3414          * for next wakeup. If we close and open the device it will
3415          * both be reset and all registers restored. This is what
3416          * happens during suspend and resume without WoL enabled.
3417          */
3418         ret = sh_eth_close(ndev);
3419         if (ret < 0)
3420                 return ret;
3421         ret = sh_eth_open(ndev);
3422         if (ret < 0)
3423                 return ret;
3424
3425         return disable_irq_wake(ndev->irq);
3426 }
3427
3428 static int sh_eth_suspend(struct device *dev)
3429 {
3430         struct net_device *ndev = dev_get_drvdata(dev);
3431         struct sh_eth_private *mdp = netdev_priv(ndev);
3432         int ret = 0;
3433
3434         if (!netif_running(ndev))
3435                 return 0;
3436
3437         netif_device_detach(ndev);
3438
3439         if (mdp->wol_enabled)
3440                 ret = sh_eth_wol_setup(ndev);
3441         else
3442                 ret = sh_eth_close(ndev);
3443
3444         return ret;
3445 }
3446
3447 static int sh_eth_resume(struct device *dev)
3448 {
3449         struct net_device *ndev = dev_get_drvdata(dev);
3450         struct sh_eth_private *mdp = netdev_priv(ndev);
3451         int ret = 0;
3452
3453         if (!netif_running(ndev))
3454                 return 0;
3455
3456         if (mdp->wol_enabled)
3457                 ret = sh_eth_wol_restore(ndev);
3458         else
3459                 ret = sh_eth_open(ndev);
3460
3461         if (ret < 0)
3462                 return ret;
3463
3464         netif_device_attach(ndev);
3465
3466         return ret;
3467 }
3468 #endif
3469
3470 static int sh_eth_runtime_nop(struct device *dev)
3471 {
3472         /* Runtime PM callback shared between ->runtime_suspend()
3473          * and ->runtime_resume(). Simply returns success.
3474          *
3475          * This driver re-initializes all registers after
3476          * pm_runtime_get_sync() anyway so there is no need
3477          * to save and restore registers here.
3478          */
3479         return 0;
3480 }
3481
3482 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3483         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3484         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3485 };
3486 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3487 #else
3488 #define SH_ETH_PM_OPS NULL
3489 #endif
3490
3491 static const struct platform_device_id sh_eth_id_table[] = {
3492         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3493         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3494         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3495         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3496         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3497         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3498         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3499         { }
3500 };
3501 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3502
3503 static struct platform_driver sh_eth_driver = {
3504         .probe = sh_eth_drv_probe,
3505         .remove = sh_eth_drv_remove,
3506         .id_table = sh_eth_id_table,
3507         .driver = {
3508                    .name = CARDNAME,
3509                    .pm = SH_ETH_PM_OPS,
3510                    .of_match_table = of_match_ptr(sh_eth_match_table),
3511         },
3512 };
3513
3514 module_platform_driver(sh_eth_driver);
3515
3516 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3517 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3518 MODULE_LICENSE("GPL v2");