drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 enum efx_ef10_default_filters {
  64         EFX_EF10_BCAST,
  65         EFX_EF10_UCDEF,
  66         EFX_EF10_MCDEF,
  67         EFX_EF10_VXLAN4_UCDEF,
  68         EFX_EF10_VXLAN4_MCDEF,
  69         EFX_EF10_VXLAN6_UCDEF,
  70         EFX_EF10_VXLAN6_MCDEF,
  71         EFX_EF10_NVGRE4_UCDEF,
  72         EFX_EF10_NVGRE4_MCDEF,
  73         EFX_EF10_NVGRE6_UCDEF,
  74         EFX_EF10_NVGRE6_MCDEF,
  75         EFX_EF10_GENEVE4_UCDEF,
  76         EFX_EF10_GENEVE4_MCDEF,
  77         EFX_EF10_GENEVE6_UCDEF,
  78         EFX_EF10_GENEVE6_MCDEF,
  79
  80         EFX_EF10_NUM_DEFAULT_FILTERS
  81 };
  82
  83 /* Per-VLAN filters information */
  84 struct efx_ef10_filter_vlan {
  85         struct list_head list;
  86         u16 vid;
  87         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  88         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  89         u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
  90 };
  91
  92 struct efx_ef10_dev_addr {
  93         u8 addr[ETH_ALEN];
  94 };
  95
  96 struct efx_ef10_filter_table {
  97 /* The MCDI match masks supported by this fw & hw, in order of priority */
  98         u32 rx_match_mcdi_flags[
  99                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
 100         unsigned int rx_match_count;
 101
 102         struct {
 103                 unsigned long spec;     /* pointer to spec plus flag bits */
 104 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
 105  * used to mark and sweep MAC filters for the device address lists.
 106  */
 107 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
 108 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
 109 #define EFX_EF10_FILTER_FLAGS           3UL
 110                 u64 handle;             /* firmware handle */
 111         } *entry;
 112         wait_queue_head_t waitq;
 113 /* Shadow of net_device address lists, guarded by mac_lock */
 114         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
 115         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
 116         int dev_uc_count;
 117         int dev_mc_count;
 118         bool uc_promisc;
 119         bool mc_promisc;
 120 /* Whether in multicast promiscuous mode when last changed */
 121         bool mc_promisc_last;
 122         bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
 123         bool vlan_filter;
 124         struct list_head vlan_list;
 125 };
 126
 127 /* An arbitrary search limit for the software hash table */
 128 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 129
 130 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 131 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 132 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 133 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 134                                               struct efx_ef10_filter_vlan *vlan);
 135 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 136 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
 137
 138 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
 139 {
 140         WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
 141         return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
 142 }
 143
 144 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
 145 {
 146         return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
 147 }
 148
 149 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
 150 {
 151         return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
 152 }
 153
 154 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 155 {
 156         efx_dword_t reg;
 157
 158         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 159         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 160                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 161 }
 162
 163 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 164 {
 165         int bar;
 166
 167         bar = efx->type->mem_bar;
 168         return resource_size(&efx->pci_dev->resource[bar]);
 169 }
 170
 171 static bool efx_ef10_is_vf(struct efx_nic *efx)
 172 {
 173         return efx->type->is_vf;
 174 }
 175
 176 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 177 {
 178         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 179         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 180         size_t outlen;
 181         int rc;
 182
 183         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 184                           sizeof(outbuf), &outlen);
 185         if (rc)
 186                 return rc;
 187         if (outlen < sizeof(outbuf))
 188                 return -EIO;
 189
 190         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 191         return 0;
 192 }
 193
 194 #ifdef CONFIG_SFC_SRIOV
 195 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 196 {
 197         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 198         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 199         size_t outlen;
 200         int rc;
 201
 202         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 203                           sizeof(outbuf), &outlen);
 204         if (rc)
 205                 return rc;
 206         if (outlen < sizeof(outbuf))
 207                 return -EIO;
 208
 209         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 210         return 0;
 211 }
 212 #endif
 213
 214 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 215 {
 216         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
 217         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 218         size_t outlen;
 219         int rc;
 220
 221         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 222
 223         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 224                           outbuf, sizeof(outbuf), &outlen);
 225         if (rc)
 226                 return rc;
 227         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 228                 netif_err(efx, drv, efx->net_dev,
 229                           "unable to read datapath firmware capabilities\n");
 230                 return -EIO;
 231         }
 232
 233         nic_data->datapath_caps =
 234                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 235
 236         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 237                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 238                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 239                 nic_data->piobuf_size = MCDI_WORD(outbuf,
 240                                 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
 241         } else {
 242                 nic_data->datapath_caps2 = 0;
 243                 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
 244         }
 245
 246         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 247          */
 248         nic_data->rx_dpcpu_fw_id =
 249                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 250         nic_data->tx_dpcpu_fw_id =
 251                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 252
 253         if (!(nic_data->datapath_caps &
 254               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 255                 netif_err(efx, probe, efx->net_dev,
 256                           "current firmware does not support an RX prefix\n");
 257                 return -ENODEV;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 264 {
 265         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 266         int rc;
 267
 268         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 269                           outbuf, sizeof(outbuf), NULL);
 270         if (rc)
 271                 return rc;
 272         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 273         return rc > 0 ? rc : -ERANGE;
 274 }
 275
 276 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 277 {
 278         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 279         unsigned int implemented;
 280         unsigned int enabled;
 281         int rc;
 282
 283         nic_data->workaround_35388 = false;
 284         nic_data->workaround_61265 = false;
 285
 286         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 287
 288         if (rc == -ENOSYS) {
 289                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 290                 rc = 0;
 291         } else if (rc == 0) {
 292                 /* Bug61265 workaround is always enabled if implemented. */
 293                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 294                         nic_data->workaround_61265 = true;
 295
 296                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 297                         nic_data->workaround_35388 = true;
 298                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 299                         /* Workaround is implemented but not enabled.
 300                          * Try to enable it.
 301                          */
 302                         rc = efx_mcdi_set_workaround(efx,
 303                                                      MC_CMD_WORKAROUND_BUG35388,
 304                                                      true, NULL);
 305                         if (rc == 0)
 306                                 nic_data->workaround_35388 = true;
 307                         /* If we failed to set the workaround just carry on. */
 308                         rc = 0;
 309                 }
 310         }
 311
 312         netif_dbg(efx, probe, efx->net_dev,
 313                   "workaround for bug 35388 is %sabled\n",
 314                   nic_data->workaround_35388 ? "en" : "dis");
 315         netif_dbg(efx, probe, efx->net_dev,
 316                   "workaround for bug 61265 is %sabled\n",
 317                   nic_data->workaround_61265 ? "en" : "dis");
 318
 319         return rc;
 320 }
 321
 322 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 323                                           const efx_dword_t *data)
 324 {
 325         unsigned int max_count;
 326
 327         if (EFX_EF10_WORKAROUND_61265(efx)) {
 328                 efx->timer_quantum_ns = MCDI_DWORD(data,
 329                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 330                 efx->timer_max_ns = MCDI_DWORD(data,
 331                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 332         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 333                 efx->timer_quantum_ns = MCDI_DWORD(data,
 334                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 335                 max_count = MCDI_DWORD(data,
 336                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 337                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 338         } else {
 339                 efx->timer_quantum_ns = MCDI_DWORD(data,
 340                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 341                 max_count = MCDI_DWORD(data,
 342                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 343                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 344         }
 345
 346         netif_dbg(efx, probe, efx->net_dev,
 347                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 348                   efx->timer_quantum_ns, efx->timer_max_ns);
 349 }
 350
 351 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 352 {
 353         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 354         int rc;
 355
 356         rc = efx_ef10_get_timer_workarounds(efx);
 357         if (rc)
 358                 return rc;
 359
 360         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 361                                 outbuf, sizeof(outbuf), NULL);
 362
 363         if (rc == 0) {
 364                 efx_ef10_process_timer_config(efx, outbuf);
 365         } else if (rc == -ENOSYS || rc == -EPERM) {
 366                 /* Not available - fall back to Huntington defaults. */
 367                 unsigned int quantum;
 368
 369                 rc = efx_ef10_get_sysclk_freq(efx);
 370                 if (rc < 0)
 371                         return rc;
 372
 373                 quantum = 1536000 / rc; /* 1536 cycles */
 374                 efx->timer_quantum_ns = quantum;
 375                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 376                 rc = 0;
 377         } else {
 378                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 379                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 380                                        NULL, 0, rc);
 381         }
 382
 383         return rc;
 384 }
 385
 386 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 387 {
 388         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 389         size_t outlen;
 390         int rc;
 391
 392         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 393
 394         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 395                           outbuf, sizeof(outbuf), &outlen);
 396         if (rc)
 397                 return rc;
 398         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 399                 return -EIO;
 400
 401         ether_addr_copy(mac_address,
 402                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 403         return 0;
 404 }
 405
 406 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 407 {
 408         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 409         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 410         size_t outlen;
 411         int num_addrs, rc;
 412
 413         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 414                        EVB_PORT_ID_ASSIGNED);
 415         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 416                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 417
 418         if (rc)
 419                 return rc;
 420         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 421                 return -EIO;
 422
 423         num_addrs = MCDI_DWORD(outbuf,
 424                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 425
 426         WARN_ON(num_addrs != 1);
 427
 428         ether_addr_copy(mac_address,
 429                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 430
 431         return 0;
 432 }
 433
 434 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 435                                                struct device_attribute *attr,
 436                                                char *buf)
 437 {
 438         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 439
 440         return sprintf(buf, "%d\n",
 441                        ((efx->mcdi->fn_flags) &
 442                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 443                        ? 1 : 0);
 444 }
 445
 446 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 447                                           struct device_attribute *attr,
 448                                           char *buf)
 449 {
 450         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 451
 452         return sprintf(buf, "%d\n",
 453                        ((efx->mcdi->fn_flags) &
 454                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 455                        ? 1 : 0);
 456 }
 457
 458 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 459 {
 460         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 461         struct efx_ef10_vlan *vlan;
 462
 463         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 464
 465         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 466                 if (vlan->vid == vid)
 467                         return vlan;
 468         }
 469
 470         return NULL;
 471 }
 472
 473 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 474 {
 475         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 476         struct efx_ef10_vlan *vlan;
 477         int rc;
 478
 479         mutex_lock(&nic_data->vlan_lock);
 480
 481         vlan = efx_ef10_find_vlan(efx, vid);
 482         if (vlan) {
 483                 /* We add VID 0 on init. 8021q adds it on module init
 484                  * for all interfaces with VLAN filtring feature.
 485                  */
 486                 if (vid == 0)
 487                         goto done_unlock;
 488                 netif_warn(efx, drv, efx->net_dev,
 489                            "VLAN %u already added\n", vid);
 490                 rc = -EALREADY;
 491                 goto fail_exist;
 492         }
 493
 494         rc = -ENOMEM;
 495         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 496         if (!vlan)
 497                 goto fail_alloc;
 498
 499         vlan->vid = vid;
 500
 501         list_add_tail(&vlan->list, &nic_data->vlan_list);
 502
 503         if (efx->filter_state) {
 504                 mutex_lock(&efx->mac_lock);
 505                 down_write(&efx->filter_sem);
 506                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 507                 up_write(&efx->filter_sem);
 508                 mutex_unlock(&efx->mac_lock);
 509                 if (rc)
 510                         goto fail_filter_add_vlan;
 511         }
 512
 513 done_unlock:
 514         mutex_unlock(&nic_data->vlan_lock);
 515         return 0;
 516
 517 fail_filter_add_vlan:
 518         list_del(&vlan->list);
 519         kfree(vlan);
 520 fail_alloc:
 521 fail_exist:
 522         mutex_unlock(&nic_data->vlan_lock);
 523         return rc;
 524 }
 525
 526 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 527                                        struct efx_ef10_vlan *vlan)
 528 {
 529         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 530
 531         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 532
 533         if (efx->filter_state) {
 534                 down_write(&efx->filter_sem);
 535                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 536                 up_write(&efx->filter_sem);
 537         }
 538
 539         list_del(&vlan->list);
 540         kfree(vlan);
 541 }
 542
 543 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 544 {
 545         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 546         struct efx_ef10_vlan *vlan;
 547         int rc = 0;
 548
 549         /* 8021q removes VID 0 on module unload for all interfaces
 550          * with VLAN filtering feature. We need to keep it to receive
 551          * untagged traffic.
 552          */
 553         if (vid == 0)
 554                 return 0;
 555
 556         mutex_lock(&nic_data->vlan_lock);
 557
 558         vlan = efx_ef10_find_vlan(efx, vid);
 559         if (!vlan) {
 560                 netif_err(efx, drv, efx->net_dev,
 561                           "VLAN %u to be deleted not found\n", vid);
 562                 rc = -ENOENT;
 563         } else {
 564                 efx_ef10_del_vlan_internal(efx, vlan);
 565         }
 566
 567         mutex_unlock(&nic_data->vlan_lock);
 568
 569         return rc;
 570 }
 571
 572 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 573 {
 574         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 575         struct efx_ef10_vlan *vlan, *next_vlan;
 576
 577         mutex_lock(&nic_data->vlan_lock);
 578         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 579                 efx_ef10_del_vlan_internal(efx, vlan);
 580         mutex_unlock(&nic_data->vlan_lock);
 581 }
 582
 583 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 584                    NULL);
 585 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 586
 587 static int efx_ef10_probe(struct efx_nic *efx)
 588 {
 589         struct efx_ef10_nic_data *nic_data;
 590         int i, rc;
 591
 592         /* We can have one VI for each 8K region.  However, until we
 593          * use TX option descriptors we need two TX queues per channel.
 594          */
 595         efx->max_channels = min_t(unsigned int,
 596                                   EFX_MAX_CHANNELS,
 597                                   efx_ef10_mem_map_size(efx) /
 598                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 599         efx->max_tx_channels = efx->max_channels;
 600         if (WARN_ON(efx->max_channels == 0))
 601                 return -EIO;
 602
 603         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 604         if (!nic_data)
 605                 return -ENOMEM;
 606         efx->nic_data = nic_data;
 607
 608         /* we assume later that we can copy from this buffer in dwords */
 609         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 610
 611         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 612                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 613         if (rc)
 614                 goto fail1;
 615
 616         /* Get the MC's warm boot count.  In case it's rebooting right
 617          * now, be prepared to retry.
 618          */
 619         i = 0;
 620         for (;;) {
 621                 rc = efx_ef10_get_warm_boot_count(efx);
 622                 if (rc >= 0)
 623                         break;
 624                 if (++i == 5)
 625                         goto fail2;
 626                 ssleep(1);
 627         }
 628         nic_data->warm_boot_count = rc;
 629
 630         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 631
 632         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 633
 634         /* In case we're recovering from a crash (kexec), we want to
 635          * cancel any outstanding request by the previous user of this
 636          * function.  We send a special message using the least
 637          * significant bits of the 'high' (doorbell) register.
 638          */
 639         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 640
 641         rc = efx_mcdi_init(efx);
 642         if (rc)
 643                 goto fail2;
 644
 645         mutex_init(&nic_data->udp_tunnels_lock);
 646
 647         /* Reset (most) configuration for this function */
 648         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 649         if (rc)
 650                 goto fail3;
 651
 652         /* Enable event logging */
 653         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 654         if (rc)
 655                 goto fail3;
 656
 657         rc = device_create_file(&efx->pci_dev->dev,
 658                                 &dev_attr_link_control_flag);
 659         if (rc)
 660                 goto fail3;
 661
 662         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 663         if (rc)
 664                 goto fail4;
 665
 666         rc = efx_ef10_get_pf_index(efx);
 667         if (rc)
 668                 goto fail5;
 669
 670         rc = efx_ef10_init_datapath_caps(efx);
 671         if (rc < 0)
 672                 goto fail5;
 673
 674         efx->rx_packet_len_offset =
 675                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 676
 677         rc = efx_mcdi_port_get_number(efx);
 678         if (rc < 0)
 679                 goto fail5;
 680         efx->port_num = rc;
 681
 682         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 683         if (rc)
 684                 goto fail5;
 685
 686         rc = efx_ef10_get_timer_config(efx);
 687         if (rc < 0)
 688                 goto fail5;
 689
 690         rc = efx_mcdi_mon_probe(efx);
 691         if (rc && rc != -EPERM)
 692                 goto fail5;
 693
 694         efx_ptp_probe(efx, NULL);
 695
 696 #ifdef CONFIG_SFC_SRIOV
 697         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 698                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 699                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 700
 701                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 702         } else
 703 #endif
 704                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 705
 706         INIT_LIST_HEAD(&nic_data->vlan_list);
 707         mutex_init(&nic_data->vlan_lock);
 708
 709         /* Add unspecified VID to support VLAN filtering being disabled */
 710         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 711         if (rc)
 712                 goto fail_add_vid_unspec;
 713
 714         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 715          * traffic.  It is added automatically if 8021q module is loaded,
 716          * but we can't rely on it since module may be not loaded.
 717          */
 718         rc = efx_ef10_add_vlan(efx, 0);
 719         if (rc)
 720                 goto fail_add_vid_0;
 721
 722         return 0;
 723
 724 fail_add_vid_0:
 725         efx_ef10_cleanup_vlans(efx);
 726 fail_add_vid_unspec:
 727         mutex_destroy(&nic_data->vlan_lock);
 728         efx_ptp_remove(efx);
 729         efx_mcdi_mon_remove(efx);
 730 fail5:
 731         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 732 fail4:
 733         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 734 fail3:
 735         efx_mcdi_detach(efx);
 736
 737         mutex_lock(&nic_data->udp_tunnels_lock);
 738         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
 739         (void)efx_ef10_set_udp_tnl_ports(efx, true);
 740         mutex_unlock(&nic_data->udp_tunnels_lock);
 741         mutex_destroy(&nic_data->udp_tunnels_lock);
 742
 743         efx_mcdi_fini(efx);
 744 fail2:
 745         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 746 fail1:
 747         kfree(nic_data);
 748         efx->nic_data = NULL;
 749         return rc;
 750 }
 751
 752 static int efx_ef10_free_vis(struct efx_nic *efx)
 753 {
 754         MCDI_DECLARE_BUF_ERR(outbuf);
 755         size_t outlen;
 756         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 757                                     outbuf, sizeof(outbuf), &outlen);
 758
 759         /* -EALREADY means nothing to free, so ignore */
 760         if (rc == -EALREADY)
 761                 rc = 0;
 762         if (rc)
 763                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 764                                        rc);
 765         return rc;
 766 }
 767
 768 #ifdef EFX_USE_PIO
 769
 770 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 771 {
 772         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 773         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 774         unsigned int i;
 775         int rc;
 776
 777         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 778
 779         for (i = 0; i < nic_data->n_piobufs; i++) {
 780                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 781                                nic_data->piobuf_handle[i]);
 782                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 783                                   NULL, 0, NULL);
 784                 WARN_ON(rc);
 785         }
 786
 787         nic_data->n_piobufs = 0;
 788 }
 789
 790 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 791 {
 792         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 793         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 794         unsigned int i;
 795         size_t outlen;
 796         int rc = 0;
 797
 798         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 799
 800         for (i = 0; i < n; i++) {
 801                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 802                                         outbuf, sizeof(outbuf), &outlen);
 803                 if (rc) {
 804                         /* Don't display the MC error if we didn't have space
 805                          * for a VF.
 806                          */
 807                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 808                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 809                                                        0, outbuf, outlen, rc);
 810                         break;
 811                 }
 812                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 813                         rc = -EIO;
 814                         break;
 815                 }
 816                 nic_data->piobuf_handle[i] =
 817                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 818                 netif_dbg(efx, probe, efx->net_dev,
 819                           "allocated PIO buffer %u handle %x\n", i,
 820                           nic_data->piobuf_handle[i]);
 821         }
 822
 823         nic_data->n_piobufs = i;
 824         if (rc)
 825                 efx_ef10_free_piobufs(efx);
 826         return rc;
 827 }
 828
 829 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 830 {
 831         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 832         MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
 833         struct efx_channel *channel;
 834         struct efx_tx_queue *tx_queue;
 835         unsigned int offset, index;
 836         int rc;
 837
 838         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 839         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 840
 841         /* Link a buffer to each VI in the write-combining mapping */
 842         for (index = 0; index < nic_data->n_piobufs; ++index) {
 843                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 844                                nic_data->piobuf_handle[index]);
 845                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 846                                nic_data->pio_write_vi_base + index);
 847                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 848                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 849                                   NULL, 0, NULL);
 850                 if (rc) {
 851                         netif_err(efx, drv, efx->net_dev,
 852                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 853                                   nic_data->pio_write_vi_base + index, index,
 854                                   rc);
 855                         goto fail;
 856                 }
 857                 netif_dbg(efx, probe, efx->net_dev,
 858                           "linked VI %u to PIO buffer %u\n",
 859                           nic_data->pio_write_vi_base + index, index);
 860         }
 861
 862         /* Link a buffer to each TX queue */
 863         efx_for_each_channel(channel, efx) {
 864                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 865                         /* We assign the PIO buffers to queues in
 866                          * reverse order to allow for the following
 867                          * special case.
 868                          */
 869                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 870                                    tx_queue->channel->channel - 1) *
 871                                   efx_piobuf_size);
 872                         index = offset / nic_data->piobuf_size;
 873                         offset = offset % nic_data->piobuf_size;
 874
 875                         /* When the host page size is 4K, the first
 876                          * host page in the WC mapping may be within
 877                          * the same VI page as the last TX queue.  We
 878                          * can only link one buffer to each VI.
 879                          */
 880                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 881                                 BUG_ON(index != 0);
 882                                 rc = 0;
 883                         } else {
 884                                 MCDI_SET_DWORD(inbuf,
 885                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 886                                                nic_data->piobuf_handle[index]);
 887                                 MCDI_SET_DWORD(inbuf,
 888                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 889                                                tx_queue->queue);
 890                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 891                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 892                                                   NULL, 0, NULL);
 893                         }
 894
 895                         if (rc) {
 896                                 /* This is non-fatal; the TX path just
 897                                  * won't use PIO for this queue
 898                                  */
 899                                 netif_err(efx, drv, efx->net_dev,
 900                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 901                                           tx_queue->queue, index, rc);
 902                                 tx_queue->piobuf = NULL;
 903                         } else {
 904                                 tx_queue->piobuf =
 905                                         nic_data->pio_write_base +
 906                                         index * EFX_VI_PAGE_SIZE + offset;
 907                                 tx_queue->piobuf_offset = offset;
 908                                 netif_dbg(efx, probe, efx->net_dev,
 909                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 910                                           tx_queue->queue, index,
 911                                           tx_queue->piobuf_offset,
 912                                           tx_queue->piobuf);
 913                         }
 914                 }
 915         }
 916
 917         return 0;
 918
 919 fail:
 920         /* inbuf was defined for MC_CMD_LINK_PIOBUF.  We can use the same
 921          * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
 922          */
 923         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
 924         while (index--) {
 925                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 926                                nic_data->pio_write_vi_base + index);
 927                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 928                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 929                              NULL, 0, NULL);
 930         }
 931         return rc;
 932 }
 933
 934 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 935 {
 936         struct efx_channel *channel;
 937         struct efx_tx_queue *tx_queue;
 938
 939         /* All our existing PIO buffers went away */
 940         efx_for_each_channel(channel, efx)
 941                 efx_for_each_channel_tx_queue(tx_queue, channel)
 942                         tx_queue->piobuf = NULL;
 943 }
 944
 945 #else /* !EFX_USE_PIO */
 946
 947 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 948 {
 949         return n == 0 ? 0 : -ENOBUFS;
 950 }
 951
 952 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 953 {
 954         return 0;
 955 }
 956
 957 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 958 {
 959 }
 960
 961 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 962 {
 963 }
 964
 965 #endif /* EFX_USE_PIO */
 966
 967 static void efx_ef10_remove(struct efx_nic *efx)
 968 {
 969         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 970         int rc;
 971
 972 #ifdef CONFIG_SFC_SRIOV
 973         struct efx_ef10_nic_data *nic_data_pf;
 974         struct pci_dev *pci_dev_pf;
 975         struct efx_nic *efx_pf;
 976         struct ef10_vf *vf;
 977
 978         if (efx->pci_dev->is_virtfn) {
 979                 pci_dev_pf = efx->pci_dev->physfn;
 980                 if (pci_dev_pf) {
 981                         efx_pf = pci_get_drvdata(pci_dev_pf);
 982                         nic_data_pf = efx_pf->nic_data;
 983                         vf = nic_data_pf->vf + nic_data->vf_index;
 984                         vf->efx = NULL;
 985                 } else
 986                         netif_info(efx, drv, efx->net_dev,
 987                                    "Could not get the PF id from VF\n");
 988         }
 989 #endif
 990
 991         efx_ef10_cleanup_vlans(efx);
 992         mutex_destroy(&nic_data->vlan_lock);
 993
 994         efx_ptp_remove(efx);
 995
 996         efx_mcdi_mon_remove(efx);
 997
 998         efx_ef10_rx_free_indir_table(efx);
 999
1000         if (nic_data->wc_membase)
1001                 iounmap(nic_data->wc_membase);
1002
1003         rc = efx_ef10_free_vis(efx);
1004         WARN_ON(rc != 0);
1005
1006         if (!nic_data->must_restore_piobufs)
1007                 efx_ef10_free_piobufs(efx);
1008
1009         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1010         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1011
1012         efx_mcdi_detach(efx);
1013
1014         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1015         mutex_lock(&nic_data->udp_tunnels_lock);
1016         (void)efx_ef10_set_udp_tnl_ports(efx, true);
1017         mutex_unlock(&nic_data->udp_tunnels_lock);
1018
1019         mutex_destroy(&nic_data->udp_tunnels_lock);
1020
1021         efx_mcdi_fini(efx);
1022         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1023         kfree(nic_data);
1024 }
1025
1026 static int efx_ef10_probe_pf(struct efx_nic *efx)
1027 {
1028         return efx_ef10_probe(efx);
1029 }
1030
1031 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1032                             u32 *port_flags, u32 *vadaptor_flags,
1033                             unsigned int *vlan_tags)
1034 {
1035         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1036         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1037         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1038         size_t outlen;
1039         int rc;
1040
1041         if (nic_data->datapath_caps &
1042             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1043                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1044                                port_id);
1045
1046                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1047                                   outbuf, sizeof(outbuf), &outlen);
1048                 if (rc)
1049                         return rc;
1050
1051                 if (outlen < sizeof(outbuf)) {
1052                         rc = -EIO;
1053                         return rc;
1054                 }
1055         }
1056
1057         if (port_flags)
1058                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1059         if (vadaptor_flags)
1060                 *vadaptor_flags =
1061                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1062         if (vlan_tags)
1063                 *vlan_tags =
1064                         MCDI_DWORD(outbuf,
1065                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1066
1067         return 0;
1068 }
1069
1070 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1071 {
1072         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1073
1074         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1075         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1076                             NULL, 0, NULL);
1077 }
1078
1079 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1080 {
1081         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1082
1083         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1084         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1085                             NULL, 0, NULL);
1086 }
1087
1088 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1089                            unsigned int port_id, u8 *mac)
1090 {
1091         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1092
1093         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1094         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1095
1096         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1097                             sizeof(inbuf), NULL, 0, NULL);
1098 }
1099
1100 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1101                            unsigned int port_id, u8 *mac)
1102 {
1103         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1104
1105         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1106         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1107
1108         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1109                             sizeof(inbuf), NULL, 0, NULL);
1110 }
1111
1112 #ifdef CONFIG_SFC_SRIOV
1113 static int efx_ef10_probe_vf(struct efx_nic *efx)
1114 {
1115         int rc;
1116         struct pci_dev *pci_dev_pf;
1117
1118         /* If the parent PF has no VF data structure, it doesn't know about this
1119          * VF so fail probe.  The VF needs to be re-created.  This can happen
1120          * if the PF driver is unloaded while the VF is assigned to a guest.
1121          */
1122         pci_dev_pf = efx->pci_dev->physfn;
1123         if (pci_dev_pf) {
1124                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1125                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1126
1127                 if (!nic_data_pf->vf) {
1128                         netif_info(efx, drv, efx->net_dev,
1129                                    "The VF cannot link to its parent PF; "
1130                                    "please destroy and re-create the VF\n");
1131                         return -EBUSY;
1132                 }
1133         }
1134
1135         rc = efx_ef10_probe(efx);
1136         if (rc)
1137                 return rc;
1138
1139         rc = efx_ef10_get_vf_index(efx);
1140         if (rc)
1141                 goto fail;
1142
1143         if (efx->pci_dev->is_virtfn) {
1144                 if (efx->pci_dev->physfn) {
1145                         struct efx_nic *efx_pf =
1146                                 pci_get_drvdata(efx->pci_dev->physfn);
1147                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1148                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1149
1150                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1151                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1152                                 efx->pci_dev;
1153                 } else
1154                         netif_info(efx, drv, efx->net_dev,
1155                                    "Could not get the PF id from VF\n");
1156         }
1157
1158         return 0;
1159
1160 fail:
1161         efx_ef10_remove(efx);
1162         return rc;
1163 }
1164 #else
1165 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1166 {
1167         return 0;
1168 }
1169 #endif
1170
1171 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1172                               unsigned int min_vis, unsigned int max_vis)
1173 {
1174         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1175         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1176         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1177         size_t outlen;
1178         int rc;
1179
1180         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1181         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1182         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1183                           outbuf, sizeof(outbuf), &outlen);
1184         if (rc != 0)
1185                 return rc;
1186
1187         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1188                 return -EIO;
1189
1190         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1191                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1192
1193         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1194         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1195         return 0;
1196 }
1197
1198 /* Note that the failure path of this function does not free
1199  * resources, as this will be done by efx_ef10_remove().
1200  */
1201 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1202 {
1203         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1204         unsigned int uc_mem_map_size, wc_mem_map_size;
1205         unsigned int min_vis = max(EFX_TXQ_TYPES,
1206                                    efx_separate_tx_channels ? 2 : 1);
1207         unsigned int channel_vis, pio_write_vi_base, max_vis;
1208         void __iomem *membase;
1209         int rc;
1210
1211         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1212
1213 #ifdef EFX_USE_PIO
1214         /* Try to allocate PIO buffers if wanted and if the full
1215          * number of PIO buffers would be sufficient to allocate one
1216          * copy-buffer per TX channel.  Failure is non-fatal, as there
1217          * are only a small number of PIO buffers shared between all
1218          * functions of the controller.
1219          */
1220         if (efx_piobuf_size != 0 &&
1221             nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1222             efx->n_tx_channels) {
1223                 unsigned int n_piobufs =
1224                         DIV_ROUND_UP(efx->n_tx_channels,
1225                                      nic_data->piobuf_size / efx_piobuf_size);
1226
1227                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1228                 if (rc == -ENOSPC)
1229                         netif_dbg(efx, probe, efx->net_dev,
1230                                   "out of PIO buffers; cannot allocate more\n");
1231                 else if (rc == -EPERM)
1232                         netif_dbg(efx, probe, efx->net_dev,
1233                                   "not permitted to allocate PIO buffers\n");
1234                 else if (rc)
1235                         netif_err(efx, probe, efx->net_dev,
1236                                   "failed to allocate PIO buffers (%d)\n", rc);
1237                 else
1238                         netif_dbg(efx, probe, efx->net_dev,
1239                                   "allocated %u PIO buffers\n", n_piobufs);
1240         }
1241 #else
1242         nic_data->n_piobufs = 0;
1243 #endif
1244
1245         /* PIO buffers should be mapped with write-combining enabled,
1246          * and we want to make single UC and WC mappings rather than
1247          * several of each (in fact that's the only option if host
1248          * page size is >4K).  So we may allocate some extra VIs just
1249          * for writing PIO buffers through.
1250          *
1251          * The UC mapping contains (channel_vis - 1) complete VIs and the
1252          * first half of the next VI.  Then the WC mapping begins with
1253          * the second half of this last VI.
1254          */
1255         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1256                                      ER_DZ_TX_PIOBUF);
1257         if (nic_data->n_piobufs) {
1258                 /* pio_write_vi_base rounds down to give the number of complete
1259                  * VIs inside the UC mapping.
1260                  */
1261                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1262                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1263                                                nic_data->n_piobufs) *
1264                                               EFX_VI_PAGE_SIZE) -
1265                                    uc_mem_map_size);
1266                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1267         } else {
1268                 pio_write_vi_base = 0;
1269                 wc_mem_map_size = 0;
1270                 max_vis = channel_vis;
1271         }
1272
1273         /* In case the last attached driver failed to free VIs, do it now */
1274         rc = efx_ef10_free_vis(efx);
1275         if (rc != 0)
1276                 return rc;
1277
1278         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1279         if (rc != 0)
1280                 return rc;
1281
1282         if (nic_data->n_allocated_vis < channel_vis) {
1283                 netif_info(efx, drv, efx->net_dev,
1284                            "Could not allocate enough VIs to satisfy RSS"
1285                            " requirements. Performance may not be optimal.\n");
1286                 /* We didn't get the VIs to populate our channels.
1287                  * We could keep what we got but then we'd have more
1288                  * interrupts than we need.
1289                  * Instead calculate new max_channels and restart
1290                  */
1291                 efx->max_channels = nic_data->n_allocated_vis;
1292                 efx->max_tx_channels =
1293                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1294
1295                 efx_ef10_free_vis(efx);
1296                 return -EAGAIN;
1297         }
1298
1299         /* If we didn't get enough VIs to map all the PIO buffers, free the
1300          * PIO buffers
1301          */
1302         if (nic_data->n_piobufs &&
1303             nic_data->n_allocated_vis <
1304             pio_write_vi_base + nic_data->n_piobufs) {
1305                 netif_dbg(efx, probe, efx->net_dev,
1306                           "%u VIs are not sufficient to map %u PIO buffers\n",
1307                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1308                 efx_ef10_free_piobufs(efx);
1309         }
1310
1311         /* Shrink the original UC mapping of the memory BAR */
1312         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1313         if (!membase) {
1314                 netif_err(efx, probe, efx->net_dev,
1315                           "could not shrink memory BAR to %x\n",
1316                           uc_mem_map_size);
1317                 return -ENOMEM;
1318         }
1319         iounmap(efx->membase);
1320         efx->membase = membase;
1321
1322         /* Set up the WC mapping if needed */
1323         if (wc_mem_map_size) {
1324                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1325                                                   uc_mem_map_size,
1326                                                   wc_mem_map_size);
1327                 if (!nic_data->wc_membase) {
1328                         netif_err(efx, probe, efx->net_dev,
1329                                   "could not allocate WC mapping of size %x\n",
1330                                   wc_mem_map_size);
1331                         return -ENOMEM;
1332                 }
1333                 nic_data->pio_write_vi_base = pio_write_vi_base;
1334                 nic_data->pio_write_base =
1335                         nic_data->wc_membase +
1336                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1337                          uc_mem_map_size);
1338
1339                 rc = efx_ef10_link_piobufs(efx);
1340                 if (rc)
1341                         efx_ef10_free_piobufs(efx);
1342         }
1343
1344         netif_dbg(efx, probe, efx->net_dev,
1345                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1346                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1347                   nic_data->wc_membase, wc_mem_map_size);
1348
1349         return 0;
1350 }
1351
1352 static int efx_ef10_init_nic(struct efx_nic *efx)
1353 {
1354         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1355         int rc;
1356
1357         if (nic_data->must_check_datapath_caps) {
1358                 rc = efx_ef10_init_datapath_caps(efx);
1359                 if (rc)
1360                         return rc;
1361                 nic_data->must_check_datapath_caps = false;
1362         }
1363
1364         if (nic_data->must_realloc_vis) {
1365                 /* We cannot let the number of VIs change now */
1366                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1367                                         nic_data->n_allocated_vis);
1368                 if (rc)
1369                         return rc;
1370                 nic_data->must_realloc_vis = false;
1371         }
1372
1373         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1374                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1375                 if (rc == 0) {
1376                         rc = efx_ef10_link_piobufs(efx);
1377                         if (rc)
1378                                 efx_ef10_free_piobufs(efx);
1379                 }
1380
1381                 /* Log an error on failure, but this is non-fatal.
1382                  * Permission errors are less important - we've presumably
1383                  * had the PIO buffer licence removed.
1384                  */
1385                 if (rc == -EPERM)
1386                         netif_dbg(efx, drv, efx->net_dev,
1387                                   "not permitted to restore PIO buffers\n");
1388                 else if (rc)
1389                         netif_err(efx, drv, efx->net_dev,
1390                                   "failed to restore PIO buffers (%d)\n", rc);
1391                 nic_data->must_restore_piobufs = false;
1392         }
1393
1394         /* don't fail init if RSS setup doesn't work */
1395         rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
1396         efx->rss_active = (rc == 0);
1397
1398         return 0;
1399 }
1400
1401 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1402 {
1403         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1404 #ifdef CONFIG_SFC_SRIOV
1405         unsigned int i;
1406 #endif
1407
1408         /* All our allocations have been reset */
1409         nic_data->must_realloc_vis = true;
1410         nic_data->must_restore_filters = true;
1411         nic_data->must_restore_piobufs = true;
1412         efx_ef10_forget_old_piobufs(efx);
1413         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1414
1415         /* Driver-created vswitches and vports must be re-created */
1416         nic_data->must_probe_vswitching = true;
1417         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1418 #ifdef CONFIG_SFC_SRIOV
1419         if (nic_data->vf)
1420                 for (i = 0; i < efx->vf_count; i++)
1421                         nic_data->vf[i].vport_id = 0;
1422 #endif
1423 }
1424
1425 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1426 {
1427         if (reason == RESET_TYPE_MC_FAILURE)
1428                 return RESET_TYPE_DATAPATH;
1429
1430         return efx_mcdi_map_reset_reason(reason);
1431 }
1432
1433 static int efx_ef10_map_reset_flags(u32 *flags)
1434 {
1435         enum {
1436                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1437                                    ETH_RESET_SHARED_SHIFT),
1438                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1439                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1440                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1441                                  ETH_RESET_SHARED_SHIFT)
1442         };
1443
1444         /* We assume for now that our PCI function is permitted to
1445          * reset everything.
1446          */
1447
1448         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1449                 *flags &= ~EF10_RESET_MC;
1450                 return RESET_TYPE_WORLD;
1451         }
1452
1453         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1454                 *flags &= ~EF10_RESET_PORT;
1455                 return RESET_TYPE_ALL;
1456         }
1457
1458         /* no invisible reset implemented */
1459
1460         return -EINVAL;
1461 }
1462
1463 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1464 {
1465         int rc = efx_mcdi_reset(efx, reset_type);
1466
1467         /* Unprivileged functions return -EPERM, but need to return success
1468          * here so that the datapath is brought back up.
1469          */
1470         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1471                 rc = 0;
1472
1473         /* If it was a port reset, trigger reallocation of MC resources.
1474          * Note that on an MC reset nothing needs to be done now because we'll
1475          * detect the MC reset later and handle it then.
1476          * For an FLR, we never get an MC reset event, but the MC has reset all
1477          * resources assigned to us, so we have to trigger reallocation now.
1478          */
1479         if ((reset_type == RESET_TYPE_ALL ||
1480              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1481                 efx_ef10_reset_mc_allocations(efx);
1482         return rc;
1483 }
1484
1485 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1486         [EF10_STAT_ ## ext_name] =                              \
1487         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1488 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1489         [EF10_STAT_ ## int_name] =                              \
1490         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1491 #define EF10_OTHER_STAT(ext_name)                               \
1492         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1493 #define GENERIC_SW_STAT(ext_name)                               \
1494         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1495
1496 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1497         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1498         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1499         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1500         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1501         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1502         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1503         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1504         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1505         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1506         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1507         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1508         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1509         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1510         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1511         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1512         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1513         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1514         EF10_OTHER_STAT(port_rx_good_bytes),
1515         EF10_OTHER_STAT(port_rx_bad_bytes),
1516         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1517         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1518         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1519         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1520         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1521         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1522         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1523         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1524         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1525         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1526         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1527         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1528         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1529         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1530         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1531         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1532         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1533         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1534         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1535         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1536         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1537         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1538         GENERIC_SW_STAT(rx_nodesc_trunc),
1539         GENERIC_SW_STAT(rx_noskb_drops),
1540         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1541         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1542         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1543         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1544         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1545         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1546         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1547         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1548         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1549         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1550         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1551         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1552         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1553         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1554         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1555         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1556         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1557         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1558         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1559         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1560         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1561         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1562         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1563         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1564         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1565         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1566         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1567         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1568         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1569         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1570 };
1571
1572 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1573                                (1ULL << EF10_STAT_port_tx_packets) |    \
1574                                (1ULL << EF10_STAT_port_tx_pause) |      \
1575                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1576                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1577                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1578                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1579                                (1ULL <<                                 \
1580                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1581                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1582                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1583                                (1ULL << EF10_STAT_port_rx_packets) |    \
1584                                (1ULL << EF10_STAT_port_rx_good) |       \
1585                                (1ULL << EF10_STAT_port_rx_bad) |        \
1586                                (1ULL << EF10_STAT_port_rx_pause) |      \
1587                                (1ULL << EF10_STAT_port_rx_control) |    \
1588                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1589                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1590                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1591                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1592                                (1ULL << EF10_STAT_port_rx_64) |         \
1593                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1594                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1595                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1596                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1597                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1598                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1599                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1600                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1601                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1602                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1603                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1604                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1605
1606 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1607  * For a 10G/40G switchable port we do not expose these because they might
1608  * not include all the packets they should.
1609  * On 8000 series NICs these statistics are always provided.
1610  */
1611 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1612                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1613                                  (1ULL << EF10_STAT_port_tx_64) |       \
1614                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1615                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1616                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1617                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1618                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1619                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1620
1621 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1622  * switchable port we do expose these because the errors will otherwise
1623  * be silent.
1624  */
1625 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1626                                   (1ULL << EF10_STAT_port_rx_length_error))
1627
1628 /* These statistics are only provided if the firmware supports the
1629  * capability PM_AND_RXDP_COUNTERS.
1630  */
1631 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1632         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1633         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1634         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1635         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1636         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1637         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1638         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1639         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1640         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1641         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1642         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1643         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1644
1645 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1646 {
1647         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1648         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1649         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1650
1651         if (!(efx->mcdi->fn_flags &
1652               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1653                 return 0;
1654
1655         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1656                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1657                 /* 8000 series have everything even at 40G */
1658                 if (nic_data->datapath_caps2 &
1659                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1660                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1661         } else {
1662                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1663         }
1664
1665         if (nic_data->datapath_caps &
1666             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1667                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1668
1669         return raw_mask;
1670 }
1671
1672 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1673 {
1674         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1675         u64 raw_mask[2];
1676
1677         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1678
1679         /* Only show vadaptor stats when EVB capability is present */
1680         if (nic_data->datapath_caps &
1681             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1682                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1683                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1684         } else {
1685                 raw_mask[1] = 0;
1686         }
1687
1688 #if BITS_PER_LONG == 64
1689         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1690         mask[0] = raw_mask[0];
1691         mask[1] = raw_mask[1];
1692 #else
1693         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1694         mask[0] = raw_mask[0] & 0xffffffff;
1695         mask[1] = raw_mask[0] >> 32;
1696         mask[2] = raw_mask[1] & 0xffffffff;
1697 #endif
1698 }
1699
1700 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1701 {
1702         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1703
1704         efx_ef10_get_stat_mask(efx, mask);
1705         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1706                                       mask, names);
1707 }
1708
1709 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1710                                            struct rtnl_link_stats64 *core_stats)
1711 {
1712         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1713         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1714         u64 *stats = nic_data->stats;
1715         size_t stats_count = 0, index;
1716
1717         efx_ef10_get_stat_mask(efx, mask);
1718
1719         if (full_stats) {
1720                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1721                         if (efx_ef10_stat_desc[index].name) {
1722                                 *full_stats++ = stats[index];
1723                                 ++stats_count;
1724                         }
1725                 }
1726         }
1727
1728         if (!core_stats)
1729                 return stats_count;
1730
1731         if (nic_data->datapath_caps &
1732                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1733                 /* Use vadaptor stats. */
1734                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1735                                          stats[EF10_STAT_rx_multicast] +
1736                                          stats[EF10_STAT_rx_broadcast];
1737                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1738                                          stats[EF10_STAT_tx_multicast] +
1739                                          stats[EF10_STAT_tx_broadcast];
1740                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1741                                        stats[EF10_STAT_rx_multicast_bytes] +
1742                                        stats[EF10_STAT_rx_broadcast_bytes];
1743                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1744                                        stats[EF10_STAT_tx_multicast_bytes] +
1745                                        stats[EF10_STAT_tx_broadcast_bytes];
1746                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1747                                          stats[GENERIC_STAT_rx_noskb_drops];
1748                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1749                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1750                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1751                 core_stats->rx_errors = core_stats->rx_crc_errors;
1752                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1753         } else {
1754                 /* Use port stats. */
1755                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1756                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1757                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1758                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1759                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1760                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1761                                          stats[GENERIC_STAT_rx_noskb_drops];
1762                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1763                 core_stats->rx_length_errors =
1764                                 stats[EF10_STAT_port_rx_gtjumbo] +
1765                                 stats[EF10_STAT_port_rx_length_error];
1766                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1767                 core_stats->rx_frame_errors =
1768                                 stats[EF10_STAT_port_rx_align_error];
1769                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1770                 core_stats->rx_errors = (core_stats->rx_length_errors +
1771                                          core_stats->rx_crc_errors +
1772                                          core_stats->rx_frame_errors);
1773         }
1774
1775         return stats_count;
1776 }
1777
1778 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1779 {
1780         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1781         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1782         __le64 generation_start, generation_end;
1783         u64 *stats = nic_data->stats;
1784         __le64 *dma_stats;
1785
1786         efx_ef10_get_stat_mask(efx, mask);
1787
1788         dma_stats = efx->stats_buffer.addr;
1789
1790         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1791         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1792                 return 0;
1793         rmb();
1794         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1795                              stats, efx->stats_buffer.addr, false);
1796         rmb();
1797         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1798         if (generation_end != generation_start)
1799                 return -EAGAIN;
1800
1801         /* Update derived statistics */
1802         efx_nic_fix_nodesc_drop_stat(efx,
1803                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1804         stats[EF10_STAT_port_rx_good_bytes] =
1805                 stats[EF10_STAT_port_rx_bytes] -
1806                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1807         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1808                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1809         efx_update_sw_stats(efx, stats);
1810         return 0;
1811 }
1812
1813
1814 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1815                                        struct rtnl_link_stats64 *core_stats)
1816 {
1817         int retry;
1818
1819         /* If we're unlucky enough to read statistics during the DMA, wait
1820          * up to 10ms for it to finish (typically takes <500us)
1821          */
1822         for (retry = 0; retry < 100; ++retry) {
1823                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1824                         break;
1825                 udelay(100);
1826         }
1827
1828         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1829 }
1830
1831 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1832 {
1833         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1834         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1835         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1836         __le64 generation_start, generation_end;
1837         u64 *stats = nic_data->stats;
1838         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1839         struct efx_buffer stats_buf;
1840         __le64 *dma_stats;
1841         int rc;
1842
1843         spin_unlock_bh(&efx->stats_lock);
1844
1845         if (in_interrupt()) {
1846                 /* If in atomic context, cannot update stats.  Just update the
1847                  * software stats and return so the caller can continue.
1848                  */
1849                 spin_lock_bh(&efx->stats_lock);
1850                 efx_update_sw_stats(efx, stats);
1851                 return 0;
1852         }
1853
1854         efx_ef10_get_stat_mask(efx, mask);
1855
1856         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1857         if (rc) {
1858                 spin_lock_bh(&efx->stats_lock);
1859                 return rc;
1860         }
1861
1862         dma_stats = stats_buf.addr;
1863         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1864
1865         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1866         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1867                               MAC_STATS_IN_DMA, 1);
1868         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1869         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1870
1871         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1872                                 NULL, 0, NULL);
1873         spin_lock_bh(&efx->stats_lock);
1874         if (rc) {
1875                 /* Expect ENOENT if DMA queues have not been set up */
1876                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1877                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1878                                                sizeof(inbuf), NULL, 0, rc);
1879                 goto out;
1880         }
1881
1882         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1883         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1884                 WARN_ON_ONCE(1);
1885                 goto out;
1886         }
1887         rmb();
1888         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1889                              stats, stats_buf.addr, false);
1890         rmb();
1891         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1892         if (generation_end != generation_start) {
1893                 rc = -EAGAIN;
1894                 goto out;
1895         }
1896
1897         efx_update_sw_stats(efx, stats);
1898 out:
1899         /* releasing a DMA coherent buffer with BH disabled can panic */
1900         spin_unlock_bh(&efx->stats_lock);
1901         efx_nic_free_buffer(efx, &stats_buf);
1902         spin_lock_bh(&efx->stats_lock);
1903         return rc;
1904 }
1905
1906 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1907                                        struct rtnl_link_stats64 *core_stats)
1908 {
1909         if (efx_ef10_try_update_nic_stats_vf(efx))
1910                 return 0;
1911
1912         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1913 }
1914
1915 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1916 {
1917         struct efx_nic *efx = channel->efx;
1918         unsigned int mode, usecs;
1919         efx_dword_t timer_cmd;
1920
1921         if (channel->irq_moderation_us) {
1922                 mode = 3;
1923                 usecs = channel->irq_moderation_us;
1924         } else {
1925                 mode = 0;
1926                 usecs = 0;
1927         }
1928
1929         if (EFX_EF10_WORKAROUND_61265(efx)) {
1930                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1931                 unsigned int ns = usecs * 1000;
1932
1933                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1934                                channel->channel);
1935                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1936                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1937                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1938
1939                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1940                                    inbuf, sizeof(inbuf), 0, NULL, 0);
1941         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1942                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1943
1944                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1945                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1946                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1947                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1948                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1949                                 channel->channel);
1950         } else {
1951                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1952
1953                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1954                                      ERF_DZ_TC_TIMER_VAL, ticks);
1955                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1956                                 channel->channel);
1957         }
1958 }
1959
1960 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1961                                 struct ethtool_wolinfo *wol) {}
1962
1963 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1964 {
1965         return -EOPNOTSUPP;
1966 }
1967
1968 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1969 {
1970         wol->supported = 0;
1971         wol->wolopts = 0;
1972         memset(&wol->sopass, 0, sizeof(wol->sopass));
1973 }
1974
1975 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1976 {
1977         if (type != 0)
1978                 return -EINVAL;
1979         return 0;
1980 }
1981
1982 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1983                                   const efx_dword_t *hdr, size_t hdr_len,
1984                                   const efx_dword_t *sdu, size_t sdu_len)
1985 {
1986         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1987         u8 *pdu = nic_data->mcdi_buf.addr;
1988
1989         memcpy(pdu, hdr, hdr_len);
1990         memcpy(pdu + hdr_len, sdu, sdu_len);
1991         wmb();
1992
1993         /* The hardware provides 'low' and 'high' (doorbell) registers
1994          * for passing the 64-bit address of an MCDI request to
1995          * firmware.  However the dwords are swapped by firmware.  The
1996          * least significant bits of the doorbell are then 0 for all
1997          * MCDI requests due to alignment.
1998          */
1999         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2000                     ER_DZ_MC_DB_LWRD);
2001         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2002                     ER_DZ_MC_DB_HWRD);
2003 }
2004
2005 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2006 {
2007         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2008         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2009
2010         rmb();
2011         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2012 }
2013
2014 static void
2015 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2016                             size_t offset, size_t outlen)
2017 {
2018         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2019         const u8 *pdu = nic_data->mcdi_buf.addr;
2020
2021         memcpy(outbuf, pdu + offset, outlen);
2022 }
2023
2024 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2025 {
2026         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2027
2028         /* All our allocations have been reset */
2029         efx_ef10_reset_mc_allocations(efx);
2030
2031         /* The datapath firmware might have been changed */
2032         nic_data->must_check_datapath_caps = true;
2033
2034         /* MAC statistics have been cleared on the NIC; clear the local
2035          * statistic that we update with efx_update_diff_stat().
2036          */
2037         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2038 }
2039
2040 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2041 {
2042         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2043         int rc;
2044
2045         rc = efx_ef10_get_warm_boot_count(efx);
2046         if (rc < 0) {
2047                 /* The firmware is presumably in the process of
2048                  * rebooting.  However, we are supposed to report each
2049                  * reboot just once, so we must only do that once we
2050                  * can read and store the updated warm boot count.
2051                  */
2052                 return 0;
2053         }
2054
2055         if (rc == nic_data->warm_boot_count)
2056                 return 0;
2057
2058         nic_data->warm_boot_count = rc;
2059         efx_ef10_mcdi_reboot_detected(efx);
2060
2061         return -EIO;
2062 }
2063
2064 /* Handle an MSI interrupt
2065  *
2066  * Handle an MSI hardware interrupt.  This routine schedules event
2067  * queue processing.  No interrupt acknowledgement cycle is necessary.
2068  * Also, we never need to check that the interrupt is for us, since
2069  * MSI interrupts cannot be shared.
2070  */
2071 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2072 {
2073         struct efx_msi_context *context = dev_id;
2074         struct efx_nic *efx = context->efx;
2075
2076         netif_vdbg(efx, intr, efx->net_dev,
2077                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2078
2079         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2080                 /* Note test interrupts */
2081                 if (context->index == efx->irq_level)
2082                         efx->last_irq_cpu = raw_smp_processor_id();
2083
2084                 /* Schedule processing of the channel */
2085                 efx_schedule_channel_irq(efx->channel[context->index]);
2086         }
2087
2088         return IRQ_HANDLED;
2089 }
2090
2091 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2092 {
2093         struct efx_nic *efx = dev_id;
2094         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2095         struct efx_channel *channel;
2096         efx_dword_t reg;
2097         u32 queues;
2098
2099         /* Read the ISR which also ACKs the interrupts */
2100         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2101         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2102
2103         if (queues == 0)
2104                 return IRQ_NONE;
2105
2106         if (likely(soft_enabled)) {
2107                 /* Note test interrupts */
2108                 if (queues & (1U << efx->irq_level))
2109                         efx->last_irq_cpu = raw_smp_processor_id();
2110
2111                 efx_for_each_channel(channel, efx) {
2112                         if (queues & 1)
2113                                 efx_schedule_channel_irq(channel);
2114                         queues >>= 1;
2115                 }
2116         }
2117
2118         netif_vdbg(efx, intr, efx->net_dev,
2119                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2120                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2121
2122         return IRQ_HANDLED;
2123 }
2124
2125 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2126 {
2127         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2128
2129         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2130                                     NULL) == 0)
2131                 return -ENOTSUPP;
2132
2133         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2134
2135         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2136         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2137                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2138 }
2139
2140 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2141 {
2142         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2143                                     (tx_queue->ptr_mask + 1) *
2144                                     sizeof(efx_qword_t),
2145                                     GFP_KERNEL);
2146 }
2147
2148 /* This writes to the TX_DESC_WPTR and also pushes data */
2149 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2150                                          const efx_qword_t *txd)
2151 {
2152         unsigned int write_ptr;
2153         efx_oword_t reg;
2154
2155         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2156         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2157         reg.qword[0] = *txd;
2158         efx_writeo_page(tx_queue->efx, &reg,
2159                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2160 }
2161
2162 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2163  */
2164 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2165                                 struct sk_buff *skb,
2166                                 bool *data_mapped)
2167 {
2168         struct efx_tx_buffer *buffer;
2169         struct tcphdr *tcp;
2170         struct iphdr *ip;
2171
2172         u16 ipv4_id;
2173         u32 seqnum;
2174         u32 mss;
2175
2176         EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2177
2178         mss = skb_shinfo(skb)->gso_size;
2179
2180         if (unlikely(mss < 4)) {
2181                 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2182                 return -EINVAL;
2183         }
2184
2185         ip = ip_hdr(skb);
2186         if (ip->version == 4) {
2187                 /* Modify IPv4 header if needed. */
2188                 ip->tot_len = 0;
2189                 ip->check = 0;
2190                 ipv4_id = ntohs(ip->id);
2191         } else {
2192                 /* Modify IPv6 header if needed. */
2193                 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2194
2195                 ipv6->payload_len = 0;
2196                 ipv4_id = 0;
2197         }
2198
2199         tcp = tcp_hdr(skb);
2200         seqnum = ntohl(tcp->seq);
2201
2202         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2203
2204         buffer->flags = EFX_TX_BUF_OPTION;
2205         buffer->len = 0;
2206         buffer->unmap_len = 0;
2207         EFX_POPULATE_QWORD_5(buffer->option,
2208                         ESF_DZ_TX_DESC_IS_OPT, 1,
2209                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2210                         ESF_DZ_TX_TSO_OPTION_TYPE,
2211                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2212                         ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2213                         ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2214                         );
2215         ++tx_queue->insert_count;
2216
2217         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2218
2219         buffer->flags = EFX_TX_BUF_OPTION;
2220         buffer->len = 0;
2221         buffer->unmap_len = 0;
2222         EFX_POPULATE_QWORD_4(buffer->option,
2223                         ESF_DZ_TX_DESC_IS_OPT, 1,
2224                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2225                         ESF_DZ_TX_TSO_OPTION_TYPE,
2226                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2227                         ESF_DZ_TX_TSO_TCP_MSS, mss
2228                         );
2229         ++tx_queue->insert_count;
2230
2231         return 0;
2232 }
2233
2234 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2235 {
2236         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2237         u32 tso_versions = 0;
2238
2239         if (nic_data->datapath_caps &
2240             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2241                 tso_versions |= BIT(1);
2242         if (nic_data->datapath_caps2 &
2243             (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2244                 tso_versions |= BIT(2);
2245         return tso_versions;
2246 }
2247
2248 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2249 {
2250         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2251                                                        EFX_BUF_SIZE));
2252         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2253         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2254         struct efx_channel *channel = tx_queue->channel;
2255         struct efx_nic *efx = tx_queue->efx;
2256         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2257         bool tso_v2 = false;
2258         size_t inlen;
2259         dma_addr_t dma_addr;
2260         efx_qword_t *txd;
2261         int rc;
2262         int i;
2263         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2264
2265         /* TSOv2 is a limited resource that can only be configured on a limited
2266          * number of queues. TSO without checksum offload is not really a thing,
2267          * so we only enable it for those queues.
2268          */
2269         if (csum_offload && (nic_data->datapath_caps2 &
2270                         (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2271                 tso_v2 = true;
2272                 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2273                                 channel->channel);
2274         }
2275
2276         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2277         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2278         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2279         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2280         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2281         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2282
2283         dma_addr = tx_queue->txd.buf.dma_addr;
2284
2285         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2286                   tx_queue->queue, entries, (u64)dma_addr);
2287
2288         for (i = 0; i < entries; ++i) {
2289                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2290                 dma_addr += EFX_BUF_SIZE;
2291         }
2292
2293         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2294
2295         do {
2296                 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2297                                 /* This flag was removed from mcdi_pcol.h for
2298                                  * the non-_EXT version of INIT_TXQ.  However,
2299                                  * firmware still honours it.
2300                                  */
2301                                 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2302                                 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2303                                 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2304
2305                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2306                                         NULL, 0, NULL);
2307                 if (rc == -ENOSPC && tso_v2) {
2308                         /* Retry without TSOv2 if we're short on contexts. */
2309                         tso_v2 = false;
2310                         netif_warn(efx, probe, efx->net_dev,
2311                                    "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2312                 } else if (rc) {
2313                         efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2314                                                MC_CMD_INIT_TXQ_EXT_IN_LEN,
2315                                                NULL, 0, rc);
2316                         goto fail;
2317                 }
2318         } while (rc);
2319
2320         /* A previous user of this TX queue might have set us up the
2321          * bomb by writing a descriptor to the TX push collector but
2322          * not the doorbell.  (Each collector belongs to a port, not a
2323          * queue or function, so cannot easily be reset.)  We must
2324          * attempt to push a no-op descriptor in its place.
2325          */
2326         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2327         tx_queue->insert_count = 1;
2328         txd = efx_tx_desc(tx_queue, 0);
2329         EFX_POPULATE_QWORD_4(*txd,
2330                              ESF_DZ_TX_DESC_IS_OPT, true,
2331                              ESF_DZ_TX_OPTION_TYPE,
2332                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2333                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2334                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2335         tx_queue->write_count = 1;
2336
2337         if (tso_v2) {
2338                 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2339                 tx_queue->tso_version = 2;
2340         } else if (nic_data->datapath_caps &
2341                         (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2342                 tx_queue->tso_version = 1;
2343         }
2344
2345         wmb();
2346         efx_ef10_push_tx_desc(tx_queue, txd);
2347
2348         return;
2349
2350 fail:
2351         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2352                     tx_queue->queue);
2353 }
2354
2355 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2356 {
2357         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2358         MCDI_DECLARE_BUF_ERR(outbuf);
2359         struct efx_nic *efx = tx_queue->efx;
2360         size_t outlen;
2361         int rc;
2362
2363         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2364                        tx_queue->queue);
2365
2366         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2367                           outbuf, sizeof(outbuf), &outlen);
2368
2369         if (rc && rc != -EALREADY)
2370                 goto fail;
2371
2372         return;
2373
2374 fail:
2375         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2376                                outbuf, outlen, rc);
2377 }
2378
2379 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2380 {
2381         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2382 }
2383
2384 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2385 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2386 {
2387         unsigned int write_ptr;
2388         efx_dword_t reg;
2389
2390         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2391         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2392         efx_writed_page(tx_queue->efx, &reg,
2393                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2394 }
2395
2396 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2397
2398 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2399                                           dma_addr_t dma_addr, unsigned int len)
2400 {
2401         if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2402                 /* If we need to break across multiple descriptors we should
2403                  * stop at a page boundary. This assumes the length limit is
2404                  * greater than the page size.
2405                  */
2406                 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2407
2408                 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2409                 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2410         }
2411
2412         return len;
2413 }
2414
2415 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2416 {
2417         unsigned int old_write_count = tx_queue->write_count;
2418         struct efx_tx_buffer *buffer;
2419         unsigned int write_ptr;
2420         efx_qword_t *txd;
2421
2422         tx_queue->xmit_more_available = false;
2423         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2424                 return;
2425
2426         do {
2427                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2428                 buffer = &tx_queue->buffer[write_ptr];
2429                 txd = efx_tx_desc(tx_queue, write_ptr);
2430                 ++tx_queue->write_count;
2431
2432                 /* Create TX descriptor ring entry */
2433                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2434                         *txd = buffer->option;
2435                         if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2436                                 /* PIO descriptor */
2437                                 tx_queue->packet_write_count = tx_queue->write_count;
2438                 } else {
2439                         tx_queue->packet_write_count = tx_queue->write_count;
2440                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2441                         EFX_POPULATE_QWORD_3(
2442                                 *txd,
2443                                 ESF_DZ_TX_KER_CONT,
2444                                 buffer->flags & EFX_TX_BUF_CONT,
2445                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2446                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2447                 }
2448         } while (tx_queue->write_count != tx_queue->insert_count);
2449
2450         wmb(); /* Ensure descriptors are written before they are fetched */
2451
2452         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2453                 txd = efx_tx_desc(tx_queue,
2454                                   old_write_count & tx_queue->ptr_mask);
2455                 efx_ef10_push_tx_desc(tx_queue, txd);
2456                 ++tx_queue->pushes;
2457         } else {
2458                 efx_ef10_notify_tx_desc(tx_queue);
2459         }
2460 }
2461
2462 #define RSS_MODE_HASH_ADDRS     (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2463                                  1 << RSS_MODE_HASH_DST_ADDR_LBN)
2464 #define RSS_MODE_HASH_PORTS     (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2465                                  1 << RSS_MODE_HASH_DST_PORT_LBN)
2466 #define RSS_CONTEXT_FLAGS_DEFAULT       (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2467                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2468                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2469                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2470                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2471                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2472                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2473                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2474                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2475                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2476
2477 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2478 {
2479         /* Firmware had a bug (sfc bug 61952) where it would not actually
2480          * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2481          * This meant that it would always contain whatever was previously
2482          * in the MCDI buffer.  Fortunately, all firmware versions with
2483          * this bug have the same default flags value for a newly-allocated
2484          * RSS context, and the only time we want to get the flags is just
2485          * after allocating.  Moreover, the response has a 32-bit hole
2486          * where the context ID would be in the request, so we can use an
2487          * overlength buffer in the request and pre-fill the flags field
2488          * with what we believe the default to be.  Thus if the firmware
2489          * has the bug, it will leave our pre-filled value in the flags
2490          * field of the response, and we will get the right answer.
2491          *
2492          * However, this does mean that this function should NOT be used if
2493          * the RSS context flags might not be their defaults - it is ONLY
2494          * reliably correct for a newly-allocated RSS context.
2495          */
2496         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2497         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2498         size_t outlen;
2499         int rc;
2500
2501         /* Check we have a hole for the context ID */
2502         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2503         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2504         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2505                        RSS_CONTEXT_FLAGS_DEFAULT);
2506         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2507                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2508         if (rc == 0) {
2509                 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2510                         rc = -EIO;
2511                 else
2512                         *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2513         }
2514         return rc;
2515 }
2516
2517 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2518  * If we fail, we just leave the RSS context at its default hash settings,
2519  * which is safe but may slightly reduce performance.
2520  * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2521  * just need to set the UDP ports flags (for both IP versions).
2522  */
2523 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2524 {
2525         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2526         u32 flags;
2527
2528         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2529
2530         if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2531                 return;
2532         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2533         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2534         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2535         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2536         if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2537                           NULL, 0, NULL))
2538                 /* Succeeded, so UDP 4-tuple is now enabled */
2539                 efx->rx_hash_udp_4tuple = true;
2540 }
2541
2542 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2543                                       bool exclusive, unsigned *context_size)
2544 {
2545         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2546         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2547         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2548         size_t outlen;
2549         int rc;
2550         u32 alloc_type = exclusive ?
2551                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2552                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2553         unsigned rss_spread = exclusive ?
2554                                 efx->rss_spread :
2555                                 min(rounddown_pow_of_two(efx->rss_spread),
2556                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2557
2558         if (!exclusive && rss_spread == 1) {
2559                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2560                 if (context_size)
2561                         *context_size = 1;
2562                 return 0;
2563         }
2564
2565         if (nic_data->datapath_caps &
2566             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2567                 return -EOPNOTSUPP;
2568
2569         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2570                        nic_data->vport_id);
2571         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2572         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2573
2574         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2575                 outbuf, sizeof(outbuf), &outlen);
2576         if (rc != 0)
2577                 return rc;
2578
2579         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2580                 return -EIO;
2581
2582         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2583
2584         if (context_size)
2585                 *context_size = rss_spread;
2586
2587         if (nic_data->datapath_caps &
2588             1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2589                 efx_ef10_set_rss_flags(efx, *context);
2590
2591         return 0;
2592 }
2593
2594 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2595 {
2596         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2597         int rc;
2598
2599         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2600                        context);
2601
2602         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2603                             NULL, 0, NULL);
2604         WARN_ON(rc != 0);
2605 }
2606
2607 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2608                                        const u32 *rx_indir_table, const u8 *key)
2609 {
2610         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2611         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2612         int i, rc;
2613
2614         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2615                        context);
2616         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2617                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2618
2619         /* This iterates over the length of efx->rx_indir_table, but copies
2620          * bytes from rx_indir_table.  That's because the latter is a pointer
2621          * rather than an array, but should have the same length.
2622          * The efx->rx_hash_key loop below is similar.
2623          */
2624         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2625                 MCDI_PTR(tablebuf,
2626                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2627                                 (u8) rx_indir_table[i];
2628
2629         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2630                           sizeof(tablebuf), NULL, 0, NULL);
2631         if (rc != 0)
2632                 return rc;
2633
2634         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2635                        context);
2636         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2637                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2638         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2639                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2640
2641         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2642                             sizeof(keybuf), NULL, 0, NULL);
2643 }
2644
2645 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2646 {
2647         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2648
2649         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2650                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2651         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2652 }
2653
2654 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2655                                               unsigned *context_size)
2656 {
2657         u32 new_rx_rss_context;
2658         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2659         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2660                                             false, context_size);
2661
2662         if (rc != 0)
2663                 return rc;
2664
2665         nic_data->rx_rss_context = new_rx_rss_context;
2666         nic_data->rx_rss_context_exclusive = false;
2667         efx_set_default_rx_indir_table(efx);
2668         return 0;
2669 }
2670
2671 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2672                                                  const u32 *rx_indir_table,
2673                                                  const u8 *key)
2674 {
2675         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2676         int rc;
2677         u32 new_rx_rss_context;
2678
2679         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2680             !nic_data->rx_rss_context_exclusive) {
2681                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2682                                                 true, NULL);
2683                 if (rc == -EOPNOTSUPP)
2684                         return rc;
2685                 else if (rc != 0)
2686                         goto fail1;
2687         } else {
2688                 new_rx_rss_context = nic_data->rx_rss_context;
2689         }
2690
2691         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2692                                          rx_indir_table, key);
2693         if (rc != 0)
2694                 goto fail2;
2695
2696         if (nic_data->rx_rss_context != new_rx_rss_context)
2697                 efx_ef10_rx_free_indir_table(efx);
2698         nic_data->rx_rss_context = new_rx_rss_context;
2699         nic_data->rx_rss_context_exclusive = true;
2700         if (rx_indir_table != efx->rx_indir_table)
2701                 memcpy(efx->rx_indir_table, rx_indir_table,
2702                        sizeof(efx->rx_indir_table));
2703         if (key != efx->rx_hash_key)
2704                 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2705
2706         return 0;
2707
2708 fail2:
2709         if (new_rx_rss_context != nic_data->rx_rss_context)
2710                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2711 fail1:
2712         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2713         return rc;
2714 }
2715
2716 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2717 {
2718         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2719         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2720         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2721         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2722         size_t outlen;
2723         int rc, i;
2724
2725         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2726                      MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2727
2728         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2729                 return -ENOENT;
2730
2731         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2732                        nic_data->rx_rss_context);
2733         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2734                      MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2735         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2736                           tablebuf, sizeof(tablebuf), &outlen);
2737         if (rc != 0)
2738                 return rc;
2739
2740         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2741                 return -EIO;
2742
2743         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2744                 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2745                                 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2746
2747         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2748                        nic_data->rx_rss_context);
2749         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2750                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2751         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2752                           keybuf, sizeof(keybuf), &outlen);
2753         if (rc != 0)
2754                 return rc;
2755
2756         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2757                 return -EIO;
2758
2759         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2760                 efx->rx_hash_key[i] = MCDI_PTR(
2761                                 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2762
2763         return 0;
2764 }
2765
2766 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2767                                           const u32 *rx_indir_table,
2768                                           const u8 *key)
2769 {
2770         int rc;
2771
2772         if (efx->rss_spread == 1)
2773                 return 0;
2774
2775         if (!key)
2776                 key = efx->rx_hash_key;
2777
2778         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
2779
2780         if (rc == -ENOBUFS && !user) {
2781                 unsigned context_size;
2782                 bool mismatch = false;
2783                 size_t i;
2784
2785                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2786                      i++)
2787                         mismatch = rx_indir_table[i] !=
2788                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2789
2790                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2791                 if (rc == 0) {
2792                         if (context_size != efx->rss_spread)
2793                                 netif_warn(efx, probe, efx->net_dev,
2794                                            "Could not allocate an exclusive RSS"
2795                                            " context; allocated a shared one of"
2796                                            " different size."
2797                                            " Wanted %u, got %u.\n",
2798                                            efx->rss_spread, context_size);
2799                         else if (mismatch)
2800                                 netif_warn(efx, probe, efx->net_dev,
2801                                            "Could not allocate an exclusive RSS"
2802                                            " context; allocated a shared one but"
2803                                            " could not apply custom"
2804                                            " indirection.\n");
2805                         else
2806                                 netif_info(efx, probe, efx->net_dev,
2807                                            "Could not allocate an exclusive RSS"
2808                                            " context; allocated a shared one.\n");
2809                 }
2810         }
2811         return rc;
2812 }
2813
2814 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2815                                           const u32 *rx_indir_table
2816                                           __attribute__ ((unused)),
2817                                           const u8 *key
2818                                           __attribute__ ((unused)))
2819 {
2820         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2821
2822         if (user)
2823                 return -EOPNOTSUPP;
2824         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2825                 return 0;
2826         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2827 }
2828
2829 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2830 {
2831         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2832                                     (rx_queue->ptr_mask + 1) *
2833                                     sizeof(efx_qword_t),
2834                                     GFP_KERNEL);
2835 }
2836
2837 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2838 {
2839         MCDI_DECLARE_BUF(inbuf,
2840                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2841                                                 EFX_BUF_SIZE));
2842         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2843         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2844         struct efx_nic *efx = rx_queue->efx;
2845         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2846         size_t inlen;
2847         dma_addr_t dma_addr;
2848         int rc;
2849         int i;
2850         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2851
2852         rx_queue->scatter_n = 0;
2853         rx_queue->scatter_len = 0;
2854
2855         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2856         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2857         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2858         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2859                        efx_rx_queue_index(rx_queue));
2860         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2861                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2862                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2863         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2864         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2865
2866         dma_addr = rx_queue->rxd.buf.dma_addr;
2867
2868         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2869                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2870
2871         for (i = 0; i < entries; ++i) {
2872                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2873                 dma_addr += EFX_BUF_SIZE;
2874         }
2875
2876         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2877
2878         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2879                           NULL, 0, NULL);
2880         if (rc)
2881                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2882                             efx_rx_queue_index(rx_queue));
2883 }
2884
2885 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2886 {
2887         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2888         MCDI_DECLARE_BUF_ERR(outbuf);
2889         struct efx_nic *efx = rx_queue->efx;
2890         size_t outlen;
2891         int rc;
2892
2893         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2894                        efx_rx_queue_index(rx_queue));
2895
2896         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2897                           outbuf, sizeof(outbuf), &outlen);
2898
2899         if (rc && rc != -EALREADY)
2900                 goto fail;
2901
2902         return;
2903
2904 fail:
2905         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2906                                outbuf, outlen, rc);
2907 }
2908
2909 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2910 {
2911         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2912 }
2913
2914 /* This creates an entry in the RX descriptor queue */
2915 static inline void
2916 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2917 {
2918         struct efx_rx_buffer *rx_buf;
2919         efx_qword_t *rxd;
2920
2921         rxd = efx_rx_desc(rx_queue, index);
2922         rx_buf = efx_rx_buffer(rx_queue, index);
2923         EFX_POPULATE_QWORD_2(*rxd,
2924                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2925                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2926 }
2927
2928 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2929 {
2930         struct efx_nic *efx = rx_queue->efx;
2931         unsigned int write_count;
2932         efx_dword_t reg;
2933
2934         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2935         write_count = rx_queue->added_count & ~7;
2936         if (rx_queue->notified_count == write_count)
2937                 return;
2938
2939         do
2940                 efx_ef10_build_rx_desc(
2941                         rx_queue,
2942                         rx_queue->notified_count & rx_queue->ptr_mask);
2943         while (++rx_queue->notified_count != write_count);
2944
2945         wmb();
2946         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2947                              write_count & rx_queue->ptr_mask);
2948         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2949                         efx_rx_queue_index(rx_queue));
2950 }
2951
2952 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2953
2954 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2955 {
2956         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2957         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2958         efx_qword_t event;
2959
2960         EFX_POPULATE_QWORD_2(event,
2961                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2962                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2963
2964         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2965
2966         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2967          * already swapped the data to little-endian order.
2968          */
2969         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2970                sizeof(efx_qword_t));
2971
2972         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2973                            inbuf, sizeof(inbuf), 0,
2974                            efx_ef10_rx_defer_refill_complete, 0);
2975 }
2976
2977 static void
2978 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2979                                   int rc, efx_dword_t *outbuf,
2980                                   size_t outlen_actual)
2981 {
2982         /* nothing to do */
2983 }
2984
2985 static int efx_ef10_ev_probe(struct efx_channel *channel)
2986 {
2987         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2988                                     (channel->eventq_mask + 1) *
2989                                     sizeof(efx_qword_t),
2990                                     GFP_KERNEL);
2991 }
2992
2993 static void efx_ef10_ev_fini(struct efx_channel *channel)
2994 {
2995         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2996         MCDI_DECLARE_BUF_ERR(outbuf);
2997         struct efx_nic *efx = channel->efx;
2998         size_t outlen;
2999         int rc;
3000
3001         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3002
3003         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3004                           outbuf, sizeof(outbuf), &outlen);
3005
3006         if (rc && rc != -EALREADY)
3007                 goto fail;
3008
3009         return;
3010
3011 fail:
3012         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3013                                outbuf, outlen, rc);
3014 }
3015
3016 static int efx_ef10_ev_init(struct efx_channel *channel)
3017 {
3018         MCDI_DECLARE_BUF(inbuf,
3019                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3020                                                    EFX_BUF_SIZE));
3021         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3022         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3023         struct efx_nic *efx = channel->efx;
3024         struct efx_ef10_nic_data *nic_data;
3025         size_t inlen, outlen;
3026         unsigned int enabled, implemented;
3027         dma_addr_t dma_addr;
3028         int rc;
3029         int i;
3030
3031         nic_data = efx->nic_data;
3032
3033         /* Fill event queue with all ones (i.e. empty events) */
3034         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3035
3036         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3037         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3038         /* INIT_EVQ expects index in vector table, not absolute */
3039         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3040         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3041                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3042         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3043         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3044         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3045                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3046         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3047
3048         if (nic_data->datapath_caps2 &
3049             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3050                 /* Use the new generic approach to specifying event queue
3051                  * configuration, requesting lower latency or higher throughput.
3052                  * The options that actually get used appear in the output.
3053                  */
3054                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3055                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3056                                       INIT_EVQ_V2_IN_FLAG_TYPE,
3057                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3058         } else {
3059                 bool cut_thru = !(nic_data->datapath_caps &
3060                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3061
3062                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3063                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3064                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3065                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3066                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3067         }
3068
3069         dma_addr = channel->eventq.buf.dma_addr;
3070         for (i = 0; i < entries; ++i) {
3071                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3072                 dma_addr += EFX_BUF_SIZE;
3073         }
3074
3075         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3076
3077         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3078                           outbuf, sizeof(outbuf), &outlen);
3079
3080         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3081                 netif_dbg(efx, drv, efx->net_dev,
3082                           "Channel %d using event queue flags %08x\n",
3083                           channel->channel,
3084                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3085
3086         /* IRQ return is ignored */
3087         if (channel->channel || rc)
3088                 return rc;
3089
3090         /* Successfully created event queue on channel 0 */
3091         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3092         if (rc == -ENOSYS) {
3093                 /* GET_WORKAROUNDS was implemented before this workaround,
3094                  * thus it must be unavailable in this firmware.
3095                  */
3096                 nic_data->workaround_26807 = false;
3097                 rc = 0;
3098         } else if (rc) {
3099                 goto fail;
3100         } else {
3101                 nic_data->workaround_26807 =
3102                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3103
3104                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3105                     !nic_data->workaround_26807) {
3106                         unsigned int flags;
3107
3108                         rc = efx_mcdi_set_workaround(efx,
3109                                                      MC_CMD_WORKAROUND_BUG26807,
3110                                                      true, &flags);
3111
3112                         if (!rc) {
3113                                 if (flags &
3114                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3115                                         netif_info(efx, drv, efx->net_dev,
3116                                                    "other functions on NIC have been reset\n");
3117
3118                                         /* With MCFW v4.6.x and earlier, the
3119                                          * boot count will have incremented,
3120                                          * so re-read the warm_boot_count
3121                                          * value now to ensure this function
3122                                          * doesn't think it has changed next
3123                                          * time it checks.
3124                                          */
3125                                         rc = efx_ef10_get_warm_boot_count(efx);
3126                                         if (rc >= 0) {
3127                                                 nic_data->warm_boot_count = rc;
3128                                                 rc = 0;
3129                                         }
3130                                 }
3131                                 nic_data->workaround_26807 = true;
3132                         } else if (rc == -EPERM) {
3133                                 rc = 0;
3134                         }
3135                 }
3136         }
3137
3138         if (!rc)
3139                 return 0;
3140
3141 fail:
3142         efx_ef10_ev_fini(channel);
3143         return rc;
3144 }
3145
3146 static void efx_ef10_ev_remove(struct efx_channel *channel)
3147 {
3148         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3149 }
3150
3151 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3152                                            unsigned int rx_queue_label)
3153 {
3154         struct efx_nic *efx = rx_queue->efx;
3155
3156         netif_info(efx, hw, efx->net_dev,
3157                    "rx event arrived on queue %d labeled as queue %u\n",
3158                    efx_rx_queue_index(rx_queue), rx_queue_label);
3159
3160         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3161 }
3162
3163 static void
3164 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3165                              unsigned int actual, unsigned int expected)
3166 {
3167         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3168         struct efx_nic *efx = rx_queue->efx;
3169
3170         netif_info(efx, hw, efx->net_dev,
3171                    "dropped %d events (index=%d expected=%d)\n",
3172                    dropped, actual, expected);
3173
3174         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3175 }
3176
3177 /* partially received RX was aborted. clean up. */
3178 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3179 {
3180         unsigned int rx_desc_ptr;
3181
3182         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3183                   "scattered RX aborted (dropping %u buffers)\n",
3184                   rx_queue->scatter_n);
3185
3186         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3187
3188         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3189                       0, EFX_RX_PKT_DISCARD);
3190
3191         rx_queue->removed_count += rx_queue->scatter_n;
3192         rx_queue->scatter_n = 0;
3193         rx_queue->scatter_len = 0;
3194         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3195 }
3196
3197 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3198                                            unsigned int n_packets,
3199                                            unsigned int rx_encap_hdr,
3200                                            unsigned int rx_l3_class,
3201                                            unsigned int rx_l4_class,
3202                                            const efx_qword_t *event)
3203 {
3204         struct efx_nic *efx = channel->efx;
3205
3206         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3207                 if (!efx->loopback_selftest)
3208                         channel->n_rx_eth_crc_err += n_packets;
3209                 return EFX_RX_PKT_DISCARD;
3210         }
3211         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3212                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3213                              rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3214                              rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3215                              rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3216                              rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3217                         netdev_WARN(efx->net_dev,
3218                                     "invalid class for RX_IPCKSUM_ERR: event="
3219                                     EFX_QWORD_FMT "\n",
3220                                     EFX_QWORD_VAL(*event));
3221                 if (!efx->loopback_selftest)
3222                         *(rx_encap_hdr ?
3223                           &channel->n_rx_outer_ip_hdr_chksum_err :
3224                           &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3225                 return 0;
3226         }
3227         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3228                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3229                              ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3230                                rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3231                               (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3232                                rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
3233                         netdev_WARN(efx->net_dev,
3234                                     "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3235                                     EFX_QWORD_FMT "\n",
3236                                     EFX_QWORD_VAL(*event));
3237                 if (!efx->loopback_selftest)
3238                         *(rx_encap_hdr ?
3239                           &channel->n_rx_outer_tcp_udp_chksum_err :
3240                           &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3241                 return 0;
3242         }
3243         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3244                 if (unlikely(!rx_encap_hdr))
3245                         netdev_WARN(efx->net_dev,
3246                                     "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3247                                     EFX_QWORD_FMT "\n",
3248                                     EFX_QWORD_VAL(*event));
3249                 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3250                                   rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3251                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3252                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3253                         netdev_WARN(efx->net_dev,
3254                                     "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3255                                     EFX_QWORD_FMT "\n",
3256                                     EFX_QWORD_VAL(*event));
3257                 if (!efx->loopback_selftest)
3258                         channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3259                 return 0;
3260         }
3261         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3262                 if (unlikely(!rx_encap_hdr))
3263                         netdev_WARN(efx->net_dev,
3264                                     "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3265                                     EFX_QWORD_FMT "\n",
3266                                     EFX_QWORD_VAL(*event));
3267                 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3268                                    rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3269                                   (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3270                                    rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
3271                         netdev_WARN(efx->net_dev,
3272                                     "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3273                                     EFX_QWORD_FMT "\n",
3274                                     EFX_QWORD_VAL(*event));
3275                 if (!efx->loopback_selftest)
3276                         channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3277                 return 0;
3278         }
3279
3280         WARN_ON(1); /* No error bits were recognised */
3281         return 0;
3282 }
3283
3284 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3285                                     const efx_qword_t *event)
3286 {
3287         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3288         unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3289         unsigned int n_descs, n_packets, i;
3290         struct efx_nic *efx = channel->efx;
3291         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3292         struct efx_rx_queue *rx_queue;
3293         efx_qword_t errors;
3294         bool rx_cont;
3295         u16 flags = 0;
3296
3297         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3298                 return 0;
3299
3300         /* Basic packet information */
3301         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3302         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3303         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3304         rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3305         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3306         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3307         rx_encap_hdr =
3308                 nic_data->datapath_caps &
3309                         (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3310                 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3311                 ESE_EZ_ENCAP_HDR_NONE;
3312
3313         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3314                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3315                             EFX_QWORD_FMT "\n",
3316                             EFX_QWORD_VAL(*event));
3317
3318         rx_queue = efx_channel_get_rx_queue(channel);
3319
3320         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3321                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3322
3323         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3324                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3325
3326         if (n_descs != rx_queue->scatter_n + 1) {
3327                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3328
3329                 /* detect rx abort */
3330                 if (unlikely(n_descs == rx_queue->scatter_n)) {
3331                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3332                                 netdev_WARN(efx->net_dev,
3333                                             "invalid RX abort: scatter_n=%u event="
3334                                             EFX_QWORD_FMT "\n",
3335                                             rx_queue->scatter_n,
3336                                             EFX_QWORD_VAL(*event));
3337                         efx_ef10_handle_rx_abort(rx_queue);
3338                         return 0;
3339                 }
3340
3341                 /* Check that RX completion merging is valid, i.e.
3342                  * the current firmware supports it and this is a
3343                  * non-scattered packet.
3344                  */
3345                 if (!(nic_data->datapath_caps &
3346                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3347                     rx_queue->scatter_n != 0 || rx_cont) {
3348                         efx_ef10_handle_rx_bad_lbits(
3349                                 rx_queue, next_ptr_lbits,
3350                                 (rx_queue->removed_count +
3351                                  rx_queue->scatter_n + 1) &
3352                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3353                         return 0;
3354                 }
3355
3356                 /* Merged completion for multiple non-scattered packets */
3357                 rx_queue->scatter_n = 1;
3358                 rx_queue->scatter_len = 0;
3359                 n_packets = n_descs;
3360                 ++channel->n_rx_merge_events;
3361                 channel->n_rx_merge_packets += n_packets;
3362                 flags |= EFX_RX_PKT_PREFIX_LEN;
3363         } else {
3364                 ++rx_queue->scatter_n;
3365                 rx_queue->scatter_len += rx_bytes;
3366                 if (rx_cont)
3367                         return 0;
3368                 n_packets = 1;
3369         }
3370
3371         EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3372                                      ESF_DZ_RX_IPCKSUM_ERR, 1,
3373                                      ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3374                                      ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3375                                      ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3376         EFX_AND_QWORD(errors, *event, errors);
3377         if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3378                 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3379                                                          rx_encap_hdr,
3380                                                          rx_l3_class, rx_l4_class,
3381                                                          event);
3382         } else {
3383                 bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3384                               rx_l4_class == ESE_DZ_L4_CLASS_UDP;
3385
3386                 switch (rx_encap_hdr) {
3387                 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3388                         flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3389                         if (tcpudp)
3390                                 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3391                         break;
3392                 case ESE_EZ_ENCAP_HDR_GRE:
3393                 case ESE_EZ_ENCAP_HDR_NONE:
3394                         if (tcpudp)
3395                                 flags |= EFX_RX_PKT_CSUMMED;
3396                         break;
3397                 default:
3398                         netdev_WARN(efx->net_dev,
3399                                     "unknown encapsulation type: event="
3400                                     EFX_QWORD_FMT "\n",
3401                                     EFX_QWORD_VAL(*event));
3402                 }
3403         }
3404
3405         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3406                 flags |= EFX_RX_PKT_TCP;
3407
3408         channel->irq_mod_score += 2 * n_packets;
3409
3410         /* Handle received packet(s) */
3411         for (i = 0; i < n_packets; i++) {
3412                 efx_rx_packet(rx_queue,
3413                               rx_queue->removed_count & rx_queue->ptr_mask,
3414                               rx_queue->scatter_n, rx_queue->scatter_len,
3415                               flags);
3416                 rx_queue->removed_count += rx_queue->scatter_n;
3417         }
3418
3419         rx_queue->scatter_n = 0;
3420         rx_queue->scatter_len = 0;
3421
3422         return n_packets;
3423 }
3424
3425 static int
3426 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3427 {
3428         struct efx_nic *efx = channel->efx;
3429         struct efx_tx_queue *tx_queue;
3430         unsigned int tx_ev_desc_ptr;
3431         unsigned int tx_ev_q_label;
3432         int tx_descs = 0;
3433
3434         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3435                 return 0;
3436
3437         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3438                 return 0;
3439
3440         /* Transmit completion */
3441         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3442         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3443         tx_queue = efx_channel_get_tx_queue(channel,
3444                                             tx_ev_q_label % EFX_TXQ_TYPES);
3445         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3446                     tx_queue->ptr_mask);
3447         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3448
3449         return tx_descs;
3450 }
3451
3452 static void
3453 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3454 {
3455         struct efx_nic *efx = channel->efx;
3456         int subcode;
3457
3458         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3459
3460         switch (subcode) {
3461         case ESE_DZ_DRV_TIMER_EV:
3462         case ESE_DZ_DRV_WAKE_UP_EV:
3463                 break;
3464         case ESE_DZ_DRV_START_UP_EV:
3465                 /* event queue init complete. ok. */
3466                 break;
3467         default:
3468                 netif_err(efx, hw, efx->net_dev,
3469                           "channel %d unknown driver event type %d"
3470                           " (data " EFX_QWORD_FMT ")\n",
3471                           channel->channel, subcode,
3472                           EFX_QWORD_VAL(*event));
3473
3474         }
3475 }
3476
3477 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3478                                                    efx_qword_t *event)
3479 {
3480         struct efx_nic *efx = channel->efx;
3481         u32 subcode;
3482
3483         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3484
3485         switch (subcode) {
3486         case EFX_EF10_TEST:
3487                 channel->event_test_cpu = raw_smp_processor_id();
3488                 break;
3489         case EFX_EF10_REFILL:
3490                 /* The queue must be empty, so we won't receive any rx
3491                  * events, so efx_process_channel() won't refill the
3492                  * queue. Refill it here
3493                  */
3494                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3495                 break;
3496         default:
3497                 netif_err(efx, hw, efx->net_dev,
3498                           "channel %d unknown driver event type %u"
3499                           " (data " EFX_QWORD_FMT ")\n",
3500                           channel->channel, (unsigned) subcode,
3501                           EFX_QWORD_VAL(*event));
3502         }
3503 }
3504
3505 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3506 {
3507         struct efx_nic *efx = channel->efx;
3508         efx_qword_t event, *p_event;
3509         unsigned int read_ptr;
3510         int ev_code;
3511         int tx_descs = 0;
3512         int spent = 0;
3513
3514         if (quota <= 0)
3515                 return spent;
3516
3517         read_ptr = channel->eventq_read_ptr;
3518
3519         for (;;) {
3520                 p_event = efx_event(channel, read_ptr);
3521                 event = *p_event;
3522
3523                 if (!efx_event_present(&event))
3524                         break;
3525
3526                 EFX_SET_QWORD(*p_event);
3527
3528                 ++read_ptr;
3529
3530                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3531
3532                 netif_vdbg(efx, drv, efx->net_dev,
3533                            "processing event on %d " EFX_QWORD_FMT "\n",
3534                            channel->channel, EFX_QWORD_VAL(event));
3535
3536                 switch (ev_code) {
3537                 case ESE_DZ_EV_CODE_MCDI_EV:
3538                         efx_mcdi_process_event(channel, &event);
3539                         break;
3540                 case ESE_DZ_EV_CODE_RX_EV:
3541                         spent += efx_ef10_handle_rx_event(channel, &event);
3542                         if (spent >= quota) {
3543                                 /* XXX can we split a merged event to
3544                                  * avoid going over-quota?
3545                                  */
3546                                 spent = quota;
3547                                 goto out;
3548                         }
3549                         break;
3550                 case ESE_DZ_EV_CODE_TX_EV:
3551                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
3552                         if (tx_descs > efx->txq_entries) {
3553                                 spent = quota;
3554                                 goto out;
3555                         } else if (++spent == quota) {
3556                                 goto out;
3557                         }
3558                         break;
3559                 case ESE_DZ_EV_CODE_DRIVER_EV:
3560                         efx_ef10_handle_driver_event(channel, &event);
3561                         if (++spent == quota)
3562                                 goto out;
3563                         break;
3564                 case EFX_EF10_DRVGEN_EV:
3565                         efx_ef10_handle_driver_generated_event(channel, &event);
3566                         break;
3567                 default:
3568                         netif_err(efx, hw, efx->net_dev,
3569                                   "channel %d unknown event type %d"
3570                                   " (data " EFX_QWORD_FMT ")\n",
3571                                   channel->channel, ev_code,
3572                                   EFX_QWORD_VAL(event));
3573                 }
3574         }
3575
3576 out:
3577         channel->eventq_read_ptr = read_ptr;
3578         return spent;
3579 }
3580
3581 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3582 {
3583         struct efx_nic *efx = channel->efx;
3584         efx_dword_t rptr;
3585
3586         if (EFX_EF10_WORKAROUND_35388(efx)) {
3587                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3588                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3589                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3590                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3591
3592                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3593                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3594                                      ERF_DD_EVQ_IND_RPTR,
3595                                      (channel->eventq_read_ptr &
3596                                       channel->eventq_mask) >>
3597                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3598                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3599                                 channel->channel);
3600                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3601                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3602                                      ERF_DD_EVQ_IND_RPTR,
3603                                      channel->eventq_read_ptr &
3604                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3605                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3606                                 channel->channel);
3607         } else {
3608                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3609                                      channel->eventq_read_ptr &
3610                                      channel->eventq_mask);
3611                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3612         }
3613 }
3614
3615 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3616 {
3617         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3618         struct efx_nic *efx = channel->efx;
3619         efx_qword_t event;
3620         int rc;
3621
3622         EFX_POPULATE_QWORD_2(event,
3623                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3624                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3625
3626         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3627
3628         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3629          * already swapped the data to little-endian order.
3630          */
3631         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3632                sizeof(efx_qword_t));
3633
3634         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3635                           NULL, 0, NULL);
3636         if (rc != 0)
3637                 goto fail;
3638
3639         return;
3640
3641 fail:
3642         WARN_ON(true);
3643         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3644 }
3645
3646 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3647 {
3648         if (atomic_dec_and_test(&efx->active_queues))
3649                 wake_up(&efx->flush_wq);
3650
3651         WARN_ON(atomic_read(&efx->active_queues) < 0);
3652 }
3653
3654 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3655 {
3656         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3657         struct efx_channel *channel;
3658         struct efx_tx_queue *tx_queue;
3659         struct efx_rx_queue *rx_queue;
3660         int pending;
3661
3662         /* If the MC has just rebooted, the TX/RX queues will have already been
3663          * torn down, but efx->active_queues needs to be set to zero.
3664          */
3665         if (nic_data->must_realloc_vis) {
3666                 atomic_set(&efx->active_queues, 0);
3667                 return 0;
3668         }
3669
3670         /* Do not attempt to write to the NIC during EEH recovery */
3671         if (efx->state != STATE_RECOVERY) {
3672                 efx_for_each_channel(channel, efx) {
3673                         efx_for_each_channel_rx_queue(rx_queue, channel)
3674                                 efx_ef10_rx_fini(rx_queue);
3675                         efx_for_each_channel_tx_queue(tx_queue, channel)
3676                                 efx_ef10_tx_fini(tx_queue);
3677                 }
3678
3679                 wait_event_timeout(efx->flush_wq,
3680                                    atomic_read(&efx->active_queues) == 0,
3681                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3682                 pending = atomic_read(&efx->active_queues);
3683                 if (pending) {
3684                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3685                                   pending);
3686                         return -ETIMEDOUT;
3687                 }
3688         }
3689
3690         return 0;
3691 }
3692
3693 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3694 {
3695         atomic_set(&efx->active_queues, 0);
3696 }
3697
3698 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3699                                   const struct efx_filter_spec *right)
3700 {
3701         if ((left->match_flags ^ right->match_flags) |
3702             ((left->flags ^ right->flags) &
3703              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3704                 return false;
3705
3706         return memcmp(&left->outer_vid, &right->outer_vid,
3707                       sizeof(struct efx_filter_spec) -
3708                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3709 }
3710
3711 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3712 {
3713         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3714         return jhash2((const u32 *)&spec->outer_vid,
3715                       (sizeof(struct efx_filter_spec) -
3716                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3717                       0);
3718         /* XXX should we randomise the initval? */
3719 }
3720
3721 /* Decide whether a filter should be exclusive or else should allow
3722  * delivery to additional recipients.  Currently we decide that
3723  * filters for specific local unicast MAC and IP addresses are
3724  * exclusive.
3725  */
3726 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3727 {
3728         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3729             !is_multicast_ether_addr(spec->loc_mac))
3730                 return true;
3731
3732         if ((spec->match_flags &
3733              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3734             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3735                 if (spec->ether_type == htons(ETH_P_IP) &&
3736                     !ipv4_is_multicast(spec->loc_host[0]))
3737                         return true;
3738                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3739                     ((const u8 *)spec->loc_host)[0] != 0xff)
3740                         return true;
3741         }
3742
3743         return false;
3744 }
3745
3746 static struct efx_filter_spec *
3747 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3748                            unsigned int filter_idx)
3749 {
3750         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3751                                           ~EFX_EF10_FILTER_FLAGS);
3752 }
3753
3754 static unsigned int
3755 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3756                            unsigned int filter_idx)
3757 {
3758         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3759 }
3760
3761 static void
3762 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3763                           unsigned int filter_idx,
3764                           const struct efx_filter_spec *spec,
3765                           unsigned int flags)
3766 {
3767         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3768 }
3769
3770 static void
3771 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3772                                            const struct efx_filter_spec *spec,
3773                                            efx_dword_t *inbuf)
3774 {
3775         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3776         u32 match_fields = 0, uc_match, mc_match;
3777
3778         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3779                        efx_ef10_filter_is_exclusive(spec) ?
3780                        MC_CMD_FILTER_OP_IN_OP_INSERT :
3781                        MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3782
3783         /* Convert match flags and values.  Unlike almost
3784          * everything else in MCDI, these fields are in
3785          * network byte order.
3786          */
3787 #define COPY_VALUE(value, mcdi_field)                                        \
3788         do {                                                         \
3789                 match_fields |=                                      \
3790                         1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
3791                         mcdi_field ## _LBN;                          \
3792                 BUILD_BUG_ON(                                        \
3793                         MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3794                         sizeof(value));                              \
3795                 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3796                        &value, sizeof(value));                       \
3797         } while (0)
3798 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
3799         if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
3800                 COPY_VALUE(spec->gen_field, mcdi_field);             \
3801         }
3802         /* Handle encap filters first.  They will always be mismatch
3803          * (unknown UC or MC) filters
3804          */
3805         if (encap_type) {
3806                 /* ether_type and outer_ip_proto need to be variables
3807                  * because COPY_VALUE wants to memcpy them
3808                  */
3809                 __be16 ether_type =
3810                         htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3811                               ETH_P_IPV6 : ETH_P_IP);
3812                 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3813                 u8 outer_ip_proto;
3814
3815                 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3816                 case EFX_ENCAP_TYPE_VXLAN:
3817                         vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3818                         /* fallthrough */
3819                 case EFX_ENCAP_TYPE_GENEVE:
3820                         COPY_VALUE(ether_type, ETHER_TYPE);
3821                         outer_ip_proto = IPPROTO_UDP;
3822                         COPY_VALUE(outer_ip_proto, IP_PROTO);
3823                         /* We always need to set the type field, even
3824                          * though we're not matching on the TNI.
3825                          */
3826                         MCDI_POPULATE_DWORD_1(inbuf,
3827                                 FILTER_OP_EXT_IN_VNI_OR_VSID,
3828                                 FILTER_OP_EXT_IN_VNI_TYPE,
3829                                 vni_type);
3830                         break;
3831                 case EFX_ENCAP_TYPE_NVGRE:
3832                         COPY_VALUE(ether_type, ETHER_TYPE);
3833                         outer_ip_proto = IPPROTO_GRE;
3834                         COPY_VALUE(outer_ip_proto, IP_PROTO);
3835                         break;
3836                 default:
3837                         WARN_ON(1);
3838                 }
3839
3840                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3841                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3842         } else {
3843                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3844                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3845         }
3846
3847         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3848                 match_fields |=
3849                         is_multicast_ether_addr(spec->loc_mac) ?
3850                         1 << mc_match :
3851                         1 << uc_match;
3852         COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3853         COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3854         COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3855         COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3856         COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3857         COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3858         COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3859         COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3860         COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3861         COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3862 #undef COPY_FIELD
3863 #undef COPY_VALUE
3864         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3865                        match_fields);
3866 }
3867
3868 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3869                                       const struct efx_filter_spec *spec,
3870                                       efx_dword_t *inbuf, u64 handle,
3871                                       bool replacing)
3872 {
3873         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3874         u32 flags = spec->flags;
3875
3876         memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
3877
3878         /* Remove RSS flag if we don't have an RSS context. */
3879         if (flags & EFX_FILTER_FLAG_RX_RSS &&
3880             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3881             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3882                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3883
3884         if (replacing) {
3885                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3886                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
3887                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3888         } else {
3889                 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
3890         }
3891
3892         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3893         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3894                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3895                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3896                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3897         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3898         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3899                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3900         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3901                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3902                        0 : spec->dmaq_id);
3903         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3904                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
3905                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3906                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3907         if (flags & EFX_FILTER_FLAG_RX_RSS)
3908                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3909                                spec->rss_context !=
3910                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3911                                spec->rss_context : nic_data->rx_rss_context);
3912 }
3913
3914 static int efx_ef10_filter_push(struct efx_nic *efx,
3915                                 const struct efx_filter_spec *spec,
3916                                 u64 *handle, bool replacing)
3917 {
3918         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3919         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
3920         int rc;
3921
3922         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3923         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3924                           outbuf, sizeof(outbuf), NULL);
3925         if (rc == 0)
3926                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3927         if (rc == -ENOSPC)
3928                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3929         return rc;
3930 }
3931
3932 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3933 {
3934         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3935         unsigned int match_flags = spec->match_flags;
3936         unsigned int uc_match, mc_match;
3937         u32 mcdi_flags = 0;
3938
3939 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) {          \
3940                 unsigned int  old_match_flags = match_flags;            \
3941                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
3942                 if (match_flags != old_match_flags)                     \
3943                         mcdi_flags |=                                   \
3944                                 (1 << ((encap) ?                        \
3945                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
3946                                        mcdi_field ## _LBN :             \
3947                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
3948                                        mcdi_field ## _LBN));            \
3949         }
3950         /* inner or outer based on encap type */
3951         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
3952         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
3953         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
3954         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
3955         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
3956         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
3957         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
3958         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
3959         /* always outer */
3960         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
3961         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
3962 #undef MAP_FILTER_TO_MCDI_FLAG
3963
3964         /* special handling for encap type, and mismatch */
3965         if (encap_type) {
3966                 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
3967                 mcdi_flags |=
3968                         (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
3969                 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
3970
3971                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3972                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3973         } else {
3974                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3975                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3976         }
3977
3978         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3979                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3980                 mcdi_flags |=
3981                         is_multicast_ether_addr(spec->loc_mac) ?
3982                         1 << mc_match :
3983                         1 << uc_match;
3984         }
3985
3986         /* Did we map them all? */
3987         WARN_ON_ONCE(match_flags);
3988
3989         return mcdi_flags;
3990 }
3991
3992 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3993                                const struct efx_filter_spec *spec)
3994 {
3995         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3996         unsigned int match_pri;
3997
3998         for (match_pri = 0;
3999              match_pri < table->rx_match_count;
4000              match_pri++)
4001                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4002                         return match_pri;
4003
4004         return -EPROTONOSUPPORT;
4005 }
4006
4007 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4008                                   struct efx_filter_spec *spec,
4009                                   bool replace_equal)
4010 {
4011         struct efx_ef10_filter_table *table = efx->filter_state;
4012         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4013         struct efx_filter_spec *saved_spec;
4014         unsigned int match_pri, hash;
4015         unsigned int priv_flags;
4016         bool replacing = false;
4017         int ins_index = -1;
4018         DEFINE_WAIT(wait);
4019         bool is_mc_recip;
4020         s32 rc;
4021
4022         /* For now, only support RX filters */
4023         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4024             EFX_FILTER_FLAG_RX)
4025                 return -EINVAL;
4026
4027         rc = efx_ef10_filter_pri(table, spec);
4028         if (rc < 0)
4029                 return rc;
4030         match_pri = rc;
4031
4032         hash = efx_ef10_filter_hash(spec);
4033         is_mc_recip = efx_filter_is_mc_recipient(spec);
4034         if (is_mc_recip)
4035                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4036
4037         /* Find any existing filters with the same match tuple or
4038          * else a free slot to insert at.  If any of them are busy,
4039          * we have to wait and retry.
4040          */
4041         for (;;) {
4042                 unsigned int depth = 1;
4043                 unsigned int i;
4044
4045                 spin_lock_bh(&efx->filter_lock);
4046
4047                 for (;;) {
4048                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4049                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4050
4051                         if (!saved_spec) {
4052                                 if (ins_index < 0)
4053                                         ins_index = i;
4054                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4055                                 if (table->entry[i].spec &
4056                                     EFX_EF10_FILTER_FLAG_BUSY)
4057                                         break;
4058                                 if (spec->priority < saved_spec->priority &&
4059                                     spec->priority != EFX_FILTER_PRI_AUTO) {
4060                                         rc = -EPERM;
4061                                         goto out_unlock;
4062                                 }
4063                                 if (!is_mc_recip) {
4064                                         /* This is the only one */
4065                                         if (spec->priority ==
4066                                             saved_spec->priority &&
4067                                             !replace_equal) {
4068                                                 rc = -EEXIST;
4069                                                 goto out_unlock;
4070                                         }
4071                                         ins_index = i;
4072                                         goto found;
4073                                 } else if (spec->priority >
4074                                            saved_spec->priority ||
4075                                            (spec->priority ==
4076                                             saved_spec->priority &&
4077                                             replace_equal)) {
4078                                         if (ins_index < 0)
4079                                                 ins_index = i;
4080                                         else
4081                                                 __set_bit(depth, mc_rem_map);
4082                                 }
4083                         }
4084
4085                         /* Once we reach the maximum search depth, use
4086                          * the first suitable slot or return -EBUSY if
4087                          * there was none
4088                          */
4089                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4090                                 if (ins_index < 0) {
4091                                         rc = -EBUSY;
4092                                         goto out_unlock;
4093                                 }
4094                                 goto found;
4095                         }
4096
4097                         ++depth;
4098                 }
4099
4100                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4101                 spin_unlock_bh(&efx->filter_lock);
4102                 schedule();
4103         }
4104
4105 found:
4106         /* Create a software table entry if necessary, and mark it
4107          * busy.  We might yet fail to insert, but any attempt to
4108          * insert a conflicting filter while we're waiting for the
4109          * firmware must find the busy entry.
4110          */
4111         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4112         if (saved_spec) {
4113                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4114                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4115                         /* Just make sure it won't be removed */
4116                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4117                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4118                         table->entry[ins_index].spec &=
4119                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4120                         rc = ins_index;
4121                         goto out_unlock;
4122                 }
4123                 replacing = true;
4124                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4125         } else {
4126                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4127                 if (!saved_spec) {
4128                         rc = -ENOMEM;
4129                         goto out_unlock;
4130                 }
4131                 *saved_spec = *spec;
4132                 priv_flags = 0;
4133         }
4134         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4135                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4136
4137         /* Mark lower-priority multicast recipients busy prior to removal */
4138         if (is_mc_recip) {
4139                 unsigned int depth, i;
4140
4141                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4142                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4143                         if (test_bit(depth, mc_rem_map))
4144                                 table->entry[i].spec |=
4145                                         EFX_EF10_FILTER_FLAG_BUSY;
4146                 }
4147         }
4148
4149         spin_unlock_bh(&efx->filter_lock);
4150
4151         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4152                                   replacing);
4153
4154         /* Finalise the software table entry */
4155         spin_lock_bh(&efx->filter_lock);
4156         if (rc == 0) {
4157                 if (replacing) {
4158                         /* Update the fields that may differ */
4159                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4160                                 saved_spec->flags |=
4161                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
4162                         saved_spec->priority = spec->priority;
4163                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4164                         saved_spec->flags |= spec->flags;
4165                         saved_spec->rss_context = spec->rss_context;
4166                         saved_spec->dmaq_id = spec->dmaq_id;
4167                 }
4168         } else if (!replacing) {
4169                 kfree(saved_spec);
4170                 saved_spec = NULL;
4171         }
4172         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4173
4174         /* Remove and finalise entries for lower-priority multicast
4175          * recipients
4176          */
4177         if (is_mc_recip) {
4178                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4179                 unsigned int depth, i;
4180
4181                 memset(inbuf, 0, sizeof(inbuf));
4182
4183                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4184                         if (!test_bit(depth, mc_rem_map))
4185                                 continue;
4186
4187                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4188                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4189                         priv_flags = efx_ef10_filter_entry_flags(table, i);
4190
4191                         if (rc == 0) {
4192                                 spin_unlock_bh(&efx->filter_lock);
4193                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4194                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4195                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4196                                                table->entry[i].handle);
4197                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4198                                                   inbuf, sizeof(inbuf),
4199                                                   NULL, 0, NULL);
4200                                 spin_lock_bh(&efx->filter_lock);
4201                         }
4202
4203                         if (rc == 0) {
4204                                 kfree(saved_spec);
4205                                 saved_spec = NULL;
4206                                 priv_flags = 0;
4207                         } else {
4208                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4209                         }
4210                         efx_ef10_filter_set_entry(table, i, saved_spec,
4211                                                   priv_flags);
4212                 }
4213         }
4214
4215         /* If successful, return the inserted filter ID */
4216         if (rc == 0)
4217                 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4218
4219         wake_up_all(&table->waitq);
4220 out_unlock:
4221         spin_unlock_bh(&efx->filter_lock);
4222         finish_wait(&table->waitq, &wait);
4223         return rc;
4224 }
4225
4226 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4227 {
4228         /* no need to do anything here on EF10 */
4229 }
4230
4231 /* Remove a filter.
4232  * If !by_index, remove by ID
4233  * If by_index, remove by index
4234  * Filter ID may come from userland and must be range-checked.
4235  */
4236 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4237                                            unsigned int priority_mask,
4238                                            u32 filter_id, bool by_index)
4239 {
4240         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4241         struct efx_ef10_filter_table *table = efx->filter_state;
4242         MCDI_DECLARE_BUF(inbuf,
4243                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4244                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4245         struct efx_filter_spec *spec;
4246         DEFINE_WAIT(wait);
4247         int rc;
4248
4249         /* Find the software table entry and mark it busy.  Don't
4250          * remove it yet; any attempt to update while we're waiting
4251          * for the firmware must find the busy entry.
4252          */
4253         for (;;) {
4254                 spin_lock_bh(&efx->filter_lock);
4255                 if (!(table->entry[filter_idx].spec &
4256                       EFX_EF10_FILTER_FLAG_BUSY))
4257                         break;
4258                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4259                 spin_unlock_bh(&efx->filter_lock);
4260                 schedule();
4261         }
4262
4263         spec = efx_ef10_filter_entry_spec(table, filter_idx);
4264         if (!spec ||
4265             (!by_index &&
4266              efx_ef10_filter_pri(table, spec) !=
4267              efx_ef10_filter_get_unsafe_pri(filter_id))) {
4268                 rc = -ENOENT;
4269                 goto out_unlock;
4270         }
4271
4272         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4273             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4274                 /* Just remove flags */
4275                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4276                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4277                 rc = 0;
4278                 goto out_unlock;
4279         }
4280
4281         if (!(priority_mask & (1U << spec->priority))) {
4282                 rc = -ENOENT;
4283                 goto out_unlock;
4284         }
4285
4286         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4287         spin_unlock_bh(&efx->filter_lock);
4288
4289         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4290                 /* Reset to an automatic filter */
4291
4292                 struct efx_filter_spec new_spec = *spec;
4293
4294                 new_spec.priority = EFX_FILTER_PRI_AUTO;
4295                 new_spec.flags = (EFX_FILTER_FLAG_RX |
4296                                   (efx_rss_enabled(efx) ?
4297                                    EFX_FILTER_FLAG_RX_RSS : 0));
4298                 new_spec.dmaq_id = 0;
4299                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4300                 rc = efx_ef10_filter_push(efx, &new_spec,
4301                                           &table->entry[filter_idx].handle,
4302                                           true);
4303
4304                 spin_lock_bh(&efx->filter_lock);
4305                 if (rc == 0)
4306                         *spec = new_spec;
4307         } else {
4308                 /* Really remove the filter */
4309
4310                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4311                                efx_ef10_filter_is_exclusive(spec) ?
4312                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4313                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4314                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4315                                table->entry[filter_idx].handle);
4316                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4317                                         inbuf, sizeof(inbuf), NULL, 0, NULL);
4318
4319                 spin_lock_bh(&efx->filter_lock);
4320                 if ((rc == 0) || (rc == -ENOENT)) {
4321                         /* Filter removed OK or didn't actually exist */
4322                         kfree(spec);
4323                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4324                 } else {
4325                         efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4326                                                MC_CMD_FILTER_OP_EXT_IN_LEN,
4327                                                NULL, 0, rc);
4328                 }
4329         }
4330
4331         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4332         wake_up_all(&table->waitq);
4333 out_unlock:
4334         spin_unlock_bh(&efx->filter_lock);
4335         finish_wait(&table->waitq, &wait);
4336         return rc;
4337 }
4338
4339 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4340                                        enum efx_filter_priority priority,
4341                                        u32 filter_id)
4342 {
4343         return efx_ef10_filter_remove_internal(efx, 1U << priority,
4344                                                filter_id, false);
4345 }
4346
4347 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4348                                           enum efx_filter_priority priority,
4349                                           u32 filter_id)
4350 {
4351         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4352                 return;
4353         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4354 }
4355
4356 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4357                                     enum efx_filter_priority priority,
4358                                     u32 filter_id, struct efx_filter_spec *spec)
4359 {
4360         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4361         struct efx_ef10_filter_table *table = efx->filter_state;
4362         const struct efx_filter_spec *saved_spec;
4363         int rc;
4364
4365         spin_lock_bh(&efx->filter_lock);
4366         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4367         if (saved_spec && saved_spec->priority == priority &&
4368             efx_ef10_filter_pri(table, saved_spec) ==
4369             efx_ef10_filter_get_unsafe_pri(filter_id)) {
4370                 *spec = *saved_spec;
4371                 rc = 0;
4372         } else {
4373                 rc = -ENOENT;
4374         }
4375         spin_unlock_bh(&efx->filter_lock);
4376         return rc;
4377 }
4378
4379 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4380                                      enum efx_filter_priority priority)
4381 {
4382         unsigned int priority_mask;
4383         unsigned int i;
4384         int rc;
4385
4386         priority_mask = (((1U << (priority + 1)) - 1) &
4387                          ~(1U << EFX_FILTER_PRI_AUTO));
4388
4389         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4390                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4391                                                      i, true);
4392                 if (rc && rc != -ENOENT)
4393                         return rc;
4394         }
4395
4396         return 0;
4397 }
4398
4399 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4400                                          enum efx_filter_priority priority)
4401 {
4402         struct efx_ef10_filter_table *table = efx->filter_state;
4403         unsigned int filter_idx;
4404         s32 count = 0;
4405
4406         spin_lock_bh(&efx->filter_lock);
4407         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4408                 if (table->entry[filter_idx].spec &&
4409                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4410                     priority)
4411                         ++count;
4412         }
4413         spin_unlock_bh(&efx->filter_lock);
4414         return count;
4415 }
4416
4417 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4418 {
4419         struct efx_ef10_filter_table *table = efx->filter_state;
4420
4421         return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4422 }
4423
4424 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4425                                       enum efx_filter_priority priority,
4426                                       u32 *buf, u32 size)
4427 {
4428         struct efx_ef10_filter_table *table = efx->filter_state;
4429         struct efx_filter_spec *spec;
4430         unsigned int filter_idx;
4431         s32 count = 0;
4432
4433         spin_lock_bh(&efx->filter_lock);
4434         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4435                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4436                 if (spec && spec->priority == priority) {
4437                         if (count == size) {
4438                                 count = -EMSGSIZE;
4439                                 break;
4440                         }
4441                         buf[count++] =
4442                                 efx_ef10_make_filter_id(
4443                                         efx_ef10_filter_pri(table, spec),
4444                                         filter_idx);
4445                 }
4446         }
4447         spin_unlock_bh(&efx->filter_lock);
4448         return count;
4449 }
4450
4451 #ifdef CONFIG_RFS_ACCEL
4452
4453 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4454
4455 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4456                                       struct efx_filter_spec *spec)
4457 {
4458         struct efx_ef10_filter_table *table = efx->filter_state;
4459         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4460         struct efx_filter_spec *saved_spec;
4461         unsigned int hash, i, depth = 1;
4462         bool replacing = false;
4463         int ins_index = -1;
4464         u64 cookie;
4465         s32 rc;
4466
4467         /* Must be an RX filter without RSS and not for a multicast
4468          * destination address (RFS only works for connected sockets).
4469          * These restrictions allow us to pass only a tiny amount of
4470          * data through to the completion function.
4471          */
4472         EFX_WARN_ON_PARANOID(spec->flags !=
4473                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4474         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4475         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4476
4477         hash = efx_ef10_filter_hash(spec);
4478
4479         spin_lock_bh(&efx->filter_lock);
4480
4481         /* Find any existing filter with the same match tuple or else
4482          * a free slot to insert at.  If an existing filter is busy,
4483          * we have to give up.
4484          */
4485         for (;;) {
4486                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4487                 saved_spec = efx_ef10_filter_entry_spec(table, i);
4488
4489                 if (!saved_spec) {
4490                         if (ins_index < 0)
4491                                 ins_index = i;
4492                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4493                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4494                                 rc = -EBUSY;
4495                                 goto fail_unlock;
4496                         }
4497                         if (spec->priority < saved_spec->priority) {
4498                                 rc = -EPERM;
4499                                 goto fail_unlock;
4500                         }
4501                         ins_index = i;
4502                         break;
4503                 }
4504
4505                 /* Once we reach the maximum search depth, use the
4506                  * first suitable slot or return -EBUSY if there was
4507                  * none
4508                  */
4509                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4510                         if (ins_index < 0) {
4511                                 rc = -EBUSY;
4512                                 goto fail_unlock;
4513                         }
4514                         break;
4515                 }
4516
4517                 ++depth;
4518         }
4519
4520         /* Create a software table entry if necessary, and mark it
4521          * busy.  We might yet fail to insert, but any attempt to
4522          * insert a conflicting filter while we're waiting for the
4523          * firmware must find the busy entry.
4524          */
4525         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4526         if (saved_spec) {
4527                 replacing = true;
4528         } else {
4529                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4530                 if (!saved_spec) {
4531                         rc = -ENOMEM;
4532                         goto fail_unlock;
4533                 }
4534                 *saved_spec = *spec;
4535         }
4536         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4537                                   EFX_EF10_FILTER_FLAG_BUSY);
4538
4539         spin_unlock_bh(&efx->filter_lock);
4540
4541         /* Pack up the variables needed on completion */
4542         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4543
4544         efx_ef10_filter_push_prep(efx, spec, inbuf,
4545                                   table->entry[ins_index].handle, replacing);
4546         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4547                            MC_CMD_FILTER_OP_OUT_LEN,
4548                            efx_ef10_filter_rfs_insert_complete, cookie);
4549
4550         return ins_index;
4551
4552 fail_unlock:
4553         spin_unlock_bh(&efx->filter_lock);
4554         return rc;
4555 }
4556
4557 static void
4558 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4559                                     int rc, efx_dword_t *outbuf,
4560                                     size_t outlen_actual)
4561 {
4562         struct efx_ef10_filter_table *table = efx->filter_state;
4563         unsigned int ins_index, dmaq_id;
4564         struct efx_filter_spec *spec;
4565         bool replacing;
4566
4567         /* Unpack the cookie */
4568         replacing = cookie >> 31;
4569         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4570         dmaq_id = cookie & 0xffff;
4571
4572         spin_lock_bh(&efx->filter_lock);
4573         spec = efx_ef10_filter_entry_spec(table, ins_index);
4574         if (rc == 0) {
4575                 table->entry[ins_index].handle =
4576                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4577                 if (replacing)
4578                         spec->dmaq_id = dmaq_id;
4579         } else if (!replacing) {
4580                 kfree(spec);
4581                 spec = NULL;
4582         }
4583         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4584         spin_unlock_bh(&efx->filter_lock);
4585
4586         wake_up_all(&table->waitq);
4587 }
4588
4589 static void
4590 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4591                                     unsigned long filter_idx,
4592                                     int rc, efx_dword_t *outbuf,
4593                                     size_t outlen_actual);
4594
4595 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4596                                            unsigned int filter_idx)
4597 {
4598         struct efx_ef10_filter_table *table = efx->filter_state;
4599         struct efx_filter_spec *spec =
4600                 efx_ef10_filter_entry_spec(table, filter_idx);
4601         MCDI_DECLARE_BUF(inbuf,
4602                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4603                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4604
4605         if (!spec ||
4606             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4607             spec->priority != EFX_FILTER_PRI_HINT ||
4608             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4609                                  flow_id, filter_idx))
4610                 return false;
4611
4612         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4613                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4614         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4615                        table->entry[filter_idx].handle);
4616         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4617                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4618                 return false;
4619
4620         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4621         return true;
4622 }
4623
4624 static void
4625 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4626                                     unsigned long filter_idx,
4627                                     int rc, efx_dword_t *outbuf,
4628                                     size_t outlen_actual)
4629 {
4630         struct efx_ef10_filter_table *table = efx->filter_state;
4631         struct efx_filter_spec *spec =
4632                 efx_ef10_filter_entry_spec(table, filter_idx);
4633
4634         spin_lock_bh(&efx->filter_lock);
4635         if (rc == 0) {
4636                 kfree(spec);
4637                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4638         }
4639         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4640         wake_up_all(&table->waitq);
4641         spin_unlock_bh(&efx->filter_lock);
4642 }
4643
4644 #endif /* CONFIG_RFS_ACCEL */
4645
4646 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4647 {
4648         int match_flags = 0;
4649
4650 #define MAP_FLAG(gen_flag, mcdi_field) do {                             \
4651                 u32 old_mcdi_flags = mcdi_flags;                        \
4652                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##  \
4653                                      mcdi_field ## _LBN);               \
4654                 if (mcdi_flags != old_mcdi_flags)                       \
4655                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4656         } while (0)
4657
4658         if (encap) {
4659                 /* encap filters must specify encap type */
4660                 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4661                 /* and imply ethertype and ip proto */
4662                 mcdi_flags &=
4663                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4664                 mcdi_flags &=
4665                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4666                 /* VLAN tags refer to the outer packet */
4667                 MAP_FLAG(INNER_VID, INNER_VLAN);
4668                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4669                 /* everything else refers to the inner packet */
4670                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4671                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4672                 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4673                 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4674                 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4675                 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4676                 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4677                 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4678                 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4679                 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4680         } else {
4681                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4682                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4683                 MAP_FLAG(REM_HOST, SRC_IP);
4684                 MAP_FLAG(LOC_HOST, DST_IP);
4685                 MAP_FLAG(REM_MAC, SRC_MAC);
4686                 MAP_FLAG(REM_PORT, SRC_PORT);
4687                 MAP_FLAG(LOC_MAC, DST_MAC);
4688                 MAP_FLAG(LOC_PORT, DST_PORT);
4689                 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4690                 MAP_FLAG(INNER_VID, INNER_VLAN);
4691                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4692                 MAP_FLAG(IP_PROTO, IP_PROTO);
4693         }
4694 #undef MAP_FLAG
4695
4696         /* Did we map them all? */
4697         if (mcdi_flags)
4698                 return -EINVAL;
4699
4700         return match_flags;
4701 }
4702
4703 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4704 {
4705         struct efx_ef10_filter_table *table = efx->filter_state;
4706         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4707
4708         /* See comment in efx_ef10_filter_table_remove() */
4709         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4710                 return;
4711
4712         if (!table)
4713                 return;
4714
4715         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4716                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4717 }
4718
4719 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4720                                             bool encap,
4721                                             enum efx_filter_match_flags match_flags)
4722 {
4723         unsigned int match_pri;
4724         int mf;
4725
4726         for (match_pri = 0;
4727              match_pri < table->rx_match_count;
4728              match_pri++) {
4729                 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4730                                 table->rx_match_mcdi_flags[match_pri]);
4731                 if (mf == match_flags)
4732                         return true;
4733         }
4734
4735         return false;
4736 }
4737
4738 static int
4739 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4740                                     struct efx_ef10_filter_table *table,
4741                                     bool encap)
4742 {
4743         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4744         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4745         unsigned int pd_match_pri, pd_match_count;
4746         size_t outlen;
4747         int rc;
4748
4749         /* Find out which RX filter types are supported, and their priorities */
4750         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4751                        encap ?
4752                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4753                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4754         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4755                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4756                           &outlen);
4757         if (rc)
4758                 return rc;
4759
4760         pd_match_count = MCDI_VAR_ARRAY_LEN(
4761                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4762
4763         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4764                 u32 mcdi_flags =
4765                         MCDI_ARRAY_DWORD(
4766                                 outbuf,
4767                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4768                                 pd_match_pri);
4769                 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4770                 if (rc < 0) {
4771                         netif_dbg(efx, probe, efx->net_dev,
4772                                   "%s: fw flags %#x pri %u not supported in driver\n",
4773                                   __func__, mcdi_flags, pd_match_pri);
4774                 } else {
4775                         netif_dbg(efx, probe, efx->net_dev,
4776                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4777                                   __func__, mcdi_flags, pd_match_pri,
4778                                   rc, table->rx_match_count);
4779                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4780                         table->rx_match_count++;
4781                 }
4782         }
4783
4784         return 0;
4785 }
4786
4787 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4788 {
4789         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4790         struct net_device *net_dev = efx->net_dev;
4791         struct efx_ef10_filter_table *table;
4792         struct efx_ef10_vlan *vlan;
4793         int rc;
4794
4795         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4796                 return -EINVAL;
4797
4798         if (efx->filter_state) /* already probed */
4799                 return 0;
4800
4801         table = kzalloc(sizeof(*table), GFP_KERNEL);
4802         if (!table)
4803                 return -ENOMEM;
4804
4805         table->rx_match_count = 0;
4806         rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4807         if (rc)
4808                 goto fail;
4809         if (nic_data->datapath_caps &
4810                    (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4811                 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4812         if (rc)
4813                 goto fail;
4814         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4815             !(efx_ef10_filter_match_supported(table, false,
4816                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4817               efx_ef10_filter_match_supported(table, false,
4818                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4819                 netif_info(efx, probe, net_dev,
4820                            "VLAN filters are not supported in this firmware variant\n");
4821                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4822                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4823                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4824         }
4825
4826         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4827         if (!table->entry) {
4828                 rc = -ENOMEM;
4829                 goto fail;
4830         }
4831
4832         table->mc_promisc_last = false;
4833         table->vlan_filter =
4834                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4835         INIT_LIST_HEAD(&table->vlan_list);
4836
4837         efx->filter_state = table;
4838         init_waitqueue_head(&table->waitq);
4839
4840         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4841                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4842                 if (rc)
4843                         goto fail_add_vlan;
4844         }
4845
4846         return 0;
4847
4848 fail_add_vlan:
4849         efx_ef10_filter_cleanup_vlans(efx);
4850         efx->filter_state = NULL;
4851 fail:
4852         kfree(table);
4853         return rc;
4854 }
4855
4856 /* Caller must hold efx->filter_sem for read if race against
4857  * efx_ef10_filter_table_remove() is possible
4858  */
4859 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4860 {
4861         struct efx_ef10_filter_table *table = efx->filter_state;
4862         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4863         unsigned int invalid_filters = 0, failed = 0;
4864         struct efx_ef10_filter_vlan *vlan;
4865         struct efx_filter_spec *spec;
4866         unsigned int filter_idx;
4867         u32 mcdi_flags;
4868         int match_pri;
4869         int rc, i;
4870
4871         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4872
4873         if (!nic_data->must_restore_filters)
4874                 return;
4875
4876         if (!table)
4877                 return;
4878
4879         spin_lock_bh(&efx->filter_lock);
4880
4881         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4882                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4883                 if (!spec)
4884                         continue;
4885
4886                 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4887                 match_pri = 0;
4888                 while (match_pri < table->rx_match_count &&
4889                        table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4890                         ++match_pri;
4891                 if (match_pri >= table->rx_match_count) {
4892                         invalid_filters++;
4893                         goto not_restored;
4894                 }
4895                 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4896                     spec->rss_context != nic_data->rx_rss_context)
4897                         netif_warn(efx, drv, efx->net_dev,
4898                                    "Warning: unable to restore a filter with specific RSS context.\n");
4899
4900                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4901                 spin_unlock_bh(&efx->filter_lock);
4902
4903                 rc = efx_ef10_filter_push(efx, spec,
4904                                           &table->entry[filter_idx].handle,
4905                                           false);
4906                 if (rc)
4907                         failed++;
4908                 spin_lock_bh(&efx->filter_lock);
4909
4910                 if (rc) {
4911 not_restored:
4912                         list_for_each_entry(vlan, &table->vlan_list, list)
4913                                 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4914                                         if (vlan->default_filters[i] == filter_idx)
4915                                                 vlan->default_filters[i] =
4916                                                         EFX_EF10_FILTER_ID_INVALID;
4917
4918                         kfree(spec);
4919                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4920                 } else {
4921                         table->entry[filter_idx].spec &=
4922                                 ~EFX_EF10_FILTER_FLAG_BUSY;
4923                 }
4924         }
4925
4926         spin_unlock_bh(&efx->filter_lock);
4927
4928         /* This can happen validly if the MC's capabilities have changed, so
4929          * is not an error.
4930          */
4931         if (invalid_filters)
4932                 netif_dbg(efx, drv, efx->net_dev,
4933                           "Did not restore %u filters that are now unsupported.\n",
4934                           invalid_filters);
4935
4936         if (failed)
4937                 netif_err(efx, hw, efx->net_dev,
4938                           "unable to restore %u filters\n", failed);
4939         else
4940                 nic_data->must_restore_filters = false;
4941 }
4942
4943 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4944 {
4945         struct efx_ef10_filter_table *table = efx->filter_state;
4946         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4947         struct efx_filter_spec *spec;
4948         unsigned int filter_idx;
4949         int rc;
4950
4951         efx_ef10_filter_cleanup_vlans(efx);
4952         efx->filter_state = NULL;
4953         /* If we were called without locking, then it's not safe to free
4954          * the table as others might be using it.  So we just WARN, leak
4955          * the memory, and potentially get an inconsistent filter table
4956          * state.
4957          * This should never actually happen.
4958          */
4959         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4960                 return;
4961
4962         if (!table)
4963                 return;
4964
4965         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4966                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4967                 if (!spec)
4968                         continue;
4969
4970                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4971                                efx_ef10_filter_is_exclusive(spec) ?
4972                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4973                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4974                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4975                                table->entry[filter_idx].handle);
4976                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4977                                         sizeof(inbuf), NULL, 0, NULL);
4978                 if (rc)
4979                         netif_info(efx, drv, efx->net_dev,
4980                                    "%s: filter %04x remove failed\n",
4981                                    __func__, filter_idx);
4982                 kfree(spec);
4983         }
4984
4985         vfree(table->entry);
4986         kfree(table);
4987 }
4988
4989 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4990 {
4991         struct efx_ef10_filter_table *table = efx->filter_state;
4992         unsigned int filter_idx;
4993
4994         if (*id != EFX_EF10_FILTER_ID_INVALID) {
4995                 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
4996                 if (!table->entry[filter_idx].spec)
4997                         netif_dbg(efx, drv, efx->net_dev,
4998                                   "marked null spec old %04x:%04x\n", *id,
4999                                   filter_idx);
5000                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5001                 *id = EFX_EF10_FILTER_ID_INVALID;
5002         }
5003 }
5004
5005 /* Mark old per-VLAN filters that may need to be removed */
5006 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5007                                            struct efx_ef10_filter_vlan *vlan)
5008 {
5009         struct efx_ef10_filter_table *table = efx->filter_state;
5010         unsigned int i;
5011
5012         for (i = 0; i < table->dev_uc_count; i++)
5013                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5014         for (i = 0; i < table->dev_mc_count; i++)
5015                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5016         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5017                 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5018 }
5019
5020 /* Mark old filters that may need to be removed.
5021  * Caller must hold efx->filter_sem for read if race against
5022  * efx_ef10_filter_table_remove() is possible
5023  */
5024 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5025 {
5026         struct efx_ef10_filter_table *table = efx->filter_state;
5027         struct efx_ef10_filter_vlan *vlan;
5028
5029         spin_lock_bh(&efx->filter_lock);
5030         list_for_each_entry(vlan, &table->vlan_list, list)
5031                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5032         spin_unlock_bh(&efx->filter_lock);
5033 }
5034
5035 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5036 {
5037         struct efx_ef10_filter_table *table = efx->filter_state;
5038         struct net_device *net_dev = efx->net_dev;
5039         struct netdev_hw_addr *uc;
5040         unsigned int i;
5041
5042         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5043         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5044         i = 1;
5045         netdev_for_each_uc_addr(uc, net_dev) {
5046                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5047                         table->uc_promisc = true;
5048                         break;
5049                 }
5050                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5051                 i++;
5052         }
5053
5054         table->dev_uc_count = i;
5055 }
5056
5057 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5058 {
5059         struct efx_ef10_filter_table *table = efx->filter_state;
5060         struct net_device *net_dev = efx->net_dev;
5061         struct netdev_hw_addr *mc;
5062         unsigned int i;
5063
5064         table->mc_overflow = false;
5065         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5066
5067         i = 0;
5068         netdev_for_each_mc_addr(mc, net_dev) {
5069                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5070                         table->mc_promisc = true;
5071                         table->mc_overflow = true;
5072                         break;
5073                 }
5074                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5075                 i++;
5076         }
5077
5078         table->dev_mc_count = i;
5079 }
5080
5081 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5082                                             struct efx_ef10_filter_vlan *vlan,
5083                                             bool multicast, bool rollback)
5084 {
5085         struct efx_ef10_filter_table *table = efx->filter_state;
5086         struct efx_ef10_dev_addr *addr_list;
5087         enum efx_filter_flags filter_flags;
5088         struct efx_filter_spec spec;
5089         u8 baddr[ETH_ALEN];
5090         unsigned int i, j;
5091         int addr_count;
5092         u16 *ids;
5093         int rc;
5094
5095         if (multicast) {
5096                 addr_list = table->dev_mc_list;
5097                 addr_count = table->dev_mc_count;
5098                 ids = vlan->mc;
5099         } else {
5100                 addr_list = table->dev_uc_list;
5101                 addr_count = table->dev_uc_count;
5102                 ids = vlan->uc;
5103         }
5104
5105         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5106
5107         /* Insert/renew filters */
5108         for (i = 0; i < addr_count; i++) {
5109                 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5110                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5111                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5112                 rc = efx_ef10_filter_insert(efx, &spec, true);
5113                 if (rc < 0) {
5114                         if (rollback) {
5115                                 netif_info(efx, drv, efx->net_dev,
5116                                            "efx_ef10_filter_insert failed rc=%d\n",
5117                                            rc);
5118                                 /* Fall back to promiscuous */
5119                                 for (j = 0; j < i; j++) {
5120                                         efx_ef10_filter_remove_unsafe(
5121                                                 efx, EFX_FILTER_PRI_AUTO,
5122                                                 ids[j]);
5123                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
5124                                 }
5125                                 return rc;
5126                         } else {
5127                                 /* keep invalid ID, and carry on */
5128                         }
5129                 } else {
5130                         ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5131                 }
5132         }
5133
5134         if (multicast && rollback) {
5135                 /* Also need an Ethernet broadcast filter */
5136                 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5137                                      EFX_EF10_FILTER_ID_INVALID);
5138                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5139                 eth_broadcast_addr(baddr);
5140                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5141                 rc = efx_ef10_filter_insert(efx, &spec, true);
5142                 if (rc < 0) {
5143                         netif_warn(efx, drv, efx->net_dev,
5144                                    "Broadcast filter insert failed rc=%d\n", rc);
5145                         /* Fall back to promiscuous */
5146                         for (j = 0; j < i; j++) {
5147                                 efx_ef10_filter_remove_unsafe(
5148                                         efx, EFX_FILTER_PRI_AUTO,
5149                                         ids[j]);
5150                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5151                         }
5152                         return rc;
5153                 } else {
5154                         vlan->default_filters[EFX_EF10_BCAST] =
5155                                 efx_ef10_filter_get_unsafe_id(rc);
5156                 }
5157         }
5158
5159         return 0;
5160 }
5161
5162 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5163                                       struct efx_ef10_filter_vlan *vlan,
5164                                       enum efx_encap_type encap_type,
5165                                       bool multicast, bool rollback)
5166 {
5167         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5168         enum efx_filter_flags filter_flags;
5169         struct efx_filter_spec spec;
5170         u8 baddr[ETH_ALEN];
5171         int rc;
5172         u16 *id;
5173
5174         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5175
5176         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5177
5178         if (multicast)
5179                 efx_filter_set_mc_def(&spec);
5180         else
5181                 efx_filter_set_uc_def(&spec);
5182
5183         if (encap_type) {
5184                 if (nic_data->datapath_caps &
5185                     (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5186                         efx_filter_set_encap_type(&spec, encap_type);
5187                 else
5188                         /* don't insert encap filters on non-supporting
5189                          * platforms. ID will be left as INVALID.
5190                          */
5191                         return 0;
5192         }
5193
5194         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5195                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5196
5197         rc = efx_ef10_filter_insert(efx, &spec, true);
5198         if (rc < 0) {
5199                 const char *um = multicast ? "Multicast" : "Unicast";
5200                 const char *encap_name = "";
5201                 const char *encap_ipv = "";
5202
5203                 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5204                     EFX_ENCAP_TYPE_VXLAN)
5205                         encap_name = "VXLAN ";
5206                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5207                          EFX_ENCAP_TYPE_NVGRE)
5208                         encap_name = "NVGRE ";
5209                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5210                          EFX_ENCAP_TYPE_GENEVE)
5211                         encap_name = "GENEVE ";
5212                 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5213                         encap_ipv = "IPv6 ";
5214                 else if (encap_type)
5215                         encap_ipv = "IPv4 ";
5216
5217                 /* unprivileged functions can't insert mismatch filters
5218                  * for encapsulated or unicast traffic, so downgrade
5219                  * those warnings to debug.
5220                  */
5221                 netif_cond_dbg(efx, drv, efx->net_dev,
5222                                rc == -EPERM && (encap_type || !multicast), warn,
5223                                "%s%s%s mismatch filter insert failed rc=%d\n",
5224                                encap_name, encap_ipv, um, rc);
5225         } else if (multicast) {
5226                 /* mapping from encap types to default filter IDs (multicast) */
5227                 static enum efx_ef10_default_filters map[] = {
5228                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5229                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5230                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5231                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5232                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5233                                 EFX_EF10_VXLAN6_MCDEF,
5234                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5235                                 EFX_EF10_NVGRE6_MCDEF,
5236                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5237                                 EFX_EF10_GENEVE6_MCDEF,
5238                 };
5239
5240                 /* quick bounds check (BCAST result impossible) */
5241                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5242                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5243                         WARN_ON(1);
5244                         return -EINVAL;
5245                 }
5246                 /* then follow map */
5247                 id = &vlan->default_filters[map[encap_type]];
5248
5249                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5250                 *id = efx_ef10_filter_get_unsafe_id(rc);
5251                 if (!nic_data->workaround_26807 && !encap_type) {
5252                         /* Also need an Ethernet broadcast filter */
5253                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5254                                            filter_flags, 0);
5255                         eth_broadcast_addr(baddr);
5256                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5257                         rc = efx_ef10_filter_insert(efx, &spec, true);
5258                         if (rc < 0) {
5259                                 netif_warn(efx, drv, efx->net_dev,
5260                                            "Broadcast filter insert failed rc=%d\n",
5261                                            rc);
5262                                 if (rollback) {
5263                                         /* Roll back the mc_def filter */
5264                                         efx_ef10_filter_remove_unsafe(
5265                                                         efx, EFX_FILTER_PRI_AUTO,
5266                                                         *id);
5267                                         *id = EFX_EF10_FILTER_ID_INVALID;
5268                                         return rc;
5269                                 }
5270                         } else {
5271                                 EFX_WARN_ON_PARANOID(
5272                                         vlan->default_filters[EFX_EF10_BCAST] !=
5273                                         EFX_EF10_FILTER_ID_INVALID);
5274                                 vlan->default_filters[EFX_EF10_BCAST] =
5275                                         efx_ef10_filter_get_unsafe_id(rc);
5276                         }
5277                 }
5278                 rc = 0;
5279         } else {
5280                 /* mapping from encap types to default filter IDs (unicast) */
5281                 static enum efx_ef10_default_filters map[] = {
5282                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5283                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5284                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5285                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5286                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5287                                 EFX_EF10_VXLAN6_UCDEF,
5288                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5289                                 EFX_EF10_NVGRE6_UCDEF,
5290                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5291                                 EFX_EF10_GENEVE6_UCDEF,
5292                 };
5293
5294                 /* quick bounds check (BCAST result impossible) */
5295                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5296                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5297                         WARN_ON(1);
5298                         return -EINVAL;
5299                 }
5300                 /* then follow map */
5301                 id = &vlan->default_filters[map[encap_type]];
5302                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5303                 *id = rc;
5304                 rc = 0;
5305         }
5306         return rc;
5307 }
5308
5309 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
5310  * flag or removes these filters, we don't need to hold the filter_lock while
5311  * scanning for these filters.
5312  */
5313 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5314 {
5315         struct efx_ef10_filter_table *table = efx->filter_state;
5316         int remove_failed = 0;
5317         int remove_noent = 0;
5318         int rc;
5319         int i;
5320
5321         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5322                 if (ACCESS_ONCE(table->entry[i].spec) &
5323                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5324                         rc = efx_ef10_filter_remove_internal(efx,
5325                                         1U << EFX_FILTER_PRI_AUTO, i, true);
5326                         if (rc == -ENOENT)
5327                                 remove_noent++;
5328                         else if (rc)
5329                                 remove_failed++;
5330                 }
5331         }
5332
5333         if (remove_failed)
5334                 netif_info(efx, drv, efx->net_dev,
5335                            "%s: failed to remove %d filters\n",
5336                            __func__, remove_failed);
5337         if (remove_noent)
5338                 netif_info(efx, drv, efx->net_dev,
5339                            "%s: failed to remove %d non-existent filters\n",
5340                            __func__, remove_noent);
5341 }
5342
5343 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5344 {
5345         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5346         u8 mac_old[ETH_ALEN];
5347         int rc, rc2;
5348
5349         /* Only reconfigure a PF-created vport */
5350         if (is_zero_ether_addr(nic_data->vport_mac))
5351                 return 0;
5352
5353         efx_device_detach_sync(efx);
5354         efx_net_stop(efx->net_dev);
5355         down_write(&efx->filter_sem);
5356         efx_ef10_filter_table_remove(efx);
5357         up_write(&efx->filter_sem);
5358
5359         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5360         if (rc)
5361                 goto restore_filters;
5362
5363         ether_addr_copy(mac_old, nic_data->vport_mac);
5364         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5365                                     nic_data->vport_mac);
5366         if (rc)
5367                 goto restore_vadaptor;
5368
5369         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5370                                     efx->net_dev->dev_addr);
5371         if (!rc) {
5372                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5373         } else {
5374                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5375                 if (rc2) {
5376                         /* Failed to add original MAC, so clear vport_mac */
5377                         eth_zero_addr(nic_data->vport_mac);
5378                         goto reset_nic;
5379                 }
5380         }
5381
5382 restore_vadaptor:
5383         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5384         if (rc2)
5385                 goto reset_nic;
5386 restore_filters:
5387         down_write(&efx->filter_sem);
5388         rc2 = efx_ef10_filter_table_probe(efx);
5389         up_write(&efx->filter_sem);
5390         if (rc2)
5391                 goto reset_nic;
5392
5393         rc2 = efx_net_open(efx->net_dev);
5394         if (rc2)
5395                 goto reset_nic;
5396
5397         efx_device_attach_if_not_resetting(efx);
5398
5399         return rc;
5400
5401 reset_nic:
5402         netif_err(efx, drv, efx->net_dev,
5403                   "Failed to restore when changing MAC address - scheduling reset\n");
5404         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5405
5406         return rc ? rc : rc2;
5407 }
5408
5409 /* Caller must hold efx->filter_sem for read if race against
5410  * efx_ef10_filter_table_remove() is possible
5411  */
5412 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5413                                               struct efx_ef10_filter_vlan *vlan)
5414 {
5415         struct efx_ef10_filter_table *table = efx->filter_state;
5416         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5417
5418         /* Do not install unspecified VID if VLAN filtering is enabled.
5419          * Do not install all specified VIDs if VLAN filtering is disabled.
5420          */
5421         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5422                 return;
5423
5424         /* Insert/renew unicast filters */
5425         if (table->uc_promisc) {
5426                 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5427                                            false, false);
5428                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5429         } else {
5430                 /* If any of the filters failed to insert, fall back to
5431                  * promiscuous mode - add in the uc_def filter.  But keep
5432                  * our individual unicast filters.
5433                  */
5434                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5435                         efx_ef10_filter_insert_def(efx, vlan,
5436                                                    EFX_ENCAP_TYPE_NONE,
5437                                                    false, false);
5438         }
5439         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5440                                    false, false);
5441         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5442                                               EFX_ENCAP_FLAG_IPV6,
5443                                    false, false);
5444         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5445                                    false, false);
5446         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5447                                               EFX_ENCAP_FLAG_IPV6,
5448                                    false, false);
5449         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5450                                    false, false);
5451         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5452                                               EFX_ENCAP_FLAG_IPV6,
5453                                    false, false);
5454
5455         /* Insert/renew multicast filters */
5456         /* If changing promiscuous state with cascaded multicast filters, remove
5457          * old filters first, so that packets are dropped rather than duplicated
5458          */
5459         if (nic_data->workaround_26807 &&
5460             table->mc_promisc_last != table->mc_promisc)
5461                 efx_ef10_filter_remove_old(efx);
5462         if (table->mc_promisc) {
5463                 if (nic_data->workaround_26807) {
5464                         /* If we failed to insert promiscuous filters, rollback
5465                          * and fall back to individual multicast filters
5466                          */
5467                         if (efx_ef10_filter_insert_def(efx, vlan,
5468                                                        EFX_ENCAP_TYPE_NONE,
5469                                                        true, true)) {
5470                                 /* Changing promisc state, so remove old filters */
5471                                 efx_ef10_filter_remove_old(efx);
5472                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5473                                                                  true, false);
5474                         }
5475                 } else {
5476                         /* If we failed to insert promiscuous filters, don't
5477                          * rollback.  Regardless, also insert the mc_list,
5478                          * unless it's incomplete due to overflow
5479                          */
5480                         efx_ef10_filter_insert_def(efx, vlan,
5481                                                    EFX_ENCAP_TYPE_NONE,
5482                                                    true, false);
5483                         if (!table->mc_overflow)
5484                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5485                                                                  true, false);
5486                 }
5487         } else {
5488                 /* If any filters failed to insert, rollback and fall back to
5489                  * promiscuous mode - mc_def filter and maybe broadcast.  If
5490                  * that fails, roll back again and insert as many of our
5491                  * individual multicast filters as we can.
5492                  */
5493                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5494                         /* Changing promisc state, so remove old filters */
5495                         if (nic_data->workaround_26807)
5496                                 efx_ef10_filter_remove_old(efx);
5497                         if (efx_ef10_filter_insert_def(efx, vlan,
5498                                                        EFX_ENCAP_TYPE_NONE,
5499                                                        true, true))
5500                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5501                                                                  true, false);
5502                 }
5503         }
5504         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5505                                    true, false);
5506         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5507                                               EFX_ENCAP_FLAG_IPV6,
5508                                    true, false);
5509         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5510                                    true, false);
5511         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5512                                               EFX_ENCAP_FLAG_IPV6,
5513                                    true, false);
5514         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5515                                    true, false);
5516         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5517                                               EFX_ENCAP_FLAG_IPV6,
5518                                    true, false);
5519 }
5520
5521 /* Caller must hold efx->filter_sem for read if race against
5522  * efx_ef10_filter_table_remove() is possible
5523  */
5524 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5525 {
5526         struct efx_ef10_filter_table *table = efx->filter_state;
5527         struct net_device *net_dev = efx->net_dev;
5528         struct efx_ef10_filter_vlan *vlan;
5529         bool vlan_filter;
5530
5531         if (!efx_dev_registered(efx))
5532                 return;
5533
5534         if (!table)
5535                 return;
5536
5537         efx_ef10_filter_mark_old(efx);
5538
5539         /* Copy/convert the address lists; add the primary station
5540          * address and broadcast address
5541          */
5542         netif_addr_lock_bh(net_dev);
5543         efx_ef10_filter_uc_addr_list(efx);
5544         efx_ef10_filter_mc_addr_list(efx);
5545         netif_addr_unlock_bh(net_dev);
5546
5547         /* If VLAN filtering changes, all old filters are finally removed.
5548          * Do it in advance to avoid conflicts for unicast untagged and
5549          * VLAN 0 tagged filters.
5550          */
5551         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5552         if (table->vlan_filter != vlan_filter) {
5553                 table->vlan_filter = vlan_filter;
5554                 efx_ef10_filter_remove_old(efx);
5555         }
5556
5557         list_for_each_entry(vlan, &table->vlan_list, list)
5558                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5559
5560         efx_ef10_filter_remove_old(efx);
5561         table->mc_promisc_last = table->mc_promisc;
5562 }
5563
5564 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5565 {
5566         struct efx_ef10_filter_table *table = efx->filter_state;
5567         struct efx_ef10_filter_vlan *vlan;
5568
5569         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5570
5571         list_for_each_entry(vlan, &table->vlan_list, list) {
5572                 if (vlan->vid == vid)
5573                         return vlan;
5574         }
5575
5576         return NULL;
5577 }
5578
5579 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5580 {
5581         struct efx_ef10_filter_table *table = efx->filter_state;
5582         struct efx_ef10_filter_vlan *vlan;
5583         unsigned int i;
5584
5585         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5586                 return -EINVAL;
5587
5588         vlan = efx_ef10_filter_find_vlan(efx, vid);
5589         if (WARN_ON(vlan)) {
5590                 netif_err(efx, drv, efx->net_dev,
5591                           "VLAN %u already added\n", vid);
5592                 return -EALREADY;
5593         }
5594
5595         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5596         if (!vlan)
5597                 return -ENOMEM;
5598
5599         vlan->vid = vid;
5600
5601         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5602                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5603         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5604                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5605         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5606                 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5607
5608         list_add_tail(&vlan->list, &table->vlan_list);
5609
5610         if (efx_dev_registered(efx))
5611                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5612
5613         return 0;
5614 }
5615
5616 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5617                                               struct efx_ef10_filter_vlan *vlan)
5618 {
5619         unsigned int i;
5620
5621         /* See comment in efx_ef10_filter_table_remove() */
5622         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5623                 return;
5624
5625         list_del(&vlan->list);
5626
5627         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5628                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5629                                               vlan->uc[i]);
5630         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5631                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5632                                               vlan->mc[i]);
5633         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5634                 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5635                         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5636                                                       vlan->default_filters[i]);
5637
5638         kfree(vlan);
5639 }
5640
5641 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5642 {
5643         struct efx_ef10_filter_vlan *vlan;
5644
5645         /* See comment in efx_ef10_filter_table_remove() */
5646         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5647                 return;
5648
5649         vlan = efx_ef10_filter_find_vlan(efx, vid);
5650         if (!vlan) {
5651                 netif_err(efx, drv, efx->net_dev,
5652                           "VLAN %u not found in filter state\n", vid);
5653                 return;
5654         }
5655
5656         efx_ef10_filter_del_vlan_internal(efx, vlan);
5657 }
5658
5659 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5660 {
5661         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5662         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5663         bool was_enabled = efx->port_enabled;
5664         int rc;
5665
5666         efx_device_detach_sync(efx);
5667         efx_net_stop(efx->net_dev);
5668
5669         mutex_lock(&efx->mac_lock);
5670         down_write(&efx->filter_sem);
5671         efx_ef10_filter_table_remove(efx);
5672
5673         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5674                         efx->net_dev->dev_addr);
5675         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5676                        nic_data->vport_id);
5677         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5678                                 sizeof(inbuf), NULL, 0, NULL);
5679
5680         efx_ef10_filter_table_probe(efx);
5681         up_write(&efx->filter_sem);
5682         mutex_unlock(&efx->mac_lock);
5683
5684         if (was_enabled)
5685                 efx_net_open(efx->net_dev);
5686         efx_device_attach_if_not_resetting(efx);
5687
5688 #ifdef CONFIG_SFC_SRIOV
5689         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5690                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5691
5692                 if (rc == -EPERM) {
5693                         struct efx_nic *efx_pf;
5694
5695                         /* Switch to PF and change MAC address on vport */
5696                         efx_pf = pci_get_drvdata(pci_dev_pf);
5697
5698                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5699                                                        nic_data->vf_index,
5700                                                        efx->net_dev->dev_addr);
5701                 } else if (!rc) {
5702                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5703                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5704                         unsigned int i;
5705
5706                         /* MAC address successfully changed by VF (with MAC
5707                          * spoofing) so update the parent PF if possible.
5708                          */
5709                         for (i = 0; i < efx_pf->vf_count; ++i) {
5710                                 struct ef10_vf *vf = nic_data->vf + i;
5711
5712                                 if (vf->efx == efx) {
5713                                         ether_addr_copy(vf->mac,
5714                                                         efx->net_dev->dev_addr);
5715                                         return 0;
5716                                 }
5717                         }
5718                 }
5719         } else
5720 #endif
5721         if (rc == -EPERM) {
5722                 netif_err(efx, drv, efx->net_dev,
5723                           "Cannot change MAC address; use sfboot to enable"
5724                           " mac-spoofing on this interface\n");
5725         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5726                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5727                  * fall-back to the method of changing the MAC address on the
5728                  * vport.  This only applies to PFs because such versions of
5729                  * MCFW do not support VFs.
5730                  */
5731                 rc = efx_ef10_vport_set_mac_address(efx);
5732         } else if (rc) {
5733                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5734                                        sizeof(inbuf), NULL, 0, rc);
5735         }
5736
5737         return rc;
5738 }
5739
5740 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5741 {
5742         efx_ef10_filter_sync_rx_mode(efx);
5743
5744         return efx_mcdi_set_mac(efx);
5745 }
5746
5747 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5748 {
5749         efx_ef10_filter_sync_rx_mode(efx);
5750
5751         return 0;
5752 }
5753
5754 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5755 {
5756         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5757
5758         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5759         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5760                             NULL, 0, NULL);
5761 }
5762
5763 /* MC BISTs follow a different poll mechanism to phy BISTs.
5764  * The BIST is done in the poll handler on the MC, and the MCDI command
5765  * will block until the BIST is done.
5766  */
5767 static int efx_ef10_poll_bist(struct efx_nic *efx)
5768 {
5769         int rc;
5770         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5771         size_t outlen;
5772         u32 result;
5773
5774         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5775                            outbuf, sizeof(outbuf), &outlen);
5776         if (rc != 0)
5777                 return rc;
5778
5779         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5780                 return -EIO;
5781
5782         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5783         switch (result) {
5784         case MC_CMD_POLL_BIST_PASSED:
5785                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5786                 return 0;
5787         case MC_CMD_POLL_BIST_TIMEOUT:
5788                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5789                 return -EIO;
5790         case MC_CMD_POLL_BIST_FAILED:
5791                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5792                 return -EIO;
5793         default:
5794                 netif_err(efx, hw, efx->net_dev,
5795                           "BIST returned unknown result %u", result);
5796                 return -EIO;
5797         }
5798 }
5799
5800 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5801 {
5802         int rc;
5803
5804         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5805
5806         rc = efx_ef10_start_bist(efx, bist_type);
5807         if (rc != 0)
5808                 return rc;
5809
5810         return efx_ef10_poll_bist(efx);
5811 }
5812
5813 static int
5814 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5815 {
5816         int rc, rc2;
5817
5818         efx_reset_down(efx, RESET_TYPE_WORLD);
5819
5820         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5821                           NULL, 0, NULL, 0, NULL);
5822         if (rc != 0)
5823                 goto out;
5824
5825         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5826         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5827
5828         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5829
5830 out:
5831         if (rc == -EPERM)
5832                 rc = 0;
5833         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5834         return rc ? rc : rc2;
5835 }
5836
5837 #ifdef CONFIG_SFC_MTD
5838
5839 struct efx_ef10_nvram_type_info {
5840         u16 type, type_mask;
5841         u8 port;
5842         const char *name;
5843 };
5844
5845 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5846         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
5847         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
5848         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
5849         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
5850         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
5851         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
5852         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
5853         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
5854         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
5855         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
5856         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
5857 };
5858 #define EF10_NVRAM_PARTITION_COUNT      ARRAY_SIZE(efx_ef10_nvram_types)
5859
5860 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5861                                         struct efx_mcdi_mtd_partition *part,
5862                                         unsigned int type,
5863                                         unsigned long *found)
5864 {
5865         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5866         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5867         const struct efx_ef10_nvram_type_info *info;
5868         size_t size, erase_size, outlen;
5869         int type_idx = 0;
5870         bool protected;
5871         int rc;
5872
5873         for (type_idx = 0; ; type_idx++) {
5874                 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
5875                         return -ENODEV;
5876                 info = efx_ef10_nvram_types + type_idx;
5877                 if ((type & ~info->type_mask) == info->type)
5878                         break;
5879         }
5880         if (info->port != efx_port_num(efx))
5881                 return -ENODEV;
5882
5883         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5884         if (rc)
5885                 return rc;
5886         if (protected)
5887                 return -ENODEV; /* hide it */
5888
5889         /* If we've already exposed a partition of this type, hide this
5890          * duplicate.  All operations on MTDs are keyed by the type anyway,
5891          * so we can't act on the duplicate.
5892          */
5893         if (__test_and_set_bit(type_idx, found))
5894                 return -EEXIST;
5895
5896         part->nvram_type = type;
5897
5898         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5899         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5900                           outbuf, sizeof(outbuf), &outlen);
5901         if (rc)
5902                 return rc;
5903         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5904                 return -EIO;
5905         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5906             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5907                 part->fw_subtype = MCDI_DWORD(outbuf,
5908                                               NVRAM_METADATA_OUT_SUBTYPE);
5909
5910         part->common.dev_type_name = "EF10 NVRAM manager";
5911         part->common.type_name = info->name;
5912
5913         part->common.mtd.type = MTD_NORFLASH;
5914         part->common.mtd.flags = MTD_CAP_NORFLASH;
5915         part->common.mtd.size = size;
5916         part->common.mtd.erasesize = erase_size;
5917
5918         return 0;
5919 }
5920
5921 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5922 {
5923         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5924         DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
5925         struct efx_mcdi_mtd_partition *parts;
5926         size_t outlen, n_parts_total, i, n_parts;
5927         unsigned int type;
5928         int rc;
5929
5930         ASSERT_RTNL();
5931
5932         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5933         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5934                           outbuf, sizeof(outbuf), &outlen);
5935         if (rc)
5936                 return rc;
5937         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5938                 return -EIO;
5939
5940         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5941         if (n_parts_total >
5942             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5943                 return -EIO;
5944
5945         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5946         if (!parts)
5947                 return -ENOMEM;
5948
5949         n_parts = 0;
5950         for (i = 0; i < n_parts_total; i++) {
5951                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5952                                         i);
5953                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
5954                                                   found);
5955                 if (rc == -EEXIST || rc == -ENODEV)
5956                         continue;
5957                 if (rc)
5958                         goto fail;
5959                 n_parts++;
5960         }
5961
5962         if (!n_parts) {
5963                 kfree(parts);
5964                 return 0;
5965         }
5966
5967         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5968 fail:
5969         if (rc)
5970                 kfree(parts);
5971         return rc;
5972 }
5973
5974 #endif /* CONFIG_SFC_MTD */
5975
5976 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5977 {
5978         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5979 }
5980
5981 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5982                                             u32 host_time) {}
5983
5984 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5985                                            bool temp)
5986 {
5987         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5988         int rc;
5989
5990         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5991             channel->sync_events_state == SYNC_EVENTS_VALID ||
5992             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5993                 return 0;
5994         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5995
5996         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5997         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5998         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5999                        channel->channel);
6000
6001         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6002                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6003
6004         if (rc != 0)
6005                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6006                                                     SYNC_EVENTS_DISABLED;
6007
6008         return rc;
6009 }
6010
6011 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6012                                             bool temp)
6013 {
6014         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6015         int rc;
6016
6017         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6018             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6019                 return 0;
6020         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6021                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6022                 return 0;
6023         }
6024         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6025                                             SYNC_EVENTS_DISABLED;
6026
6027         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6028         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6029         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6030                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6031         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6032                        channel->channel);
6033
6034         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6035                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6036
6037         return rc;
6038 }
6039
6040 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6041                                            bool temp)
6042 {
6043         int (*set)(struct efx_channel *channel, bool temp);
6044         struct efx_channel *channel;
6045
6046         set = en ?
6047               efx_ef10_rx_enable_timestamping :
6048               efx_ef10_rx_disable_timestamping;
6049
6050         efx_for_each_channel(channel, efx) {
6051                 int rc = set(channel, temp);
6052                 if (en && rc != 0) {
6053                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6054                         return rc;
6055                 }
6056         }
6057
6058         return 0;
6059 }
6060
6061 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6062                                          struct hwtstamp_config *init)
6063 {
6064         return -EOPNOTSUPP;
6065 }
6066
6067 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6068                                       struct hwtstamp_config *init)
6069 {
6070         int rc;
6071
6072         switch (init->rx_filter) {
6073         case HWTSTAMP_FILTER_NONE:
6074                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6075                 /* if TX timestamping is still requested then leave PTP on */
6076                 return efx_ptp_change_mode(efx,
6077                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
6078         case HWTSTAMP_FILTER_ALL:
6079         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6080         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6081         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6082         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6083         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6084         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6085         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6086         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6087         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6088         case HWTSTAMP_FILTER_PTP_V2_EVENT:
6089         case HWTSTAMP_FILTER_PTP_V2_SYNC:
6090         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6091         case HWTSTAMP_FILTER_NTP_ALL:
6092                 init->rx_filter = HWTSTAMP_FILTER_ALL;
6093                 rc = efx_ptp_change_mode(efx, true, 0);
6094                 if (!rc)
6095                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6096                 if (rc)
6097                         efx_ptp_change_mode(efx, false, 0);
6098                 return rc;
6099         default:
6100                 return -ERANGE;
6101         }
6102 }
6103
6104 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6105                                      struct netdev_phys_item_id *ppid)
6106 {
6107         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6108
6109         if (!is_valid_ether_addr(nic_data->port_id))
6110                 return -EOPNOTSUPP;
6111
6112         ppid->id_len = ETH_ALEN;
6113         memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6114
6115         return 0;
6116 }
6117
6118 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6119 {
6120         if (proto != htons(ETH_P_8021Q))
6121                 return -EINVAL;
6122
6123         return efx_ef10_add_vlan(efx, vid);
6124 }
6125
6126 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6127 {
6128         if (proto != htons(ETH_P_8021Q))
6129                 return -EINVAL;
6130
6131         return efx_ef10_del_vlan(efx, vid);
6132 }
6133
6134 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6135  * ports table, ensuring that any TSO descriptors that were made on a now-
6136  * removed tunnel port will be blown away and won't break things when we try
6137  * to transmit them using the new ports table.
6138  */
6139 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6140 {
6141         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6142         MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6143         MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6144         bool will_reset = false;
6145         size_t num_entries = 0;
6146         size_t inlen, outlen;
6147         size_t i;
6148         int rc;
6149         efx_dword_t flags_and_num_entries;
6150
6151         WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6152
6153         nic_data->udp_tunnels_dirty = false;
6154
6155         if (!(nic_data->datapath_caps &
6156             (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6157                 efx_device_attach_if_not_resetting(efx);
6158                 return 0;
6159         }
6160
6161         BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6162                      MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6163
6164         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6165                 if (nic_data->udp_tunnels[i].count &&
6166                     nic_data->udp_tunnels[i].port) {
6167                         efx_dword_t entry;
6168
6169                         EFX_POPULATE_DWORD_2(entry,
6170                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6171                                         ntohs(nic_data->udp_tunnels[i].port),
6172                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6173                                         nic_data->udp_tunnels[i].type);
6174                         *_MCDI_ARRAY_DWORD(inbuf,
6175                                 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6176                                 num_entries++) = entry;
6177                 }
6178         }
6179
6180         BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6181                       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6182                      EFX_WORD_1_LBN);
6183         BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6184                      EFX_WORD_1_WIDTH);
6185         EFX_POPULATE_DWORD_2(flags_and_num_entries,
6186                              MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6187                                 !!unloading,
6188                              EFX_WORD_1, num_entries);
6189         *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6190                 flags_and_num_entries;
6191
6192         inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6193
6194         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6195                                 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6196         if (rc == -EIO) {
6197                 /* Most likely the MC rebooted due to another function also
6198                  * setting its tunnel port list. Mark the tunnel port list as
6199                  * dirty, so it will be pushed upon coming up from the reboot.
6200                  */
6201                 nic_data->udp_tunnels_dirty = true;
6202                 return 0;
6203         }
6204
6205         if (rc) {
6206                 /* expected not available on unprivileged functions */
6207                 if (rc != -EPERM)
6208                         netif_warn(efx, drv, efx->net_dev,
6209                                    "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6210         } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6211                    (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6212                 netif_info(efx, drv, efx->net_dev,
6213                            "Rebooting MC due to UDP tunnel port list change\n");
6214                 will_reset = true;
6215                 if (unloading)
6216                         /* Delay for the MC reset to complete. This will make
6217                          * unloading other functions a bit smoother. This is a
6218                          * race, but the other unload will work whichever way
6219                          * it goes, this just avoids an unnecessary error
6220                          * message.
6221                          */
6222                         msleep(100);
6223         }
6224         if (!will_reset && !unloading) {
6225                 /* The caller will have detached, relying on the MC reset to
6226                  * trigger a re-attach.  Since there won't be an MC reset, we
6227                  * have to do the attach ourselves.
6228                  */
6229                 efx_device_attach_if_not_resetting(efx);
6230         }
6231
6232         return rc;
6233 }
6234
6235 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6236 {
6237         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6238         int rc = 0;
6239
6240         mutex_lock(&nic_data->udp_tunnels_lock);
6241         if (nic_data->udp_tunnels_dirty) {
6242                 /* Make sure all TX are stopped while we modify the table, else
6243                  * we might race against an efx_features_check().
6244                  */
6245                 efx_device_detach_sync(efx);
6246                 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6247         }
6248         mutex_unlock(&nic_data->udp_tunnels_lock);
6249         return rc;
6250 }
6251
6252 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6253                                                              __be16 port)
6254 {
6255         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6256         size_t i;
6257
6258         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6259                 if (!nic_data->udp_tunnels[i].count)
6260                         continue;
6261                 if (nic_data->udp_tunnels[i].port == port)
6262                         return &nic_data->udp_tunnels[i];
6263         }
6264         return NULL;
6265 }
6266
6267 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6268                                      struct efx_udp_tunnel tnl)
6269 {
6270         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6271         struct efx_udp_tunnel *match;
6272         char typebuf[8];
6273         size_t i;
6274         int rc;
6275
6276         if (!(nic_data->datapath_caps &
6277               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6278                 return 0;
6279
6280         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6281         netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6282                   typebuf, ntohs(tnl.port));
6283
6284         mutex_lock(&nic_data->udp_tunnels_lock);
6285         /* Make sure all TX are stopped while we add to the table, else we
6286          * might race against an efx_features_check().
6287          */
6288         efx_device_detach_sync(efx);
6289
6290         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6291         if (match != NULL) {
6292                 if (match->type == tnl.type) {
6293                         netif_dbg(efx, drv, efx->net_dev,
6294                                   "Referencing existing tunnel entry\n");
6295                         match->count++;
6296                         /* No need to cause an MCDI update */
6297                         rc = 0;
6298                         goto unlock_out;
6299                 }
6300                 efx_get_udp_tunnel_type_name(match->type,
6301                                              typebuf, sizeof(typebuf));
6302                 netif_dbg(efx, drv, efx->net_dev,
6303                           "UDP port %d is already in use by %s\n",
6304                           ntohs(tnl.port), typebuf);
6305                 rc = -EEXIST;
6306                 goto unlock_out;
6307         }
6308
6309         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6310                 if (!nic_data->udp_tunnels[i].count) {
6311                         nic_data->udp_tunnels[i] = tnl;
6312                         nic_data->udp_tunnels[i].count = 1;
6313                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6314                         goto unlock_out;
6315                 }
6316
6317         netif_dbg(efx, drv, efx->net_dev,
6318                   "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6319                   typebuf, ntohs(tnl.port));
6320
6321         rc = -ENOMEM;
6322
6323 unlock_out:
6324         mutex_unlock(&nic_data->udp_tunnels_lock);
6325         return rc;
6326 }
6327
6328 /* Called under the TX lock with the TX queue running, hence no-one can be
6329  * in the middle of updating the UDP tunnels table.  However, they could
6330  * have tried and failed the MCDI, in which case they'll have set the dirty
6331  * flag before dropping their locks.
6332  */
6333 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6334 {
6335         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6336
6337         if (!(nic_data->datapath_caps &
6338               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6339                 return false;
6340
6341         if (nic_data->udp_tunnels_dirty)
6342                 /* SW table may not match HW state, so just assume we can't
6343                  * use any UDP tunnel offloads.
6344                  */
6345                 return false;
6346
6347         return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6348 }
6349
6350 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6351                                      struct efx_udp_tunnel tnl)
6352 {
6353         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6354         struct efx_udp_tunnel *match;
6355         char typebuf[8];
6356         int rc;
6357
6358         if (!(nic_data->datapath_caps &
6359               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6360                 return 0;
6361
6362         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6363         netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6364                   typebuf, ntohs(tnl.port));
6365
6366         mutex_lock(&nic_data->udp_tunnels_lock);
6367         /* Make sure all TX are stopped while we remove from the table, else we
6368          * might race against an efx_features_check().
6369          */
6370         efx_device_detach_sync(efx);
6371
6372         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6373         if (match != NULL) {
6374                 if (match->type == tnl.type) {
6375                         if (--match->count) {
6376                                 /* Port is still in use, so nothing to do */
6377                                 netif_dbg(efx, drv, efx->net_dev,
6378                                           "UDP tunnel port %d remains active\n",
6379                                           ntohs(tnl.port));
6380                                 rc = 0;
6381                                 goto out_unlock;
6382                         }
6383                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6384                         goto out_unlock;
6385                 }
6386                 efx_get_udp_tunnel_type_name(match->type,
6387                                              typebuf, sizeof(typebuf));
6388                 netif_warn(efx, drv, efx->net_dev,
6389                            "UDP port %d is actually in use by %s, not removing\n",
6390                            ntohs(tnl.port), typebuf);
6391         }
6392         rc = -ENOENT;
6393
6394 out_unlock:
6395         mutex_unlock(&nic_data->udp_tunnels_lock);
6396         return rc;
6397 }
6398
6399 #define EF10_OFFLOAD_FEATURES           \
6400         (NETIF_F_IP_CSUM |              \
6401          NETIF_F_HW_VLAN_CTAG_FILTER |  \
6402          NETIF_F_IPV6_CSUM |            \
6403          NETIF_F_RXHASH |               \
6404          NETIF_F_NTUPLE)
6405
6406 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6407         .is_vf = true,
6408         .mem_bar = EFX_MEM_VF_BAR,
6409         .mem_map_size = efx_ef10_mem_map_size,
6410         .probe = efx_ef10_probe_vf,
6411         .remove = efx_ef10_remove,
6412         .dimension_resources = efx_ef10_dimension_resources,
6413         .init = efx_ef10_init_nic,
6414         .fini = efx_port_dummy_op_void,
6415         .map_reset_reason = efx_ef10_map_reset_reason,
6416         .map_reset_flags = efx_ef10_map_reset_flags,
6417         .reset = efx_ef10_reset,
6418         .probe_port = efx_mcdi_port_probe,
6419         .remove_port = efx_mcdi_port_remove,
6420         .fini_dmaq = efx_ef10_fini_dmaq,
6421         .prepare_flr = efx_ef10_prepare_flr,
6422         .finish_flr = efx_port_dummy_op_void,
6423         .describe_stats = efx_ef10_describe_stats,
6424         .update_stats = efx_ef10_update_stats_vf,
6425         .start_stats = efx_port_dummy_op_void,
6426         .pull_stats = efx_port_dummy_op_void,
6427         .stop_stats = efx_port_dummy_op_void,
6428         .set_id_led = efx_mcdi_set_id_led,
6429         .push_irq_moderation = efx_ef10_push_irq_moderation,
6430         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6431         .check_mac_fault = efx_mcdi_mac_check_fault,
6432         .reconfigure_port = efx_mcdi_port_reconfigure,
6433         .get_wol = efx_ef10_get_wol_vf,
6434         .set_wol = efx_ef10_set_wol_vf,
6435         .resume_wol = efx_port_dummy_op_void,
6436         .mcdi_request = efx_ef10_mcdi_request,
6437         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6438         .mcdi_read_response = efx_ef10_mcdi_read_response,
6439         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6440         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6441         .irq_enable_master = efx_port_dummy_op_void,
6442         .irq_test_generate = efx_ef10_irq_test_generate,
6443         .irq_disable_non_ev = efx_port_dummy_op_void,
6444         .irq_handle_msi = efx_ef10_msi_interrupt,
6445         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6446         .tx_probe = efx_ef10_tx_probe,
6447         .tx_init = efx_ef10_tx_init,
6448         .tx_remove = efx_ef10_tx_remove,
6449         .tx_write = efx_ef10_tx_write,
6450         .tx_limit_len = efx_ef10_tx_limit_len,
6451         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6452         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6453         .rx_probe = efx_ef10_rx_probe,
6454         .rx_init = efx_ef10_rx_init,
6455         .rx_remove = efx_ef10_rx_remove,
6456         .rx_write = efx_ef10_rx_write,
6457         .rx_defer_refill = efx_ef10_rx_defer_refill,
6458         .ev_probe = efx_ef10_ev_probe,
6459         .ev_init = efx_ef10_ev_init,
6460         .ev_fini = efx_ef10_ev_fini,
6461         .ev_remove = efx_ef10_ev_remove,
6462         .ev_process = efx_ef10_ev_process,
6463         .ev_read_ack = efx_ef10_ev_read_ack,
6464         .ev_test_generate = efx_ef10_ev_test_generate,
6465         .filter_table_probe = efx_ef10_filter_table_probe,
6466         .filter_table_restore = efx_ef10_filter_table_restore,
6467         .filter_table_remove = efx_ef10_filter_table_remove,
6468         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6469         .filter_insert = efx_ef10_filter_insert,
6470         .filter_remove_safe = efx_ef10_filter_remove_safe,
6471         .filter_get_safe = efx_ef10_filter_get_safe,
6472         .filter_clear_rx = efx_ef10_filter_clear_rx,
6473         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6474         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6475         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6476 #ifdef CONFIG_RFS_ACCEL
6477         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6478         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6479 #endif
6480 #ifdef CONFIG_SFC_MTD
6481         .mtd_probe = efx_port_dummy_op_int,
6482 #endif
6483         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6484         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6485         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6486         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6487 #ifdef CONFIG_SFC_SRIOV
6488         .vswitching_probe = efx_ef10_vswitching_probe_vf,
6489         .vswitching_restore = efx_ef10_vswitching_restore_vf,
6490         .vswitching_remove = efx_ef10_vswitching_remove_vf,
6491 #endif
6492         .get_mac_address = efx_ef10_get_mac_address_vf,
6493         .set_mac_address = efx_ef10_set_mac_address,
6494
6495         .get_phys_port_id = efx_ef10_get_phys_port_id,
6496         .revision = EFX_REV_HUNT_A0,
6497         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6498         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6499         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6500         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6501         .can_rx_scatter = true,
6502         .always_rx_scatter = true,
6503         .min_interrupt_mode = EFX_INT_MODE_MSIX,
6504         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6505         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6506         .offload_features = EF10_OFFLOAD_FEATURES,
6507         .mcdi_max_ver = 2,
6508         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6509         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6510                             1 << HWTSTAMP_FILTER_ALL,
6511         .rx_hash_key_size = 40,
6512 };
6513
6514 const struct efx_nic_type efx_hunt_a0_nic_type = {
6515         .is_vf = false,
6516         .mem_bar = EFX_MEM_BAR,
6517         .mem_map_size = efx_ef10_mem_map_size,
6518         .probe = efx_ef10_probe_pf,
6519         .remove = efx_ef10_remove,
6520         .dimension_resources = efx_ef10_dimension_resources,
6521         .init = efx_ef10_init_nic,
6522         .fini = efx_port_dummy_op_void,
6523         .map_reset_reason = efx_ef10_map_reset_reason,
6524         .map_reset_flags = efx_ef10_map_reset_flags,
6525         .reset = efx_ef10_reset,
6526         .probe_port = efx_mcdi_port_probe,
6527         .remove_port = efx_mcdi_port_remove,
6528         .fini_dmaq = efx_ef10_fini_dmaq,
6529         .prepare_flr = efx_ef10_prepare_flr,
6530         .finish_flr = efx_port_dummy_op_void,
6531         .describe_stats = efx_ef10_describe_stats,
6532         .update_stats = efx_ef10_update_stats_pf,
6533         .start_stats = efx_mcdi_mac_start_stats,
6534         .pull_stats = efx_mcdi_mac_pull_stats,
6535         .stop_stats = efx_mcdi_mac_stop_stats,
6536         .set_id_led = efx_mcdi_set_id_led,
6537         .push_irq_moderation = efx_ef10_push_irq_moderation,
6538         .reconfigure_mac = efx_ef10_mac_reconfigure,
6539         .check_mac_fault = efx_mcdi_mac_check_fault,
6540         .reconfigure_port = efx_mcdi_port_reconfigure,
6541         .get_wol = efx_ef10_get_wol,
6542         .set_wol = efx_ef10_set_wol,
6543         .resume_wol = efx_port_dummy_op_void,
6544         .test_chip = efx_ef10_test_chip,
6545         .test_nvram = efx_mcdi_nvram_test_all,
6546         .mcdi_request = efx_ef10_mcdi_request,
6547         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6548         .mcdi_read_response = efx_ef10_mcdi_read_response,
6549         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6550         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6551         .irq_enable_master = efx_port_dummy_op_void,
6552         .irq_test_generate = efx_ef10_irq_test_generate,
6553         .irq_disable_non_ev = efx_port_dummy_op_void,
6554         .irq_handle_msi = efx_ef10_msi_interrupt,
6555         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6556         .tx_probe = efx_ef10_tx_probe,
6557         .tx_init = efx_ef10_tx_init,
6558         .tx_remove = efx_ef10_tx_remove,
6559         .tx_write = efx_ef10_tx_write,
6560         .tx_limit_len = efx_ef10_tx_limit_len,
6561         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6562         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6563         .rx_probe = efx_ef10_rx_probe,
6564         .rx_init = efx_ef10_rx_init,
6565         .rx_remove = efx_ef10_rx_remove,
6566         .rx_write = efx_ef10_rx_write,
6567         .rx_defer_refill = efx_ef10_rx_defer_refill,
6568         .ev_probe = efx_ef10_ev_probe,
6569         .ev_init = efx_ef10_ev_init,
6570         .ev_fini = efx_ef10_ev_fini,
6571         .ev_remove = efx_ef10_ev_remove,
6572         .ev_process = efx_ef10_ev_process,
6573         .ev_read_ack = efx_ef10_ev_read_ack,
6574         .ev_test_generate = efx_ef10_ev_test_generate,
6575         .filter_table_probe = efx_ef10_filter_table_probe,
6576         .filter_table_restore = efx_ef10_filter_table_restore,
6577         .filter_table_remove = efx_ef10_filter_table_remove,
6578         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6579         .filter_insert = efx_ef10_filter_insert,
6580         .filter_remove_safe = efx_ef10_filter_remove_safe,
6581         .filter_get_safe = efx_ef10_filter_get_safe,
6582         .filter_clear_rx = efx_ef10_filter_clear_rx,
6583         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6584         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6585         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6586 #ifdef CONFIG_RFS_ACCEL
6587         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6588         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6589 #endif
6590 #ifdef CONFIG_SFC_MTD
6591         .mtd_probe = efx_ef10_mtd_probe,
6592         .mtd_rename = efx_mcdi_mtd_rename,
6593         .mtd_read = efx_mcdi_mtd_read,
6594         .mtd_erase = efx_mcdi_mtd_erase,
6595         .mtd_write = efx_mcdi_mtd_write,
6596         .mtd_sync = efx_mcdi_mtd_sync,
6597 #endif
6598         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6599         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6600         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6601         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6602         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6603         .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6604         .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6605         .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6606         .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6607 #ifdef CONFIG_SFC_SRIOV
6608         .sriov_configure = efx_ef10_sriov_configure,
6609         .sriov_init = efx_ef10_sriov_init,
6610         .sriov_fini = efx_ef10_sriov_fini,
6611         .sriov_wanted = efx_ef10_sriov_wanted,
6612         .sriov_reset = efx_ef10_sriov_reset,
6613         .sriov_flr = efx_ef10_sriov_flr,
6614         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6615         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6616         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6617         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6618         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6619         .vswitching_probe = efx_ef10_vswitching_probe_pf,
6620         .vswitching_restore = efx_ef10_vswitching_restore_pf,
6621         .vswitching_remove = efx_ef10_vswitching_remove_pf,
6622 #endif
6623         .get_mac_address = efx_ef10_get_mac_address_pf,
6624         .set_mac_address = efx_ef10_set_mac_address,
6625         .tso_versions = efx_ef10_tso_versions,
6626
6627         .get_phys_port_id = efx_ef10_get_phys_port_id,
6628         .revision = EFX_REV_HUNT_A0,
6629         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6630         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6631         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6632         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6633         .can_rx_scatter = true,
6634         .always_rx_scatter = true,
6635         .option_descriptors = true,
6636         .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6637         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6638         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6639         .offload_features = EF10_OFFLOAD_FEATURES,
6640         .mcdi_max_ver = 2,
6641         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6642         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6643                             1 << HWTSTAMP_FILTER_ALL,
6644         .rx_hash_key_size = 40,
6645 };