drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31 /* The maximum size of a shared RSS context */
  32 /* TODO: this should really be from the mcdi protocol export */
  33 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  34
  35 /* The filter table(s) are managed by firmware and we have write-only
  36  * access.  When removing filters we must identify them to the
  37  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  38  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  39  * be able to tell in advance whether a requested insertion will
  40  * replace an existing filter.  Therefore we maintain a software hash
  41  * table, which should be at least as large as the hardware hash
  42  * table.
  43  *
  44  * Huntington has a single 8K filter table shared between all filter
  45  * types and both ports.
  46  */
  47 #define HUNT_FILTER_TBL_ROWS 8192
  48
  49 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  50
  51 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  52 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  53
  54 /* VLAN list entry */
  55 struct efx_ef10_vlan {
  56         struct list_head list;
  57         u16 vid;
  58 };
  59
  60 enum efx_ef10_default_filters {
  61         EFX_EF10_BCAST,
  62         EFX_EF10_UCDEF,
  63         EFX_EF10_MCDEF,
  64         EFX_EF10_VXLAN4_UCDEF,
  65         EFX_EF10_VXLAN4_MCDEF,
  66         EFX_EF10_VXLAN6_UCDEF,
  67         EFX_EF10_VXLAN6_MCDEF,
  68         EFX_EF10_NVGRE4_UCDEF,
  69         EFX_EF10_NVGRE4_MCDEF,
  70         EFX_EF10_NVGRE6_UCDEF,
  71         EFX_EF10_NVGRE6_MCDEF,
  72         EFX_EF10_GENEVE4_UCDEF,
  73         EFX_EF10_GENEVE4_MCDEF,
  74         EFX_EF10_GENEVE6_UCDEF,
  75         EFX_EF10_GENEVE6_MCDEF,
  76
  77         EFX_EF10_NUM_DEFAULT_FILTERS
  78 };
  79
  80 /* Per-VLAN filters information */
  81 struct efx_ef10_filter_vlan {
  82         struct list_head list;
  83         u16 vid;
  84         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  85         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  86         u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
  87 };
  88
  89 struct efx_ef10_dev_addr {
  90         u8 addr[ETH_ALEN];
  91 };
  92
  93 struct efx_ef10_filter_table {
  94 /* The MCDI match masks supported by this fw & hw, in order of priority */
  95         u32 rx_match_mcdi_flags[
  96                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
  97         unsigned int rx_match_count;
  98
  99         struct rw_semaphore lock; /* Protects entries */
 100         struct {
 101                 unsigned long spec;     /* pointer to spec plus flag bits */
 102 /* AUTO_OLD is used to mark and sweep MAC filters for the device address lists. */
 103 /* unused flag  1UL */
 104 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
 105 #define EFX_EF10_FILTER_FLAGS           3UL
 106                 u64 handle;             /* firmware handle */
 107         } *entry;
 108 /* Shadow of net_device address lists, guarded by mac_lock */
 109         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
 110         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
 111         int dev_uc_count;
 112         int dev_mc_count;
 113         bool uc_promisc;
 114         bool mc_promisc;
 115 /* Whether in multicast promiscuous mode when last changed */
 116         bool mc_promisc_last;
 117         bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
 118         bool vlan_filter;
 119         struct list_head vlan_list;
 120 };
 121
 122 /* An arbitrary search limit for the software hash table */
 123 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 124
 125 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 126 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 127 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 128 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 129                                               struct efx_ef10_filter_vlan *vlan);
 130 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 131 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
 132
 133 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
 134 {
 135         WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
 136         return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
 137 }
 138
 139 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
 140 {
 141         return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
 142 }
 143
 144 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
 145 {
 146         return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
 147 }
 148
 149 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 150 {
 151         efx_dword_t reg;
 152
 153         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 154         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 155                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 156 }
 157
 158 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
 159  * I/O space and BAR 2(&3) for memory.  On SFC9250 (Medford2), there is no I/O
 160  * bar; PFs use BAR 0/1 for memory.
 161  */
 162 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
 163 {
 164         switch (efx->pci_dev->device) {
 165         case 0x0b03: /* SFC9250 PF */
 166                 return 0;
 167         default:
 168                 return 2;
 169         }
 170 }
 171
 172 /* All VFs use BAR 0/1 for memory */
 173 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
 174 {
 175         return 0;
 176 }
 177
 178 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 179 {
 180         int bar;
 181
 182         bar = efx->type->mem_bar(efx);
 183         return resource_size(&efx->pci_dev->resource[bar]);
 184 }
 185
 186 static bool efx_ef10_is_vf(struct efx_nic *efx)
 187 {
 188         return efx->type->is_vf;
 189 }
 190
 191 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 192 {
 193         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 194         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 195         size_t outlen;
 196         int rc;
 197
 198         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 199                           sizeof(outbuf), &outlen);
 200         if (rc)
 201                 return rc;
 202         if (outlen < sizeof(outbuf))
 203                 return -EIO;
 204
 205         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 206         return 0;
 207 }
 208
 209 #ifdef CONFIG_SFC_SRIOV
 210 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 211 {
 212         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 213         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 214         size_t outlen;
 215         int rc;
 216
 217         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 218                           sizeof(outbuf), &outlen);
 219         if (rc)
 220                 return rc;
 221         if (outlen < sizeof(outbuf))
 222                 return -EIO;
 223
 224         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 225         return 0;
 226 }
 227 #endif
 228
 229 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 230 {
 231         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
 232         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 233         size_t outlen;
 234         int rc;
 235
 236         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 237
 238         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 239                           outbuf, sizeof(outbuf), &outlen);
 240         if (rc)
 241                 return rc;
 242         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 243                 netif_err(efx, drv, efx->net_dev,
 244                           "unable to read datapath firmware capabilities\n");
 245                 return -EIO;
 246         }
 247
 248         nic_data->datapath_caps =
 249                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 250
 251         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 252                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 253                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 254                 nic_data->piobuf_size = MCDI_WORD(outbuf,
 255                                 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
 256         } else {
 257                 nic_data->datapath_caps2 = 0;
 258                 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
 259         }
 260
 261         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 262          */
 263         nic_data->rx_dpcpu_fw_id =
 264                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 265         nic_data->tx_dpcpu_fw_id =
 266                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 267
 268         if (!(nic_data->datapath_caps &
 269               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 270                 netif_err(efx, probe, efx->net_dev,
 271                           "current firmware does not support an RX prefix\n");
 272                 return -ENODEV;
 273         }
 274
 275         if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
 276                 u8 vi_window_mode = MCDI_BYTE(outbuf,
 277                                 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
 278
 279                 switch (vi_window_mode) {
 280                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
 281                         efx->vi_stride = 8192;
 282                         break;
 283                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
 284                         efx->vi_stride = 16384;
 285                         break;
 286                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
 287                         efx->vi_stride = 65536;
 288                         break;
 289                 default:
 290                         netif_err(efx, probe, efx->net_dev,
 291                                   "Unrecognised VI window mode %d\n",
 292                                   vi_window_mode);
 293                         return -EIO;
 294                 }
 295                 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
 296                           efx->vi_stride);
 297         } else {
 298                 /* keep default VI stride */
 299                 netif_dbg(efx, probe, efx->net_dev,
 300                           "firmware did not report VI window mode, assuming vi_stride = %u\n",
 301                           efx->vi_stride);
 302         }
 303
 304         if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
 305                 efx->num_mac_stats = MCDI_WORD(outbuf,
 306                                 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
 307                 netif_dbg(efx, probe, efx->net_dev,
 308                           "firmware reports num_mac_stats = %u\n",
 309                           efx->num_mac_stats);
 310         } else {
 311                 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
 312                 netif_dbg(efx, probe, efx->net_dev,
 313                           "firmware did not report num_mac_stats, assuming %u\n",
 314                           efx->num_mac_stats);
 315         }
 316
 317         return 0;
 318 }
 319
 320 static void efx_ef10_read_licensed_features(struct efx_nic *efx)
 321 {
 322         MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
 323         MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
 324         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 325         size_t outlen;
 326         int rc;
 327
 328         MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
 329                        MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
 330         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
 331                                 outbuf, sizeof(outbuf), &outlen);
 332         if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
 333                 return;
 334
 335         nic_data->licensed_features = MCDI_QWORD(outbuf,
 336                                          LICENSING_V3_OUT_LICENSED_FEATURES);
 337 }
 338
 339 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 340 {
 341         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 342         int rc;
 343
 344         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 345                           outbuf, sizeof(outbuf), NULL);
 346         if (rc)
 347                 return rc;
 348         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 349         return rc > 0 ? rc : -ERANGE;
 350 }
 351
 352 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 353 {
 354         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 355         unsigned int implemented;
 356         unsigned int enabled;
 357         int rc;
 358
 359         nic_data->workaround_35388 = false;
 360         nic_data->workaround_61265 = false;
 361
 362         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 363
 364         if (rc == -ENOSYS) {
 365                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 366                 rc = 0;
 367         } else if (rc == 0) {
 368                 /* Bug61265 workaround is always enabled if implemented. */
 369                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 370                         nic_data->workaround_61265 = true;
 371
 372                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 373                         nic_data->workaround_35388 = true;
 374                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 375                         /* Workaround is implemented but not enabled.
 376                          * Try to enable it.
 377                          */
 378                         rc = efx_mcdi_set_workaround(efx,
 379                                                      MC_CMD_WORKAROUND_BUG35388,
 380                                                      true, NULL);
 381                         if (rc == 0)
 382                                 nic_data->workaround_35388 = true;
 383                         /* If we failed to set the workaround just carry on. */
 384                         rc = 0;
 385                 }
 386         }
 387
 388         netif_dbg(efx, probe, efx->net_dev,
 389                   "workaround for bug 35388 is %sabled\n",
 390                   nic_data->workaround_35388 ? "en" : "dis");
 391         netif_dbg(efx, probe, efx->net_dev,
 392                   "workaround for bug 61265 is %sabled\n",
 393                   nic_data->workaround_61265 ? "en" : "dis");
 394
 395         return rc;
 396 }
 397
 398 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 399                                           const efx_dword_t *data)
 400 {
 401         unsigned int max_count;
 402
 403         if (EFX_EF10_WORKAROUND_61265(efx)) {
 404                 efx->timer_quantum_ns = MCDI_DWORD(data,
 405                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 406                 efx->timer_max_ns = MCDI_DWORD(data,
 407                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 408         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 409                 efx->timer_quantum_ns = MCDI_DWORD(data,
 410                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 411                 max_count = MCDI_DWORD(data,
 412                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 413                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 414         } else {
 415                 efx->timer_quantum_ns = MCDI_DWORD(data,
 416                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 417                 max_count = MCDI_DWORD(data,
 418                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 419                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 420         }
 421
 422         netif_dbg(efx, probe, efx->net_dev,
 423                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 424                   efx->timer_quantum_ns, efx->timer_max_ns);
 425 }
 426
 427 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 428 {
 429         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 430         int rc;
 431
 432         rc = efx_ef10_get_timer_workarounds(efx);
 433         if (rc)
 434                 return rc;
 435
 436         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 437                                 outbuf, sizeof(outbuf), NULL);
 438
 439         if (rc == 0) {
 440                 efx_ef10_process_timer_config(efx, outbuf);
 441         } else if (rc == -ENOSYS || rc == -EPERM) {
 442                 /* Not available - fall back to Huntington defaults. */
 443                 unsigned int quantum;
 444
 445                 rc = efx_ef10_get_sysclk_freq(efx);
 446                 if (rc < 0)
 447                         return rc;
 448
 449                 quantum = 1536000 / rc; /* 1536 cycles */
 450                 efx->timer_quantum_ns = quantum;
 451                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 452                 rc = 0;
 453         } else {
 454                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 455                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 456                                        NULL, 0, rc);
 457         }
 458
 459         return rc;
 460 }
 461
 462 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 463 {
 464         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 465         size_t outlen;
 466         int rc;
 467
 468         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 469
 470         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 471                           outbuf, sizeof(outbuf), &outlen);
 472         if (rc)
 473                 return rc;
 474         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 475                 return -EIO;
 476
 477         ether_addr_copy(mac_address,
 478                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 479         return 0;
 480 }
 481
 482 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 483 {
 484         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 485         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 486         size_t outlen;
 487         int num_addrs, rc;
 488
 489         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 490                        EVB_PORT_ID_ASSIGNED);
 491         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 492                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 493
 494         if (rc)
 495                 return rc;
 496         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 497                 return -EIO;
 498
 499         num_addrs = MCDI_DWORD(outbuf,
 500                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 501
 502         WARN_ON(num_addrs != 1);
 503
 504         ether_addr_copy(mac_address,
 505                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 506
 507         return 0;
 508 }
 509
 510 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 511                                                struct device_attribute *attr,
 512                                                char *buf)
 513 {
 514         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 515
 516         return sprintf(buf, "%d\n",
 517                        ((efx->mcdi->fn_flags) &
 518                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 519                        ? 1 : 0);
 520 }
 521
 522 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 523                                           struct device_attribute *attr,
 524                                           char *buf)
 525 {
 526         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 527
 528         return sprintf(buf, "%d\n",
 529                        ((efx->mcdi->fn_flags) &
 530                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 531                        ? 1 : 0);
 532 }
 533
 534 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 535 {
 536         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 537         struct efx_ef10_vlan *vlan;
 538
 539         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 540
 541         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 542                 if (vlan->vid == vid)
 543                         return vlan;
 544         }
 545
 546         return NULL;
 547 }
 548
 549 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 550 {
 551         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 552         struct efx_ef10_vlan *vlan;
 553         int rc;
 554
 555         mutex_lock(&nic_data->vlan_lock);
 556
 557         vlan = efx_ef10_find_vlan(efx, vid);
 558         if (vlan) {
 559                 /* We add VID 0 on init. 8021q adds it on module init
 560                  * for all interfaces with VLAN filtring feature.
 561                  */
 562                 if (vid == 0)
 563                         goto done_unlock;
 564                 netif_warn(efx, drv, efx->net_dev,
 565                            "VLAN %u already added\n", vid);
 566                 rc = -EALREADY;
 567                 goto fail_exist;
 568         }
 569
 570         rc = -ENOMEM;
 571         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 572         if (!vlan)
 573                 goto fail_alloc;
 574
 575         vlan->vid = vid;
 576
 577         list_add_tail(&vlan->list, &nic_data->vlan_list);
 578
 579         if (efx->filter_state) {
 580                 mutex_lock(&efx->mac_lock);
 581                 down_write(&efx->filter_sem);
 582                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 583                 up_write(&efx->filter_sem);
 584                 mutex_unlock(&efx->mac_lock);
 585                 if (rc)
 586                         goto fail_filter_add_vlan;
 587         }
 588
 589 done_unlock:
 590         mutex_unlock(&nic_data->vlan_lock);
 591         return 0;
 592
 593 fail_filter_add_vlan:
 594         list_del(&vlan->list);
 595         kfree(vlan);
 596 fail_alloc:
 597 fail_exist:
 598         mutex_unlock(&nic_data->vlan_lock);
 599         return rc;
 600 }
 601
 602 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 603                                        struct efx_ef10_vlan *vlan)
 604 {
 605         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 606
 607         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 608
 609         if (efx->filter_state) {
 610                 down_write(&efx->filter_sem);
 611                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 612                 up_write(&efx->filter_sem);
 613         }
 614
 615         list_del(&vlan->list);
 616         kfree(vlan);
 617 }
 618
 619 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 620 {
 621         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 622         struct efx_ef10_vlan *vlan;
 623         int rc = 0;
 624
 625         /* 8021q removes VID 0 on module unload for all interfaces
 626          * with VLAN filtering feature. We need to keep it to receive
 627          * untagged traffic.
 628          */
 629         if (vid == 0)
 630                 return 0;
 631
 632         mutex_lock(&nic_data->vlan_lock);
 633
 634         vlan = efx_ef10_find_vlan(efx, vid);
 635         if (!vlan) {
 636                 netif_err(efx, drv, efx->net_dev,
 637                           "VLAN %u to be deleted not found\n", vid);
 638                 rc = -ENOENT;
 639         } else {
 640                 efx_ef10_del_vlan_internal(efx, vlan);
 641         }
 642
 643         mutex_unlock(&nic_data->vlan_lock);
 644
 645         return rc;
 646 }
 647
 648 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 649 {
 650         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 651         struct efx_ef10_vlan *vlan, *next_vlan;
 652
 653         mutex_lock(&nic_data->vlan_lock);
 654         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 655                 efx_ef10_del_vlan_internal(efx, vlan);
 656         mutex_unlock(&nic_data->vlan_lock);
 657 }
 658
 659 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 660                    NULL);
 661 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 662
 663 static int efx_ef10_probe(struct efx_nic *efx)
 664 {
 665         struct efx_ef10_nic_data *nic_data;
 666         int i, rc;
 667
 668         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 669         if (!nic_data)
 670                 return -ENOMEM;
 671         efx->nic_data = nic_data;
 672
 673         /* we assume later that we can copy from this buffer in dwords */
 674         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 675
 676         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 677                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 678         if (rc)
 679                 goto fail1;
 680
 681         /* Get the MC's warm boot count.  In case it's rebooting right
 682          * now, be prepared to retry.
 683          */
 684         i = 0;
 685         for (;;) {
 686                 rc = efx_ef10_get_warm_boot_count(efx);
 687                 if (rc >= 0)
 688                         break;
 689                 if (++i == 5)
 690                         goto fail2;
 691                 ssleep(1);
 692         }
 693         nic_data->warm_boot_count = rc;
 694
 695         efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
 696
 697         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 698
 699         /* In case we're recovering from a crash (kexec), we want to
 700          * cancel any outstanding request by the previous user of this
 701          * function.  We send a special message using the least
 702          * significant bits of the 'high' (doorbell) register.
 703          */
 704         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 705
 706         rc = efx_mcdi_init(efx);
 707         if (rc)
 708                 goto fail2;
 709
 710         mutex_init(&nic_data->udp_tunnels_lock);
 711
 712         /* Reset (most) configuration for this function */
 713         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 714         if (rc)
 715                 goto fail3;
 716
 717         /* Enable event logging */
 718         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 719         if (rc)
 720                 goto fail3;
 721
 722         rc = device_create_file(&efx->pci_dev->dev,
 723                                 &dev_attr_link_control_flag);
 724         if (rc)
 725                 goto fail3;
 726
 727         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 728         if (rc)
 729                 goto fail4;
 730
 731         rc = efx_ef10_get_pf_index(efx);
 732         if (rc)
 733                 goto fail5;
 734
 735         rc = efx_ef10_init_datapath_caps(efx);
 736         if (rc < 0)
 737                 goto fail5;
 738
 739         efx_ef10_read_licensed_features(efx);
 740
 741         /* We can have one VI for each vi_stride-byte region.
 742          * However, until we use TX option descriptors we need two TX queues
 743          * per channel.
 744          */
 745         efx->max_channels = min_t(unsigned int,
 746                                   EFX_MAX_CHANNELS,
 747                                   efx_ef10_mem_map_size(efx) /
 748                                   (efx->vi_stride * EFX_TXQ_TYPES));
 749         efx->max_tx_channels = efx->max_channels;
 750         if (WARN_ON(efx->max_channels == 0)) {
 751                 rc = -EIO;
 752                 goto fail5;
 753         }
 754
 755         efx->rx_packet_len_offset =
 756                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 757
 758         if (nic_data->datapath_caps &
 759             (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
 760                 efx->net_dev->hw_features |= NETIF_F_RXFCS;
 761
 762         rc = efx_mcdi_port_get_number(efx);
 763         if (rc < 0)
 764                 goto fail5;
 765         efx->port_num = rc;
 766
 767         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 768         if (rc)
 769                 goto fail5;
 770
 771         rc = efx_ef10_get_timer_config(efx);
 772         if (rc < 0)
 773                 goto fail5;
 774
 775         rc = efx_mcdi_mon_probe(efx);
 776         if (rc && rc != -EPERM)
 777                 goto fail5;
 778
 779         efx_ptp_defer_probe_with_channel(efx);
 780
 781 #ifdef CONFIG_SFC_SRIOV
 782         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 783                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 784                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 785
 786                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 787         } else
 788 #endif
 789                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 790
 791         INIT_LIST_HEAD(&nic_data->vlan_list);
 792         mutex_init(&nic_data->vlan_lock);
 793
 794         /* Add unspecified VID to support VLAN filtering being disabled */
 795         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 796         if (rc)
 797                 goto fail_add_vid_unspec;
 798
 799         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 800          * traffic.  It is added automatically if 8021q module is loaded,
 801          * but we can't rely on it since module may be not loaded.
 802          */
 803         rc = efx_ef10_add_vlan(efx, 0);
 804         if (rc)
 805                 goto fail_add_vid_0;
 806
 807         return 0;
 808
 809 fail_add_vid_0:
 810         efx_ef10_cleanup_vlans(efx);
 811 fail_add_vid_unspec:
 812         mutex_destroy(&nic_data->vlan_lock);
 813         efx_ptp_remove(efx);
 814         efx_mcdi_mon_remove(efx);
 815 fail5:
 816         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 817 fail4:
 818         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 819 fail3:
 820         efx_mcdi_detach(efx);
 821
 822         mutex_lock(&nic_data->udp_tunnels_lock);
 823         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
 824         (void)efx_ef10_set_udp_tnl_ports(efx, true);
 825         mutex_unlock(&nic_data->udp_tunnels_lock);
 826         mutex_destroy(&nic_data->udp_tunnels_lock);
 827
 828         efx_mcdi_fini(efx);
 829 fail2:
 830         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 831 fail1:
 832         kfree(nic_data);
 833         efx->nic_data = NULL;
 834         return rc;
 835 }
 836
 837 static int efx_ef10_free_vis(struct efx_nic *efx)
 838 {
 839         MCDI_DECLARE_BUF_ERR(outbuf);
 840         size_t outlen;
 841         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 842                                     outbuf, sizeof(outbuf), &outlen);
 843
 844         /* -EALREADY means nothing to free, so ignore */
 845         if (rc == -EALREADY)
 846                 rc = 0;
 847         if (rc)
 848                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 849                                        rc);
 850         return rc;
 851 }
 852
 853 #ifdef EFX_USE_PIO
 854
 855 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 856 {
 857         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 858         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 859         unsigned int i;
 860         int rc;
 861
 862         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 863
 864         for (i = 0; i < nic_data->n_piobufs; i++) {
 865                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 866                                nic_data->piobuf_handle[i]);
 867                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 868                                   NULL, 0, NULL);
 869                 WARN_ON(rc);
 870         }
 871
 872         nic_data->n_piobufs = 0;
 873 }
 874
 875 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 876 {
 877         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 878         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 879         unsigned int i;
 880         size_t outlen;
 881         int rc = 0;
 882
 883         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 884
 885         for (i = 0; i < n; i++) {
 886                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 887                                         outbuf, sizeof(outbuf), &outlen);
 888                 if (rc) {
 889                         /* Don't display the MC error if we didn't have space
 890                          * for a VF.
 891                          */
 892                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 893                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 894                                                        0, outbuf, outlen, rc);
 895                         break;
 896                 }
 897                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 898                         rc = -EIO;
 899                         break;
 900                 }
 901                 nic_data->piobuf_handle[i] =
 902                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 903                 netif_dbg(efx, probe, efx->net_dev,
 904                           "allocated PIO buffer %u handle %x\n", i,
 905                           nic_data->piobuf_handle[i]);
 906         }
 907
 908         nic_data->n_piobufs = i;
 909         if (rc)
 910                 efx_ef10_free_piobufs(efx);
 911         return rc;
 912 }
 913
 914 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 915 {
 916         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 917         MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
 918         struct efx_channel *channel;
 919         struct efx_tx_queue *tx_queue;
 920         unsigned int offset, index;
 921         int rc;
 922
 923         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 924         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 925
 926         /* Link a buffer to each VI in the write-combining mapping */
 927         for (index = 0; index < nic_data->n_piobufs; ++index) {
 928                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 929                                nic_data->piobuf_handle[index]);
 930                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 931                                nic_data->pio_write_vi_base + index);
 932                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 933                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 934                                   NULL, 0, NULL);
 935                 if (rc) {
 936                         netif_err(efx, drv, efx->net_dev,
 937                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 938                                   nic_data->pio_write_vi_base + index, index,
 939                                   rc);
 940                         goto fail;
 941                 }
 942                 netif_dbg(efx, probe, efx->net_dev,
 943                           "linked VI %u to PIO buffer %u\n",
 944                           nic_data->pio_write_vi_base + index, index);
 945         }
 946
 947         /* Link a buffer to each TX queue */
 948         efx_for_each_channel(channel, efx) {
 949                 /* Extra channels, even those with TXQs (PTP), do not require
 950                  * PIO resources.
 951                  */
 952                 if (!channel->type->want_pio)
 953                         continue;
 954                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 955                         /* We assign the PIO buffers to queues in
 956                          * reverse order to allow for the following
 957                          * special case.
 958                          */
 959                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 960                                    tx_queue->channel->channel - 1) *
 961                                   efx_piobuf_size);
 962                         index = offset / nic_data->piobuf_size;
 963                         offset = offset % nic_data->piobuf_size;
 964
 965                         /* When the host page size is 4K, the first
 966                          * host page in the WC mapping may be within
 967                          * the same VI page as the last TX queue.  We
 968                          * can only link one buffer to each VI.
 969                          */
 970                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 971                                 BUG_ON(index != 0);
 972                                 rc = 0;
 973                         } else {
 974                                 MCDI_SET_DWORD(inbuf,
 975                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 976                                                nic_data->piobuf_handle[index]);
 977                                 MCDI_SET_DWORD(inbuf,
 978                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 979                                                tx_queue->queue);
 980                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 981                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 982                                                   NULL, 0, NULL);
 983                         }
 984
 985                         if (rc) {
 986                                 /* This is non-fatal; the TX path just
 987                                  * won't use PIO for this queue
 988                                  */
 989                                 netif_err(efx, drv, efx->net_dev,
 990                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 991                                           tx_queue->queue, index, rc);
 992                                 tx_queue->piobuf = NULL;
 993                         } else {
 994                                 tx_queue->piobuf =
 995                                         nic_data->pio_write_base +
 996                                         index * efx->vi_stride + offset;
 997                                 tx_queue->piobuf_offset = offset;
 998                                 netif_dbg(efx, probe, efx->net_dev,
 999                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
1000                                           tx_queue->queue, index,
1001                                           tx_queue->piobuf_offset,
1002                                           tx_queue->piobuf);
1003                         }
1004                 }
1005         }
1006
1007         return 0;
1008
1009 fail:
1010         /* inbuf was defined for MC_CMD_LINK_PIOBUF.  We can use the same
1011          * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
1012          */
1013         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
1014         while (index--) {
1015                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
1016                                nic_data->pio_write_vi_base + index);
1017                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
1018                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
1019                              NULL, 0, NULL);
1020         }
1021         return rc;
1022 }
1023
1024 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1025 {
1026         struct efx_channel *channel;
1027         struct efx_tx_queue *tx_queue;
1028
1029         /* All our existing PIO buffers went away */
1030         efx_for_each_channel(channel, efx)
1031                 efx_for_each_channel_tx_queue(tx_queue, channel)
1032                         tx_queue->piobuf = NULL;
1033 }
1034
1035 #else /* !EFX_USE_PIO */
1036
1037 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1038 {
1039         return n == 0 ? 0 : -ENOBUFS;
1040 }
1041
1042 static int efx_ef10_link_piobufs(struct efx_nic *efx)
1043 {
1044         return 0;
1045 }
1046
1047 static void efx_ef10_free_piobufs(struct efx_nic *efx)
1048 {
1049 }
1050
1051 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1052 {
1053 }
1054
1055 #endif /* EFX_USE_PIO */
1056
1057 static void efx_ef10_remove(struct efx_nic *efx)
1058 {
1059         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060         int rc;
1061
1062 #ifdef CONFIG_SFC_SRIOV
1063         struct efx_ef10_nic_data *nic_data_pf;
1064         struct pci_dev *pci_dev_pf;
1065         struct efx_nic *efx_pf;
1066         struct ef10_vf *vf;
1067
1068         if (efx->pci_dev->is_virtfn) {
1069                 pci_dev_pf = efx->pci_dev->physfn;
1070                 if (pci_dev_pf) {
1071                         efx_pf = pci_get_drvdata(pci_dev_pf);
1072                         nic_data_pf = efx_pf->nic_data;
1073                         vf = nic_data_pf->vf + nic_data->vf_index;
1074                         vf->efx = NULL;
1075                 } else
1076                         netif_info(efx, drv, efx->net_dev,
1077                                    "Could not get the PF id from VF\n");
1078         }
1079 #endif
1080
1081         efx_ef10_cleanup_vlans(efx);
1082         mutex_destroy(&nic_data->vlan_lock);
1083
1084         efx_ptp_remove(efx);
1085
1086         efx_mcdi_mon_remove(efx);
1087
1088         efx_ef10_rx_free_indir_table(efx);
1089
1090         if (nic_data->wc_membase)
1091                 iounmap(nic_data->wc_membase);
1092
1093         rc = efx_ef10_free_vis(efx);
1094         WARN_ON(rc != 0);
1095
1096         if (!nic_data->must_restore_piobufs)
1097                 efx_ef10_free_piobufs(efx);
1098
1099         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1100         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1101
1102         efx_mcdi_detach(efx);
1103
1104         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1105         mutex_lock(&nic_data->udp_tunnels_lock);
1106         (void)efx_ef10_set_udp_tnl_ports(efx, true);
1107         mutex_unlock(&nic_data->udp_tunnels_lock);
1108
1109         mutex_destroy(&nic_data->udp_tunnels_lock);
1110
1111         efx_mcdi_fini(efx);
1112         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1113         kfree(nic_data);
1114 }
1115
1116 static int efx_ef10_probe_pf(struct efx_nic *efx)
1117 {
1118         return efx_ef10_probe(efx);
1119 }
1120
1121 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1122                             u32 *port_flags, u32 *vadaptor_flags,
1123                             unsigned int *vlan_tags)
1124 {
1125         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1126         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1127         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1128         size_t outlen;
1129         int rc;
1130
1131         if (nic_data->datapath_caps &
1132             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1133                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1134                                port_id);
1135
1136                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1137                                   outbuf, sizeof(outbuf), &outlen);
1138                 if (rc)
1139                         return rc;
1140
1141                 if (outlen < sizeof(outbuf)) {
1142                         rc = -EIO;
1143                         return rc;
1144                 }
1145         }
1146
1147         if (port_flags)
1148                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1149         if (vadaptor_flags)
1150                 *vadaptor_flags =
1151                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1152         if (vlan_tags)
1153                 *vlan_tags =
1154                         MCDI_DWORD(outbuf,
1155                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1156
1157         return 0;
1158 }
1159
1160 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1161 {
1162         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1163
1164         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1165         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1166                             NULL, 0, NULL);
1167 }
1168
1169 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1170 {
1171         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1172
1173         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1174         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1175                             NULL, 0, NULL);
1176 }
1177
1178 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1179                            unsigned int port_id, u8 *mac)
1180 {
1181         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1182
1183         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1184         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1185
1186         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1187                             sizeof(inbuf), NULL, 0, NULL);
1188 }
1189
1190 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1191                            unsigned int port_id, u8 *mac)
1192 {
1193         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1194
1195         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1196         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1197
1198         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1199                             sizeof(inbuf), NULL, 0, NULL);
1200 }
1201
1202 #ifdef CONFIG_SFC_SRIOV
1203 static int efx_ef10_probe_vf(struct efx_nic *efx)
1204 {
1205         int rc;
1206         struct pci_dev *pci_dev_pf;
1207
1208         /* If the parent PF has no VF data structure, it doesn't know about this
1209          * VF so fail probe.  The VF needs to be re-created.  This can happen
1210          * if the PF driver is unloaded while the VF is assigned to a guest.
1211          */
1212         pci_dev_pf = efx->pci_dev->physfn;
1213         if (pci_dev_pf) {
1214                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1215                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1216
1217                 if (!nic_data_pf->vf) {
1218                         netif_info(efx, drv, efx->net_dev,
1219                                    "The VF cannot link to its parent PF; "
1220                                    "please destroy and re-create the VF\n");
1221                         return -EBUSY;
1222                 }
1223         }
1224
1225         rc = efx_ef10_probe(efx);
1226         if (rc)
1227                 return rc;
1228
1229         rc = efx_ef10_get_vf_index(efx);
1230         if (rc)
1231                 goto fail;
1232
1233         if (efx->pci_dev->is_virtfn) {
1234                 if (efx->pci_dev->physfn) {
1235                         struct efx_nic *efx_pf =
1236                                 pci_get_drvdata(efx->pci_dev->physfn);
1237                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1238                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1239
1240                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1241                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1242                                 efx->pci_dev;
1243                 } else
1244                         netif_info(efx, drv, efx->net_dev,
1245                                    "Could not get the PF id from VF\n");
1246         }
1247
1248         return 0;
1249
1250 fail:
1251         efx_ef10_remove(efx);
1252         return rc;
1253 }
1254 #else
1255 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1256 {
1257         return 0;
1258 }
1259 #endif
1260
1261 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1262                               unsigned int min_vis, unsigned int max_vis)
1263 {
1264         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1265         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1266         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1267         size_t outlen;
1268         int rc;
1269
1270         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1271         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1272         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1273                           outbuf, sizeof(outbuf), &outlen);
1274         if (rc != 0)
1275                 return rc;
1276
1277         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1278                 return -EIO;
1279
1280         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1281                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1282
1283         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1284         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1285         return 0;
1286 }
1287
1288 /* Note that the failure path of this function does not free
1289  * resources, as this will be done by efx_ef10_remove().
1290  */
1291 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1292 {
1293         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1294         unsigned int uc_mem_map_size, wc_mem_map_size;
1295         unsigned int min_vis = max(EFX_TXQ_TYPES,
1296                                    efx_separate_tx_channels ? 2 : 1);
1297         unsigned int channel_vis, pio_write_vi_base, max_vis;
1298         void __iomem *membase;
1299         int rc;
1300
1301         channel_vis = max(efx->n_channels,
1302                           (efx->n_tx_channels + efx->n_extra_tx_channels) *
1303                           EFX_TXQ_TYPES);
1304
1305 #ifdef EFX_USE_PIO
1306         /* Try to allocate PIO buffers if wanted and if the full
1307          * number of PIO buffers would be sufficient to allocate one
1308          * copy-buffer per TX channel.  Failure is non-fatal, as there
1309          * are only a small number of PIO buffers shared between all
1310          * functions of the controller.
1311          */
1312         if (efx_piobuf_size != 0 &&
1313             nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1314             efx->n_tx_channels) {
1315                 unsigned int n_piobufs =
1316                         DIV_ROUND_UP(efx->n_tx_channels,
1317                                      nic_data->piobuf_size / efx_piobuf_size);
1318
1319                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1320                 if (rc == -ENOSPC)
1321                         netif_dbg(efx, probe, efx->net_dev,
1322                                   "out of PIO buffers; cannot allocate more\n");
1323                 else if (rc == -EPERM)
1324                         netif_dbg(efx, probe, efx->net_dev,
1325                                   "not permitted to allocate PIO buffers\n");
1326                 else if (rc)
1327                         netif_err(efx, probe, efx->net_dev,
1328                                   "failed to allocate PIO buffers (%d)\n", rc);
1329                 else
1330                         netif_dbg(efx, probe, efx->net_dev,
1331                                   "allocated %u PIO buffers\n", n_piobufs);
1332         }
1333 #else
1334         nic_data->n_piobufs = 0;
1335 #endif
1336
1337         /* PIO buffers should be mapped with write-combining enabled,
1338          * and we want to make single UC and WC mappings rather than
1339          * several of each (in fact that's the only option if host
1340          * page size is >4K).  So we may allocate some extra VIs just
1341          * for writing PIO buffers through.
1342          *
1343          * The UC mapping contains (channel_vis - 1) complete VIs and the
1344          * first 4K of the next VI.  Then the WC mapping begins with
1345          * the remainder of this last VI.
1346          */
1347         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1348                                      ER_DZ_TX_PIOBUF);
1349         if (nic_data->n_piobufs) {
1350                 /* pio_write_vi_base rounds down to give the number of complete
1351                  * VIs inside the UC mapping.
1352                  */
1353                 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1354                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1355                                                nic_data->n_piobufs) *
1356                                               efx->vi_stride) -
1357                                    uc_mem_map_size);
1358                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1359         } else {
1360                 pio_write_vi_base = 0;
1361                 wc_mem_map_size = 0;
1362                 max_vis = channel_vis;
1363         }
1364
1365         /* In case the last attached driver failed to free VIs, do it now */
1366         rc = efx_ef10_free_vis(efx);
1367         if (rc != 0)
1368                 return rc;
1369
1370         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1371         if (rc != 0)
1372                 return rc;
1373
1374         if (nic_data->n_allocated_vis < channel_vis) {
1375                 netif_info(efx, drv, efx->net_dev,
1376                            "Could not allocate enough VIs to satisfy RSS"
1377                            " requirements. Performance may not be optimal.\n");
1378                 /* We didn't get the VIs to populate our channels.
1379                  * We could keep what we got but then we'd have more
1380                  * interrupts than we need.
1381                  * Instead calculate new max_channels and restart
1382                  */
1383                 efx->max_channels = nic_data->n_allocated_vis;
1384                 efx->max_tx_channels =
1385                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1386
1387                 efx_ef10_free_vis(efx);
1388                 return -EAGAIN;
1389         }
1390
1391         /* If we didn't get enough VIs to map all the PIO buffers, free the
1392          * PIO buffers
1393          */
1394         if (nic_data->n_piobufs &&
1395             nic_data->n_allocated_vis <
1396             pio_write_vi_base + nic_data->n_piobufs) {
1397                 netif_dbg(efx, probe, efx->net_dev,
1398                           "%u VIs are not sufficient to map %u PIO buffers\n",
1399                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1400                 efx_ef10_free_piobufs(efx);
1401         }
1402
1403         /* Shrink the original UC mapping of the memory BAR */
1404         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1405         if (!membase) {
1406                 netif_err(efx, probe, efx->net_dev,
1407                           "could not shrink memory BAR to %x\n",
1408                           uc_mem_map_size);
1409                 return -ENOMEM;
1410         }
1411         iounmap(efx->membase);
1412         efx->membase = membase;
1413
1414         /* Set up the WC mapping if needed */
1415         if (wc_mem_map_size) {
1416                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1417                                                   uc_mem_map_size,
1418                                                   wc_mem_map_size);
1419                 if (!nic_data->wc_membase) {
1420                         netif_err(efx, probe, efx->net_dev,
1421                                   "could not allocate WC mapping of size %x\n",
1422                                   wc_mem_map_size);
1423                         return -ENOMEM;
1424                 }
1425                 nic_data->pio_write_vi_base = pio_write_vi_base;
1426                 nic_data->pio_write_base =
1427                         nic_data->wc_membase +
1428                         (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1429                          uc_mem_map_size);
1430
1431                 rc = efx_ef10_link_piobufs(efx);
1432                 if (rc)
1433                         efx_ef10_free_piobufs(efx);
1434         }
1435
1436         netif_dbg(efx, probe, efx->net_dev,
1437                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1438                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1439                   nic_data->wc_membase, wc_mem_map_size);
1440
1441         return 0;
1442 }
1443
1444 static int efx_ef10_init_nic(struct efx_nic *efx)
1445 {
1446         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1447         int rc;
1448
1449         if (nic_data->must_check_datapath_caps) {
1450                 rc = efx_ef10_init_datapath_caps(efx);
1451                 if (rc)
1452                         return rc;
1453                 nic_data->must_check_datapath_caps = false;
1454         }
1455
1456         if (nic_data->must_realloc_vis) {
1457                 /* We cannot let the number of VIs change now */
1458                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1459                                         nic_data->n_allocated_vis);
1460                 if (rc)
1461                         return rc;
1462                 nic_data->must_realloc_vis = false;
1463         }
1464
1465         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1466                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1467                 if (rc == 0) {
1468                         rc = efx_ef10_link_piobufs(efx);
1469                         if (rc)
1470                                 efx_ef10_free_piobufs(efx);
1471                 }
1472
1473                 /* Log an error on failure, but this is non-fatal.
1474                  * Permission errors are less important - we've presumably
1475                  * had the PIO buffer licence removed.
1476                  */
1477                 if (rc == -EPERM)
1478                         netif_dbg(efx, drv, efx->net_dev,
1479                                   "not permitted to restore PIO buffers\n");
1480                 else if (rc)
1481                         netif_err(efx, drv, efx->net_dev,
1482                                   "failed to restore PIO buffers (%d)\n", rc);
1483                 nic_data->must_restore_piobufs = false;
1484         }
1485
1486         /* don't fail init if RSS setup doesn't work */
1487         rc = efx->type->rx_push_rss_config(efx, false,
1488                                            efx->rss_context.rx_indir_table, NULL);
1489
1490         return 0;
1491 }
1492
1493 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1494 {
1495         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1496 #ifdef CONFIG_SFC_SRIOV
1497         unsigned int i;
1498 #endif
1499
1500         /* All our allocations have been reset */
1501         nic_data->must_realloc_vis = true;
1502         nic_data->must_restore_rss_contexts = true;
1503         nic_data->must_restore_filters = true;
1504         nic_data->must_restore_piobufs = true;
1505         efx_ef10_forget_old_piobufs(efx);
1506         efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
1507
1508         /* Driver-created vswitches and vports must be re-created */
1509         nic_data->must_probe_vswitching = true;
1510         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1511 #ifdef CONFIG_SFC_SRIOV
1512         if (nic_data->vf)
1513                 for (i = 0; i < efx->vf_count; i++)
1514                         nic_data->vf[i].vport_id = 0;
1515 #endif
1516 }
1517
1518 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1519 {
1520         if (reason == RESET_TYPE_MC_FAILURE)
1521                 return RESET_TYPE_DATAPATH;
1522
1523         return efx_mcdi_map_reset_reason(reason);
1524 }
1525
1526 static int efx_ef10_map_reset_flags(u32 *flags)
1527 {
1528         enum {
1529                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1530                                    ETH_RESET_SHARED_SHIFT),
1531                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1532                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1533                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1534                                  ETH_RESET_SHARED_SHIFT)
1535         };
1536
1537         /* We assume for now that our PCI function is permitted to
1538          * reset everything.
1539          */
1540
1541         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1542                 *flags &= ~EF10_RESET_MC;
1543                 return RESET_TYPE_WORLD;
1544         }
1545
1546         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1547                 *flags &= ~EF10_RESET_PORT;
1548                 return RESET_TYPE_ALL;
1549         }
1550
1551         /* no invisible reset implemented */
1552
1553         return -EINVAL;
1554 }
1555
1556 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1557 {
1558         int rc = efx_mcdi_reset(efx, reset_type);
1559
1560         /* Unprivileged functions return -EPERM, but need to return success
1561          * here so that the datapath is brought back up.
1562          */
1563         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1564                 rc = 0;
1565
1566         /* If it was a port reset, trigger reallocation of MC resources.
1567          * Note that on an MC reset nothing needs to be done now because we'll
1568          * detect the MC reset later and handle it then.
1569          * For an FLR, we never get an MC reset event, but the MC has reset all
1570          * resources assigned to us, so we have to trigger reallocation now.
1571          */
1572         if ((reset_type == RESET_TYPE_ALL ||
1573              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1574                 efx_ef10_reset_mc_allocations(efx);
1575         return rc;
1576 }
1577
1578 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1579         [EF10_STAT_ ## ext_name] =                              \
1580         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1581 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1582         [EF10_STAT_ ## int_name] =                              \
1583         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1584 #define EF10_OTHER_STAT(ext_name)                               \
1585         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1586 #define GENERIC_SW_STAT(ext_name)                               \
1587         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1588
1589 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1590         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1591         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1592         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1593         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1594         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1595         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1596         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1597         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1598         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1599         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1600         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1601         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1602         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1603         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1604         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1605         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1606         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1607         EF10_OTHER_STAT(port_rx_good_bytes),
1608         EF10_OTHER_STAT(port_rx_bad_bytes),
1609         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1610         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1611         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1612         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1613         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1614         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1615         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1616         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1617         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1618         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1619         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1620         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1621         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1622         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1623         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1624         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1625         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1626         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1627         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1628         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1629         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1630         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1631         GENERIC_SW_STAT(rx_nodesc_trunc),
1632         GENERIC_SW_STAT(rx_noskb_drops),
1633         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1634         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1635         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1636         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1637         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1638         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1639         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1640         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1641         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1642         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1643         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1644         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1645         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1646         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1647         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1648         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1649         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1650         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1651         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1652         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1653         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1654         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1655         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1656         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1657         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1658         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1659         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1660         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1661         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1662         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1663         EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1664         EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1665         EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1666         EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1667         EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1668         EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1669         EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1670         EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1671         EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1672         EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1673         EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1674         EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1675         EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1676         EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1677         EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1678         EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1679         EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1680         EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1681         EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1682         EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1683         EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1684         EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1685 };
1686
1687 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1688                                (1ULL << EF10_STAT_port_tx_packets) |    \
1689                                (1ULL << EF10_STAT_port_tx_pause) |      \
1690                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1691                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1692                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1693                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1694                                (1ULL <<                                 \
1695                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1696                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1697                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1698                                (1ULL << EF10_STAT_port_rx_packets) |    \
1699                                (1ULL << EF10_STAT_port_rx_good) |       \
1700                                (1ULL << EF10_STAT_port_rx_bad) |        \
1701                                (1ULL << EF10_STAT_port_rx_pause) |      \
1702                                (1ULL << EF10_STAT_port_rx_control) |    \
1703                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1704                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1705                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1706                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1707                                (1ULL << EF10_STAT_port_rx_64) |         \
1708                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1709                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1710                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1711                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1712                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1713                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1714                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1715                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1716                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1717                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1718                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1719                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1720
1721 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1722  * For a 10G/40G switchable port we do not expose these because they might
1723  * not include all the packets they should.
1724  * On 8000 series NICs these statistics are always provided.
1725  */
1726 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1727                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1728                                  (1ULL << EF10_STAT_port_tx_64) |       \
1729                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1730                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1731                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1732                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1733                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1734                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1735
1736 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1737  * switchable port we do expose these because the errors will otherwise
1738  * be silent.
1739  */
1740 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1741                                   (1ULL << EF10_STAT_port_rx_length_error))
1742
1743 /* These statistics are only provided if the firmware supports the
1744  * capability PM_AND_RXDP_COUNTERS.
1745  */
1746 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1747         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1748         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1749         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1750         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1751         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1752         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1753         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1754         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1755         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1756         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1757         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1758         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1759
1760 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1761  * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1762  * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1763  * These bits are in the second u64 of the raw mask.
1764  */
1765 #define EF10_FEC_STAT_MASK (                                            \
1766         (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) |             \
1767         (1ULL << (EF10_STAT_fec_corrected_errors - 64)) |               \
1768         (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) |        \
1769         (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) |        \
1770         (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) |        \
1771         (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1772
1773 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1774  * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1775  * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1776  * These bits are in the second u64 of the raw mask.
1777  */
1778 #define EF10_CTPIO_STAT_MASK (                                          \
1779         (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) |             \
1780         (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) |           \
1781         (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) |           \
1782         (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) |                \
1783         (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) |               \
1784         (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) |                 \
1785         (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) |            \
1786         (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) |             \
1787         (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) |              \
1788         (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) |          \
1789         (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) |         \
1790         (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) |                \
1791         (1ULL << (EF10_STAT_ctpio_success - 64)) |                      \
1792         (1ULL << (EF10_STAT_ctpio_fallback - 64)) |                     \
1793         (1ULL << (EF10_STAT_ctpio_poison - 64)) |                       \
1794         (1ULL << (EF10_STAT_ctpio_erase - 64)))
1795
1796 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1797 {
1798         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1799         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1800         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1801
1802         if (!(efx->mcdi->fn_flags &
1803               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1804                 return 0;
1805
1806         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1807                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1808                 /* 8000 series have everything even at 40G */
1809                 if (nic_data->datapath_caps2 &
1810                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1811                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1812         } else {
1813                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1814         }
1815
1816         if (nic_data->datapath_caps &
1817             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1818                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1819
1820         return raw_mask;
1821 }
1822
1823 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1824 {
1825         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1826         u64 raw_mask[2];
1827
1828         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1829
1830         /* Only show vadaptor stats when EVB capability is present */
1831         if (nic_data->datapath_caps &
1832             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1833                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1834                 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1835         } else {
1836                 raw_mask[1] = 0;
1837         }
1838         /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1839         if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1840                 raw_mask[1] |= EF10_FEC_STAT_MASK;
1841
1842         /* CTPIO stats appear in V3. Only show them on devices that actually
1843          * support CTPIO. Although this driver doesn't use CTPIO others might,
1844          * and we may be reporting the stats for the underlying port.
1845          */
1846         if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1847             (nic_data->datapath_caps2 &
1848              (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1849                 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1850
1851 #if BITS_PER_LONG == 64
1852         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1853         mask[0] = raw_mask[0];
1854         mask[1] = raw_mask[1];
1855 #else
1856         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1857         mask[0] = raw_mask[0] & 0xffffffff;
1858         mask[1] = raw_mask[0] >> 32;
1859         mask[2] = raw_mask[1] & 0xffffffff;
1860 #endif
1861 }
1862
1863 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1864 {
1865         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1866
1867         efx_ef10_get_stat_mask(efx, mask);
1868         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1869                                       mask, names);
1870 }
1871
1872 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1873                                            struct rtnl_link_stats64 *core_stats)
1874 {
1875         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1876         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1877         u64 *stats = nic_data->stats;
1878         size_t stats_count = 0, index;
1879
1880         efx_ef10_get_stat_mask(efx, mask);
1881
1882         if (full_stats) {
1883                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1884                         if (efx_ef10_stat_desc[index].name) {
1885                                 *full_stats++ = stats[index];
1886                                 ++stats_count;
1887                         }
1888                 }
1889         }
1890
1891         if (!core_stats)
1892                 return stats_count;
1893
1894         if (nic_data->datapath_caps &
1895                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1896                 /* Use vadaptor stats. */
1897                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1898                                          stats[EF10_STAT_rx_multicast] +
1899                                          stats[EF10_STAT_rx_broadcast];
1900                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1901                                          stats[EF10_STAT_tx_multicast] +
1902                                          stats[EF10_STAT_tx_broadcast];
1903                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1904                                        stats[EF10_STAT_rx_multicast_bytes] +
1905                                        stats[EF10_STAT_rx_broadcast_bytes];
1906                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1907                                        stats[EF10_STAT_tx_multicast_bytes] +
1908                                        stats[EF10_STAT_tx_broadcast_bytes];
1909                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1910                                          stats[GENERIC_STAT_rx_noskb_drops];
1911                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1912                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1913                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1914                 core_stats->rx_errors = core_stats->rx_crc_errors;
1915                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1916         } else {
1917                 /* Use port stats. */
1918                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1919                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1920                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1921                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1922                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1923                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1924                                          stats[GENERIC_STAT_rx_noskb_drops];
1925                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1926                 core_stats->rx_length_errors =
1927                                 stats[EF10_STAT_port_rx_gtjumbo] +
1928                                 stats[EF10_STAT_port_rx_length_error];
1929                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1930                 core_stats->rx_frame_errors =
1931                                 stats[EF10_STAT_port_rx_align_error];
1932                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1933                 core_stats->rx_errors = (core_stats->rx_length_errors +
1934                                          core_stats->rx_crc_errors +
1935                                          core_stats->rx_frame_errors);
1936         }
1937
1938         return stats_count;
1939 }
1940
1941 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1942 {
1943         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1944         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1945         __le64 generation_start, generation_end;
1946         u64 *stats = nic_data->stats;
1947         __le64 *dma_stats;
1948
1949         efx_ef10_get_stat_mask(efx, mask);
1950
1951         dma_stats = efx->stats_buffer.addr;
1952
1953         generation_end = dma_stats[efx->num_mac_stats - 1];
1954         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1955                 return 0;
1956         rmb();
1957         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1958                              stats, efx->stats_buffer.addr, false);
1959         rmb();
1960         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1961         if (generation_end != generation_start)
1962                 return -EAGAIN;
1963
1964         /* Update derived statistics */
1965         efx_nic_fix_nodesc_drop_stat(efx,
1966                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1967         stats[EF10_STAT_port_rx_good_bytes] =
1968                 stats[EF10_STAT_port_rx_bytes] -
1969                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1970         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1971                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1972         efx_update_sw_stats(efx, stats);
1973         return 0;
1974 }
1975
1976
1977 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1978                                        struct rtnl_link_stats64 *core_stats)
1979 {
1980         int retry;
1981
1982         /* If we're unlucky enough to read statistics during the DMA, wait
1983          * up to 10ms for it to finish (typically takes <500us)
1984          */
1985         for (retry = 0; retry < 100; ++retry) {
1986                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1987                         break;
1988                 udelay(100);
1989         }
1990
1991         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1992 }
1993
1994 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1995 {
1996         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1997         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1999         __le64 generation_start, generation_end;
2000         u64 *stats = nic_data->stats;
2001         u32 dma_len = efx->num_mac_stats * sizeof(u64);
2002         struct efx_buffer stats_buf;
2003         __le64 *dma_stats;
2004         int rc;
2005
2006         spin_unlock_bh(&efx->stats_lock);
2007
2008         if (in_interrupt()) {
2009                 /* If in atomic context, cannot update stats.  Just update the
2010                  * software stats and return so the caller can continue.
2011                  */
2012                 spin_lock_bh(&efx->stats_lock);
2013                 efx_update_sw_stats(efx, stats);
2014                 return 0;
2015         }
2016
2017         efx_ef10_get_stat_mask(efx, mask);
2018
2019         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
2020         if (rc) {
2021                 spin_lock_bh(&efx->stats_lock);
2022                 return rc;
2023         }
2024
2025         dma_stats = stats_buf.addr;
2026         dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
2027
2028         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
2029         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
2030                               MAC_STATS_IN_DMA, 1);
2031         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
2032         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2033
2034         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
2035                                 NULL, 0, NULL);
2036         spin_lock_bh(&efx->stats_lock);
2037         if (rc) {
2038                 /* Expect ENOENT if DMA queues have not been set up */
2039                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
2040                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
2041                                                sizeof(inbuf), NULL, 0, rc);
2042                 goto out;
2043         }
2044
2045         generation_end = dma_stats[efx->num_mac_stats - 1];
2046         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
2047                 WARN_ON_ONCE(1);
2048                 goto out;
2049         }
2050         rmb();
2051         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
2052                              stats, stats_buf.addr, false);
2053         rmb();
2054         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
2055         if (generation_end != generation_start) {
2056                 rc = -EAGAIN;
2057                 goto out;
2058         }
2059
2060         efx_update_sw_stats(efx, stats);
2061 out:
2062         /* releasing a DMA coherent buffer with BH disabled can panic */
2063         spin_unlock_bh(&efx->stats_lock);
2064         efx_nic_free_buffer(efx, &stats_buf);
2065         spin_lock_bh(&efx->stats_lock);
2066         return rc;
2067 }
2068
2069 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
2070                                        struct rtnl_link_stats64 *core_stats)
2071 {
2072         if (efx_ef10_try_update_nic_stats_vf(efx))
2073                 return 0;
2074
2075         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
2076 }
2077
2078 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
2079 {
2080         struct efx_nic *efx = channel->efx;
2081         unsigned int mode, usecs;
2082         efx_dword_t timer_cmd;
2083
2084         if (channel->irq_moderation_us) {
2085                 mode = 3;
2086                 usecs = channel->irq_moderation_us;
2087         } else {
2088                 mode = 0;
2089                 usecs = 0;
2090         }
2091
2092         if (EFX_EF10_WORKAROUND_61265(efx)) {
2093                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
2094                 unsigned int ns = usecs * 1000;
2095
2096                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2097                                channel->channel);
2098                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2099                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2100                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2101
2102                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2103                                    inbuf, sizeof(inbuf), 0, NULL, 0);
2104         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2105                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2106
2107                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2108                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
2109                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
2110                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2111                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2112                                 channel->channel);
2113         } else {
2114                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2115
2116                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2117                                      ERF_DZ_TC_TIMER_VAL, ticks,
2118                                      ERF_FZ_TC_TMR_REL_VAL, ticks);
2119                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2120                                 channel->channel);
2121         }
2122 }
2123
2124 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2125                                 struct ethtool_wolinfo *wol) {}
2126
2127 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2128 {
2129         return -EOPNOTSUPP;
2130 }
2131
2132 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2133 {
2134         wol->supported = 0;
2135         wol->wolopts = 0;
2136         memset(&wol->sopass, 0, sizeof(wol->sopass));
2137 }
2138
2139 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2140 {
2141         if (type != 0)
2142                 return -EINVAL;
2143         return 0;
2144 }
2145
2146 static void efx_ef10_mcdi_request(struct efx_nic *efx,
2147                                   const efx_dword_t *hdr, size_t hdr_len,
2148                                   const efx_dword_t *sdu, size_t sdu_len)
2149 {
2150         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2151         u8 *pdu = nic_data->mcdi_buf.addr;
2152
2153         memcpy(pdu, hdr, hdr_len);
2154         memcpy(pdu + hdr_len, sdu, sdu_len);
2155         wmb();
2156
2157         /* The hardware provides 'low' and 'high' (doorbell) registers
2158          * for passing the 64-bit address of an MCDI request to
2159          * firmware.  However the dwords are swapped by firmware.  The
2160          * least significant bits of the doorbell are then 0 for all
2161          * MCDI requests due to alignment.
2162          */
2163         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2164                     ER_DZ_MC_DB_LWRD);
2165         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2166                     ER_DZ_MC_DB_HWRD);
2167 }
2168
2169 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2170 {
2171         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2172         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2173
2174         rmb();
2175         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2176 }
2177
2178 static void
2179 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2180                             size_t offset, size_t outlen)
2181 {
2182         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2183         const u8 *pdu = nic_data->mcdi_buf.addr;
2184
2185         memcpy(outbuf, pdu + offset, outlen);
2186 }
2187
2188 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2189 {
2190         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2191
2192         /* All our allocations have been reset */
2193         efx_ef10_reset_mc_allocations(efx);
2194
2195         /* The datapath firmware might have been changed */
2196         nic_data->must_check_datapath_caps = true;
2197
2198         /* MAC statistics have been cleared on the NIC; clear the local
2199          * statistic that we update with efx_update_diff_stat().
2200          */
2201         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2202 }
2203
2204 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2205 {
2206         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2207         int rc;
2208
2209         rc = efx_ef10_get_warm_boot_count(efx);
2210         if (rc < 0) {
2211                 /* The firmware is presumably in the process of
2212                  * rebooting.  However, we are supposed to report each
2213                  * reboot just once, so we must only do that once we
2214                  * can read and store the updated warm boot count.
2215                  */
2216                 return 0;
2217         }
2218
2219         if (rc == nic_data->warm_boot_count)
2220                 return 0;
2221
2222         nic_data->warm_boot_count = rc;
2223         efx_ef10_mcdi_reboot_detected(efx);
2224
2225         return -EIO;
2226 }
2227
2228 /* Handle an MSI interrupt
2229  *
2230  * Handle an MSI hardware interrupt.  This routine schedules event
2231  * queue processing.  No interrupt acknowledgement cycle is necessary.
2232  * Also, we never need to check that the interrupt is for us, since
2233  * MSI interrupts cannot be shared.
2234  */
2235 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2236 {
2237         struct efx_msi_context *context = dev_id;
2238         struct efx_nic *efx = context->efx;
2239
2240         netif_vdbg(efx, intr, efx->net_dev,
2241                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2242
2243         if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2244                 /* Note test interrupts */
2245                 if (context->index == efx->irq_level)
2246                         efx->last_irq_cpu = raw_smp_processor_id();
2247
2248                 /* Schedule processing of the channel */
2249                 efx_schedule_channel_irq(efx->channel[context->index]);
2250         }
2251
2252         return IRQ_HANDLED;
2253 }
2254
2255 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2256 {
2257         struct efx_nic *efx = dev_id;
2258         bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2259         struct efx_channel *channel;
2260         efx_dword_t reg;
2261         u32 queues;
2262
2263         /* Read the ISR which also ACKs the interrupts */
2264         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2265         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2266
2267         if (queues == 0)
2268                 return IRQ_NONE;
2269
2270         if (likely(soft_enabled)) {
2271                 /* Note test interrupts */
2272                 if (queues & (1U << efx->irq_level))
2273                         efx->last_irq_cpu = raw_smp_processor_id();
2274
2275                 efx_for_each_channel(channel, efx) {
2276                         if (queues & 1)
2277                                 efx_schedule_channel_irq(channel);
2278                         queues >>= 1;
2279                 }
2280         }
2281
2282         netif_vdbg(efx, intr, efx->net_dev,
2283                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2284                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2285
2286         return IRQ_HANDLED;
2287 }
2288
2289 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2290 {
2291         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2292
2293         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2294                                     NULL) == 0)
2295                 return -ENOTSUPP;
2296
2297         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2298
2299         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2300         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2301                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2302 }
2303
2304 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2305 {
2306         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2307                                     (tx_queue->ptr_mask + 1) *
2308                                     sizeof(efx_qword_t),
2309                                     GFP_KERNEL);
2310 }
2311
2312 /* This writes to the TX_DESC_WPTR and also pushes data */
2313 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2314                                          const efx_qword_t *txd)
2315 {
2316         unsigned int write_ptr;
2317         efx_oword_t reg;
2318
2319         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2320         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2321         reg.qword[0] = *txd;
2322         efx_writeo_page(tx_queue->efx, &reg,
2323                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2324 }
2325
2326 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2327  */
2328 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2329                                 struct sk_buff *skb,
2330                                 bool *data_mapped)
2331 {
2332         struct efx_tx_buffer *buffer;
2333         struct tcphdr *tcp;
2334         struct iphdr *ip;
2335
2336         u16 ipv4_id;
2337         u32 seqnum;
2338         u32 mss;
2339
2340         EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2341
2342         mss = skb_shinfo(skb)->gso_size;
2343
2344         if (unlikely(mss < 4)) {
2345                 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2346                 return -EINVAL;
2347         }
2348
2349         ip = ip_hdr(skb);
2350         if (ip->version == 4) {
2351                 /* Modify IPv4 header if needed. */
2352                 ip->tot_len = 0;
2353                 ip->check = 0;
2354                 ipv4_id = ntohs(ip->id);
2355         } else {
2356                 /* Modify IPv6 header if needed. */
2357                 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2358
2359                 ipv6->payload_len = 0;
2360                 ipv4_id = 0;
2361         }
2362
2363         tcp = tcp_hdr(skb);
2364         seqnum = ntohl(tcp->seq);
2365
2366         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2367
2368         buffer->flags = EFX_TX_BUF_OPTION;
2369         buffer->len = 0;
2370         buffer->unmap_len = 0;
2371         EFX_POPULATE_QWORD_5(buffer->option,
2372                         ESF_DZ_TX_DESC_IS_OPT, 1,
2373                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2374                         ESF_DZ_TX_TSO_OPTION_TYPE,
2375                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2376                         ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2377                         ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2378                         );
2379         ++tx_queue->insert_count;
2380
2381         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2382
2383         buffer->flags = EFX_TX_BUF_OPTION;
2384         buffer->len = 0;
2385         buffer->unmap_len = 0;
2386         EFX_POPULATE_QWORD_4(buffer->option,
2387                         ESF_DZ_TX_DESC_IS_OPT, 1,
2388                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2389                         ESF_DZ_TX_TSO_OPTION_TYPE,
2390                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2391                         ESF_DZ_TX_TSO_TCP_MSS, mss
2392                         );
2393         ++tx_queue->insert_count;
2394
2395         return 0;
2396 }
2397
2398 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2399 {
2400         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2401         u32 tso_versions = 0;
2402
2403         if (nic_data->datapath_caps &
2404             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2405                 tso_versions |= BIT(1);
2406         if (nic_data->datapath_caps2 &
2407             (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2408                 tso_versions |= BIT(2);
2409         return tso_versions;
2410 }
2411
2412 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2413 {
2414         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2415                                                        EFX_BUF_SIZE));
2416         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2417         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2418         struct efx_channel *channel = tx_queue->channel;
2419         struct efx_nic *efx = tx_queue->efx;
2420         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2421         bool tso_v2 = false;
2422         size_t inlen;
2423         dma_addr_t dma_addr;
2424         efx_qword_t *txd;
2425         int rc;
2426         int i;
2427         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2428
2429         /* Only attempt to enable TX timestamping if we have the license for it,
2430          * otherwise TXQ init will fail
2431          */
2432         if (!(nic_data->licensed_features &
2433               (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
2434                 tx_queue->timestamping = false;
2435                 /* Disable sync events on this channel. */
2436                 if (efx->type->ptp_set_ts_sync_events)
2437                         efx->type->ptp_set_ts_sync_events(efx, false, false);
2438         }
2439
2440         /* TSOv2 is a limited resource that can only be configured on a limited
2441          * number of queues. TSO without checksum offload is not really a thing,
2442          * so we only enable it for those queues.
2443          * TSOv2 cannot be used with Hardware timestamping.
2444          */
2445         if (csum_offload && (nic_data->datapath_caps2 &
2446                         (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) &&
2447             !tx_queue->timestamping) {
2448                 tso_v2 = true;
2449                 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2450                                 channel->channel);
2451         }
2452
2453         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2454         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2455         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2456         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2457         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2458         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2459
2460         dma_addr = tx_queue->txd.buf.dma_addr;
2461
2462         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2463                   tx_queue->queue, entries, (u64)dma_addr);
2464
2465         for (i = 0; i < entries; ++i) {
2466                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2467                 dma_addr += EFX_BUF_SIZE;
2468         }
2469
2470         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2471
2472         do {
2473                 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS,
2474                                 /* This flag was removed from mcdi_pcol.h for
2475                                  * the non-_EXT version of INIT_TXQ.  However,
2476                                  * firmware still honours it.
2477                                  */
2478                                 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2479                                 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2480                                 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
2481                                 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP,
2482                                                 tx_queue->timestamping);
2483
2484                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2485                                         NULL, 0, NULL);
2486                 if (rc == -ENOSPC && tso_v2) {
2487                         /* Retry without TSOv2 if we're short on contexts. */
2488                         tso_v2 = false;
2489                         netif_warn(efx, probe, efx->net_dev,
2490                                    "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2491                 } else if (rc) {
2492                         efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2493                                                MC_CMD_INIT_TXQ_EXT_IN_LEN,
2494                                                NULL, 0, rc);
2495                         goto fail;
2496                 }
2497         } while (rc);
2498
2499         /* A previous user of this TX queue might have set us up the
2500          * bomb by writing a descriptor to the TX push collector but
2501          * not the doorbell.  (Each collector belongs to a port, not a
2502          * queue or function, so cannot easily be reset.)  We must
2503          * attempt to push a no-op descriptor in its place.
2504          */
2505         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2506         tx_queue->insert_count = 1;
2507         txd = efx_tx_desc(tx_queue, 0);
2508         EFX_POPULATE_QWORD_5(*txd,
2509                              ESF_DZ_TX_DESC_IS_OPT, true,
2510                              ESF_DZ_TX_OPTION_TYPE,
2511                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2512                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2513                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload,
2514                              ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2515         tx_queue->write_count = 1;
2516
2517         if (tso_v2) {
2518                 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2519                 tx_queue->tso_version = 2;
2520         } else if (nic_data->datapath_caps &
2521                         (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2522                 tx_queue->tso_version = 1;
2523         }
2524
2525         wmb();
2526         efx_ef10_push_tx_desc(tx_queue, txd);
2527
2528         return;
2529
2530 fail:
2531         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2532                     tx_queue->queue);
2533 }
2534
2535 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2536 {
2537         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2538         MCDI_DECLARE_BUF_ERR(outbuf);
2539         struct efx_nic *efx = tx_queue->efx;
2540         size_t outlen;
2541         int rc;
2542
2543         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2544                        tx_queue->queue);
2545
2546         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2547                           outbuf, sizeof(outbuf), &outlen);
2548
2549         if (rc && rc != -EALREADY)
2550                 goto fail;
2551
2552         return;
2553
2554 fail:
2555         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2556                                outbuf, outlen, rc);
2557 }
2558
2559 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2560 {
2561         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2562 }
2563
2564 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2565 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2566 {
2567         unsigned int write_ptr;
2568         efx_dword_t reg;
2569
2570         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2571         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2572         efx_writed_page(tx_queue->efx, &reg,
2573                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2574 }
2575
2576 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2577
2578 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2579                                           dma_addr_t dma_addr, unsigned int len)
2580 {
2581         if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2582                 /* If we need to break across multiple descriptors we should
2583                  * stop at a page boundary. This assumes the length limit is
2584                  * greater than the page size.
2585                  */
2586                 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2587
2588                 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2589                 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2590         }
2591
2592         return len;
2593 }
2594
2595 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2596 {
2597         unsigned int old_write_count = tx_queue->write_count;
2598         struct efx_tx_buffer *buffer;
2599         unsigned int write_ptr;
2600         efx_qword_t *txd;
2601
2602         tx_queue->xmit_more_available = false;
2603         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2604                 return;
2605
2606         do {
2607                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2608                 buffer = &tx_queue->buffer[write_ptr];
2609                 txd = efx_tx_desc(tx_queue, write_ptr);
2610                 ++tx_queue->write_count;
2611
2612                 /* Create TX descriptor ring entry */
2613                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2614                         *txd = buffer->option;
2615                         if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2616                                 /* PIO descriptor */
2617                                 tx_queue->packet_write_count = tx_queue->write_count;
2618                 } else {
2619                         tx_queue->packet_write_count = tx_queue->write_count;
2620                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2621                         EFX_POPULATE_QWORD_3(
2622                                 *txd,
2623                                 ESF_DZ_TX_KER_CONT,
2624                                 buffer->flags & EFX_TX_BUF_CONT,
2625                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2626                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2627                 }
2628         } while (tx_queue->write_count != tx_queue->insert_count);
2629
2630         wmb(); /* Ensure descriptors are written before they are fetched */
2631
2632         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2633                 txd = efx_tx_desc(tx_queue,
2634                                   old_write_count & tx_queue->ptr_mask);
2635                 efx_ef10_push_tx_desc(tx_queue, txd);
2636                 ++tx_queue->pushes;
2637         } else {
2638                 efx_ef10_notify_tx_desc(tx_queue);
2639         }
2640 }
2641
2642 #define RSS_MODE_HASH_ADDRS     (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2643                                  1 << RSS_MODE_HASH_DST_ADDR_LBN)
2644 #define RSS_MODE_HASH_PORTS     (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2645                                  1 << RSS_MODE_HASH_DST_PORT_LBN)
2646 #define RSS_CONTEXT_FLAGS_DEFAULT       (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2647                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2648                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2649                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2650                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2651                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2652                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2653                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2654                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2655                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2656
2657 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2658 {
2659         /* Firmware had a bug (sfc bug 61952) where it would not actually
2660          * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2661          * This meant that it would always contain whatever was previously
2662          * in the MCDI buffer.  Fortunately, all firmware versions with
2663          * this bug have the same default flags value for a newly-allocated
2664          * RSS context, and the only time we want to get the flags is just
2665          * after allocating.  Moreover, the response has a 32-bit hole
2666          * where the context ID would be in the request, so we can use an
2667          * overlength buffer in the request and pre-fill the flags field
2668          * with what we believe the default to be.  Thus if the firmware
2669          * has the bug, it will leave our pre-filled value in the flags
2670          * field of the response, and we will get the right answer.
2671          *
2672          * However, this does mean that this function should NOT be used if
2673          * the RSS context flags might not be their defaults - it is ONLY
2674          * reliably correct for a newly-allocated RSS context.
2675          */
2676         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2677         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2678         size_t outlen;
2679         int rc;
2680
2681         /* Check we have a hole for the context ID */
2682         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2683         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2684         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2685                        RSS_CONTEXT_FLAGS_DEFAULT);
2686         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2687                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2688         if (rc == 0) {
2689                 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2690                         rc = -EIO;
2691                 else
2692                         *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2693         }
2694         return rc;
2695 }
2696
2697 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2698  * If we fail, we just leave the RSS context at its default hash settings,
2699  * which is safe but may slightly reduce performance.
2700  * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2701  * just need to set the UDP ports flags (for both IP versions).
2702  */
2703 static void efx_ef10_set_rss_flags(struct efx_nic *efx,
2704                                    struct efx_rss_context *ctx)
2705 {
2706         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2707         u32 flags;
2708
2709         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2710
2711         if (efx_ef10_get_rss_flags(efx, ctx->context_id, &flags) != 0)
2712                 return;
2713         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
2714                        ctx->context_id);
2715         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2716         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2717         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2718         if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2719                           NULL, 0, NULL))
2720                 /* Succeeded, so UDP 4-tuple is now enabled */
2721                 ctx->rx_hash_udp_4tuple = true;
2722 }
2723
2724 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, bool exclusive,
2725                                       struct efx_rss_context *ctx,
2726                                       unsigned *context_size)
2727 {
2728         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2729         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2730         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2731         size_t outlen;
2732         int rc;
2733         u32 alloc_type = exclusive ?
2734                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2735                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2736         unsigned rss_spread = exclusive ?
2737                                 efx->rss_spread :
2738                                 min(rounddown_pow_of_two(efx->rss_spread),
2739                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2740
2741         if (!exclusive && rss_spread == 1) {
2742                 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2743                 if (context_size)
2744                         *context_size = 1;
2745                 return 0;
2746         }
2747
2748         if (nic_data->datapath_caps &
2749             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2750                 return -EOPNOTSUPP;
2751
2752         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2753                        nic_data->vport_id);
2754         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2755         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2756
2757         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2758                 outbuf, sizeof(outbuf), &outlen);
2759         if (rc != 0)
2760                 return rc;
2761
2762         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2763                 return -EIO;
2764
2765         ctx->context_id = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2766
2767         if (context_size)
2768                 *context_size = rss_spread;
2769
2770         if (nic_data->datapath_caps &
2771             1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2772                 efx_ef10_set_rss_flags(efx, ctx);
2773
2774         return 0;
2775 }
2776
2777 static int efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2778 {
2779         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2780
2781         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2782                        context);
2783         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2784                             NULL, 0, NULL);
2785 }
2786
2787 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2788                                        const u32 *rx_indir_table, const u8 *key)
2789 {
2790         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2791         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2792         int i, rc;
2793
2794         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2795                        context);
2796         BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_indir_table) !=
2797                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2798
2799         /* This iterates over the length of efx->rss_context.rx_indir_table, but
2800          * copies bytes from rx_indir_table.  That's because the latter is a
2801          * pointer rather than an array, but should have the same length.
2802          * The efx->rss_context.rx_hash_key loop below is similar.
2803          */
2804         for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_indir_table); ++i)
2805                 MCDI_PTR(tablebuf,
2806                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2807                                 (u8) rx_indir_table[i];
2808
2809         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2810                           sizeof(tablebuf), NULL, 0, NULL);
2811         if (rc != 0)
2812                 return rc;
2813
2814         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2815                        context);
2816         BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_hash_key) !=
2817                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2818         for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_hash_key); ++i)
2819                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2820
2821         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2822                             sizeof(keybuf), NULL, 0, NULL);
2823 }
2824
2825 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2826 {
2827         int rc;
2828
2829         if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID) {
2830                 rc = efx_ef10_free_rss_context(efx, efx->rss_context.context_id);
2831                 WARN_ON(rc != 0);
2832         }
2833         efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2834 }
2835
2836 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2837                                               unsigned *context_size)
2838 {
2839         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2840         int rc = efx_ef10_alloc_rss_context(efx, false, &efx->rss_context,
2841                                             context_size);
2842
2843         if (rc != 0)
2844                 return rc;
2845
2846         nic_data->rx_rss_context_exclusive = false;
2847         efx_set_default_rx_indir_table(efx, &efx->rss_context);
2848         return 0;
2849 }
2850
2851 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2852                                                  const u32 *rx_indir_table,
2853                                                  const u8 *key)
2854 {
2855         u32 old_rx_rss_context = efx->rss_context.context_id;
2856         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2857         int rc;
2858
2859         if (efx->rss_context.context_id == EFX_EF10_RSS_CONTEXT_INVALID ||
2860             !nic_data->rx_rss_context_exclusive) {
2861                 rc = efx_ef10_alloc_rss_context(efx, true, &efx->rss_context,
2862                                                 NULL);
2863                 if (rc == -EOPNOTSUPP)
2864                         return rc;
2865                 else if (rc != 0)
2866                         goto fail1;
2867         }
2868
2869         rc = efx_ef10_populate_rss_table(efx, efx->rss_context.context_id,
2870                                          rx_indir_table, key);
2871         if (rc != 0)
2872                 goto fail2;
2873
2874         if (efx->rss_context.context_id != old_rx_rss_context &&
2875             old_rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2876                 WARN_ON(efx_ef10_free_rss_context(efx, old_rx_rss_context) != 0);
2877         nic_data->rx_rss_context_exclusive = true;
2878         if (rx_indir_table != efx->rss_context.rx_indir_table)
2879                 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
2880                        sizeof(efx->rss_context.rx_indir_table));
2881         if (key != efx->rss_context.rx_hash_key)
2882                 memcpy(efx->rss_context.rx_hash_key, key,
2883                        efx->type->rx_hash_key_size);
2884
2885         return 0;
2886
2887 fail2:
2888         if (old_rx_rss_context != efx->rss_context.context_id) {
2889                 WARN_ON(efx_ef10_free_rss_context(efx, efx->rss_context.context_id) != 0);
2890                 efx->rss_context.context_id = old_rx_rss_context;
2891         }
2892 fail1:
2893         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2894         return rc;
2895 }
2896
2897 static int efx_ef10_rx_push_rss_context_config(struct efx_nic *efx,
2898                                                struct efx_rss_context *ctx,
2899                                                const u32 *rx_indir_table,
2900                                                const u8 *key)
2901 {
2902         int rc;
2903
2904         WARN_ON(!mutex_is_locked(&efx->rss_lock));
2905
2906         if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
2907                 rc = efx_ef10_alloc_rss_context(efx, true, ctx, NULL);
2908                 if (rc)
2909                         return rc;
2910         }
2911
2912         if (!rx_indir_table) /* Delete this context */
2913                 return efx_ef10_free_rss_context(efx, ctx->context_id);
2914
2915         rc = efx_ef10_populate_rss_table(efx, ctx->context_id,
2916                                          rx_indir_table, key);
2917         if (rc)
2918                 return rc;
2919
2920         memcpy(ctx->rx_indir_table, rx_indir_table,
2921                sizeof(efx->rss_context.rx_indir_table));
2922         memcpy(ctx->rx_hash_key, key, efx->type->rx_hash_key_size);
2923
2924         return 0;
2925 }
2926
2927 static int efx_ef10_rx_pull_rss_context_config(struct efx_nic *efx,
2928                                                struct efx_rss_context *ctx)
2929 {
2930         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2931         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2932         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2933         size_t outlen;
2934         int rc, i;
2935
2936         WARN_ON(!mutex_is_locked(&efx->rss_lock));
2937
2938         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2939                      MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2940
2941         if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID)
2942                 return -ENOENT;
2943
2944         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2945                        ctx->context_id);
2946         BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_indir_table) !=
2947                      MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2948         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2949                           tablebuf, sizeof(tablebuf), &outlen);
2950         if (rc != 0)
2951                 return rc;
2952
2953         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2954                 return -EIO;
2955
2956         for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
2957                 ctx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2958                                 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2959
2960         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2961                        ctx->context_id);
2962         BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_hash_key) !=
2963                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2964         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2965                           keybuf, sizeof(keybuf), &outlen);
2966         if (rc != 0)
2967                 return rc;
2968
2969         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2970                 return -EIO;
2971
2972         for (i = 0; i < ARRAY_SIZE(ctx->rx_hash_key); ++i)
2973                 ctx->rx_hash_key[i] = MCDI_PTR(
2974                                 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2975
2976         return 0;
2977 }
2978
2979 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2980 {
2981         int rc;
2982
2983         mutex_lock(&efx->rss_lock);
2984         rc = efx_ef10_rx_pull_rss_context_config(efx, &efx->rss_context);
2985         mutex_unlock(&efx->rss_lock);
2986         return rc;
2987 }
2988
2989 static void efx_ef10_rx_restore_rss_contexts(struct efx_nic *efx)
2990 {
2991         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2992         struct efx_rss_context *ctx;
2993         int rc;
2994
2995         WARN_ON(!mutex_is_locked(&efx->rss_lock));
2996
2997         if (!nic_data->must_restore_rss_contexts)
2998                 return;
2999
3000         list_for_each_entry(ctx, &efx->rss_context.list, list) {
3001                 /* previous NIC RSS context is gone */
3002                 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
3003                 /* so try to allocate a new one */
3004                 rc = efx_ef10_rx_push_rss_context_config(efx, ctx,
3005                                                          ctx->rx_indir_table,
3006                                                          ctx->rx_hash_key);
3007                 if (rc)
3008                         netif_warn(efx, probe, efx->net_dev,
3009                                    "failed to restore RSS context %u, rc=%d"
3010                                    "; RSS filters may fail to be applied\n",
3011                                    ctx->user_id, rc);
3012         }
3013         nic_data->must_restore_rss_contexts = false;
3014 }
3015
3016 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
3017                                           const u32 *rx_indir_table,
3018                                           const u8 *key)
3019 {
3020         int rc;
3021
3022         if (efx->rss_spread == 1)
3023                 return 0;
3024
3025         if (!key)
3026                 key = efx->rss_context.rx_hash_key;
3027
3028         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
3029
3030         if (rc == -ENOBUFS && !user) {
3031                 unsigned context_size;
3032                 bool mismatch = false;
3033                 size_t i;
3034
3035                 for (i = 0;
3036                      i < ARRAY_SIZE(efx->rss_context.rx_indir_table) && !mismatch;
3037                      i++)
3038                         mismatch = rx_indir_table[i] !=
3039                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
3040
3041                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
3042                 if (rc == 0) {
3043                         if (context_size != efx->rss_spread)
3044                                 netif_warn(efx, probe, efx->net_dev,
3045                                            "Could not allocate an exclusive RSS"
3046                                            " context; allocated a shared one of"
3047                                            " different size."
3048                                            " Wanted %u, got %u.\n",
3049                                            efx->rss_spread, context_size);
3050                         else if (mismatch)
3051                                 netif_warn(efx, probe, efx->net_dev,
3052                                            "Could not allocate an exclusive RSS"
3053                                            " context; allocated a shared one but"
3054                                            " could not apply custom"
3055                                            " indirection.\n");
3056                         else
3057                                 netif_info(efx, probe, efx->net_dev,
3058                                            "Could not allocate an exclusive RSS"
3059                                            " context; allocated a shared one.\n");
3060                 }
3061         }
3062         return rc;
3063 }
3064
3065 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
3066                                           const u32 *rx_indir_table
3067                                           __attribute__ ((unused)),
3068                                           const u8 *key
3069                                           __attribute__ ((unused)))
3070 {
3071         if (user)
3072                 return -EOPNOTSUPP;
3073         if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID)
3074                 return 0;
3075         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
3076 }
3077
3078 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
3079 {
3080         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
3081                                     (rx_queue->ptr_mask + 1) *
3082                                     sizeof(efx_qword_t),
3083                                     GFP_KERNEL);
3084 }
3085
3086 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
3087 {
3088         MCDI_DECLARE_BUF(inbuf,
3089                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
3090                                                 EFX_BUF_SIZE));
3091         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3092         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
3093         struct efx_nic *efx = rx_queue->efx;
3094         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3095         size_t inlen;
3096         dma_addr_t dma_addr;
3097         int rc;
3098         int i;
3099         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
3100
3101         rx_queue->scatter_n = 0;
3102         rx_queue->scatter_len = 0;
3103
3104         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
3105         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
3106         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
3107         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
3108                        efx_rx_queue_index(rx_queue));
3109         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
3110                               INIT_RXQ_IN_FLAG_PREFIX, 1,
3111                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
3112         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
3113         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
3114
3115         dma_addr = rx_queue->rxd.buf.dma_addr;
3116
3117         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
3118                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
3119
3120         for (i = 0; i < entries; ++i) {
3121                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
3122                 dma_addr += EFX_BUF_SIZE;
3123         }
3124
3125         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
3126
3127         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
3128                           NULL, 0, NULL);
3129         if (rc)
3130                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
3131                             efx_rx_queue_index(rx_queue));
3132 }
3133
3134 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
3135 {
3136         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
3137         MCDI_DECLARE_BUF_ERR(outbuf);
3138         struct efx_nic *efx = rx_queue->efx;
3139         size_t outlen;
3140         int rc;
3141
3142         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
3143                        efx_rx_queue_index(rx_queue));
3144
3145         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
3146                           outbuf, sizeof(outbuf), &outlen);
3147
3148         if (rc && rc != -EALREADY)
3149                 goto fail;
3150
3151         return;
3152
3153 fail:
3154         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
3155                                outbuf, outlen, rc);
3156 }
3157
3158 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
3159 {
3160         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
3161 }
3162
3163 /* This creates an entry in the RX descriptor queue */
3164 static inline void
3165 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
3166 {
3167         struct efx_rx_buffer *rx_buf;
3168         efx_qword_t *rxd;
3169
3170         rxd = efx_rx_desc(rx_queue, index);
3171         rx_buf = efx_rx_buffer(rx_queue, index);
3172         EFX_POPULATE_QWORD_2(*rxd,
3173                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
3174                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
3175 }
3176
3177 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
3178 {
3179         struct efx_nic *efx = rx_queue->efx;
3180         unsigned int write_count;
3181         efx_dword_t reg;
3182
3183         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
3184         write_count = rx_queue->added_count & ~7;
3185         if (rx_queue->notified_count == write_count)
3186                 return;
3187
3188         do
3189                 efx_ef10_build_rx_desc(
3190                         rx_queue,
3191                         rx_queue->notified_count & rx_queue->ptr_mask);
3192         while (++rx_queue->notified_count != write_count);
3193
3194         wmb();
3195         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3196                              write_count & rx_queue->ptr_mask);
3197         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
3198                         efx_rx_queue_index(rx_queue));
3199 }
3200
3201 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3202
3203 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3204 {
3205         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3206         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3207         efx_qword_t event;
3208
3209         EFX_POPULATE_QWORD_2(event,
3210                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3211                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3212
3213         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3214
3215         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3216          * already swapped the data to little-endian order.
3217          */
3218         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3219                sizeof(efx_qword_t));
3220
3221         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3222                            inbuf, sizeof(inbuf), 0,
3223                            efx_ef10_rx_defer_refill_complete, 0);
3224 }
3225
3226 static void
3227 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3228                                   int rc, efx_dword_t *outbuf,
3229                                   size_t outlen_actual)
3230 {
3231         /* nothing to do */
3232 }
3233
3234 static int efx_ef10_ev_probe(struct efx_channel *channel)
3235 {
3236         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3237                                     (channel->eventq_mask + 1) *
3238                                     sizeof(efx_qword_t),
3239                                     GFP_KERNEL);
3240 }
3241
3242 static void efx_ef10_ev_fini(struct efx_channel *channel)
3243 {
3244         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3245         MCDI_DECLARE_BUF_ERR(outbuf);
3246         struct efx_nic *efx = channel->efx;
3247         size_t outlen;
3248         int rc;
3249
3250         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3251
3252         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3253                           outbuf, sizeof(outbuf), &outlen);
3254
3255         if (rc && rc != -EALREADY)
3256                 goto fail;
3257
3258         return;
3259
3260 fail:
3261         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3262                                outbuf, outlen, rc);
3263 }
3264
3265 static int efx_ef10_ev_init(struct efx_channel *channel)
3266 {
3267         MCDI_DECLARE_BUF(inbuf,
3268                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3269                                                    EFX_BUF_SIZE));
3270         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3271         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3272         struct efx_nic *efx = channel->efx;
3273         struct efx_ef10_nic_data *nic_data;
3274         size_t inlen, outlen;
3275         unsigned int enabled, implemented;
3276         dma_addr_t dma_addr;
3277         int rc;
3278         int i;
3279
3280         nic_data = efx->nic_data;
3281
3282         /* Fill event queue with all ones (i.e. empty events) */
3283         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3284
3285         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3286         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3287         /* INIT_EVQ expects index in vector table, not absolute */
3288         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3289         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3290                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3291         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3292         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3293         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3294                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3295         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3296
3297         if (nic_data->datapath_caps2 &
3298             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3299                 /* Use the new generic approach to specifying event queue
3300                  * configuration, requesting lower latency or higher throughput.
3301                  * The options that actually get used appear in the output.
3302                  */
3303                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3304                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3305                                       INIT_EVQ_V2_IN_FLAG_TYPE,
3306                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3307         } else {
3308                 bool cut_thru = !(nic_data->datapath_caps &
3309                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3310
3311                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3312                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3313                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3314                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3315                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3316         }
3317
3318         dma_addr = channel->eventq.buf.dma_addr;
3319         for (i = 0; i < entries; ++i) {
3320                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3321                 dma_addr += EFX_BUF_SIZE;
3322         }
3323
3324         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3325
3326         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3327                           outbuf, sizeof(outbuf), &outlen);
3328
3329         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3330                 netif_dbg(efx, drv, efx->net_dev,
3331                           "Channel %d using event queue flags %08x\n",
3332                           channel->channel,
3333                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3334
3335         /* IRQ return is ignored */
3336         if (channel->channel || rc)
3337                 return rc;
3338
3339         /* Successfully created event queue on channel 0 */
3340         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3341         if (rc == -ENOSYS) {
3342                 /* GET_WORKAROUNDS was implemented before this workaround,
3343                  * thus it must be unavailable in this firmware.
3344                  */
3345                 nic_data->workaround_26807 = false;
3346                 rc = 0;
3347         } else if (rc) {
3348                 goto fail;
3349         } else {
3350                 nic_data->workaround_26807 =
3351                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3352
3353                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3354                     !nic_data->workaround_26807) {
3355                         unsigned int flags;
3356
3357                         rc = efx_mcdi_set_workaround(efx,
3358                                                      MC_CMD_WORKAROUND_BUG26807,
3359                                                      true, &flags);
3360
3361                         if (!rc) {
3362                                 if (flags &
3363                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3364                                         netif_info(efx, drv, efx->net_dev,
3365                                                    "other functions on NIC have been reset\n");
3366
3367                                         /* With MCFW v4.6.x and earlier, the
3368                                          * boot count will have incremented,
3369                                          * so re-read the warm_boot_count
3370                                          * value now to ensure this function
3371                                          * doesn't think it has changed next
3372                                          * time it checks.
3373                                          */
3374                                         rc = efx_ef10_get_warm_boot_count(efx);
3375                                         if (rc >= 0) {
3376                                                 nic_data->warm_boot_count = rc;
3377                                                 rc = 0;
3378                                         }
3379                                 }
3380                                 nic_data->workaround_26807 = true;
3381                         } else if (rc == -EPERM) {
3382                                 rc = 0;
3383                         }
3384                 }
3385         }
3386
3387         if (!rc)
3388                 return 0;
3389
3390 fail:
3391         efx_ef10_ev_fini(channel);
3392         return rc;
3393 }
3394
3395 static void efx_ef10_ev_remove(struct efx_channel *channel)
3396 {
3397         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3398 }
3399
3400 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3401                                            unsigned int rx_queue_label)
3402 {
3403         struct efx_nic *efx = rx_queue->efx;
3404
3405         netif_info(efx, hw, efx->net_dev,
3406                    "rx event arrived on queue %d labeled as queue %u\n",
3407                    efx_rx_queue_index(rx_queue), rx_queue_label);
3408
3409         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3410 }
3411
3412 static void
3413 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3414                              unsigned int actual, unsigned int expected)
3415 {
3416         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3417         struct efx_nic *efx = rx_queue->efx;
3418
3419         netif_info(efx, hw, efx->net_dev,
3420                    "dropped %d events (index=%d expected=%d)\n",
3421                    dropped, actual, expected);
3422
3423         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3424 }
3425
3426 /* partially received RX was aborted. clean up. */
3427 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3428 {
3429         unsigned int rx_desc_ptr;
3430
3431         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3432                   "scattered RX aborted (dropping %u buffers)\n",
3433                   rx_queue->scatter_n);
3434
3435         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3436
3437         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3438                       0, EFX_RX_PKT_DISCARD);
3439
3440         rx_queue->removed_count += rx_queue->scatter_n;
3441         rx_queue->scatter_n = 0;
3442         rx_queue->scatter_len = 0;
3443         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3444 }
3445
3446 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3447                                            unsigned int n_packets,
3448                                            unsigned int rx_encap_hdr,
3449                                            unsigned int rx_l3_class,
3450                                            unsigned int rx_l4_class,
3451                                            const efx_qword_t *event)
3452 {
3453         struct efx_nic *efx = channel->efx;
3454         bool handled = false;
3455
3456         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3457                 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3458                         if (!efx->loopback_selftest)
3459                                 channel->n_rx_eth_crc_err += n_packets;
3460                         return EFX_RX_PKT_DISCARD;
3461                 }
3462                 handled = true;
3463         }
3464         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3465                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3466                              rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3467                              rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3468                              rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3469                              rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3470                         netdev_WARN(efx->net_dev,
3471                                     "invalid class for RX_IPCKSUM_ERR: event="
3472                                     EFX_QWORD_FMT "\n",
3473                                     EFX_QWORD_VAL(*event));
3474                 if (!efx->loopback_selftest)
3475                         *(rx_encap_hdr ?
3476                           &channel->n_rx_outer_ip_hdr_chksum_err :
3477                           &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3478                 return 0;
3479         }
3480         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3481                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3482                              ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3483                                rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3484                               (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3485                                rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
3486                         netdev_WARN(efx->net_dev,
3487                                     "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3488                                     EFX_QWORD_FMT "\n",
3489                                     EFX_QWORD_VAL(*event));
3490                 if (!efx->loopback_selftest)
3491                         *(rx_encap_hdr ?
3492                           &channel->n_rx_outer_tcp_udp_chksum_err :
3493                           &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3494                 return 0;
3495         }
3496         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3497                 if (unlikely(!rx_encap_hdr))
3498                         netdev_WARN(efx->net_dev,
3499                                     "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3500                                     EFX_QWORD_FMT "\n",
3501                                     EFX_QWORD_VAL(*event));
3502                 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3503                                   rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3504                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3505                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3506                         netdev_WARN(efx->net_dev,
3507                                     "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3508                                     EFX_QWORD_FMT "\n",
3509                                     EFX_QWORD_VAL(*event));
3510                 if (!efx->loopback_selftest)
3511                         channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3512                 return 0;
3513         }
3514         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3515                 if (unlikely(!rx_encap_hdr))
3516                         netdev_WARN(efx->net_dev,
3517                                     "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3518                                     EFX_QWORD_FMT "\n",
3519                                     EFX_QWORD_VAL(*event));
3520                 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3521                                    rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3522                                   (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3523                                    rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
3524                         netdev_WARN(efx->net_dev,
3525                                     "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3526                                     EFX_QWORD_FMT "\n",
3527                                     EFX_QWORD_VAL(*event));
3528                 if (!efx->loopback_selftest)
3529                         channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3530                 return 0;
3531         }
3532
3533         WARN_ON(!handled); /* No error bits were recognised */
3534         return 0;
3535 }
3536
3537 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3538                                     const efx_qword_t *event)
3539 {
3540         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3541         unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3542         unsigned int n_descs, n_packets, i;
3543         struct efx_nic *efx = channel->efx;
3544         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3545         struct efx_rx_queue *rx_queue;
3546         efx_qword_t errors;
3547         bool rx_cont;
3548         u16 flags = 0;
3549
3550         if (unlikely(READ_ONCE(efx->reset_pending)))
3551                 return 0;
3552
3553         /* Basic packet information */
3554         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3555         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3556         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3557         rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3558         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
3559         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3560         rx_encap_hdr =
3561                 nic_data->datapath_caps &
3562                         (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3563                 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3564                 ESE_EZ_ENCAP_HDR_NONE;
3565
3566         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3567                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3568                             EFX_QWORD_FMT "\n",
3569                             EFX_QWORD_VAL(*event));
3570
3571         rx_queue = efx_channel_get_rx_queue(channel);
3572
3573         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3574                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3575
3576         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3577                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3578
3579         if (n_descs != rx_queue->scatter_n + 1) {
3580                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3581
3582                 /* detect rx abort */
3583                 if (unlikely(n_descs == rx_queue->scatter_n)) {
3584                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3585                                 netdev_WARN(efx->net_dev,
3586                                             "invalid RX abort: scatter_n=%u event="
3587                                             EFX_QWORD_FMT "\n",
3588                                             rx_queue->scatter_n,
3589                                             EFX_QWORD_VAL(*event));
3590                         efx_ef10_handle_rx_abort(rx_queue);
3591                         return 0;
3592                 }
3593
3594                 /* Check that RX completion merging is valid, i.e.
3595                  * the current firmware supports it and this is a
3596                  * non-scattered packet.
3597                  */
3598                 if (!(nic_data->datapath_caps &
3599                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3600                     rx_queue->scatter_n != 0 || rx_cont) {
3601                         efx_ef10_handle_rx_bad_lbits(
3602                                 rx_queue, next_ptr_lbits,
3603                                 (rx_queue->removed_count +
3604                                  rx_queue->scatter_n + 1) &
3605                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3606                         return 0;
3607                 }
3608
3609                 /* Merged completion for multiple non-scattered packets */
3610                 rx_queue->scatter_n = 1;
3611                 rx_queue->scatter_len = 0;
3612                 n_packets = n_descs;
3613                 ++channel->n_rx_merge_events;
3614                 channel->n_rx_merge_packets += n_packets;
3615                 flags |= EFX_RX_PKT_PREFIX_LEN;
3616         } else {
3617                 ++rx_queue->scatter_n;
3618                 rx_queue->scatter_len += rx_bytes;
3619                 if (rx_cont)
3620                         return 0;
3621                 n_packets = 1;
3622         }
3623
3624         EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3625                                      ESF_DZ_RX_IPCKSUM_ERR, 1,
3626                                      ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3627                                      ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3628                                      ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3629         EFX_AND_QWORD(errors, *event, errors);
3630         if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3631                 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3632                                                          rx_encap_hdr,
3633                                                          rx_l3_class, rx_l4_class,
3634                                                          event);
3635         } else {
3636                 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3637                               rx_l4_class == ESE_FZ_L4_CLASS_UDP;
3638
3639                 switch (rx_encap_hdr) {
3640                 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3641                         flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3642                         if (tcpudp)
3643                                 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3644                         break;
3645                 case ESE_EZ_ENCAP_HDR_GRE:
3646                 case ESE_EZ_ENCAP_HDR_NONE:
3647                         if (tcpudp)
3648                                 flags |= EFX_RX_PKT_CSUMMED;
3649                         break;
3650                 default:
3651                         netdev_WARN(efx->net_dev,
3652                                     "unknown encapsulation type: event="
3653                                     EFX_QWORD_FMT "\n",
3654                                     EFX_QWORD_VAL(*event));
3655                 }
3656         }
3657
3658         if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
3659                 flags |= EFX_RX_PKT_TCP;
3660
3661         channel->irq_mod_score += 2 * n_packets;
3662
3663         /* Handle received packet(s) */
3664         for (i = 0; i < n_packets; i++) {
3665                 efx_rx_packet(rx_queue,
3666                               rx_queue->removed_count & rx_queue->ptr_mask,
3667                               rx_queue->scatter_n, rx_queue->scatter_len,
3668                               flags);
3669                 rx_queue->removed_count += rx_queue->scatter_n;
3670         }
3671
3672         rx_queue->scatter_n = 0;
3673         rx_queue->scatter_len = 0;
3674
3675         return n_packets;
3676 }
3677
3678 static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
3679 {
3680         u32 tstamp;
3681
3682         tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
3683         tstamp <<= 16;
3684         tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
3685
3686         return tstamp;
3687 }
3688
3689 static void
3690 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3691 {
3692         struct efx_nic *efx = channel->efx;
3693         struct efx_tx_queue *tx_queue;
3694         unsigned int tx_ev_desc_ptr;
3695         unsigned int tx_ev_q_label;
3696         unsigned int tx_ev_type;
3697         u64 ts_part;
3698
3699         if (unlikely(READ_ONCE(efx->reset_pending)))
3700                 return;
3701
3702         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3703                 return;
3704
3705         /* Get the transmit queue */
3706         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3707         tx_queue = efx_channel_get_tx_queue(channel,
3708                                             tx_ev_q_label % EFX_TXQ_TYPES);
3709
3710         if (!tx_queue->timestamping) {
3711                 /* Transmit completion */
3712                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3713                 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3714                 return;
3715         }
3716
3717         /* Transmit timestamps are only available for 8XXX series. They result
3718          * in three events per packet. These occur in order, and are:
3719          *  - the normal completion event
3720          *  - the low part of the timestamp
3721          *  - the high part of the timestamp
3722          *
3723          * Each part of the timestamp is itself split across two 16 bit
3724          * fields in the event.
3725          */
3726         tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
3727
3728         switch (tx_ev_type) {
3729         case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3730                 /* In case of Queue flush or FLR, we might have received
3731                  * the previous TX completion event but not the Timestamp
3732                  * events.
3733                  */
3734                 if (tx_queue->completed_desc_ptr != tx_queue->ptr_mask)
3735                         efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3736
3737                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event,
3738                                                  ESF_DZ_TX_DESCR_INDX);
3739                 tx_queue->completed_desc_ptr =
3740                                         tx_ev_desc_ptr & tx_queue->ptr_mask;
3741                 break;
3742
3743         case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
3744                 ts_part = efx_ef10_extract_event_ts(event);
3745                 tx_queue->completed_timestamp_minor = ts_part;
3746                 break;
3747
3748         case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
3749                 ts_part = efx_ef10_extract_event_ts(event);
3750                 tx_queue->completed_timestamp_major = ts_part;
3751
3752                 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3753                 tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
3754                 break;
3755
3756         default:
3757                 netif_err(efx, hw, efx->net_dev,
3758                           "channel %d unknown tx event type %d (data "
3759                           EFX_QWORD_FMT ")\n",
3760                           channel->channel, tx_ev_type,
3761                           EFX_QWORD_VAL(*event));
3762                 break;
3763         }
3764 }
3765
3766 static void
3767 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3768 {
3769         struct efx_nic *efx = channel->efx;
3770         int subcode;
3771
3772         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3773
3774         switch (subcode) {
3775         case ESE_DZ_DRV_TIMER_EV:
3776         case ESE_DZ_DRV_WAKE_UP_EV:
3777                 break;
3778         case ESE_DZ_DRV_START_UP_EV:
3779                 /* event queue init complete. ok. */
3780                 break;
3781         default:
3782                 netif_err(efx, hw, efx->net_dev,
3783                           "channel %d unknown driver event type %d"
3784                           " (data " EFX_QWORD_FMT ")\n",
3785                           channel->channel, subcode,
3786                           EFX_QWORD_VAL(*event));
3787
3788         }
3789 }
3790
3791 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3792                                                    efx_qword_t *event)
3793 {
3794         struct efx_nic *efx = channel->efx;
3795         u32 subcode;
3796
3797         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3798
3799         switch (subcode) {
3800         case EFX_EF10_TEST:
3801                 channel->event_test_cpu = raw_smp_processor_id();
3802                 break;
3803         case EFX_EF10_REFILL:
3804                 /* The queue must be empty, so we won't receive any rx
3805                  * events, so efx_process_channel() won't refill the
3806                  * queue. Refill it here
3807                  */
3808                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3809                 break;
3810         default:
3811                 netif_err(efx, hw, efx->net_dev,
3812                           "channel %d unknown driver event type %u"
3813                           " (data " EFX_QWORD_FMT ")\n",
3814                           channel->channel, (unsigned) subcode,
3815                           EFX_QWORD_VAL(*event));
3816         }
3817 }
3818
3819 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3820 {
3821         struct efx_nic *efx = channel->efx;
3822         efx_qword_t event, *p_event;
3823         unsigned int read_ptr;
3824         int ev_code;
3825         int spent = 0;
3826
3827         if (quota <= 0)
3828                 return spent;
3829
3830         read_ptr = channel->eventq_read_ptr;
3831
3832         for (;;) {
3833                 p_event = efx_event(channel, read_ptr);
3834                 event = *p_event;
3835
3836                 if (!efx_event_present(&event))
3837                         break;
3838
3839                 EFX_SET_QWORD(*p_event);
3840
3841                 ++read_ptr;
3842
3843                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3844
3845                 netif_vdbg(efx, drv, efx->net_dev,
3846                            "processing event on %d " EFX_QWORD_FMT "\n",
3847                            channel->channel, EFX_QWORD_VAL(event));
3848
3849                 switch (ev_code) {
3850                 case ESE_DZ_EV_CODE_MCDI_EV:
3851                         efx_mcdi_process_event(channel, &event);
3852                         break;
3853                 case ESE_DZ_EV_CODE_RX_EV:
3854                         spent += efx_ef10_handle_rx_event(channel, &event);
3855                         if (spent >= quota) {
3856                                 /* XXX can we split a merged event to
3857                                  * avoid going over-quota?
3858                                  */
3859                                 spent = quota;
3860                                 goto out;
3861                         }
3862                         break;
3863                 case ESE_DZ_EV_CODE_TX_EV:
3864                         efx_ef10_handle_tx_event(channel, &event);
3865                         break;
3866                 case ESE_DZ_EV_CODE_DRIVER_EV:
3867                         efx_ef10_handle_driver_event(channel, &event);
3868                         if (++spent == quota)
3869                                 goto out;
3870                         break;
3871                 case EFX_EF10_DRVGEN_EV:
3872                         efx_ef10_handle_driver_generated_event(channel, &event);
3873                         break;
3874                 default:
3875                         netif_err(efx, hw, efx->net_dev,
3876                                   "channel %d unknown event type %d"
3877                                   " (data " EFX_QWORD_FMT ")\n",
3878                                   channel->channel, ev_code,
3879                                   EFX_QWORD_VAL(event));
3880                 }
3881         }
3882
3883 out:
3884         channel->eventq_read_ptr = read_ptr;
3885         return spent;
3886 }
3887
3888 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3889 {
3890         struct efx_nic *efx = channel->efx;
3891         efx_dword_t rptr;
3892
3893         if (EFX_EF10_WORKAROUND_35388(efx)) {
3894                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3895                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3896                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3897                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3898
3899                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3900                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3901                                      ERF_DD_EVQ_IND_RPTR,
3902                                      (channel->eventq_read_ptr &
3903                                       channel->eventq_mask) >>
3904                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3905                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3906                                 channel->channel);
3907                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3908                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3909                                      ERF_DD_EVQ_IND_RPTR,
3910                                      channel->eventq_read_ptr &
3911                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3912                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3913                                 channel->channel);
3914         } else {
3915                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3916                                      channel->eventq_read_ptr &
3917                                      channel->eventq_mask);
3918                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3919         }
3920 }
3921
3922 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3923 {
3924         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3925         struct efx_nic *efx = channel->efx;
3926         efx_qword_t event;
3927         int rc;
3928
3929         EFX_POPULATE_QWORD_2(event,
3930                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3931                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3932
3933         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3934
3935         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3936          * already swapped the data to little-endian order.
3937          */
3938         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3939                sizeof(efx_qword_t));
3940
3941         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3942                           NULL, 0, NULL);
3943         if (rc != 0)
3944                 goto fail;
3945
3946         return;
3947
3948 fail:
3949         WARN_ON(true);
3950         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3951 }
3952
3953 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3954 {
3955         if (atomic_dec_and_test(&efx->active_queues))
3956                 wake_up(&efx->flush_wq);
3957
3958         WARN_ON(atomic_read(&efx->active_queues) < 0);
3959 }
3960
3961 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3962 {
3963         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3964         struct efx_channel *channel;
3965         struct efx_tx_queue *tx_queue;
3966         struct efx_rx_queue *rx_queue;
3967         int pending;
3968
3969         /* If the MC has just rebooted, the TX/RX queues will have already been
3970          * torn down, but efx->active_queues needs to be set to zero.
3971          */
3972         if (nic_data->must_realloc_vis) {
3973                 atomic_set(&efx->active_queues, 0);
3974                 return 0;
3975         }
3976
3977         /* Do not attempt to write to the NIC during EEH recovery */
3978         if (efx->state != STATE_RECOVERY) {
3979                 efx_for_each_channel(channel, efx) {
3980                         efx_for_each_channel_rx_queue(rx_queue, channel)
3981                                 efx_ef10_rx_fini(rx_queue);
3982                         efx_for_each_channel_tx_queue(tx_queue, channel)
3983                                 efx_ef10_tx_fini(tx_queue);
3984                 }
3985
3986                 wait_event_timeout(efx->flush_wq,
3987                                    atomic_read(&efx->active_queues) == 0,
3988                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3989                 pending = atomic_read(&efx->active_queues);
3990                 if (pending) {
3991                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3992                                   pending);
3993                         return -ETIMEDOUT;
3994                 }
3995         }
3996
3997         return 0;
3998 }
3999
4000 static void efx_ef10_prepare_flr(struct efx_nic *efx)
4001 {
4002         atomic_set(&efx->active_queues, 0);
4003 }
4004
4005 /* Decide whether a filter should be exclusive or else should allow
4006  * delivery to additional recipients.  Currently we decide that
4007  * filters for specific local unicast MAC and IP addresses are
4008  * exclusive.
4009  */
4010 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
4011 {
4012         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
4013             !is_multicast_ether_addr(spec->loc_mac))
4014                 return true;
4015
4016         if ((spec->match_flags &
4017              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
4018             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
4019                 if (spec->ether_type == htons(ETH_P_IP) &&
4020                     !ipv4_is_multicast(spec->loc_host[0]))
4021                         return true;
4022                 if (spec->ether_type == htons(ETH_P_IPV6) &&
4023                     ((const u8 *)spec->loc_host)[0] != 0xff)
4024                         return true;
4025         }
4026
4027         return false;
4028 }
4029
4030 static struct efx_filter_spec *
4031 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
4032                            unsigned int filter_idx)
4033 {
4034         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
4035                                           ~EFX_EF10_FILTER_FLAGS);
4036 }
4037
4038 static unsigned int
4039 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
4040                            unsigned int filter_idx)
4041 {
4042         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
4043 }
4044
4045 static void
4046 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
4047                           unsigned int filter_idx,
4048                           const struct efx_filter_spec *spec,
4049                           unsigned int flags)
4050 {
4051         table->entry[filter_idx].spec = (unsigned long)spec | flags;
4052 }
4053
4054 static void
4055 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
4056                                            const struct efx_filter_spec *spec,
4057                                            efx_dword_t *inbuf)
4058 {
4059         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4060         u32 match_fields = 0, uc_match, mc_match;
4061
4062         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4063                        efx_ef10_filter_is_exclusive(spec) ?
4064                        MC_CMD_FILTER_OP_IN_OP_INSERT :
4065                        MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
4066
4067         /* Convert match flags and values.  Unlike almost
4068          * everything else in MCDI, these fields are in
4069          * network byte order.
4070          */
4071 #define COPY_VALUE(value, mcdi_field)                                        \
4072         do {                                                         \
4073                 match_fields |=                                      \
4074                         1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
4075                         mcdi_field ## _LBN;                          \
4076                 BUILD_BUG_ON(                                        \
4077                         MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
4078                         sizeof(value));                              \
4079                 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
4080                        &value, sizeof(value));                       \
4081         } while (0)
4082 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
4083         if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
4084                 COPY_VALUE(spec->gen_field, mcdi_field);             \
4085         }
4086         /* Handle encap filters first.  They will always be mismatch
4087          * (unknown UC or MC) filters
4088          */
4089         if (encap_type) {
4090                 /* ether_type and outer_ip_proto need to be variables
4091                  * because COPY_VALUE wants to memcpy them
4092                  */
4093                 __be16 ether_type =
4094                         htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
4095                               ETH_P_IPV6 : ETH_P_IP);
4096                 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
4097                 u8 outer_ip_proto;
4098
4099                 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
4100                 case EFX_ENCAP_TYPE_VXLAN:
4101                         vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
4102                         /* fallthrough */
4103                 case EFX_ENCAP_TYPE_GENEVE:
4104                         COPY_VALUE(ether_type, ETHER_TYPE);
4105                         outer_ip_proto = IPPROTO_UDP;
4106                         COPY_VALUE(outer_ip_proto, IP_PROTO);
4107                         /* We always need to set the type field, even
4108                          * though we're not matching on the TNI.
4109                          */
4110                         MCDI_POPULATE_DWORD_1(inbuf,
4111                                 FILTER_OP_EXT_IN_VNI_OR_VSID,
4112                                 FILTER_OP_EXT_IN_VNI_TYPE,
4113                                 vni_type);
4114                         break;
4115                 case EFX_ENCAP_TYPE_NVGRE:
4116                         COPY_VALUE(ether_type, ETHER_TYPE);
4117                         outer_ip_proto = IPPROTO_GRE;
4118                         COPY_VALUE(outer_ip_proto, IP_PROTO);
4119                         break;
4120                 default:
4121                         WARN_ON(1);
4122                 }
4123
4124                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4125                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4126         } else {
4127                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4128                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4129         }
4130
4131         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
4132                 match_fields |=
4133                         is_multicast_ether_addr(spec->loc_mac) ?
4134                         1 << mc_match :
4135                         1 << uc_match;
4136         COPY_FIELD(REM_HOST, rem_host, SRC_IP);
4137         COPY_FIELD(LOC_HOST, loc_host, DST_IP);
4138         COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
4139         COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
4140         COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
4141         COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
4142         COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
4143         COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
4144         COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
4145         COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
4146 #undef COPY_FIELD
4147 #undef COPY_VALUE
4148         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
4149                        match_fields);
4150 }
4151
4152 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
4153                                       const struct efx_filter_spec *spec,
4154                                       efx_dword_t *inbuf, u64 handle,
4155                                       struct efx_rss_context *ctx,
4156                                       bool replacing)
4157 {
4158         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4159         u32 flags = spec->flags;
4160
4161         memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
4162
4163         /* If RSS filter, caller better have given us an RSS context */
4164         if (flags & EFX_FILTER_FLAG_RX_RSS) {
4165                 /* We don't have the ability to return an error, so we'll just
4166                  * log a warning and disable RSS for the filter.
4167                  */
4168                 if (WARN_ON_ONCE(!ctx))
4169                         flags &= ~EFX_FILTER_FLAG_RX_RSS;
4170                 else if (WARN_ON_ONCE(ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID))
4171                         flags &= ~EFX_FILTER_FLAG_RX_RSS;
4172         }
4173
4174         if (replacing) {
4175                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4176                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
4177                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
4178         } else {
4179                 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
4180         }
4181
4182         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
4183         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
4184                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4185                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
4186                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
4187         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
4188         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
4189                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
4190         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
4191                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4192                        0 : spec->dmaq_id);
4193         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
4194                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
4195                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
4196                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
4197         if (flags & EFX_FILTER_FLAG_RX_RSS)
4198                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, ctx->context_id);
4199 }
4200
4201 static int efx_ef10_filter_push(struct efx_nic *efx,
4202                                 const struct efx_filter_spec *spec, u64 *handle,
4203                                 struct efx_rss_context *ctx, bool replacing)
4204 {
4205         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4206         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
4207         int rc;
4208
4209         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, ctx, replacing);
4210         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4211                           outbuf, sizeof(outbuf), NULL);
4212         if (rc == 0)
4213                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4214         if (rc == -ENOSPC)
4215                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
4216         return rc;
4217 }
4218
4219 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
4220 {
4221         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4222         unsigned int match_flags = spec->match_flags;
4223         unsigned int uc_match, mc_match;
4224         u32 mcdi_flags = 0;
4225
4226 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) {          \
4227                 unsigned int  old_match_flags = match_flags;            \
4228                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
4229                 if (match_flags != old_match_flags)                     \
4230                         mcdi_flags |=                                   \
4231                                 (1 << ((encap) ?                        \
4232                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4233                                        mcdi_field ## _LBN :             \
4234                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4235                                        mcdi_field ## _LBN));            \
4236         }
4237         /* inner or outer based on encap type */
4238         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4239         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4240         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4241         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4242         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4243         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4244         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4245         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4246         /* always outer */
4247         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4248         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
4249 #undef MAP_FILTER_TO_MCDI_FLAG
4250
4251         /* special handling for encap type, and mismatch */
4252         if (encap_type) {
4253                 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4254                 mcdi_flags |=
4255                         (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4256                 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4257
4258                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4259                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4260         } else {
4261                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4262                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4263         }
4264
4265         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4266                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4267                 mcdi_flags |=
4268                         is_multicast_ether_addr(spec->loc_mac) ?
4269                         1 << mc_match :
4270                         1 << uc_match;
4271         }
4272
4273         /* Did we map them all? */
4274         WARN_ON_ONCE(match_flags);
4275
4276         return mcdi_flags;
4277 }
4278
4279 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4280                                const struct efx_filter_spec *spec)
4281 {
4282         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4283         unsigned int match_pri;
4284
4285         for (match_pri = 0;
4286              match_pri < table->rx_match_count;
4287              match_pri++)
4288                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4289                         return match_pri;
4290
4291         return -EPROTONOSUPPORT;
4292 }
4293
4294 static s32 efx_ef10_filter_insert_locked(struct efx_nic *efx,
4295                                          struct efx_filter_spec *spec,
4296                                          bool replace_equal)
4297 {
4298         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4299         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4300         struct efx_ef10_filter_table *table;
4301         struct efx_filter_spec *saved_spec;
4302         struct efx_rss_context *ctx = NULL;
4303         unsigned int match_pri, hash;
4304         unsigned int priv_flags;
4305         bool rss_locked = false;
4306         bool replacing = false;
4307         unsigned int depth, i;
4308         int ins_index = -1;
4309         DEFINE_WAIT(wait);
4310         bool is_mc_recip;
4311         s32 rc;
4312
4313         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4314         table = efx->filter_state;
4315         down_write(&table->lock);
4316
4317         /* For now, only support RX filters */
4318         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4319             EFX_FILTER_FLAG_RX) {
4320                 rc = -EINVAL;
4321                 goto out_unlock;
4322         }
4323
4324         rc = efx_ef10_filter_pri(table, spec);
4325         if (rc < 0)
4326                 goto out_unlock;
4327         match_pri = rc;
4328
4329         hash = efx_filter_spec_hash(spec);
4330         is_mc_recip = efx_filter_is_mc_recipient(spec);
4331         if (is_mc_recip)
4332                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4333
4334         if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
4335                 mutex_lock(&efx->rss_lock);
4336                 rss_locked = true;
4337                 if (spec->rss_context)
4338                         ctx = efx_find_rss_context_entry(efx, spec->rss_context);
4339                 else
4340                         ctx = &efx->rss_context;
4341                 if (!ctx) {
4342                         rc = -ENOENT;
4343                         goto out_unlock;
4344                 }
4345                 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
4346                         rc = -EOPNOTSUPP;
4347                         goto out_unlock;
4348                 }
4349         }
4350
4351         /* Find any existing filters with the same match tuple or
4352          * else a free slot to insert at.
4353          */
4354         for (depth = 1; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4355                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4356                 saved_spec = efx_ef10_filter_entry_spec(table, i);
4357
4358                 if (!saved_spec) {
4359                         if (ins_index < 0)
4360                                 ins_index = i;
4361                 } else if (efx_filter_spec_equal(spec, saved_spec)) {
4362                         if (spec->priority < saved_spec->priority &&
4363                             spec->priority != EFX_FILTER_PRI_AUTO) {
4364                                 rc = -EPERM;
4365                                 goto out_unlock;
4366                         }
4367                         if (!is_mc_recip) {
4368                                 /* This is the only one */
4369                                 if (spec->priority ==
4370                                     saved_spec->priority &&
4371                                     !replace_equal) {
4372                                         rc = -EEXIST;
4373                                         goto out_unlock;
4374                                 }
4375                                 ins_index = i;
4376                                 break;
4377                         } else if (spec->priority >
4378                                    saved_spec->priority ||
4379                                    (spec->priority ==
4380                                     saved_spec->priority &&
4381                                     replace_equal)) {
4382                                 if (ins_index < 0)
4383                                         ins_index = i;
4384                                 else
4385                                         __set_bit(depth, mc_rem_map);
4386                         }
4387                 }
4388         }
4389
4390         /* Once we reach the maximum search depth, use the first suitable
4391          * slot, or return -EBUSY if there was none
4392          */
4393         if (ins_index < 0) {
4394                 rc = -EBUSY;
4395                 goto out_unlock;
4396         }
4397
4398         /* Create a software table entry if necessary. */
4399         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4400         if (saved_spec) {
4401                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4402                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4403                         /* Just make sure it won't be removed */
4404                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4405                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4406                         table->entry[ins_index].spec &=
4407                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4408                         rc = ins_index;
4409                         goto out_unlock;
4410                 }
4411                 replacing = true;
4412                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4413         } else {
4414                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4415                 if (!saved_spec) {
4416                         rc = -ENOMEM;
4417                         goto out_unlock;
4418                 }
4419                 *saved_spec = *spec;
4420                 priv_flags = 0;
4421         }
4422         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4423
4424         /* Actually insert the filter on the HW */
4425         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4426                                   ctx, replacing);
4427
4428         if (rc == -EINVAL && nic_data->must_realloc_vis)
4429                 /* The MC rebooted under us, causing it to reject our filter
4430                  * insertion as pointing to an invalid VI (spec->dmaq_id).
4431                  */
4432                 rc = -EAGAIN;
4433
4434         /* Finalise the software table entry */
4435         if (rc == 0) {
4436                 if (replacing) {
4437                         /* Update the fields that may differ */
4438                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4439                                 saved_spec->flags |=
4440                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
4441                         saved_spec->priority = spec->priority;
4442                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4443                         saved_spec->flags |= spec->flags;
4444                         saved_spec->rss_context = spec->rss_context;
4445                         saved_spec->dmaq_id = spec->dmaq_id;
4446                 }
4447         } else if (!replacing) {
4448                 kfree(saved_spec);
4449                 saved_spec = NULL;
4450         } else {
4451                 /* We failed to replace, so the old filter is still present.
4452                  * Roll back the software table to reflect this.  In fact the
4453                  * efx_ef10_filter_set_entry() call below will do the right
4454                  * thing, so nothing extra is needed here.
4455                  */
4456         }
4457         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4458
4459         /* Remove and finalise entries for lower-priority multicast
4460          * recipients
4461          */
4462         if (is_mc_recip) {
4463                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4464                 unsigned int depth, i;
4465
4466                 memset(inbuf, 0, sizeof(inbuf));
4467
4468                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4469                         if (!test_bit(depth, mc_rem_map))
4470                                 continue;
4471
4472                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4473                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4474                         priv_flags = efx_ef10_filter_entry_flags(table, i);
4475
4476                         if (rc == 0) {
4477                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4478                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4479                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4480                                                table->entry[i].handle);
4481                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4482                                                   inbuf, sizeof(inbuf),
4483                                                   NULL, 0, NULL);
4484                         }
4485
4486                         if (rc == 0) {
4487                                 kfree(saved_spec);
4488                                 saved_spec = NULL;
4489                                 priv_flags = 0;
4490                         }
4491                         efx_ef10_filter_set_entry(table, i, saved_spec,
4492                                                   priv_flags);
4493                 }
4494         }
4495
4496         /* If successful, return the inserted filter ID */
4497         if (rc == 0)
4498                 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4499
4500 out_unlock:
4501         if (rss_locked)
4502                 mutex_unlock(&efx->rss_lock);
4503         up_write(&table->lock);
4504         return rc;
4505 }
4506
4507 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4508                                   struct efx_filter_spec *spec,
4509                                   bool replace_equal)
4510 {
4511         s32 ret;
4512
4513         down_read(&efx->filter_sem);
4514         ret = efx_ef10_filter_insert_locked(efx, spec, replace_equal);
4515         up_read(&efx->filter_sem);
4516
4517         return ret;
4518 }
4519
4520 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4521 {
4522         /* no need to do anything here on EF10 */
4523 }
4524
4525 /* Remove a filter.
4526  * If !by_index, remove by ID
4527  * If by_index, remove by index
4528  * Filter ID may come from userland and must be range-checked.
4529  * Caller must hold efx->filter_sem for read, and efx->filter_state->lock
4530  * for write.
4531  */
4532 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4533                                            unsigned int priority_mask,
4534                                            u32 filter_id, bool by_index)
4535 {
4536         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4537         struct efx_ef10_filter_table *table = efx->filter_state;
4538         MCDI_DECLARE_BUF(inbuf,
4539                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4540                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4541         struct efx_filter_spec *spec;
4542         DEFINE_WAIT(wait);
4543         int rc;
4544
4545         spec = efx_ef10_filter_entry_spec(table, filter_idx);
4546         if (!spec ||
4547             (!by_index &&
4548              efx_ef10_filter_pri(table, spec) !=
4549              efx_ef10_filter_get_unsafe_pri(filter_id)))
4550                 return -ENOENT;
4551
4552         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4553             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4554                 /* Just remove flags */
4555                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4556                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4557                 return 0;
4558         }
4559
4560         if (!(priority_mask & (1U << spec->priority)))
4561                 return -ENOENT;
4562
4563         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4564                 /* Reset to an automatic filter */
4565
4566                 struct efx_filter_spec new_spec = *spec;
4567
4568                 new_spec.priority = EFX_FILTER_PRI_AUTO;
4569                 new_spec.flags = (EFX_FILTER_FLAG_RX |
4570                                   (efx_rss_active(&efx->rss_context) ?
4571                                    EFX_FILTER_FLAG_RX_RSS : 0));
4572                 new_spec.dmaq_id = 0;
4573                 new_spec.rss_context = 0;
4574                 rc = efx_ef10_filter_push(efx, &new_spec,
4575                                           &table->entry[filter_idx].handle,
4576                                           &efx->rss_context,
4577                                           true);
4578
4579                 if (rc == 0)
4580                         *spec = new_spec;
4581         } else {
4582                 /* Really remove the filter */
4583
4584                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4585                                efx_ef10_filter_is_exclusive(spec) ?
4586                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4587                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4588                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4589                                table->entry[filter_idx].handle);
4590                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4591                                         inbuf, sizeof(inbuf), NULL, 0, NULL);
4592
4593                 if ((rc == 0) || (rc == -ENOENT)) {
4594                         /* Filter removed OK or didn't actually exist */
4595                         kfree(spec);
4596                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4597                 } else {
4598                         efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4599                                                MC_CMD_FILTER_OP_EXT_IN_LEN,
4600                                                NULL, 0, rc);
4601                 }
4602         }
4603
4604         return rc;
4605 }
4606
4607 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4608                                        enum efx_filter_priority priority,
4609                                        u32 filter_id)
4610 {
4611         struct efx_ef10_filter_table *table;
4612         int rc;
4613
4614         down_read(&efx->filter_sem);
4615         table = efx->filter_state;
4616         down_write(&table->lock);
4617         rc = efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4618                                              false);
4619         up_write(&table->lock);
4620         up_read(&efx->filter_sem);
4621         return rc;
4622 }
4623
4624 /* Caller must hold efx->filter_sem for read */
4625 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4626                                           enum efx_filter_priority priority,
4627                                           u32 filter_id)
4628 {
4629         struct efx_ef10_filter_table *table = efx->filter_state;
4630
4631         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4632                 return;
4633
4634         down_write(&table->lock);
4635         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4636                                         true);
4637         up_write(&table->lock);
4638 }
4639
4640 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4641                                     enum efx_filter_priority priority,
4642                                     u32 filter_id, struct efx_filter_spec *spec)
4643 {
4644         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4645         const struct efx_filter_spec *saved_spec;
4646         struct efx_ef10_filter_table *table;
4647         int rc;
4648
4649         down_read(&efx->filter_sem);
4650         table = efx->filter_state;
4651         down_read(&table->lock);
4652         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4653         if (saved_spec && saved_spec->priority == priority &&
4654             efx_ef10_filter_pri(table, saved_spec) ==
4655             efx_ef10_filter_get_unsafe_pri(filter_id)) {
4656                 *spec = *saved_spec;
4657                 rc = 0;
4658         } else {
4659                 rc = -ENOENT;
4660         }
4661         up_read(&table->lock);
4662         up_read(&efx->filter_sem);
4663         return rc;
4664 }
4665
4666 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4667                                     enum efx_filter_priority priority)
4668 {
4669         struct efx_ef10_filter_table *table;
4670         unsigned int priority_mask;
4671         unsigned int i;
4672         int rc;
4673
4674         priority_mask = (((1U << (priority + 1)) - 1) &
4675                          ~(1U << EFX_FILTER_PRI_AUTO));
4676
4677         down_read(&efx->filter_sem);
4678         table = efx->filter_state;
4679         down_write(&table->lock);
4680         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4681                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4682                                                      i, true);
4683                 if (rc && rc != -ENOENT)
4684                         break;
4685                 rc = 0;
4686         }
4687
4688         up_write(&table->lock);
4689         up_read(&efx->filter_sem);
4690         return rc;
4691 }
4692
4693 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4694                                          enum efx_filter_priority priority)
4695 {
4696         struct efx_ef10_filter_table *table;
4697         unsigned int filter_idx;
4698         s32 count = 0;
4699
4700         down_read(&efx->filter_sem);
4701         table = efx->filter_state;
4702         down_read(&table->lock);
4703         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4704                 if (table->entry[filter_idx].spec &&
4705                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4706                     priority)
4707                         ++count;
4708         }
4709         up_read(&table->lock);
4710         up_read(&efx->filter_sem);
4711         return count;
4712 }
4713
4714 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4715 {
4716         struct efx_ef10_filter_table *table = efx->filter_state;
4717
4718         return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4719 }
4720
4721 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4722                                       enum efx_filter_priority priority,
4723                                       u32 *buf, u32 size)
4724 {
4725         struct efx_ef10_filter_table *table;
4726         struct efx_filter_spec *spec;
4727         unsigned int filter_idx;
4728         s32 count = 0;
4729
4730         down_read(&efx->filter_sem);
4731         table = efx->filter_state;
4732         down_read(&table->lock);
4733
4734         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4735                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4736                 if (spec && spec->priority == priority) {
4737                         if (count == size) {
4738                                 count = -EMSGSIZE;
4739                                 break;
4740                         }
4741                         buf[count++] =
4742                                 efx_ef10_make_filter_id(
4743                                         efx_ef10_filter_pri(table, spec),
4744                                         filter_idx);
4745                 }
4746         }
4747         up_read(&table->lock);
4748         up_read(&efx->filter_sem);
4749         return count;
4750 }
4751
4752 #ifdef CONFIG_RFS_ACCEL
4753
4754 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4755                                            unsigned int filter_idx)
4756 {
4757         struct efx_filter_spec *spec, saved_spec;
4758         struct efx_ef10_filter_table *table;
4759         struct efx_arfs_rule *rule = NULL;
4760         bool ret = true, force = false;
4761         u16 arfs_id;
4762
4763         down_read(&efx->filter_sem);
4764         table = efx->filter_state;
4765         down_write(&table->lock);
4766         spec = efx_ef10_filter_entry_spec(table, filter_idx);
4767
4768         if (!spec || spec->priority != EFX_FILTER_PRI_HINT)
4769                 goto out_unlock;
4770
4771         spin_lock_bh(&efx->rps_hash_lock);
4772         if (!efx->rps_hash_table) {
4773                 /* In the absence of the table, we always return 0 to ARFS. */
4774                 arfs_id = 0;
4775         } else {
4776                 rule = efx_rps_hash_find(efx, spec);
4777                 if (!rule)
4778                         /* ARFS table doesn't know of this filter, so remove it */
4779                         goto expire;
4780                 arfs_id = rule->arfs_id;
4781                 ret = efx_rps_check_rule(rule, filter_idx, &force);
4782                 if (force)
4783                         goto expire;
4784                 if (!ret) {
4785                         spin_unlock_bh(&efx->rps_hash_lock);
4786                         goto out_unlock;
4787                 }
4788         }
4789         if (!rps_may_expire_flow(efx->net_dev, spec->dmaq_id, flow_id, arfs_id))
4790                 ret = false;
4791         else if (rule)
4792                 rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
4793 expire:
4794         saved_spec = *spec; /* remove operation will kfree spec */
4795         spin_unlock_bh(&efx->rps_hash_lock);
4796         /* At this point (since we dropped the lock), another thread might queue
4797          * up a fresh insertion request (but the actual insertion will be held
4798          * up by our possession of the filter table lock).  In that case, it
4799          * will set rule->filter_id to EFX_ARFS_FILTER_ID_PENDING, meaning that
4800          * the rule is not removed by efx_rps_hash_del() below.
4801          */
4802         if (ret)
4803                 ret = efx_ef10_filter_remove_internal(efx, 1U << spec->priority,
4804                                                       filter_idx, true) == 0;
4805         /* While we can't safely dereference rule (we dropped the lock), we can
4806          * still test it for NULL.
4807          */
4808         if (ret && rule) {
4809                 /* Expiring, so remove entry from ARFS table */
4810                 spin_lock_bh(&efx->rps_hash_lock);
4811                 efx_rps_hash_del(efx, &saved_spec);
4812                 spin_unlock_bh(&efx->rps_hash_lock);
4813         }
4814 out_unlock:
4815         up_write(&table->lock);
4816         up_read(&efx->filter_sem);
4817         return ret;
4818 }
4819
4820 #endif /* CONFIG_RFS_ACCEL */
4821
4822 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4823 {
4824         int match_flags = 0;
4825
4826 #define MAP_FLAG(gen_flag, mcdi_field) do {                             \
4827                 u32 old_mcdi_flags = mcdi_flags;                        \
4828                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##  \
4829                                      mcdi_field ## _LBN);               \
4830                 if (mcdi_flags != old_mcdi_flags)                       \
4831                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4832         } while (0)
4833
4834         if (encap) {
4835                 /* encap filters must specify encap type */
4836                 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4837                 /* and imply ethertype and ip proto */
4838                 mcdi_flags &=
4839                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4840                 mcdi_flags &=
4841                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4842                 /* VLAN tags refer to the outer packet */
4843                 MAP_FLAG(INNER_VID, INNER_VLAN);
4844                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4845                 /* everything else refers to the inner packet */
4846                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4847                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4848                 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4849                 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4850                 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4851                 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4852                 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4853                 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4854                 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4855                 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4856         } else {
4857                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4858                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4859                 MAP_FLAG(REM_HOST, SRC_IP);
4860                 MAP_FLAG(LOC_HOST, DST_IP);
4861                 MAP_FLAG(REM_MAC, SRC_MAC);
4862                 MAP_FLAG(REM_PORT, SRC_PORT);
4863                 MAP_FLAG(LOC_MAC, DST_MAC);
4864                 MAP_FLAG(LOC_PORT, DST_PORT);
4865                 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4866                 MAP_FLAG(INNER_VID, INNER_VLAN);
4867                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4868                 MAP_FLAG(IP_PROTO, IP_PROTO);
4869         }
4870 #undef MAP_FLAG
4871
4872         /* Did we map them all? */
4873         if (mcdi_flags)
4874                 return -EINVAL;
4875
4876         return match_flags;
4877 }
4878
4879 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4880 {
4881         struct efx_ef10_filter_table *table = efx->filter_state;
4882         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4883
4884         /* See comment in efx_ef10_filter_table_remove() */
4885         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4886                 return;
4887
4888         if (!table)
4889                 return;
4890
4891         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4892                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4893 }
4894
4895 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4896                                             bool encap,
4897                                             enum efx_filter_match_flags match_flags)
4898 {
4899         unsigned int match_pri;
4900         int mf;
4901
4902         for (match_pri = 0;
4903              match_pri < table->rx_match_count;
4904              match_pri++) {
4905                 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4906                                 table->rx_match_mcdi_flags[match_pri]);
4907                 if (mf == match_flags)
4908                         return true;
4909         }
4910
4911         return false;
4912 }
4913
4914 static int
4915 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4916                                     struct efx_ef10_filter_table *table,
4917                                     bool encap)
4918 {
4919         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4920         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4921         unsigned int pd_match_pri, pd_match_count;
4922         size_t outlen;
4923         int rc;
4924
4925         /* Find out which RX filter types are supported, and their priorities */
4926         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4927                        encap ?
4928                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4929                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4930         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4931                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4932                           &outlen);
4933         if (rc)
4934                 return rc;
4935
4936         pd_match_count = MCDI_VAR_ARRAY_LEN(
4937                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4938
4939         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4940                 u32 mcdi_flags =
4941                         MCDI_ARRAY_DWORD(
4942                                 outbuf,
4943                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4944                                 pd_match_pri);
4945                 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4946                 if (rc < 0) {
4947                         netif_dbg(efx, probe, efx->net_dev,
4948                                   "%s: fw flags %#x pri %u not supported in driver\n",
4949                                   __func__, mcdi_flags, pd_match_pri);
4950                 } else {
4951                         netif_dbg(efx, probe, efx->net_dev,
4952                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4953                                   __func__, mcdi_flags, pd_match_pri,
4954                                   rc, table->rx_match_count);
4955                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4956                         table->rx_match_count++;
4957                 }
4958         }
4959
4960         return 0;
4961 }
4962
4963 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4964 {
4965         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4966         struct net_device *net_dev = efx->net_dev;
4967         struct efx_ef10_filter_table *table;
4968         struct efx_ef10_vlan *vlan;
4969         int rc;
4970
4971         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4972                 return -EINVAL;
4973
4974         if (efx->filter_state) /* already probed */
4975                 return 0;
4976
4977         table = kzalloc(sizeof(*table), GFP_KERNEL);
4978         if (!table)
4979                 return -ENOMEM;
4980
4981         table->rx_match_count = 0;
4982         rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4983         if (rc)
4984                 goto fail;
4985         if (nic_data->datapath_caps &
4986                    (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4987                 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4988         if (rc)
4989                 goto fail;
4990         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4991             !(efx_ef10_filter_match_supported(table, false,
4992                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4993               efx_ef10_filter_match_supported(table, false,
4994                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4995                 netif_info(efx, probe, net_dev,
4996                            "VLAN filters are not supported in this firmware variant\n");
4997                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4998                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4999                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
5000         }
5001
5002         table->entry = vzalloc(array_size(HUNT_FILTER_TBL_ROWS,
5003                                           sizeof(*table->entry)));
5004         if (!table->entry) {
5005                 rc = -ENOMEM;
5006                 goto fail;
5007         }
5008
5009         table->mc_promisc_last = false;
5010         table->vlan_filter =
5011                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5012         INIT_LIST_HEAD(&table->vlan_list);
5013         init_rwsem(&table->lock);
5014
5015         efx->filter_state = table;
5016
5017         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
5018                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
5019                 if (rc)
5020                         goto fail_add_vlan;
5021         }
5022
5023         return 0;
5024
5025 fail_add_vlan:
5026         efx_ef10_filter_cleanup_vlans(efx);
5027         efx->filter_state = NULL;
5028 fail:
5029         kfree(table);
5030         return rc;
5031 }
5032
5033 /* Caller must hold efx->filter_sem for read if race against
5034  * efx_ef10_filter_table_remove() is possible
5035  */
5036 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
5037 {
5038         struct efx_ef10_filter_table *table = efx->filter_state;
5039         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5040         unsigned int invalid_filters = 0, failed = 0;
5041         struct efx_ef10_filter_vlan *vlan;
5042         struct efx_filter_spec *spec;
5043         struct efx_rss_context *ctx;
5044         unsigned int filter_idx;
5045         u32 mcdi_flags;
5046         int match_pri;
5047         int rc, i;
5048
5049         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5050
5051         if (!nic_data->must_restore_filters)
5052                 return;
5053
5054         if (!table)
5055                 return;
5056
5057         down_write(&table->lock);
5058         mutex_lock(&efx->rss_lock);
5059
5060         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5061                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5062                 if (!spec)
5063                         continue;
5064
5065                 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
5066                 match_pri = 0;
5067                 while (match_pri < table->rx_match_count &&
5068                        table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
5069                         ++match_pri;
5070                 if (match_pri >= table->rx_match_count) {
5071                         invalid_filters++;
5072                         goto not_restored;
5073                 }
5074                 if (spec->rss_context)
5075                         ctx = efx_find_rss_context_entry(efx, spec->rss_context);
5076                 else
5077                         ctx = &efx->rss_context;
5078                 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
5079                         if (!ctx) {
5080                                 netif_warn(efx, drv, efx->net_dev,
5081                                            "Warning: unable to restore a filter with nonexistent RSS context %u.\n",
5082                                            spec->rss_context);
5083                                 invalid_filters++;
5084                                 goto not_restored;
5085                         }
5086                         if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
5087                                 netif_warn(efx, drv, efx->net_dev,
5088                                            "Warning: unable to restore a filter with RSS context %u as it was not created.\n",
5089                                            spec->rss_context);
5090                                 invalid_filters++;
5091                                 goto not_restored;
5092                         }
5093                 }
5094
5095                 rc = efx_ef10_filter_push(efx, spec,
5096                                           &table->entry[filter_idx].handle,
5097                                           ctx, false);
5098                 if (rc)
5099                         failed++;
5100
5101                 if (rc) {
5102 not_restored:
5103                         list_for_each_entry(vlan, &table->vlan_list, list)
5104                                 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
5105                                         if (vlan->default_filters[i] == filter_idx)
5106                                                 vlan->default_filters[i] =
5107                                                         EFX_EF10_FILTER_ID_INVALID;
5108
5109                         kfree(spec);
5110                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
5111                 }
5112         }
5113
5114         mutex_unlock(&efx->rss_lock);
5115         up_write(&table->lock);
5116
5117         /* This can happen validly if the MC's capabilities have changed, so
5118          * is not an error.
5119          */
5120         if (invalid_filters)
5121                 netif_dbg(efx, drv, efx->net_dev,
5122                           "Did not restore %u filters that are now unsupported.\n",
5123                           invalid_filters);
5124
5125         if (failed)
5126                 netif_err(efx, hw, efx->net_dev,
5127                           "unable to restore %u filters\n", failed);
5128         else
5129                 nic_data->must_restore_filters = false;
5130 }
5131
5132 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5133 {
5134         struct efx_ef10_filter_table *table = efx->filter_state;
5135         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
5136         struct efx_filter_spec *spec;
5137         unsigned int filter_idx;
5138         int rc;
5139
5140         efx_ef10_filter_cleanup_vlans(efx);
5141         efx->filter_state = NULL;
5142         /* If we were called without locking, then it's not safe to free
5143          * the table as others might be using it.  So we just WARN, leak
5144          * the memory, and potentially get an inconsistent filter table
5145          * state.
5146          * This should never actually happen.
5147          */
5148         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5149                 return;
5150
5151         if (!table)
5152                 return;
5153
5154         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5155                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5156                 if (!spec)
5157                         continue;
5158
5159                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5160                                efx_ef10_filter_is_exclusive(spec) ?
5161                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
5162                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5163                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5164                                table->entry[filter_idx].handle);
5165                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5166                                         sizeof(inbuf), NULL, 0, NULL);
5167                 if (rc)
5168                         netif_info(efx, drv, efx->net_dev,
5169                                    "%s: filter %04x remove failed\n",
5170                                    __func__, filter_idx);
5171                 kfree(spec);
5172         }
5173
5174         vfree(table->entry);
5175         kfree(table);
5176 }
5177
5178 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5179 {
5180         struct efx_ef10_filter_table *table = efx->filter_state;
5181         unsigned int filter_idx;
5182
5183         efx_rwsem_assert_write_locked(&table->lock);
5184
5185         if (*id != EFX_EF10_FILTER_ID_INVALID) {
5186                 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5187                 if (!table->entry[filter_idx].spec)
5188                         netif_dbg(efx, drv, efx->net_dev,
5189                                   "marked null spec old %04x:%04x\n", *id,
5190                                   filter_idx);
5191                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5192                 *id = EFX_EF10_FILTER_ID_INVALID;
5193         }
5194 }
5195
5196 /* Mark old per-VLAN filters that may need to be removed */
5197 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5198                                            struct efx_ef10_filter_vlan *vlan)
5199 {
5200         struct efx_ef10_filter_table *table = efx->filter_state;
5201         unsigned int i;
5202
5203         for (i = 0; i < table->dev_uc_count; i++)
5204                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5205         for (i = 0; i < table->dev_mc_count; i++)
5206                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5207         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5208                 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5209 }
5210
5211 /* Mark old filters that may need to be removed.
5212  * Caller must hold efx->filter_sem for read if race against
5213  * efx_ef10_filter_table_remove() is possible
5214  */
5215 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5216 {
5217         struct efx_ef10_filter_table *table = efx->filter_state;
5218         struct efx_ef10_filter_vlan *vlan;
5219
5220         down_write(&table->lock);
5221         list_for_each_entry(vlan, &table->vlan_list, list)
5222                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5223         up_write(&table->lock);
5224 }
5225
5226 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5227 {
5228         struct efx_ef10_filter_table *table = efx->filter_state;
5229         struct net_device *net_dev = efx->net_dev;
5230         struct netdev_hw_addr *uc;
5231         unsigned int i;
5232
5233         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5234         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5235         i = 1;
5236         netdev_for_each_uc_addr(uc, net_dev) {
5237                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5238                         table->uc_promisc = true;
5239                         break;
5240                 }
5241                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5242                 i++;
5243         }
5244
5245         table->dev_uc_count = i;
5246 }
5247
5248 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5249 {
5250         struct efx_ef10_filter_table *table = efx->filter_state;
5251         struct net_device *net_dev = efx->net_dev;
5252         struct netdev_hw_addr *mc;
5253         unsigned int i;
5254
5255         table->mc_overflow = false;
5256         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5257
5258         i = 0;
5259         netdev_for_each_mc_addr(mc, net_dev) {
5260                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5261                         table->mc_promisc = true;
5262                         table->mc_overflow = true;
5263                         break;
5264                 }
5265                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5266                 i++;
5267         }
5268
5269         table->dev_mc_count = i;
5270 }
5271
5272 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5273                                             struct efx_ef10_filter_vlan *vlan,
5274                                             bool multicast, bool rollback)
5275 {
5276         struct efx_ef10_filter_table *table = efx->filter_state;
5277         struct efx_ef10_dev_addr *addr_list;
5278         enum efx_filter_flags filter_flags;
5279         struct efx_filter_spec spec;
5280         u8 baddr[ETH_ALEN];
5281         unsigned int i, j;
5282         int addr_count;
5283         u16 *ids;
5284         int rc;
5285
5286         if (multicast) {
5287                 addr_list = table->dev_mc_list;
5288                 addr_count = table->dev_mc_count;
5289                 ids = vlan->mc;
5290         } else {
5291                 addr_list = table->dev_uc_list;
5292                 addr_count = table->dev_uc_count;
5293                 ids = vlan->uc;
5294         }
5295
5296         filter_flags = efx_rss_active(&efx->rss_context) ? EFX_FILTER_FLAG_RX_RSS : 0;
5297
5298         /* Insert/renew filters */
5299         for (i = 0; i < addr_count; i++) {
5300                 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5301                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5302                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5303                 rc = efx_ef10_filter_insert_locked(efx, &spec, true);
5304                 if (rc < 0) {
5305                         if (rollback) {
5306                                 netif_info(efx, drv, efx->net_dev,
5307                                            "efx_ef10_filter_insert failed rc=%d\n",
5308                                            rc);
5309                                 /* Fall back to promiscuous */
5310                                 for (j = 0; j < i; j++) {
5311                                         efx_ef10_filter_remove_unsafe(
5312                                                 efx, EFX_FILTER_PRI_AUTO,
5313                                                 ids[j]);
5314                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
5315                                 }
5316                                 return rc;
5317                         } else {
5318                                 /* keep invalid ID, and carry on */
5319                         }
5320                 } else {
5321                         ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5322                 }
5323         }
5324
5325         if (multicast && rollback) {
5326                 /* Also need an Ethernet broadcast filter */
5327                 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5328                                      EFX_EF10_FILTER_ID_INVALID);
5329                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5330                 eth_broadcast_addr(baddr);
5331                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5332                 rc = efx_ef10_filter_insert_locked(efx, &spec, true);
5333                 if (rc < 0) {
5334                         netif_warn(efx, drv, efx->net_dev,
5335                                    "Broadcast filter insert failed rc=%d\n", rc);
5336                         /* Fall back to promiscuous */
5337                         for (j = 0; j < i; j++) {
5338                                 efx_ef10_filter_remove_unsafe(
5339                                         efx, EFX_FILTER_PRI_AUTO,
5340                                         ids[j]);
5341                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5342                         }
5343                         return rc;
5344                 } else {
5345                         vlan->default_filters[EFX_EF10_BCAST] =
5346                                 efx_ef10_filter_get_unsafe_id(rc);
5347                 }
5348         }
5349
5350         return 0;
5351 }
5352
5353 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5354                                       struct efx_ef10_filter_vlan *vlan,
5355                                       enum efx_encap_type encap_type,
5356                                       bool multicast, bool rollback)
5357 {
5358         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5359         enum efx_filter_flags filter_flags;
5360         struct efx_filter_spec spec;
5361         u8 baddr[ETH_ALEN];
5362         int rc;
5363         u16 *id;
5364
5365         filter_flags = efx_rss_active(&efx->rss_context) ? EFX_FILTER_FLAG_RX_RSS : 0;
5366
5367         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5368
5369         if (multicast)
5370                 efx_filter_set_mc_def(&spec);
5371         else
5372                 efx_filter_set_uc_def(&spec);
5373
5374         if (encap_type) {
5375                 if (nic_data->datapath_caps &
5376                     (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5377                         efx_filter_set_encap_type(&spec, encap_type);
5378                 else
5379                         /* don't insert encap filters on non-supporting
5380                          * platforms. ID will be left as INVALID.
5381                          */
5382                         return 0;
5383         }
5384
5385         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5386                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5387
5388         rc = efx_ef10_filter_insert_locked(efx, &spec, true);
5389         if (rc < 0) {
5390                 const char *um = multicast ? "Multicast" : "Unicast";
5391                 const char *encap_name = "";
5392                 const char *encap_ipv = "";
5393
5394                 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5395                     EFX_ENCAP_TYPE_VXLAN)
5396                         encap_name = "VXLAN ";
5397                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5398                          EFX_ENCAP_TYPE_NVGRE)
5399                         encap_name = "NVGRE ";
5400                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5401                          EFX_ENCAP_TYPE_GENEVE)
5402                         encap_name = "GENEVE ";
5403                 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5404                         encap_ipv = "IPv6 ";
5405                 else if (encap_type)
5406                         encap_ipv = "IPv4 ";
5407
5408                 /* unprivileged functions can't insert mismatch filters
5409                  * for encapsulated or unicast traffic, so downgrade
5410                  * those warnings to debug.
5411                  */
5412                 netif_cond_dbg(efx, drv, efx->net_dev,
5413                                rc == -EPERM && (encap_type || !multicast), warn,
5414                                "%s%s%s mismatch filter insert failed rc=%d\n",
5415                                encap_name, encap_ipv, um, rc);
5416         } else if (multicast) {
5417                 /* mapping from encap types to default filter IDs (multicast) */
5418                 static enum efx_ef10_default_filters map[] = {
5419                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5420                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5421                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5422                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5423                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5424                                 EFX_EF10_VXLAN6_MCDEF,
5425                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5426                                 EFX_EF10_NVGRE6_MCDEF,
5427                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5428                                 EFX_EF10_GENEVE6_MCDEF,
5429                 };
5430
5431                 /* quick bounds check (BCAST result impossible) */
5432                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5433                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5434                         WARN_ON(1);
5435                         return -EINVAL;
5436                 }
5437                 /* then follow map */
5438                 id = &vlan->default_filters[map[encap_type]];
5439
5440                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5441                 *id = efx_ef10_filter_get_unsafe_id(rc);
5442                 if (!nic_data->workaround_26807 && !encap_type) {
5443                         /* Also need an Ethernet broadcast filter */
5444                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5445                                            filter_flags, 0);
5446                         eth_broadcast_addr(baddr);
5447                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5448                         rc = efx_ef10_filter_insert_locked(efx, &spec, true);
5449                         if (rc < 0) {
5450                                 netif_warn(efx, drv, efx->net_dev,
5451                                            "Broadcast filter insert failed rc=%d\n",
5452                                            rc);
5453                                 if (rollback) {
5454                                         /* Roll back the mc_def filter */
5455                                         efx_ef10_filter_remove_unsafe(
5456                                                         efx, EFX_FILTER_PRI_AUTO,
5457                                                         *id);
5458                                         *id = EFX_EF10_FILTER_ID_INVALID;
5459                                         return rc;
5460                                 }
5461                         } else {
5462                                 EFX_WARN_ON_PARANOID(
5463                                         vlan->default_filters[EFX_EF10_BCAST] !=
5464                                         EFX_EF10_FILTER_ID_INVALID);
5465                                 vlan->default_filters[EFX_EF10_BCAST] =
5466                                         efx_ef10_filter_get_unsafe_id(rc);
5467                         }
5468                 }
5469                 rc = 0;
5470         } else {
5471                 /* mapping from encap types to default filter IDs (unicast) */
5472                 static enum efx_ef10_default_filters map[] = {
5473                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5474                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5475                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5476                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5477                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5478                                 EFX_EF10_VXLAN6_UCDEF,
5479                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5480                                 EFX_EF10_NVGRE6_UCDEF,
5481                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5482                                 EFX_EF10_GENEVE6_UCDEF,
5483                 };
5484
5485                 /* quick bounds check (BCAST result impossible) */
5486                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5487                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5488                         WARN_ON(1);
5489                         return -EINVAL;
5490                 }
5491                 /* then follow map */
5492                 id = &vlan->default_filters[map[encap_type]];
5493                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5494                 *id = rc;
5495                 rc = 0;
5496         }
5497         return rc;
5498 }
5499
5500 /* Remove filters that weren't renewed. */
5501 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5502 {
5503         struct efx_ef10_filter_table *table = efx->filter_state;
5504         int remove_failed = 0;
5505         int remove_noent = 0;
5506         int rc;
5507         int i;
5508
5509         down_write(&table->lock);
5510         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5511                 if (READ_ONCE(table->entry[i].spec) &
5512                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5513                         rc = efx_ef10_filter_remove_internal(efx,
5514                                         1U << EFX_FILTER_PRI_AUTO, i, true);
5515                         if (rc == -ENOENT)
5516                                 remove_noent++;
5517                         else if (rc)
5518                                 remove_failed++;
5519                 }
5520         }
5521         up_write(&table->lock);
5522
5523         if (remove_failed)
5524                 netif_info(efx, drv, efx->net_dev,
5525                            "%s: failed to remove %d filters\n",
5526                            __func__, remove_failed);
5527         if (remove_noent)
5528                 netif_info(efx, drv, efx->net_dev,
5529                            "%s: failed to remove %d non-existent filters\n",
5530                            __func__, remove_noent);
5531 }
5532
5533 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5534 {
5535         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5536         u8 mac_old[ETH_ALEN];
5537         int rc, rc2;
5538
5539         /* Only reconfigure a PF-created vport */
5540         if (is_zero_ether_addr(nic_data->vport_mac))
5541                 return 0;
5542
5543         efx_device_detach_sync(efx);
5544         efx_net_stop(efx->net_dev);
5545         down_write(&efx->filter_sem);
5546         efx_ef10_filter_table_remove(efx);
5547         up_write(&efx->filter_sem);
5548
5549         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5550         if (rc)
5551                 goto restore_filters;
5552
5553         ether_addr_copy(mac_old, nic_data->vport_mac);
5554         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5555                                     nic_data->vport_mac);
5556         if (rc)
5557                 goto restore_vadaptor;
5558
5559         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5560                                     efx->net_dev->dev_addr);
5561         if (!rc) {
5562                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5563         } else {
5564                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5565                 if (rc2) {
5566                         /* Failed to add original MAC, so clear vport_mac */
5567                         eth_zero_addr(nic_data->vport_mac);
5568                         goto reset_nic;
5569                 }
5570         }
5571
5572 restore_vadaptor:
5573         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5574         if (rc2)
5575                 goto reset_nic;
5576 restore_filters:
5577         down_write(&efx->filter_sem);
5578         rc2 = efx_ef10_filter_table_probe(efx);
5579         up_write(&efx->filter_sem);
5580         if (rc2)
5581                 goto reset_nic;
5582
5583         rc2 = efx_net_open(efx->net_dev);
5584         if (rc2)
5585                 goto reset_nic;
5586
5587         efx_device_attach_if_not_resetting(efx);
5588
5589         return rc;
5590
5591 reset_nic:
5592         netif_err(efx, drv, efx->net_dev,
5593                   "Failed to restore when changing MAC address - scheduling reset\n");
5594         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5595
5596         return rc ? rc : rc2;
5597 }
5598
5599 /* Caller must hold efx->filter_sem for read if race against
5600  * efx_ef10_filter_table_remove() is possible
5601  */
5602 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5603                                               struct efx_ef10_filter_vlan *vlan)
5604 {
5605         struct efx_ef10_filter_table *table = efx->filter_state;
5606         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5607
5608         /* Do not install unspecified VID if VLAN filtering is enabled.
5609          * Do not install all specified VIDs if VLAN filtering is disabled.
5610          */
5611         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5612                 return;
5613
5614         /* Insert/renew unicast filters */
5615         if (table->uc_promisc) {
5616                 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5617                                            false, false);
5618                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5619         } else {
5620                 /* If any of the filters failed to insert, fall back to
5621                  * promiscuous mode - add in the uc_def filter.  But keep
5622                  * our individual unicast filters.
5623                  */
5624                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5625                         efx_ef10_filter_insert_def(efx, vlan,
5626                                                    EFX_ENCAP_TYPE_NONE,
5627                                                    false, false);
5628         }
5629         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5630                                    false, false);
5631         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5632                                               EFX_ENCAP_FLAG_IPV6,
5633                                    false, false);
5634         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5635                                    false, false);
5636         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5637                                               EFX_ENCAP_FLAG_IPV6,
5638                                    false, false);
5639         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5640                                    false, false);
5641         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5642                                               EFX_ENCAP_FLAG_IPV6,
5643                                    false, false);
5644
5645         /* Insert/renew multicast filters */
5646         /* If changing promiscuous state with cascaded multicast filters, remove
5647          * old filters first, so that packets are dropped rather than duplicated
5648          */
5649         if (nic_data->workaround_26807 &&
5650             table->mc_promisc_last != table->mc_promisc)
5651                 efx_ef10_filter_remove_old(efx);
5652         if (table->mc_promisc) {
5653                 if (nic_data->workaround_26807) {
5654                         /* If we failed to insert promiscuous filters, rollback
5655                          * and fall back to individual multicast filters
5656                          */
5657                         if (efx_ef10_filter_insert_def(efx, vlan,
5658                                                        EFX_ENCAP_TYPE_NONE,
5659                                                        true, true)) {
5660                                 /* Changing promisc state, so remove old filters */
5661                                 efx_ef10_filter_remove_old(efx);
5662                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5663                                                                  true, false);
5664                         }
5665                 } else {
5666                         /* If we failed to insert promiscuous filters, don't
5667                          * rollback.  Regardless, also insert the mc_list,
5668                          * unless it's incomplete due to overflow
5669                          */
5670                         efx_ef10_filter_insert_def(efx, vlan,
5671                                                    EFX_ENCAP_TYPE_NONE,
5672                                                    true, false);
5673                         if (!table->mc_overflow)
5674                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5675                                                                  true, false);
5676                 }
5677         } else {
5678                 /* If any filters failed to insert, rollback and fall back to
5679                  * promiscuous mode - mc_def filter and maybe broadcast.  If
5680                  * that fails, roll back again and insert as many of our
5681                  * individual multicast filters as we can.
5682                  */
5683                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5684                         /* Changing promisc state, so remove old filters */
5685                         if (nic_data->workaround_26807)
5686                                 efx_ef10_filter_remove_old(efx);
5687                         if (efx_ef10_filter_insert_def(efx, vlan,
5688                                                        EFX_ENCAP_TYPE_NONE,
5689                                                        true, true))
5690                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5691                                                                  true, false);
5692                 }
5693         }
5694         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5695                                    true, false);
5696         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5697                                               EFX_ENCAP_FLAG_IPV6,
5698                                    true, false);
5699         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5700                                    true, false);
5701         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5702                                               EFX_ENCAP_FLAG_IPV6,
5703                                    true, false);
5704         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5705                                    true, false);
5706         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5707                                               EFX_ENCAP_FLAG_IPV6,
5708                                    true, false);
5709 }
5710
5711 /* Caller must hold efx->filter_sem for read if race against
5712  * efx_ef10_filter_table_remove() is possible
5713  */
5714 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5715 {
5716         struct efx_ef10_filter_table *table = efx->filter_state;
5717         struct net_device *net_dev = efx->net_dev;
5718         struct efx_ef10_filter_vlan *vlan;
5719         bool vlan_filter;
5720
5721         if (!efx_dev_registered(efx))
5722                 return;
5723
5724         if (!table)
5725                 return;
5726
5727         efx_ef10_filter_mark_old(efx);
5728
5729         /* Copy/convert the address lists; add the primary station
5730          * address and broadcast address
5731          */
5732         netif_addr_lock_bh(net_dev);
5733         efx_ef10_filter_uc_addr_list(efx);
5734         efx_ef10_filter_mc_addr_list(efx);
5735         netif_addr_unlock_bh(net_dev);
5736
5737         /* If VLAN filtering changes, all old filters are finally removed.
5738          * Do it in advance to avoid conflicts for unicast untagged and
5739          * VLAN 0 tagged filters.
5740          */
5741         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5742         if (table->vlan_filter != vlan_filter) {
5743                 table->vlan_filter = vlan_filter;
5744                 efx_ef10_filter_remove_old(efx);
5745         }
5746
5747         list_for_each_entry(vlan, &table->vlan_list, list)
5748                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5749
5750         efx_ef10_filter_remove_old(efx);
5751         table->mc_promisc_last = table->mc_promisc;
5752 }
5753
5754 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5755 {
5756         struct efx_ef10_filter_table *table = efx->filter_state;
5757         struct efx_ef10_filter_vlan *vlan;
5758
5759         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5760
5761         list_for_each_entry(vlan, &table->vlan_list, list) {
5762                 if (vlan->vid == vid)
5763                         return vlan;
5764         }
5765
5766         return NULL;
5767 }
5768
5769 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5770 {
5771         struct efx_ef10_filter_table *table = efx->filter_state;
5772         struct efx_ef10_filter_vlan *vlan;
5773         unsigned int i;
5774
5775         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5776                 return -EINVAL;
5777
5778         vlan = efx_ef10_filter_find_vlan(efx, vid);
5779         if (WARN_ON(vlan)) {
5780                 netif_err(efx, drv, efx->net_dev,
5781                           "VLAN %u already added\n", vid);
5782                 return -EALREADY;
5783         }
5784
5785         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5786         if (!vlan)
5787                 return -ENOMEM;
5788
5789         vlan->vid = vid;
5790
5791         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5792                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5793         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5794                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5795         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5796                 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5797
5798         list_add_tail(&vlan->list, &table->vlan_list);
5799
5800         if (efx_dev_registered(efx))
5801                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5802
5803         return 0;
5804 }
5805
5806 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5807                                               struct efx_ef10_filter_vlan *vlan)
5808 {
5809         unsigned int i;
5810
5811         /* See comment in efx_ef10_filter_table_remove() */
5812         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5813                 return;
5814
5815         list_del(&vlan->list);
5816
5817         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5818                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5819                                               vlan->uc[i]);
5820         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5821                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5822                                               vlan->mc[i]);
5823         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5824                 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5825                         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5826                                                       vlan->default_filters[i]);
5827
5828         kfree(vlan);
5829 }
5830
5831 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5832 {
5833         struct efx_ef10_filter_vlan *vlan;
5834
5835         /* See comment in efx_ef10_filter_table_remove() */
5836         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5837                 return;
5838
5839         vlan = efx_ef10_filter_find_vlan(efx, vid);
5840         if (!vlan) {
5841                 netif_err(efx, drv, efx->net_dev,
5842                           "VLAN %u not found in filter state\n", vid);
5843                 return;
5844         }
5845
5846         efx_ef10_filter_del_vlan_internal(efx, vlan);
5847 }
5848
5849 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5850 {
5851         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5852         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5853         bool was_enabled = efx->port_enabled;
5854         int rc;
5855
5856         efx_device_detach_sync(efx);
5857         efx_net_stop(efx->net_dev);
5858
5859         mutex_lock(&efx->mac_lock);
5860         down_write(&efx->filter_sem);
5861         efx_ef10_filter_table_remove(efx);
5862
5863         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5864                         efx->net_dev->dev_addr);
5865         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5866                        nic_data->vport_id);
5867         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5868                                 sizeof(inbuf), NULL, 0, NULL);
5869
5870         efx_ef10_filter_table_probe(efx);
5871         up_write(&efx->filter_sem);
5872         mutex_unlock(&efx->mac_lock);
5873
5874         if (was_enabled)
5875                 efx_net_open(efx->net_dev);
5876         efx_device_attach_if_not_resetting(efx);
5877
5878 #ifdef CONFIG_SFC_SRIOV
5879         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5880                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5881
5882                 if (rc == -EPERM) {
5883                         struct efx_nic *efx_pf;
5884
5885                         /* Switch to PF and change MAC address on vport */
5886                         efx_pf = pci_get_drvdata(pci_dev_pf);
5887
5888                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5889                                                        nic_data->vf_index,
5890                                                        efx->net_dev->dev_addr);
5891                 } else if (!rc) {
5892                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5893                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5894                         unsigned int i;
5895
5896                         /* MAC address successfully changed by VF (with MAC
5897                          * spoofing) so update the parent PF if possible.
5898                          */
5899                         for (i = 0; i < efx_pf->vf_count; ++i) {
5900                                 struct ef10_vf *vf = nic_data->vf + i;
5901
5902                                 if (vf->efx == efx) {
5903                                         ether_addr_copy(vf->mac,
5904                                                         efx->net_dev->dev_addr);
5905                                         return 0;
5906                                 }
5907                         }
5908                 }
5909         } else
5910 #endif
5911         if (rc == -EPERM) {
5912                 netif_err(efx, drv, efx->net_dev,
5913                           "Cannot change MAC address; use sfboot to enable"
5914                           " mac-spoofing on this interface\n");
5915         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5916                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5917                  * fall-back to the method of changing the MAC address on the
5918                  * vport.  This only applies to PFs because such versions of
5919                  * MCFW do not support VFs.
5920                  */
5921                 rc = efx_ef10_vport_set_mac_address(efx);
5922         } else if (rc) {
5923                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5924                                        sizeof(inbuf), NULL, 0, rc);
5925         }
5926
5927         return rc;
5928 }
5929
5930 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5931 {
5932         efx_ef10_filter_sync_rx_mode(efx);
5933
5934         return efx_mcdi_set_mac(efx);
5935 }
5936
5937 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5938 {
5939         efx_ef10_filter_sync_rx_mode(efx);
5940
5941         return 0;
5942 }
5943
5944 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5945 {
5946         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5947
5948         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5949         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5950                             NULL, 0, NULL);
5951 }
5952
5953 /* MC BISTs follow a different poll mechanism to phy BISTs.
5954  * The BIST is done in the poll handler on the MC, and the MCDI command
5955  * will block until the BIST is done.
5956  */
5957 static int efx_ef10_poll_bist(struct efx_nic *efx)
5958 {
5959         int rc;
5960         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5961         size_t outlen;
5962         u32 result;
5963
5964         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5965                            outbuf, sizeof(outbuf), &outlen);
5966         if (rc != 0)
5967                 return rc;
5968
5969         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5970                 return -EIO;
5971
5972         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5973         switch (result) {
5974         case MC_CMD_POLL_BIST_PASSED:
5975                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5976                 return 0;
5977         case MC_CMD_POLL_BIST_TIMEOUT:
5978                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5979                 return -EIO;
5980         case MC_CMD_POLL_BIST_FAILED:
5981                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5982                 return -EIO;
5983         default:
5984                 netif_err(efx, hw, efx->net_dev,
5985                           "BIST returned unknown result %u", result);
5986                 return -EIO;
5987         }
5988 }
5989
5990 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5991 {
5992         int rc;
5993
5994         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5995
5996         rc = efx_ef10_start_bist(efx, bist_type);
5997         if (rc != 0)
5998                 return rc;
5999
6000         return efx_ef10_poll_bist(efx);
6001 }
6002
6003 static int
6004 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
6005 {
6006         int rc, rc2;
6007
6008         efx_reset_down(efx, RESET_TYPE_WORLD);
6009
6010         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
6011                           NULL, 0, NULL, 0, NULL);
6012         if (rc != 0)
6013                 goto out;
6014
6015         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
6016         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
6017
6018         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
6019
6020 out:
6021         if (rc == -EPERM)
6022                 rc = 0;
6023         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
6024         return rc ? rc : rc2;
6025 }
6026
6027 #ifdef CONFIG_SFC_MTD
6028
6029 struct efx_ef10_nvram_type_info {
6030         u16 type, type_mask;
6031         u8 port;
6032         const char *name;
6033 };
6034
6035 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
6036         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
6037         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
6038         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
6039         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
6040         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
6041         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
6042         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
6043         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
6044         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
6045         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
6046         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
6047 };
6048 #define EF10_NVRAM_PARTITION_COUNT      ARRAY_SIZE(efx_ef10_nvram_types)
6049
6050 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
6051                                         struct efx_mcdi_mtd_partition *part,
6052                                         unsigned int type,
6053                                         unsigned long *found)
6054 {
6055         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
6056         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
6057         const struct efx_ef10_nvram_type_info *info;
6058         size_t size, erase_size, outlen;
6059         int type_idx = 0;
6060         bool protected;
6061         int rc;
6062
6063         for (type_idx = 0; ; type_idx++) {
6064                 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
6065                         return -ENODEV;
6066                 info = efx_ef10_nvram_types + type_idx;
6067                 if ((type & ~info->type_mask) == info->type)
6068                         break;
6069         }
6070         if (info->port != efx_port_num(efx))
6071                 return -ENODEV;
6072
6073         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
6074         if (rc)
6075                 return rc;
6076         if (protected)
6077                 return -ENODEV; /* hide it */
6078
6079         /* If we've already exposed a partition of this type, hide this
6080          * duplicate.  All operations on MTDs are keyed by the type anyway,
6081          * so we can't act on the duplicate.
6082          */
6083         if (__test_and_set_bit(type_idx, found))
6084                 return -EEXIST;
6085
6086         part->nvram_type = type;
6087
6088         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
6089         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
6090                           outbuf, sizeof(outbuf), &outlen);
6091         if (rc)
6092                 return rc;
6093         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
6094                 return -EIO;
6095         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
6096             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
6097                 part->fw_subtype = MCDI_DWORD(outbuf,
6098                                               NVRAM_METADATA_OUT_SUBTYPE);
6099
6100         part->common.dev_type_name = "EF10 NVRAM manager";
6101         part->common.type_name = info->name;
6102
6103         part->common.mtd.type = MTD_NORFLASH;
6104         part->common.mtd.flags = MTD_CAP_NORFLASH;
6105         part->common.mtd.size = size;
6106         part->common.mtd.erasesize = erase_size;
6107
6108         return 0;
6109 }
6110
6111 static int efx_ef10_mtd_probe(struct efx_nic *efx)
6112 {
6113         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
6114         DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
6115         struct efx_mcdi_mtd_partition *parts;
6116         size_t outlen, n_parts_total, i, n_parts;
6117         unsigned int type;
6118         int rc;
6119
6120         ASSERT_RTNL();
6121
6122         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
6123         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
6124                           outbuf, sizeof(outbuf), &outlen);
6125         if (rc)
6126                 return rc;
6127         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
6128                 return -EIO;
6129
6130         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
6131         if (n_parts_total >
6132             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
6133                 return -EIO;
6134
6135         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6136         if (!parts)
6137                 return -ENOMEM;
6138
6139         n_parts = 0;
6140         for (i = 0; i < n_parts_total; i++) {
6141                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6142                                         i);
6143                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
6144                                                   found);
6145                 if (rc == -EEXIST || rc == -ENODEV)
6146                         continue;
6147                 if (rc)
6148                         goto fail;
6149                 n_parts++;
6150         }
6151
6152         if (!n_parts) {
6153                 kfree(parts);
6154                 return 0;
6155         }
6156
6157         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6158 fail:
6159         if (rc)
6160                 kfree(parts);
6161         return rc;
6162 }
6163
6164 #endif /* CONFIG_SFC_MTD */
6165
6166 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6167 {
6168         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6169 }
6170
6171 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6172                                             u32 host_time) {}
6173
6174 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6175                                            bool temp)
6176 {
6177         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6178         int rc;
6179
6180         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6181             channel->sync_events_state == SYNC_EVENTS_VALID ||
6182             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6183                 return 0;
6184         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6185
6186         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6187         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6188         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6189                        channel->channel);
6190
6191         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6192                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6193
6194         if (rc != 0)
6195                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6196                                                     SYNC_EVENTS_DISABLED;
6197
6198         return rc;
6199 }
6200
6201 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6202                                             bool temp)
6203 {
6204         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6205         int rc;
6206
6207         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6208             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6209                 return 0;
6210         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6211                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6212                 return 0;
6213         }
6214         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6215                                             SYNC_EVENTS_DISABLED;
6216
6217         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6218         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6219         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6220                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6221         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6222                        channel->channel);
6223
6224         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6225                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6226
6227         return rc;
6228 }
6229
6230 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6231                                            bool temp)
6232 {
6233         int (*set)(struct efx_channel *channel, bool temp);
6234         struct efx_channel *channel;
6235
6236         set = en ?
6237               efx_ef10_rx_enable_timestamping :
6238               efx_ef10_rx_disable_timestamping;
6239
6240         channel = efx_ptp_channel(efx);
6241         if (channel) {
6242                 int rc = set(channel, temp);
6243                 if (en && rc != 0) {
6244                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6245                         return rc;
6246                 }
6247         }
6248
6249         return 0;
6250 }
6251
6252 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6253                                          struct hwtstamp_config *init)
6254 {
6255         return -EOPNOTSUPP;
6256 }
6257
6258 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6259                                       struct hwtstamp_config *init)
6260 {
6261         int rc;
6262
6263         switch (init->rx_filter) {
6264         case HWTSTAMP_FILTER_NONE:
6265                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6266                 /* if TX timestamping is still requested then leave PTP on */
6267                 return efx_ptp_change_mode(efx,
6268                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
6269         case HWTSTAMP_FILTER_ALL:
6270         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6271         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6272         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6273         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6274         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6275         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6276         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6277         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6278         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6279         case HWTSTAMP_FILTER_PTP_V2_EVENT:
6280         case HWTSTAMP_FILTER_PTP_V2_SYNC:
6281         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6282         case HWTSTAMP_FILTER_NTP_ALL:
6283                 init->rx_filter = HWTSTAMP_FILTER_ALL;
6284                 rc = efx_ptp_change_mode(efx, true, 0);
6285                 if (!rc)
6286                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6287                 if (rc)
6288                         efx_ptp_change_mode(efx, false, 0);
6289                 return rc;
6290         default:
6291                 return -ERANGE;
6292         }
6293 }
6294
6295 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6296                                      struct netdev_phys_item_id *ppid)
6297 {
6298         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6299
6300         if (!is_valid_ether_addr(nic_data->port_id))
6301                 return -EOPNOTSUPP;
6302
6303         ppid->id_len = ETH_ALEN;
6304         memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6305
6306         return 0;
6307 }
6308
6309 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6310 {
6311         if (proto != htons(ETH_P_8021Q))
6312                 return -EINVAL;
6313
6314         return efx_ef10_add_vlan(efx, vid);
6315 }
6316
6317 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6318 {
6319         if (proto != htons(ETH_P_8021Q))
6320                 return -EINVAL;
6321
6322         return efx_ef10_del_vlan(efx, vid);
6323 }
6324
6325 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6326  * ports table, ensuring that any TSO descriptors that were made on a now-
6327  * removed tunnel port will be blown away and won't break things when we try
6328  * to transmit them using the new ports table.
6329  */
6330 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6331 {
6332         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6333         MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6334         MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6335         bool will_reset = false;
6336         size_t num_entries = 0;
6337         size_t inlen, outlen;
6338         size_t i;
6339         int rc;
6340         efx_dword_t flags_and_num_entries;
6341
6342         WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6343
6344         nic_data->udp_tunnels_dirty = false;
6345
6346         if (!(nic_data->datapath_caps &
6347             (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6348                 efx_device_attach_if_not_resetting(efx);
6349                 return 0;
6350         }
6351
6352         BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6353                      MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6354
6355         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6356                 if (nic_data->udp_tunnels[i].count &&
6357                     nic_data->udp_tunnels[i].port) {
6358                         efx_dword_t entry;
6359
6360                         EFX_POPULATE_DWORD_2(entry,
6361                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6362                                         ntohs(nic_data->udp_tunnels[i].port),
6363                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6364                                         nic_data->udp_tunnels[i].type);
6365                         *_MCDI_ARRAY_DWORD(inbuf,
6366                                 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6367                                 num_entries++) = entry;
6368                 }
6369         }
6370
6371         BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6372                       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6373                      EFX_WORD_1_LBN);
6374         BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6375                      EFX_WORD_1_WIDTH);
6376         EFX_POPULATE_DWORD_2(flags_and_num_entries,
6377                              MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6378                                 !!unloading,
6379                              EFX_WORD_1, num_entries);
6380         *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6381                 flags_and_num_entries;
6382
6383         inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6384
6385         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6386                                 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6387         if (rc == -EIO) {
6388                 /* Most likely the MC rebooted due to another function also
6389                  * setting its tunnel port list. Mark the tunnel port list as
6390                  * dirty, so it will be pushed upon coming up from the reboot.
6391                  */
6392                 nic_data->udp_tunnels_dirty = true;
6393                 return 0;
6394         }
6395
6396         if (rc) {
6397                 /* expected not available on unprivileged functions */
6398                 if (rc != -EPERM)
6399                         netif_warn(efx, drv, efx->net_dev,
6400                                    "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6401         } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6402                    (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6403                 netif_info(efx, drv, efx->net_dev,
6404                            "Rebooting MC due to UDP tunnel port list change\n");
6405                 will_reset = true;
6406                 if (unloading)
6407                         /* Delay for the MC reset to complete. This will make
6408                          * unloading other functions a bit smoother. This is a
6409                          * race, but the other unload will work whichever way
6410                          * it goes, this just avoids an unnecessary error
6411                          * message.
6412                          */
6413                         msleep(100);
6414         }
6415         if (!will_reset && !unloading) {
6416                 /* The caller will have detached, relying on the MC reset to
6417                  * trigger a re-attach.  Since there won't be an MC reset, we
6418                  * have to do the attach ourselves.
6419                  */
6420                 efx_device_attach_if_not_resetting(efx);
6421         }
6422
6423         return rc;
6424 }
6425
6426 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6427 {
6428         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6429         int rc = 0;
6430
6431         mutex_lock(&nic_data->udp_tunnels_lock);
6432         if (nic_data->udp_tunnels_dirty) {
6433                 /* Make sure all TX are stopped while we modify the table, else
6434                  * we might race against an efx_features_check().
6435                  */
6436                 efx_device_detach_sync(efx);
6437                 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6438         }
6439         mutex_unlock(&nic_data->udp_tunnels_lock);
6440         return rc;
6441 }
6442
6443 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6444                                                              __be16 port)
6445 {
6446         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6447         size_t i;
6448
6449         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6450                 if (!nic_data->udp_tunnels[i].count)
6451                         continue;
6452                 if (nic_data->udp_tunnels[i].port == port)
6453                         return &nic_data->udp_tunnels[i];
6454         }
6455         return NULL;
6456 }
6457
6458 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6459                                      struct efx_udp_tunnel tnl)
6460 {
6461         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6462         struct efx_udp_tunnel *match;
6463         char typebuf[8];
6464         size_t i;
6465         int rc;
6466
6467         if (!(nic_data->datapath_caps &
6468               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6469                 return 0;
6470
6471         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6472         netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6473                   typebuf, ntohs(tnl.port));
6474
6475         mutex_lock(&nic_data->udp_tunnels_lock);
6476         /* Make sure all TX are stopped while we add to the table, else we
6477          * might race against an efx_features_check().
6478          */
6479         efx_device_detach_sync(efx);
6480
6481         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6482         if (match != NULL) {
6483                 if (match->type == tnl.type) {
6484                         netif_dbg(efx, drv, efx->net_dev,
6485                                   "Referencing existing tunnel entry\n");
6486                         match->count++;
6487                         /* No need to cause an MCDI update */
6488                         rc = 0;
6489                         goto unlock_out;
6490                 }
6491                 efx_get_udp_tunnel_type_name(match->type,
6492                                              typebuf, sizeof(typebuf));
6493                 netif_dbg(efx, drv, efx->net_dev,
6494                           "UDP port %d is already in use by %s\n",
6495                           ntohs(tnl.port), typebuf);
6496                 rc = -EEXIST;
6497                 goto unlock_out;
6498         }
6499
6500         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6501                 if (!nic_data->udp_tunnels[i].count) {
6502                         nic_data->udp_tunnels[i] = tnl;
6503                         nic_data->udp_tunnels[i].count = 1;
6504                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6505                         goto unlock_out;
6506                 }
6507
6508         netif_dbg(efx, drv, efx->net_dev,
6509                   "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6510                   typebuf, ntohs(tnl.port));
6511
6512         rc = -ENOMEM;
6513
6514 unlock_out:
6515         mutex_unlock(&nic_data->udp_tunnels_lock);
6516         return rc;
6517 }
6518
6519 /* Called under the TX lock with the TX queue running, hence no-one can be
6520  * in the middle of updating the UDP tunnels table.  However, they could
6521  * have tried and failed the MCDI, in which case they'll have set the dirty
6522  * flag before dropping their locks.
6523  */
6524 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6525 {
6526         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6527
6528         if (!(nic_data->datapath_caps &
6529               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6530                 return false;
6531
6532         if (nic_data->udp_tunnels_dirty)
6533                 /* SW table may not match HW state, so just assume we can't
6534                  * use any UDP tunnel offloads.
6535                  */
6536                 return false;
6537
6538         return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6539 }
6540
6541 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6542                                      struct efx_udp_tunnel tnl)
6543 {
6544         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6545         struct efx_udp_tunnel *match;
6546         char typebuf[8];
6547         int rc;
6548
6549         if (!(nic_data->datapath_caps &
6550               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6551                 return 0;
6552
6553         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6554         netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6555                   typebuf, ntohs(tnl.port));
6556
6557         mutex_lock(&nic_data->udp_tunnels_lock);
6558         /* Make sure all TX are stopped while we remove from the table, else we
6559          * might race against an efx_features_check().
6560          */
6561         efx_device_detach_sync(efx);
6562
6563         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6564         if (match != NULL) {
6565                 if (match->type == tnl.type) {
6566                         if (--match->count) {
6567                                 /* Port is still in use, so nothing to do */
6568                                 netif_dbg(efx, drv, efx->net_dev,
6569                                           "UDP tunnel port %d remains active\n",
6570                                           ntohs(tnl.port));
6571                                 rc = 0;
6572                                 goto out_unlock;
6573                         }
6574                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6575                         goto out_unlock;
6576                 }
6577                 efx_get_udp_tunnel_type_name(match->type,
6578                                              typebuf, sizeof(typebuf));
6579                 netif_warn(efx, drv, efx->net_dev,
6580                            "UDP port %d is actually in use by %s, not removing\n",
6581                            ntohs(tnl.port), typebuf);
6582         }
6583         rc = -ENOENT;
6584
6585 out_unlock:
6586         mutex_unlock(&nic_data->udp_tunnels_lock);
6587         return rc;
6588 }
6589
6590 #define EF10_OFFLOAD_FEATURES           \
6591         (NETIF_F_IP_CSUM |              \
6592          NETIF_F_HW_VLAN_CTAG_FILTER |  \
6593          NETIF_F_IPV6_CSUM |            \
6594          NETIF_F_RXHASH |               \
6595          NETIF_F_NTUPLE)
6596
6597 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6598         .is_vf = true,
6599         .mem_bar = efx_ef10_vf_mem_bar,
6600         .mem_map_size = efx_ef10_mem_map_size,
6601         .probe = efx_ef10_probe_vf,
6602         .remove = efx_ef10_remove,
6603         .dimension_resources = efx_ef10_dimension_resources,
6604         .init = efx_ef10_init_nic,
6605         .fini = efx_port_dummy_op_void,
6606         .map_reset_reason = efx_ef10_map_reset_reason,
6607         .map_reset_flags = efx_ef10_map_reset_flags,
6608         .reset = efx_ef10_reset,
6609         .probe_port = efx_mcdi_port_probe,
6610         .remove_port = efx_mcdi_port_remove,
6611         .fini_dmaq = efx_ef10_fini_dmaq,
6612         .prepare_flr = efx_ef10_prepare_flr,
6613         .finish_flr = efx_port_dummy_op_void,
6614         .describe_stats = efx_ef10_describe_stats,
6615         .update_stats = efx_ef10_update_stats_vf,
6616         .start_stats = efx_port_dummy_op_void,
6617         .pull_stats = efx_port_dummy_op_void,
6618         .stop_stats = efx_port_dummy_op_void,
6619         .set_id_led = efx_mcdi_set_id_led,
6620         .push_irq_moderation = efx_ef10_push_irq_moderation,
6621         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6622         .check_mac_fault = efx_mcdi_mac_check_fault,
6623         .reconfigure_port = efx_mcdi_port_reconfigure,
6624         .get_wol = efx_ef10_get_wol_vf,
6625         .set_wol = efx_ef10_set_wol_vf,
6626         .resume_wol = efx_port_dummy_op_void,
6627         .mcdi_request = efx_ef10_mcdi_request,
6628         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6629         .mcdi_read_response = efx_ef10_mcdi_read_response,
6630         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6631         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6632         .irq_enable_master = efx_port_dummy_op_void,
6633         .irq_test_generate = efx_ef10_irq_test_generate,
6634         .irq_disable_non_ev = efx_port_dummy_op_void,
6635         .irq_handle_msi = efx_ef10_msi_interrupt,
6636         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6637         .tx_probe = efx_ef10_tx_probe,
6638         .tx_init = efx_ef10_tx_init,
6639         .tx_remove = efx_ef10_tx_remove,
6640         .tx_write = efx_ef10_tx_write,
6641         .tx_limit_len = efx_ef10_tx_limit_len,
6642         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6643         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6644         .rx_probe = efx_ef10_rx_probe,
6645         .rx_init = efx_ef10_rx_init,
6646         .rx_remove = efx_ef10_rx_remove,
6647         .rx_write = efx_ef10_rx_write,
6648         .rx_defer_refill = efx_ef10_rx_defer_refill,
6649         .ev_probe = efx_ef10_ev_probe,
6650         .ev_init = efx_ef10_ev_init,
6651         .ev_fini = efx_ef10_ev_fini,
6652         .ev_remove = efx_ef10_ev_remove,
6653         .ev_process = efx_ef10_ev_process,
6654         .ev_read_ack = efx_ef10_ev_read_ack,
6655         .ev_test_generate = efx_ef10_ev_test_generate,
6656         .filter_table_probe = efx_ef10_filter_table_probe,
6657         .filter_table_restore = efx_ef10_filter_table_restore,
6658         .filter_table_remove = efx_ef10_filter_table_remove,
6659         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6660         .filter_insert = efx_ef10_filter_insert,
6661         .filter_remove_safe = efx_ef10_filter_remove_safe,
6662         .filter_get_safe = efx_ef10_filter_get_safe,
6663         .filter_clear_rx = efx_ef10_filter_clear_rx,
6664         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6665         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6666         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6667 #ifdef CONFIG_RFS_ACCEL
6668         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6669 #endif
6670 #ifdef CONFIG_SFC_MTD
6671         .mtd_probe = efx_port_dummy_op_int,
6672 #endif
6673         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6674         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6675         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6676         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6677 #ifdef CONFIG_SFC_SRIOV
6678         .vswitching_probe = efx_ef10_vswitching_probe_vf,
6679         .vswitching_restore = efx_ef10_vswitching_restore_vf,
6680         .vswitching_remove = efx_ef10_vswitching_remove_vf,
6681 #endif
6682         .get_mac_address = efx_ef10_get_mac_address_vf,
6683         .set_mac_address = efx_ef10_set_mac_address,
6684
6685         .get_phys_port_id = efx_ef10_get_phys_port_id,
6686         .revision = EFX_REV_HUNT_A0,
6687         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6688         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6689         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6690         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6691         .can_rx_scatter = true,
6692         .always_rx_scatter = true,
6693         .min_interrupt_mode = EFX_INT_MODE_MSIX,
6694         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6695         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6696         .offload_features = EF10_OFFLOAD_FEATURES,
6697         .mcdi_max_ver = 2,
6698         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6699         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6700                             1 << HWTSTAMP_FILTER_ALL,
6701         .rx_hash_key_size = 40,
6702 };
6703
6704 const struct efx_nic_type efx_hunt_a0_nic_type = {
6705         .is_vf = false,
6706         .mem_bar = efx_ef10_pf_mem_bar,
6707         .mem_map_size = efx_ef10_mem_map_size,
6708         .probe = efx_ef10_probe_pf,
6709         .remove = efx_ef10_remove,
6710         .dimension_resources = efx_ef10_dimension_resources,
6711         .init = efx_ef10_init_nic,
6712         .fini = efx_port_dummy_op_void,
6713         .map_reset_reason = efx_ef10_map_reset_reason,
6714         .map_reset_flags = efx_ef10_map_reset_flags,
6715         .reset = efx_ef10_reset,
6716         .probe_port = efx_mcdi_port_probe,
6717         .remove_port = efx_mcdi_port_remove,
6718         .fini_dmaq = efx_ef10_fini_dmaq,
6719         .prepare_flr = efx_ef10_prepare_flr,
6720         .finish_flr = efx_port_dummy_op_void,
6721         .describe_stats = efx_ef10_describe_stats,
6722         .update_stats = efx_ef10_update_stats_pf,
6723         .start_stats = efx_mcdi_mac_start_stats,
6724         .pull_stats = efx_mcdi_mac_pull_stats,
6725         .stop_stats = efx_mcdi_mac_stop_stats,
6726         .set_id_led = efx_mcdi_set_id_led,
6727         .push_irq_moderation = efx_ef10_push_irq_moderation,
6728         .reconfigure_mac = efx_ef10_mac_reconfigure,
6729         .check_mac_fault = efx_mcdi_mac_check_fault,
6730         .reconfigure_port = efx_mcdi_port_reconfigure,
6731         .get_wol = efx_ef10_get_wol,
6732         .set_wol = efx_ef10_set_wol,
6733         .resume_wol = efx_port_dummy_op_void,
6734         .test_chip = efx_ef10_test_chip,
6735         .test_nvram = efx_mcdi_nvram_test_all,
6736         .mcdi_request = efx_ef10_mcdi_request,
6737         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6738         .mcdi_read_response = efx_ef10_mcdi_read_response,
6739         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6740         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6741         .irq_enable_master = efx_port_dummy_op_void,
6742         .irq_test_generate = efx_ef10_irq_test_generate,
6743         .irq_disable_non_ev = efx_port_dummy_op_void,
6744         .irq_handle_msi = efx_ef10_msi_interrupt,
6745         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6746         .tx_probe = efx_ef10_tx_probe,
6747         .tx_init = efx_ef10_tx_init,
6748         .tx_remove = efx_ef10_tx_remove,
6749         .tx_write = efx_ef10_tx_write,
6750         .tx_limit_len = efx_ef10_tx_limit_len,
6751         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6752         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6753         .rx_push_rss_context_config = efx_ef10_rx_push_rss_context_config,
6754         .rx_pull_rss_context_config = efx_ef10_rx_pull_rss_context_config,
6755         .rx_restore_rss_contexts = efx_ef10_rx_restore_rss_contexts,
6756         .rx_probe = efx_ef10_rx_probe,
6757         .rx_init = efx_ef10_rx_init,
6758         .rx_remove = efx_ef10_rx_remove,
6759         .rx_write = efx_ef10_rx_write,
6760         .rx_defer_refill = efx_ef10_rx_defer_refill,
6761         .ev_probe = efx_ef10_ev_probe,
6762         .ev_init = efx_ef10_ev_init,
6763         .ev_fini = efx_ef10_ev_fini,
6764         .ev_remove = efx_ef10_ev_remove,
6765         .ev_process = efx_ef10_ev_process,
6766         .ev_read_ack = efx_ef10_ev_read_ack,
6767         .ev_test_generate = efx_ef10_ev_test_generate,
6768         .filter_table_probe = efx_ef10_filter_table_probe,
6769         .filter_table_restore = efx_ef10_filter_table_restore,
6770         .filter_table_remove = efx_ef10_filter_table_remove,
6771         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6772         .filter_insert = efx_ef10_filter_insert,
6773         .filter_remove_safe = efx_ef10_filter_remove_safe,
6774         .filter_get_safe = efx_ef10_filter_get_safe,
6775         .filter_clear_rx = efx_ef10_filter_clear_rx,
6776         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6777         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6778         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6779 #ifdef CONFIG_RFS_ACCEL
6780         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6781 #endif
6782 #ifdef CONFIG_SFC_MTD
6783         .mtd_probe = efx_ef10_mtd_probe,
6784         .mtd_rename = efx_mcdi_mtd_rename,
6785         .mtd_read = efx_mcdi_mtd_read,
6786         .mtd_erase = efx_mcdi_mtd_erase,
6787         .mtd_write = efx_mcdi_mtd_write,
6788         .mtd_sync = efx_mcdi_mtd_sync,
6789 #endif
6790         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6791         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6792         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6793         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6794         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6795         .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6796         .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6797         .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6798         .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6799 #ifdef CONFIG_SFC_SRIOV
6800         .sriov_configure = efx_ef10_sriov_configure,
6801         .sriov_init = efx_ef10_sriov_init,
6802         .sriov_fini = efx_ef10_sriov_fini,
6803         .sriov_wanted = efx_ef10_sriov_wanted,
6804         .sriov_reset = efx_ef10_sriov_reset,
6805         .sriov_flr = efx_ef10_sriov_flr,
6806         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6807         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6808         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6809         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6810         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6811         .vswitching_probe = efx_ef10_vswitching_probe_pf,
6812         .vswitching_restore = efx_ef10_vswitching_restore_pf,
6813         .vswitching_remove = efx_ef10_vswitching_remove_pf,
6814 #endif
6815         .get_mac_address = efx_ef10_get_mac_address_pf,
6816         .set_mac_address = efx_ef10_set_mac_address,
6817         .tso_versions = efx_ef10_tso_versions,
6818
6819         .get_phys_port_id = efx_ef10_get_phys_port_id,
6820         .revision = EFX_REV_HUNT_A0,
6821         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6822         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6823         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6824         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6825         .can_rx_scatter = true,
6826         .always_rx_scatter = true,
6827         .option_descriptors = true,
6828         .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6829         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6830         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6831         .offload_features = EF10_OFFLOAD_FEATURES,
6832         .mcdi_max_ver = 2,
6833         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6834         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6835                             1 << HWTSTAMP_FILTER_ALL,
6836         .rx_hash_key_size = 40,
6837 };