drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

   1 /*
   2  * Qualcomm Atheros IPQ806x GMAC glue layer
   3  *
   4  * Copyright (C) 2015 The Linux Foundation
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  */
  18
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/phy.h>
  22 #include <linux/regmap.h>
  23 #include <linux/clk.h>
  24 #include <linux/reset.h>
  25 #include <linux/of_net.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/stmmac.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/module.h>
  30
  31 #include "stmmac_platform.h"
  32
  33 #define NSS_COMMON_CLK_GATE                     0x8
  34 #define NSS_COMMON_CLK_GATE_PTP_EN(x)           BIT(0x10 + x)
  35 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x)      BIT(0x9 + (x * 2))
  36 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x)      BIT(0x8 + (x * 2))
  37 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x)       BIT(0x4 + x)
  38 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x)       BIT(0x0 + x)
  39
  40 #define NSS_COMMON_CLK_DIV0                     0xC
  41 #define NSS_COMMON_CLK_DIV_OFFSET(x)            (x * 8)
  42 #define NSS_COMMON_CLK_DIV_MASK                 0x7f
  43
  44 #define NSS_COMMON_CLK_SRC_CTRL                 0x14
  45 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)       (x)
  46 /* Mode is coded on 1 bit but is different depending on the MAC ID:
  47  * MAC0: QSGMII=0 RGMII=1
  48  * MAC1: QSGMII=0 SGMII=0 RGMII=1
  49  * MAC2 & MAC3: QSGMII=0 SGMII=1
  50  */
  51 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x)        1
  52 #define NSS_COMMON_CLK_SRC_CTRL_SGMII(x)        ((x >= 2) ? 1 : 0)
  53
  54 #define NSS_COMMON_GMAC_CTL(x)                  (0x30 + (x * 4))
  55 #define NSS_COMMON_GMAC_CTL_CSYS_REQ            BIT(19)
  56 #define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL       BIT(16)
  57 #define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET    8
  58 #define NSS_COMMON_GMAC_CTL_IFG_OFFSET          0
  59
  60 #define NSS_COMMON_CLK_DIV_RGMII_1000           1
  61 #define NSS_COMMON_CLK_DIV_RGMII_100            9
  62 #define NSS_COMMON_CLK_DIV_RGMII_10             99
  63 #define NSS_COMMON_CLK_DIV_SGMII_1000           0
  64 #define NSS_COMMON_CLK_DIV_SGMII_100            4
  65 #define NSS_COMMON_CLK_DIV_SGMII_10             49
  66
  67 #define QSGMII_PCS_CAL_LCKDT_CTL                0x120
  68 #define QSGMII_PCS_CAL_LCKDT_CTL_RST            BIT(19)
  69
  70 /* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
  71 #define QSGMII_PHY_SGMII_CTL(x)                 ((x == 1) ? 0x134 : \
  72                                                  (0x13c + (4 * (x - 2))))
  73 #define QSGMII_PHY_CDR_EN                       BIT(0)
  74 #define QSGMII_PHY_RX_FRONT_EN                  BIT(1)
  75 #define QSGMII_PHY_RX_SIGNAL_DETECT_EN          BIT(2)
  76 #define QSGMII_PHY_TX_DRIVER_EN                 BIT(3)
  77 #define QSGMII_PHY_QSGMII_EN                    BIT(7)
  78 #define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET       12
  79 #define QSGMII_PHY_RX_DC_BIAS_OFFSET            18
  80 #define QSGMII_PHY_RX_INPUT_EQU_OFFSET          20
  81 #define QSGMII_PHY_CDR_PI_SLEW_OFFSET           22
  82 #define QSGMII_PHY_TX_DRV_AMP_OFFSET            28
  83
  84 struct ipq806x_gmac {
  85         struct platform_device *pdev;
  86         struct regmap *nss_common;
  87         struct regmap *qsgmii_csr;
  88         uint32_t id;
  89         struct clk *core_clk;
  90         phy_interface_t phy_mode;
  91 };
  92
  93 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
  94 {
  95         struct device *dev = &gmac->pdev->dev;
  96         int div;
  97
  98         switch (speed) {
  99         case SPEED_1000:
 100                 div = NSS_COMMON_CLK_DIV_SGMII_1000;
 101                 break;
 102
 103         case SPEED_100:
 104                 div = NSS_COMMON_CLK_DIV_SGMII_100;
 105                 break;
 106
 107         case SPEED_10:
 108                 div = NSS_COMMON_CLK_DIV_SGMII_10;
 109                 break;
 110
 111         default:
 112                 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
 113                 return -EINVAL;
 114         }
 115
 116         return div;
 117 }
 118
 119 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
 120 {
 121         struct device *dev = &gmac->pdev->dev;
 122         int div;
 123
 124         switch (speed) {
 125         case SPEED_1000:
 126                 div = NSS_COMMON_CLK_DIV_RGMII_1000;
 127                 break;
 128
 129         case SPEED_100:
 130                 div = NSS_COMMON_CLK_DIV_RGMII_100;
 131                 break;
 132
 133         case SPEED_10:
 134                 div = NSS_COMMON_CLK_DIV_RGMII_10;
 135                 break;
 136
 137         default:
 138                 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
 139                 return -EINVAL;
 140         }
 141
 142         return div;
 143 }
 144
 145 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
 146 {
 147         uint32_t clk_bits, val;
 148         int div;
 149
 150         switch (gmac->phy_mode) {
 151         case PHY_INTERFACE_MODE_RGMII:
 152                 div = get_clk_div_rgmii(gmac, speed);
 153                 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
 154                            NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
 155                 break;
 156
 157         case PHY_INTERFACE_MODE_SGMII:
 158                 div = get_clk_div_sgmii(gmac, speed);
 159                 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
 160                            NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
 161                 break;
 162
 163         default:
 164                 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
 165                         phy_modes(gmac->phy_mode));
 166                 return -EINVAL;
 167         }
 168
 169         /* Disable the clocks */
 170         regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
 171         val &= ~clk_bits;
 172         regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
 173
 174         /* Set the divider */
 175         regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
 176         val &= ~(NSS_COMMON_CLK_DIV_MASK
 177                  << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
 178         val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
 179         regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
 180
 181         /* Enable the clock back */
 182         regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
 183         val |= clk_bits;
 184         regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
 185
 186         return 0;
 187 }
 188
 189 static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
 190 {
 191         struct device *dev = &gmac->pdev->dev;
 192
 193         gmac->phy_mode = of_get_phy_mode(dev->of_node);
 194         if ((int)gmac->phy_mode < 0) {
 195                 dev_err(dev, "missing phy mode property\n");
 196                 return -EINVAL;
 197         }
 198
 199         if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
 200                 dev_err(dev, "missing qcom id property\n");
 201                 return -EINVAL;
 202         }
 203
 204         /* The GMACs are called 1 to 4 in the documentation, but to simplify the
 205          * code and keep it consistent with the Linux convention, we'll number
 206          * them from 0 to 3 here.
 207          */
 208         if (gmac->id > 3) {
 209                 dev_err(dev, "invalid gmac id\n");
 210                 return -EINVAL;
 211         }
 212
 213         gmac->core_clk = devm_clk_get(dev, "stmmaceth");
 214         if (IS_ERR(gmac->core_clk)) {
 215                 dev_err(dev, "missing stmmaceth clk property\n");
 216                 return PTR_ERR(gmac->core_clk);
 217         }
 218         clk_set_rate(gmac->core_clk, 266000000);
 219
 220         /* Setup the register map for the nss common registers */
 221         gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
 222                                                            "qcom,nss-common");
 223         if (IS_ERR(gmac->nss_common)) {
 224                 dev_err(dev, "missing nss-common node\n");
 225                 return PTR_ERR(gmac->nss_common);
 226         }
 227
 228         /* Setup the register map for the qsgmii csr registers */
 229         gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
 230                                                            "qcom,qsgmii-csr");
 231         if (IS_ERR(gmac->qsgmii_csr))
 232                 dev_err(dev, "missing qsgmii-csr node\n");
 233
 234         return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
 235 }
 236
 237 static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)
 238 {
 239         struct ipq806x_gmac *gmac = priv;
 240
 241         ipq806x_gmac_set_speed(gmac, speed);
 242 }
 243
 244 static int ipq806x_gmac_probe(struct platform_device *pdev)
 245 {
 246         struct plat_stmmacenet_data *plat_dat;
 247         struct stmmac_resources stmmac_res;
 248         struct device *dev = &pdev->dev;
 249         struct ipq806x_gmac *gmac;
 250         int val;
 251         int err;
 252
 253         val = stmmac_get_platform_resources(pdev, &stmmac_res);
 254         if (val)
 255                 return val;
 256
 257         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 258         if (IS_ERR(plat_dat))
 259                 return PTR_ERR(plat_dat);
 260
 261         gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
 262         if (!gmac) {
 263                 err = -ENOMEM;
 264                 goto err_remove_config_dt;
 265         }
 266
 267         gmac->pdev = pdev;
 268
 269         err = ipq806x_gmac_of_parse(gmac);
 270         if (err) {
 271                 dev_err(dev, "device tree parsing error\n");
 272                 goto err_remove_config_dt;
 273         }
 274
 275         regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
 276                      QSGMII_PCS_CAL_LCKDT_CTL_RST);
 277
 278         /* Inter frame gap is set to 12 */
 279         val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
 280               12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
 281         /* We also initiate an AXI low power exit request */
 282         val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
 283         switch (gmac->phy_mode) {
 284         case PHY_INTERFACE_MODE_RGMII:
 285                 val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
 286                 break;
 287         case PHY_INTERFACE_MODE_SGMII:
 288                 val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
 289                 break;
 290         default:
 291                 goto err_unsupported_phy;
 292         }
 293         regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
 294
 295         /* Configure the clock src according to the mode */
 296         regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
 297         val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
 298         switch (gmac->phy_mode) {
 299         case PHY_INTERFACE_MODE_RGMII:
 300                 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
 301                         NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
 302                 break;
 303         case PHY_INTERFACE_MODE_SGMII:
 304                 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
 305                         NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
 306                 break;
 307         default:
 308                 goto err_unsupported_phy;
 309         }
 310         regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
 311
 312         /* Enable PTP clock */
 313         regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
 314         val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
 315         switch (gmac->phy_mode) {
 316         case PHY_INTERFACE_MODE_RGMII:
 317                 val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
 318                         NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
 319                 break;
 320         case PHY_INTERFACE_MODE_SGMII:
 321                 val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
 322                                 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
 323                 break;
 324         default:
 325                 goto err_unsupported_phy;
 326         }
 327         regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
 328
 329         if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
 330                 regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
 331                              QSGMII_PHY_CDR_EN |
 332                              QSGMII_PHY_RX_FRONT_EN |
 333                              QSGMII_PHY_RX_SIGNAL_DETECT_EN |
 334                              QSGMII_PHY_TX_DRIVER_EN |
 335                              QSGMII_PHY_QSGMII_EN |
 336                              0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
 337                              0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
 338                              0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
 339                              0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
 340                              0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
 341         }
 342
 343         plat_dat->has_gmac = true;
 344         plat_dat->bsp_priv = gmac;
 345         plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
 346         plat_dat->multicast_filter_bins = 0;
 347         plat_dat->tx_fifo_size = 8192;
 348         plat_dat->rx_fifo_size = 8192;
 349
 350         err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 351         if (err)
 352                 goto err_remove_config_dt;
 353
 354         return 0;
 355
 356 err_unsupported_phy:
 357         dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
 358                 phy_modes(gmac->phy_mode));
 359         err = -EINVAL;
 360
 361 err_remove_config_dt:
 362         stmmac_remove_config_dt(pdev, plat_dat);
 363
 364         return err;
 365 }
 366
 367 static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
 368         { .compatible = "qcom,ipq806x-gmac" },
 369         { }
 370 };
 371 MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
 372
 373 static struct platform_driver ipq806x_gmac_dwmac_driver = {
 374         .probe = ipq806x_gmac_probe,
 375         .remove = stmmac_pltfr_remove,
 376         .driver = {
 377                 .name           = "ipq806x-gmac-dwmac",
 378                 .pm             = &stmmac_pltfr_pm_ops,
 379                 .of_match_table = ipq806x_gmac_dwmac_match,
 380         },
 381 };
 382 module_platform_driver(ipq806x_gmac_dwmac_driver);
 383
 384 MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
 385 MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
 386 MODULE_LICENSE("Dual BSD/GPL");