2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
19 #include <linux/iopoll.h>
20 #include <linux/mdio-mux.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/regmap.h>
30 #include <linux/stmmac.h>
33 #include "stmmac_platform.h"
35 /* General notes on dwmac-sun8i:
36 * Locking: no locking is necessary in this file because all necessary locking
37 * is done in the "stmmac files"
40 /* struct emac_variant - Describe dwmac-sun8i hardware variant
41 * @default_syscon_value: The default value of the EMAC register in syscon
42 * This value is used for disabling properly EMAC
43 * and used as a good starting value in case of the
44 * boot process(uboot) leave some stuff.
45 * @syscon_field reg_field for the syscon's gmac register
46 * @soc_has_internal_phy: Does the MAC embed an internal PHY
47 * @support_mii: Does the MAC handle MII
48 * @support_rmii: Does the MAC handle RMII
49 * @support_rgmii: Does the MAC handle RGMII
51 * @rx_delay_max: Maximum raw value for RX delay chain
52 * @tx_delay_max: Maximum raw value for TX delay chain
53 * These two also indicate the bitmask for
54 * the RX and TX delay chain registers. A
55 * value of zero indicates this is not supported.
58 u32 default_syscon_value;
59 const struct reg_field *syscon_field;
60 bool soc_has_internal_phy;
68 /* struct sunxi_priv_data - hold all sunxi private data
69 * @tx_clk: reference to MAC TX clock
70 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
71 * @regulator: reference to the optional regulator
72 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
73 * @variant: reference to the current board variant
74 * @regmap: regmap for using the syscon
75 * @internal_phy_powered: Does the internal PHY is enabled
76 * @use_internal_phy: Is the internal PHY selected for use
77 * @mux_handle: Internal pointer used by mdio-mux lib
79 struct sunxi_priv_data {
82 struct regulator *regulator;
83 struct reset_control *rst_ephy;
84 const struct emac_variant *variant;
85 struct regmap_field *regmap_field;
86 bool internal_phy_powered;
87 bool use_internal_phy;
91 /* EMAC clock register @ 0x30 in the "system control" address range */
92 static const struct reg_field sun8i_syscon_reg_field = {
98 /* EMAC clock register @ 0x164 in the CCU address range */
99 static const struct reg_field sun8i_ccu_reg_field = {
105 static const struct emac_variant emac_variant_h3 = {
106 .default_syscon_value = 0x58000,
107 .syscon_field = &sun8i_syscon_reg_field,
108 .soc_has_internal_phy = true,
110 .support_rmii = true,
111 .support_rgmii = true,
116 static const struct emac_variant emac_variant_v3s = {
117 .default_syscon_value = 0x38000,
118 .syscon_field = &sun8i_syscon_reg_field,
119 .soc_has_internal_phy = true,
123 static const struct emac_variant emac_variant_a83t = {
124 .default_syscon_value = 0,
125 .syscon_field = &sun8i_syscon_reg_field,
126 .soc_has_internal_phy = false,
128 .support_rgmii = true,
133 static const struct emac_variant emac_variant_r40 = {
134 .default_syscon_value = 0,
135 .syscon_field = &sun8i_ccu_reg_field,
137 .support_rgmii = true,
141 static const struct emac_variant emac_variant_a64 = {
142 .default_syscon_value = 0,
143 .syscon_field = &sun8i_syscon_reg_field,
144 .soc_has_internal_phy = false,
146 .support_rmii = true,
147 .support_rgmii = true,
152 #define EMAC_BASIC_CTL0 0x00
153 #define EMAC_BASIC_CTL1 0x04
154 #define EMAC_INT_STA 0x08
155 #define EMAC_INT_EN 0x0C
156 #define EMAC_TX_CTL0 0x10
157 #define EMAC_TX_CTL1 0x14
158 #define EMAC_TX_FLOW_CTL 0x1C
159 #define EMAC_TX_DESC_LIST 0x20
160 #define EMAC_RX_CTL0 0x24
161 #define EMAC_RX_CTL1 0x28
162 #define EMAC_RX_DESC_LIST 0x34
163 #define EMAC_RX_FRM_FLT 0x38
164 #define EMAC_MDIO_CMD 0x48
165 #define EMAC_MDIO_DATA 0x4C
166 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
167 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
168 #define EMAC_TX_DMA_STA 0xB0
169 #define EMAC_TX_CUR_DESC 0xB4
170 #define EMAC_TX_CUR_BUF 0xB8
171 #define EMAC_RX_DMA_STA 0xC0
172 #define EMAC_RX_CUR_DESC 0xC4
173 #define EMAC_RX_CUR_BUF 0xC8
175 /* Use in EMAC_BASIC_CTL0 */
176 #define EMAC_DUPLEX_FULL BIT(0)
177 #define EMAC_LOOPBACK BIT(1)
178 #define EMAC_SPEED_1000 0
179 #define EMAC_SPEED_100 (0x03 << 2)
180 #define EMAC_SPEED_10 (0x02 << 2)
182 /* Use in EMAC_BASIC_CTL1 */
183 #define EMAC_BURSTLEN_SHIFT 24
185 /* Used in EMAC_RX_FRM_FLT */
186 #define EMAC_FRM_FLT_RXALL BIT(0)
187 #define EMAC_FRM_FLT_CTL BIT(13)
188 #define EMAC_FRM_FLT_MULTICAST BIT(16)
191 #define EMAC_RX_MD BIT(1)
192 #define EMAC_RX_TH_MASK GENMASK(4, 5)
193 #define EMAC_RX_TH_32 0
194 #define EMAC_RX_TH_64 (0x1 << 4)
195 #define EMAC_RX_TH_96 (0x2 << 4)
196 #define EMAC_RX_TH_128 (0x3 << 4)
197 #define EMAC_RX_DMA_EN BIT(30)
198 #define EMAC_RX_DMA_START BIT(31)
201 #define EMAC_TX_MD BIT(1)
202 #define EMAC_TX_NEXT_FRM BIT(2)
203 #define EMAC_TX_TH_MASK GENMASK(8, 10)
204 #define EMAC_TX_TH_64 0
205 #define EMAC_TX_TH_128 (0x1 << 8)
206 #define EMAC_TX_TH_192 (0x2 << 8)
207 #define EMAC_TX_TH_256 (0x3 << 8)
208 #define EMAC_TX_DMA_EN BIT(30)
209 #define EMAC_TX_DMA_START BIT(31)
211 /* Used in RX_CTL0 */
212 #define EMAC_RX_RECEIVER_EN BIT(31)
213 #define EMAC_RX_DO_CRC BIT(27)
214 #define EMAC_RX_FLOW_CTL_EN BIT(16)
216 /* Used in TX_CTL0 */
217 #define EMAC_TX_TRANSMITTER_EN BIT(31)
219 /* Used in EMAC_TX_FLOW_CTL */
220 #define EMAC_TX_FLOW_CTL_EN BIT(0)
222 /* Used in EMAC_INT_STA */
223 #define EMAC_TX_INT BIT(0)
224 #define EMAC_TX_DMA_STOP_INT BIT(1)
225 #define EMAC_TX_BUF_UA_INT BIT(2)
226 #define EMAC_TX_TIMEOUT_INT BIT(3)
227 #define EMAC_TX_UNDERFLOW_INT BIT(4)
228 #define EMAC_TX_EARLY_INT BIT(5)
229 #define EMAC_RX_INT BIT(8)
230 #define EMAC_RX_BUF_UA_INT BIT(9)
231 #define EMAC_RX_DMA_STOP_INT BIT(10)
232 #define EMAC_RX_TIMEOUT_INT BIT(11)
233 #define EMAC_RX_OVERFLOW_INT BIT(12)
234 #define EMAC_RX_EARLY_INT BIT(13)
235 #define EMAC_RGMII_STA_INT BIT(16)
237 #define MAC_ADDR_TYPE_DST BIT(31)
239 /* H3 specific bits for EPHY */
240 #define H3_EPHY_ADDR_SHIFT 20
241 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
242 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
243 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
244 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
245 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
246 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
247 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
249 /* H3/A64 specific bits */
250 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
252 /* Generic system control EMAC_CLK bits */
253 #define SYSCON_ETXDC_SHIFT 10
254 #define SYSCON_ERXDC_SHIFT 5
255 /* EMAC PHY Interface Type */
256 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
257 #define SYSCON_ETCS_MASK GENMASK(1, 0)
258 #define SYSCON_ETCS_MII 0x0
259 #define SYSCON_ETCS_EXT_GMII 0x1
260 #define SYSCON_ETCS_INT_GMII 0x2
262 /* sun8i_dwmac_dma_reset() - reset the EMAC
263 * Called from stmmac via stmmac_dma_ops->reset
265 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
267 writel(0, ioaddr + EMAC_RX_CTL1);
268 writel(0, ioaddr + EMAC_TX_CTL1);
269 writel(0, ioaddr + EMAC_RX_FRM_FLT);
270 writel(0, ioaddr + EMAC_RX_DESC_LIST);
271 writel(0, ioaddr + EMAC_TX_DESC_LIST);
272 writel(0, ioaddr + EMAC_INT_EN);
273 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
277 /* sun8i_dwmac_dma_init() - initialize the EMAC
278 * Called from stmmac via stmmac_dma_ops->init
280 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
281 struct stmmac_dma_cfg *dma_cfg, int atds)
283 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
284 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
287 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,
288 struct stmmac_dma_cfg *dma_cfg,
289 u32 dma_rx_phy, u32 chan)
291 /* Write RX descriptors address */
292 writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST);
295 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,
296 struct stmmac_dma_cfg *dma_cfg,
297 u32 dma_tx_phy, u32 chan)
299 /* Write TX descriptors address */
300 writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST);
303 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
304 * Called from stmmac_dma_ops->dump_regs
307 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
311 for (i = 0; i < 0xC8; i += 4) {
312 if (i == 0x32 || i == 0x3C)
314 reg_space[i / 4] = readl(ioaddr + i);
318 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
319 * Called from stmmac_ops->dump_regs
322 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
326 void __iomem *ioaddr = hw->pcsr;
328 for (i = 0; i < 0xC8; i += 4) {
329 if (i == 0x32 || i == 0x3C)
331 reg_space[i / 4] = readl(ioaddr + i);
335 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
337 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
340 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
342 writel(0, ioaddr + EMAC_INT_EN);
345 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
349 v = readl(ioaddr + EMAC_TX_CTL1);
350 v |= EMAC_TX_DMA_START;
352 writel(v, ioaddr + EMAC_TX_CTL1);
355 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
359 v = readl(ioaddr + EMAC_TX_CTL1);
360 v |= EMAC_TX_DMA_START;
362 writel(v, ioaddr + EMAC_TX_CTL1);
365 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
369 v = readl(ioaddr + EMAC_TX_CTL1);
370 v &= ~EMAC_TX_DMA_EN;
371 writel(v, ioaddr + EMAC_TX_CTL1);
374 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
378 v = readl(ioaddr + EMAC_RX_CTL1);
379 v |= EMAC_RX_DMA_START;
381 writel(v, ioaddr + EMAC_RX_CTL1);
384 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
388 v = readl(ioaddr + EMAC_RX_CTL1);
389 v &= ~EMAC_RX_DMA_EN;
390 writel(v, ioaddr + EMAC_RX_CTL1);
393 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
394 struct stmmac_extra_stats *x, u32 chan)
399 v = readl(ioaddr + EMAC_INT_STA);
401 if (v & EMAC_TX_INT) {
403 x->tx_normal_irq_n++;
406 if (v & EMAC_TX_DMA_STOP_INT)
407 x->tx_process_stopped_irq++;
409 if (v & EMAC_TX_BUF_UA_INT)
410 x->tx_process_stopped_irq++;
412 if (v & EMAC_TX_TIMEOUT_INT)
413 ret |= tx_hard_error;
415 if (v & EMAC_TX_UNDERFLOW_INT) {
416 ret |= tx_hard_error;
417 x->tx_undeflow_irq++;
420 if (v & EMAC_TX_EARLY_INT)
423 if (v & EMAC_RX_INT) {
425 x->rx_normal_irq_n++;
428 if (v & EMAC_RX_BUF_UA_INT)
429 x->rx_buf_unav_irq++;
431 if (v & EMAC_RX_DMA_STOP_INT)
432 x->rx_process_stopped_irq++;
434 if (v & EMAC_RX_TIMEOUT_INT)
435 ret |= tx_hard_error;
437 if (v & EMAC_RX_OVERFLOW_INT) {
438 ret |= tx_hard_error;
439 x->rx_overflow_irq++;
442 if (v & EMAC_RX_EARLY_INT)
445 if (v & EMAC_RGMII_STA_INT)
448 writel(v, ioaddr + EMAC_INT_STA);
453 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
454 u32 channel, int fifosz, u8 qmode)
458 v = readl(ioaddr + EMAC_RX_CTL1);
459 if (mode == SF_DMA_MODE) {
463 v &= ~EMAC_RX_TH_MASK;
473 writel(v, ioaddr + EMAC_RX_CTL1);
476 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
477 u32 channel, int fifosz, u8 qmode)
481 v = readl(ioaddr + EMAC_TX_CTL1);
482 if (mode == SF_DMA_MODE) {
484 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
486 * "Operating on second frame increase the performance
487 * especially when transmit store-and-forward is used."
489 v |= EMAC_TX_NEXT_FRM;
492 v &= ~EMAC_TX_TH_MASK;
502 writel(v, ioaddr + EMAC_TX_CTL1);
505 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
506 .reset = sun8i_dwmac_dma_reset,
507 .init = sun8i_dwmac_dma_init,
508 .init_rx_chan = sun8i_dwmac_dma_init_rx,
509 .init_tx_chan = sun8i_dwmac_dma_init_tx,
510 .dump_regs = sun8i_dwmac_dump_regs,
511 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
512 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
513 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
514 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
515 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
516 .start_tx = sun8i_dwmac_dma_start_tx,
517 .stop_tx = sun8i_dwmac_dma_stop_tx,
518 .start_rx = sun8i_dwmac_dma_start_rx,
519 .stop_rx = sun8i_dwmac_dma_stop_rx,
520 .dma_interrupt = sun8i_dwmac_dma_interrupt,
523 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
525 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
527 struct net_device *ndev = platform_get_drvdata(pdev);
528 struct sunxi_priv_data *gmac = priv;
531 if (gmac->regulator) {
532 ret = regulator_enable(gmac->regulator);
534 dev_err(&pdev->dev, "Fail to enable regulator\n");
539 ret = clk_prepare_enable(gmac->tx_clk);
541 dev_err(&pdev->dev, "Could not enable AHB clock\n");
542 goto err_disable_regulator;
545 if (gmac->use_internal_phy) {
546 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
548 goto err_disable_clk;
554 clk_disable_unprepare(gmac->tx_clk);
555 err_disable_regulator:
557 regulator_disable(gmac->regulator);
562 static void sun8i_dwmac_core_init(struct mac_device_info *hw,
563 struct net_device *dev)
565 void __iomem *ioaddr = hw->pcsr;
568 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
569 writel(v, ioaddr + EMAC_BASIC_CTL1);
572 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
576 t = readl(ioaddr + EMAC_TX_CTL0);
577 r = readl(ioaddr + EMAC_RX_CTL0);
579 t |= EMAC_TX_TRANSMITTER_EN;
580 r |= EMAC_RX_RECEIVER_EN;
582 t &= ~EMAC_TX_TRANSMITTER_EN;
583 r &= ~EMAC_RX_RECEIVER_EN;
585 writel(t, ioaddr + EMAC_TX_CTL0);
586 writel(r, ioaddr + EMAC_RX_CTL0);
589 /* Set MAC address at slot reg_n
590 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
591 * If addr is NULL, clear the slot
593 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
597 void __iomem *ioaddr = hw->pcsr;
601 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
605 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
606 EMAC_MACADDR_LO(reg_n));
608 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
609 v |= MAC_ADDR_TYPE_DST;
610 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
614 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
618 void __iomem *ioaddr = hw->pcsr;
620 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
621 EMAC_MACADDR_LO(reg_n));
624 /* caution this function must return non 0 to work */
625 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
627 void __iomem *ioaddr = hw->pcsr;
630 v = readl(ioaddr + EMAC_RX_CTL0);
632 writel(v, ioaddr + EMAC_RX_CTL0);
637 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
638 struct net_device *dev)
640 void __iomem *ioaddr = hw->pcsr;
643 struct netdev_hw_addr *ha;
644 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
646 v = EMAC_FRM_FLT_CTL;
648 if (dev->flags & IFF_PROMISC) {
649 v = EMAC_FRM_FLT_RXALL;
650 } else if (dev->flags & IFF_ALLMULTI) {
651 v |= EMAC_FRM_FLT_MULTICAST;
652 } else if (macaddrs <= hw->unicast_filter_entries) {
653 if (!netdev_mc_empty(dev)) {
654 netdev_for_each_mc_addr(ha, dev) {
655 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
659 if (!netdev_uc_empty(dev)) {
660 netdev_for_each_uc_addr(ha, dev) {
661 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
666 netdev_info(dev, "Too many address, switching to promiscuous\n");
667 v = EMAC_FRM_FLT_RXALL;
670 /* Disable unused address filter slots */
671 while (i < hw->unicast_filter_entries)
672 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
674 writel(v, ioaddr + EMAC_RX_FRM_FLT);
677 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
678 unsigned int duplex, unsigned int fc,
679 unsigned int pause_time, u32 tx_cnt)
681 void __iomem *ioaddr = hw->pcsr;
684 v = readl(ioaddr + EMAC_RX_CTL0);
686 v |= EMAC_RX_FLOW_CTL_EN;
688 v &= ~EMAC_RX_FLOW_CTL_EN;
689 writel(v, ioaddr + EMAC_RX_CTL0);
691 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
693 v |= EMAC_TX_FLOW_CTL_EN;
695 v &= ~EMAC_TX_FLOW_CTL_EN;
696 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
699 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
704 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
705 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
707 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
708 * need more if no cable plugged. 100ms seems OK
710 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
711 !(v & 0x01), 100, 100000);
714 dev_err(priv->device, "EMAC reset timeout\n");
720 /* Search in mdio-mux node for internal PHY node and get its clk/reset */
721 static int get_ephy_nodes(struct stmmac_priv *priv)
723 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
724 struct device_node *mdio_mux, *iphynode;
725 struct device_node *mdio_internal;
728 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
730 dev_err(priv->device, "Cannot get mdio-mux node\n");
734 mdio_internal = of_get_compatible_child(mdio_mux,
735 "allwinner,sun8i-h3-mdio-internal");
736 of_node_put(mdio_mux);
737 if (!mdio_internal) {
738 dev_err(priv->device, "Cannot get internal_mdio node\n");
742 /* Seek for internal PHY */
743 for_each_child_of_node(mdio_internal, iphynode) {
744 gmac->ephy_clk = of_clk_get(iphynode, 0);
745 if (IS_ERR(gmac->ephy_clk))
747 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
748 if (IS_ERR(gmac->rst_ephy)) {
749 ret = PTR_ERR(gmac->rst_ephy);
750 if (ret == -EPROBE_DEFER) {
751 of_node_put(iphynode);
752 of_node_put(mdio_internal);
757 dev_info(priv->device, "Found internal PHY node\n");
758 of_node_put(iphynode);
759 of_node_put(mdio_internal);
763 of_node_put(mdio_internal);
767 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
769 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
772 if (gmac->internal_phy_powered) {
773 dev_warn(priv->device, "Internal PHY already powered\n");
777 dev_info(priv->device, "Powering internal PHY\n");
778 ret = clk_prepare_enable(gmac->ephy_clk);
780 dev_err(priv->device, "Cannot enable internal PHY\n");
784 /* Make sure the EPHY is properly reseted, as U-Boot may leave
785 * it at deasserted state, and thus it may fail to reset EMAC.
787 reset_control_assert(gmac->rst_ephy);
789 ret = reset_control_deassert(gmac->rst_ephy);
791 dev_err(priv->device, "Cannot deassert internal phy\n");
792 clk_disable_unprepare(gmac->ephy_clk);
796 gmac->internal_phy_powered = true;
801 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
803 if (!gmac->internal_phy_powered)
806 clk_disable_unprepare(gmac->ephy_clk);
807 reset_control_assert(gmac->rst_ephy);
808 gmac->internal_phy_powered = false;
812 /* MDIO multiplexing switch function
813 * This function is called by the mdio-mux layer when it thinks the mdio bus
814 * multiplexer needs to switch.
815 * 'current_child' is the current value of the mux register
816 * 'desired_child' is the value of the 'reg' property of the target child MDIO
818 * The first time this function is called, current_child == -1.
819 * If current_child == desired_child, then the mux is already set to the
822 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
825 struct stmmac_priv *priv = data;
826 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
830 if (current_child ^ desired_child) {
831 regmap_field_read(gmac->regmap_field, ®);
832 switch (desired_child) {
833 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
834 dev_info(priv->device, "Switch mux to internal PHY");
835 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
836 gmac->use_internal_phy = true;
838 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
839 dev_info(priv->device, "Switch mux to external PHY");
840 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
841 gmac->use_internal_phy = false;
844 dev_err(priv->device, "Invalid child ID %x\n",
848 regmap_field_write(gmac->regmap_field, val);
849 if (gmac->use_internal_phy) {
850 ret = sun8i_dwmac_power_internal_phy(priv);
854 sun8i_dwmac_unpower_internal_phy(gmac);
856 /* After changing syscon value, the MAC need reset or it will
857 * use the last value (and so the last PHY set).
859 ret = sun8i_dwmac_reset(priv);
864 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
867 struct device_node *mdio_mux;
868 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
870 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
874 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
875 &gmac->mux_handle, priv, priv->mii);
876 of_node_put(mdio_mux);
880 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
882 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
883 struct device_node *node = priv->device->of_node;
887 regmap_field_read(gmac->regmap_field, &val);
888 reg = gmac->variant->default_syscon_value;
890 dev_warn(priv->device,
891 "Current syscon value is not the default %x (expect %x)\n",
894 if (gmac->variant->soc_has_internal_phy) {
895 if (of_property_read_bool(node, "allwinner,leds-active-low"))
896 reg |= H3_EPHY_LED_POL;
898 reg &= ~H3_EPHY_LED_POL;
900 /* Force EPHY xtal frequency to 24MHz. */
901 reg |= H3_EPHY_CLK_SEL;
903 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
905 dev_err(priv->device, "Could not parse MDIO addr\n");
908 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
909 * address. No need to mask it again.
911 reg |= 1 << H3_EPHY_ADDR_SHIFT;
913 /* For SoCs without internal PHY the PHY selection bit should be
914 * set to 0 (external PHY).
916 reg &= ~H3_EPHY_SELECT;
919 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
921 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
925 dev_dbg(priv->device, "set tx-delay to %x\n", val);
926 if (val <= gmac->variant->tx_delay_max) {
927 reg &= ~(gmac->variant->tx_delay_max <<
929 reg |= (val << SYSCON_ETXDC_SHIFT);
931 dev_err(priv->device, "Invalid TX clock delay: %d\n",
937 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
939 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
943 dev_dbg(priv->device, "set rx-delay to %x\n", val);
944 if (val <= gmac->variant->rx_delay_max) {
945 reg &= ~(gmac->variant->rx_delay_max <<
947 reg |= (val << SYSCON_ERXDC_SHIFT);
949 dev_err(priv->device, "Invalid RX clock delay: %d\n",
955 /* Clear interface mode bits */
956 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
957 if (gmac->variant->support_rmii)
958 reg &= ~SYSCON_RMII_EN;
960 switch (priv->plat->interface) {
961 case PHY_INTERFACE_MODE_MII:
964 case PHY_INTERFACE_MODE_RGMII:
965 case PHY_INTERFACE_MODE_RGMII_ID:
966 case PHY_INTERFACE_MODE_RGMII_RXID:
967 case PHY_INTERFACE_MODE_RGMII_TXID:
968 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
970 case PHY_INTERFACE_MODE_RMII:
971 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
974 dev_err(priv->device, "Unsupported interface mode: %s",
975 phy_modes(priv->plat->interface));
979 regmap_field_write(gmac->regmap_field, reg);
984 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
986 u32 reg = gmac->variant->default_syscon_value;
988 regmap_field_write(gmac->regmap_field, reg);
991 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
993 struct sunxi_priv_data *gmac = priv;
995 if (gmac->variant->soc_has_internal_phy) {
996 if (gmac->internal_phy_powered)
997 sun8i_dwmac_unpower_internal_phy(gmac);
1000 sun8i_dwmac_unset_syscon(gmac);
1002 clk_disable_unprepare(gmac->tx_clk);
1004 if (gmac->regulator)
1005 regulator_disable(gmac->regulator);
1008 static const struct stmmac_ops sun8i_dwmac_ops = {
1009 .core_init = sun8i_dwmac_core_init,
1010 .set_mac = sun8i_dwmac_set_mac,
1011 .dump_regs = sun8i_dwmac_dump_mac_regs,
1012 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
1013 .set_filter = sun8i_dwmac_set_filter,
1014 .flow_ctrl = sun8i_dwmac_flow_ctrl,
1015 .set_umac_addr = sun8i_dwmac_set_umac_addr,
1016 .get_umac_addr = sun8i_dwmac_get_umac_addr,
1019 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
1021 struct mac_device_info *mac;
1022 struct stmmac_priv *priv = ppriv;
1025 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1029 ret = sun8i_dwmac_set_syscon(priv);
1033 mac->pcsr = priv->ioaddr;
1034 mac->mac = &sun8i_dwmac_ops;
1035 mac->dma = &sun8i_dwmac_dma_ops;
1037 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1039 /* The loopback bit seems to be re-set when link change
1040 * Simply mask it each time
1041 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1043 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1044 mac->link.speed10 = EMAC_SPEED_10;
1045 mac->link.speed100 = EMAC_SPEED_100;
1046 mac->link.speed1000 = EMAC_SPEED_1000;
1047 mac->link.duplex = EMAC_DUPLEX_FULL;
1048 mac->mii.addr = EMAC_MDIO_CMD;
1049 mac->mii.data = EMAC_MDIO_DATA;
1050 mac->mii.reg_shift = 4;
1051 mac->mii.reg_mask = GENMASK(8, 4);
1052 mac->mii.addr_shift = 12;
1053 mac->mii.addr_mask = GENMASK(16, 12);
1054 mac->mii.clk_csr_shift = 20;
1055 mac->mii.clk_csr_mask = GENMASK(22, 20);
1056 mac->unicast_filter_entries = 8;
1058 /* Synopsys Id is not available */
1059 priv->synopsys_id = 0;
1064 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1066 struct device_node *syscon_node;
1067 struct platform_device *syscon_pdev;
1068 struct regmap *regmap = NULL;
1070 syscon_node = of_parse_phandle(node, "syscon", 0);
1072 return ERR_PTR(-ENODEV);
1074 syscon_pdev = of_find_device_by_node(syscon_node);
1076 /* platform device might not be probed yet */
1077 regmap = ERR_PTR(-EPROBE_DEFER);
1081 /* If no regmap is found then the other device driver is at fault */
1082 regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1084 regmap = ERR_PTR(-EINVAL);
1086 platform_device_put(syscon_pdev);
1088 of_node_put(syscon_node);
1092 static int sun8i_dwmac_probe(struct platform_device *pdev)
1094 struct plat_stmmacenet_data *plat_dat;
1095 struct stmmac_resources stmmac_res;
1096 struct sunxi_priv_data *gmac;
1097 struct device *dev = &pdev->dev;
1099 struct stmmac_priv *priv;
1100 struct net_device *ndev;
1101 struct regmap *regmap;
1103 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1107 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1108 if (IS_ERR(plat_dat))
1109 return PTR_ERR(plat_dat);
1111 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1115 gmac->variant = of_device_get_match_data(&pdev->dev);
1116 if (!gmac->variant) {
1117 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1121 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
1122 if (IS_ERR(gmac->tx_clk)) {
1123 dev_err(dev, "Could not get TX clock\n");
1124 return PTR_ERR(gmac->tx_clk);
1127 /* Optional regulator for PHY */
1128 gmac->regulator = devm_regulator_get_optional(dev, "phy");
1129 if (IS_ERR(gmac->regulator)) {
1130 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1131 return -EPROBE_DEFER;
1132 dev_info(dev, "No regulator found\n");
1133 gmac->regulator = NULL;
1136 /* The "GMAC clock control" register might be located in the
1137 * CCU address range (on the R40), or the system control address
1138 * range (on most other sun8i and later SoCs).
1140 * The former controls most if not all clocks in the SoC. The
1141 * latter has an SoC identification register, and on some SoCs,
1142 * controls to map device specific SRAM to either the intended
1143 * peripheral, or the CPU address space.
1145 * In either case, there should be a coordinated and restricted
1146 * method of accessing the register needed here. This is done by
1147 * having the device export a custom regmap, instead of a generic
1148 * syscon, which grants all access to all registers.
1150 * To support old device trees, we fall back to using the syscon
1151 * interface if possible.
1153 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1155 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1157 if (IS_ERR(regmap)) {
1158 ret = PTR_ERR(regmap);
1159 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1163 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1164 *gmac->variant->syscon_field);
1165 if (IS_ERR(gmac->regmap_field)) {
1166 ret = PTR_ERR(gmac->regmap_field);
1167 dev_err(dev, "Unable to map syscon register: %d\n", ret);
1171 plat_dat->interface = of_get_phy_mode(dev->of_node);
1173 /* platform data specifying hardware features and callbacks.
1174 * hardware features were copied from Allwinner drivers.
1176 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1177 plat_dat->tx_coe = 1;
1178 plat_dat->has_sun8i = true;
1179 plat_dat->bsp_priv = gmac;
1180 plat_dat->init = sun8i_dwmac_init;
1181 plat_dat->exit = sun8i_dwmac_exit;
1182 plat_dat->setup = sun8i_dwmac_setup;
1183 plat_dat->tx_fifo_size = 4096;
1184 plat_dat->rx_fifo_size = 16384;
1186 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1190 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1194 ndev = dev_get_drvdata(&pdev->dev);
1195 priv = netdev_priv(ndev);
1196 /* The mux must be registered after parent MDIO
1197 * so after stmmac_dvr_probe()
1199 if (gmac->variant->soc_has_internal_phy) {
1200 ret = get_ephy_nodes(priv);
1203 ret = sun8i_dwmac_register_mdio_mux(priv);
1205 dev_err(&pdev->dev, "Failed to register mux\n");
1209 ret = sun8i_dwmac_reset(priv);
1216 reset_control_put(gmac->rst_ephy);
1217 clk_put(gmac->ephy_clk);
1218 sun8i_dwmac_unset_syscon(gmac);
1220 stmmac_pltfr_remove(pdev);
1224 static int sun8i_dwmac_remove(struct platform_device *pdev)
1226 struct net_device *ndev = platform_get_drvdata(pdev);
1227 struct stmmac_priv *priv = netdev_priv(ndev);
1228 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1230 if (gmac->variant->soc_has_internal_phy) {
1231 mdio_mux_uninit(gmac->mux_handle);
1232 sun8i_dwmac_unpower_internal_phy(gmac);
1233 reset_control_put(gmac->rst_ephy);
1234 clk_put(gmac->ephy_clk);
1237 stmmac_pltfr_remove(pdev);
1242 static const struct of_device_id sun8i_dwmac_match[] = {
1243 { .compatible = "allwinner,sun8i-h3-emac",
1244 .data = &emac_variant_h3 },
1245 { .compatible = "allwinner,sun8i-v3s-emac",
1246 .data = &emac_variant_v3s },
1247 { .compatible = "allwinner,sun8i-a83t-emac",
1248 .data = &emac_variant_a83t },
1249 { .compatible = "allwinner,sun8i-r40-gmac",
1250 .data = &emac_variant_r40 },
1251 { .compatible = "allwinner,sun50i-a64-emac",
1252 .data = &emac_variant_a64 },
1255 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1257 static struct platform_driver sun8i_dwmac_driver = {
1258 .probe = sun8i_dwmac_probe,
1259 .remove = sun8i_dwmac_remove,
1261 .name = "dwmac-sun8i",
1262 .pm = &stmmac_pltfr_pm_ops,
1263 .of_match_table = sun8i_dwmac_match,
1266 module_platform_driver(sun8i_dwmac_driver);
1268 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1269 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1270 MODULE_LICENSE("GPL");