1 /*******************************************************************************
2 This is the driver for the MAC 10/100 on-chip Ethernet controller
3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
8 This only implements the mac core functions for this chip.
10 Copyright (C) 2007-2009 STMicroelectronics Ltd
12 This program is free software; you can redistribute it and/or modify it
13 under the terms and conditions of the GNU General Public License,
14 version 2, as published by the Free Software Foundation.
16 This program is distributed in the hope it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 The full GNU General Public License is included in this distribution in
22 the file called "COPYING".
24 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/crc32.h>
33 static void dwmac100_core_init(struct mac_device_info *hw,
34 struct net_device *dev)
36 void __iomem *ioaddr = hw->pcsr;
37 u32 value = readl(ioaddr + MAC_CONTROL);
39 value |= MAC_CORE_INIT;
41 /* Clear ASTP bit because Ethernet switch tagging formats such as
42 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
43 * hardware to truncate packets on reception.
45 if (netdev_uses_dsa(dev))
46 value &= ~MAC_CONTROL_ASTP;
48 writel(value, ioaddr + MAC_CONTROL);
50 #ifdef STMMAC_VLAN_TAG_USED
51 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
55 static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
57 void __iomem *ioaddr = hw->pcsr;
59 reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
60 reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
61 reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
62 reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
63 reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
64 reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
65 reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
66 reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
69 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
74 static int dwmac100_irq_status(struct mac_device_info *hw,
75 struct stmmac_extra_stats *x)
80 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
84 void __iomem *ioaddr = hw->pcsr;
85 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
88 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
92 void __iomem *ioaddr = hw->pcsr;
93 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
96 static void dwmac100_set_filter(struct mac_device_info *hw,
97 struct net_device *dev)
99 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
100 u32 value = readl(ioaddr + MAC_CONTROL);
102 if (dev->flags & IFF_PROMISC) {
103 value |= MAC_CONTROL_PR;
104 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
106 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
107 || (dev->flags & IFF_ALLMULTI)) {
108 value |= MAC_CONTROL_PM;
109 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
110 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
111 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
112 } else if (netdev_mc_empty(dev)) { /* no multicast */
113 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
114 MAC_CONTROL_HO | MAC_CONTROL_HP);
117 struct netdev_hw_addr *ha;
119 /* Perfect filter mode for physical address and Hash
120 * filter for multicast
122 value |= MAC_CONTROL_HP;
123 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
124 MAC_CONTROL_IF | MAC_CONTROL_HO);
126 memset(mc_filter, 0, sizeof(mc_filter));
127 netdev_for_each_mc_addr(ha, dev) {
128 /* The upper 6 bits of the calculated CRC are used to
129 * index the contens of the hash table
131 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
132 /* The most significant bit determines the register to
133 * use (H/L) while the other 5 bits determine the bit
134 * within the register.
136 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
138 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
139 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
142 writel(value, ioaddr + MAC_CONTROL);
145 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
146 unsigned int fc, unsigned int pause_time,
149 void __iomem *ioaddr = hw->pcsr;
150 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
153 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
154 writel(flow, ioaddr + MAC_FLOW_CTRL);
157 /* No PMT module supported on ST boards with this Eth chip. */
158 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
163 const struct stmmac_ops dwmac100_ops = {
164 .core_init = dwmac100_core_init,
165 .set_mac = stmmac_set_mac,
166 .rx_ipc = dwmac100_rx_ipc_enable,
167 .dump_regs = dwmac100_dump_mac_regs,
168 .host_irq_status = dwmac100_irq_status,
169 .set_filter = dwmac100_set_filter,
170 .flow_ctrl = dwmac100_flow_ctrl,
172 .set_umac_addr = dwmac100_set_umac_addr,
173 .get_umac_addr = dwmac100_get_umac_addr,
176 int dwmac100_setup(struct stmmac_priv *priv)
178 struct mac_device_info *mac = priv->hw;
180 dev_info(priv->device, "\tDWMAC100\n");
182 mac->pcsr = priv->ioaddr;
183 mac->link.duplex = MAC_CONTROL_F;
184 mac->link.speed10 = 0;
185 mac->link.speed100 = 0;
186 mac->link.speed1000 = 0;
187 mac->link.speed_mask = MAC_CONTROL_PS;
188 mac->mii.addr = MAC_MII_ADDR;
189 mac->mii.data = MAC_MII_DATA;
190 mac->mii.addr_shift = 11;
191 mac->mii.addr_mask = 0x0000F800;
192 mac->mii.reg_shift = 6;
193 mac->mii.reg_mask = 0x000007C0;
194 mac->mii.clk_csr_shift = 2;
195 mac->mii.clk_csr_mask = GENMASK(5, 2);