drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include <net/dsa.h>
  21 #include "stmmac_pcs.h"
  22 #include "dwmac4.h"
  23
  24 static void dwmac4_core_init(struct mac_device_info *hw,
  25                              struct net_device *dev)
  26 {
  27         void __iomem *ioaddr = hw->pcsr;
  28         u32 value = readl(ioaddr + GMAC_CONFIG);
  29         int mtu = dev->mtu;
  30
  31         value |= GMAC_CORE_INIT;
  32
  33         if (mtu > 1500)
  34                 value |= GMAC_CONFIG_2K;
  35         if (mtu > 2000)
  36                 value |= GMAC_CONFIG_JE;
  37
  38         if (hw->ps) {
  39                 value |= GMAC_CONFIG_TE;
  40
  41                 value &= hw->link.speed_mask;
  42                 switch (hw->ps) {
  43                 case SPEED_1000:
  44                         value |= hw->link.speed1000;
  45                         break;
  46                 case SPEED_100:
  47                         value |= hw->link.speed100;
  48                         break;
  49                 case SPEED_10:
  50                         value |= hw->link.speed10;
  51                         break;
  52                 }
  53         }
  54
  55         writel(value, ioaddr + GMAC_CONFIG);
  56
  57         /* Mask GMAC interrupts */
  58         value = GMAC_INT_DEFAULT_MASK;
  59         if (hw->pmt)
  60                 value |= GMAC_INT_PMT_EN;
  61         if (hw->pcs)
  62                 value |= GMAC_PCS_IRQ_DEFAULT;
  63
  64         writel(value, ioaddr + GMAC_INT_EN);
  65 }
  66
  67 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  68                                    u8 mode, u32 queue)
  69 {
  70         void __iomem *ioaddr = hw->pcsr;
  71         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  72
  73         value &= GMAC_RX_QUEUE_CLEAR(queue);
  74         if (mode == MTL_QUEUE_AVB)
  75                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  76         else if (mode == MTL_QUEUE_DCB)
  77                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  78
  79         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  80 }
  81
  82 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  83                                      u32 prio, u32 queue)
  84 {
  85         void __iomem *ioaddr = hw->pcsr;
  86         u32 base_register;
  87         u32 value;
  88
  89         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  90
  91         value = readl(ioaddr + base_register);
  92
  93         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
  94         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
  95                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
  96         writel(value, ioaddr + base_register);
  97 }
  98
  99 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 100                                      u32 prio, u32 queue)
 101 {
 102         void __iomem *ioaddr = hw->pcsr;
 103         u32 base_register;
 104         u32 value;
 105
 106         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 107
 108         value = readl(ioaddr + base_register);
 109
 110         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 111         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 112                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 113
 114         writel(value, ioaddr + base_register);
 115 }
 116
 117 static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
 118                                     u8 packet, u32 queue)
 119 {
 120         void __iomem *ioaddr = hw->pcsr;
 121         u32 value;
 122
 123         static const struct stmmac_rx_routing route_possibilities[] = {
 124                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 125                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 126                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 127                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 128                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 129         };
 130
 131         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 132
 133         /* routing configuration */
 134         value &= ~route_possibilities[packet - 1].reg_mask;
 135         value |= (queue << route_possibilities[packet-1].reg_shift) &
 136                  route_possibilities[packet - 1].reg_mask;
 137
 138         /* some packets require extra ops */
 139         if (packet == PACKET_AVCPQ) {
 140                 value &= ~GMAC_RXQCTRL_TACPQE;
 141                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 142         } else if (packet == PACKET_MCBCQ) {
 143                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 144                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 145         }
 146
 147         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 148 }
 149
 150 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 151                                           u32 rx_alg)
 152 {
 153         void __iomem *ioaddr = hw->pcsr;
 154         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 155
 156         value &= ~MTL_OPERATION_RAA;
 157         switch (rx_alg) {
 158         case MTL_RX_ALGORITHM_SP:
 159                 value |= MTL_OPERATION_RAA_SP;
 160                 break;
 161         case MTL_RX_ALGORITHM_WSP:
 162                 value |= MTL_OPERATION_RAA_WSP;
 163                 break;
 164         default:
 165                 break;
 166         }
 167
 168         writel(value, ioaddr + MTL_OPERATION_MODE);
 169 }
 170
 171 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 172                                           u32 tx_alg)
 173 {
 174         void __iomem *ioaddr = hw->pcsr;
 175         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 176
 177         value &= ~MTL_OPERATION_SCHALG_MASK;
 178         switch (tx_alg) {
 179         case MTL_TX_ALGORITHM_WRR:
 180                 value |= MTL_OPERATION_SCHALG_WRR;
 181                 break;
 182         case MTL_TX_ALGORITHM_WFQ:
 183                 value |= MTL_OPERATION_SCHALG_WFQ;
 184                 break;
 185         case MTL_TX_ALGORITHM_DWRR:
 186                 value |= MTL_OPERATION_SCHALG_DWRR;
 187                 break;
 188         case MTL_TX_ALGORITHM_SP:
 189                 value |= MTL_OPERATION_SCHALG_SP;
 190                 break;
 191         default:
 192                 break;
 193         }
 194 }
 195
 196 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 197                                            u32 weight, u32 queue)
 198 {
 199         void __iomem *ioaddr = hw->pcsr;
 200         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 201
 202         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 203         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 204         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 205 }
 206
 207 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 208 {
 209         void __iomem *ioaddr = hw->pcsr;
 210         u32 value;
 211
 212         if (queue < 4)
 213                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 214         else
 215                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 216
 217         if (queue == 0 || queue == 4) {
 218                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 219                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 220         } else {
 221                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 222                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 223         }
 224
 225         if (queue < 4)
 226                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 227         else
 228                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 229 }
 230
 231 static void dwmac4_config_cbs(struct mac_device_info *hw,
 232                               u32 send_slope, u32 idle_slope,
 233                               u32 high_credit, u32 low_credit, u32 queue)
 234 {
 235         void __iomem *ioaddr = hw->pcsr;
 236         u32 value;
 237
 238         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 239         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 240         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 241         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 242         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 243
 244         /* enable AV algorithm */
 245         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 246         value |= MTL_ETS_CTRL_AVALG;
 247         value |= MTL_ETS_CTRL_CC;
 248         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 249
 250         /* configure send slope */
 251         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 252         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 253         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 254         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 255
 256         /* configure idle slope (same register as tx weight) */
 257         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 258
 259         /* configure high credit */
 260         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 261         value &= ~MTL_HIGH_CRED_HC_MASK;
 262         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 263         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 264
 265         /* configure high credit */
 266         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 267         value &= ~MTL_HIGH_CRED_LC_MASK;
 268         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 269         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 270 }
 271
 272 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 273 {
 274         void __iomem *ioaddr = hw->pcsr;
 275         int i;
 276
 277         for (i = 0; i < GMAC_REG_NUM; i++)
 278                 reg_space[i] = readl(ioaddr + i * 4);
 279 }
 280
 281 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 282 {
 283         void __iomem *ioaddr = hw->pcsr;
 284         u32 value = readl(ioaddr + GMAC_CONFIG);
 285
 286         if (hw->rx_csum)
 287                 value |= GMAC_CONFIG_IPC;
 288         else
 289                 value &= ~GMAC_CONFIG_IPC;
 290
 291         writel(value, ioaddr + GMAC_CONFIG);
 292
 293         value = readl(ioaddr + GMAC_CONFIG);
 294
 295         return !!(value & GMAC_CONFIG_IPC);
 296 }
 297
 298 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 299 {
 300         void __iomem *ioaddr = hw->pcsr;
 301         unsigned int pmt = 0;
 302         u32 config;
 303
 304         if (mode & WAKE_MAGIC) {
 305                 pr_debug("GMAC: WOL Magic frame\n");
 306                 pmt |= power_down | magic_pkt_en;
 307         }
 308         if (mode & WAKE_UCAST) {
 309                 pr_debug("GMAC: WOL on global unicast\n");
 310                 pmt |= power_down | global_unicast | wake_up_frame_en;
 311         }
 312
 313         if (pmt) {
 314                 /* The receiver must be enabled for WOL before powering down */
 315                 config = readl(ioaddr + GMAC_CONFIG);
 316                 config |= GMAC_CONFIG_RE;
 317                 writel(config, ioaddr + GMAC_CONFIG);
 318         }
 319         writel(pmt, ioaddr + GMAC_PMT);
 320 }
 321
 322 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 323                                  unsigned char *addr, unsigned int reg_n)
 324 {
 325         void __iomem *ioaddr = hw->pcsr;
 326
 327         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 328                                    GMAC_ADDR_LOW(reg_n));
 329 }
 330
 331 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 332                                  unsigned char *addr, unsigned int reg_n)
 333 {
 334         void __iomem *ioaddr = hw->pcsr;
 335
 336         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 337                                    GMAC_ADDR_LOW(reg_n));
 338 }
 339
 340 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 341                                 bool en_tx_lpi_clockgating)
 342 {
 343         void __iomem *ioaddr = hw->pcsr;
 344         u32 value;
 345
 346         /* Enable the link status receive on RGMII, SGMII ore SMII
 347          * receive path and instruct the transmit to enter in LPI
 348          * state.
 349          */
 350         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 351         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 352
 353         if (en_tx_lpi_clockgating)
 354                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 355
 356         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 357 }
 358
 359 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 360 {
 361         void __iomem *ioaddr = hw->pcsr;
 362         u32 value;
 363
 364         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 365         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 366         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 367 }
 368
 369 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 370 {
 371         void __iomem *ioaddr = hw->pcsr;
 372         u32 value;
 373
 374         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 375
 376         if (link)
 377                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 378         else
 379                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 380
 381         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 382 }
 383
 384 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 385 {
 386         void __iomem *ioaddr = hw->pcsr;
 387         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 388
 389         /* Program the timers in the LPI timer control register:
 390          * LS: minimum time (ms) for which the link
 391          *  status from PHY should be ok before transmitting
 392          *  the LPI pattern.
 393          * TW: minimum time (us) for which the core waits
 394          *  after it has stopped transmitting the LPI pattern.
 395          */
 396         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 397 }
 398
 399 static void dwmac4_set_filter(struct mac_device_info *hw,
 400                               struct net_device *dev)
 401 {
 402         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 403         unsigned int value = 0;
 404
 405         if (dev->flags & IFF_PROMISC) {
 406                 value = GMAC_PACKET_FILTER_PR;
 407         } else if ((dev->flags & IFF_ALLMULTI) ||
 408                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 409                 /* Pass all multi */
 410                 value = GMAC_PACKET_FILTER_PM;
 411                 /* Set the 64 bits of the HASH tab. To be updated if taller
 412                  * hash table is used
 413                  */
 414                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 415                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 416         } else if (!netdev_mc_empty(dev)) {
 417                 u32 mc_filter[2];
 418                 struct netdev_hw_addr *ha;
 419
 420                 /* Hash filter for multicast */
 421                 value = GMAC_PACKET_FILTER_HMC;
 422
 423                 memset(mc_filter, 0, sizeof(mc_filter));
 424                 netdev_for_each_mc_addr(ha, dev) {
 425                         /* The upper 6 bits of the calculated CRC are used to
 426                          * index the content of the Hash Table Reg 0 and 1.
 427                          */
 428                         int bit_nr =
 429                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 430                         /* The most significant bit determines the register
 431                          * to use while the other 5 bits determines the bit
 432                          * within the selected register
 433                          */
 434                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 435                 }
 436                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 437                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 438         }
 439
 440         /* Handle multiple unicast addresses */
 441         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 442                 /* Switch to promiscuous mode if more than 128 addrs
 443                  * are required
 444                  */
 445                 value |= GMAC_PACKET_FILTER_PR;
 446         } else {
 447                 struct netdev_hw_addr *ha;
 448                 int reg = 1;
 449
 450                 netdev_for_each_uc_addr(ha, dev) {
 451                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 452                         reg++;
 453                 }
 454
 455                 while (reg <= GMAC_MAX_PERFECT_ADDRESSES) {
 456                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 457                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 458                         reg++;
 459                 }
 460         }
 461
 462         writel(value, ioaddr + GMAC_PACKET_FILTER);
 463 }
 464
 465 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 466                              unsigned int fc, unsigned int pause_time,
 467                              u32 tx_cnt)
 468 {
 469         void __iomem *ioaddr = hw->pcsr;
 470         unsigned int flow = 0;
 471         u32 queue = 0;
 472
 473         pr_debug("GMAC Flow-Control:\n");
 474         if (fc & FLOW_RX) {
 475                 pr_debug("\tReceive Flow-Control ON\n");
 476                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 477         }
 478         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 479
 480         if (fc & FLOW_TX) {
 481                 pr_debug("\tTransmit Flow-Control ON\n");
 482
 483                 if (duplex)
 484                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 485
 486                 for (queue = 0; queue < tx_cnt; queue++) {
 487                         flow = GMAC_TX_FLOW_CTRL_TFE;
 488
 489                         if (duplex)
 490                                 flow |=
 491                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 492
 493                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 494                 }
 495         } else {
 496                 for (queue = 0; queue < tx_cnt; queue++)
 497                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 498         }
 499 }
 500
 501 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 502                             bool loopback)
 503 {
 504         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 505 }
 506
 507 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 508 {
 509         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 510 }
 511
 512 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 513 {
 514         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 515 }
 516
 517 /* RGMII or SMII interface */
 518 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 519 {
 520         u32 status;
 521
 522         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 523         x->irq_rgmii_n++;
 524
 525         /* Check the link status */
 526         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 527                 int speed_value;
 528
 529                 x->pcs_link = 1;
 530
 531                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 532                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 533                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 534                         x->pcs_speed = SPEED_1000;
 535                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 536                         x->pcs_speed = SPEED_100;
 537                 else
 538                         x->pcs_speed = SPEED_10;
 539
 540                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 541
 542                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 543                         x->pcs_duplex ? "Full" : "Half");
 544         } else {
 545                 x->pcs_link = 0;
 546                 pr_info("Link is Down\n");
 547         }
 548 }
 549
 550 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 551 {
 552         void __iomem *ioaddr = hw->pcsr;
 553         u32 mtl_int_qx_status;
 554         int ret = 0;
 555
 556         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 557
 558         /* Check MTL Interrupt */
 559         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 560                 /* read Queue x Interrupt status */
 561                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 562
 563                 if (status & MTL_RX_OVERFLOW_INT) {
 564                         /*  clear Interrupt */
 565                         writel(status | MTL_RX_OVERFLOW_INT,
 566                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 567                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 568                 }
 569         }
 570
 571         return ret;
 572 }
 573
 574 static int dwmac4_irq_status(struct mac_device_info *hw,
 575                              struct stmmac_extra_stats *x)
 576 {
 577         void __iomem *ioaddr = hw->pcsr;
 578         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 579         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 580         int ret = 0;
 581
 582         /* Discard disabled bits */
 583         intr_status &= intr_enable;
 584
 585         /* Not used events (e.g. MMC interrupts) are not handled. */
 586         if ((intr_status & mmc_tx_irq))
 587                 x->mmc_tx_irq_n++;
 588         if (unlikely(intr_status & mmc_rx_irq))
 589                 x->mmc_rx_irq_n++;
 590         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 591                 x->mmc_rx_csum_offload_irq_n++;
 592         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 593         if (unlikely(intr_status & pmt_irq)) {
 594                 readl(ioaddr + GMAC_PMT);
 595                 x->irq_receive_pmt_irq_n++;
 596         }
 597
 598         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 599         if (intr_status & PCS_RGSMIIIS_IRQ)
 600                 dwmac4_phystatus(ioaddr, x);
 601
 602         return ret;
 603 }
 604
 605 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 606                          u32 rx_queues, u32 tx_queues)
 607 {
 608         u32 value;
 609         u32 queue;
 610
 611         for (queue = 0; queue < tx_queues; queue++) {
 612                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 613
 614                 if (value & MTL_DEBUG_TXSTSFSTS)
 615                         x->mtl_tx_status_fifo_full++;
 616                 if (value & MTL_DEBUG_TXFSTS)
 617                         x->mtl_tx_fifo_not_empty++;
 618                 if (value & MTL_DEBUG_TWCSTS)
 619                         x->mmtl_fifo_ctrl++;
 620                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 621                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 622                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 623                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 624                                 x->mtl_tx_fifo_read_ctrl_write++;
 625                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 626                                 x->mtl_tx_fifo_read_ctrl_wait++;
 627                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 628                                 x->mtl_tx_fifo_read_ctrl_read++;
 629                         else
 630                                 x->mtl_tx_fifo_read_ctrl_idle++;
 631                 }
 632                 if (value & MTL_DEBUG_TXPAUSED)
 633                         x->mac_tx_in_pause++;
 634         }
 635
 636         for (queue = 0; queue < rx_queues; queue++) {
 637                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 638
 639                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 640                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 641                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 642
 643                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 644                                 x->mtl_rx_fifo_fill_level_full++;
 645                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 646                                 x->mtl_rx_fifo_fill_above_thresh++;
 647                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 648                                 x->mtl_rx_fifo_fill_below_thresh++;
 649                         else
 650                                 x->mtl_rx_fifo_fill_level_empty++;
 651                 }
 652                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 653                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 654                                      MTL_DEBUG_RRCSTS_SHIFT;
 655
 656                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 657                                 x->mtl_rx_fifo_read_ctrl_flush++;
 658                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 659                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 660                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 661                                 x->mtl_rx_fifo_read_ctrl_status++;
 662                         else
 663                                 x->mtl_rx_fifo_read_ctrl_idle++;
 664                 }
 665                 if (value & MTL_DEBUG_RWCSTS)
 666                         x->mtl_rx_fifo_ctrl_active++;
 667         }
 668
 669         /* GMAC debug */
 670         value = readl(ioaddr + GMAC_DEBUG);
 671
 672         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 673                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 674                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 675
 676                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 677                         x->mac_tx_frame_ctrl_xfer++;
 678                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 679                         x->mac_tx_frame_ctrl_pause++;
 680                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 681                         x->mac_tx_frame_ctrl_wait++;
 682                 else
 683                         x->mac_tx_frame_ctrl_idle++;
 684         }
 685         if (value & GMAC_DEBUG_TPESTS)
 686                 x->mac_gmii_tx_proto_engine++;
 687         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 688                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 689                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 690         if (value & GMAC_DEBUG_RPESTS)
 691                 x->mac_gmii_rx_proto_engine++;
 692 }
 693
 694 static const struct stmmac_ops dwmac4_ops = {
 695         .core_init = dwmac4_core_init,
 696         .set_mac = stmmac_set_mac,
 697         .rx_ipc = dwmac4_rx_ipc_enable,
 698         .rx_queue_enable = dwmac4_rx_queue_enable,
 699         .rx_queue_prio = dwmac4_rx_queue_priority,
 700         .tx_queue_prio = dwmac4_tx_queue_priority,
 701         .rx_queue_routing = dwmac4_tx_queue_routing,
 702         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 703         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 704         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 705         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 706         .config_cbs = dwmac4_config_cbs,
 707         .dump_regs = dwmac4_dump_regs,
 708         .host_irq_status = dwmac4_irq_status,
 709         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 710         .flow_ctrl = dwmac4_flow_ctrl,
 711         .pmt = dwmac4_pmt,
 712         .set_umac_addr = dwmac4_set_umac_addr,
 713         .get_umac_addr = dwmac4_get_umac_addr,
 714         .set_eee_mode = dwmac4_set_eee_mode,
 715         .reset_eee_mode = dwmac4_reset_eee_mode,
 716         .set_eee_timer = dwmac4_set_eee_timer,
 717         .set_eee_pls = dwmac4_set_eee_pls,
 718         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 719         .pcs_rane = dwmac4_rane,
 720         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 721         .debug = dwmac4_debug,
 722         .set_filter = dwmac4_set_filter,
 723 };
 724
 725 static const struct stmmac_ops dwmac410_ops = {
 726         .core_init = dwmac4_core_init,
 727         .set_mac = stmmac_dwmac4_set_mac,
 728         .rx_ipc = dwmac4_rx_ipc_enable,
 729         .rx_queue_enable = dwmac4_rx_queue_enable,
 730         .rx_queue_prio = dwmac4_rx_queue_priority,
 731         .tx_queue_prio = dwmac4_tx_queue_priority,
 732         .rx_queue_routing = dwmac4_tx_queue_routing,
 733         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 734         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 735         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 736         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 737         .config_cbs = dwmac4_config_cbs,
 738         .dump_regs = dwmac4_dump_regs,
 739         .host_irq_status = dwmac4_irq_status,
 740         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 741         .flow_ctrl = dwmac4_flow_ctrl,
 742         .pmt = dwmac4_pmt,
 743         .set_umac_addr = dwmac4_set_umac_addr,
 744         .get_umac_addr = dwmac4_get_umac_addr,
 745         .set_eee_mode = dwmac4_set_eee_mode,
 746         .reset_eee_mode = dwmac4_reset_eee_mode,
 747         .set_eee_timer = dwmac4_set_eee_timer,
 748         .set_eee_pls = dwmac4_set_eee_pls,
 749         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 750         .pcs_rane = dwmac4_rane,
 751         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 752         .debug = dwmac4_debug,
 753         .set_filter = dwmac4_set_filter,
 754 };
 755
 756 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 757                                      int perfect_uc_entries, int *synopsys_id)
 758 {
 759         struct mac_device_info *mac;
 760         u32 hwid = readl(ioaddr + GMAC_VERSION);
 761
 762         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 763         if (!mac)
 764                 return NULL;
 765
 766         mac->pcsr = ioaddr;
 767         mac->multicast_filter_bins = mcbins;
 768         mac->unicast_filter_entries = perfect_uc_entries;
 769         mac->mcast_bits_log2 = 0;
 770
 771         if (mac->multicast_filter_bins)
 772                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 773
 774         mac->link.duplex = GMAC_CONFIG_DM;
 775         mac->link.speed10 = GMAC_CONFIG_PS;
 776         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 777         mac->link.speed1000 = 0;
 778         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 779         mac->mii.addr = GMAC_MDIO_ADDR;
 780         mac->mii.data = GMAC_MDIO_DATA;
 781         mac->mii.addr_shift = 21;
 782         mac->mii.addr_mask = GENMASK(25, 21);
 783         mac->mii.reg_shift = 16;
 784         mac->mii.reg_mask = GENMASK(20, 16);
 785         mac->mii.clk_csr_shift = 8;
 786         mac->mii.clk_csr_mask = GENMASK(11, 8);
 787
 788         /* Get and dump the chip ID */
 789         *synopsys_id = stmmac_get_synopsys_id(hwid);
 790
 791         if (*synopsys_id > DWMAC_CORE_4_00)
 792                 mac->dma = &dwmac410_dma_ops;
 793         else
 794                 mac->dma = &dwmac4_dma_ops;
 795
 796         if (*synopsys_id >= DWMAC_CORE_4_00)
 797                 mac->mac = &dwmac410_ops;
 798         else
 799                 mac->mac = &dwmac4_ops;
 800
 801         return mac;
 802 }