2 * This contains the functions to handle the descriptors for DesignWare databook
5 * Copyright (C) 2015 STMicroelectronics Ltd
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * Author: Alexandre Torgue <alexandre.torgue@st.com>
14 #include <linux/stmmac.h>
16 #include "dwmac4_descs.h"
18 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
22 struct net_device_stats *stats = (struct net_device_stats *)data;
28 /* Get tx owner first */
29 if (unlikely(tdes3 & TDES3_OWN))
32 /* Verify tx error by looking at the last segment. */
33 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
36 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
37 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
39 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
40 x->tx_frame_flushed++;
41 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
43 stats->tx_carrier_errors++;
45 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
47 stats->tx_carrier_errors++;
49 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
50 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
52 (tdes3 & TDES3_COLLISION_COUNT_MASK)
53 >> TDES3_COLLISION_COUNT_SHIFT;
55 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
58 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
61 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
62 x->tx_ip_header_error++;
64 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
65 x->tx_payload_error++;
70 if (unlikely(tdes3 & TDES3_DEFERRED))
76 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
79 struct net_device_stats *stats = (struct net_device_stats *)data;
80 unsigned int rdes1 = p->des1;
81 unsigned int rdes2 = p->des2;
82 unsigned int rdes3 = p->des3;
86 if (unlikely(rdes3 & RDES3_OWN))
89 /* Verify rx error by looking at the last segment. */
90 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
93 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
94 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
95 stats->rx_length_errors++;
96 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
97 x->rx_gmac_overflow++;
99 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
102 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
105 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
107 stats->rx_crc_errors++;
110 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
116 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
118 if (rdes1 & RDES1_IP_HDR_ERROR)
120 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
121 x->ip_csum_bypassed++;
122 if (rdes1 & RDES1_IPV4_HEADER)
124 if (rdes1 & RDES1_IPV6_HEADER)
127 if (message_type == RDES_EXT_NO_PTP)
128 x->no_ptp_rx_msg_type_ext++;
129 else if (message_type == RDES_EXT_SYNC)
130 x->ptp_rx_msg_type_sync++;
131 else if (message_type == RDES_EXT_FOLLOW_UP)
132 x->ptp_rx_msg_type_follow_up++;
133 else if (message_type == RDES_EXT_DELAY_REQ)
134 x->ptp_rx_msg_type_delay_req++;
135 else if (message_type == RDES_EXT_DELAY_RESP)
136 x->ptp_rx_msg_type_delay_resp++;
137 else if (message_type == RDES_EXT_PDELAY_REQ)
138 x->ptp_rx_msg_type_pdelay_req++;
139 else if (message_type == RDES_EXT_PDELAY_RESP)
140 x->ptp_rx_msg_type_pdelay_resp++;
141 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
142 x->ptp_rx_msg_type_pdelay_follow_up++;
143 else if (message_type == RDES_PTP_ANNOUNCE)
144 x->ptp_rx_msg_type_announce++;
145 else if (message_type == RDES_PTP_MANAGEMENT)
146 x->ptp_rx_msg_type_management++;
147 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
148 x->ptp_rx_msg_pkt_reserved_type++;
150 if (rdes1 & RDES1_PTP_PACKET_TYPE)
152 if (rdes1 & RDES1_PTP_VER)
154 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
155 x->timestamp_dropped++;
157 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
158 x->sa_rx_filter_fail++;
161 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
162 x->da_rx_filter_fail++;
166 if (rdes2 & RDES2_L3_FILTER_MATCH)
167 x->l3_filter_match++;
168 if (rdes2 & RDES2_L4_FILTER_MATCH)
169 x->l4_filter_match++;
170 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
171 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
172 x->l3_l4_filter_no_match++;
177 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
179 return (p->des2 & TDES2_BUFFER1_SIZE_MASK);
182 static int dwmac4_get_tx_owner(struct dma_desc *p)
184 return (p->des3 & TDES3_OWN) >> TDES3_OWN_SHIFT;
187 static void dwmac4_set_tx_owner(struct dma_desc *p)
189 p->des3 |= TDES3_OWN;
192 static void dwmac4_set_rx_owner(struct dma_desc *p)
194 p->des3 |= RDES3_OWN;
197 static int dwmac4_get_tx_ls(struct dma_desc *p)
199 return (p->des3 & TDES3_LAST_DESCRIPTOR) >> TDES3_LAST_DESCRIPTOR_SHIFT;
202 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
204 return (p->des3 & RDES3_PACKET_SIZE_MASK);
207 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
209 p->des2 |= TDES2_TIMESTAMP_ENABLE;
212 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
214 /* Context type from W/B descriptor must be zero */
215 if (p->des3 & TDES3_CONTEXT_TYPE)
218 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
219 if (p->des3 & TDES3_TIMESTAMP_STATUS)
225 static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
227 struct dma_desc *p = (struct dma_desc *)desc;
231 /* convert high/sec time stamp value to nanosecond */
232 ns += p->des1 * 1000000000ULL;
237 static int dwmac4_rx_check_timestamp(void *desc)
239 struct dma_desc *p = (struct dma_desc *)desc;
243 own = p->des3 & RDES3_OWN;
244 ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
245 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
247 if (likely(!own && ctxt)) {
248 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
249 /* Corrupted value */
252 /* A valid Timestamp is ready to be read */
256 /* Timestamp not ready */
260 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, u32 ats)
262 struct dma_desc *p = (struct dma_desc *)desc;
265 /* Get the status from normal w/b descriptor */
266 if (likely(p->des3 & TDES3_RS1V)) {
267 if (likely(p->des1 & RDES1_TIMESTAMP_AVAILABLE)) {
270 /* Check if timestamp is OK from context descriptor */
272 ret = dwmac4_rx_check_timestamp(desc);
277 } while ((ret == 1) || (i < 10));
287 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
290 p->des3 = RDES3_OWN | RDES3_BUFFER1_VALID_ADDR;
293 p->des3 |= RDES3_INT_ON_COMPLETION_EN;
296 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
304 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
305 bool csum_flag, int mode, bool tx_own,
308 unsigned int tdes3 = p->des3;
310 p->des2 |= (len & TDES2_BUFFER1_SIZE_MASK);
313 tdes3 |= TDES3_FIRST_DESCRIPTOR;
315 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
317 if (likely(csum_flag))
318 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
320 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
323 tdes3 |= TDES3_LAST_DESCRIPTOR;
325 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
327 /* Finally set the OWN bit. Later the DMA will start! */
332 /* When the own bit, for the first frame, has to be set, all
333 * descriptors for the same frame has to be set before, to
334 * avoid race condition.
341 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
342 int len1, int len2, bool tx_own,
343 bool ls, unsigned int tcphdrlen,
344 unsigned int tcppayloadlen)
346 unsigned int tdes3 = p->des3;
349 p->des2 |= (len1 & TDES2_BUFFER1_SIZE_MASK);
352 p->des2 |= (len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
353 & TDES2_BUFFER2_SIZE_MASK;
356 tdes3 |= TDES3_FIRST_DESCRIPTOR |
357 TDES3_TCP_SEGMENTATION_ENABLE |
358 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
359 TDES3_SLOT_NUMBER_MASK) |
360 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
362 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
366 tdes3 |= TDES3_LAST_DESCRIPTOR;
368 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
370 /* Finally set the OWN bit. Later the DMA will start! */
375 /* When the own bit, for the first frame, has to be set, all
376 * descriptors for the same frame has to be set before, to
377 * avoid race condition.
384 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
390 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
392 p->des2 |= TDES2_INTERRUPT_ON_COMPLETION;
395 static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
397 struct dma_desc *p = (struct dma_desc *)head;
400 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
402 for (i = 0; i < size; i++) {
403 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
404 i, (unsigned int)virt_to_phys(p),
405 p->des0, p->des1, p->des2, p->des3);
410 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
415 p->des3 = TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV;
418 const struct stmmac_desc_ops dwmac4_desc_ops = {
419 .tx_status = dwmac4_wrback_get_tx_status,
420 .rx_status = dwmac4_wrback_get_rx_status,
421 .get_tx_len = dwmac4_rd_get_tx_len,
422 .get_tx_owner = dwmac4_get_tx_owner,
423 .set_tx_owner = dwmac4_set_tx_owner,
424 .set_rx_owner = dwmac4_set_rx_owner,
425 .get_tx_ls = dwmac4_get_tx_ls,
426 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
427 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
428 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
429 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
430 .get_timestamp = dwmac4_get_timestamp,
431 .set_tx_ic = dwmac4_rd_set_tx_ic,
432 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
433 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
434 .release_tx_desc = dwmac4_release_tx_desc,
435 .init_rx_desc = dwmac4_rd_init_rx_desc,
436 .init_tx_desc = dwmac4_rd_init_tx_desc,
437 .display_ring = dwmac4_display_ring,
438 .set_mss = dwmac4_set_mss_ctxt,
441 const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };