drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  59 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  60
  61 /* Module parameters */
  62 #define TX_TIMEO        5000
  63 static int watchdog = TX_TIMEO;
  64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  66
  67 static int debug = -1;
  68 module_param(debug, int, S_IRUGO | S_IWUSR);
  69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  70
  71 static int phyaddr = -1;
  72 module_param(phyaddr, int, S_IRUGO);
  73 MODULE_PARM_DESC(phyaddr, "Physical device address");
  74
  75 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  76 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  77
  78 static int flow_ctrl = FLOW_OFF;
  79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  81
  82 static int pause = PAUSE_TIME;
  83 module_param(pause, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  85
  86 #define TC_DEFAULT 64
  87 static int tc = TC_DEFAULT;
  88 module_param(tc, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(tc, "DMA threshold control value");
  90
  91 #define DEFAULT_BUFSIZE 1536
  92 static int buf_sz = DEFAULT_BUFSIZE;
  93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  95
  96 #define STMMAC_RX_COPYBREAK     256
  97
  98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  99                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 100                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 101
 102 #define STMMAC_DEFAULT_LPI_TIMER        1000
 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 107
 108 /* By default the driver will use the ring mode to manage tx and rx descriptors
 109  * but passing this value so user can force to use the chain instead of the ring
 110  */
 111 static unsigned int chain_mode;
 112 module_param(chain_mode, int, S_IRUGO);
 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 114
 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 116
 117 #ifdef CONFIG_DEBUG_FS
 118 static int stmmac_init_fs(struct net_device *dev);
 119 static void stmmac_exit_fs(struct net_device *dev);
 120 #endif
 121
 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 123
 124 /**
 125  * stmmac_verify_args - verify the driver parameters.
 126  * Description: it checks the driver parameters and set a default in case of
 127  * errors.
 128  */
 129 static void stmmac_verify_args(void)
 130 {
 131         if (unlikely(watchdog < 0))
 132                 watchdog = TX_TIMEO;
 133         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 134                 buf_sz = DEFAULT_BUFSIZE;
 135         if (unlikely(flow_ctrl > 1))
 136                 flow_ctrl = FLOW_AUTO;
 137         else if (likely(flow_ctrl < 0))
 138                 flow_ctrl = FLOW_OFF;
 139         if (unlikely((pause < 0) || (pause > 0xffff)))
 140                 pause = PAUSE_TIME;
 141         if (eee_timer < 0)
 142                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 143 }
 144
 145 /**
 146  * stmmac_clk_csr_set - dynamically set the MDC clock
 147  * @priv: driver private structure
 148  * Description: this is to dynamically set the MDC clock according to the csr
 149  * clock input.
 150  * Note:
 151  *      If a specific clk_csr value is passed from the platform
 152  *      this means that the CSR Clock Range selection cannot be
 153  *      changed at run-time and it is fixed (as reported in the driver
 154  *      documentation). Viceversa the driver will try to set the MDC
 155  *      clock dynamically according to the actual clock input.
 156  */
 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 158 {
 159         u32 clk_rate;
 160
 161         clk_rate = clk_get_rate(priv->stmmac_clk);
 162
 163         /* Platform provided default clk_csr would be assumed valid
 164          * for all other cases except for the below mentioned ones.
 165          * For values higher than the IEEE 802.3 specified frequency
 166          * we can not estimate the proper divider as it is not known
 167          * the frequency of clk_csr_i. So we do not change the default
 168          * divider.
 169          */
 170         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 171                 if (clk_rate < CSR_F_35M)
 172                         priv->clk_csr = STMMAC_CSR_20_35M;
 173                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 174                         priv->clk_csr = STMMAC_CSR_35_60M;
 175                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 176                         priv->clk_csr = STMMAC_CSR_60_100M;
 177                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 178                         priv->clk_csr = STMMAC_CSR_100_150M;
 179                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 180                         priv->clk_csr = STMMAC_CSR_150_250M;
 181                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 182                         priv->clk_csr = STMMAC_CSR_250_300M;
 183         }
 184 }
 185
 186 static void print_pkt(unsigned char *buf, int len)
 187 {
 188         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 189         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 190 }
 191
 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 193 {
 194         unsigned avail;
 195
 196         if (priv->dirty_tx > priv->cur_tx)
 197                 avail = priv->dirty_tx - priv->cur_tx - 1;
 198         else
 199                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 200
 201         return avail;
 202 }
 203
 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 205 {
 206         unsigned dirty;
 207
 208         if (priv->dirty_rx <= priv->cur_rx)
 209                 dirty = priv->cur_rx - priv->dirty_rx;
 210         else
 211                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 212
 213         return dirty;
 214 }
 215
 216 /**
 217  * stmmac_hw_fix_mac_speed - callback for speed selection
 218  * @priv: driver private structure
 219  * Description: on some platforms (e.g. ST), some HW system configuraton
 220  * registers have to be set according to the link speed negotiated.
 221  */
 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 223 {
 224         struct phy_device *phydev = priv->phydev;
 225
 226         if (likely(priv->plat->fix_mac_speed))
 227                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 228 }
 229
 230 /**
 231  * stmmac_enable_eee_mode - check and enter in LPI mode
 232  * @priv: driver private structure
 233  * Description: this function is to verify and enter in LPI mode in case of
 234  * EEE.
 235  */
 236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 237 {
 238         /* Check and enter in LPI mode */
 239         if ((priv->dirty_tx == priv->cur_tx) &&
 240             (priv->tx_path_in_lpi_mode == false))
 241                 priv->hw->mac->set_eee_mode(priv->hw);
 242 }
 243
 244 /**
 245  * stmmac_disable_eee_mode - disable and exit from LPI mode
 246  * @priv: driver private structure
 247  * Description: this function is to exit and disable EEE in case of
 248  * LPI state is true. This is called by the xmit.
 249  */
 250 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 251 {
 252         priv->hw->mac->reset_eee_mode(priv->hw);
 253         del_timer_sync(&priv->eee_ctrl_timer);
 254         priv->tx_path_in_lpi_mode = false;
 255 }
 256
 257 /**
 258  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 259  * @arg : data hook
 260  * Description:
 261  *  if there is no data transfer and if we are not in LPI state,
 262  *  then MAC Transmitter can be moved to LPI state.
 263  */
 264 static void stmmac_eee_ctrl_timer(unsigned long arg)
 265 {
 266         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 267
 268         stmmac_enable_eee_mode(priv);
 269         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 270 }
 271
 272 /**
 273  * stmmac_eee_init - init EEE
 274  * @priv: driver private structure
 275  * Description:
 276  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 277  *  can also manage EEE, this function enable the LPI state and start related
 278  *  timer.
 279  */
 280 bool stmmac_eee_init(struct stmmac_priv *priv)
 281 {
 282         unsigned long flags;
 283         int interface = priv->plat->interface;
 284         bool ret = false;
 285
 286         if ((interface != PHY_INTERFACE_MODE_MII) &&
 287             (interface != PHY_INTERFACE_MODE_GMII) &&
 288             !phy_interface_mode_is_rgmii(interface))
 289                 goto out;
 290
 291         /* Using PCS we cannot dial with the phy registers at this stage
 292          * so we do not support extra feature like EEE.
 293          */
 294         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 295             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 296             (priv->hw->pcs == STMMAC_PCS_RTBI))
 297                 goto out;
 298
 299         /* MAC core supports the EEE feature. */
 300         if (priv->dma_cap.eee) {
 301                 int tx_lpi_timer = priv->tx_lpi_timer;
 302
 303                 /* Check if the PHY supports EEE */
 304                 if (phy_init_eee(priv->phydev, 1)) {
 305                         /* To manage at run-time if the EEE cannot be supported
 306                          * anymore (for example because the lp caps have been
 307                          * changed).
 308                          * In that case the driver disable own timers.
 309                          */
 310                         spin_lock_irqsave(&priv->lock, flags);
 311                         if (priv->eee_active) {
 312                                 pr_debug("stmmac: disable EEE\n");
 313                                 del_timer_sync(&priv->eee_ctrl_timer);
 314                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 315                                                              tx_lpi_timer);
 316                         }
 317                         priv->eee_active = 0;
 318                         spin_unlock_irqrestore(&priv->lock, flags);
 319                         goto out;
 320                 }
 321                 /* Activate the EEE and start timers */
 322                 spin_lock_irqsave(&priv->lock, flags);
 323                 if (!priv->eee_active) {
 324                         priv->eee_active = 1;
 325                         setup_timer(&priv->eee_ctrl_timer,
 326                                     stmmac_eee_ctrl_timer,
 327                                     (unsigned long)priv);
 328                         mod_timer(&priv->eee_ctrl_timer,
 329                                   STMMAC_LPI_T(eee_timer));
 330
 331                         priv->hw->mac->set_eee_timer(priv->hw,
 332                                                      STMMAC_DEFAULT_LIT_LS,
 333                                                      tx_lpi_timer);
 334                 }
 335                 /* Set HW EEE according to the speed */
 336                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 337
 338                 ret = true;
 339                 spin_unlock_irqrestore(&priv->lock, flags);
 340
 341                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 342         }
 343 out:
 344         return ret;
 345 }
 346
 347 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 348  * @priv: driver private structure
 349  * @p : descriptor pointer
 350  * @skb : the socket buffer
 351  * Description :
 352  * This function will read timestamp from the descriptor & pass it to stack.
 353  * and also perform some sanity checks.
 354  */
 355 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 356                                    struct dma_desc *p, struct sk_buff *skb)
 357 {
 358         struct skb_shared_hwtstamps shhwtstamp;
 359         u64 ns;
 360
 361         if (!priv->hwts_tx_en)
 362                 return;
 363
 364         /* exit if skb doesn't support hw tstamp */
 365         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 366                 return;
 367
 368         /* check tx tstamp status */
 369         if (!priv->hw->desc->get_tx_timestamp_status(p)) {
 370                 /* get the valid tstamp */
 371                 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 372
 373                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 374                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 375
 376                 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 377                 /* pass tstamp to stack */
 378                 skb_tstamp_tx(skb, &shhwtstamp);
 379         }
 380
 381         return;
 382 }
 383
 384 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 385  * @priv: driver private structure
 386  * @p : descriptor pointer
 387  * @np : next descriptor pointer
 388  * @skb : the socket buffer
 389  * Description :
 390  * This function will read received packet's timestamp from the descriptor
 391  * and pass it to stack. It also perform some sanity checks.
 392  */
 393 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 394                                    struct dma_desc *np, struct sk_buff *skb)
 395 {
 396         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 397         u64 ns;
 398
 399         if (!priv->hwts_rx_en)
 400                 return;
 401
 402         /* Check if timestamp is available */
 403         if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
 404                 /* For GMAC4, the valid timestamp is from CTX next desc. */
 405                 if (priv->plat->has_gmac4)
 406                         ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
 407                 else
 408                         ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 409
 410                 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 411                 shhwtstamp = skb_hwtstamps(skb);
 412                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 413                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 414         } else  {
 415                 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
 416         }
 417 }
 418
 419 /**
 420  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 421  *  @dev: device pointer.
 422  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 423  *  a proprietary structure used to pass information to the driver.
 424  *  Description:
 425  *  This function configures the MAC to enable/disable both outgoing(TX)
 426  *  and incoming(RX) packets time stamping based on user input.
 427  *  Return Value:
 428  *  0 on success and an appropriate -ve integer on failure.
 429  */
 430 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 431 {
 432         struct stmmac_priv *priv = netdev_priv(dev);
 433         struct hwtstamp_config config;
 434         struct timespec64 now;
 435         u64 temp = 0;
 436         u32 ptp_v2 = 0;
 437         u32 tstamp_all = 0;
 438         u32 ptp_over_ipv4_udp = 0;
 439         u32 ptp_over_ipv6_udp = 0;
 440         u32 ptp_over_ethernet = 0;
 441         u32 snap_type_sel = 0;
 442         u32 ts_master_en = 0;
 443         u32 ts_event_en = 0;
 444         u32 value = 0;
 445         u32 sec_inc;
 446
 447         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 448                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 449                 priv->hwts_tx_en = 0;
 450                 priv->hwts_rx_en = 0;
 451
 452                 return -EOPNOTSUPP;
 453         }
 454
 455         if (copy_from_user(&config, ifr->ifr_data,
 456                            sizeof(struct hwtstamp_config)))
 457                 return -EFAULT;
 458
 459         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 460                  __func__, config.flags, config.tx_type, config.rx_filter);
 461
 462         /* reserved for future extensions */
 463         if (config.flags)
 464                 return -EINVAL;
 465
 466         if (config.tx_type != HWTSTAMP_TX_OFF &&
 467             config.tx_type != HWTSTAMP_TX_ON)
 468                 return -ERANGE;
 469
 470         if (priv->adv_ts) {
 471                 switch (config.rx_filter) {
 472                 case HWTSTAMP_FILTER_NONE:
 473                         /* time stamp no incoming packet at all */
 474                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 475                         break;
 476
 477                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 478                         /* PTP v1, UDP, any kind of event packet */
 479                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 480                         /* take time stamp for all event messages */
 481                         if (priv->plat->has_gmac4)
 482                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 483                         else
 484                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 485
 486                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 487                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 488                         break;
 489
 490                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 491                         /* PTP v1, UDP, Sync packet */
 492                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 493                         /* take time stamp for SYNC messages only */
 494                         ts_event_en = PTP_TCR_TSEVNTENA;
 495
 496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 498                         break;
 499
 500                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 501                         /* PTP v1, UDP, Delay_req packet */
 502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 503                         /* take time stamp for Delay_Req messages only */
 504                         ts_master_en = PTP_TCR_TSMSTRENA;
 505                         ts_event_en = PTP_TCR_TSEVNTENA;
 506
 507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 509                         break;
 510
 511                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 512                         /* PTP v2, UDP, any kind of event packet */
 513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 514                         ptp_v2 = PTP_TCR_TSVER2ENA;
 515                         /* take time stamp for all event messages */
 516                         if (priv->plat->has_gmac4)
 517                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 518                         else
 519                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 520
 521                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 522                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 523                         break;
 524
 525                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 526                         /* PTP v2, UDP, Sync packet */
 527                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 528                         ptp_v2 = PTP_TCR_TSVER2ENA;
 529                         /* take time stamp for SYNC messages only */
 530                         ts_event_en = PTP_TCR_TSEVNTENA;
 531
 532                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 533                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 534                         break;
 535
 536                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 537                         /* PTP v2, UDP, Delay_req packet */
 538                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 539                         ptp_v2 = PTP_TCR_TSVER2ENA;
 540                         /* take time stamp for Delay_Req messages only */
 541                         ts_master_en = PTP_TCR_TSMSTRENA;
 542                         ts_event_en = PTP_TCR_TSEVNTENA;
 543
 544                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 545                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 546                         break;
 547
 548                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 549                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 550                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 551                         ptp_v2 = PTP_TCR_TSVER2ENA;
 552                         /* take time stamp for all event messages */
 553                         if (priv->plat->has_gmac4)
 554                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 555                         else
 556                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 557
 558                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 559                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 560                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 561                         break;
 562
 563                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 564                         /* PTP v2/802.AS1, any layer, Sync packet */
 565                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 566                         ptp_v2 = PTP_TCR_TSVER2ENA;
 567                         /* take time stamp for SYNC messages only */
 568                         ts_event_en = PTP_TCR_TSEVNTENA;
 569
 570                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 571                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 572                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 573                         break;
 574
 575                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 576                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 577                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 578                         ptp_v2 = PTP_TCR_TSVER2ENA;
 579                         /* take time stamp for Delay_Req messages only */
 580                         ts_master_en = PTP_TCR_TSMSTRENA;
 581                         ts_event_en = PTP_TCR_TSEVNTENA;
 582
 583                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 584                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 585                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 586                         break;
 587
 588                 case HWTSTAMP_FILTER_ALL:
 589                         /* time stamp any incoming packet */
 590                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 591                         tstamp_all = PTP_TCR_TSENALL;
 592                         break;
 593
 594                 default:
 595                         return -ERANGE;
 596                 }
 597         } else {
 598                 switch (config.rx_filter) {
 599                 case HWTSTAMP_FILTER_NONE:
 600                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 601                         break;
 602                 default:
 603                         /* PTP v1, UDP, any kind of event packet */
 604                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 605                         break;
 606                 }
 607         }
 608         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 609         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 610
 611         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 612                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
 613         else {
 614                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 615                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 616                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 617                          ts_master_en | snap_type_sel);
 618                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
 619
 620                 /* program Sub Second Increment reg */
 621                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 622                         priv->ptpaddr, priv->clk_ptp_rate,
 623                         priv->plat->has_gmac4);
 624                 temp = div_u64(1000000000ULL, sec_inc);
 625
 626                 /* calculate default added value:
 627                  * formula is :
 628                  * addend = (2^32)/freq_div_ratio;
 629                  * where, freq_div_ratio = 1e9ns/sec_inc
 630                  */
 631                 temp = (u64)(temp << 32);
 632                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 633                 priv->hw->ptp->config_addend(priv->ptpaddr,
 634                                              priv->default_addend);
 635
 636                 /* initialize system time */
 637                 ktime_get_real_ts64(&now);
 638
 639                 /* lower 32 bits of tv_sec are safe until y2106 */
 640                 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
 641                                             now.tv_nsec);
 642         }
 643
 644         return copy_to_user(ifr->ifr_data, &config,
 645                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 646 }
 647
 648 /**
 649  * stmmac_init_ptp - init PTP
 650  * @priv: driver private structure
 651  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 652  * This is done by looking at the HW cap. register.
 653  * This function also registers the ptp driver.
 654  */
 655 static int stmmac_init_ptp(struct stmmac_priv *priv)
 656 {
 657         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 658                 return -EOPNOTSUPP;
 659
 660         /* Fall-back to main clock in case of no PTP ref is passed */
 661         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 662         if (IS_ERR(priv->clk_ptp_ref)) {
 663                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 664                 priv->clk_ptp_ref = NULL;
 665                 netdev_dbg(priv->dev, "PTP uses main clock\n");
 666         } else {
 667                 clk_prepare_enable(priv->clk_ptp_ref);
 668                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 669                 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
 670         }
 671
 672         priv->adv_ts = 0;
 673         /* Check if adv_ts can be enabled for dwmac 4.x core */
 674         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
 675                 priv->adv_ts = 1;
 676         /* Dwmac 3.x core with extend_desc can support adv_ts */
 677         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 678                 priv->adv_ts = 1;
 679
 680         if (priv->dma_cap.time_stamp)
 681                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 682
 683         if (priv->adv_ts)
 684                 netdev_info(priv->dev,
 685                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 686
 687         priv->hw->ptp = &stmmac_ptp;
 688         priv->hwts_tx_en = 0;
 689         priv->hwts_rx_en = 0;
 690
 691         stmmac_ptp_register(priv);
 692
 693         return 0;
 694 }
 695
 696 static void stmmac_release_ptp(struct stmmac_priv *priv)
 697 {
 698         if (priv->clk_ptp_ref)
 699                 clk_disable_unprepare(priv->clk_ptp_ref);
 700         stmmac_ptp_unregister(priv);
 701 }
 702
 703 /**
 704  * stmmac_adjust_link - adjusts the link parameters
 705  * @dev: net device structure
 706  * Description: this is the helper called by the physical abstraction layer
 707  * drivers to communicate the phy link status. According the speed and duplex
 708  * this driver can invoke registered glue-logic as well.
 709  * It also invoke the eee initialization because it could happen when switch
 710  * on different networks (that are eee capable).
 711  */
 712 static void stmmac_adjust_link(struct net_device *dev)
 713 {
 714         struct stmmac_priv *priv = netdev_priv(dev);
 715         struct phy_device *phydev = priv->phydev;
 716         unsigned long flags;
 717         int new_state = 0;
 718         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 719
 720         if (phydev == NULL)
 721                 return;
 722
 723         spin_lock_irqsave(&priv->lock, flags);
 724
 725         if (phydev->link) {
 726                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 727
 728                 /* Now we make sure that we can be in full duplex mode.
 729                  * If not, we operate in half-duplex mode. */
 730                 if (phydev->duplex != priv->oldduplex) {
 731                         new_state = 1;
 732                         if (!(phydev->duplex))
 733                                 ctrl &= ~priv->hw->link.duplex;
 734                         else
 735                                 ctrl |= priv->hw->link.duplex;
 736                         priv->oldduplex = phydev->duplex;
 737                 }
 738                 /* Flow Control operation */
 739                 if (phydev->pause)
 740                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 741                                                  fc, pause_time);
 742
 743                 if (phydev->speed != priv->speed) {
 744                         new_state = 1;
 745                         switch (phydev->speed) {
 746                         case 1000:
 747                                 if (likely((priv->plat->has_gmac) ||
 748                                            (priv->plat->has_gmac4)))
 749                                         ctrl &= ~priv->hw->link.port;
 750                                 stmmac_hw_fix_mac_speed(priv);
 751                                 break;
 752                         case 100:
 753                         case 10:
 754                                 if (likely((priv->plat->has_gmac) ||
 755                                            (priv->plat->has_gmac4))) {
 756                                         ctrl |= priv->hw->link.port;
 757                                         if (phydev->speed == SPEED_100) {
 758                                                 ctrl |= priv->hw->link.speed;
 759                                         } else {
 760                                                 ctrl &= ~(priv->hw->link.speed);
 761                                         }
 762                                 } else {
 763                                         ctrl &= ~priv->hw->link.port;
 764                                 }
 765                                 stmmac_hw_fix_mac_speed(priv);
 766                                 break;
 767                         default:
 768                                 if (netif_msg_link(priv))
 769                                         pr_warn("%s: Speed (%d) not 10/100\n",
 770                                                 dev->name, phydev->speed);
 771                                 break;
 772                         }
 773
 774                         priv->speed = phydev->speed;
 775                 }
 776
 777                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 778
 779                 if (!priv->oldlink) {
 780                         new_state = 1;
 781                         priv->oldlink = 1;
 782                 }
 783         } else if (priv->oldlink) {
 784                 new_state = 1;
 785                 priv->oldlink = 0;
 786                 priv->speed = 0;
 787                 priv->oldduplex = -1;
 788         }
 789
 790         if (new_state && netif_msg_link(priv))
 791                 phy_print_status(phydev);
 792
 793         spin_unlock_irqrestore(&priv->lock, flags);
 794
 795         if (phydev->is_pseudo_fixed_link)
 796                 /* Stop PHY layer to call the hook to adjust the link in case
 797                  * of a switch is attached to the stmmac driver.
 798                  */
 799                 phydev->irq = PHY_IGNORE_INTERRUPT;
 800         else
 801                 /* At this stage, init the EEE if supported.
 802                  * Never called in case of fixed_link.
 803                  */
 804                 priv->eee_enabled = stmmac_eee_init(priv);
 805 }
 806
 807 /**
 808  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 809  * @priv: driver private structure
 810  * Description: this is to verify if the HW supports the PCS.
 811  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 812  * configured for the TBI, RTBI, or SGMII PHY interface.
 813  */
 814 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 815 {
 816         int interface = priv->plat->interface;
 817
 818         if (priv->dma_cap.pcs) {
 819                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 820                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 821                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 822                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 823                         pr_debug("STMMAC: PCS RGMII support enable\n");
 824                         priv->hw->pcs = STMMAC_PCS_RGMII;
 825                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 826                         pr_debug("STMMAC: PCS SGMII support enable\n");
 827                         priv->hw->pcs = STMMAC_PCS_SGMII;
 828                 }
 829         }
 830 }
 831
 832 /**
 833  * stmmac_init_phy - PHY initialization
 834  * @dev: net device structure
 835  * Description: it initializes the driver's PHY state, and attaches the PHY
 836  * to the mac driver.
 837  *  Return value:
 838  *  0 on success
 839  */
 840 static int stmmac_init_phy(struct net_device *dev)
 841 {
 842         struct stmmac_priv *priv = netdev_priv(dev);
 843         struct phy_device *phydev;
 844         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 845         char bus_id[MII_BUS_ID_SIZE];
 846         int interface = priv->plat->interface;
 847         int max_speed = priv->plat->max_speed;
 848         priv->oldlink = 0;
 849         priv->speed = 0;
 850         priv->oldduplex = -1;
 851
 852         if (priv->plat->phy_node) {
 853                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 854                                         &stmmac_adjust_link, 0, interface);
 855         } else {
 856                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 857                          priv->plat->bus_id);
 858
 859                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 860                          priv->plat->phy_addr);
 861                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 862                          phy_id_fmt);
 863
 864                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 865                                      interface);
 866         }
 867
 868         if (IS_ERR_OR_NULL(phydev)) {
 869                 pr_err("%s: Could not attach to PHY\n", dev->name);
 870                 if (!phydev)
 871                         return -ENODEV;
 872
 873                 return PTR_ERR(phydev);
 874         }
 875
 876         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 877         if ((interface == PHY_INTERFACE_MODE_MII) ||
 878             (interface == PHY_INTERFACE_MODE_RMII) ||
 879                 (max_speed < 1000 && max_speed > 0))
 880                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 881                                          SUPPORTED_1000baseT_Full);
 882
 883         /*
 884          * Broken HW is sometimes missing the pull-up resistor on the
 885          * MDIO line, which results in reads to non-existent devices returning
 886          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 887          * device as well.
 888          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 889          */
 890         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 891                 phy_disconnect(phydev);
 892                 return -ENODEV;
 893         }
 894
 895         /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
 896          * subsequent PHY polling, make sure we force a link transition if
 897          * we have a UP/DOWN/UP transition
 898          */
 899         if (phydev->is_pseudo_fixed_link)
 900                 phydev->irq = PHY_POLL;
 901
 902         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 903                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 904
 905         priv->phydev = phydev;
 906
 907         return 0;
 908 }
 909
 910 static void stmmac_display_rings(struct stmmac_priv *priv)
 911 {
 912         void *head_rx, *head_tx;
 913
 914         if (priv->extend_desc) {
 915                 head_rx = (void *)priv->dma_erx;
 916                 head_tx = (void *)priv->dma_etx;
 917         } else {
 918                 head_rx = (void *)priv->dma_rx;
 919                 head_tx = (void *)priv->dma_tx;
 920         }
 921
 922         /* Display Rx ring */
 923         priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
 924         /* Display Tx ring */
 925         priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
 926 }
 927
 928 static int stmmac_set_bfsize(int mtu, int bufsize)
 929 {
 930         int ret = bufsize;
 931
 932         if (mtu >= BUF_SIZE_8KiB)
 933                 ret = BUF_SIZE_16KiB;
 934         else if (mtu >= BUF_SIZE_4KiB)
 935                 ret = BUF_SIZE_8KiB;
 936         else if (mtu >= BUF_SIZE_2KiB)
 937                 ret = BUF_SIZE_4KiB;
 938         else if (mtu > DEFAULT_BUFSIZE)
 939                 ret = BUF_SIZE_2KiB;
 940         else
 941                 ret = DEFAULT_BUFSIZE;
 942
 943         return ret;
 944 }
 945
 946 /**
 947  * stmmac_clear_descriptors - clear descriptors
 948  * @priv: driver private structure
 949  * Description: this function is called to clear the tx and rx descriptors
 950  * in case of both basic and extended descriptors are used.
 951  */
 952 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 953 {
 954         int i;
 955
 956         /* Clear the Rx/Tx descriptors */
 957         for (i = 0; i < DMA_RX_SIZE; i++)
 958                 if (priv->extend_desc)
 959                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 960                                                      priv->use_riwt, priv->mode,
 961                                                      (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
 962                 else
 963                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 964                                                      priv->use_riwt, priv->mode,
 965                                                      (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
 966         for (i = 0; i < DMA_TX_SIZE; i++)
 967                 if (priv->extend_desc)
 968                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 969                                                      priv->mode,
 970                                                      (i == DMA_TX_SIZE - 1));
 971                 else
 972                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 973                                                      priv->mode,
 974                                                      (i == DMA_TX_SIZE - 1));
 975 }
 976
 977 /**
 978  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 979  * @priv: driver private structure
 980  * @p: descriptor pointer
 981  * @i: descriptor index
 982  * @flags: gfp flag.
 983  * Description: this function is called to allocate a receive buffer, perform
 984  * the DMA mapping and init the descriptor.
 985  */
 986 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 987                                   int i, gfp_t flags)
 988 {
 989         struct sk_buff *skb;
 990
 991         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 992         if (!skb) {
 993                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 994                 return -ENOMEM;
 995         }
 996         priv->rx_skbuff[i] = skb;
 997         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 998                                                 priv->dma_buf_sz,
 999                                                 DMA_FROM_DEVICE);
1000         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1001                 pr_err("%s: DMA mapping error\n", __func__);
1002                 dev_kfree_skb_any(skb);
1003                 return -EINVAL;
1004         }
1005
1006         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1007                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1008         else
1009                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1010
1011         if ((priv->hw->mode->init_desc3) &&
1012             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1013                 priv->hw->mode->init_desc3(p);
1014
1015         return 0;
1016 }
1017
1018 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1019 {
1020         if (priv->rx_skbuff[i]) {
1021                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1022                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1023                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1024         }
1025         priv->rx_skbuff[i] = NULL;
1026 }
1027
1028 /**
1029  * init_dma_desc_rings - init the RX/TX descriptor rings
1030  * @dev: net device structure
1031  * @flags: gfp flag.
1032  * Description: this function initializes the DMA RX/TX descriptors
1033  * and allocates the socket buffers. It suppors the chained and ring
1034  * modes.
1035  */
1036 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1037 {
1038         int i;
1039         struct stmmac_priv *priv = netdev_priv(dev);
1040         unsigned int bfsize = 0;
1041         int ret = -ENOMEM;
1042
1043         if (priv->hw->mode->set_16kib_bfsize)
1044                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1045
1046         if (bfsize < BUF_SIZE_16KiB)
1047                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1048
1049         priv->dma_buf_sz = bfsize;
1050
1051         if (netif_msg_probe(priv)) {
1052                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1053                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1054
1055                 /* RX INITIALIZATION */
1056                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1057         }
1058         for (i = 0; i < DMA_RX_SIZE; i++) {
1059                 struct dma_desc *p;
1060                 if (priv->extend_desc)
1061                         p = &((priv->dma_erx + i)->basic);
1062                 else
1063                         p = priv->dma_rx + i;
1064
1065                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1066                 if (ret)
1067                         goto err_init_rx_buffers;
1068
1069                 if (netif_msg_probe(priv))
1070                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1071                                  priv->rx_skbuff[i]->data,
1072                                  (unsigned int)priv->rx_skbuff_dma[i]);
1073         }
1074         priv->cur_rx = 0;
1075         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1076         buf_sz = bfsize;
1077
1078         /* Setup the chained descriptor addresses */
1079         if (priv->mode == STMMAC_CHAIN_MODE) {
1080                 if (priv->extend_desc) {
1081                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1082                                              DMA_RX_SIZE, 1);
1083                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1084                                              DMA_TX_SIZE, 1);
1085                 } else {
1086                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1087                                              DMA_RX_SIZE, 0);
1088                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1089                                              DMA_TX_SIZE, 0);
1090                 }
1091         }
1092
1093         /* TX INITIALIZATION */
1094         for (i = 0; i < DMA_TX_SIZE; i++) {
1095                 struct dma_desc *p;
1096                 if (priv->extend_desc)
1097                         p = &((priv->dma_etx + i)->basic);
1098                 else
1099                         p = priv->dma_tx + i;
1100
1101                 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1102                         p->des0 = 0;
1103                         p->des1 = 0;
1104                         p->des2 = 0;
1105                         p->des3 = 0;
1106                 } else {
1107                         p->des2 = 0;
1108                 }
1109
1110                 priv->tx_skbuff_dma[i].buf = 0;
1111                 priv->tx_skbuff_dma[i].map_as_page = false;
1112                 priv->tx_skbuff_dma[i].len = 0;
1113                 priv->tx_skbuff_dma[i].last_segment = false;
1114                 priv->tx_skbuff[i] = NULL;
1115         }
1116
1117         priv->dirty_tx = 0;
1118         priv->cur_tx = 0;
1119         netdev_reset_queue(priv->dev);
1120
1121         stmmac_clear_descriptors(priv);
1122
1123         if (netif_msg_hw(priv))
1124                 stmmac_display_rings(priv);
1125
1126         return 0;
1127 err_init_rx_buffers:
1128         while (--i >= 0)
1129                 stmmac_free_rx_buffers(priv, i);
1130         return ret;
1131 }
1132
1133 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1134 {
1135         int i;
1136
1137         for (i = 0; i < DMA_RX_SIZE; i++)
1138                 stmmac_free_rx_buffers(priv, i);
1139 }
1140
1141 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1142 {
1143         int i;
1144
1145         for (i = 0; i < DMA_TX_SIZE; i++) {
1146                 struct dma_desc *p;
1147
1148                 if (priv->extend_desc)
1149                         p = &((priv->dma_etx + i)->basic);
1150                 else
1151                         p = priv->dma_tx + i;
1152
1153                 if (priv->tx_skbuff_dma[i].buf) {
1154                         if (priv->tx_skbuff_dma[i].map_as_page)
1155                                 dma_unmap_page(priv->device,
1156                                                priv->tx_skbuff_dma[i].buf,
1157                                                priv->tx_skbuff_dma[i].len,
1158                                                DMA_TO_DEVICE);
1159                         else
1160                                 dma_unmap_single(priv->device,
1161                                                  priv->tx_skbuff_dma[i].buf,
1162                                                  priv->tx_skbuff_dma[i].len,
1163                                                  DMA_TO_DEVICE);
1164                 }
1165
1166                 if (priv->tx_skbuff[i] != NULL) {
1167                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1168                         priv->tx_skbuff[i] = NULL;
1169                         priv->tx_skbuff_dma[i].buf = 0;
1170                         priv->tx_skbuff_dma[i].map_as_page = false;
1171                 }
1172         }
1173 }
1174
1175 /**
1176  * alloc_dma_desc_resources - alloc TX/RX resources.
1177  * @priv: private structure
1178  * Description: according to which descriptor can be used (extend or basic)
1179  * this function allocates the resources for TX and RX paths. In case of
1180  * reception, for example, it pre-allocated the RX socket buffer in order to
1181  * allow zero-copy mechanism.
1182  */
1183 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1184 {
1185         int ret = -ENOMEM;
1186
1187         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1188                                             GFP_KERNEL);
1189         if (!priv->rx_skbuff_dma)
1190                 return -ENOMEM;
1191
1192         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1193                                         GFP_KERNEL);
1194         if (!priv->rx_skbuff)
1195                 goto err_rx_skbuff;
1196
1197         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1198                                             sizeof(*priv->tx_skbuff_dma),
1199                                             GFP_KERNEL);
1200         if (!priv->tx_skbuff_dma)
1201                 goto err_tx_skbuff_dma;
1202
1203         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1204                                         GFP_KERNEL);
1205         if (!priv->tx_skbuff)
1206                 goto err_tx_skbuff;
1207
1208         if (priv->extend_desc) {
1209                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1210                                                     sizeof(struct
1211                                                            dma_extended_desc),
1212                                                     &priv->dma_rx_phy,
1213                                                     GFP_KERNEL);
1214                 if (!priv->dma_erx)
1215                         goto err_dma;
1216
1217                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1218                                                     sizeof(struct
1219                                                            dma_extended_desc),
1220                                                     &priv->dma_tx_phy,
1221                                                     GFP_KERNEL);
1222                 if (!priv->dma_etx) {
1223                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1224                                           sizeof(struct dma_extended_desc),
1225                                           priv->dma_erx, priv->dma_rx_phy);
1226                         goto err_dma;
1227                 }
1228         } else {
1229                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1230                                                    sizeof(struct dma_desc),
1231                                                    &priv->dma_rx_phy,
1232                                                    GFP_KERNEL);
1233                 if (!priv->dma_rx)
1234                         goto err_dma;
1235
1236                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1237                                                    sizeof(struct dma_desc),
1238                                                    &priv->dma_tx_phy,
1239                                                    GFP_KERNEL);
1240                 if (!priv->dma_tx) {
1241                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1242                                           sizeof(struct dma_desc),
1243                                           priv->dma_rx, priv->dma_rx_phy);
1244                         goto err_dma;
1245                 }
1246         }
1247
1248         return 0;
1249
1250 err_dma:
1251         kfree(priv->tx_skbuff);
1252 err_tx_skbuff:
1253         kfree(priv->tx_skbuff_dma);
1254 err_tx_skbuff_dma:
1255         kfree(priv->rx_skbuff);
1256 err_rx_skbuff:
1257         kfree(priv->rx_skbuff_dma);
1258         return ret;
1259 }
1260
1261 static void free_dma_desc_resources(struct stmmac_priv *priv)
1262 {
1263         /* Release the DMA TX/RX socket buffers */
1264         dma_free_rx_skbufs(priv);
1265         dma_free_tx_skbufs(priv);
1266
1267         /* Free DMA regions of consistent memory previously allocated */
1268         if (!priv->extend_desc) {
1269                 dma_free_coherent(priv->device,
1270                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1271                                   priv->dma_tx, priv->dma_tx_phy);
1272                 dma_free_coherent(priv->device,
1273                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1274                                   priv->dma_rx, priv->dma_rx_phy);
1275         } else {
1276                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1277                                   sizeof(struct dma_extended_desc),
1278                                   priv->dma_etx, priv->dma_tx_phy);
1279                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1280                                   sizeof(struct dma_extended_desc),
1281                                   priv->dma_erx, priv->dma_rx_phy);
1282         }
1283         kfree(priv->rx_skbuff_dma);
1284         kfree(priv->rx_skbuff);
1285         kfree(priv->tx_skbuff_dma);
1286         kfree(priv->tx_skbuff);
1287 }
1288
1289 /**
1290  *  stmmac_dma_operation_mode - HW DMA operation mode
1291  *  @priv: driver private structure
1292  *  Description: it is used for configuring the DMA operation mode register in
1293  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1294  */
1295 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1296 {
1297         int rxfifosz = priv->plat->rx_fifo_size;
1298
1299         if (priv->plat->force_thresh_dma_mode)
1300                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1301         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1302                 /*
1303                  * In case of GMAC, SF mode can be enabled
1304                  * to perform the TX COE in HW. This depends on:
1305                  * 1) TX COE if actually supported
1306                  * 2) There is no bugged Jumbo frame support
1307                  *    that needs to not insert csum in the TDES.
1308                  */
1309                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1310                                         rxfifosz);
1311                 priv->xstats.threshold = SF_DMA_MODE;
1312         } else
1313                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1314                                         rxfifosz);
1315 }
1316
1317 /**
1318  * stmmac_tx_clean - to manage the transmission completion
1319  * @priv: driver private structure
1320  * Description: it reclaims the transmit resources after transmission completes.
1321  */
1322 static void stmmac_tx_clean(struct stmmac_priv *priv)
1323 {
1324         unsigned int bytes_compl = 0, pkts_compl = 0;
1325         unsigned int entry = priv->dirty_tx;
1326
1327         spin_lock(&priv->tx_lock);
1328
1329         priv->xstats.tx_clean++;
1330
1331         while (entry != priv->cur_tx) {
1332                 struct sk_buff *skb = priv->tx_skbuff[entry];
1333                 struct dma_desc *p;
1334                 int status;
1335
1336                 if (priv->extend_desc)
1337                         p = (struct dma_desc *)(priv->dma_etx + entry);
1338                 else
1339                         p = priv->dma_tx + entry;
1340
1341                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1342                                                       &priv->xstats, p,
1343                                                       priv->ioaddr);
1344                 /* Check if the descriptor is owned by the DMA */
1345                 if (unlikely(status & tx_dma_own))
1346                         break;
1347
1348                 /* Make sure descriptor fields are read after reading
1349                  * the own bit.
1350                  */
1351                 dma_rmb();
1352
1353                 /* Just consider the last segment and ...*/
1354                 if (likely(!(status & tx_not_ls))) {
1355                         /* ... verify the status error condition */
1356                         if (unlikely(status & tx_err)) {
1357                                 priv->dev->stats.tx_errors++;
1358                         } else {
1359                                 priv->dev->stats.tx_packets++;
1360                                 priv->xstats.tx_pkt_n++;
1361                         }
1362                         stmmac_get_tx_hwtstamp(priv, p, skb);
1363                 }
1364
1365                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1366                         if (priv->tx_skbuff_dma[entry].map_as_page)
1367                                 dma_unmap_page(priv->device,
1368                                                priv->tx_skbuff_dma[entry].buf,
1369                                                priv->tx_skbuff_dma[entry].len,
1370                                                DMA_TO_DEVICE);
1371                         else
1372                                 dma_unmap_single(priv->device,
1373                                                  priv->tx_skbuff_dma[entry].buf,
1374                                                  priv->tx_skbuff_dma[entry].len,
1375                                                  DMA_TO_DEVICE);
1376                         priv->tx_skbuff_dma[entry].buf = 0;
1377                         priv->tx_skbuff_dma[entry].len = 0;
1378                         priv->tx_skbuff_dma[entry].map_as_page = false;
1379                 }
1380
1381                 if (priv->hw->mode->clean_desc3)
1382                         priv->hw->mode->clean_desc3(priv, p);
1383
1384                 priv->tx_skbuff_dma[entry].last_segment = false;
1385                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1386
1387                 if (likely(skb != NULL)) {
1388                         pkts_compl++;
1389                         bytes_compl += skb->len;
1390                         dev_consume_skb_any(skb);
1391                         priv->tx_skbuff[entry] = NULL;
1392                 }
1393
1394                 priv->hw->desc->release_tx_desc(p, priv->mode);
1395
1396                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1397         }
1398         priv->dirty_tx = entry;
1399
1400         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1401
1402         if (unlikely(netif_queue_stopped(priv->dev) &&
1403                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1404                 netif_tx_lock(priv->dev);
1405                 if (netif_queue_stopped(priv->dev) &&
1406                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1407                         if (netif_msg_tx_done(priv))
1408                                 pr_debug("%s: restart transmit\n", __func__);
1409                         netif_wake_queue(priv->dev);
1410                 }
1411                 netif_tx_unlock(priv->dev);
1412         }
1413
1414         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1415                 stmmac_enable_eee_mode(priv);
1416                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1417         }
1418         spin_unlock(&priv->tx_lock);
1419 }
1420
1421 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1422 {
1423         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1424 }
1425
1426 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1427 {
1428         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1429 }
1430
1431 /**
1432  * stmmac_tx_err - to manage the tx error
1433  * @priv: driver private structure
1434  * Description: it cleans the descriptors and restarts the transmission
1435  * in case of transmission errors.
1436  */
1437 static void stmmac_tx_err(struct stmmac_priv *priv)
1438 {
1439         int i;
1440         netif_stop_queue(priv->dev);
1441
1442         priv->hw->dma->stop_tx(priv->ioaddr);
1443         dma_free_tx_skbufs(priv);
1444         for (i = 0; i < DMA_TX_SIZE; i++)
1445                 if (priv->extend_desc)
1446                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1447                                                      priv->mode,
1448                                                      (i == DMA_TX_SIZE - 1));
1449                 else
1450                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1451                                                      priv->mode,
1452                                                      (i == DMA_TX_SIZE - 1));
1453         priv->dirty_tx = 0;
1454         priv->cur_tx = 0;
1455         netdev_reset_queue(priv->dev);
1456         priv->hw->dma->start_tx(priv->ioaddr);
1457
1458         priv->dev->stats.tx_errors++;
1459         netif_wake_queue(priv->dev);
1460 }
1461
1462 /**
1463  * stmmac_dma_interrupt - DMA ISR
1464  * @priv: driver private structure
1465  * Description: this is the DMA ISR. It is called by the main ISR.
1466  * It calls the dwmac dma routine and schedule poll method in case of some
1467  * work can be done.
1468  */
1469 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1470 {
1471         int status;
1472         int rxfifosz = priv->plat->rx_fifo_size;
1473
1474         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1475         if (likely((status & handle_rx)) || (status & handle_tx)) {
1476                 if (likely(napi_schedule_prep(&priv->napi))) {
1477                         stmmac_disable_dma_irq(priv);
1478                         __napi_schedule(&priv->napi);
1479                 }
1480         }
1481         if (unlikely(status & tx_hard_error_bump_tc)) {
1482                 /* Try to bump up the dma threshold on this failure */
1483                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1484                     (tc <= 256)) {
1485                         tc += 64;
1486                         if (priv->plat->force_thresh_dma_mode)
1487                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1488                                                         rxfifosz);
1489                         else
1490                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1491                                                         SF_DMA_MODE, rxfifosz);
1492                         priv->xstats.threshold = tc;
1493                 }
1494         } else if (unlikely(status == tx_hard_error))
1495                 stmmac_tx_err(priv);
1496 }
1497
1498 /**
1499  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1500  * @priv: driver private structure
1501  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1502  */
1503 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1504 {
1505         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1506                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1507
1508         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1509                 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1510                 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1511         } else {
1512                 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1513                 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1514         }
1515
1516         dwmac_mmc_intr_all_mask(priv->mmcaddr);
1517
1518         if (priv->dma_cap.rmon) {
1519                 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1520                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1521         } else
1522                 pr_info(" No MAC Management Counters available\n");
1523 }
1524
1525 /**
1526  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1527  * @priv: driver private structure
1528  * Description: select the Enhanced/Alternate or Normal descriptors.
1529  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1530  * supported by the HW capability register.
1531  */
1532 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1533 {
1534         if (priv->plat->enh_desc) {
1535                 pr_info(" Enhanced/Alternate descriptors\n");
1536
1537                 /* GMAC older than 3.50 has no extended descriptors */
1538                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1539                         pr_info("\tEnabled extended descriptors\n");
1540                         priv->extend_desc = 1;
1541                 } else
1542                         pr_warn("Extended descriptors not supported\n");
1543
1544                 priv->hw->desc = &enh_desc_ops;
1545         } else {
1546                 pr_info(" Normal descriptors\n");
1547                 priv->hw->desc = &ndesc_ops;
1548         }
1549 }
1550
1551 /**
1552  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1553  * @priv: driver private structure
1554  * Description:
1555  *  new GMAC chip generations have a new register to indicate the
1556  *  presence of the optional feature/functions.
1557  *  This can be also used to override the value passed through the
1558  *  platform and necessary for old MAC10/100 and GMAC chips.
1559  */
1560 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1561 {
1562         u32 ret = 0;
1563
1564         if (priv->hw->dma->get_hw_feature) {
1565                 priv->hw->dma->get_hw_feature(priv->ioaddr,
1566                                               &priv->dma_cap);
1567                 ret = 1;
1568         }
1569
1570         return ret;
1571 }
1572
1573 /**
1574  * stmmac_check_ether_addr - check if the MAC addr is valid
1575  * @priv: driver private structure
1576  * Description:
1577  * it is to verify if the MAC address is valid, in case of failures it
1578  * generates a random MAC address
1579  */
1580 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1581 {
1582         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1583                 priv->hw->mac->get_umac_addr(priv->hw,
1584                                              priv->dev->dev_addr, 0);
1585                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1586                         eth_hw_addr_random(priv->dev);
1587                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1588                         priv->dev->dev_addr);
1589         }
1590 }
1591
1592 /**
1593  * stmmac_init_dma_engine - DMA init.
1594  * @priv: driver private structure
1595  * Description:
1596  * It inits the DMA invoking the specific MAC/GMAC callback.
1597  * Some DMA parameters can be passed from the platform;
1598  * in case of these are not passed a default is kept for the MAC or GMAC.
1599  */
1600 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1601 {
1602         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1603         int mixed_burst = 0;
1604         int atds = 0;
1605         int ret = 0;
1606
1607         if (priv->plat->dma_cfg) {
1608                 pbl = priv->plat->dma_cfg->pbl;
1609                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1610                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1611                 aal = priv->plat->dma_cfg->aal;
1612         }
1613
1614         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1615                 atds = 1;
1616
1617         ret = priv->hw->dma->reset(priv->ioaddr);
1618         if (ret) {
1619                 dev_err(priv->device, "Failed to reset the dma\n");
1620                 return ret;
1621         }
1622
1623         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1624                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1625
1626         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1627                 priv->rx_tail_addr = priv->dma_rx_phy +
1628                             (DMA_RX_SIZE * sizeof(struct dma_desc));
1629                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1630                                                STMMAC_CHAN0);
1631
1632                 priv->tx_tail_addr = priv->dma_tx_phy +
1633                             (DMA_TX_SIZE * sizeof(struct dma_desc));
1634                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1635                                                STMMAC_CHAN0);
1636         }
1637
1638         if (priv->plat->axi && priv->hw->dma->axi)
1639                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1640
1641         return ret;
1642 }
1643
1644 /**
1645  * stmmac_tx_timer - mitigation sw timer for tx.
1646  * @data: data pointer
1647  * Description:
1648  * This is the timer handler to directly invoke the stmmac_tx_clean.
1649  */
1650 static void stmmac_tx_timer(unsigned long data)
1651 {
1652         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1653
1654         stmmac_tx_clean(priv);
1655 }
1656
1657 /**
1658  * stmmac_init_tx_coalesce - init tx mitigation options.
1659  * @priv: driver private structure
1660  * Description:
1661  * This inits the transmit coalesce parameters: i.e. timer rate,
1662  * timer handler and default threshold used for enabling the
1663  * interrupt on completion bit.
1664  */
1665 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1666 {
1667         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1668         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1669         init_timer(&priv->txtimer);
1670         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1671         priv->txtimer.data = (unsigned long)priv;
1672         priv->txtimer.function = stmmac_tx_timer;
1673         add_timer(&priv->txtimer);
1674 }
1675
1676 /**
1677  * stmmac_hw_setup - setup mac in a usable state.
1678  *  @dev : pointer to the device structure.
1679  *  Description:
1680  *  this is the main function to setup the HW in a usable state because the
1681  *  dma engine is reset, the core registers are configured (e.g. AXI,
1682  *  Checksum features, timers). The DMA is ready to start receiving and
1683  *  transmitting.
1684  *  Return value:
1685  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1686  *  file on failure.
1687  */
1688 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1689 {
1690         struct stmmac_priv *priv = netdev_priv(dev);
1691         int ret;
1692
1693         /* DMA initialization and SW reset */
1694         ret = stmmac_init_dma_engine(priv);
1695         if (ret < 0) {
1696                 pr_err("%s: DMA engine initialization failed\n", __func__);
1697                 return ret;
1698         }
1699
1700         /* Copy the MAC addr into the HW  */
1701         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1702
1703         /* If required, perform hw setup of the bus. */
1704         if (priv->plat->bus_setup)
1705                 priv->plat->bus_setup(priv->ioaddr);
1706
1707         /* PS and related bits will be programmed according to the speed */
1708         if (priv->hw->pcs) {
1709                 int speed = priv->plat->mac_port_sel_speed;
1710
1711                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1712                     (speed == SPEED_1000)) {
1713                         priv->hw->ps = speed;
1714                 } else {
1715                         dev_warn(priv->device, "invalid port speed\n");
1716                         priv->hw->ps = 0;
1717                 }
1718         }
1719
1720         /* Initialize the MAC Core */
1721         priv->hw->mac->core_init(priv->hw, dev->mtu);
1722
1723         ret = priv->hw->mac->rx_ipc(priv->hw);
1724         if (!ret) {
1725                 pr_warn(" RX IPC Checksum Offload disabled\n");
1726                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1727                 priv->hw->rx_csum = 0;
1728         }
1729
1730         /* Enable the MAC Rx/Tx */
1731         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1732                 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1733         else
1734                 stmmac_set_mac(priv->ioaddr, true);
1735
1736         /* Set the HW DMA mode and the COE */
1737         stmmac_dma_operation_mode(priv);
1738
1739         stmmac_mmc_setup(priv);
1740
1741         if (init_ptp) {
1742                 ret = stmmac_init_ptp(priv);
1743                 if (ret)
1744                         netdev_warn(priv->dev, "fail to init PTP.\n");
1745         }
1746
1747 #ifdef CONFIG_DEBUG_FS
1748         ret = stmmac_init_fs(dev);
1749         if (ret < 0)
1750                 pr_warn("%s: failed debugFS registration\n", __func__);
1751 #endif
1752         /* Dump DMA/MAC registers */
1753         if (netif_msg_hw(priv)) {
1754                 priv->hw->mac->dump_regs(priv->hw);
1755                 priv->hw->dma->dump_regs(priv->ioaddr);
1756         }
1757         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1758
1759         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1760                 priv->rx_riwt = MAX_DMA_RIWT;
1761                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1762         }
1763
1764         if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1765                 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1766
1767         /*  set TX ring length */
1768         if (priv->hw->dma->set_tx_ring_len)
1769                 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1770                                                (DMA_TX_SIZE - 1));
1771         /*  set RX ring length */
1772         if (priv->hw->dma->set_rx_ring_len)
1773                 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1774                                                (DMA_RX_SIZE - 1));
1775         /* Enable TSO */
1776         if (priv->tso)
1777                 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1778
1779         /* Start the ball rolling... */
1780         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1781         priv->hw->dma->start_tx(priv->ioaddr);
1782         priv->hw->dma->start_rx(priv->ioaddr);
1783
1784         return 0;
1785 }
1786
1787 /**
1788  *  stmmac_open - open entry point of the driver
1789  *  @dev : pointer to the device structure.
1790  *  Description:
1791  *  This function is the open entry point of the driver.
1792  *  Return value:
1793  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1794  *  file on failure.
1795  */
1796 static int stmmac_open(struct net_device *dev)
1797 {
1798         struct stmmac_priv *priv = netdev_priv(dev);
1799         int ret;
1800
1801         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1802             priv->hw->pcs != STMMAC_PCS_TBI &&
1803             priv->hw->pcs != STMMAC_PCS_RTBI) {
1804                 ret = stmmac_init_phy(dev);
1805                 if (ret) {
1806                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1807                                __func__, ret);
1808                         return ret;
1809                 }
1810         }
1811
1812         /* Extra statistics */
1813         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1814         priv->xstats.threshold = tc;
1815
1816         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1817         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1818         priv->mss = 0;
1819
1820         ret = alloc_dma_desc_resources(priv);
1821         if (ret < 0) {
1822                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1823                 goto dma_desc_error;
1824         }
1825
1826         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1827         if (ret < 0) {
1828                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1829                 goto init_error;
1830         }
1831
1832         ret = stmmac_hw_setup(dev, true);
1833         if (ret < 0) {
1834                 pr_err("%s: Hw setup failed\n", __func__);
1835                 goto init_error;
1836         }
1837
1838         stmmac_init_tx_coalesce(priv);
1839
1840         if (priv->phydev)
1841                 phy_start(priv->phydev);
1842
1843         /* Request the IRQ lines */
1844         ret = request_irq(dev->irq, stmmac_interrupt,
1845                           IRQF_SHARED, dev->name, dev);
1846         if (unlikely(ret < 0)) {
1847                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1848                        __func__, dev->irq, ret);
1849                 goto init_error;
1850         }
1851
1852         /* Request the Wake IRQ in case of another line is used for WoL */
1853         if (priv->wol_irq != dev->irq) {
1854                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1855                                   IRQF_SHARED, dev->name, dev);
1856                 if (unlikely(ret < 0)) {
1857                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1858                                __func__, priv->wol_irq, ret);
1859                         goto wolirq_error;
1860                 }
1861         }
1862
1863         /* Request the IRQ lines */
1864         if (priv->lpi_irq > 0) {
1865                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1866                                   dev->name, dev);
1867                 if (unlikely(ret < 0)) {
1868                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1869                                __func__, priv->lpi_irq, ret);
1870                         goto lpiirq_error;
1871                 }
1872         }
1873
1874         napi_enable(&priv->napi);
1875         netif_start_queue(dev);
1876
1877         return 0;
1878
1879 lpiirq_error:
1880         if (priv->wol_irq != dev->irq)
1881                 free_irq(priv->wol_irq, dev);
1882 wolirq_error:
1883         free_irq(dev->irq, dev);
1884
1885 init_error:
1886         free_dma_desc_resources(priv);
1887 dma_desc_error:
1888         if (priv->phydev)
1889                 phy_disconnect(priv->phydev);
1890
1891         return ret;
1892 }
1893
1894 /**
1895  *  stmmac_release - close entry point of the driver
1896  *  @dev : device pointer.
1897  *  Description:
1898  *  This is the stop entry point of the driver.
1899  */
1900 static int stmmac_release(struct net_device *dev)
1901 {
1902         struct stmmac_priv *priv = netdev_priv(dev);
1903
1904         /* Stop and disconnect the PHY */
1905         if (priv->phydev) {
1906                 phy_stop(priv->phydev);
1907                 phy_disconnect(priv->phydev);
1908                 priv->phydev = NULL;
1909         }
1910
1911         netif_stop_queue(dev);
1912
1913         napi_disable(&priv->napi);
1914
1915         del_timer_sync(&priv->txtimer);
1916
1917         /* Free the IRQ lines */
1918         free_irq(dev->irq, dev);
1919         if (priv->wol_irq != dev->irq)
1920                 free_irq(priv->wol_irq, dev);
1921         if (priv->lpi_irq > 0)
1922                 free_irq(priv->lpi_irq, dev);
1923
1924         if (priv->eee_enabled) {
1925                 priv->tx_path_in_lpi_mode = false;
1926                 del_timer_sync(&priv->eee_ctrl_timer);
1927         }
1928
1929         /* Stop TX/RX DMA and clear the descriptors */
1930         priv->hw->dma->stop_tx(priv->ioaddr);
1931         priv->hw->dma->stop_rx(priv->ioaddr);
1932
1933         /* Release and free the Rx/Tx resources */
1934         free_dma_desc_resources(priv);
1935
1936         /* Disable the MAC Rx/Tx */
1937         stmmac_set_mac(priv->ioaddr, false);
1938
1939         netif_carrier_off(dev);
1940
1941 #ifdef CONFIG_DEBUG_FS
1942         stmmac_exit_fs(dev);
1943 #endif
1944
1945         stmmac_release_ptp(priv);
1946
1947         return 0;
1948 }
1949
1950 /**
1951  *  stmmac_tso_allocator - close entry point of the driver
1952  *  @priv: driver private structure
1953  *  @des: buffer start address
1954  *  @total_len: total length to fill in descriptors
1955  *  @last_segmant: condition for the last descriptor
1956  *  Description:
1957  *  This function fills descriptor and request new descriptors according to
1958  *  buffer length to fill
1959  */
1960 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1961                                  int total_len, bool last_segment)
1962 {
1963         struct dma_desc *desc;
1964         int tmp_len;
1965         u32 buff_size;
1966
1967         tmp_len = total_len;
1968
1969         while (tmp_len > 0) {
1970                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1971                 desc = priv->dma_tx + priv->cur_tx;
1972
1973                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
1974                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1975                             TSO_MAX_BUFF_SIZE : tmp_len;
1976
1977                 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1978                         0, 1,
1979                         (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
1980                         0, 0);
1981
1982                 tmp_len -= TSO_MAX_BUFF_SIZE;
1983         }
1984 }
1985
1986 /**
1987  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1988  *  @skb : the socket buffer
1989  *  @dev : device pointer
1990  *  Description: this is the transmit function that is called on TSO frames
1991  *  (support available on GMAC4 and newer chips).
1992  *  Diagram below show the ring programming in case of TSO frames:
1993  *
1994  *  First Descriptor
1995  *   --------
1996  *   | DES0 |---> buffer1 = L2/L3/L4 header
1997  *   | DES1 |---> TCP Payload (can continue on next descr...)
1998  *   | DES2 |---> buffer 1 and 2 len
1999  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2000  *   --------
2001  *      |
2002  *     ...
2003  *      |
2004  *   --------
2005  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2006  *   | DES1 | --|
2007  *   | DES2 | --> buffer 1 and 2 len
2008  *   | DES3 |
2009  *   --------
2010  *
2011  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2012  */
2013 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2014 {
2015         u32 pay_len, mss;
2016         int tmp_pay_len = 0;
2017         struct stmmac_priv *priv = netdev_priv(dev);
2018         int nfrags = skb_shinfo(skb)->nr_frags;
2019         unsigned int first_entry, des;
2020         struct dma_desc *desc, *first, *mss_desc = NULL;
2021         u8 proto_hdr_len;
2022         int i;
2023
2024         spin_lock(&priv->tx_lock);
2025
2026         /* Compute header lengths */
2027         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2028
2029         /* Desc availability based on threshold should be enough safe */
2030         if (unlikely(stmmac_tx_avail(priv) <
2031                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2032                 if (!netif_queue_stopped(dev)) {
2033                         netif_stop_queue(dev);
2034                         /* This is a hard error, log it. */
2035                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2036                 }
2037                 spin_unlock(&priv->tx_lock);
2038                 return NETDEV_TX_BUSY;
2039         }
2040
2041         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2042
2043         mss = skb_shinfo(skb)->gso_size;
2044
2045         /* set new MSS value if needed */
2046         if (mss != priv->mss) {
2047                 mss_desc = priv->dma_tx + priv->cur_tx;
2048                 priv->hw->desc->set_mss(mss_desc, mss);
2049                 priv->mss = mss;
2050                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2051         }
2052
2053         if (netif_msg_tx_queued(priv)) {
2054                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2055                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2056                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2057                         skb->data_len);
2058         }
2059
2060         first_entry = priv->cur_tx;
2061
2062         desc = priv->dma_tx + first_entry;
2063         first = desc;
2064
2065         /* first descriptor: fill Headers on Buf1 */
2066         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2067                              DMA_TO_DEVICE);
2068         if (dma_mapping_error(priv->device, des))
2069                 goto dma_map_err;
2070
2071         priv->tx_skbuff_dma[first_entry].buf = des;
2072         priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2073         priv->tx_skbuff[first_entry] = skb;
2074
2075         first->des0 = cpu_to_le32(des);
2076
2077         /* Fill start of payload in buff2 of first descriptor */
2078         if (pay_len)
2079                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2080
2081         /* If needed take extra descriptors to fill the remaining payload */
2082         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2083
2084         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2085
2086         /* Prepare fragments */
2087         for (i = 0; i < nfrags; i++) {
2088                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2089
2090                 des = skb_frag_dma_map(priv->device, frag, 0,
2091                                        skb_frag_size(frag),
2092                                        DMA_TO_DEVICE);
2093
2094                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2095                                      (i == nfrags - 1));
2096
2097                 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2098                 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2099                 priv->tx_skbuff[priv->cur_tx] = NULL;
2100                 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2101         }
2102
2103         priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2104
2105         priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2106
2107         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2108                 if (netif_msg_hw(priv))
2109                         pr_debug("%s: stop transmitted packets\n", __func__);
2110                 netif_stop_queue(dev);
2111         }
2112
2113         dev->stats.tx_bytes += skb->len;
2114         priv->xstats.tx_tso_frames++;
2115         priv->xstats.tx_tso_nfrags += nfrags;
2116
2117         /* Manage tx mitigation */
2118         priv->tx_count_frames += nfrags + 1;
2119         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2120                 mod_timer(&priv->txtimer,
2121                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2122         } else {
2123                 priv->tx_count_frames = 0;
2124                 priv->hw->desc->set_tx_ic(desc);
2125                 priv->xstats.tx_set_ic_bit++;
2126         }
2127
2128         if (!priv->hwts_tx_en)
2129                 skb_tx_timestamp(skb);
2130
2131         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2132                      priv->hwts_tx_en)) {
2133                 /* declare that device is doing timestamping */
2134                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2135                 priv->hw->desc->enable_tx_timestamp(first);
2136         }
2137
2138         /* Complete the first descriptor before granting the DMA */
2139         priv->hw->desc->prepare_tso_tx_desc(first, 1,
2140                         proto_hdr_len,
2141                         pay_len,
2142                         1, priv->tx_skbuff_dma[first_entry].last_segment,
2143                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2144
2145         /* If context desc is used to change MSS */
2146         if (mss_desc) {
2147                 /* Make sure that first descriptor has been completely
2148                  * written, including its own bit. This is because MSS is
2149                  * actually before first descriptor, so we need to make
2150                  * sure that MSS's own bit is the last thing written.
2151                  */
2152                 dma_wmb();
2153                 priv->hw->desc->set_tx_owner(mss_desc);
2154         }
2155
2156         /* The own bit must be the latest setting done when prepare the
2157          * descriptor and then barrier is needed to make sure that
2158          * all is coherent before granting the DMA engine.
2159          */
2160         smp_wmb();
2161
2162         if (netif_msg_pktdata(priv)) {
2163                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2164                         __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2165                         priv->cur_tx, first, nfrags);
2166
2167                 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2168                                              0);
2169
2170                 pr_info(">>> frame to be transmitted: ");
2171                 print_pkt(skb->data, skb_headlen(skb));
2172         }
2173
2174         netdev_sent_queue(dev, skb->len);
2175
2176         priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2177                                        STMMAC_CHAN0);
2178
2179         spin_unlock(&priv->tx_lock);
2180         return NETDEV_TX_OK;
2181
2182 dma_map_err:
2183         spin_unlock(&priv->tx_lock);
2184         dev_err(priv->device, "Tx dma map failed\n");
2185         dev_kfree_skb(skb);
2186         priv->dev->stats.tx_dropped++;
2187         return NETDEV_TX_OK;
2188 }
2189
2190 /**
2191  *  stmmac_xmit - Tx entry point of the driver
2192  *  @skb : the socket buffer
2193  *  @dev : device pointer
2194  *  Description : this is the tx entry point of the driver.
2195  *  It programs the chain or the ring and supports oversized frames
2196  *  and SG feature.
2197  */
2198 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2199 {
2200         struct stmmac_priv *priv = netdev_priv(dev);
2201         unsigned int nopaged_len = skb_headlen(skb);
2202         int i, csum_insertion = 0, is_jumbo = 0;
2203         int nfrags = skb_shinfo(skb)->nr_frags;
2204         int entry;
2205         unsigned int first_entry;
2206         struct dma_desc *desc, *first;
2207         unsigned int enh_desc;
2208         unsigned int des;
2209
2210         /* Manage oversized TCP frames for GMAC4 device */
2211         if (skb_is_gso(skb) && priv->tso) {
2212                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2213                         return stmmac_tso_xmit(skb, dev);
2214         }
2215
2216         spin_lock(&priv->tx_lock);
2217
2218         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2219                 spin_unlock(&priv->tx_lock);
2220                 if (!netif_queue_stopped(dev)) {
2221                         netif_stop_queue(dev);
2222                         /* This is a hard error, log it. */
2223                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2224                 }
2225                 return NETDEV_TX_BUSY;
2226         }
2227
2228         if (priv->tx_path_in_lpi_mode)
2229                 stmmac_disable_eee_mode(priv);
2230
2231         entry = priv->cur_tx;
2232         first_entry = entry;
2233
2234         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2235
2236         if (likely(priv->extend_desc))
2237                 desc = (struct dma_desc *)(priv->dma_etx + entry);
2238         else
2239                 desc = priv->dma_tx + entry;
2240
2241         first = desc;
2242
2243         priv->tx_skbuff[first_entry] = skb;
2244
2245         enh_desc = priv->plat->enh_desc;
2246         /* To program the descriptors according to the size of the frame */
2247         if (enh_desc)
2248                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2249
2250         if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2251                                          DWMAC_CORE_4_00)) {
2252                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2253                 if (unlikely(entry < 0))
2254                         goto dma_map_err;
2255         }
2256
2257         for (i = 0; i < nfrags; i++) {
2258                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2259                 int len = skb_frag_size(frag);
2260                 bool last_segment = (i == (nfrags - 1));
2261
2262                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2263
2264                 if (likely(priv->extend_desc))
2265                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2266                 else
2267                         desc = priv->dma_tx + entry;
2268
2269                 des = skb_frag_dma_map(priv->device, frag, 0, len,
2270                                        DMA_TO_DEVICE);
2271                 if (dma_mapping_error(priv->device, des))
2272                         goto dma_map_err; /* should reuse desc w/o issues */
2273
2274                 priv->tx_skbuff[entry] = NULL;
2275
2276                 priv->tx_skbuff_dma[entry].buf = des;
2277                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2278                         desc->des0 = cpu_to_le32(des);
2279                 else
2280                         desc->des2 = cpu_to_le32(des);
2281
2282                 priv->tx_skbuff_dma[entry].map_as_page = true;
2283                 priv->tx_skbuff_dma[entry].len = len;
2284                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2285
2286                 /* Prepare the descriptor and set the own bit too */
2287                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2288                                                 priv->mode, 1, last_segment);
2289         }
2290
2291         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2292
2293         priv->cur_tx = entry;
2294
2295         if (netif_msg_pktdata(priv)) {
2296                 void *tx_head;
2297
2298                 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2299                          __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2300                          entry, first, nfrags);
2301
2302                 if (priv->extend_desc)
2303                         tx_head = (void *)priv->dma_etx;
2304                 else
2305                         tx_head = (void *)priv->dma_tx;
2306
2307                 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2308
2309                 pr_debug(">>> frame to be transmitted: ");
2310                 print_pkt(skb->data, skb->len);
2311         }
2312
2313         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2314                 if (netif_msg_hw(priv))
2315                         pr_debug("%s: stop transmitted packets\n", __func__);
2316                 netif_stop_queue(dev);
2317         }
2318
2319         dev->stats.tx_bytes += skb->len;
2320
2321         /* According to the coalesce parameter the IC bit for the latest
2322          * segment is reset and the timer re-started to clean the tx status.
2323          * This approach takes care about the fragments: desc is the first
2324          * element in case of no SG.
2325          */
2326         priv->tx_count_frames += nfrags + 1;
2327         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2328                 mod_timer(&priv->txtimer,
2329                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2330         } else {
2331                 priv->tx_count_frames = 0;
2332                 priv->hw->desc->set_tx_ic(desc);
2333                 priv->xstats.tx_set_ic_bit++;
2334         }
2335
2336         if (!priv->hwts_tx_en)
2337                 skb_tx_timestamp(skb);
2338
2339         /* Ready to fill the first descriptor and set the OWN bit w/o any
2340          * problems because all the descriptors are actually ready to be
2341          * passed to the DMA engine.
2342          */
2343         if (likely(!is_jumbo)) {
2344                 bool last_segment = (nfrags == 0);
2345
2346                 des = dma_map_single(priv->device, skb->data,
2347                                      nopaged_len, DMA_TO_DEVICE);
2348                 if (dma_mapping_error(priv->device, des))
2349                         goto dma_map_err;
2350
2351                 priv->tx_skbuff_dma[first_entry].buf = des;
2352                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2353                         first->des0 = cpu_to_le32(des);
2354                 else
2355                         first->des2 = cpu_to_le32(des);
2356
2357                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2358                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2359
2360                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2361                              priv->hwts_tx_en)) {
2362                         /* declare that device is doing timestamping */
2363                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2364                         priv->hw->desc->enable_tx_timestamp(first);
2365                 }
2366
2367                 /* Prepare the first descriptor setting the OWN bit too */
2368                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2369                                                 csum_insertion, priv->mode, 1,
2370                                                 last_segment);
2371
2372                 /* The own bit must be the latest setting done when prepare the
2373                  * descriptor and then barrier is needed to make sure that
2374                  * all is coherent before granting the DMA engine.
2375                  */
2376                 smp_wmb();
2377         }
2378
2379         netdev_sent_queue(dev, skb->len);
2380
2381         if (priv->synopsys_id < DWMAC_CORE_4_00)
2382                 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2383         else
2384                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2385                                                STMMAC_CHAN0);
2386
2387         spin_unlock(&priv->tx_lock);
2388         return NETDEV_TX_OK;
2389
2390 dma_map_err:
2391         spin_unlock(&priv->tx_lock);
2392         dev_err(priv->device, "Tx dma map failed\n");
2393         dev_kfree_skb(skb);
2394         priv->dev->stats.tx_dropped++;
2395         return NETDEV_TX_OK;
2396 }
2397
2398 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2399 {
2400         struct ethhdr *ehdr;
2401         u16 vlanid;
2402
2403         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2404             NETIF_F_HW_VLAN_CTAG_RX &&
2405             !__vlan_get_tag(skb, &vlanid)) {
2406                 /* pop the vlan tag */
2407                 ehdr = (struct ethhdr *)skb->data;
2408                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2409                 skb_pull(skb, VLAN_HLEN);
2410                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2411         }
2412 }
2413
2414
2415 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2416 {
2417         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2418                 return 0;
2419
2420         return 1;
2421 }
2422
2423 /**
2424  * stmmac_rx_refill - refill used skb preallocated buffers
2425  * @priv: driver private structure
2426  * Description : this is to reallocate the skb for the reception process
2427  * that is based on zero-copy.
2428  */
2429 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2430 {
2431         int bfsize = priv->dma_buf_sz;
2432         unsigned int entry = priv->dirty_rx;
2433         int dirty = stmmac_rx_dirty(priv);
2434
2435         while (dirty-- > 0) {
2436                 struct dma_desc *p;
2437
2438                 if (priv->extend_desc)
2439                         p = (struct dma_desc *)(priv->dma_erx + entry);
2440                 else
2441                         p = priv->dma_rx + entry;
2442
2443                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2444                         struct sk_buff *skb;
2445
2446                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2447                         if (unlikely(!skb)) {
2448                                 /* so for a while no zero-copy! */
2449                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2450                                 if (unlikely(net_ratelimit()))
2451                                         dev_err(priv->device,
2452                                                 "fail to alloc skb entry %d\n",
2453                                                 entry);
2454                                 break;
2455                         }
2456
2457                         priv->rx_skbuff[entry] = skb;
2458                         priv->rx_skbuff_dma[entry] =
2459                             dma_map_single(priv->device, skb->data, bfsize,
2460                                            DMA_FROM_DEVICE);
2461                         if (dma_mapping_error(priv->device,
2462                                               priv->rx_skbuff_dma[entry])) {
2463                                 dev_err(priv->device, "Rx dma map failed\n");
2464                                 dev_kfree_skb(skb);
2465                                 break;
2466                         }
2467
2468                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2469                                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2470                                 p->des1 = 0;
2471                         } else {
2472                                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2473                         }
2474                         if (priv->hw->mode->refill_desc3)
2475                                 priv->hw->mode->refill_desc3(priv, p);
2476
2477                         if (priv->rx_zeroc_thresh > 0)
2478                                 priv->rx_zeroc_thresh--;
2479
2480                         if (netif_msg_rx_status(priv))
2481                                 pr_debug("\trefill entry #%d\n", entry);
2482                 }
2483                 wmb();
2484
2485                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2486                         priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0, priv->dma_buf_sz);
2487                 else
2488                         priv->hw->desc->set_rx_owner(p);
2489
2490                 wmb();
2491
2492                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2493         }
2494         priv->dirty_rx = entry;
2495 }
2496
2497 /**
2498  * stmmac_rx - manage the receive process
2499  * @priv: driver private structure
2500  * @limit: napi bugget.
2501  * Description :  this the function called by the napi poll method.
2502  * It gets all the frames inside the ring.
2503  */
2504 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2505 {
2506         unsigned int next_entry = priv->cur_rx;
2507         unsigned int count = 0;
2508         int coe = priv->hw->rx_csum;
2509
2510         if (netif_msg_rx_status(priv)) {
2511                 void *rx_head;
2512
2513                 pr_info(">>>>>> %s: descriptor ring:\n", __func__);
2514                 if (priv->extend_desc)
2515                         rx_head = (void *)priv->dma_erx;
2516                 else
2517                         rx_head = (void *)priv->dma_rx;
2518
2519                 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2520         }
2521         while (count < limit) {
2522                 int entry, status;
2523                 struct dma_desc *p;
2524                 struct dma_desc *np;
2525
2526                 entry = next_entry;
2527
2528                 if (priv->extend_desc)
2529                         p = (struct dma_desc *)(priv->dma_erx + entry);
2530                 else
2531                         p = priv->dma_rx + entry;
2532
2533                 /* read the status of the incoming frame */
2534                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2535                                                    &priv->xstats, p);
2536                 /* check if managed by the DMA otherwise go ahead */
2537                 if (unlikely(status & dma_own))
2538                         break;
2539
2540                 count++;
2541
2542                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2543                 next_entry = priv->cur_rx;
2544
2545                 if (priv->extend_desc)
2546                         np = (struct dma_desc *)(priv->dma_erx + next_entry);
2547                 else
2548                         np = priv->dma_rx + next_entry;
2549
2550                 prefetch(np);
2551
2552                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2553                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2554                                                            &priv->xstats,
2555                                                            priv->dma_erx +
2556                                                            entry);
2557                 if (unlikely(status == discard_frame)) {
2558                         priv->dev->stats.rx_errors++;
2559                         if (priv->hwts_rx_en && !priv->extend_desc) {
2560                                 /* DESC2 & DESC3 will be overwitten by device
2561                                  * with timestamp value, hence reinitialize
2562                                  * them in stmmac_rx_refill() function so that
2563                                  * device can reuse it.
2564                                  */
2565                                 priv->rx_skbuff[entry] = NULL;
2566                                 dma_unmap_single(priv->device,
2567                                                  priv->rx_skbuff_dma[entry],
2568                                                  priv->dma_buf_sz,
2569                                                  DMA_FROM_DEVICE);
2570                         }
2571                 } else {
2572                         struct sk_buff *skb;
2573                         int frame_len;
2574                         unsigned int des;
2575
2576                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2577                                 des = le32_to_cpu(p->des0);
2578                         else
2579                                 des = le32_to_cpu(p->des2);
2580
2581                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2582
2583                         /*  If frame length is greather than skb buffer size
2584                          *  (preallocated during init) then the packet is
2585                          *  ignored
2586                          */
2587                         if (frame_len > priv->dma_buf_sz) {
2588                                 pr_err("%s: len %d larger than size (%d)\n",
2589                                        priv->dev->name, frame_len,
2590                                        priv->dma_buf_sz);
2591                                 priv->dev->stats.rx_length_errors++;
2592                                 continue;
2593                         }
2594
2595                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2596                          * Type frames (LLC/LLC-SNAP)
2597                          */
2598                         if (unlikely(status != llc_snap))
2599                                 frame_len -= ETH_FCS_LEN;
2600
2601                         if (netif_msg_rx_status(priv)) {
2602                                 pr_info("\tdesc: %p [entry %d] buff=0x%x\n",
2603                                         p, entry, des);
2604                                 if (frame_len > ETH_FRAME_LEN)
2605                                         pr_debug("\tframe size %d, COE: %d\n",
2606                                                  frame_len, status);
2607                         }
2608
2609                         /* The zero-copy is always used for all the sizes
2610                          * in case of GMAC4 because it needs
2611                          * to refill the used descriptors, always.
2612                          */
2613                         if (unlikely(!priv->plat->has_gmac4 &&
2614                                      ((frame_len < priv->rx_copybreak) ||
2615                                      stmmac_rx_threshold_count(priv)))) {
2616                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2617                                                                 frame_len);
2618                                 if (unlikely(!skb)) {
2619                                         if (net_ratelimit())
2620                                                 dev_warn(priv->device,
2621                                                          "packet dropped\n");
2622                                         priv->dev->stats.rx_dropped++;
2623                                         continue;
2624                                 }
2625
2626                                 dma_sync_single_for_cpu(priv->device,
2627                                                         priv->rx_skbuff_dma
2628                                                         [entry], frame_len,
2629                                                         DMA_FROM_DEVICE);
2630                                 skb_copy_to_linear_data(skb,
2631                                                         priv->
2632                                                         rx_skbuff[entry]->data,
2633                                                         frame_len);
2634
2635                                 skb_put(skb, frame_len);
2636                                 dma_sync_single_for_device(priv->device,
2637                                                            priv->rx_skbuff_dma
2638                                                            [entry], frame_len,
2639                                                            DMA_FROM_DEVICE);
2640                         } else {
2641                                 skb = priv->rx_skbuff[entry];
2642                                 if (unlikely(!skb)) {
2643                                         pr_err("%s: Inconsistent Rx chain\n",
2644                                                priv->dev->name);
2645                                         priv->dev->stats.rx_dropped++;
2646                                         continue;
2647                                 }
2648                                 prefetch(skb->data - NET_IP_ALIGN);
2649                                 priv->rx_skbuff[entry] = NULL;
2650                                 priv->rx_zeroc_thresh++;
2651
2652                                 skb_put(skb, frame_len);
2653                                 dma_unmap_single(priv->device,
2654                                                  priv->rx_skbuff_dma[entry],
2655                                                  priv->dma_buf_sz,
2656                                                  DMA_FROM_DEVICE);
2657                         }
2658
2659                         if (netif_msg_pktdata(priv)) {
2660                                 pr_debug("frame received (%dbytes)", frame_len);
2661                                 print_pkt(skb->data, frame_len);
2662                         }
2663
2664                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
2665
2666                         stmmac_rx_vlan(priv->dev, skb);
2667
2668                         skb->protocol = eth_type_trans(skb, priv->dev);
2669
2670                         if (unlikely(!coe))
2671                                 skb_checksum_none_assert(skb);
2672                         else
2673                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2674
2675                         napi_gro_receive(&priv->napi, skb);
2676
2677                         priv->dev->stats.rx_packets++;
2678                         priv->dev->stats.rx_bytes += frame_len;
2679                 }
2680         }
2681
2682         stmmac_rx_refill(priv);
2683
2684         priv->xstats.rx_pkt_n += count;
2685
2686         return count;
2687 }
2688
2689 /**
2690  *  stmmac_poll - stmmac poll method (NAPI)
2691  *  @napi : pointer to the napi structure.
2692  *  @budget : maximum number of packets that the current CPU can receive from
2693  *            all interfaces.
2694  *  Description :
2695  *  To look at the incoming frames and clear the tx resources.
2696  */
2697 static int stmmac_poll(struct napi_struct *napi, int budget)
2698 {
2699         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2700         int work_done = 0;
2701
2702         priv->xstats.napi_poll++;
2703         stmmac_tx_clean(priv);
2704
2705         work_done = stmmac_rx(priv, budget);
2706         if (work_done < budget) {
2707                 napi_complete(napi);
2708                 stmmac_enable_dma_irq(priv);
2709         }
2710         return work_done;
2711 }
2712
2713 /**
2714  *  stmmac_tx_timeout
2715  *  @dev : Pointer to net device structure
2716  *  Description: this function is called when a packet transmission fails to
2717  *   complete within a reasonable time. The driver will mark the error in the
2718  *   netdev structure and arrange for the device to be reset to a sane state
2719  *   in order to transmit a new packet.
2720  */
2721 static void stmmac_tx_timeout(struct net_device *dev)
2722 {
2723         struct stmmac_priv *priv = netdev_priv(dev);
2724
2725         /* Clear Tx resources and restart transmitting again */
2726         stmmac_tx_err(priv);
2727 }
2728
2729 /**
2730  *  stmmac_set_rx_mode - entry point for multicast addressing
2731  *  @dev : pointer to the device structure
2732  *  Description:
2733  *  This function is a driver entry point which gets called by the kernel
2734  *  whenever multicast addresses must be enabled/disabled.
2735  *  Return value:
2736  *  void.
2737  */
2738 static void stmmac_set_rx_mode(struct net_device *dev)
2739 {
2740         struct stmmac_priv *priv = netdev_priv(dev);
2741
2742         priv->hw->mac->set_filter(priv->hw, dev);
2743 }
2744
2745 /**
2746  *  stmmac_change_mtu - entry point to change MTU size for the device.
2747  *  @dev : device pointer.
2748  *  @new_mtu : the new MTU size for the device.
2749  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2750  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2751  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2752  *  Return value:
2753  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2754  *  file on failure.
2755  */
2756 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2757 {
2758         struct stmmac_priv *priv = netdev_priv(dev);
2759         int max_mtu;
2760
2761         if (netif_running(dev)) {
2762                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2763                 return -EBUSY;
2764         }
2765
2766         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2767                 max_mtu = JUMBO_LEN;
2768         else
2769                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2770
2771         if (priv->plat->maxmtu < max_mtu)
2772                 max_mtu = priv->plat->maxmtu;
2773
2774         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2775                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2776                 return -EINVAL;
2777         }
2778
2779         dev->mtu = new_mtu;
2780
2781         netdev_update_features(dev);
2782
2783         return 0;
2784 }
2785
2786 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2787                                              netdev_features_t features)
2788 {
2789         struct stmmac_priv *priv = netdev_priv(dev);
2790
2791         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2792                 features &= ~NETIF_F_RXCSUM;
2793
2794         if (!priv->plat->tx_coe)
2795                 features &= ~NETIF_F_CSUM_MASK;
2796
2797         /* Some GMAC devices have a bugged Jumbo frame support that
2798          * needs to have the Tx COE disabled for oversized frames
2799          * (due to limited buffer sizes). In this case we disable
2800          * the TX csum insertionin the TDES and not use SF.
2801          */
2802         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2803                 features &= ~NETIF_F_CSUM_MASK;
2804
2805         /* Disable tso if asked by ethtool */
2806         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2807                 if (features & NETIF_F_TSO)
2808                         priv->tso = true;
2809                 else
2810                         priv->tso = false;
2811         }
2812
2813         return features;
2814 }
2815
2816 static int stmmac_set_features(struct net_device *netdev,
2817                                netdev_features_t features)
2818 {
2819         struct stmmac_priv *priv = netdev_priv(netdev);
2820
2821         /* Keep the COE Type in case of csum is supporting */
2822         if (features & NETIF_F_RXCSUM)
2823                 priv->hw->rx_csum = priv->plat->rx_coe;
2824         else
2825                 priv->hw->rx_csum = 0;
2826         /* No check needed because rx_coe has been set before and it will be
2827          * fixed in case of issue.
2828          */
2829         priv->hw->mac->rx_ipc(priv->hw);
2830
2831         return 0;
2832 }
2833
2834 /**
2835  *  stmmac_interrupt - main ISR
2836  *  @irq: interrupt number.
2837  *  @dev_id: to pass the net device pointer.
2838  *  Description: this is the main driver interrupt service routine.
2839  *  It can call:
2840  *  o DMA service routine (to manage incoming frame reception and transmission
2841  *    status)
2842  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2843  *    interrupts.
2844  */
2845 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2846 {
2847         struct net_device *dev = (struct net_device *)dev_id;
2848         struct stmmac_priv *priv = netdev_priv(dev);
2849
2850         if (priv->irq_wake)
2851                 pm_wakeup_event(priv->device, 0);
2852
2853         if (unlikely(!dev)) {
2854                 pr_err("%s: invalid dev pointer\n", __func__);
2855                 return IRQ_NONE;
2856         }
2857
2858         /* To handle GMAC own interrupts */
2859         if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2860                 int status = priv->hw->mac->host_irq_status(priv->hw,
2861                                                             &priv->xstats);
2862                 if (unlikely(status)) {
2863                         /* For LPI we need to save the tx status */
2864                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2865                                 priv->tx_path_in_lpi_mode = true;
2866                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2867                                 priv->tx_path_in_lpi_mode = false;
2868                         if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2869                                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2870                                                         priv->rx_tail_addr,
2871                                                         STMMAC_CHAN0);
2872                 }
2873
2874                 /* PCS link status */
2875                 if (priv->hw->pcs) {
2876                         if (priv->xstats.pcs_link)
2877                                 netif_carrier_on(dev);
2878                         else
2879                                 netif_carrier_off(dev);
2880                 }
2881         }
2882
2883         /* To handle DMA interrupts */
2884         stmmac_dma_interrupt(priv);
2885
2886         return IRQ_HANDLED;
2887 }
2888
2889 #ifdef CONFIG_NET_POLL_CONTROLLER
2890 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2891  * to allow network I/O with interrupts disabled.
2892  */
2893 static void stmmac_poll_controller(struct net_device *dev)
2894 {
2895         disable_irq(dev->irq);
2896         stmmac_interrupt(dev->irq, dev);
2897         enable_irq(dev->irq);
2898 }
2899 #endif
2900
2901 /**
2902  *  stmmac_ioctl - Entry point for the Ioctl
2903  *  @dev: Device pointer.
2904  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2905  *  a proprietary structure used to pass information to the driver.
2906  *  @cmd: IOCTL command
2907  *  Description:
2908  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2909  */
2910 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2911 {
2912         struct stmmac_priv *priv = netdev_priv(dev);
2913         int ret = -EOPNOTSUPP;
2914
2915         if (!netif_running(dev))
2916                 return -EINVAL;
2917
2918         switch (cmd) {
2919         case SIOCGMIIPHY:
2920         case SIOCGMIIREG:
2921         case SIOCSMIIREG:
2922                 if (!priv->phydev)
2923                         return -EINVAL;
2924                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2925                 break;
2926         case SIOCSHWTSTAMP:
2927                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2928                 break;
2929         default:
2930                 break;
2931         }
2932
2933         return ret;
2934 }
2935
2936 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
2937 {
2938         struct stmmac_priv *priv = netdev_priv(ndev);
2939         int ret = 0;
2940
2941         ret = eth_mac_addr(ndev, addr);
2942         if (ret)
2943                 return ret;
2944
2945         priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);
2946
2947         return ret;
2948 }
2949
2950 #ifdef CONFIG_DEBUG_FS
2951 static struct dentry *stmmac_fs_dir;
2952
2953 static void sysfs_display_ring(void *head, int size, int extend_desc,
2954                                struct seq_file *seq)
2955 {
2956         int i;
2957         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2958         struct dma_desc *p = (struct dma_desc *)head;
2959
2960         for (i = 0; i < size; i++) {
2961                 u64 x;
2962                 if (extend_desc) {
2963                         x = *(u64 *) ep;
2964                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2965                                    i, (unsigned int)virt_to_phys(ep),
2966                                    le32_to_cpu(ep->basic.des0),
2967                                    le32_to_cpu(ep->basic.des1),
2968                                    le32_to_cpu(ep->basic.des2),
2969                                    le32_to_cpu(ep->basic.des3));
2970                         ep++;
2971                 } else {
2972                         x = *(u64 *) p;
2973                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2974                                    i, (unsigned int)virt_to_phys(ep),
2975                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
2976                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
2977                         p++;
2978                 }
2979                 seq_printf(seq, "\n");
2980         }
2981 }
2982
2983 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2984 {
2985         struct net_device *dev = seq->private;
2986         struct stmmac_priv *priv = netdev_priv(dev);
2987
2988         if (priv->extend_desc) {
2989                 seq_printf(seq, "Extended RX descriptor ring:\n");
2990                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2991                 seq_printf(seq, "Extended TX descriptor ring:\n");
2992                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2993         } else {
2994                 seq_printf(seq, "RX descriptor ring:\n");
2995                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2996                 seq_printf(seq, "TX descriptor ring:\n");
2997                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3004 {
3005         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3006 }
3007
3008 static const struct file_operations stmmac_rings_status_fops = {
3009         .owner = THIS_MODULE,
3010         .open = stmmac_sysfs_ring_open,
3011         .read = seq_read,
3012         .llseek = seq_lseek,
3013         .release = single_release,
3014 };
3015
3016 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3017 {
3018         struct net_device *dev = seq->private;
3019         struct stmmac_priv *priv = netdev_priv(dev);
3020
3021         if (!priv->hw_cap_support) {
3022                 seq_printf(seq, "DMA HW features not supported\n");
3023                 return 0;
3024         }
3025
3026         seq_printf(seq, "==============================\n");
3027         seq_printf(seq, "\tDMA HW features\n");
3028         seq_printf(seq, "==============================\n");
3029
3030         seq_printf(seq, "\t10/100 Mbps %s\n",
3031                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3032         seq_printf(seq, "\t1000 Mbps %s\n",
3033                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3034         seq_printf(seq, "\tHalf duple %s\n",
3035                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3036         seq_printf(seq, "\tHash Filter: %s\n",
3037                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3038         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3039                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3040         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
3041                    (priv->dma_cap.pcs) ? "Y" : "N");
3042         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3043                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3044         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3045                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3046         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3047                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3048         seq_printf(seq, "\tRMON module: %s\n",
3049                    (priv->dma_cap.rmon) ? "Y" : "N");
3050         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3051                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3052         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
3053                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3054         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3055                    (priv->dma_cap.eee) ? "Y" : "N");
3056         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3057         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3058                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3059         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3060                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3061                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3062         } else {
3063                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3064                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3065                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3066                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3067         }
3068         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3069                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3070         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3071                    priv->dma_cap.number_rx_channel);
3072         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3073                    priv->dma_cap.number_tx_channel);
3074         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3075                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3076
3077         return 0;
3078 }
3079
3080 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3081 {
3082         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3083 }
3084
3085 static const struct file_operations stmmac_dma_cap_fops = {
3086         .owner = THIS_MODULE,
3087         .open = stmmac_sysfs_dma_cap_open,
3088         .read = seq_read,
3089         .llseek = seq_lseek,
3090         .release = single_release,
3091 };
3092
3093 static int stmmac_init_fs(struct net_device *dev)
3094 {
3095         struct stmmac_priv *priv = netdev_priv(dev);
3096
3097         /* Create per netdev entries */
3098         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3099
3100         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3101                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3102                        STMMAC_RESOURCE_NAME, dev->name);
3103
3104                 return -ENOMEM;
3105         }
3106
3107         /* Entry to report DMA RX/TX rings */
3108         priv->dbgfs_rings_status =
3109                 debugfs_create_file("descriptors_status", S_IRUGO,
3110                                     priv->dbgfs_dir, dev,
3111                                     &stmmac_rings_status_fops);
3112
3113         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3114                 pr_info("ERROR creating stmmac ring debugfs file\n");
3115                 debugfs_remove_recursive(priv->dbgfs_dir);
3116
3117                 return -ENOMEM;
3118         }
3119
3120         /* Entry to report the DMA HW features */
3121         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3122                                             priv->dbgfs_dir,
3123                                             dev, &stmmac_dma_cap_fops);
3124
3125         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3126                 pr_info("ERROR creating stmmac MMC debugfs file\n");
3127                 debugfs_remove_recursive(priv->dbgfs_dir);
3128
3129                 return -ENOMEM;
3130         }
3131
3132         return 0;
3133 }
3134
3135 static void stmmac_exit_fs(struct net_device *dev)
3136 {
3137         struct stmmac_priv *priv = netdev_priv(dev);
3138
3139         debugfs_remove_recursive(priv->dbgfs_dir);
3140 }
3141 #endif /* CONFIG_DEBUG_FS */
3142
3143 static const struct net_device_ops stmmac_netdev_ops = {
3144         .ndo_open = stmmac_open,
3145         .ndo_start_xmit = stmmac_xmit,
3146         .ndo_stop = stmmac_release,
3147         .ndo_change_mtu = stmmac_change_mtu,
3148         .ndo_fix_features = stmmac_fix_features,
3149         .ndo_set_features = stmmac_set_features,
3150         .ndo_set_rx_mode = stmmac_set_rx_mode,
3151         .ndo_tx_timeout = stmmac_tx_timeout,
3152         .ndo_do_ioctl = stmmac_ioctl,
3153 #ifdef CONFIG_NET_POLL_CONTROLLER
3154         .ndo_poll_controller = stmmac_poll_controller,
3155 #endif
3156         .ndo_set_mac_address = stmmac_set_mac_address,
3157 };
3158
3159 /**
3160  *  stmmac_hw_init - Init the MAC device
3161  *  @priv: driver private structure
3162  *  Description: this function is to configure the MAC device according to
3163  *  some platform parameters or the HW capability register. It prepares the
3164  *  driver to use either ring or chain modes and to setup either enhanced or
3165  *  normal descriptors.
3166  */
3167 static int stmmac_hw_init(struct stmmac_priv *priv)
3168 {
3169         struct mac_device_info *mac;
3170
3171         /* Identify the MAC HW device */
3172         if (priv->plat->has_gmac) {
3173                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3174                 mac = dwmac1000_setup(priv->ioaddr,
3175                                       priv->plat->multicast_filter_bins,
3176                                       priv->plat->unicast_filter_entries,
3177                                       &priv->synopsys_id);
3178         } else if (priv->plat->has_gmac4) {
3179                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3180                 mac = dwmac4_setup(priv->ioaddr,
3181                                    priv->plat->multicast_filter_bins,
3182                                    priv->plat->unicast_filter_entries,
3183                                    &priv->synopsys_id);
3184         } else {
3185                 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3186         }
3187         if (!mac)
3188                 return -ENOMEM;
3189
3190         priv->hw = mac;
3191
3192         /* To use the chained or ring mode */
3193         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3194                 priv->hw->mode = &dwmac4_ring_mode_ops;
3195         } else {
3196                 if (chain_mode) {
3197                         priv->hw->mode = &chain_mode_ops;
3198                         pr_info(" Chain mode enabled\n");
3199                         priv->mode = STMMAC_CHAIN_MODE;
3200                 } else {
3201                         priv->hw->mode = &ring_mode_ops;
3202                         pr_info(" Ring mode enabled\n");
3203                         priv->mode = STMMAC_RING_MODE;
3204                 }
3205         }
3206
3207         /* Get the HW capability (new GMAC newer than 3.50a) */
3208         priv->hw_cap_support = stmmac_get_hw_features(priv);
3209         if (priv->hw_cap_support) {
3210                 pr_info(" DMA HW capability register supported");
3211
3212                 /* We can override some gmac/dma configuration fields: e.g.
3213                  * enh_desc, tx_coe (e.g. that are passed through the
3214                  * platform) with the values from the HW capability
3215                  * register (if supported).
3216                  */
3217                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3218                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3219                 priv->hw->pmt = priv->plat->pmt;
3220
3221                 /* TXCOE doesn't work in thresh DMA mode */
3222                 if (priv->plat->force_thresh_dma_mode)
3223                         priv->plat->tx_coe = 0;
3224                 else
3225                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
3226
3227                 /* In case of GMAC4 rx_coe is from HW cap register. */
3228                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3229
3230                 if (priv->dma_cap.rx_coe_type2)
3231                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3232                 else if (priv->dma_cap.rx_coe_type1)
3233                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3234
3235         } else
3236                 pr_info(" No HW DMA feature register supported");
3237
3238         /* To use alternate (extended), normal or GMAC4 descriptor structures */
3239         if (priv->synopsys_id >= DWMAC_CORE_4_00)
3240                 priv->hw->desc = &dwmac4_desc_ops;
3241         else
3242                 stmmac_selec_desc_mode(priv);
3243
3244         if (priv->plat->rx_coe) {
3245                 priv->hw->rx_csum = priv->plat->rx_coe;
3246                 pr_info(" RX Checksum Offload Engine supported\n");
3247                 if (priv->synopsys_id < DWMAC_CORE_4_00)
3248                         pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3249         }
3250         if (priv->plat->tx_coe)
3251                 pr_info(" TX Checksum insertion supported\n");
3252
3253         if (priv->plat->pmt) {
3254                 pr_info(" Wake-Up On Lan supported\n");
3255                 device_set_wakeup_capable(priv->device, 1);
3256         }
3257
3258         if (priv->dma_cap.tsoen)
3259                 pr_info(" TSO supported\n");
3260
3261         return 0;
3262 }
3263
3264 /**
3265  * stmmac_dvr_probe
3266  * @device: device pointer
3267  * @plat_dat: platform data pointer
3268  * @res: stmmac resource pointer
3269  * Description: this is the main probe function used to
3270  * call the alloc_etherdev, allocate the priv structure.
3271  * Return:
3272  * returns 0 on success, otherwise errno.
3273  */
3274 int stmmac_dvr_probe(struct device *device,
3275                      struct plat_stmmacenet_data *plat_dat,
3276                      struct stmmac_resources *res)
3277 {
3278         int ret = 0;
3279         struct net_device *ndev = NULL;
3280         struct stmmac_priv *priv;
3281
3282         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3283         if (!ndev)
3284                 return -ENOMEM;
3285
3286         SET_NETDEV_DEV(ndev, device);
3287
3288         priv = netdev_priv(ndev);
3289         priv->device = device;
3290         priv->dev = ndev;
3291
3292         stmmac_set_ethtool_ops(ndev);
3293         priv->pause = pause;
3294         priv->plat = plat_dat;
3295         priv->ioaddr = res->addr;
3296         priv->dev->base_addr = (unsigned long)res->addr;
3297
3298         priv->dev->irq = res->irq;
3299         priv->wol_irq = res->wol_irq;
3300         priv->lpi_irq = res->lpi_irq;
3301
3302         if (res->mac)
3303                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3304
3305         dev_set_drvdata(device, priv->dev);
3306
3307         /* Verify driver arguments */
3308         stmmac_verify_args();
3309
3310         /* Override with kernel parameters if supplied XXX CRS XXX
3311          * this needs to have multiple instances
3312          */
3313         if ((phyaddr >= 0) && (phyaddr <= 31))
3314                 priv->plat->phy_addr = phyaddr;
3315
3316         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3317         if (IS_ERR(priv->stmmac_clk)) {
3318                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3319                          __func__);
3320                 /* If failed to obtain stmmac_clk and specific clk_csr value
3321                  * is NOT passed from the platform, probe fail.
3322                  */
3323                 if (!priv->plat->clk_csr) {
3324                         ret = PTR_ERR(priv->stmmac_clk);
3325                         goto error_clk_get;
3326                 } else {
3327                         priv->stmmac_clk = NULL;
3328                 }
3329         }
3330         clk_prepare_enable(priv->stmmac_clk);
3331
3332         priv->pclk = devm_clk_get(priv->device, "pclk");
3333         if (IS_ERR(priv->pclk)) {
3334                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3335                         ret = -EPROBE_DEFER;
3336                         goto error_pclk_get;
3337                 }
3338                 priv->pclk = NULL;
3339         }
3340         clk_prepare_enable(priv->pclk);
3341
3342         priv->stmmac_rst = devm_reset_control_get(priv->device,
3343                                                   STMMAC_RESOURCE_NAME);
3344         if (IS_ERR(priv->stmmac_rst)) {
3345                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3346                         ret = -EPROBE_DEFER;
3347                         goto error_hw_init;
3348                 }
3349                 dev_info(priv->device, "no reset control found\n");
3350                 priv->stmmac_rst = NULL;
3351         }
3352         if (priv->stmmac_rst)
3353                 reset_control_deassert(priv->stmmac_rst);
3354
3355         /* Init MAC and get the capabilities */
3356         ret = stmmac_hw_init(priv);
3357         if (ret)
3358                 goto error_hw_init;
3359
3360         stmmac_check_ether_addr(priv);
3361
3362         ndev->netdev_ops = &stmmac_netdev_ops;
3363
3364         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3365                             NETIF_F_RXCSUM;
3366
3367         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3368                 ndev->hw_features |= NETIF_F_TSO;
3369                 priv->tso = true;
3370                 pr_info(" TSO feature enabled\n");
3371         }
3372         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3373         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3374 #ifdef STMMAC_VLAN_TAG_USED
3375         /* Both mac100 and gmac support receive VLAN tag detection */
3376         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3377 #endif
3378         priv->msg_enable = netif_msg_init(debug, default_msg_level);
3379
3380         if (flow_ctrl)
3381                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3382
3383         /* Rx Watchdog is available in the COREs newer than the 3.40.
3384          * In some case, for example on bugged HW this feature
3385          * has to be disable and this can be done by passing the
3386          * riwt_off field from the platform.
3387          */
3388         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3389                 priv->use_riwt = 1;
3390                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3391         }
3392
3393         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3394
3395         spin_lock_init(&priv->lock);
3396         spin_lock_init(&priv->tx_lock);
3397
3398         /* If a specific clk_csr value is passed from the platform
3399          * this means that the CSR Clock Range selection cannot be
3400          * changed at run-time and it is fixed. Viceversa the driver'll try to
3401          * set the MDC clock dynamically according to the csr actual
3402          * clock input.
3403          */
3404         if (!priv->plat->clk_csr)
3405                 stmmac_clk_csr_set(priv);
3406         else
3407                 priv->clk_csr = priv->plat->clk_csr;
3408
3409         stmmac_check_pcs_mode(priv);
3410
3411         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
3412             priv->hw->pcs != STMMAC_PCS_TBI &&
3413             priv->hw->pcs != STMMAC_PCS_RTBI) {
3414                 /* MDIO bus Registration */
3415                 ret = stmmac_mdio_register(ndev);
3416                 if (ret < 0) {
3417                         pr_debug("%s: MDIO bus (id: %d) registration failed",
3418                                  __func__, priv->plat->bus_id);
3419                         goto error_napi_register;
3420                 }
3421         }
3422
3423         ret = register_netdev(ndev);
3424         if (ret) {
3425                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3426                 goto error_netdev_register;
3427         }
3428
3429         return ret;
3430
3431 error_netdev_register:
3432         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3433             priv->hw->pcs != STMMAC_PCS_TBI &&
3434             priv->hw->pcs != STMMAC_PCS_RTBI)
3435                 stmmac_mdio_unregister(ndev);
3436 error_napi_register:
3437         netif_napi_del(&priv->napi);
3438 error_hw_init:
3439         clk_disable_unprepare(priv->pclk);
3440 error_pclk_get:
3441         clk_disable_unprepare(priv->stmmac_clk);
3442 error_clk_get:
3443         free_netdev(ndev);
3444
3445         return ret;
3446 }
3447 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3448
3449 /**
3450  * stmmac_dvr_remove
3451  * @dev: device pointer
3452  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3453  * changes the link status, releases the DMA descriptor rings.
3454  */
3455 int stmmac_dvr_remove(struct device *dev)
3456 {
3457         struct net_device *ndev = dev_get_drvdata(dev);
3458         struct stmmac_priv *priv = netdev_priv(ndev);
3459
3460         pr_info("%s:\n\tremoving driver", __func__);
3461
3462         priv->hw->dma->stop_rx(priv->ioaddr);
3463         priv->hw->dma->stop_tx(priv->ioaddr);
3464
3465         stmmac_set_mac(priv->ioaddr, false);
3466         netif_carrier_off(ndev);
3467         unregister_netdev(ndev);
3468         if (priv->stmmac_rst)
3469                 reset_control_assert(priv->stmmac_rst);
3470         clk_disable_unprepare(priv->pclk);
3471         clk_disable_unprepare(priv->stmmac_clk);
3472         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3473             priv->hw->pcs != STMMAC_PCS_TBI &&
3474             priv->hw->pcs != STMMAC_PCS_RTBI)
3475                 stmmac_mdio_unregister(ndev);
3476         free_netdev(ndev);
3477
3478         return 0;
3479 }
3480 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3481
3482 /**
3483  * stmmac_suspend - suspend callback
3484  * @dev: device pointer
3485  * Description: this is the function to suspend the device and it is called
3486  * by the platform driver to stop the network queue, release the resources,
3487  * program the PMT register (for WoL), clean and release driver resources.
3488  */
3489 int stmmac_suspend(struct device *dev)
3490 {
3491         struct net_device *ndev = dev_get_drvdata(dev);
3492         struct stmmac_priv *priv = netdev_priv(ndev);
3493         unsigned long flags;
3494
3495         if (!ndev || !netif_running(ndev))
3496                 return 0;
3497
3498         if (priv->phydev)
3499                 phy_stop(priv->phydev);
3500
3501         spin_lock_irqsave(&priv->lock, flags);
3502
3503         netif_device_detach(ndev);
3504         netif_stop_queue(ndev);
3505
3506         napi_disable(&priv->napi);
3507
3508         if (priv->eee_enabled) {
3509                 priv->tx_path_in_lpi_mode = false;
3510                 del_timer_sync(&priv->eee_ctrl_timer);
3511         }
3512
3513         /* Stop TX/RX DMA */
3514         priv->hw->dma->stop_tx(priv->ioaddr);
3515         priv->hw->dma->stop_rx(priv->ioaddr);
3516
3517         /* Enable Power down mode by programming the PMT regs */
3518         if (device_may_wakeup(priv->device)) {
3519                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3520                 priv->irq_wake = 1;
3521         } else {
3522                 stmmac_set_mac(priv->ioaddr, false);
3523                 pinctrl_pm_select_sleep_state(priv->device);
3524                 /* Disable clock in case of PWM is off */
3525                 clk_disable(priv->pclk);
3526                 clk_disable(priv->stmmac_clk);
3527         }
3528         spin_unlock_irqrestore(&priv->lock, flags);
3529
3530         priv->oldlink = 0;
3531         priv->speed = 0;
3532         priv->oldduplex = -1;
3533         return 0;
3534 }
3535 EXPORT_SYMBOL_GPL(stmmac_suspend);
3536
3537 /**
3538  * stmmac_resume - resume callback
3539  * @dev: device pointer
3540  * Description: when resume this function is invoked to setup the DMA and CORE
3541  * in a usable state.
3542  */
3543 int stmmac_resume(struct device *dev)
3544 {
3545         struct net_device *ndev = dev_get_drvdata(dev);
3546         struct stmmac_priv *priv = netdev_priv(ndev);
3547         unsigned long flags;
3548
3549         if (!netif_running(ndev))
3550                 return 0;
3551
3552         /* Power Down bit, into the PM register, is cleared
3553          * automatically as soon as a magic packet or a Wake-up frame
3554          * is received. Anyway, it's better to manually clear
3555          * this bit because it can generate problems while resuming
3556          * from another devices (e.g. serial console).
3557          */
3558         if (device_may_wakeup(priv->device)) {
3559                 spin_lock_irqsave(&priv->lock, flags);
3560                 priv->hw->mac->pmt(priv->hw, 0);
3561                 spin_unlock_irqrestore(&priv->lock, flags);
3562                 priv->irq_wake = 0;
3563         } else {
3564                 pinctrl_pm_select_default_state(priv->device);
3565                 /* enable the clk prevously disabled */
3566                 clk_enable(priv->stmmac_clk);
3567                 clk_enable(priv->pclk);
3568                 /* reset the phy so that it's ready */
3569                 if (priv->mii)
3570                         stmmac_mdio_reset(priv->mii);
3571         }
3572
3573         netif_device_attach(ndev);
3574
3575         spin_lock_irqsave(&priv->lock, flags);
3576
3577         priv->cur_rx = 0;
3578         priv->dirty_rx = 0;
3579         priv->dirty_tx = 0;
3580         priv->cur_tx = 0;
3581         /* reset private mss value to force mss context settings at
3582          * next tso xmit (only used for gmac4).
3583          */
3584         priv->mss = 0;
3585
3586         stmmac_clear_descriptors(priv);
3587
3588         stmmac_hw_setup(ndev, false);
3589         stmmac_init_tx_coalesce(priv);
3590         stmmac_set_rx_mode(ndev);
3591
3592         napi_enable(&priv->napi);
3593
3594         netif_start_queue(ndev);
3595
3596         spin_unlock_irqrestore(&priv->lock, flags);
3597
3598         if (priv->phydev)
3599                 phy_start(priv->phydev);
3600
3601         return 0;
3602 }
3603 EXPORT_SYMBOL_GPL(stmmac_resume);
3604
3605 #ifndef MODULE
3606 static int __init stmmac_cmdline_opt(char *str)
3607 {
3608         char *opt;
3609
3610         if (!str || !*str)
3611                 return 1;
3612         while ((opt = strsep(&str, ",")) != NULL) {
3613                 if (!strncmp(opt, "debug:", 6)) {
3614                         if (kstrtoint(opt + 6, 0, &debug))
3615                                 goto err;
3616                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3617                         if (kstrtoint(opt + 8, 0, &phyaddr))
3618                                 goto err;
3619                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3620                         if (kstrtoint(opt + 7, 0, &buf_sz))
3621                                 goto err;
3622                 } else if (!strncmp(opt, "tc:", 3)) {
3623                         if (kstrtoint(opt + 3, 0, &tc))
3624                                 goto err;
3625                 } else if (!strncmp(opt, "watchdog:", 9)) {
3626                         if (kstrtoint(opt + 9, 0, &watchdog))
3627                                 goto err;
3628                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3629                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3630                                 goto err;
3631                 } else if (!strncmp(opt, "pause:", 6)) {
3632                         if (kstrtoint(opt + 6, 0, &pause))
3633                                 goto err;
3634                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3635                         if (kstrtoint(opt + 10, 0, &eee_timer))
3636                                 goto err;
3637                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3638                         if (kstrtoint(opt + 11, 0, &chain_mode))
3639                                 goto err;
3640                 }
3641         }
3642         return 1;
3643
3644 err:
3645         pr_err("%s: ERROR broken module parameter conversion", __func__);
3646         return 1;
3647 }
3648
3649 __setup("stmmaceth=", stmmac_cmdline_opt);
3650 #endif /* MODULE */
3651
3652 static int __init stmmac_init(void)
3653 {
3654 #ifdef CONFIG_DEBUG_FS
3655         /* Create debugfs main directory if it doesn't exist yet */
3656         if (!stmmac_fs_dir) {
3657                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3658
3659                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3660                         pr_err("ERROR %s, debugfs create directory failed\n",
3661                                STMMAC_RESOURCE_NAME);
3662
3663                         return -ENOMEM;
3664                 }
3665         }
3666 #endif
3667
3668         return 0;
3669 }
3670
3671 static void __exit stmmac_exit(void)
3672 {
3673 #ifdef CONFIG_DEBUG_FS
3674         debugfs_remove_recursive(stmmac_fs_dir);
3675 #endif
3676 }
3677
3678 module_init(stmmac_init)
3679 module_exit(stmmac_exit)
3680
3681 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3682 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3683 MODULE_LICENSE("GPL");