drivers/net/ethernet/sun/niu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* niu.c: Neptune ethernet driver.
   3  *
   4  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/pci.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/delay.h>
  19 #include <linux/bitops.h>
  20 #include <linux/mii.h>
  21 #include <linux/if.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/if_vlan.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/ipv6.h>
  27 #include <linux/log2.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/crc32.h>
  30 #include <linux/list.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/io.h>
  34 #include <linux/of_device.h>
  35
  36 #include "niu.h"
  37
  38 #define DRV_MODULE_NAME         "niu"
  39 #define DRV_MODULE_VERSION      "1.1"
  40 #define DRV_MODULE_RELDATE      "Apr 22, 2010"
  41
  42 static char version[] =
  43         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  44
  45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  46 MODULE_DESCRIPTION("NIU ethernet driver");
  47 MODULE_LICENSE("GPL");
  48 MODULE_VERSION(DRV_MODULE_VERSION);
  49
  50 #ifndef readq
  51 static u64 readq(void __iomem *reg)
  52 {
  53         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  54 }
  55
  56 static void writeq(u64 val, void __iomem *reg)
  57 {
  58         writel(val & 0xffffffff, reg);
  59         writel(val >> 32, reg + 0x4UL);
  60 }
  61 #endif
  62
  63 static const struct pci_device_id niu_pci_tbl[] = {
  64         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  65         {}
  66 };
  67
  68 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  69
  70 #define NIU_TX_TIMEOUT                  (5 * HZ)
  71
  72 #define nr64(reg)               readq(np->regs + (reg))
  73 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  74
  75 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  76 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  77
  78 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  79 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  80
  81 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  82 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  83
  84 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  85 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  86
  87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  88
  89 static int niu_debug;
  90 static int debug = -1;
  91 module_param(debug, int, 0);
  92 MODULE_PARM_DESC(debug, "NIU debug level");
  93
  94 #define niu_lock_parent(np, flags) \
  95         spin_lock_irqsave(&np->parent->lock, flags)
  96 #define niu_unlock_parent(np, flags) \
  97         spin_unlock_irqrestore(&np->parent->lock, flags)
  98
  99 static int serdes_init_10g_serdes(struct niu *np);
 100
 101 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 102                                      u64 bits, int limit, int delay)
 103 {
 104         while (--limit >= 0) {
 105                 u64 val = nr64_mac(reg);
 106
 107                 if (!(val & bits))
 108                         break;
 109                 udelay(delay);
 110         }
 111         if (limit < 0)
 112                 return -ENODEV;
 113         return 0;
 114 }
 115
 116 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 117                                         u64 bits, int limit, int delay,
 118                                         const char *reg_name)
 119 {
 120         int err;
 121
 122         nw64_mac(reg, bits);
 123         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 124         if (err)
 125                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 126                            (unsigned long long)bits, reg_name,
 127                            (unsigned long long)nr64_mac(reg));
 128         return err;
 129 }
 130
 131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 132 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 133         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 134 })
 135
 136 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 137                                      u64 bits, int limit, int delay)
 138 {
 139         while (--limit >= 0) {
 140                 u64 val = nr64_ipp(reg);
 141
 142                 if (!(val & bits))
 143                         break;
 144                 udelay(delay);
 145         }
 146         if (limit < 0)
 147                 return -ENODEV;
 148         return 0;
 149 }
 150
 151 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 152                                         u64 bits, int limit, int delay,
 153                                         const char *reg_name)
 154 {
 155         int err;
 156         u64 val;
 157
 158         val = nr64_ipp(reg);
 159         val |= bits;
 160         nw64_ipp(reg, val);
 161
 162         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 163         if (err)
 164                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 165                            (unsigned long long)bits, reg_name,
 166                            (unsigned long long)nr64_ipp(reg));
 167         return err;
 168 }
 169
 170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 171 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 172         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 173 })
 174
 175 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 176                                  u64 bits, int limit, int delay)
 177 {
 178         while (--limit >= 0) {
 179                 u64 val = nr64(reg);
 180
 181                 if (!(val & bits))
 182                         break;
 183                 udelay(delay);
 184         }
 185         if (limit < 0)
 186                 return -ENODEV;
 187         return 0;
 188 }
 189
 190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 191 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 192         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 193 })
 194
 195 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 196                                     u64 bits, int limit, int delay,
 197                                     const char *reg_name)
 198 {
 199         int err;
 200
 201         nw64(reg, bits);
 202         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 203         if (err)
 204                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 205                            (unsigned long long)bits, reg_name,
 206                            (unsigned long long)nr64(reg));
 207         return err;
 208 }
 209
 210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 211 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 212         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 213 })
 214
 215 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 216 {
 217         u64 val = (u64) lp->timer;
 218
 219         if (on)
 220                 val |= LDG_IMGMT_ARM;
 221
 222         nw64(LDG_IMGMT(lp->ldg_num), val);
 223 }
 224
 225 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 226 {
 227         unsigned long mask_reg, bits;
 228         u64 val;
 229
 230         if (ldn < 0 || ldn > LDN_MAX)
 231                 return -EINVAL;
 232
 233         if (ldn < 64) {
 234                 mask_reg = LD_IM0(ldn);
 235                 bits = LD_IM0_MASK;
 236         } else {
 237                 mask_reg = LD_IM1(ldn - 64);
 238                 bits = LD_IM1_MASK;
 239         }
 240
 241         val = nr64(mask_reg);
 242         if (on)
 243                 val &= ~bits;
 244         else
 245                 val |= bits;
 246         nw64(mask_reg, val);
 247
 248         return 0;
 249 }
 250
 251 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 252 {
 253         struct niu_parent *parent = np->parent;
 254         int i;
 255
 256         for (i = 0; i <= LDN_MAX; i++) {
 257                 int err;
 258
 259                 if (parent->ldg_map[i] != lp->ldg_num)
 260                         continue;
 261
 262                 err = niu_ldn_irq_enable(np, i, on);
 263                 if (err)
 264                         return err;
 265         }
 266         return 0;
 267 }
 268
 269 static int niu_enable_interrupts(struct niu *np, int on)
 270 {
 271         int i;
 272
 273         for (i = 0; i < np->num_ldg; i++) {
 274                 struct niu_ldg *lp = &np->ldg[i];
 275                 int err;
 276
 277                 err = niu_enable_ldn_in_ldg(np, lp, on);
 278                 if (err)
 279                         return err;
 280         }
 281         for (i = 0; i < np->num_ldg; i++)
 282                 niu_ldg_rearm(np, &np->ldg[i], on);
 283
 284         return 0;
 285 }
 286
 287 static u32 phy_encode(u32 type, int port)
 288 {
 289         return type << (port * 2);
 290 }
 291
 292 static u32 phy_decode(u32 val, int port)
 293 {
 294         return (val >> (port * 2)) & PORT_TYPE_MASK;
 295 }
 296
 297 static int mdio_wait(struct niu *np)
 298 {
 299         int limit = 1000;
 300         u64 val;
 301
 302         while (--limit > 0) {
 303                 val = nr64(MIF_FRAME_OUTPUT);
 304                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 305                         return val & MIF_FRAME_OUTPUT_DATA;
 306
 307                 udelay(10);
 308         }
 309
 310         return -ENODEV;
 311 }
 312
 313 static int mdio_read(struct niu *np, int port, int dev, int reg)
 314 {
 315         int err;
 316
 317         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 318         err = mdio_wait(np);
 319         if (err < 0)
 320                 return err;
 321
 322         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 323         return mdio_wait(np);
 324 }
 325
 326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 327 {
 328         int err;
 329
 330         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 331         err = mdio_wait(np);
 332         if (err < 0)
 333                 return err;
 334
 335         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 336         err = mdio_wait(np);
 337         if (err < 0)
 338                 return err;
 339
 340         return 0;
 341 }
 342
 343 static int mii_read(struct niu *np, int port, int reg)
 344 {
 345         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 346         return mdio_wait(np);
 347 }
 348
 349 static int mii_write(struct niu *np, int port, int reg, int data)
 350 {
 351         int err;
 352
 353         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 354         err = mdio_wait(np);
 355         if (err < 0)
 356                 return err;
 357
 358         return 0;
 359 }
 360
 361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 362 {
 363         int err;
 364
 365         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 366                          ESR2_TI_PLL_TX_CFG_L(channel),
 367                          val & 0xffff);
 368         if (!err)
 369                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 370                                  ESR2_TI_PLL_TX_CFG_H(channel),
 371                                  val >> 16);
 372         return err;
 373 }
 374
 375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 376 {
 377         int err;
 378
 379         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 380                          ESR2_TI_PLL_RX_CFG_L(channel),
 381                          val & 0xffff);
 382         if (!err)
 383                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 384                                  ESR2_TI_PLL_RX_CFG_H(channel),
 385                                  val >> 16);
 386         return err;
 387 }
 388
 389 /* Mode is always 10G fiber.  */
 390 static int serdes_init_niu_10g_fiber(struct niu *np)
 391 {
 392         struct niu_link_config *lp = &np->link_config;
 393         u32 tx_cfg, rx_cfg;
 394         unsigned long i;
 395
 396         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 397         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 398                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 399                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 400
 401         if (lp->loopback_mode == LOOPBACK_PHY) {
 402                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 403
 404                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 405                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 406
 407                 tx_cfg |= PLL_TX_CFG_ENTEST;
 408                 rx_cfg |= PLL_RX_CFG_ENTEST;
 409         }
 410
 411         /* Initialize all 4 lanes of the SERDES.  */
 412         for (i = 0; i < 4; i++) {
 413                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 414                 if (err)
 415                         return err;
 416         }
 417
 418         for (i = 0; i < 4; i++) {
 419                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 420                 if (err)
 421                         return err;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int serdes_init_niu_1g_serdes(struct niu *np)
 428 {
 429         struct niu_link_config *lp = &np->link_config;
 430         u16 pll_cfg, pll_sts;
 431         int max_retry = 100;
 432         u64 uninitialized_var(sig), mask, val;
 433         u32 tx_cfg, rx_cfg;
 434         unsigned long i;
 435         int err;
 436
 437         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 438                   PLL_TX_CFG_RATE_HALF);
 439         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 440                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 441                   PLL_RX_CFG_RATE_HALF);
 442
 443         if (np->port == 0)
 444                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 445
 446         if (lp->loopback_mode == LOOPBACK_PHY) {
 447                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 448
 449                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 450                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 451
 452                 tx_cfg |= PLL_TX_CFG_ENTEST;
 453                 rx_cfg |= PLL_RX_CFG_ENTEST;
 454         }
 455
 456         /* Initialize PLL for 1G */
 457         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 458
 459         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 460                          ESR2_TI_PLL_CFG_L, pll_cfg);
 461         if (err) {
 462                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 463                            np->port, __func__);
 464                 return err;
 465         }
 466
 467         pll_sts = PLL_CFG_ENPLL;
 468
 469         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 470                          ESR2_TI_PLL_STS_L, pll_sts);
 471         if (err) {
 472                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 473                            np->port, __func__);
 474                 return err;
 475         }
 476
 477         udelay(200);
 478
 479         /* Initialize all 4 lanes of the SERDES.  */
 480         for (i = 0; i < 4; i++) {
 481                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 482                 if (err)
 483                         return err;
 484         }
 485
 486         for (i = 0; i < 4; i++) {
 487                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 488                 if (err)
 489                         return err;
 490         }
 491
 492         switch (np->port) {
 493         case 0:
 494                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 495                 mask = val;
 496                 break;
 497
 498         case 1:
 499                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 500                 mask = val;
 501                 break;
 502
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         while (max_retry--) {
 508                 sig = nr64(ESR_INT_SIGNALS);
 509                 if ((sig & mask) == val)
 510                         break;
 511
 512                 mdelay(500);
 513         }
 514
 515         if ((sig & mask) != val) {
 516                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 517                            np->port, (int)(sig & mask), (int)val);
 518                 return -ENODEV;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int serdes_init_niu_10g_serdes(struct niu *np)
 525 {
 526         struct niu_link_config *lp = &np->link_config;
 527         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 528         int max_retry = 100;
 529         u64 uninitialized_var(sig), mask, val;
 530         unsigned long i;
 531         int err;
 532
 533         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 534         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 535                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 536                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 537
 538         if (lp->loopback_mode == LOOPBACK_PHY) {
 539                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 540
 541                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 542                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 543
 544                 tx_cfg |= PLL_TX_CFG_ENTEST;
 545                 rx_cfg |= PLL_RX_CFG_ENTEST;
 546         }
 547
 548         /* Initialize PLL for 10G */
 549         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 550
 551         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 552                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 553         if (err) {
 554                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 555                            np->port, __func__);
 556                 return err;
 557         }
 558
 559         pll_sts = PLL_CFG_ENPLL;
 560
 561         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 562                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 563         if (err) {
 564                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 565                            np->port, __func__);
 566                 return err;
 567         }
 568
 569         udelay(200);
 570
 571         /* Initialize all 4 lanes of the SERDES.  */
 572         for (i = 0; i < 4; i++) {
 573                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 574                 if (err)
 575                         return err;
 576         }
 577
 578         for (i = 0; i < 4; i++) {
 579                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 580                 if (err)
 581                         return err;
 582         }
 583
 584         /* check if serdes is ready */
 585
 586         switch (np->port) {
 587         case 0:
 588                 mask = ESR_INT_SIGNALS_P0_BITS;
 589                 val = (ESR_INT_SRDY0_P0 |
 590                        ESR_INT_DET0_P0 |
 591                        ESR_INT_XSRDY_P0 |
 592                        ESR_INT_XDP_P0_CH3 |
 593                        ESR_INT_XDP_P0_CH2 |
 594                        ESR_INT_XDP_P0_CH1 |
 595                        ESR_INT_XDP_P0_CH0);
 596                 break;
 597
 598         case 1:
 599                 mask = ESR_INT_SIGNALS_P1_BITS;
 600                 val = (ESR_INT_SRDY0_P1 |
 601                        ESR_INT_DET0_P1 |
 602                        ESR_INT_XSRDY_P1 |
 603                        ESR_INT_XDP_P1_CH3 |
 604                        ESR_INT_XDP_P1_CH2 |
 605                        ESR_INT_XDP_P1_CH1 |
 606                        ESR_INT_XDP_P1_CH0);
 607                 break;
 608
 609         default:
 610                 return -EINVAL;
 611         }
 612
 613         while (max_retry--) {
 614                 sig = nr64(ESR_INT_SIGNALS);
 615                 if ((sig & mask) == val)
 616                         break;
 617
 618                 mdelay(500);
 619         }
 620
 621         if ((sig & mask) != val) {
 622                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
 623                         np->port, (int)(sig & mask), (int)val);
 624
 625                 /* 10G failed, try initializing at 1G */
 626                 err = serdes_init_niu_1g_serdes(np);
 627                 if (!err) {
 628                         np->flags &= ~NIU_FLAGS_10G;
 629                         np->mac_xcvr = MAC_XCVR_PCS;
 630                 }  else {
 631                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
 632                                    np->port);
 633                         return -ENODEV;
 634                 }
 635         }
 636         return 0;
 637 }
 638
 639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 640 {
 641         int err;
 642
 643         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 644         if (err >= 0) {
 645                 *val = (err & 0xffff);
 646                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 647                                 ESR_RXTX_CTRL_H(chan));
 648                 if (err >= 0)
 649                         *val |= ((err & 0xffff) << 16);
 650                 err = 0;
 651         }
 652         return err;
 653 }
 654
 655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 656 {
 657         int err;
 658
 659         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 660                         ESR_GLUE_CTRL0_L(chan));
 661         if (err >= 0) {
 662                 *val = (err & 0xffff);
 663                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 664                                 ESR_GLUE_CTRL0_H(chan));
 665                 if (err >= 0) {
 666                         *val |= ((err & 0xffff) << 16);
 667                         err = 0;
 668                 }
 669         }
 670         return err;
 671 }
 672
 673 static int esr_read_reset(struct niu *np, u32 *val)
 674 {
 675         int err;
 676
 677         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 678                         ESR_RXTX_RESET_CTRL_L);
 679         if (err >= 0) {
 680                 *val = (err & 0xffff);
 681                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 682                                 ESR_RXTX_RESET_CTRL_H);
 683                 if (err >= 0) {
 684                         *val |= ((err & 0xffff) << 16);
 685                         err = 0;
 686                 }
 687         }
 688         return err;
 689 }
 690
 691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 692 {
 693         int err;
 694
 695         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 696                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 697         if (!err)
 698                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 699                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 700         return err;
 701 }
 702
 703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 704 {
 705         int err;
 706
 707         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 708                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 709         if (!err)
 710                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 711                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 712         return err;
 713 }
 714
 715 static int esr_reset(struct niu *np)
 716 {
 717         u32 uninitialized_var(reset);
 718         int err;
 719
 720         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 721                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 722         if (err)
 723                 return err;
 724         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 725                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 726         if (err)
 727                 return err;
 728         udelay(200);
 729
 730         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 731                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 732         if (err)
 733                 return err;
 734         udelay(200);
 735
 736         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 737                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 738         if (err)
 739                 return err;
 740         udelay(200);
 741
 742         err = esr_read_reset(np, &reset);
 743         if (err)
 744                 return err;
 745         if (reset != 0) {
 746                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
 747                            np->port, reset);
 748                 return -ENODEV;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int serdes_init_10g(struct niu *np)
 755 {
 756         struct niu_link_config *lp = &np->link_config;
 757         unsigned long ctrl_reg, test_cfg_reg, i;
 758         u64 ctrl_val, test_cfg_val, sig, mask, val;
 759         int err;
 760
 761         switch (np->port) {
 762         case 0:
 763                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 764                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 765                 break;
 766         case 1:
 767                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 768                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 769                 break;
 770
 771         default:
 772                 return -EINVAL;
 773         }
 774         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 775                     ENET_SERDES_CTRL_SDET_1 |
 776                     ENET_SERDES_CTRL_SDET_2 |
 777                     ENET_SERDES_CTRL_SDET_3 |
 778                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 779                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 780                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 781                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 782                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 783                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 784                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 785                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 786         test_cfg_val = 0;
 787
 788         if (lp->loopback_mode == LOOPBACK_PHY) {
 789                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 790                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 791                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 792                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 793                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 794                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 795                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 796                                   ENET_SERDES_TEST_MD_3_SHIFT));
 797         }
 798
 799         nw64(ctrl_reg, ctrl_val);
 800         nw64(test_cfg_reg, test_cfg_val);
 801
 802         /* Initialize all 4 lanes of the SERDES.  */
 803         for (i = 0; i < 4; i++) {
 804                 u32 rxtx_ctrl, glue0;
 805
 806                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 807                 if (err)
 808                         return err;
 809                 err = esr_read_glue0(np, i, &glue0);
 810                 if (err)
 811                         return err;
 812
 813                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 814                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 815                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 816
 817                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 818                            ESR_GLUE_CTRL0_THCNT |
 819                            ESR_GLUE_CTRL0_BLTIME);
 820                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 821                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 822                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 823                           (BLTIME_300_CYCLES <<
 824                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 825
 826                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 827                 if (err)
 828                         return err;
 829                 err = esr_write_glue0(np, i, glue0);
 830                 if (err)
 831                         return err;
 832         }
 833
 834         err = esr_reset(np);
 835         if (err)
 836                 return err;
 837
 838         sig = nr64(ESR_INT_SIGNALS);
 839         switch (np->port) {
 840         case 0:
 841                 mask = ESR_INT_SIGNALS_P0_BITS;
 842                 val = (ESR_INT_SRDY0_P0 |
 843                        ESR_INT_DET0_P0 |
 844                        ESR_INT_XSRDY_P0 |
 845                        ESR_INT_XDP_P0_CH3 |
 846                        ESR_INT_XDP_P0_CH2 |
 847                        ESR_INT_XDP_P0_CH1 |
 848                        ESR_INT_XDP_P0_CH0);
 849                 break;
 850
 851         case 1:
 852                 mask = ESR_INT_SIGNALS_P1_BITS;
 853                 val = (ESR_INT_SRDY0_P1 |
 854                        ESR_INT_DET0_P1 |
 855                        ESR_INT_XSRDY_P1 |
 856                        ESR_INT_XDP_P1_CH3 |
 857                        ESR_INT_XDP_P1_CH2 |
 858                        ESR_INT_XDP_P1_CH1 |
 859                        ESR_INT_XDP_P1_CH0);
 860                 break;
 861
 862         default:
 863                 return -EINVAL;
 864         }
 865
 866         if ((sig & mask) != val) {
 867                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 868                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 869                         return 0;
 870                 }
 871                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 872                            np->port, (int)(sig & mask), (int)val);
 873                 return -ENODEV;
 874         }
 875         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 876                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 877         return 0;
 878 }
 879
 880 static int serdes_init_1g(struct niu *np)
 881 {
 882         u64 val;
 883
 884         val = nr64(ENET_SERDES_1_PLL_CFG);
 885         val &= ~ENET_SERDES_PLL_FBDIV2;
 886         switch (np->port) {
 887         case 0:
 888                 val |= ENET_SERDES_PLL_HRATE0;
 889                 break;
 890         case 1:
 891                 val |= ENET_SERDES_PLL_HRATE1;
 892                 break;
 893         case 2:
 894                 val |= ENET_SERDES_PLL_HRATE2;
 895                 break;
 896         case 3:
 897                 val |= ENET_SERDES_PLL_HRATE3;
 898                 break;
 899         default:
 900                 return -EINVAL;
 901         }
 902         nw64(ENET_SERDES_1_PLL_CFG, val);
 903
 904         return 0;
 905 }
 906
 907 static int serdes_init_1g_serdes(struct niu *np)
 908 {
 909         struct niu_link_config *lp = &np->link_config;
 910         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 911         u64 ctrl_val, test_cfg_val, sig, mask, val;
 912         int err;
 913         u64 reset_val, val_rd;
 914
 915         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 916                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 917                 ENET_SERDES_PLL_FBDIV0;
 918         switch (np->port) {
 919         case 0:
 920                 reset_val =  ENET_SERDES_RESET_0;
 921                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 922                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 923                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 924                 break;
 925         case 1:
 926                 reset_val =  ENET_SERDES_RESET_1;
 927                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 928                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 929                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 930                 break;
 931
 932         default:
 933                 return -EINVAL;
 934         }
 935         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 936                     ENET_SERDES_CTRL_SDET_1 |
 937                     ENET_SERDES_CTRL_SDET_2 |
 938                     ENET_SERDES_CTRL_SDET_3 |
 939                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 940                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 941                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 942                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 943                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 944                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 945                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 946                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 947         test_cfg_val = 0;
 948
 949         if (lp->loopback_mode == LOOPBACK_PHY) {
 950                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 951                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 952                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 953                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 954                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 955                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 956                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 957                                   ENET_SERDES_TEST_MD_3_SHIFT));
 958         }
 959
 960         nw64(ENET_SERDES_RESET, reset_val);
 961         mdelay(20);
 962         val_rd = nr64(ENET_SERDES_RESET);
 963         val_rd &= ~reset_val;
 964         nw64(pll_cfg, val);
 965         nw64(ctrl_reg, ctrl_val);
 966         nw64(test_cfg_reg, test_cfg_val);
 967         nw64(ENET_SERDES_RESET, val_rd);
 968         mdelay(2000);
 969
 970         /* Initialize all 4 lanes of the SERDES.  */
 971         for (i = 0; i < 4; i++) {
 972                 u32 rxtx_ctrl, glue0;
 973
 974                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 975                 if (err)
 976                         return err;
 977                 err = esr_read_glue0(np, i, &glue0);
 978                 if (err)
 979                         return err;
 980
 981                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 982                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 983                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 984
 985                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 986                            ESR_GLUE_CTRL0_THCNT |
 987                            ESR_GLUE_CTRL0_BLTIME);
 988                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 989                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 990                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 991                           (BLTIME_300_CYCLES <<
 992                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 993
 994                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 995                 if (err)
 996                         return err;
 997                 err = esr_write_glue0(np, i, glue0);
 998                 if (err)
 999                         return err;
1000         }
1001
1002
1003         sig = nr64(ESR_INT_SIGNALS);
1004         switch (np->port) {
1005         case 0:
1006                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007                 mask = val;
1008                 break;
1009
1010         case 1:
1011                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012                 mask = val;
1013                 break;
1014
1015         default:
1016                 return -EINVAL;
1017         }
1018
1019         if ((sig & mask) != val) {
1020                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021                            np->port, (int)(sig & mask), (int)val);
1022                 return -ENODEV;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 {
1030         struct niu_link_config *lp = &np->link_config;
1031         int link_up;
1032         u64 val;
1033         u16 current_speed;
1034         unsigned long flags;
1035         u8 current_duplex;
1036
1037         link_up = 0;
1038         current_speed = SPEED_INVALID;
1039         current_duplex = DUPLEX_INVALID;
1040
1041         spin_lock_irqsave(&np->lock, flags);
1042
1043         val = nr64_pcs(PCS_MII_STAT);
1044
1045         if (val & PCS_MII_STAT_LINK_STATUS) {
1046                 link_up = 1;
1047                 current_speed = SPEED_1000;
1048                 current_duplex = DUPLEX_FULL;
1049         }
1050
1051         lp->active_speed = current_speed;
1052         lp->active_duplex = current_duplex;
1053         spin_unlock_irqrestore(&np->lock, flags);
1054
1055         *link_up_p = link_up;
1056         return 0;
1057 }
1058
1059 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 {
1061         unsigned long flags;
1062         struct niu_link_config *lp = &np->link_config;
1063         int link_up = 0;
1064         int link_ok = 1;
1065         u64 val, val2;
1066         u16 current_speed;
1067         u8 current_duplex;
1068
1069         if (!(np->flags & NIU_FLAGS_10G))
1070                 return link_status_1g_serdes(np, link_up_p);
1071
1072         current_speed = SPEED_INVALID;
1073         current_duplex = DUPLEX_INVALID;
1074         spin_lock_irqsave(&np->lock, flags);
1075
1076         val = nr64_xpcs(XPCS_STATUS(0));
1077         val2 = nr64_mac(XMAC_INTER2);
1078         if (val2 & 0x01000000)
1079                 link_ok = 0;
1080
1081         if ((val & 0x1000ULL) && link_ok) {
1082                 link_up = 1;
1083                 current_speed = SPEED_10000;
1084                 current_duplex = DUPLEX_FULL;
1085         }
1086         lp->active_speed = current_speed;
1087         lp->active_duplex = current_duplex;
1088         spin_unlock_irqrestore(&np->lock, flags);
1089         *link_up_p = link_up;
1090         return 0;
1091 }
1092
1093 static int link_status_mii(struct niu *np, int *link_up_p)
1094 {
1095         struct niu_link_config *lp = &np->link_config;
1096         int err;
1097         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098         int supported, advertising, active_speed, active_duplex;
1099
1100         err = mii_read(np, np->phy_addr, MII_BMCR);
1101         if (unlikely(err < 0))
1102                 return err;
1103         bmcr = err;
1104
1105         err = mii_read(np, np->phy_addr, MII_BMSR);
1106         if (unlikely(err < 0))
1107                 return err;
1108         bmsr = err;
1109
1110         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111         if (unlikely(err < 0))
1112                 return err;
1113         advert = err;
1114
1115         err = mii_read(np, np->phy_addr, MII_LPA);
1116         if (unlikely(err < 0))
1117                 return err;
1118         lpa = err;
1119
1120         if (likely(bmsr & BMSR_ESTATEN)) {
1121                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122                 if (unlikely(err < 0))
1123                         return err;
1124                 estatus = err;
1125
1126                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127                 if (unlikely(err < 0))
1128                         return err;
1129                 ctrl1000 = err;
1130
1131                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132                 if (unlikely(err < 0))
1133                         return err;
1134                 stat1000 = err;
1135         } else
1136                 estatus = ctrl1000 = stat1000 = 0;
1137
1138         supported = 0;
1139         if (bmsr & BMSR_ANEGCAPABLE)
1140                 supported |= SUPPORTED_Autoneg;
1141         if (bmsr & BMSR_10HALF)
1142                 supported |= SUPPORTED_10baseT_Half;
1143         if (bmsr & BMSR_10FULL)
1144                 supported |= SUPPORTED_10baseT_Full;
1145         if (bmsr & BMSR_100HALF)
1146                 supported |= SUPPORTED_100baseT_Half;
1147         if (bmsr & BMSR_100FULL)
1148                 supported |= SUPPORTED_100baseT_Full;
1149         if (estatus & ESTATUS_1000_THALF)
1150                 supported |= SUPPORTED_1000baseT_Half;
1151         if (estatus & ESTATUS_1000_TFULL)
1152                 supported |= SUPPORTED_1000baseT_Full;
1153         lp->supported = supported;
1154
1155         advertising = mii_adv_to_ethtool_adv_t(advert);
1156         advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1157
1158         if (bmcr & BMCR_ANENABLE) {
1159                 int neg, neg1000;
1160
1161                 lp->active_autoneg = 1;
1162                 advertising |= ADVERTISED_Autoneg;
1163
1164                 neg = advert & lpa;
1165                 neg1000 = (ctrl1000 << 2) & stat1000;
1166
1167                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1168                         active_speed = SPEED_1000;
1169                 else if (neg & LPA_100)
1170                         active_speed = SPEED_100;
1171                 else if (neg & (LPA_10HALF | LPA_10FULL))
1172                         active_speed = SPEED_10;
1173                 else
1174                         active_speed = SPEED_INVALID;
1175
1176                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1177                         active_duplex = DUPLEX_FULL;
1178                 else if (active_speed != SPEED_INVALID)
1179                         active_duplex = DUPLEX_HALF;
1180                 else
1181                         active_duplex = DUPLEX_INVALID;
1182         } else {
1183                 lp->active_autoneg = 0;
1184
1185                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1186                         active_speed = SPEED_1000;
1187                 else if (bmcr & BMCR_SPEED100)
1188                         active_speed = SPEED_100;
1189                 else
1190                         active_speed = SPEED_10;
1191
1192                 if (bmcr & BMCR_FULLDPLX)
1193                         active_duplex = DUPLEX_FULL;
1194                 else
1195                         active_duplex = DUPLEX_HALF;
1196         }
1197
1198         lp->active_advertising = advertising;
1199         lp->active_speed = active_speed;
1200         lp->active_duplex = active_duplex;
1201         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1202
1203         return 0;
1204 }
1205
1206 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1207 {
1208         struct niu_link_config *lp = &np->link_config;
1209         u16 current_speed, bmsr;
1210         unsigned long flags;
1211         u8 current_duplex;
1212         int err, link_up;
1213
1214         link_up = 0;
1215         current_speed = SPEED_INVALID;
1216         current_duplex = DUPLEX_INVALID;
1217
1218         spin_lock_irqsave(&np->lock, flags);
1219
1220         err = -EINVAL;
1221
1222         err = mii_read(np, np->phy_addr, MII_BMSR);
1223         if (err < 0)
1224                 goto out;
1225
1226         bmsr = err;
1227         if (bmsr & BMSR_LSTATUS) {
1228                 link_up = 1;
1229                 current_speed = SPEED_1000;
1230                 current_duplex = DUPLEX_FULL;
1231         }
1232         lp->active_speed = current_speed;
1233         lp->active_duplex = current_duplex;
1234         err = 0;
1235
1236 out:
1237         spin_unlock_irqrestore(&np->lock, flags);
1238
1239         *link_up_p = link_up;
1240         return err;
1241 }
1242
1243 static int link_status_1g(struct niu *np, int *link_up_p)
1244 {
1245         struct niu_link_config *lp = &np->link_config;
1246         unsigned long flags;
1247         int err;
1248
1249         spin_lock_irqsave(&np->lock, flags);
1250
1251         err = link_status_mii(np, link_up_p);
1252         lp->supported |= SUPPORTED_TP;
1253         lp->active_advertising |= ADVERTISED_TP;
1254
1255         spin_unlock_irqrestore(&np->lock, flags);
1256         return err;
1257 }
1258
1259 static int bcm8704_reset(struct niu *np)
1260 {
1261         int err, limit;
1262
1263         err = mdio_read(np, np->phy_addr,
1264                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1265         if (err < 0 || err == 0xffff)
1266                 return err;
1267         err |= BMCR_RESET;
1268         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1269                          MII_BMCR, err);
1270         if (err)
1271                 return err;
1272
1273         limit = 1000;
1274         while (--limit >= 0) {
1275                 err = mdio_read(np, np->phy_addr,
1276                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1277                 if (err < 0)
1278                         return err;
1279                 if (!(err & BMCR_RESET))
1280                         break;
1281         }
1282         if (limit < 0) {
1283                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1284                            np->port, (err & 0xffff));
1285                 return -ENODEV;
1286         }
1287         return 0;
1288 }
1289
1290 /* When written, certain PHY registers need to be read back twice
1291  * in order for the bits to settle properly.
1292  */
1293 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1294 {
1295         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1296         if (err < 0)
1297                 return err;
1298         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1299         if (err < 0)
1300                 return err;
1301         return 0;
1302 }
1303
1304 static int bcm8706_init_user_dev3(struct niu *np)
1305 {
1306         int err;
1307
1308
1309         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1310                         BCM8704_USER_OPT_DIGITAL_CTRL);
1311         if (err < 0)
1312                 return err;
1313         err &= ~USER_ODIG_CTRL_GPIOS;
1314         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1315         err |=  USER_ODIG_CTRL_RESV2;
1316         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1317                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1318         if (err)
1319                 return err;
1320
1321         mdelay(1000);
1322
1323         return 0;
1324 }
1325
1326 static int bcm8704_init_user_dev3(struct niu *np)
1327 {
1328         int err;
1329
1330         err = mdio_write(np, np->phy_addr,
1331                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1332                          (USER_CONTROL_OPTXRST_LVL |
1333                           USER_CONTROL_OPBIASFLT_LVL |
1334                           USER_CONTROL_OBTMPFLT_LVL |
1335                           USER_CONTROL_OPPRFLT_LVL |
1336                           USER_CONTROL_OPTXFLT_LVL |
1337                           USER_CONTROL_OPRXLOS_LVL |
1338                           USER_CONTROL_OPRXFLT_LVL |
1339                           USER_CONTROL_OPTXON_LVL |
1340                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1341         if (err)
1342                 return err;
1343
1344         err = mdio_write(np, np->phy_addr,
1345                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1346                          (USER_PMD_TX_CTL_XFP_CLKEN |
1347                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1348                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1349                           USER_PMD_TX_CTL_TSCK_LPWREN));
1350         if (err)
1351                 return err;
1352
1353         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1354         if (err)
1355                 return err;
1356         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1357         if (err)
1358                 return err;
1359
1360         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1361                         BCM8704_USER_OPT_DIGITAL_CTRL);
1362         if (err < 0)
1363                 return err;
1364         err &= ~USER_ODIG_CTRL_GPIOS;
1365         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1366         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1367                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1368         if (err)
1369                 return err;
1370
1371         mdelay(1000);
1372
1373         return 0;
1374 }
1375
1376 static int mrvl88x2011_act_led(struct niu *np, int val)
1377 {
1378         int     err;
1379
1380         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1381                 MRVL88X2011_LED_8_TO_11_CTL);
1382         if (err < 0)
1383                 return err;
1384
1385         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1386         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1387
1388         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1389                           MRVL88X2011_LED_8_TO_11_CTL, err);
1390 }
1391
1392 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1393 {
1394         int     err;
1395
1396         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1397                         MRVL88X2011_LED_BLINK_CTL);
1398         if (err >= 0) {
1399                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1400                 err |= (rate << 4);
1401
1402                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1403                                  MRVL88X2011_LED_BLINK_CTL, err);
1404         }
1405
1406         return err;
1407 }
1408
1409 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1410 {
1411         int     err;
1412
1413         /* Set LED functions */
1414         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1415         if (err)
1416                 return err;
1417
1418         /* led activity */
1419         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1420         if (err)
1421                 return err;
1422
1423         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1424                         MRVL88X2011_GENERAL_CTL);
1425         if (err < 0)
1426                 return err;
1427
1428         err |= MRVL88X2011_ENA_XFPREFCLK;
1429
1430         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1431                          MRVL88X2011_GENERAL_CTL, err);
1432         if (err < 0)
1433                 return err;
1434
1435         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1436                         MRVL88X2011_PMA_PMD_CTL_1);
1437         if (err < 0)
1438                 return err;
1439
1440         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1441                 err |= MRVL88X2011_LOOPBACK;
1442         else
1443                 err &= ~MRVL88X2011_LOOPBACK;
1444
1445         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1446                          MRVL88X2011_PMA_PMD_CTL_1, err);
1447         if (err < 0)
1448                 return err;
1449
1450         /* Enable PMD  */
1451         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1452                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1453 }
1454
1455
1456 static int xcvr_diag_bcm870x(struct niu *np)
1457 {
1458         u16 analog_stat0, tx_alarm_status;
1459         int err = 0;
1460
1461 #if 1
1462         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1463                         MII_STAT1000);
1464         if (err < 0)
1465                 return err;
1466         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1467
1468         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1469         if (err < 0)
1470                 return err;
1471         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1472
1473         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1474                         MII_NWAYTEST);
1475         if (err < 0)
1476                 return err;
1477         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1478 #endif
1479
1480         /* XXX dig this out it might not be so useful XXX */
1481         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1482                         BCM8704_USER_ANALOG_STATUS0);
1483         if (err < 0)
1484                 return err;
1485         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1486                         BCM8704_USER_ANALOG_STATUS0);
1487         if (err < 0)
1488                 return err;
1489         analog_stat0 = err;
1490
1491         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1492                         BCM8704_USER_TX_ALARM_STATUS);
1493         if (err < 0)
1494                 return err;
1495         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1496                         BCM8704_USER_TX_ALARM_STATUS);
1497         if (err < 0)
1498                 return err;
1499         tx_alarm_status = err;
1500
1501         if (analog_stat0 != 0x03fc) {
1502                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1503                         pr_info("Port %u cable not connected or bad cable\n",
1504                                 np->port);
1505                 } else if (analog_stat0 == 0x639c) {
1506                         pr_info("Port %u optical module is bad or missing\n",
1507                                 np->port);
1508                 }
1509         }
1510
1511         return 0;
1512 }
1513
1514 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1515 {
1516         struct niu_link_config *lp = &np->link_config;
1517         int err;
1518
1519         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1520                         MII_BMCR);
1521         if (err < 0)
1522                 return err;
1523
1524         err &= ~BMCR_LOOPBACK;
1525
1526         if (lp->loopback_mode == LOOPBACK_MAC)
1527                 err |= BMCR_LOOPBACK;
1528
1529         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1530                          MII_BMCR, err);
1531         if (err)
1532                 return err;
1533
1534         return 0;
1535 }
1536
1537 static int xcvr_init_10g_bcm8706(struct niu *np)
1538 {
1539         int err = 0;
1540         u64 val;
1541
1542         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1543             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1544                         return err;
1545
1546         val = nr64_mac(XMAC_CONFIG);
1547         val &= ~XMAC_CONFIG_LED_POLARITY;
1548         val |= XMAC_CONFIG_FORCE_LED_ON;
1549         nw64_mac(XMAC_CONFIG, val);
1550
1551         val = nr64(MIF_CONFIG);
1552         val |= MIF_CONFIG_INDIRECT_MODE;
1553         nw64(MIF_CONFIG, val);
1554
1555         err = bcm8704_reset(np);
1556         if (err)
1557                 return err;
1558
1559         err = xcvr_10g_set_lb_bcm870x(np);
1560         if (err)
1561                 return err;
1562
1563         err = bcm8706_init_user_dev3(np);
1564         if (err)
1565                 return err;
1566
1567         err = xcvr_diag_bcm870x(np);
1568         if (err)
1569                 return err;
1570
1571         return 0;
1572 }
1573
1574 static int xcvr_init_10g_bcm8704(struct niu *np)
1575 {
1576         int err;
1577
1578         err = bcm8704_reset(np);
1579         if (err)
1580                 return err;
1581
1582         err = bcm8704_init_user_dev3(np);
1583         if (err)
1584                 return err;
1585
1586         err = xcvr_10g_set_lb_bcm870x(np);
1587         if (err)
1588                 return err;
1589
1590         err =  xcvr_diag_bcm870x(np);
1591         if (err)
1592                 return err;
1593
1594         return 0;
1595 }
1596
1597 static int xcvr_init_10g(struct niu *np)
1598 {
1599         int phy_id, err;
1600         u64 val;
1601
1602         val = nr64_mac(XMAC_CONFIG);
1603         val &= ~XMAC_CONFIG_LED_POLARITY;
1604         val |= XMAC_CONFIG_FORCE_LED_ON;
1605         nw64_mac(XMAC_CONFIG, val);
1606
1607         /* XXX shared resource, lock parent XXX */
1608         val = nr64(MIF_CONFIG);
1609         val |= MIF_CONFIG_INDIRECT_MODE;
1610         nw64(MIF_CONFIG, val);
1611
1612         phy_id = phy_decode(np->parent->port_phy, np->port);
1613         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1614
1615         /* handle different phy types */
1616         switch (phy_id & NIU_PHY_ID_MASK) {
1617         case NIU_PHY_ID_MRVL88X2011:
1618                 err = xcvr_init_10g_mrvl88x2011(np);
1619                 break;
1620
1621         default: /* bcom 8704 */
1622                 err = xcvr_init_10g_bcm8704(np);
1623                 break;
1624         }
1625
1626         return err;
1627 }
1628
1629 static int mii_reset(struct niu *np)
1630 {
1631         int limit, err;
1632
1633         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1634         if (err)
1635                 return err;
1636
1637         limit = 1000;
1638         while (--limit >= 0) {
1639                 udelay(500);
1640                 err = mii_read(np, np->phy_addr, MII_BMCR);
1641                 if (err < 0)
1642                         return err;
1643                 if (!(err & BMCR_RESET))
1644                         break;
1645         }
1646         if (limit < 0) {
1647                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1648                            np->port, err);
1649                 return -ENODEV;
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int xcvr_init_1g_rgmii(struct niu *np)
1656 {
1657         int err;
1658         u64 val;
1659         u16 bmcr, bmsr, estat;
1660
1661         val = nr64(MIF_CONFIG);
1662         val &= ~MIF_CONFIG_INDIRECT_MODE;
1663         nw64(MIF_CONFIG, val);
1664
1665         err = mii_reset(np);
1666         if (err)
1667                 return err;
1668
1669         err = mii_read(np, np->phy_addr, MII_BMSR);
1670         if (err < 0)
1671                 return err;
1672         bmsr = err;
1673
1674         estat = 0;
1675         if (bmsr & BMSR_ESTATEN) {
1676                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1677                 if (err < 0)
1678                         return err;
1679                 estat = err;
1680         }
1681
1682         bmcr = 0;
1683         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1684         if (err)
1685                 return err;
1686
1687         if (bmsr & BMSR_ESTATEN) {
1688                 u16 ctrl1000 = 0;
1689
1690                 if (estat & ESTATUS_1000_TFULL)
1691                         ctrl1000 |= ADVERTISE_1000FULL;
1692                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1693                 if (err)
1694                         return err;
1695         }
1696
1697         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1698
1699         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1700         if (err)
1701                 return err;
1702
1703         err = mii_read(np, np->phy_addr, MII_BMCR);
1704         if (err < 0)
1705                 return err;
1706         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1707
1708         err = mii_read(np, np->phy_addr, MII_BMSR);
1709         if (err < 0)
1710                 return err;
1711
1712         return 0;
1713 }
1714
1715 static int mii_init_common(struct niu *np)
1716 {
1717         struct niu_link_config *lp = &np->link_config;
1718         u16 bmcr, bmsr, adv, estat;
1719         int err;
1720
1721         err = mii_reset(np);
1722         if (err)
1723                 return err;
1724
1725         err = mii_read(np, np->phy_addr, MII_BMSR);
1726         if (err < 0)
1727                 return err;
1728         bmsr = err;
1729
1730         estat = 0;
1731         if (bmsr & BMSR_ESTATEN) {
1732                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1733                 if (err < 0)
1734                         return err;
1735                 estat = err;
1736         }
1737
1738         bmcr = 0;
1739         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1740         if (err)
1741                 return err;
1742
1743         if (lp->loopback_mode == LOOPBACK_MAC) {
1744                 bmcr |= BMCR_LOOPBACK;
1745                 if (lp->active_speed == SPEED_1000)
1746                         bmcr |= BMCR_SPEED1000;
1747                 if (lp->active_duplex == DUPLEX_FULL)
1748                         bmcr |= BMCR_FULLDPLX;
1749         }
1750
1751         if (lp->loopback_mode == LOOPBACK_PHY) {
1752                 u16 aux;
1753
1754                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1755                        BCM5464R_AUX_CTL_WRITE_1);
1756                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1757                 if (err)
1758                         return err;
1759         }
1760
1761         if (lp->autoneg) {
1762                 u16 ctrl1000;
1763
1764                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1765                 if ((bmsr & BMSR_10HALF) &&
1766                         (lp->advertising & ADVERTISED_10baseT_Half))
1767                         adv |= ADVERTISE_10HALF;
1768                 if ((bmsr & BMSR_10FULL) &&
1769                         (lp->advertising & ADVERTISED_10baseT_Full))
1770                         adv |= ADVERTISE_10FULL;
1771                 if ((bmsr & BMSR_100HALF) &&
1772                         (lp->advertising & ADVERTISED_100baseT_Half))
1773                         adv |= ADVERTISE_100HALF;
1774                 if ((bmsr & BMSR_100FULL) &&
1775                         (lp->advertising & ADVERTISED_100baseT_Full))
1776                         adv |= ADVERTISE_100FULL;
1777                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1778                 if (err)
1779                         return err;
1780
1781                 if (likely(bmsr & BMSR_ESTATEN)) {
1782                         ctrl1000 = 0;
1783                         if ((estat & ESTATUS_1000_THALF) &&
1784                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1785                                 ctrl1000 |= ADVERTISE_1000HALF;
1786                         if ((estat & ESTATUS_1000_TFULL) &&
1787                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1788                                 ctrl1000 |= ADVERTISE_1000FULL;
1789                         err = mii_write(np, np->phy_addr,
1790                                         MII_CTRL1000, ctrl1000);
1791                         if (err)
1792                                 return err;
1793                 }
1794
1795                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1796         } else {
1797                 /* !lp->autoneg */
1798                 int fulldpx;
1799
1800                 if (lp->duplex == DUPLEX_FULL) {
1801                         bmcr |= BMCR_FULLDPLX;
1802                         fulldpx = 1;
1803                 } else if (lp->duplex == DUPLEX_HALF)
1804                         fulldpx = 0;
1805                 else
1806                         return -EINVAL;
1807
1808                 if (lp->speed == SPEED_1000) {
1809                         /* if X-full requested while not supported, or
1810                            X-half requested while not supported... */
1811                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1812                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1813                                 return -EINVAL;
1814                         bmcr |= BMCR_SPEED1000;
1815                 } else if (lp->speed == SPEED_100) {
1816                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1817                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1818                                 return -EINVAL;
1819                         bmcr |= BMCR_SPEED100;
1820                 } else if (lp->speed == SPEED_10) {
1821                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1822                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1823                                 return -EINVAL;
1824                 } else
1825                         return -EINVAL;
1826         }
1827
1828         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1829         if (err)
1830                 return err;
1831
1832 #if 0
1833         err = mii_read(np, np->phy_addr, MII_BMCR);
1834         if (err < 0)
1835                 return err;
1836         bmcr = err;
1837
1838         err = mii_read(np, np->phy_addr, MII_BMSR);
1839         if (err < 0)
1840                 return err;
1841         bmsr = err;
1842
1843         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1844                 np->port, bmcr, bmsr);
1845 #endif
1846
1847         return 0;
1848 }
1849
1850 static int xcvr_init_1g(struct niu *np)
1851 {
1852         u64 val;
1853
1854         /* XXX shared resource, lock parent XXX */
1855         val = nr64(MIF_CONFIG);
1856         val &= ~MIF_CONFIG_INDIRECT_MODE;
1857         nw64(MIF_CONFIG, val);
1858
1859         return mii_init_common(np);
1860 }
1861
1862 static int niu_xcvr_init(struct niu *np)
1863 {
1864         const struct niu_phy_ops *ops = np->phy_ops;
1865         int err;
1866
1867         err = 0;
1868         if (ops->xcvr_init)
1869                 err = ops->xcvr_init(np);
1870
1871         return err;
1872 }
1873
1874 static int niu_serdes_init(struct niu *np)
1875 {
1876         const struct niu_phy_ops *ops = np->phy_ops;
1877         int err;
1878
1879         err = 0;
1880         if (ops->serdes_init)
1881                 err = ops->serdes_init(np);
1882
1883         return err;
1884 }
1885
1886 static void niu_init_xif(struct niu *);
1887 static void niu_handle_led(struct niu *, int status);
1888
1889 static int niu_link_status_common(struct niu *np, int link_up)
1890 {
1891         struct niu_link_config *lp = &np->link_config;
1892         struct net_device *dev = np->dev;
1893         unsigned long flags;
1894
1895         if (!netif_carrier_ok(dev) && link_up) {
1896                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1897                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1898                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1899                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1900                            "10Mbit/sec",
1901                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1902
1903                 spin_lock_irqsave(&np->lock, flags);
1904                 niu_init_xif(np);
1905                 niu_handle_led(np, 1);
1906                 spin_unlock_irqrestore(&np->lock, flags);
1907
1908                 netif_carrier_on(dev);
1909         } else if (netif_carrier_ok(dev) && !link_up) {
1910                 netif_warn(np, link, dev, "Link is down\n");
1911                 spin_lock_irqsave(&np->lock, flags);
1912                 niu_handle_led(np, 0);
1913                 spin_unlock_irqrestore(&np->lock, flags);
1914                 netif_carrier_off(dev);
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1921 {
1922         int err, link_up, pma_status, pcs_status;
1923
1924         link_up = 0;
1925
1926         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1927                         MRVL88X2011_10G_PMD_STATUS_2);
1928         if (err < 0)
1929                 goto out;
1930
1931         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1932         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1933                         MRVL88X2011_PMA_PMD_STATUS_1);
1934         if (err < 0)
1935                 goto out;
1936
1937         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1938
1939         /* Check PMC Register : 3.0001.2 == 1: read twice */
1940         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1941                         MRVL88X2011_PMA_PMD_STATUS_1);
1942         if (err < 0)
1943                 goto out;
1944
1945         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1946                         MRVL88X2011_PMA_PMD_STATUS_1);
1947         if (err < 0)
1948                 goto out;
1949
1950         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1951
1952         /* Check XGXS Register : 4.0018.[0-3,12] */
1953         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1954                         MRVL88X2011_10G_XGXS_LANE_STAT);
1955         if (err < 0)
1956                 goto out;
1957
1958         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1959                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1960                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1961                     0x800))
1962                 link_up = (pma_status && pcs_status) ? 1 : 0;
1963
1964         np->link_config.active_speed = SPEED_10000;
1965         np->link_config.active_duplex = DUPLEX_FULL;
1966         err = 0;
1967 out:
1968         mrvl88x2011_act_led(np, (link_up ?
1969                                  MRVL88X2011_LED_CTL_PCS_ACT :
1970                                  MRVL88X2011_LED_CTL_OFF));
1971
1972         *link_up_p = link_up;
1973         return err;
1974 }
1975
1976 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1977 {
1978         int err, link_up;
1979         link_up = 0;
1980
1981         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1982                         BCM8704_PMD_RCV_SIGDET);
1983         if (err < 0 || err == 0xffff)
1984                 goto out;
1985         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1986                 err = 0;
1987                 goto out;
1988         }
1989
1990         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1991                         BCM8704_PCS_10G_R_STATUS);
1992         if (err < 0)
1993                 goto out;
1994
1995         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1996                 err = 0;
1997                 goto out;
1998         }
1999
2000         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2001                         BCM8704_PHYXS_XGXS_LANE_STAT);
2002         if (err < 0)
2003                 goto out;
2004         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2005                     PHYXS_XGXS_LANE_STAT_MAGIC |
2006                     PHYXS_XGXS_LANE_STAT_PATTEST |
2007                     PHYXS_XGXS_LANE_STAT_LANE3 |
2008                     PHYXS_XGXS_LANE_STAT_LANE2 |
2009                     PHYXS_XGXS_LANE_STAT_LANE1 |
2010                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2011                 err = 0;
2012                 np->link_config.active_speed = SPEED_INVALID;
2013                 np->link_config.active_duplex = DUPLEX_INVALID;
2014                 goto out;
2015         }
2016
2017         link_up = 1;
2018         np->link_config.active_speed = SPEED_10000;
2019         np->link_config.active_duplex = DUPLEX_FULL;
2020         err = 0;
2021
2022 out:
2023         *link_up_p = link_up;
2024         return err;
2025 }
2026
2027 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2028 {
2029         int err, link_up;
2030
2031         link_up = 0;
2032
2033         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2034                         BCM8704_PMD_RCV_SIGDET);
2035         if (err < 0)
2036                 goto out;
2037         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2038                 err = 0;
2039                 goto out;
2040         }
2041
2042         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2043                         BCM8704_PCS_10G_R_STATUS);
2044         if (err < 0)
2045                 goto out;
2046         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2047                 err = 0;
2048                 goto out;
2049         }
2050
2051         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2052                         BCM8704_PHYXS_XGXS_LANE_STAT);
2053         if (err < 0)
2054                 goto out;
2055
2056         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2057                     PHYXS_XGXS_LANE_STAT_MAGIC |
2058                     PHYXS_XGXS_LANE_STAT_LANE3 |
2059                     PHYXS_XGXS_LANE_STAT_LANE2 |
2060                     PHYXS_XGXS_LANE_STAT_LANE1 |
2061                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2062                 err = 0;
2063                 goto out;
2064         }
2065
2066         link_up = 1;
2067         np->link_config.active_speed = SPEED_10000;
2068         np->link_config.active_duplex = DUPLEX_FULL;
2069         err = 0;
2070
2071 out:
2072         *link_up_p = link_up;
2073         return err;
2074 }
2075
2076 static int link_status_10g(struct niu *np, int *link_up_p)
2077 {
2078         unsigned long flags;
2079         int err = -EINVAL;
2080
2081         spin_lock_irqsave(&np->lock, flags);
2082
2083         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2084                 int phy_id;
2085
2086                 phy_id = phy_decode(np->parent->port_phy, np->port);
2087                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2088
2089                 /* handle different phy types */
2090                 switch (phy_id & NIU_PHY_ID_MASK) {
2091                 case NIU_PHY_ID_MRVL88X2011:
2092                         err = link_status_10g_mrvl(np, link_up_p);
2093                         break;
2094
2095                 default: /* bcom 8704 */
2096                         err = link_status_10g_bcom(np, link_up_p);
2097                         break;
2098                 }
2099         }
2100
2101         spin_unlock_irqrestore(&np->lock, flags);
2102
2103         return err;
2104 }
2105
2106 static int niu_10g_phy_present(struct niu *np)
2107 {
2108         u64 sig, mask, val;
2109
2110         sig = nr64(ESR_INT_SIGNALS);
2111         switch (np->port) {
2112         case 0:
2113                 mask = ESR_INT_SIGNALS_P0_BITS;
2114                 val = (ESR_INT_SRDY0_P0 |
2115                        ESR_INT_DET0_P0 |
2116                        ESR_INT_XSRDY_P0 |
2117                        ESR_INT_XDP_P0_CH3 |
2118                        ESR_INT_XDP_P0_CH2 |
2119                        ESR_INT_XDP_P0_CH1 |
2120                        ESR_INT_XDP_P0_CH0);
2121                 break;
2122
2123         case 1:
2124                 mask = ESR_INT_SIGNALS_P1_BITS;
2125                 val = (ESR_INT_SRDY0_P1 |
2126                        ESR_INT_DET0_P1 |
2127                        ESR_INT_XSRDY_P1 |
2128                        ESR_INT_XDP_P1_CH3 |
2129                        ESR_INT_XDP_P1_CH2 |
2130                        ESR_INT_XDP_P1_CH1 |
2131                        ESR_INT_XDP_P1_CH0);
2132                 break;
2133
2134         default:
2135                 return 0;
2136         }
2137
2138         if ((sig & mask) != val)
2139                 return 0;
2140         return 1;
2141 }
2142
2143 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2144 {
2145         unsigned long flags;
2146         int err = 0;
2147         int phy_present;
2148         int phy_present_prev;
2149
2150         spin_lock_irqsave(&np->lock, flags);
2151
2152         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2153                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2154                         1 : 0;
2155                 phy_present = niu_10g_phy_present(np);
2156                 if (phy_present != phy_present_prev) {
2157                         /* state change */
2158                         if (phy_present) {
2159                                 /* A NEM was just plugged in */
2160                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2161                                 if (np->phy_ops->xcvr_init)
2162                                         err = np->phy_ops->xcvr_init(np);
2163                                 if (err) {
2164                                         err = mdio_read(np, np->phy_addr,
2165                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2166                                         if (err == 0xffff) {
2167                                                 /* No mdio, back-to-back XAUI */
2168                                                 goto out;
2169                                         }
2170                                         /* debounce */
2171                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2172                                 }
2173                         } else {
2174                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2175                                 *link_up_p = 0;
2176                                 netif_warn(np, link, np->dev,
2177                                            "Hotplug PHY Removed\n");
2178                         }
2179                 }
2180 out:
2181                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2182                         err = link_status_10g_bcm8706(np, link_up_p);
2183                         if (err == 0xffff) {
2184                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2185                                 *link_up_p = 1;
2186                                 np->link_config.active_speed = SPEED_10000;
2187                                 np->link_config.active_duplex = DUPLEX_FULL;
2188                         }
2189                 }
2190         }
2191
2192         spin_unlock_irqrestore(&np->lock, flags);
2193
2194         return 0;
2195 }
2196
2197 static int niu_link_status(struct niu *np, int *link_up_p)
2198 {
2199         const struct niu_phy_ops *ops = np->phy_ops;
2200         int err;
2201
2202         err = 0;
2203         if (ops->link_status)
2204                 err = ops->link_status(np, link_up_p);
2205
2206         return err;
2207 }
2208
2209 static void niu_timer(struct timer_list *t)
2210 {
2211         struct niu *np = from_timer(np, t, timer);
2212         unsigned long off;
2213         int err, link_up;
2214
2215         err = niu_link_status(np, &link_up);
2216         if (!err)
2217                 niu_link_status_common(np, link_up);
2218
2219         if (netif_carrier_ok(np->dev))
2220                 off = 5 * HZ;
2221         else
2222                 off = 1 * HZ;
2223         np->timer.expires = jiffies + off;
2224
2225         add_timer(&np->timer);
2226 }
2227
2228 static const struct niu_phy_ops phy_ops_10g_serdes = {
2229         .serdes_init            = serdes_init_10g_serdes,
2230         .link_status            = link_status_10g_serdes,
2231 };
2232
2233 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2234         .serdes_init            = serdes_init_niu_10g_serdes,
2235         .link_status            = link_status_10g_serdes,
2236 };
2237
2238 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2239         .serdes_init            = serdes_init_niu_1g_serdes,
2240         .link_status            = link_status_1g_serdes,
2241 };
2242
2243 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2244         .xcvr_init              = xcvr_init_1g_rgmii,
2245         .link_status            = link_status_1g_rgmii,
2246 };
2247
2248 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2249         .serdes_init            = serdes_init_niu_10g_fiber,
2250         .xcvr_init              = xcvr_init_10g,
2251         .link_status            = link_status_10g,
2252 };
2253
2254 static const struct niu_phy_ops phy_ops_10g_fiber = {
2255         .serdes_init            = serdes_init_10g,
2256         .xcvr_init              = xcvr_init_10g,
2257         .link_status            = link_status_10g,
2258 };
2259
2260 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2261         .serdes_init            = serdes_init_10g,
2262         .xcvr_init              = xcvr_init_10g_bcm8706,
2263         .link_status            = link_status_10g_hotplug,
2264 };
2265
2266 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2267         .serdes_init            = serdes_init_niu_10g_fiber,
2268         .xcvr_init              = xcvr_init_10g_bcm8706,
2269         .link_status            = link_status_10g_hotplug,
2270 };
2271
2272 static const struct niu_phy_ops phy_ops_10g_copper = {
2273         .serdes_init            = serdes_init_10g,
2274         .link_status            = link_status_10g, /* XXX */
2275 };
2276
2277 static const struct niu_phy_ops phy_ops_1g_fiber = {
2278         .serdes_init            = serdes_init_1g,
2279         .xcvr_init              = xcvr_init_1g,
2280         .link_status            = link_status_1g,
2281 };
2282
2283 static const struct niu_phy_ops phy_ops_1g_copper = {
2284         .xcvr_init              = xcvr_init_1g,
2285         .link_status            = link_status_1g,
2286 };
2287
2288 struct niu_phy_template {
2289         const struct niu_phy_ops        *ops;
2290         u32                             phy_addr_base;
2291 };
2292
2293 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2294         .ops            = &phy_ops_10g_fiber_niu,
2295         .phy_addr_base  = 16,
2296 };
2297
2298 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2299         .ops            = &phy_ops_10g_serdes_niu,
2300         .phy_addr_base  = 0,
2301 };
2302
2303 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2304         .ops            = &phy_ops_1g_serdes_niu,
2305         .phy_addr_base  = 0,
2306 };
2307
2308 static const struct niu_phy_template phy_template_10g_fiber = {
2309         .ops            = &phy_ops_10g_fiber,
2310         .phy_addr_base  = 8,
2311 };
2312
2313 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2314         .ops            = &phy_ops_10g_fiber_hotplug,
2315         .phy_addr_base  = 8,
2316 };
2317
2318 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2319         .ops            = &phy_ops_niu_10g_hotplug,
2320         .phy_addr_base  = 8,
2321 };
2322
2323 static const struct niu_phy_template phy_template_10g_copper = {
2324         .ops            = &phy_ops_10g_copper,
2325         .phy_addr_base  = 10,
2326 };
2327
2328 static const struct niu_phy_template phy_template_1g_fiber = {
2329         .ops            = &phy_ops_1g_fiber,
2330         .phy_addr_base  = 0,
2331 };
2332
2333 static const struct niu_phy_template phy_template_1g_copper = {
2334         .ops            = &phy_ops_1g_copper,
2335         .phy_addr_base  = 0,
2336 };
2337
2338 static const struct niu_phy_template phy_template_1g_rgmii = {
2339         .ops            = &phy_ops_1g_rgmii,
2340         .phy_addr_base  = 0,
2341 };
2342
2343 static const struct niu_phy_template phy_template_10g_serdes = {
2344         .ops            = &phy_ops_10g_serdes,
2345         .phy_addr_base  = 0,
2346 };
2347
2348 static int niu_atca_port_num[4] = {
2349         0, 0,  11, 10
2350 };
2351
2352 static int serdes_init_10g_serdes(struct niu *np)
2353 {
2354         struct niu_link_config *lp = &np->link_config;
2355         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2356         u64 ctrl_val, test_cfg_val, sig, mask, val;
2357
2358         switch (np->port) {
2359         case 0:
2360                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2361                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2362                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2363                 break;
2364         case 1:
2365                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2366                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2367                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2368                 break;
2369
2370         default:
2371                 return -EINVAL;
2372         }
2373         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2374                     ENET_SERDES_CTRL_SDET_1 |
2375                     ENET_SERDES_CTRL_SDET_2 |
2376                     ENET_SERDES_CTRL_SDET_3 |
2377                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2378                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2379                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2380                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2381                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2382                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2383                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2384                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2385         test_cfg_val = 0;
2386
2387         if (lp->loopback_mode == LOOPBACK_PHY) {
2388                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2389                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2390                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2391                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2392                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2393                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2394                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2395                                   ENET_SERDES_TEST_MD_3_SHIFT));
2396         }
2397
2398         esr_reset(np);
2399         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2400         nw64(ctrl_reg, ctrl_val);
2401         nw64(test_cfg_reg, test_cfg_val);
2402
2403         /* Initialize all 4 lanes of the SERDES.  */
2404         for (i = 0; i < 4; i++) {
2405                 u32 rxtx_ctrl, glue0;
2406                 int err;
2407
2408                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2409                 if (err)
2410                         return err;
2411                 err = esr_read_glue0(np, i, &glue0);
2412                 if (err)
2413                         return err;
2414
2415                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2416                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2417                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2418
2419                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2420                            ESR_GLUE_CTRL0_THCNT |
2421                            ESR_GLUE_CTRL0_BLTIME);
2422                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2423                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2424                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2425                           (BLTIME_300_CYCLES <<
2426                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2427
2428                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2429                 if (err)
2430                         return err;
2431                 err = esr_write_glue0(np, i, glue0);
2432                 if (err)
2433                         return err;
2434         }
2435
2436
2437         sig = nr64(ESR_INT_SIGNALS);
2438         switch (np->port) {
2439         case 0:
2440                 mask = ESR_INT_SIGNALS_P0_BITS;
2441                 val = (ESR_INT_SRDY0_P0 |
2442                        ESR_INT_DET0_P0 |
2443                        ESR_INT_XSRDY_P0 |
2444                        ESR_INT_XDP_P0_CH3 |
2445                        ESR_INT_XDP_P0_CH2 |
2446                        ESR_INT_XDP_P0_CH1 |
2447                        ESR_INT_XDP_P0_CH0);
2448                 break;
2449
2450         case 1:
2451                 mask = ESR_INT_SIGNALS_P1_BITS;
2452                 val = (ESR_INT_SRDY0_P1 |
2453                        ESR_INT_DET0_P1 |
2454                        ESR_INT_XSRDY_P1 |
2455                        ESR_INT_XDP_P1_CH3 |
2456                        ESR_INT_XDP_P1_CH2 |
2457                        ESR_INT_XDP_P1_CH1 |
2458                        ESR_INT_XDP_P1_CH0);
2459                 break;
2460
2461         default:
2462                 return -EINVAL;
2463         }
2464
2465         if ((sig & mask) != val) {
2466                 int err;
2467                 err = serdes_init_1g_serdes(np);
2468                 if (!err) {
2469                         np->flags &= ~NIU_FLAGS_10G;
2470                         np->mac_xcvr = MAC_XCVR_PCS;
2471                 }  else {
2472                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2473                                    np->port);
2474                         return -ENODEV;
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481 static int niu_determine_phy_disposition(struct niu *np)
2482 {
2483         struct niu_parent *parent = np->parent;
2484         u8 plat_type = parent->plat_type;
2485         const struct niu_phy_template *tp;
2486         u32 phy_addr_off = 0;
2487
2488         if (plat_type == PLAT_TYPE_NIU) {
2489                 switch (np->flags &
2490                         (NIU_FLAGS_10G |
2491                          NIU_FLAGS_FIBER |
2492                          NIU_FLAGS_XCVR_SERDES)) {
2493                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2494                         /* 10G Serdes */
2495                         tp = &phy_template_niu_10g_serdes;
2496                         break;
2497                 case NIU_FLAGS_XCVR_SERDES:
2498                         /* 1G Serdes */
2499                         tp = &phy_template_niu_1g_serdes;
2500                         break;
2501                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2502                         /* 10G Fiber */
2503                 default:
2504                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2505                                 tp = &phy_template_niu_10g_hotplug;
2506                                 if (np->port == 0)
2507                                         phy_addr_off = 8;
2508                                 if (np->port == 1)
2509                                         phy_addr_off = 12;
2510                         } else {
2511                                 tp = &phy_template_niu_10g_fiber;
2512                                 phy_addr_off += np->port;
2513                         }
2514                         break;
2515                 }
2516         } else {
2517                 switch (np->flags &
2518                         (NIU_FLAGS_10G |
2519                          NIU_FLAGS_FIBER |
2520                          NIU_FLAGS_XCVR_SERDES)) {
2521                 case 0:
2522                         /* 1G copper */
2523                         tp = &phy_template_1g_copper;
2524                         if (plat_type == PLAT_TYPE_VF_P0)
2525                                 phy_addr_off = 10;
2526                         else if (plat_type == PLAT_TYPE_VF_P1)
2527                                 phy_addr_off = 26;
2528
2529                         phy_addr_off += (np->port ^ 0x3);
2530                         break;
2531
2532                 case NIU_FLAGS_10G:
2533                         /* 10G copper */
2534                         tp = &phy_template_10g_copper;
2535                         break;
2536
2537                 case NIU_FLAGS_FIBER:
2538                         /* 1G fiber */
2539                         tp = &phy_template_1g_fiber;
2540                         break;
2541
2542                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2543                         /* 10G fiber */
2544                         tp = &phy_template_10g_fiber;
2545                         if (plat_type == PLAT_TYPE_VF_P0 ||
2546                             plat_type == PLAT_TYPE_VF_P1)
2547                                 phy_addr_off = 8;
2548                         phy_addr_off += np->port;
2549                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2550                                 tp = &phy_template_10g_fiber_hotplug;
2551                                 if (np->port == 0)
2552                                         phy_addr_off = 8;
2553                                 if (np->port == 1)
2554                                         phy_addr_off = 12;
2555                         }
2556                         break;
2557
2558                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2559                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2560                 case NIU_FLAGS_XCVR_SERDES:
2561                         switch(np->port) {
2562                         case 0:
2563                         case 1:
2564                                 tp = &phy_template_10g_serdes;
2565                                 break;
2566                         case 2:
2567                         case 3:
2568                                 tp = &phy_template_1g_rgmii;
2569                                 break;
2570                         default:
2571                                 return -EINVAL;
2572                         }
2573                         phy_addr_off = niu_atca_port_num[np->port];
2574                         break;
2575
2576                 default:
2577                         return -EINVAL;
2578                 }
2579         }
2580
2581         np->phy_ops = tp->ops;
2582         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2583
2584         return 0;
2585 }
2586
2587 static int niu_init_link(struct niu *np)
2588 {
2589         struct niu_parent *parent = np->parent;
2590         int err, ignore;
2591
2592         if (parent->plat_type == PLAT_TYPE_NIU) {
2593                 err = niu_xcvr_init(np);
2594                 if (err)
2595                         return err;
2596                 msleep(200);
2597         }
2598         err = niu_serdes_init(np);
2599         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2600                 return err;
2601         msleep(200);
2602         err = niu_xcvr_init(np);
2603         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2604                 niu_link_status(np, &ignore);
2605         return 0;
2606 }
2607
2608 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2609 {
2610         u16 reg0 = addr[4] << 8 | addr[5];
2611         u16 reg1 = addr[2] << 8 | addr[3];
2612         u16 reg2 = addr[0] << 8 | addr[1];
2613
2614         if (np->flags & NIU_FLAGS_XMAC) {
2615                 nw64_mac(XMAC_ADDR0, reg0);
2616                 nw64_mac(XMAC_ADDR1, reg1);
2617                 nw64_mac(XMAC_ADDR2, reg2);
2618         } else {
2619                 nw64_mac(BMAC_ADDR0, reg0);
2620                 nw64_mac(BMAC_ADDR1, reg1);
2621                 nw64_mac(BMAC_ADDR2, reg2);
2622         }
2623 }
2624
2625 static int niu_num_alt_addr(struct niu *np)
2626 {
2627         if (np->flags & NIU_FLAGS_XMAC)
2628                 return XMAC_NUM_ALT_ADDR;
2629         else
2630                 return BMAC_NUM_ALT_ADDR;
2631 }
2632
2633 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2634 {
2635         u16 reg0 = addr[4] << 8 | addr[5];
2636         u16 reg1 = addr[2] << 8 | addr[3];
2637         u16 reg2 = addr[0] << 8 | addr[1];
2638
2639         if (index >= niu_num_alt_addr(np))
2640                 return -EINVAL;
2641
2642         if (np->flags & NIU_FLAGS_XMAC) {
2643                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2644                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2645                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2646         } else {
2647                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2648                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2649                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2656 {
2657         unsigned long reg;
2658         u64 val, mask;
2659
2660         if (index >= niu_num_alt_addr(np))
2661                 return -EINVAL;
2662
2663         if (np->flags & NIU_FLAGS_XMAC) {
2664                 reg = XMAC_ADDR_CMPEN;
2665                 mask = 1 << index;
2666         } else {
2667                 reg = BMAC_ADDR_CMPEN;
2668                 mask = 1 << (index + 1);
2669         }
2670
2671         val = nr64_mac(reg);
2672         if (on)
2673                 val |= mask;
2674         else
2675                 val &= ~mask;
2676         nw64_mac(reg, val);
2677
2678         return 0;
2679 }
2680
2681 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2682                                    int num, int mac_pref)
2683 {
2684         u64 val = nr64_mac(reg);
2685         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2686         val |= num;
2687         if (mac_pref)
2688                 val |= HOST_INFO_MPR;
2689         nw64_mac(reg, val);
2690 }
2691
2692 static int __set_rdc_table_num(struct niu *np,
2693                                int xmac_index, int bmac_index,
2694                                int rdc_table_num, int mac_pref)
2695 {
2696         unsigned long reg;
2697
2698         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2699                 return -EINVAL;
2700         if (np->flags & NIU_FLAGS_XMAC)
2701                 reg = XMAC_HOST_INFO(xmac_index);
2702         else
2703                 reg = BMAC_HOST_INFO(bmac_index);
2704         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2705         return 0;
2706 }
2707
2708 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2709                                          int mac_pref)
2710 {
2711         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2712 }
2713
2714 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2715                                            int mac_pref)
2716 {
2717         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2718 }
2719
2720 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2721                                      int table_num, int mac_pref)
2722 {
2723         if (idx >= niu_num_alt_addr(np))
2724                 return -EINVAL;
2725         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2726 }
2727
2728 static u64 vlan_entry_set_parity(u64 reg_val)
2729 {
2730         u64 port01_mask;
2731         u64 port23_mask;
2732
2733         port01_mask = 0x00ff;
2734         port23_mask = 0xff00;
2735
2736         if (hweight64(reg_val & port01_mask) & 1)
2737                 reg_val |= ENET_VLAN_TBL_PARITY0;
2738         else
2739                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2740
2741         if (hweight64(reg_val & port23_mask) & 1)
2742                 reg_val |= ENET_VLAN_TBL_PARITY1;
2743         else
2744                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2745
2746         return reg_val;
2747 }
2748
2749 static void vlan_tbl_write(struct niu *np, unsigned long index,
2750                            int port, int vpr, int rdc_table)
2751 {
2752         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2753
2754         reg_val &= ~((ENET_VLAN_TBL_VPR |
2755                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2756                      ENET_VLAN_TBL_SHIFT(port));
2757         if (vpr)
2758                 reg_val |= (ENET_VLAN_TBL_VPR <<
2759                             ENET_VLAN_TBL_SHIFT(port));
2760         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2761
2762         reg_val = vlan_entry_set_parity(reg_val);
2763
2764         nw64(ENET_VLAN_TBL(index), reg_val);
2765 }
2766
2767 static void vlan_tbl_clear(struct niu *np)
2768 {
2769         int i;
2770
2771         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2772                 nw64(ENET_VLAN_TBL(i), 0);
2773 }
2774
2775 static int tcam_wait_bit(struct niu *np, u64 bit)
2776 {
2777         int limit = 1000;
2778
2779         while (--limit > 0) {
2780                 if (nr64(TCAM_CTL) & bit)
2781                         break;
2782                 udelay(1);
2783         }
2784         if (limit <= 0)
2785                 return -ENODEV;
2786
2787         return 0;
2788 }
2789
2790 static int tcam_flush(struct niu *np, int index)
2791 {
2792         nw64(TCAM_KEY_0, 0x00);
2793         nw64(TCAM_KEY_MASK_0, 0xff);
2794         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2795
2796         return tcam_wait_bit(np, TCAM_CTL_STAT);
2797 }
2798
2799 #if 0
2800 static int tcam_read(struct niu *np, int index,
2801                      u64 *key, u64 *mask)
2802 {
2803         int err;
2804
2805         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2806         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2807         if (!err) {
2808                 key[0] = nr64(TCAM_KEY_0);
2809                 key[1] = nr64(TCAM_KEY_1);
2810                 key[2] = nr64(TCAM_KEY_2);
2811                 key[3] = nr64(TCAM_KEY_3);
2812                 mask[0] = nr64(TCAM_KEY_MASK_0);
2813                 mask[1] = nr64(TCAM_KEY_MASK_1);
2814                 mask[2] = nr64(TCAM_KEY_MASK_2);
2815                 mask[3] = nr64(TCAM_KEY_MASK_3);
2816         }
2817         return err;
2818 }
2819 #endif
2820
2821 static int tcam_write(struct niu *np, int index,
2822                       u64 *key, u64 *mask)
2823 {
2824         nw64(TCAM_KEY_0, key[0]);
2825         nw64(TCAM_KEY_1, key[1]);
2826         nw64(TCAM_KEY_2, key[2]);
2827         nw64(TCAM_KEY_3, key[3]);
2828         nw64(TCAM_KEY_MASK_0, mask[0]);
2829         nw64(TCAM_KEY_MASK_1, mask[1]);
2830         nw64(TCAM_KEY_MASK_2, mask[2]);
2831         nw64(TCAM_KEY_MASK_3, mask[3]);
2832         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2833
2834         return tcam_wait_bit(np, TCAM_CTL_STAT);
2835 }
2836
2837 #if 0
2838 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2839 {
2840         int err;
2841
2842         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2843         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2844         if (!err)
2845                 *data = nr64(TCAM_KEY_1);
2846
2847         return err;
2848 }
2849 #endif
2850
2851 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2852 {
2853         nw64(TCAM_KEY_1, assoc_data);
2854         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2855
2856         return tcam_wait_bit(np, TCAM_CTL_STAT);
2857 }
2858
2859 static void tcam_enable(struct niu *np, int on)
2860 {
2861         u64 val = nr64(FFLP_CFG_1);
2862
2863         if (on)
2864                 val &= ~FFLP_CFG_1_TCAM_DIS;
2865         else
2866                 val |= FFLP_CFG_1_TCAM_DIS;
2867         nw64(FFLP_CFG_1, val);
2868 }
2869
2870 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2871 {
2872         u64 val = nr64(FFLP_CFG_1);
2873
2874         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2875                  FFLP_CFG_1_CAMLAT |
2876                  FFLP_CFG_1_CAMRATIO);
2877         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2878         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2879         nw64(FFLP_CFG_1, val);
2880
2881         val = nr64(FFLP_CFG_1);
2882         val |= FFLP_CFG_1_FFLPINITDONE;
2883         nw64(FFLP_CFG_1, val);
2884 }
2885
2886 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2887                                       int on)
2888 {
2889         unsigned long reg;
2890         u64 val;
2891
2892         if (class < CLASS_CODE_ETHERTYPE1 ||
2893             class > CLASS_CODE_ETHERTYPE2)
2894                 return -EINVAL;
2895
2896         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2897         val = nr64(reg);
2898         if (on)
2899                 val |= L2_CLS_VLD;
2900         else
2901                 val &= ~L2_CLS_VLD;
2902         nw64(reg, val);
2903
2904         return 0;
2905 }
2906
2907 #if 0
2908 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2909                                    u64 ether_type)
2910 {
2911         unsigned long reg;
2912         u64 val;
2913
2914         if (class < CLASS_CODE_ETHERTYPE1 ||
2915             class > CLASS_CODE_ETHERTYPE2 ||
2916             (ether_type & ~(u64)0xffff) != 0)
2917                 return -EINVAL;
2918
2919         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2920         val = nr64(reg);
2921         val &= ~L2_CLS_ETYPE;
2922         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2923         nw64(reg, val);
2924
2925         return 0;
2926 }
2927 #endif
2928
2929 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2930                                      int on)
2931 {
2932         unsigned long reg;
2933         u64 val;
2934
2935         if (class < CLASS_CODE_USER_PROG1 ||
2936             class > CLASS_CODE_USER_PROG4)
2937                 return -EINVAL;
2938
2939         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2940         val = nr64(reg);
2941         if (on)
2942                 val |= L3_CLS_VALID;
2943         else
2944                 val &= ~L3_CLS_VALID;
2945         nw64(reg, val);
2946
2947         return 0;
2948 }
2949
2950 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2951                                   int ipv6, u64 protocol_id,
2952                                   u64 tos_mask, u64 tos_val)
2953 {
2954         unsigned long reg;
2955         u64 val;
2956
2957         if (class < CLASS_CODE_USER_PROG1 ||
2958             class > CLASS_CODE_USER_PROG4 ||
2959             (protocol_id & ~(u64)0xff) != 0 ||
2960             (tos_mask & ~(u64)0xff) != 0 ||
2961             (tos_val & ~(u64)0xff) != 0)
2962                 return -EINVAL;
2963
2964         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2965         val = nr64(reg);
2966         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2967                  L3_CLS_TOSMASK | L3_CLS_TOS);
2968         if (ipv6)
2969                 val |= L3_CLS_IPVER;
2970         val |= (protocol_id << L3_CLS_PID_SHIFT);
2971         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2972         val |= (tos_val << L3_CLS_TOS_SHIFT);
2973         nw64(reg, val);
2974
2975         return 0;
2976 }
2977
2978 static int tcam_early_init(struct niu *np)
2979 {
2980         unsigned long i;
2981         int err;
2982
2983         tcam_enable(np, 0);
2984         tcam_set_lat_and_ratio(np,
2985                                DEFAULT_TCAM_LATENCY,
2986                                DEFAULT_TCAM_ACCESS_RATIO);
2987         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2988                 err = tcam_user_eth_class_enable(np, i, 0);
2989                 if (err)
2990                         return err;
2991         }
2992         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2993                 err = tcam_user_ip_class_enable(np, i, 0);
2994                 if (err)
2995                         return err;
2996         }
2997
2998         return 0;
2999 }
3000
3001 static int tcam_flush_all(struct niu *np)
3002 {
3003         unsigned long i;
3004
3005         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3006                 int err = tcam_flush(np, i);
3007                 if (err)
3008                         return err;
3009         }
3010         return 0;
3011 }
3012
3013 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3014 {
3015         return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3016 }
3017
3018 #if 0
3019 static int hash_read(struct niu *np, unsigned long partition,
3020                      unsigned long index, unsigned long num_entries,
3021                      u64 *data)
3022 {
3023         u64 val = hash_addr_regval(index, num_entries);
3024         unsigned long i;
3025
3026         if (partition >= FCRAM_NUM_PARTITIONS ||
3027             index + num_entries > FCRAM_SIZE)
3028                 return -EINVAL;
3029
3030         nw64(HASH_TBL_ADDR(partition), val);
3031         for (i = 0; i < num_entries; i++)
3032                 data[i] = nr64(HASH_TBL_DATA(partition));
3033
3034         return 0;
3035 }
3036 #endif
3037
3038 static int hash_write(struct niu *np, unsigned long partition,
3039                       unsigned long index, unsigned long num_entries,
3040                       u64 *data)
3041 {
3042         u64 val = hash_addr_regval(index, num_entries);
3043         unsigned long i;
3044
3045         if (partition >= FCRAM_NUM_PARTITIONS ||
3046             index + (num_entries * 8) > FCRAM_SIZE)
3047                 return -EINVAL;
3048
3049         nw64(HASH_TBL_ADDR(partition), val);
3050         for (i = 0; i < num_entries; i++)
3051                 nw64(HASH_TBL_DATA(partition), data[i]);
3052
3053         return 0;
3054 }
3055
3056 static void fflp_reset(struct niu *np)
3057 {
3058         u64 val;
3059
3060         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3061         udelay(10);
3062         nw64(FFLP_CFG_1, 0);
3063
3064         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3065         nw64(FFLP_CFG_1, val);
3066 }
3067
3068 static void fflp_set_timings(struct niu *np)
3069 {
3070         u64 val = nr64(FFLP_CFG_1);
3071
3072         val &= ~FFLP_CFG_1_FFLPINITDONE;
3073         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3074         nw64(FFLP_CFG_1, val);
3075
3076         val = nr64(FFLP_CFG_1);
3077         val |= FFLP_CFG_1_FFLPINITDONE;
3078         nw64(FFLP_CFG_1, val);
3079
3080         val = nr64(FCRAM_REF_TMR);
3081         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3082         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3083         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3084         nw64(FCRAM_REF_TMR, val);
3085 }
3086
3087 static int fflp_set_partition(struct niu *np, u64 partition,
3088                               u64 mask, u64 base, int enable)
3089 {
3090         unsigned long reg;
3091         u64 val;
3092
3093         if (partition >= FCRAM_NUM_PARTITIONS ||
3094             (mask & ~(u64)0x1f) != 0 ||
3095             (base & ~(u64)0x1f) != 0)
3096                 return -EINVAL;
3097
3098         reg = FLW_PRT_SEL(partition);
3099
3100         val = nr64(reg);
3101         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3102         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3103         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3104         if (enable)
3105                 val |= FLW_PRT_SEL_EXT;
3106         nw64(reg, val);
3107
3108         return 0;
3109 }
3110
3111 static int fflp_disable_all_partitions(struct niu *np)
3112 {
3113         unsigned long i;
3114
3115         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3116                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3117                 if (err)
3118                         return err;
3119         }
3120         return 0;
3121 }
3122
3123 static void fflp_llcsnap_enable(struct niu *np, int on)
3124 {
3125         u64 val = nr64(FFLP_CFG_1);
3126
3127         if (on)
3128                 val |= FFLP_CFG_1_LLCSNAP;
3129         else
3130                 val &= ~FFLP_CFG_1_LLCSNAP;
3131         nw64(FFLP_CFG_1, val);
3132 }
3133
3134 static void fflp_errors_enable(struct niu *np, int on)
3135 {
3136         u64 val = nr64(FFLP_CFG_1);
3137
3138         if (on)
3139                 val &= ~FFLP_CFG_1_ERRORDIS;
3140         else
3141                 val |= FFLP_CFG_1_ERRORDIS;
3142         nw64(FFLP_CFG_1, val);
3143 }
3144
3145 static int fflp_hash_clear(struct niu *np)
3146 {
3147         struct fcram_hash_ipv4 ent;
3148         unsigned long i;
3149
3150         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3151         memset(&ent, 0, sizeof(ent));
3152         ent.header = HASH_HEADER_EXT;
3153
3154         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3155                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3156                 if (err)
3157                         return err;
3158         }
3159         return 0;
3160 }
3161
3162 static int fflp_early_init(struct niu *np)
3163 {
3164         struct niu_parent *parent;
3165         unsigned long flags;
3166         int err;
3167
3168         niu_lock_parent(np, flags);
3169
3170         parent = np->parent;
3171         err = 0;
3172         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3173                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3174                         fflp_reset(np);
3175                         fflp_set_timings(np);
3176                         err = fflp_disable_all_partitions(np);
3177                         if (err) {
3178                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3179                                              "fflp_disable_all_partitions failed, err=%d\n",
3180                                              err);
3181                                 goto out;
3182                         }
3183                 }
3184
3185                 err = tcam_early_init(np);
3186                 if (err) {
3187                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3188                                      "tcam_early_init failed, err=%d\n", err);
3189                         goto out;
3190                 }
3191                 fflp_llcsnap_enable(np, 1);
3192                 fflp_errors_enable(np, 0);
3193                 nw64(H1POLY, 0);
3194                 nw64(H2POLY, 0);
3195
3196                 err = tcam_flush_all(np);
3197                 if (err) {
3198                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3199                                      "tcam_flush_all failed, err=%d\n", err);
3200                         goto out;
3201                 }
3202                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3203                         err = fflp_hash_clear(np);
3204                         if (err) {
3205                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3206                                              "fflp_hash_clear failed, err=%d\n",
3207                                              err);
3208                                 goto out;
3209                         }
3210                 }
3211
3212                 vlan_tbl_clear(np);
3213
3214                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3215         }
3216 out:
3217         niu_unlock_parent(np, flags);
3218         return err;
3219 }
3220
3221 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3222 {
3223         if (class_code < CLASS_CODE_USER_PROG1 ||
3224             class_code > CLASS_CODE_SCTP_IPV6)
3225                 return -EINVAL;
3226
3227         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3228         return 0;
3229 }
3230
3231 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3232 {
3233         if (class_code < CLASS_CODE_USER_PROG1 ||
3234             class_code > CLASS_CODE_SCTP_IPV6)
3235                 return -EINVAL;
3236
3237         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3238         return 0;
3239 }
3240
3241 /* Entries for the ports are interleaved in the TCAM */
3242 static u16 tcam_get_index(struct niu *np, u16 idx)
3243 {
3244         /* One entry reserved for IP fragment rule */
3245         if (idx >= (np->clas.tcam_sz - 1))
3246                 idx = 0;
3247         return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3248 }
3249
3250 static u16 tcam_get_size(struct niu *np)
3251 {
3252         /* One entry reserved for IP fragment rule */
3253         return np->clas.tcam_sz - 1;
3254 }
3255
3256 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3257 {
3258         /* One entry reserved for IP fragment rule */
3259         return np->clas.tcam_valid_entries - 1;
3260 }
3261
3262 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3263                               u32 offset, u32 size, u32 truesize)
3264 {
3265         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3266
3267         skb->len += size;
3268         skb->data_len += size;
3269         skb->truesize += truesize;
3270 }
3271
3272 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3273 {
3274         a >>= PAGE_SHIFT;
3275         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3276
3277         return a & (MAX_RBR_RING_SIZE - 1);
3278 }
3279
3280 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3281                                     struct page ***link)
3282 {
3283         unsigned int h = niu_hash_rxaddr(rp, addr);
3284         struct page *p, **pp;
3285
3286         addr &= PAGE_MASK;
3287         pp = &rp->rxhash[h];
3288         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3289                 if (p->index == addr) {
3290                         *link = pp;
3291                         goto found;
3292                 }
3293         }
3294         BUG();
3295
3296 found:
3297         return p;
3298 }
3299
3300 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3301 {
3302         unsigned int h = niu_hash_rxaddr(rp, base);
3303
3304         page->index = base;
3305         page->mapping = (struct address_space *) rp->rxhash[h];
3306         rp->rxhash[h] = page;
3307 }
3308
3309 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3310                             gfp_t mask, int start_index)
3311 {
3312         struct page *page;
3313         u64 addr;
3314         int i;
3315
3316         page = alloc_page(mask);
3317         if (!page)
3318                 return -ENOMEM;
3319
3320         addr = np->ops->map_page(np->device, page, 0,
3321                                  PAGE_SIZE, DMA_FROM_DEVICE);
3322         if (!addr) {
3323                 __free_page(page);
3324                 return -ENOMEM;
3325         }
3326
3327         niu_hash_page(rp, page, addr);
3328         if (rp->rbr_blocks_per_page > 1)
3329                 page_ref_add(page, rp->rbr_blocks_per_page - 1);
3330
3331         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3332                 __le32 *rbr = &rp->rbr[start_index + i];
3333
3334                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3335                 addr += rp->rbr_block_size;
3336         }
3337
3338         return 0;
3339 }
3340
3341 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3342 {
3343         int index = rp->rbr_index;
3344
3345         rp->rbr_pending++;
3346         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3347                 int err = niu_rbr_add_page(np, rp, mask, index);
3348
3349                 if (unlikely(err)) {
3350                         rp->rbr_pending--;
3351                         return;
3352                 }
3353
3354                 rp->rbr_index += rp->rbr_blocks_per_page;
3355                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3356                 if (rp->rbr_index == rp->rbr_table_size)
3357                         rp->rbr_index = 0;
3358
3359                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3360                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3361                         rp->rbr_pending = 0;
3362                 }
3363         }
3364 }
3365
3366 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3367 {
3368         unsigned int index = rp->rcr_index;
3369         int num_rcr = 0;
3370
3371         rp->rx_dropped++;
3372         while (1) {
3373                 struct page *page, **link;
3374                 u64 addr, val;
3375                 u32 rcr_size;
3376
3377                 num_rcr++;
3378
3379                 val = le64_to_cpup(&rp->rcr[index]);
3380                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3381                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3382                 page = niu_find_rxpage(rp, addr, &link);
3383
3384                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3385                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3386                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3387                         *link = (struct page *) page->mapping;
3388                         np->ops->unmap_page(np->device, page->index,
3389                                             PAGE_SIZE, DMA_FROM_DEVICE);
3390                         page->index = 0;
3391                         page->mapping = NULL;
3392                         __free_page(page);
3393                         rp->rbr_refill_pending++;
3394                 }
3395
3396                 index = NEXT_RCR(rp, index);
3397                 if (!(val & RCR_ENTRY_MULTI))
3398                         break;
3399
3400         }
3401         rp->rcr_index = index;
3402
3403         return num_rcr;
3404 }
3405
3406 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3407                               struct rx_ring_info *rp)
3408 {
3409         unsigned int index = rp->rcr_index;
3410         struct rx_pkt_hdr1 *rh;
3411         struct sk_buff *skb;
3412         int len, num_rcr;
3413
3414         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3415         if (unlikely(!skb))
3416                 return niu_rx_pkt_ignore(np, rp);
3417
3418         num_rcr = 0;
3419         while (1) {
3420                 struct page *page, **link;
3421                 u32 rcr_size, append_size;
3422                 u64 addr, val, off;
3423
3424                 num_rcr++;
3425
3426                 val = le64_to_cpup(&rp->rcr[index]);
3427
3428                 len = (val & RCR_ENTRY_L2_LEN) >>
3429                         RCR_ENTRY_L2_LEN_SHIFT;
3430                 append_size = len + ETH_HLEN + ETH_FCS_LEN;
3431
3432                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3433                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3434                 page = niu_find_rxpage(rp, addr, &link);
3435
3436                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3437                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3438
3439                 off = addr & ~PAGE_MASK;
3440                 if (num_rcr == 1) {
3441                         int ptype;
3442
3443                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3444                         if ((ptype == RCR_PKT_TYPE_TCP ||
3445                              ptype == RCR_PKT_TYPE_UDP) &&
3446                             !(val & (RCR_ENTRY_NOPORT |
3447                                      RCR_ENTRY_ERROR)))
3448                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3449                         else
3450                                 skb_checksum_none_assert(skb);
3451                 } else if (!(val & RCR_ENTRY_MULTI))
3452                         append_size = append_size - skb->len;
3453
3454                 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3455                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3456                         *link = (struct page *) page->mapping;
3457                         np->ops->unmap_page(np->device, page->index,
3458                                             PAGE_SIZE, DMA_FROM_DEVICE);
3459                         page->index = 0;
3460                         page->mapping = NULL;
3461                         rp->rbr_refill_pending++;
3462                 } else
3463                         get_page(page);
3464
3465                 index = NEXT_RCR(rp, index);
3466                 if (!(val & RCR_ENTRY_MULTI))
3467                         break;
3468
3469         }
3470         rp->rcr_index = index;
3471
3472         len += sizeof(*rh);
3473         len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3474         __pskb_pull_tail(skb, len);
3475
3476         rh = (struct rx_pkt_hdr1 *) skb->data;
3477         if (np->dev->features & NETIF_F_RXHASH)
3478                 skb_set_hash(skb,
3479                              ((u32)rh->hashval2_0 << 24 |
3480                               (u32)rh->hashval2_1 << 16 |
3481                               (u32)rh->hashval1_1 << 8 |
3482                               (u32)rh->hashval1_2 << 0),
3483                              PKT_HASH_TYPE_L3);
3484         skb_pull(skb, sizeof(*rh));
3485
3486         rp->rx_packets++;
3487         rp->rx_bytes += skb->len;
3488
3489         skb->protocol = eth_type_trans(skb, np->dev);
3490         skb_record_rx_queue(skb, rp->rx_channel);
3491         napi_gro_receive(napi, skb);
3492
3493         return num_rcr;
3494 }
3495
3496 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3497 {
3498         int blocks_per_page = rp->rbr_blocks_per_page;
3499         int err, index = rp->rbr_index;
3500
3501         err = 0;
3502         while (index < (rp->rbr_table_size - blocks_per_page)) {
3503                 err = niu_rbr_add_page(np, rp, mask, index);
3504                 if (unlikely(err))
3505                         break;
3506
3507                 index += blocks_per_page;
3508         }
3509
3510         rp->rbr_index = index;
3511         return err;
3512 }
3513
3514 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3515 {
3516         int i;
3517
3518         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3519                 struct page *page;
3520
3521                 page = rp->rxhash[i];
3522                 while (page) {
3523                         struct page *next = (struct page *) page->mapping;
3524                         u64 base = page->index;
3525
3526                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3527                                             DMA_FROM_DEVICE);
3528                         page->index = 0;
3529                         page->mapping = NULL;
3530
3531                         __free_page(page);
3532
3533                         page = next;
3534                 }
3535         }
3536
3537         for (i = 0; i < rp->rbr_table_size; i++)
3538                 rp->rbr[i] = cpu_to_le32(0);
3539         rp->rbr_index = 0;
3540 }
3541
3542 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3543 {
3544         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3545         struct sk_buff *skb = tb->skb;
3546         struct tx_pkt_hdr *tp;
3547         u64 tx_flags;
3548         int i, len;
3549
3550         tp = (struct tx_pkt_hdr *) skb->data;
3551         tx_flags = le64_to_cpup(&tp->flags);
3552
3553         rp->tx_packets++;
3554         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3555                          ((tx_flags & TXHDR_PAD) / 2));
3556
3557         len = skb_headlen(skb);
3558         np->ops->unmap_single(np->device, tb->mapping,
3559                               len, DMA_TO_DEVICE);
3560
3561         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3562                 rp->mark_pending--;
3563
3564         tb->skb = NULL;
3565         do {
3566                 idx = NEXT_TX(rp, idx);
3567                 len -= MAX_TX_DESC_LEN;
3568         } while (len > 0);
3569
3570         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3571                 tb = &rp->tx_buffs[idx];
3572                 BUG_ON(tb->skb != NULL);
3573                 np->ops->unmap_page(np->device, tb->mapping,
3574                                     skb_frag_size(&skb_shinfo(skb)->frags[i]),
3575                                     DMA_TO_DEVICE);
3576                 idx = NEXT_TX(rp, idx);
3577         }
3578
3579         dev_kfree_skb(skb);
3580
3581         return idx;
3582 }
3583
3584 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3585
3586 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3587 {
3588         struct netdev_queue *txq;
3589         u16 pkt_cnt, tmp;
3590         int cons, index;
3591         u64 cs;
3592
3593         index = (rp - np->tx_rings);
3594         txq = netdev_get_tx_queue(np->dev, index);
3595
3596         cs = rp->tx_cs;
3597         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3598                 goto out;
3599
3600         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3601         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3602                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3603
3604         rp->last_pkt_cnt = tmp;
3605
3606         cons = rp->cons;
3607
3608         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3609                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3610
3611         while (pkt_cnt--)
3612                 cons = release_tx_packet(np, rp, cons);
3613
3614         rp->cons = cons;
3615         smp_mb();
3616
3617 out:
3618         if (unlikely(netif_tx_queue_stopped(txq) &&
3619                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3620                 __netif_tx_lock(txq, smp_processor_id());
3621                 if (netif_tx_queue_stopped(txq) &&
3622                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3623                         netif_tx_wake_queue(txq);
3624                 __netif_tx_unlock(txq);
3625         }
3626 }
3627
3628 static inline void niu_sync_rx_discard_stats(struct niu *np,
3629                                              struct rx_ring_info *rp,
3630                                              const int limit)
3631 {
3632         /* This elaborate scheme is needed for reading the RX discard
3633          * counters, as they are only 16-bit and can overflow quickly,
3634          * and because the overflow indication bit is not usable as
3635          * the counter value does not wrap, but remains at max value
3636          * 0xFFFF.
3637          *
3638          * In theory and in practice counters can be lost in between
3639          * reading nr64() and clearing the counter nw64().  For this
3640          * reason, the number of counter clearings nw64() is
3641          * limited/reduced though the limit parameter.
3642          */
3643         int rx_channel = rp->rx_channel;
3644         u32 misc, wred;
3645
3646         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3647          * following discard events: IPP (Input Port Process),
3648          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3649          * Block Ring) prefetch buffer is empty.
3650          */
3651         misc = nr64(RXMISC(rx_channel));
3652         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3653                 nw64(RXMISC(rx_channel), 0);
3654                 rp->rx_errors += misc & RXMISC_COUNT;
3655
3656                 if (unlikely(misc & RXMISC_OFLOW))
3657                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3658                                 rx_channel);
3659
3660                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3661                              "rx-%d: MISC drop=%u over=%u\n",
3662                              rx_channel, misc, misc-limit);
3663         }
3664
3665         /* WRED (Weighted Random Early Discard) by hardware */
3666         wred = nr64(RED_DIS_CNT(rx_channel));
3667         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3668                 nw64(RED_DIS_CNT(rx_channel), 0);
3669                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3670
3671                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3672                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3673
3674                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3675                              "rx-%d: WRED drop=%u over=%u\n",
3676                              rx_channel, wred, wred-limit);
3677         }
3678 }
3679
3680 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3681                        struct rx_ring_info *rp, int budget)
3682 {
3683         int qlen, rcr_done = 0, work_done = 0;
3684         struct rxdma_mailbox *mbox = rp->mbox;
3685         u64 stat;
3686
3687 #if 1
3688         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3689         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3690 #else
3691         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3692         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3693 #endif
3694         mbox->rx_dma_ctl_stat = 0;
3695         mbox->rcrstat_a = 0;
3696
3697         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3698                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3699                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3700
3701         rcr_done = work_done = 0;
3702         qlen = min(qlen, budget);
3703         while (work_done < qlen) {
3704                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3705                 work_done++;
3706         }
3707
3708         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3709                 unsigned int i;
3710
3711                 for (i = 0; i < rp->rbr_refill_pending; i++)
3712                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3713                 rp->rbr_refill_pending = 0;
3714         }
3715
3716         stat = (RX_DMA_CTL_STAT_MEX |
3717                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3718                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3719
3720         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3721
3722         /* Only sync discards stats when qlen indicate potential for drops */
3723         if (qlen > 10)
3724                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3725
3726         return work_done;
3727 }
3728
3729 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3730 {
3731         u64 v0 = lp->v0;
3732         u32 tx_vec = (v0 >> 32);
3733         u32 rx_vec = (v0 & 0xffffffff);
3734         int i, work_done = 0;
3735
3736         netif_printk(np, intr, KERN_DEBUG, np->dev,
3737                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3738
3739         for (i = 0; i < np->num_tx_rings; i++) {
3740                 struct tx_ring_info *rp = &np->tx_rings[i];
3741                 if (tx_vec & (1 << rp->tx_channel))
3742                         niu_tx_work(np, rp);
3743                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3744         }
3745
3746         for (i = 0; i < np->num_rx_rings; i++) {
3747                 struct rx_ring_info *rp = &np->rx_rings[i];
3748
3749                 if (rx_vec & (1 << rp->rx_channel)) {
3750                         int this_work_done;
3751
3752                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3753                                                      budget);
3754
3755                         budget -= this_work_done;
3756                         work_done += this_work_done;
3757                 }
3758                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3759         }
3760
3761         return work_done;
3762 }
3763
3764 static int niu_poll(struct napi_struct *napi, int budget)
3765 {
3766         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3767         struct niu *np = lp->np;
3768         int work_done;
3769
3770         work_done = niu_poll_core(np, lp, budget);
3771
3772         if (work_done < budget) {
3773                 napi_complete_done(napi, work_done);
3774                 niu_ldg_rearm(np, lp, 1);
3775         }
3776         return work_done;
3777 }
3778
3779 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3780                                   u64 stat)
3781 {
3782         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3783
3784         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3785                 pr_cont("RBR_TMOUT ");
3786         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3787                 pr_cont("RSP_CNT ");
3788         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3789                 pr_cont("BYTE_EN_BUS ");
3790         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3791                 pr_cont("RSP_DAT ");
3792         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3793                 pr_cont("RCR_ACK ");
3794         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3795                 pr_cont("RCR_SHA_PAR ");
3796         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3797                 pr_cont("RBR_PRE_PAR ");
3798         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3799                 pr_cont("CONFIG ");
3800         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3801                 pr_cont("RCRINCON ");
3802         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3803                 pr_cont("RCRFULL ");
3804         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3805                 pr_cont("RBRFULL ");
3806         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3807                 pr_cont("RBRLOGPAGE ");
3808         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3809                 pr_cont("CFIGLOGPAGE ");
3810         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3811                 pr_cont("DC_FIDO ");
3812
3813         pr_cont(")\n");
3814 }
3815
3816 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3817 {
3818         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3819         int err = 0;
3820
3821
3822         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3823                     RX_DMA_CTL_STAT_PORT_FATAL))
3824                 err = -EINVAL;
3825
3826         if (err) {
3827                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3828                            rp->rx_channel,
3829                            (unsigned long long) stat);
3830
3831                 niu_log_rxchan_errors(np, rp, stat);
3832         }
3833
3834         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3835              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3836
3837         return err;
3838 }
3839
3840 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3841                                   u64 cs)
3842 {
3843         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3844
3845         if (cs & TX_CS_MBOX_ERR)
3846                 pr_cont("MBOX ");
3847         if (cs & TX_CS_PKT_SIZE_ERR)
3848                 pr_cont("PKT_SIZE ");
3849         if (cs & TX_CS_TX_RING_OFLOW)
3850                 pr_cont("TX_RING_OFLOW ");
3851         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3852                 pr_cont("PREF_BUF_PAR ");
3853         if (cs & TX_CS_NACK_PREF)
3854                 pr_cont("NACK_PREF ");
3855         if (cs & TX_CS_NACK_PKT_RD)
3856                 pr_cont("NACK_PKT_RD ");
3857         if (cs & TX_CS_CONF_PART_ERR)
3858                 pr_cont("CONF_PART ");
3859         if (cs & TX_CS_PKT_PRT_ERR)
3860                 pr_cont("PKT_PTR ");
3861
3862         pr_cont(")\n");
3863 }
3864
3865 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3866 {
3867         u64 cs, logh, logl;
3868
3869         cs = nr64(TX_CS(rp->tx_channel));
3870         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3871         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3872
3873         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3874                    rp->tx_channel,
3875                    (unsigned long long)cs,
3876                    (unsigned long long)logh,
3877                    (unsigned long long)logl);
3878
3879         niu_log_txchan_errors(np, rp, cs);
3880
3881         return -ENODEV;
3882 }
3883
3884 static int niu_mif_interrupt(struct niu *np)
3885 {
3886         u64 mif_status = nr64(MIF_STATUS);
3887         int phy_mdint = 0;
3888
3889         if (np->flags & NIU_FLAGS_XMAC) {
3890                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3891
3892                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3893                         phy_mdint = 1;
3894         }
3895
3896         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3897                    (unsigned long long)mif_status, phy_mdint);
3898
3899         return -ENODEV;
3900 }
3901
3902 static void niu_xmac_interrupt(struct niu *np)
3903 {
3904         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3905         u64 val;
3906
3907         val = nr64_mac(XTXMAC_STATUS);
3908         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3909                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3910         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3911                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3912         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3913                 mp->tx_fifo_errors++;
3914         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3915                 mp->tx_overflow_errors++;
3916         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3917                 mp->tx_max_pkt_size_errors++;
3918         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3919                 mp->tx_underflow_errors++;
3920
3921         val = nr64_mac(XRXMAC_STATUS);
3922         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3923                 mp->rx_local_faults++;
3924         if (val & XRXMAC_STATUS_RFLT_DET)
3925                 mp->rx_remote_faults++;
3926         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3927                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3928         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3929                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3930         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3931                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3932         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3933                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3934         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3935                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3936         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3937                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3938         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3939                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3940         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3941                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3942         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3943                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3944         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3945                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3946         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3947                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3948         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3949                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3950         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3951                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3952         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3953                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3954         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3955                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3956         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3957                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3958         if (val & XRXMAC_STATUS_RXUFLOW)
3959                 mp->rx_underflows++;
3960         if (val & XRXMAC_STATUS_RXOFLOW)
3961                 mp->rx_overflows++;
3962
3963         val = nr64_mac(XMAC_FC_STAT);
3964         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3965                 mp->pause_off_state++;
3966         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3967                 mp->pause_on_state++;
3968         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3969                 mp->pause_received++;
3970 }
3971
3972 static void niu_bmac_interrupt(struct niu *np)
3973 {
3974         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3975         u64 val;
3976
3977         val = nr64_mac(BTXMAC_STATUS);
3978         if (val & BTXMAC_STATUS_UNDERRUN)
3979                 mp->tx_underflow_errors++;
3980         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3981                 mp->tx_max_pkt_size_errors++;
3982         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3983                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3984         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3985                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3986
3987         val = nr64_mac(BRXMAC_STATUS);
3988         if (val & BRXMAC_STATUS_OVERFLOW)
3989                 mp->rx_overflows++;
3990         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3991                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3992         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3993                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3994         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3995                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3996         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3997                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3998
3999         val = nr64_mac(BMAC_CTRL_STATUS);
4000         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4001                 mp->pause_off_state++;
4002         if (val & BMAC_CTRL_STATUS_PAUSE)
4003                 mp->pause_on_state++;
4004         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4005                 mp->pause_received++;
4006 }
4007
4008 static int niu_mac_interrupt(struct niu *np)
4009 {
4010         if (np->flags & NIU_FLAGS_XMAC)
4011                 niu_xmac_interrupt(np);
4012         else
4013                 niu_bmac_interrupt(np);
4014
4015         return 0;
4016 }
4017
4018 static void niu_log_device_error(struct niu *np, u64 stat)
4019 {
4020         netdev_err(np->dev, "Core device errors ( ");
4021
4022         if (stat & SYS_ERR_MASK_META2)
4023                 pr_cont("META2 ");
4024         if (stat & SYS_ERR_MASK_META1)
4025                 pr_cont("META1 ");
4026         if (stat & SYS_ERR_MASK_PEU)
4027                 pr_cont("PEU ");
4028         if (stat & SYS_ERR_MASK_TXC)
4029                 pr_cont("TXC ");
4030         if (stat & SYS_ERR_MASK_RDMC)
4031                 pr_cont("RDMC ");
4032         if (stat & SYS_ERR_MASK_TDMC)
4033                 pr_cont("TDMC ");
4034         if (stat & SYS_ERR_MASK_ZCP)
4035                 pr_cont("ZCP ");
4036         if (stat & SYS_ERR_MASK_FFLP)
4037                 pr_cont("FFLP ");
4038         if (stat & SYS_ERR_MASK_IPP)
4039                 pr_cont("IPP ");
4040         if (stat & SYS_ERR_MASK_MAC)
4041                 pr_cont("MAC ");
4042         if (stat & SYS_ERR_MASK_SMX)
4043                 pr_cont("SMX ");
4044
4045         pr_cont(")\n");
4046 }
4047
4048 static int niu_device_error(struct niu *np)
4049 {
4050         u64 stat = nr64(SYS_ERR_STAT);
4051
4052         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4053                    (unsigned long long)stat);
4054
4055         niu_log_device_error(np, stat);
4056
4057         return -ENODEV;
4058 }
4059
4060 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4061                               u64 v0, u64 v1, u64 v2)
4062 {
4063
4064         int i, err = 0;
4065
4066         lp->v0 = v0;
4067         lp->v1 = v1;
4068         lp->v2 = v2;
4069
4070         if (v1 & 0x00000000ffffffffULL) {
4071                 u32 rx_vec = (v1 & 0xffffffff);
4072
4073                 for (i = 0; i < np->num_rx_rings; i++) {
4074                         struct rx_ring_info *rp = &np->rx_rings[i];
4075
4076                         if (rx_vec & (1 << rp->rx_channel)) {
4077                                 int r = niu_rx_error(np, rp);
4078                                 if (r) {
4079                                         err = r;
4080                                 } else {
4081                                         if (!v0)
4082                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4083                                                      RX_DMA_CTL_STAT_MEX);
4084                                 }
4085                         }
4086                 }
4087         }
4088         if (v1 & 0x7fffffff00000000ULL) {
4089                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4090
4091                 for (i = 0; i < np->num_tx_rings; i++) {
4092                         struct tx_ring_info *rp = &np->tx_rings[i];
4093
4094                         if (tx_vec & (1 << rp->tx_channel)) {
4095                                 int r = niu_tx_error(np, rp);
4096                                 if (r)
4097                                         err = r;
4098                         }
4099                 }
4100         }
4101         if ((v0 | v1) & 0x8000000000000000ULL) {
4102                 int r = niu_mif_interrupt(np);
4103                 if (r)
4104                         err = r;
4105         }
4106         if (v2) {
4107                 if (v2 & 0x01ef) {
4108                         int r = niu_mac_interrupt(np);
4109                         if (r)
4110                                 err = r;
4111                 }
4112                 if (v2 & 0x0210) {
4113                         int r = niu_device_error(np);
4114                         if (r)
4115                                 err = r;
4116                 }
4117         }
4118
4119         if (err)
4120                 niu_enable_interrupts(np, 0);
4121
4122         return err;
4123 }
4124
4125 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4126                             int ldn)
4127 {
4128         struct rxdma_mailbox *mbox = rp->mbox;
4129         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4130
4131         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4132                       RX_DMA_CTL_STAT_RCRTO);
4133         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4134
4135         netif_printk(np, intr, KERN_DEBUG, np->dev,
4136                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4137 }
4138
4139 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4140                             int ldn)
4141 {
4142         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4143
4144         netif_printk(np, intr, KERN_DEBUG, np->dev,
4145                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4146 }
4147
4148 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4149 {
4150         struct niu_parent *parent = np->parent;
4151         u32 rx_vec, tx_vec;
4152         int i;
4153
4154         tx_vec = (v0 >> 32);
4155         rx_vec = (v0 & 0xffffffff);
4156
4157         for (i = 0; i < np->num_rx_rings; i++) {
4158                 struct rx_ring_info *rp = &np->rx_rings[i];
4159                 int ldn = LDN_RXDMA(rp->rx_channel);
4160
4161                 if (parent->ldg_map[ldn] != ldg)
4162                         continue;
4163
4164                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4165                 if (rx_vec & (1 << rp->rx_channel))
4166                         niu_rxchan_intr(np, rp, ldn);
4167         }
4168
4169         for (i = 0; i < np->num_tx_rings; i++) {
4170                 struct tx_ring_info *rp = &np->tx_rings[i];
4171                 int ldn = LDN_TXDMA(rp->tx_channel);
4172
4173                 if (parent->ldg_map[ldn] != ldg)
4174                         continue;
4175
4176                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4177                 if (tx_vec & (1 << rp->tx_channel))
4178                         niu_txchan_intr(np, rp, ldn);
4179         }
4180 }
4181
4182 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4183                               u64 v0, u64 v1, u64 v2)
4184 {
4185         if (likely(napi_schedule_prep(&lp->napi))) {
4186                 lp->v0 = v0;
4187                 lp->v1 = v1;
4188                 lp->v2 = v2;
4189                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4190                 __napi_schedule(&lp->napi);
4191         }
4192 }
4193
4194 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4195 {
4196         struct niu_ldg *lp = dev_id;
4197         struct niu *np = lp->np;
4198         int ldg = lp->ldg_num;
4199         unsigned long flags;
4200         u64 v0, v1, v2;
4201
4202         if (netif_msg_intr(np))
4203                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4204                        __func__, lp, ldg);
4205
4206         spin_lock_irqsave(&np->lock, flags);
4207
4208         v0 = nr64(LDSV0(ldg));
4209         v1 = nr64(LDSV1(ldg));
4210         v2 = nr64(LDSV2(ldg));
4211
4212         if (netif_msg_intr(np))
4213                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4214                        (unsigned long long) v0,
4215                        (unsigned long long) v1,
4216                        (unsigned long long) v2);
4217
4218         if (unlikely(!v0 && !v1 && !v2)) {
4219                 spin_unlock_irqrestore(&np->lock, flags);
4220                 return IRQ_NONE;
4221         }
4222
4223         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4224                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4225                 if (err)
4226                         goto out;
4227         }
4228         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4229                 niu_schedule_napi(np, lp, v0, v1, v2);
4230         else
4231                 niu_ldg_rearm(np, lp, 1);
4232 out:
4233         spin_unlock_irqrestore(&np->lock, flags);
4234
4235         return IRQ_HANDLED;
4236 }
4237
4238 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4239 {
4240         if (rp->mbox) {
4241                 np->ops->free_coherent(np->device,
4242                                        sizeof(struct rxdma_mailbox),
4243                                        rp->mbox, rp->mbox_dma);
4244                 rp->mbox = NULL;
4245         }
4246         if (rp->rcr) {
4247                 np->ops->free_coherent(np->device,
4248                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4249                                        rp->rcr, rp->rcr_dma);
4250                 rp->rcr = NULL;
4251                 rp->rcr_table_size = 0;
4252                 rp->rcr_index = 0;
4253         }
4254         if (rp->rbr) {
4255                 niu_rbr_free(np, rp);
4256
4257                 np->ops->free_coherent(np->device,
4258                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4259                                        rp->rbr, rp->rbr_dma);
4260                 rp->rbr = NULL;
4261                 rp->rbr_table_size = 0;
4262                 rp->rbr_index = 0;
4263         }
4264         kfree(rp->rxhash);
4265         rp->rxhash = NULL;
4266 }
4267
4268 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4269 {
4270         if (rp->mbox) {
4271                 np->ops->free_coherent(np->device,
4272                                        sizeof(struct txdma_mailbox),
4273                                        rp->mbox, rp->mbox_dma);
4274                 rp->mbox = NULL;
4275         }
4276         if (rp->descr) {
4277                 int i;
4278
4279                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4280                         if (rp->tx_buffs[i].skb)
4281                                 (void) release_tx_packet(np, rp, i);
4282                 }
4283
4284                 np->ops->free_coherent(np->device,
4285                                        MAX_TX_RING_SIZE * sizeof(__le64),
4286                                        rp->descr, rp->descr_dma);
4287                 rp->descr = NULL;
4288                 rp->pending = 0;
4289                 rp->prod = 0;
4290                 rp->cons = 0;
4291                 rp->wrap_bit = 0;
4292         }
4293 }
4294
4295 static void niu_free_channels(struct niu *np)
4296 {
4297         int i;
4298
4299         if (np->rx_rings) {
4300                 for (i = 0; i < np->num_rx_rings; i++) {
4301                         struct rx_ring_info *rp = &np->rx_rings[i];
4302
4303                         niu_free_rx_ring_info(np, rp);
4304                 }
4305                 kfree(np->rx_rings);
4306                 np->rx_rings = NULL;
4307                 np->num_rx_rings = 0;
4308         }
4309
4310         if (np->tx_rings) {
4311                 for (i = 0; i < np->num_tx_rings; i++) {
4312                         struct tx_ring_info *rp = &np->tx_rings[i];
4313
4314                         niu_free_tx_ring_info(np, rp);
4315                 }
4316                 kfree(np->tx_rings);
4317                 np->tx_rings = NULL;
4318                 np->num_tx_rings = 0;
4319         }
4320 }
4321
4322 static int niu_alloc_rx_ring_info(struct niu *np,
4323                                   struct rx_ring_info *rp)
4324 {
4325         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4326
4327         rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *),
4328                              GFP_KERNEL);
4329         if (!rp->rxhash)
4330                 return -ENOMEM;
4331
4332         rp->mbox = np->ops->alloc_coherent(np->device,
4333                                            sizeof(struct rxdma_mailbox),
4334                                            &rp->mbox_dma, GFP_KERNEL);
4335         if (!rp->mbox)
4336                 return -ENOMEM;
4337         if ((unsigned long)rp->mbox & (64UL - 1)) {
4338                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4339                            rp->mbox);
4340                 return -EINVAL;
4341         }
4342
4343         rp->rcr = np->ops->alloc_coherent(np->device,
4344                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4345                                           &rp->rcr_dma, GFP_KERNEL);
4346         if (!rp->rcr)
4347                 return -ENOMEM;
4348         if ((unsigned long)rp->rcr & (64UL - 1)) {
4349                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4350                            rp->rcr);
4351                 return -EINVAL;
4352         }
4353         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4354         rp->rcr_index = 0;
4355
4356         rp->rbr = np->ops->alloc_coherent(np->device,
4357                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4358                                           &rp->rbr_dma, GFP_KERNEL);
4359         if (!rp->rbr)
4360                 return -ENOMEM;
4361         if ((unsigned long)rp->rbr & (64UL - 1)) {
4362                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4363                            rp->rbr);
4364                 return -EINVAL;
4365         }
4366         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4367         rp->rbr_index = 0;
4368         rp->rbr_pending = 0;
4369
4370         return 0;
4371 }
4372
4373 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4374 {
4375         int mtu = np->dev->mtu;
4376
4377         /* These values are recommended by the HW designers for fair
4378          * utilization of DRR amongst the rings.
4379          */
4380         rp->max_burst = mtu + 32;
4381         if (rp->max_burst > 4096)
4382                 rp->max_burst = 4096;
4383 }
4384
4385 static int niu_alloc_tx_ring_info(struct niu *np,
4386                                   struct tx_ring_info *rp)
4387 {
4388         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4389
4390         rp->mbox = np->ops->alloc_coherent(np->device,
4391                                            sizeof(struct txdma_mailbox),
4392                                            &rp->mbox_dma, GFP_KERNEL);
4393         if (!rp->mbox)
4394                 return -ENOMEM;
4395         if ((unsigned long)rp->mbox & (64UL - 1)) {
4396                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4397                            rp->mbox);
4398                 return -EINVAL;
4399         }
4400
4401         rp->descr = np->ops->alloc_coherent(np->device,
4402                                             MAX_TX_RING_SIZE * sizeof(__le64),
4403                                             &rp->descr_dma, GFP_KERNEL);
4404         if (!rp->descr)
4405                 return -ENOMEM;
4406         if ((unsigned long)rp->descr & (64UL - 1)) {
4407                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4408                            rp->descr);
4409                 return -EINVAL;
4410         }
4411
4412         rp->pending = MAX_TX_RING_SIZE;
4413         rp->prod = 0;
4414         rp->cons = 0;
4415         rp->wrap_bit = 0;
4416
4417         /* XXX make these configurable... XXX */
4418         rp->mark_freq = rp->pending / 4;
4419
4420         niu_set_max_burst(np, rp);
4421
4422         return 0;
4423 }
4424
4425 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4426 {
4427         u16 bss;
4428
4429         bss = min(PAGE_SHIFT, 15);
4430
4431         rp->rbr_block_size = 1 << bss;
4432         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4433
4434         rp->rbr_sizes[0] = 256;
4435         rp->rbr_sizes[1] = 1024;
4436         if (np->dev->mtu > ETH_DATA_LEN) {
4437                 switch (PAGE_SIZE) {
4438                 case 4 * 1024:
4439                         rp->rbr_sizes[2] = 4096;
4440                         break;
4441
4442                 default:
4443                         rp->rbr_sizes[2] = 8192;
4444                         break;
4445                 }
4446         } else {
4447                 rp->rbr_sizes[2] = 2048;
4448         }
4449         rp->rbr_sizes[3] = rp->rbr_block_size;
4450 }
4451
4452 static int niu_alloc_channels(struct niu *np)
4453 {
4454         struct niu_parent *parent = np->parent;
4455         int first_rx_channel, first_tx_channel;
4456         int num_rx_rings, num_tx_rings;
4457         struct rx_ring_info *rx_rings;
4458         struct tx_ring_info *tx_rings;
4459         int i, port, err;
4460
4461         port = np->port;
4462         first_rx_channel = first_tx_channel = 0;
4463         for (i = 0; i < port; i++) {
4464                 first_rx_channel += parent->rxchan_per_port[i];
4465                 first_tx_channel += parent->txchan_per_port[i];
4466         }
4467
4468         num_rx_rings = parent->rxchan_per_port[port];
4469         num_tx_rings = parent->txchan_per_port[port];
4470
4471         rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4472                            GFP_KERNEL);
4473         err = -ENOMEM;
4474         if (!rx_rings)
4475                 goto out_err;
4476
4477         np->num_rx_rings = num_rx_rings;
4478         smp_wmb();
4479         np->rx_rings = rx_rings;
4480
4481         netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4482
4483         for (i = 0; i < np->num_rx_rings; i++) {
4484                 struct rx_ring_info *rp = &np->rx_rings[i];
4485
4486                 rp->np = np;
4487                 rp->rx_channel = first_rx_channel + i;
4488
4489                 err = niu_alloc_rx_ring_info(np, rp);
4490                 if (err)
4491                         goto out_err;
4492
4493                 niu_size_rbr(np, rp);
4494
4495                 /* XXX better defaults, configurable, etc... XXX */
4496                 rp->nonsyn_window = 64;
4497                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4498                 rp->syn_window = 64;
4499                 rp->syn_threshold = rp->rcr_table_size - 64;
4500                 rp->rcr_pkt_threshold = 16;
4501                 rp->rcr_timeout = 8;
4502                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4503                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4504                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4505
4506                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4507                 if (err)
4508                         return err;
4509         }
4510
4511         tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4512                            GFP_KERNEL);
4513         err = -ENOMEM;
4514         if (!tx_rings)
4515                 goto out_err;
4516
4517         np->num_tx_rings = num_tx_rings;
4518         smp_wmb();
4519         np->tx_rings = tx_rings;
4520
4521         netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4522
4523         for (i = 0; i < np->num_tx_rings; i++) {
4524                 struct tx_ring_info *rp = &np->tx_rings[i];
4525
4526                 rp->np = np;
4527                 rp->tx_channel = first_tx_channel + i;
4528
4529                 err = niu_alloc_tx_ring_info(np, rp);
4530                 if (err)
4531                         goto out_err;
4532         }
4533
4534         return 0;
4535
4536 out_err:
4537         niu_free_channels(np);
4538         return err;
4539 }
4540
4541 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4542 {
4543         int limit = 1000;
4544
4545         while (--limit > 0) {
4546                 u64 val = nr64(TX_CS(channel));
4547                 if (val & TX_CS_SNG_STATE)
4548                         return 0;
4549         }
4550         return -ENODEV;
4551 }
4552
4553 static int niu_tx_channel_stop(struct niu *np, int channel)
4554 {
4555         u64 val = nr64(TX_CS(channel));
4556
4557         val |= TX_CS_STOP_N_GO;
4558         nw64(TX_CS(channel), val);
4559
4560         return niu_tx_cs_sng_poll(np, channel);
4561 }
4562
4563 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4564 {
4565         int limit = 1000;
4566
4567         while (--limit > 0) {
4568                 u64 val = nr64(TX_CS(channel));
4569                 if (!(val & TX_CS_RST))
4570                         return 0;
4571         }
4572         return -ENODEV;
4573 }
4574
4575 static int niu_tx_channel_reset(struct niu *np, int channel)
4576 {
4577         u64 val = nr64(TX_CS(channel));
4578         int err;
4579
4580         val |= TX_CS_RST;
4581         nw64(TX_CS(channel), val);
4582
4583         err = niu_tx_cs_reset_poll(np, channel);
4584         if (!err)
4585                 nw64(TX_RING_KICK(channel), 0);
4586
4587         return err;
4588 }
4589
4590 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4591 {
4592         u64 val;
4593
4594         nw64(TX_LOG_MASK1(channel), 0);
4595         nw64(TX_LOG_VAL1(channel), 0);
4596         nw64(TX_LOG_MASK2(channel), 0);
4597         nw64(TX_LOG_VAL2(channel), 0);
4598         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4599         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4600         nw64(TX_LOG_PAGE_HDL(channel), 0);
4601
4602         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4603         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4604         nw64(TX_LOG_PAGE_VLD(channel), val);
4605
4606         /* XXX TXDMA 32bit mode? XXX */
4607
4608         return 0;
4609 }
4610
4611 static void niu_txc_enable_port(struct niu *np, int on)
4612 {
4613         unsigned long flags;
4614         u64 val, mask;
4615
4616         niu_lock_parent(np, flags);
4617         val = nr64(TXC_CONTROL);
4618         mask = (u64)1 << np->port;
4619         if (on) {
4620                 val |= TXC_CONTROL_ENABLE | mask;
4621         } else {
4622                 val &= ~mask;
4623                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4624                         val &= ~TXC_CONTROL_ENABLE;
4625         }
4626         nw64(TXC_CONTROL, val);
4627         niu_unlock_parent(np, flags);
4628 }
4629
4630 static void niu_txc_set_imask(struct niu *np, u64 imask)
4631 {
4632         unsigned long flags;
4633         u64 val;
4634
4635         niu_lock_parent(np, flags);
4636         val = nr64(TXC_INT_MASK);
4637         val &= ~TXC_INT_MASK_VAL(np->port);
4638         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4639         niu_unlock_parent(np, flags);
4640 }
4641
4642 static void niu_txc_port_dma_enable(struct niu *np, int on)
4643 {
4644         u64 val = 0;
4645
4646         if (on) {
4647                 int i;
4648
4649                 for (i = 0; i < np->num_tx_rings; i++)
4650                         val |= (1 << np->tx_rings[i].tx_channel);
4651         }
4652         nw64(TXC_PORT_DMA(np->port), val);
4653 }
4654
4655 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4656 {
4657         int err, channel = rp->tx_channel;
4658         u64 val, ring_len;
4659
4660         err = niu_tx_channel_stop(np, channel);
4661         if (err)
4662                 return err;
4663
4664         err = niu_tx_channel_reset(np, channel);
4665         if (err)
4666                 return err;
4667
4668         err = niu_tx_channel_lpage_init(np, channel);
4669         if (err)
4670                 return err;
4671
4672         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4673         nw64(TX_ENT_MSK(channel), 0);
4674
4675         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4676                               TX_RNG_CFIG_STADDR)) {
4677                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4678                            channel, (unsigned long long)rp->descr_dma);
4679                 return -EINVAL;
4680         }
4681
4682         /* The length field in TX_RNG_CFIG is measured in 64-byte
4683          * blocks.  rp->pending is the number of TX descriptors in
4684          * our ring, 8 bytes each, thus we divide by 8 bytes more
4685          * to get the proper value the chip wants.
4686          */
4687         ring_len = (rp->pending / 8);
4688
4689         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4690                rp->descr_dma);
4691         nw64(TX_RNG_CFIG(channel), val);
4692
4693         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4694             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4695                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4696                             channel, (unsigned long long)rp->mbox_dma);
4697                 return -EINVAL;
4698         }
4699         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4700         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4701
4702         nw64(TX_CS(channel), 0);
4703
4704         rp->last_pkt_cnt = 0;
4705
4706         return 0;
4707 }
4708
4709 static void niu_init_rdc_groups(struct niu *np)
4710 {
4711         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4712         int i, first_table_num = tp->first_table_num;
4713
4714         for (i = 0; i < tp->num_tables; i++) {
4715                 struct rdc_table *tbl = &tp->tables[i];
4716                 int this_table = first_table_num + i;
4717                 int slot;
4718
4719                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4720                         nw64(RDC_TBL(this_table, slot),
4721                              tbl->rxdma_channel[slot]);
4722         }
4723
4724         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4725 }
4726
4727 static void niu_init_drr_weight(struct niu *np)
4728 {
4729         int type = phy_decode(np->parent->port_phy, np->port);
4730         u64 val;
4731
4732         switch (type) {
4733         case PORT_TYPE_10G:
4734                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4735                 break;
4736
4737         case PORT_TYPE_1G:
4738         default:
4739                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4740                 break;
4741         }
4742         nw64(PT_DRR_WT(np->port), val);
4743 }
4744
4745 static int niu_init_hostinfo(struct niu *np)
4746 {
4747         struct niu_parent *parent = np->parent;
4748         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4749         int i, err, num_alt = niu_num_alt_addr(np);
4750         int first_rdc_table = tp->first_table_num;
4751
4752         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4753         if (err)
4754                 return err;
4755
4756         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4757         if (err)
4758                 return err;
4759
4760         for (i = 0; i < num_alt; i++) {
4761                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4762                 if (err)
4763                         return err;
4764         }
4765
4766         return 0;
4767 }
4768
4769 static int niu_rx_channel_reset(struct niu *np, int channel)
4770 {
4771         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4772                                       RXDMA_CFIG1_RST, 1000, 10,
4773                                       "RXDMA_CFIG1");
4774 }
4775
4776 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4777 {
4778         u64 val;
4779
4780         nw64(RX_LOG_MASK1(channel), 0);
4781         nw64(RX_LOG_VAL1(channel), 0);
4782         nw64(RX_LOG_MASK2(channel), 0);
4783         nw64(RX_LOG_VAL2(channel), 0);
4784         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4785         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4786         nw64(RX_LOG_PAGE_HDL(channel), 0);
4787
4788         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4789         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4790         nw64(RX_LOG_PAGE_VLD(channel), val);
4791
4792         return 0;
4793 }
4794
4795 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4796 {
4797         u64 val;
4798
4799         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4800                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4801                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4802                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4803         nw64(RDC_RED_PARA(rp->rx_channel), val);
4804 }
4805
4806 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4807 {
4808         u64 val = 0;
4809
4810         *ret = 0;
4811         switch (rp->rbr_block_size) {
4812         case 4 * 1024:
4813                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4814                 break;
4815         case 8 * 1024:
4816                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4817                 break;
4818         case 16 * 1024:
4819                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4820                 break;
4821         case 32 * 1024:
4822                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4823                 break;
4824         default:
4825                 return -EINVAL;
4826         }
4827         val |= RBR_CFIG_B_VLD2;
4828         switch (rp->rbr_sizes[2]) {
4829         case 2 * 1024:
4830                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4831                 break;
4832         case 4 * 1024:
4833                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4834                 break;
4835         case 8 * 1024:
4836                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4837                 break;
4838         case 16 * 1024:
4839                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4840                 break;
4841
4842         default:
4843                 return -EINVAL;
4844         }
4845         val |= RBR_CFIG_B_VLD1;
4846         switch (rp->rbr_sizes[1]) {
4847         case 1 * 1024:
4848                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4849                 break;
4850         case 2 * 1024:
4851                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4852                 break;
4853         case 4 * 1024:
4854                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4855                 break;
4856         case 8 * 1024:
4857                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4858                 break;
4859
4860         default:
4861                 return -EINVAL;
4862         }
4863         val |= RBR_CFIG_B_VLD0;
4864         switch (rp->rbr_sizes[0]) {
4865         case 256:
4866                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4867                 break;
4868         case 512:
4869                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4870                 break;
4871         case 1 * 1024:
4872                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4873                 break;
4874         case 2 * 1024:
4875                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4876                 break;
4877
4878         default:
4879                 return -EINVAL;
4880         }
4881
4882         *ret = val;
4883         return 0;
4884 }
4885
4886 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4887 {
4888         u64 val = nr64(RXDMA_CFIG1(channel));
4889         int limit;
4890
4891         if (on)
4892                 val |= RXDMA_CFIG1_EN;
4893         else
4894                 val &= ~RXDMA_CFIG1_EN;
4895         nw64(RXDMA_CFIG1(channel), val);
4896
4897         limit = 1000;
4898         while (--limit > 0) {
4899                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4900                         break;
4901                 udelay(10);
4902         }
4903         if (limit <= 0)
4904                 return -ENODEV;
4905         return 0;
4906 }
4907
4908 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4909 {
4910         int err, channel = rp->rx_channel;
4911         u64 val;
4912
4913         err = niu_rx_channel_reset(np, channel);
4914         if (err)
4915                 return err;
4916
4917         err = niu_rx_channel_lpage_init(np, channel);
4918         if (err)
4919                 return err;
4920
4921         niu_rx_channel_wred_init(np, rp);
4922
4923         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4924         nw64(RX_DMA_CTL_STAT(channel),
4925              (RX_DMA_CTL_STAT_MEX |
4926               RX_DMA_CTL_STAT_RCRTHRES |
4927               RX_DMA_CTL_STAT_RCRTO |
4928               RX_DMA_CTL_STAT_RBR_EMPTY));
4929         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4930         nw64(RXDMA_CFIG2(channel),
4931              ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4932               RXDMA_CFIG2_FULL_HDR));
4933         nw64(RBR_CFIG_A(channel),
4934              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4935              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4936         err = niu_compute_rbr_cfig_b(rp, &val);
4937         if (err)
4938                 return err;
4939         nw64(RBR_CFIG_B(channel), val);
4940         nw64(RCRCFIG_A(channel),
4941              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4942              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4943         nw64(RCRCFIG_B(channel),
4944              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4945              RCRCFIG_B_ENTOUT |
4946              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4947
4948         err = niu_enable_rx_channel(np, channel, 1);
4949         if (err)
4950                 return err;
4951
4952         nw64(RBR_KICK(channel), rp->rbr_index);
4953
4954         val = nr64(RX_DMA_CTL_STAT(channel));
4955         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4956         nw64(RX_DMA_CTL_STAT(channel), val);
4957
4958         return 0;
4959 }
4960
4961 static int niu_init_rx_channels(struct niu *np)
4962 {
4963         unsigned long flags;
4964         u64 seed = jiffies_64;
4965         int err, i;
4966
4967         niu_lock_parent(np, flags);
4968         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4969         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4970         niu_unlock_parent(np, flags);
4971
4972         /* XXX RXDMA 32bit mode? XXX */
4973
4974         niu_init_rdc_groups(np);
4975         niu_init_drr_weight(np);
4976
4977         err = niu_init_hostinfo(np);
4978         if (err)
4979                 return err;
4980
4981         for (i = 0; i < np->num_rx_rings; i++) {
4982                 struct rx_ring_info *rp = &np->rx_rings[i];
4983
4984                 err = niu_init_one_rx_channel(np, rp);
4985                 if (err)
4986                         return err;
4987         }
4988
4989         return 0;
4990 }
4991
4992 static int niu_set_ip_frag_rule(struct niu *np)
4993 {
4994         struct niu_parent *parent = np->parent;
4995         struct niu_classifier *cp = &np->clas;
4996         struct niu_tcam_entry *tp;
4997         int index, err;
4998
4999         index = cp->tcam_top;
5000         tp = &parent->tcam[index];
5001
5002         /* Note that the noport bit is the same in both ipv4 and
5003          * ipv6 format TCAM entries.
5004          */
5005         memset(tp, 0, sizeof(*tp));
5006         tp->key[1] = TCAM_V4KEY1_NOPORT;
5007         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5008         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5009                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5010         err = tcam_write(np, index, tp->key, tp->key_mask);
5011         if (err)
5012                 return err;
5013         err = tcam_assoc_write(np, index, tp->assoc_data);
5014         if (err)
5015                 return err;
5016         tp->valid = 1;
5017         cp->tcam_valid_entries++;
5018
5019         return 0;
5020 }
5021
5022 static int niu_init_classifier_hw(struct niu *np)
5023 {
5024         struct niu_parent *parent = np->parent;
5025         struct niu_classifier *cp = &np->clas;
5026         int i, err;
5027
5028         nw64(H1POLY, cp->h1_init);
5029         nw64(H2POLY, cp->h2_init);
5030
5031         err = niu_init_hostinfo(np);
5032         if (err)
5033                 return err;
5034
5035         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5036                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5037
5038                 vlan_tbl_write(np, i, np->port,
5039                                vp->vlan_pref, vp->rdc_num);
5040         }
5041
5042         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5043                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5044
5045                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5046                                                 ap->rdc_num, ap->mac_pref);
5047                 if (err)
5048                         return err;
5049         }
5050
5051         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5052                 int index = i - CLASS_CODE_USER_PROG1;
5053
5054                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5055                 if (err)
5056                         return err;
5057                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5058                 if (err)
5059                         return err;
5060         }
5061
5062         err = niu_set_ip_frag_rule(np);
5063         if (err)
5064                 return err;
5065
5066         tcam_enable(np, 1);
5067
5068         return 0;
5069 }
5070
5071 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5072 {
5073         nw64(ZCP_RAM_DATA0, data[0]);
5074         nw64(ZCP_RAM_DATA1, data[1]);
5075         nw64(ZCP_RAM_DATA2, data[2]);
5076         nw64(ZCP_RAM_DATA3, data[3]);
5077         nw64(ZCP_RAM_DATA4, data[4]);
5078         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5079         nw64(ZCP_RAM_ACC,
5080              (ZCP_RAM_ACC_WRITE |
5081               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5082               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5083
5084         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5085                                    1000, 100);
5086 }
5087
5088 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5089 {
5090         int err;
5091
5092         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5093                                   1000, 100);
5094         if (err) {
5095                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5096                            (unsigned long long)nr64(ZCP_RAM_ACC));
5097                 return err;
5098         }
5099
5100         nw64(ZCP_RAM_ACC,
5101              (ZCP_RAM_ACC_READ |
5102               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5103               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5104
5105         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5106                                   1000, 100);
5107         if (err) {
5108                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5109                            (unsigned long long)nr64(ZCP_RAM_ACC));
5110                 return err;
5111         }
5112
5113         data[0] = nr64(ZCP_RAM_DATA0);
5114         data[1] = nr64(ZCP_RAM_DATA1);
5115         data[2] = nr64(ZCP_RAM_DATA2);
5116         data[3] = nr64(ZCP_RAM_DATA3);
5117         data[4] = nr64(ZCP_RAM_DATA4);
5118
5119         return 0;
5120 }
5121
5122 static void niu_zcp_cfifo_reset(struct niu *np)
5123 {
5124         u64 val = nr64(RESET_CFIFO);
5125
5126         val |= RESET_CFIFO_RST(np->port);
5127         nw64(RESET_CFIFO, val);
5128         udelay(10);
5129
5130         val &= ~RESET_CFIFO_RST(np->port);
5131         nw64(RESET_CFIFO, val);
5132 }
5133
5134 static int niu_init_zcp(struct niu *np)
5135 {
5136         u64 data[5], rbuf[5];
5137         int i, max, err;
5138
5139         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5140                 if (np->port == 0 || np->port == 1)
5141                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5142                 else
5143                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5144         } else
5145                 max = NIU_CFIFO_ENTRIES;
5146
5147         data[0] = 0;
5148         data[1] = 0;
5149         data[2] = 0;
5150         data[3] = 0;
5151         data[4] = 0;
5152
5153         for (i = 0; i < max; i++) {
5154                 err = niu_zcp_write(np, i, data);
5155                 if (err)
5156                         return err;
5157                 err = niu_zcp_read(np, i, rbuf);
5158                 if (err)
5159                         return err;
5160         }
5161
5162         niu_zcp_cfifo_reset(np);
5163         nw64(CFIFO_ECC(np->port), 0);
5164         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5165         (void) nr64(ZCP_INT_STAT);
5166         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5167
5168         return 0;
5169 }
5170
5171 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5172 {
5173         u64 val = nr64_ipp(IPP_CFIG);
5174
5175         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5176         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5177         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5178         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5179         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5180         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5181         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5182         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5183 }
5184
5185 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5186 {
5187         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5188         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5189         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5190         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5191         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5192         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5193 }
5194
5195 static int niu_ipp_reset(struct niu *np)
5196 {
5197         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5198                                           1000, 100, "IPP_CFIG");
5199 }
5200
5201 static int niu_init_ipp(struct niu *np)
5202 {
5203         u64 data[5], rbuf[5], val;
5204         int i, max, err;
5205
5206         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5207                 if (np->port == 0 || np->port == 1)
5208                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5209                 else
5210                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5211         } else
5212                 max = NIU_DFIFO_ENTRIES;
5213
5214         data[0] = 0;
5215         data[1] = 0;
5216         data[2] = 0;
5217         data[3] = 0;
5218         data[4] = 0;
5219
5220         for (i = 0; i < max; i++) {
5221                 niu_ipp_write(np, i, data);
5222                 niu_ipp_read(np, i, rbuf);
5223         }
5224
5225         (void) nr64_ipp(IPP_INT_STAT);
5226         (void) nr64_ipp(IPP_INT_STAT);
5227
5228         err = niu_ipp_reset(np);
5229         if (err)
5230                 return err;
5231
5232         (void) nr64_ipp(IPP_PKT_DIS);
5233         (void) nr64_ipp(IPP_BAD_CS_CNT);
5234         (void) nr64_ipp(IPP_ECC);
5235
5236         (void) nr64_ipp(IPP_INT_STAT);
5237
5238         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5239
5240         val = nr64_ipp(IPP_CFIG);
5241         val &= ~IPP_CFIG_IP_MAX_PKT;
5242         val |= (IPP_CFIG_IPP_ENABLE |
5243                 IPP_CFIG_DFIFO_ECC_EN |
5244                 IPP_CFIG_DROP_BAD_CRC |
5245                 IPP_CFIG_CKSUM_EN |
5246                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5247         nw64_ipp(IPP_CFIG, val);
5248
5249         return 0;
5250 }
5251
5252 static void niu_handle_led(struct niu *np, int status)
5253 {
5254         u64 val;
5255         val = nr64_mac(XMAC_CONFIG);
5256
5257         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5258             (np->flags & NIU_FLAGS_FIBER) != 0) {
5259                 if (status) {
5260                         val |= XMAC_CONFIG_LED_POLARITY;
5261                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5262                 } else {
5263                         val |= XMAC_CONFIG_FORCE_LED_ON;
5264                         val &= ~XMAC_CONFIG_LED_POLARITY;
5265                 }
5266         }
5267
5268         nw64_mac(XMAC_CONFIG, val);
5269 }
5270
5271 static void niu_init_xif_xmac(struct niu *np)
5272 {
5273         struct niu_link_config *lp = &np->link_config;
5274         u64 val;
5275
5276         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5277                 val = nr64(MIF_CONFIG);
5278                 val |= MIF_CONFIG_ATCA_GE;
5279                 nw64(MIF_CONFIG, val);
5280         }
5281
5282         val = nr64_mac(XMAC_CONFIG);
5283         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5284
5285         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5286
5287         if (lp->loopback_mode == LOOPBACK_MAC) {
5288                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5289                 val |= XMAC_CONFIG_LOOPBACK;
5290         } else {
5291                 val &= ~XMAC_CONFIG_LOOPBACK;
5292         }
5293
5294         if (np->flags & NIU_FLAGS_10G) {
5295                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5296         } else {
5297                 val |= XMAC_CONFIG_LFS_DISABLE;
5298                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5299                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5300                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5301                 else
5302                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5303         }
5304
5305         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5306
5307         if (lp->active_speed == SPEED_100)
5308                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5309         else
5310                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5311
5312         nw64_mac(XMAC_CONFIG, val);
5313
5314         val = nr64_mac(XMAC_CONFIG);
5315         val &= ~XMAC_CONFIG_MODE_MASK;
5316         if (np->flags & NIU_FLAGS_10G) {
5317                 val |= XMAC_CONFIG_MODE_XGMII;
5318         } else {
5319                 if (lp->active_speed == SPEED_1000)
5320                         val |= XMAC_CONFIG_MODE_GMII;
5321                 else
5322                         val |= XMAC_CONFIG_MODE_MII;
5323         }
5324
5325         nw64_mac(XMAC_CONFIG, val);
5326 }
5327
5328 static void niu_init_xif_bmac(struct niu *np)
5329 {
5330         struct niu_link_config *lp = &np->link_config;
5331         u64 val;
5332
5333         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5334
5335         if (lp->loopback_mode == LOOPBACK_MAC)
5336                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5337         else
5338                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5339
5340         if (lp->active_speed == SPEED_1000)
5341                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5342         else
5343                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5344
5345         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5346                  BMAC_XIF_CONFIG_LED_POLARITY);
5347
5348         if (!(np->flags & NIU_FLAGS_10G) &&
5349             !(np->flags & NIU_FLAGS_FIBER) &&
5350             lp->active_speed == SPEED_100)
5351                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5352         else
5353                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5354
5355         nw64_mac(BMAC_XIF_CONFIG, val);
5356 }
5357
5358 static void niu_init_xif(struct niu *np)
5359 {
5360         if (np->flags & NIU_FLAGS_XMAC)
5361                 niu_init_xif_xmac(np);
5362         else
5363                 niu_init_xif_bmac(np);
5364 }
5365
5366 static void niu_pcs_mii_reset(struct niu *np)
5367 {
5368         int limit = 1000;
5369         u64 val = nr64_pcs(PCS_MII_CTL);
5370         val |= PCS_MII_CTL_RST;
5371         nw64_pcs(PCS_MII_CTL, val);
5372         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5373                 udelay(100);
5374                 val = nr64_pcs(PCS_MII_CTL);
5375         }
5376 }
5377
5378 static void niu_xpcs_reset(struct niu *np)
5379 {
5380         int limit = 1000;
5381         u64 val = nr64_xpcs(XPCS_CONTROL1);
5382         val |= XPCS_CONTROL1_RESET;
5383         nw64_xpcs(XPCS_CONTROL1, val);
5384         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5385                 udelay(100);
5386                 val = nr64_xpcs(XPCS_CONTROL1);
5387         }
5388 }
5389
5390 static int niu_init_pcs(struct niu *np)
5391 {
5392         struct niu_link_config *lp = &np->link_config;
5393         u64 val;
5394
5395         switch (np->flags & (NIU_FLAGS_10G |
5396                              NIU_FLAGS_FIBER |
5397                              NIU_FLAGS_XCVR_SERDES)) {
5398         case NIU_FLAGS_FIBER:
5399                 /* 1G fiber */
5400                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5401                 nw64_pcs(PCS_DPATH_MODE, 0);
5402                 niu_pcs_mii_reset(np);
5403                 break;
5404
5405         case NIU_FLAGS_10G:
5406         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5407         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5408                 /* 10G SERDES */
5409                 if (!(np->flags & NIU_FLAGS_XMAC))
5410                         return -EINVAL;
5411
5412                 /* 10G copper or fiber */
5413                 val = nr64_mac(XMAC_CONFIG);
5414                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5415                 nw64_mac(XMAC_CONFIG, val);
5416
5417                 niu_xpcs_reset(np);
5418
5419                 val = nr64_xpcs(XPCS_CONTROL1);
5420                 if (lp->loopback_mode == LOOPBACK_PHY)
5421                         val |= XPCS_CONTROL1_LOOPBACK;
5422                 else
5423                         val &= ~XPCS_CONTROL1_LOOPBACK;
5424                 nw64_xpcs(XPCS_CONTROL1, val);
5425
5426                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5427                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5428                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5429                 break;
5430
5431
5432         case NIU_FLAGS_XCVR_SERDES:
5433                 /* 1G SERDES */
5434                 niu_pcs_mii_reset(np);
5435                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5436                 nw64_pcs(PCS_DPATH_MODE, 0);
5437                 break;
5438
5439         case 0:
5440                 /* 1G copper */
5441         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5442                 /* 1G RGMII FIBER */
5443                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5444                 niu_pcs_mii_reset(np);
5445                 break;
5446
5447         default:
5448                 return -EINVAL;
5449         }
5450
5451         return 0;
5452 }
5453
5454 static int niu_reset_tx_xmac(struct niu *np)
5455 {
5456         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5457                                           (XTXMAC_SW_RST_REG_RS |
5458                                            XTXMAC_SW_RST_SOFT_RST),
5459                                           1000, 100, "XTXMAC_SW_RST");
5460 }
5461
5462 static int niu_reset_tx_bmac(struct niu *np)
5463 {
5464         int limit;
5465
5466         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5467         limit = 1000;
5468         while (--limit >= 0) {
5469                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5470                         break;
5471                 udelay(100);
5472         }
5473         if (limit < 0) {
5474                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5475                         np->port,
5476                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5477                 return -ENODEV;
5478         }
5479
5480         return 0;
5481 }
5482
5483 static int niu_reset_tx_mac(struct niu *np)
5484 {
5485         if (np->flags & NIU_FLAGS_XMAC)
5486                 return niu_reset_tx_xmac(np);
5487         else
5488                 return niu_reset_tx_bmac(np);
5489 }
5490
5491 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5492 {
5493         u64 val;
5494
5495         val = nr64_mac(XMAC_MIN);
5496         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5497                  XMAC_MIN_RX_MIN_PKT_SIZE);
5498         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5499         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5500         nw64_mac(XMAC_MIN, val);
5501
5502         nw64_mac(XMAC_MAX, max);
5503
5504         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5505
5506         val = nr64_mac(XMAC_IPG);
5507         if (np->flags & NIU_FLAGS_10G) {
5508                 val &= ~XMAC_IPG_IPG_XGMII;
5509                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5510         } else {
5511                 val &= ~XMAC_IPG_IPG_MII_GMII;
5512                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5513         }
5514         nw64_mac(XMAC_IPG, val);
5515
5516         val = nr64_mac(XMAC_CONFIG);
5517         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5518                  XMAC_CONFIG_STRETCH_MODE |
5519                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5520                  XMAC_CONFIG_TX_ENABLE);
5521         nw64_mac(XMAC_CONFIG, val);
5522
5523         nw64_mac(TXMAC_FRM_CNT, 0);
5524         nw64_mac(TXMAC_BYTE_CNT, 0);
5525 }
5526
5527 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5528 {
5529         u64 val;
5530
5531         nw64_mac(BMAC_MIN_FRAME, min);
5532         nw64_mac(BMAC_MAX_FRAME, max);
5533
5534         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5535         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5536         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5537
5538         val = nr64_mac(BTXMAC_CONFIG);
5539         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5540                  BTXMAC_CONFIG_ENABLE);
5541         nw64_mac(BTXMAC_CONFIG, val);
5542 }
5543
5544 static void niu_init_tx_mac(struct niu *np)
5545 {
5546         u64 min, max;
5547
5548         min = 64;
5549         if (np->dev->mtu > ETH_DATA_LEN)
5550                 max = 9216;
5551         else
5552                 max = 1522;
5553
5554         /* The XMAC_MIN register only accepts values for TX min which
5555          * have the low 3 bits cleared.
5556          */
5557         BUG_ON(min & 0x7);
5558
5559         if (np->flags & NIU_FLAGS_XMAC)
5560                 niu_init_tx_xmac(np, min, max);
5561         else
5562                 niu_init_tx_bmac(np, min, max);
5563 }
5564
5565 static int niu_reset_rx_xmac(struct niu *np)
5566 {
5567         int limit;
5568
5569         nw64_mac(XRXMAC_SW_RST,
5570                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5571         limit = 1000;
5572         while (--limit >= 0) {
5573                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5574                                                  XRXMAC_SW_RST_SOFT_RST)))
5575                         break;
5576                 udelay(100);
5577         }
5578         if (limit < 0) {
5579                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5580                         np->port,
5581                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5582                 return -ENODEV;
5583         }
5584
5585         return 0;
5586 }
5587
5588 static int niu_reset_rx_bmac(struct niu *np)
5589 {
5590         int limit;
5591
5592         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5593         limit = 1000;
5594         while (--limit >= 0) {
5595                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5596                         break;
5597                 udelay(100);
5598         }
5599         if (limit < 0) {
5600                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5601                         np->port,
5602                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5603                 return -ENODEV;
5604         }
5605
5606         return 0;
5607 }
5608
5609 static int niu_reset_rx_mac(struct niu *np)
5610 {
5611         if (np->flags & NIU_FLAGS_XMAC)
5612                 return niu_reset_rx_xmac(np);
5613         else
5614                 return niu_reset_rx_bmac(np);
5615 }
5616
5617 static void niu_init_rx_xmac(struct niu *np)
5618 {
5619         struct niu_parent *parent = np->parent;
5620         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5621         int first_rdc_table = tp->first_table_num;
5622         unsigned long i;
5623         u64 val;
5624
5625         nw64_mac(XMAC_ADD_FILT0, 0);
5626         nw64_mac(XMAC_ADD_FILT1, 0);
5627         nw64_mac(XMAC_ADD_FILT2, 0);
5628         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5629         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5630         for (i = 0; i < MAC_NUM_HASH; i++)
5631                 nw64_mac(XMAC_HASH_TBL(i), 0);
5632         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5633         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5634         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5635
5636         val = nr64_mac(XMAC_CONFIG);
5637         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5638                  XMAC_CONFIG_PROMISCUOUS |
5639                  XMAC_CONFIG_PROMISC_GROUP |
5640                  XMAC_CONFIG_ERR_CHK_DIS |
5641                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5642                  XMAC_CONFIG_RESERVED_MULTICAST |
5643                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5644                  XMAC_CONFIG_ADDR_FILTER_EN |
5645                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5646                  XMAC_CONFIG_STRIP_CRC |
5647                  XMAC_CONFIG_PASS_FLOW_CTRL |
5648                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5649         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5650         nw64_mac(XMAC_CONFIG, val);
5651
5652         nw64_mac(RXMAC_BT_CNT, 0);
5653         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5654         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5655         nw64_mac(RXMAC_FRAG_CNT, 0);
5656         nw64_mac(RXMAC_HIST_CNT1, 0);
5657         nw64_mac(RXMAC_HIST_CNT2, 0);
5658         nw64_mac(RXMAC_HIST_CNT3, 0);
5659         nw64_mac(RXMAC_HIST_CNT4, 0);
5660         nw64_mac(RXMAC_HIST_CNT5, 0);
5661         nw64_mac(RXMAC_HIST_CNT6, 0);
5662         nw64_mac(RXMAC_HIST_CNT7, 0);
5663         nw64_mac(RXMAC_MPSZER_CNT, 0);
5664         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5665         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5666         nw64_mac(LINK_FAULT_CNT, 0);
5667 }
5668
5669 static void niu_init_rx_bmac(struct niu *np)
5670 {
5671         struct niu_parent *parent = np->parent;
5672         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5673         int first_rdc_table = tp->first_table_num;
5674         unsigned long i;
5675         u64 val;
5676
5677         nw64_mac(BMAC_ADD_FILT0, 0);
5678         nw64_mac(BMAC_ADD_FILT1, 0);
5679         nw64_mac(BMAC_ADD_FILT2, 0);
5680         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5681         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5682         for (i = 0; i < MAC_NUM_HASH; i++)
5683                 nw64_mac(BMAC_HASH_TBL(i), 0);
5684         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5685         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5686         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5687
5688         val = nr64_mac(BRXMAC_CONFIG);
5689         val &= ~(BRXMAC_CONFIG_ENABLE |
5690                  BRXMAC_CONFIG_STRIP_PAD |
5691                  BRXMAC_CONFIG_STRIP_FCS |
5692                  BRXMAC_CONFIG_PROMISC |
5693                  BRXMAC_CONFIG_PROMISC_GRP |
5694                  BRXMAC_CONFIG_ADDR_FILT_EN |
5695                  BRXMAC_CONFIG_DISCARD_DIS);
5696         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5697         nw64_mac(BRXMAC_CONFIG, val);
5698
5699         val = nr64_mac(BMAC_ADDR_CMPEN);
5700         val |= BMAC_ADDR_CMPEN_EN0;
5701         nw64_mac(BMAC_ADDR_CMPEN, val);
5702 }
5703
5704 static void niu_init_rx_mac(struct niu *np)
5705 {
5706         niu_set_primary_mac(np, np->dev->dev_addr);
5707
5708         if (np->flags & NIU_FLAGS_XMAC)
5709                 niu_init_rx_xmac(np);
5710         else
5711                 niu_init_rx_bmac(np);
5712 }
5713
5714 static void niu_enable_tx_xmac(struct niu *np, int on)
5715 {
5716         u64 val = nr64_mac(XMAC_CONFIG);
5717
5718         if (on)
5719                 val |= XMAC_CONFIG_TX_ENABLE;
5720         else
5721                 val &= ~XMAC_CONFIG_TX_ENABLE;
5722         nw64_mac(XMAC_CONFIG, val);
5723 }
5724
5725 static void niu_enable_tx_bmac(struct niu *np, int on)
5726 {
5727         u64 val = nr64_mac(BTXMAC_CONFIG);
5728
5729         if (on)
5730                 val |= BTXMAC_CONFIG_ENABLE;
5731         else
5732                 val &= ~BTXMAC_CONFIG_ENABLE;
5733         nw64_mac(BTXMAC_CONFIG, val);
5734 }
5735
5736 static void niu_enable_tx_mac(struct niu *np, int on)
5737 {
5738         if (np->flags & NIU_FLAGS_XMAC)
5739                 niu_enable_tx_xmac(np, on);
5740         else
5741                 niu_enable_tx_bmac(np, on);
5742 }
5743
5744 static void niu_enable_rx_xmac(struct niu *np, int on)
5745 {
5746         u64 val = nr64_mac(XMAC_CONFIG);
5747
5748         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5749                  XMAC_CONFIG_PROMISCUOUS);
5750
5751         if (np->flags & NIU_FLAGS_MCAST)
5752                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5753         if (np->flags & NIU_FLAGS_PROMISC)
5754                 val |= XMAC_CONFIG_PROMISCUOUS;
5755
5756         if (on)
5757                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5758         else
5759                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5760         nw64_mac(XMAC_CONFIG, val);
5761 }
5762
5763 static void niu_enable_rx_bmac(struct niu *np, int on)
5764 {
5765         u64 val = nr64_mac(BRXMAC_CONFIG);
5766
5767         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5768                  BRXMAC_CONFIG_PROMISC);
5769
5770         if (np->flags & NIU_FLAGS_MCAST)
5771                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5772         if (np->flags & NIU_FLAGS_PROMISC)
5773                 val |= BRXMAC_CONFIG_PROMISC;
5774
5775         if (on)
5776                 val |= BRXMAC_CONFIG_ENABLE;
5777         else
5778                 val &= ~BRXMAC_CONFIG_ENABLE;
5779         nw64_mac(BRXMAC_CONFIG, val);
5780 }
5781
5782 static void niu_enable_rx_mac(struct niu *np, int on)
5783 {
5784         if (np->flags & NIU_FLAGS_XMAC)
5785                 niu_enable_rx_xmac(np, on);
5786         else
5787                 niu_enable_rx_bmac(np, on);
5788 }
5789
5790 static int niu_init_mac(struct niu *np)
5791 {
5792         int err;
5793
5794         niu_init_xif(np);
5795         err = niu_init_pcs(np);
5796         if (err)
5797                 return err;
5798
5799         err = niu_reset_tx_mac(np);
5800         if (err)
5801                 return err;
5802         niu_init_tx_mac(np);
5803         err = niu_reset_rx_mac(np);
5804         if (err)
5805                 return err;
5806         niu_init_rx_mac(np);
5807
5808         /* This looks hookey but the RX MAC reset we just did will
5809          * undo some of the state we setup in niu_init_tx_mac() so we
5810          * have to call it again.  In particular, the RX MAC reset will
5811          * set the XMAC_MAX register back to it's default value.
5812          */
5813         niu_init_tx_mac(np);
5814         niu_enable_tx_mac(np, 1);
5815
5816         niu_enable_rx_mac(np, 1);
5817
5818         return 0;
5819 }
5820
5821 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5822 {
5823         (void) niu_tx_channel_stop(np, rp->tx_channel);
5824 }
5825
5826 static void niu_stop_tx_channels(struct niu *np)
5827 {
5828         int i;
5829
5830         for (i = 0; i < np->num_tx_rings; i++) {
5831                 struct tx_ring_info *rp = &np->tx_rings[i];
5832
5833                 niu_stop_one_tx_channel(np, rp);
5834         }
5835 }
5836
5837 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5838 {
5839         (void) niu_tx_channel_reset(np, rp->tx_channel);
5840 }
5841
5842 static void niu_reset_tx_channels(struct niu *np)
5843 {
5844         int i;
5845
5846         for (i = 0; i < np->num_tx_rings; i++) {
5847                 struct tx_ring_info *rp = &np->tx_rings[i];
5848
5849                 niu_reset_one_tx_channel(np, rp);
5850         }
5851 }
5852
5853 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5854 {
5855         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5856 }
5857
5858 static void niu_stop_rx_channels(struct niu *np)
5859 {
5860         int i;
5861
5862         for (i = 0; i < np->num_rx_rings; i++) {
5863                 struct rx_ring_info *rp = &np->rx_rings[i];
5864
5865                 niu_stop_one_rx_channel(np, rp);
5866         }
5867 }
5868
5869 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5870 {
5871         int channel = rp->rx_channel;
5872
5873         (void) niu_rx_channel_reset(np, channel);
5874         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5875         nw64(RX_DMA_CTL_STAT(channel), 0);
5876         (void) niu_enable_rx_channel(np, channel, 0);
5877 }
5878
5879 static void niu_reset_rx_channels(struct niu *np)
5880 {
5881         int i;
5882
5883         for (i = 0; i < np->num_rx_rings; i++) {
5884                 struct rx_ring_info *rp = &np->rx_rings[i];
5885
5886                 niu_reset_one_rx_channel(np, rp);
5887         }
5888 }
5889
5890 static void niu_disable_ipp(struct niu *np)
5891 {
5892         u64 rd, wr, val;
5893         int limit;
5894
5895         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5896         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5897         limit = 100;
5898         while (--limit >= 0 && (rd != wr)) {
5899                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5900                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5901         }
5902         if (limit < 0 &&
5903             (rd != 0 && wr != 1)) {
5904                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5905                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5906                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5907         }
5908
5909         val = nr64_ipp(IPP_CFIG);
5910         val &= ~(IPP_CFIG_IPP_ENABLE |
5911                  IPP_CFIG_DFIFO_ECC_EN |
5912                  IPP_CFIG_DROP_BAD_CRC |
5913                  IPP_CFIG_CKSUM_EN);
5914         nw64_ipp(IPP_CFIG, val);
5915
5916         (void) niu_ipp_reset(np);
5917 }
5918
5919 static int niu_init_hw(struct niu *np)
5920 {
5921         int i, err;
5922
5923         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5924         niu_txc_enable_port(np, 1);
5925         niu_txc_port_dma_enable(np, 1);
5926         niu_txc_set_imask(np, 0);
5927
5928         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5929         for (i = 0; i < np->num_tx_rings; i++) {
5930                 struct tx_ring_info *rp = &np->tx_rings[i];
5931
5932                 err = niu_init_one_tx_channel(np, rp);
5933                 if (err)
5934                         return err;
5935         }
5936
5937         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5938         err = niu_init_rx_channels(np);
5939         if (err)
5940                 goto out_uninit_tx_channels;
5941
5942         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5943         err = niu_init_classifier_hw(np);
5944         if (err)
5945                 goto out_uninit_rx_channels;
5946
5947         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5948         err = niu_init_zcp(np);
5949         if (err)
5950                 goto out_uninit_rx_channels;
5951
5952         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5953         err = niu_init_ipp(np);
5954         if (err)
5955                 goto out_uninit_rx_channels;
5956
5957         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5958         err = niu_init_mac(np);
5959         if (err)
5960                 goto out_uninit_ipp;
5961
5962         return 0;
5963
5964 out_uninit_ipp:
5965         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5966         niu_disable_ipp(np);
5967
5968 out_uninit_rx_channels:
5969         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5970         niu_stop_rx_channels(np);
5971         niu_reset_rx_channels(np);
5972
5973 out_uninit_tx_channels:
5974         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5975         niu_stop_tx_channels(np);
5976         niu_reset_tx_channels(np);
5977
5978         return err;
5979 }
5980
5981 static void niu_stop_hw(struct niu *np)
5982 {
5983         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
5984         niu_enable_interrupts(np, 0);
5985
5986         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
5987         niu_enable_rx_mac(np, 0);
5988
5989         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
5990         niu_disable_ipp(np);
5991
5992         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
5993         niu_stop_tx_channels(np);
5994
5995         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
5996         niu_stop_rx_channels(np);
5997
5998         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
5999         niu_reset_tx_channels(np);
6000
6001         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6002         niu_reset_rx_channels(np);
6003 }
6004
6005 static void niu_set_irq_name(struct niu *np)
6006 {
6007         int port = np->port;
6008         int i, j = 1;
6009
6010         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6011
6012         if (port == 0) {
6013                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6014                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6015                 j = 3;
6016         }
6017
6018         for (i = 0; i < np->num_ldg - j; i++) {
6019                 if (i < np->num_rx_rings)
6020                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6021                                 np->dev->name, i);
6022                 else if (i < np->num_tx_rings + np->num_rx_rings)
6023                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6024                                 i - np->num_rx_rings);
6025         }
6026 }
6027
6028 static int niu_request_irq(struct niu *np)
6029 {
6030         int i, j, err;
6031
6032         niu_set_irq_name(np);
6033
6034         err = 0;
6035         for (i = 0; i < np->num_ldg; i++) {
6036                 struct niu_ldg *lp = &np->ldg[i];
6037
6038                 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6039                                   np->irq_name[i], lp);
6040                 if (err)
6041                         goto out_free_irqs;
6042
6043         }
6044
6045         return 0;
6046
6047 out_free_irqs:
6048         for (j = 0; j < i; j++) {
6049                 struct niu_ldg *lp = &np->ldg[j];
6050
6051                 free_irq(lp->irq, lp);
6052         }
6053         return err;
6054 }
6055
6056 static void niu_free_irq(struct niu *np)
6057 {
6058         int i;
6059
6060         for (i = 0; i < np->num_ldg; i++) {
6061                 struct niu_ldg *lp = &np->ldg[i];
6062
6063                 free_irq(lp->irq, lp);
6064         }
6065 }
6066
6067 static void niu_enable_napi(struct niu *np)
6068 {
6069         int i;
6070
6071         for (i = 0; i < np->num_ldg; i++)
6072                 napi_enable(&np->ldg[i].napi);
6073 }
6074
6075 static void niu_disable_napi(struct niu *np)
6076 {
6077         int i;
6078
6079         for (i = 0; i < np->num_ldg; i++)
6080                 napi_disable(&np->ldg[i].napi);
6081 }
6082
6083 static int niu_open(struct net_device *dev)
6084 {
6085         struct niu *np = netdev_priv(dev);
6086         int err;
6087
6088         netif_carrier_off(dev);
6089
6090         err = niu_alloc_channels(np);
6091         if (err)
6092                 goto out_err;
6093
6094         err = niu_enable_interrupts(np, 0);
6095         if (err)
6096                 goto out_free_channels;
6097
6098         err = niu_request_irq(np);
6099         if (err)
6100                 goto out_free_channels;
6101
6102         niu_enable_napi(np);
6103
6104         spin_lock_irq(&np->lock);
6105
6106         err = niu_init_hw(np);
6107         if (!err) {
6108                 timer_setup(&np->timer, niu_timer, 0);
6109                 np->timer.expires = jiffies + HZ;
6110
6111                 err = niu_enable_interrupts(np, 1);
6112                 if (err)
6113                         niu_stop_hw(np);
6114         }
6115
6116         spin_unlock_irq(&np->lock);
6117
6118         if (err) {
6119                 niu_disable_napi(np);
6120                 goto out_free_irq;
6121         }
6122
6123         netif_tx_start_all_queues(dev);
6124
6125         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6126                 netif_carrier_on(dev);
6127
6128         add_timer(&np->timer);
6129
6130         return 0;
6131
6132 out_free_irq:
6133         niu_free_irq(np);
6134
6135 out_free_channels:
6136         niu_free_channels(np);
6137
6138 out_err:
6139         return err;
6140 }
6141
6142 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6143 {
6144         cancel_work_sync(&np->reset_task);
6145
6146         niu_disable_napi(np);
6147         netif_tx_stop_all_queues(dev);
6148
6149         del_timer_sync(&np->timer);
6150
6151         spin_lock_irq(&np->lock);
6152
6153         niu_stop_hw(np);
6154
6155         spin_unlock_irq(&np->lock);
6156 }
6157
6158 static int niu_close(struct net_device *dev)
6159 {
6160         struct niu *np = netdev_priv(dev);
6161
6162         niu_full_shutdown(np, dev);
6163
6164         niu_free_irq(np);
6165
6166         niu_free_channels(np);
6167
6168         niu_handle_led(np, 0);
6169
6170         return 0;
6171 }
6172
6173 static void niu_sync_xmac_stats(struct niu *np)
6174 {
6175         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6176
6177         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6178         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6179
6180         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6181         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6182         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6183         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6184         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6185         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6186         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6187         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6188         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6189         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6190         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6191         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6192         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6193         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6194         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6195         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6196 }
6197
6198 static void niu_sync_bmac_stats(struct niu *np)
6199 {
6200         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6201
6202         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6203         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6204
6205         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6206         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6207         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6208         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6209 }
6210
6211 static void niu_sync_mac_stats(struct niu *np)
6212 {
6213         if (np->flags & NIU_FLAGS_XMAC)
6214                 niu_sync_xmac_stats(np);
6215         else
6216                 niu_sync_bmac_stats(np);
6217 }
6218
6219 static void niu_get_rx_stats(struct niu *np,
6220                              struct rtnl_link_stats64 *stats)
6221 {
6222         u64 pkts, dropped, errors, bytes;
6223         struct rx_ring_info *rx_rings;
6224         int i;
6225
6226         pkts = dropped = errors = bytes = 0;
6227
6228         rx_rings = READ_ONCE(np->rx_rings);
6229         if (!rx_rings)
6230                 goto no_rings;
6231
6232         for (i = 0; i < np->num_rx_rings; i++) {
6233                 struct rx_ring_info *rp = &rx_rings[i];
6234
6235                 niu_sync_rx_discard_stats(np, rp, 0);
6236
6237                 pkts += rp->rx_packets;
6238                 bytes += rp->rx_bytes;
6239                 dropped += rp->rx_dropped;
6240                 errors += rp->rx_errors;
6241         }
6242
6243 no_rings:
6244         stats->rx_packets = pkts;
6245         stats->rx_bytes = bytes;
6246         stats->rx_dropped = dropped;
6247         stats->rx_errors = errors;
6248 }
6249
6250 static void niu_get_tx_stats(struct niu *np,
6251                              struct rtnl_link_stats64 *stats)
6252 {
6253         u64 pkts, errors, bytes;
6254         struct tx_ring_info *tx_rings;
6255         int i;
6256
6257         pkts = errors = bytes = 0;
6258
6259         tx_rings = READ_ONCE(np->tx_rings);
6260         if (!tx_rings)
6261                 goto no_rings;
6262
6263         for (i = 0; i < np->num_tx_rings; i++) {
6264                 struct tx_ring_info *rp = &tx_rings[i];
6265
6266                 pkts += rp->tx_packets;
6267                 bytes += rp->tx_bytes;
6268                 errors += rp->tx_errors;
6269         }
6270
6271 no_rings:
6272         stats->tx_packets = pkts;
6273         stats->tx_bytes = bytes;
6274         stats->tx_errors = errors;
6275 }
6276
6277 static void niu_get_stats(struct net_device *dev,
6278                           struct rtnl_link_stats64 *stats)
6279 {
6280         struct niu *np = netdev_priv(dev);
6281
6282         if (netif_running(dev)) {
6283                 niu_get_rx_stats(np, stats);
6284                 niu_get_tx_stats(np, stats);
6285         }
6286 }
6287
6288 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6289 {
6290         int i;
6291
6292         for (i = 0; i < 16; i++)
6293                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6294 }
6295
6296 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6297 {
6298         int i;
6299
6300         for (i = 0; i < 16; i++)
6301                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6302 }
6303
6304 static void niu_load_hash(struct niu *np, u16 *hash)
6305 {
6306         if (np->flags & NIU_FLAGS_XMAC)
6307                 niu_load_hash_xmac(np, hash);
6308         else
6309                 niu_load_hash_bmac(np, hash);
6310 }
6311
6312 static void niu_set_rx_mode(struct net_device *dev)
6313 {
6314         struct niu *np = netdev_priv(dev);
6315         int i, alt_cnt, err;
6316         struct netdev_hw_addr *ha;
6317         unsigned long flags;
6318         u16 hash[16] = { 0, };
6319
6320         spin_lock_irqsave(&np->lock, flags);
6321         niu_enable_rx_mac(np, 0);
6322
6323         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6324         if (dev->flags & IFF_PROMISC)
6325                 np->flags |= NIU_FLAGS_PROMISC;
6326         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6327                 np->flags |= NIU_FLAGS_MCAST;
6328
6329         alt_cnt = netdev_uc_count(dev);
6330         if (alt_cnt > niu_num_alt_addr(np)) {
6331                 alt_cnt = 0;
6332                 np->flags |= NIU_FLAGS_PROMISC;
6333         }
6334
6335         if (alt_cnt) {
6336                 int index = 0;
6337
6338                 netdev_for_each_uc_addr(ha, dev) {
6339                         err = niu_set_alt_mac(np, index, ha->addr);
6340                         if (err)
6341                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6342                                             err, index);
6343                         err = niu_enable_alt_mac(np, index, 1);
6344                         if (err)
6345                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6346                                             err, index);
6347
6348                         index++;
6349                 }
6350         } else {
6351                 int alt_start;
6352                 if (np->flags & NIU_FLAGS_XMAC)
6353                         alt_start = 0;
6354                 else
6355                         alt_start = 1;
6356                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6357                         err = niu_enable_alt_mac(np, i, 0);
6358                         if (err)
6359                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6360                                             err, i);
6361                 }
6362         }
6363         if (dev->flags & IFF_ALLMULTI) {
6364                 for (i = 0; i < 16; i++)
6365                         hash[i] = 0xffff;
6366         } else if (!netdev_mc_empty(dev)) {
6367                 netdev_for_each_mc_addr(ha, dev) {
6368                         u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6369
6370                         crc >>= 24;
6371                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6372                 }
6373         }
6374
6375         if (np->flags & NIU_FLAGS_MCAST)
6376                 niu_load_hash(np, hash);
6377
6378         niu_enable_rx_mac(np, 1);
6379         spin_unlock_irqrestore(&np->lock, flags);
6380 }
6381
6382 static int niu_set_mac_addr(struct net_device *dev, void *p)
6383 {
6384         struct niu *np = netdev_priv(dev);
6385         struct sockaddr *addr = p;
6386         unsigned long flags;
6387
6388         if (!is_valid_ether_addr(addr->sa_data))
6389                 return -EADDRNOTAVAIL;
6390
6391         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6392
6393         if (!netif_running(dev))
6394                 return 0;
6395
6396         spin_lock_irqsave(&np->lock, flags);
6397         niu_enable_rx_mac(np, 0);
6398         niu_set_primary_mac(np, dev->dev_addr);
6399         niu_enable_rx_mac(np, 1);
6400         spin_unlock_irqrestore(&np->lock, flags);
6401
6402         return 0;
6403 }
6404
6405 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6406 {
6407         return -EOPNOTSUPP;
6408 }
6409
6410 static void niu_netif_stop(struct niu *np)
6411 {
6412         netif_trans_update(np->dev);    /* prevent tx timeout */
6413
6414         niu_disable_napi(np);
6415
6416         netif_tx_disable(np->dev);
6417 }
6418
6419 static void niu_netif_start(struct niu *np)
6420 {
6421         /* NOTE: unconditional netif_wake_queue is only appropriate
6422          * so long as all callers are assured to have free tx slots
6423          * (such as after niu_init_hw).
6424          */
6425         netif_tx_wake_all_queues(np->dev);
6426
6427         niu_enable_napi(np);
6428
6429         niu_enable_interrupts(np, 1);
6430 }
6431
6432 static void niu_reset_buffers(struct niu *np)
6433 {
6434         int i, j, k, err;
6435
6436         if (np->rx_rings) {
6437                 for (i = 0; i < np->num_rx_rings; i++) {
6438                         struct rx_ring_info *rp = &np->rx_rings[i];
6439
6440                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6441                                 struct page *page;
6442
6443                                 page = rp->rxhash[j];
6444                                 while (page) {
6445                                         struct page *next =
6446                                                 (struct page *) page->mapping;
6447                                         u64 base = page->index;
6448                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6449                                         rp->rbr[k++] = cpu_to_le32(base);
6450                                         page = next;
6451                                 }
6452                         }
6453                         for (; k < MAX_RBR_RING_SIZE; k++) {
6454                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6455                                 if (unlikely(err))
6456                                         break;
6457                         }
6458
6459                         rp->rbr_index = rp->rbr_table_size - 1;
6460                         rp->rcr_index = 0;
6461                         rp->rbr_pending = 0;
6462                         rp->rbr_refill_pending = 0;
6463                 }
6464         }
6465         if (np->tx_rings) {
6466                 for (i = 0; i < np->num_tx_rings; i++) {
6467                         struct tx_ring_info *rp = &np->tx_rings[i];
6468
6469                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6470                                 if (rp->tx_buffs[j].skb)
6471                                         (void) release_tx_packet(np, rp, j);
6472                         }
6473
6474                         rp->pending = MAX_TX_RING_SIZE;
6475                         rp->prod = 0;
6476                         rp->cons = 0;
6477                         rp->wrap_bit = 0;
6478                 }
6479         }
6480 }
6481
6482 static void niu_reset_task(struct work_struct *work)
6483 {
6484         struct niu *np = container_of(work, struct niu, reset_task);
6485         unsigned long flags;
6486         int err;
6487
6488         spin_lock_irqsave(&np->lock, flags);
6489         if (!netif_running(np->dev)) {
6490                 spin_unlock_irqrestore(&np->lock, flags);
6491                 return;
6492         }
6493
6494         spin_unlock_irqrestore(&np->lock, flags);
6495
6496         del_timer_sync(&np->timer);
6497
6498         niu_netif_stop(np);
6499
6500         spin_lock_irqsave(&np->lock, flags);
6501
6502         niu_stop_hw(np);
6503
6504         spin_unlock_irqrestore(&np->lock, flags);
6505
6506         niu_reset_buffers(np);
6507
6508         spin_lock_irqsave(&np->lock, flags);
6509
6510         err = niu_init_hw(np);
6511         if (!err) {
6512                 np->timer.expires = jiffies + HZ;
6513                 add_timer(&np->timer);
6514                 niu_netif_start(np);
6515         }
6516
6517         spin_unlock_irqrestore(&np->lock, flags);
6518 }
6519
6520 static void niu_tx_timeout(struct net_device *dev)
6521 {
6522         struct niu *np = netdev_priv(dev);
6523
6524         dev_err(np->device, "%s: Transmit timed out, resetting\n",
6525                 dev->name);
6526
6527         schedule_work(&np->reset_task);
6528 }
6529
6530 static void niu_set_txd(struct tx_ring_info *rp, int index,
6531                         u64 mapping, u64 len, u64 mark,
6532                         u64 n_frags)
6533 {
6534         __le64 *desc = &rp->descr[index];
6535
6536         *desc = cpu_to_le64(mark |
6537                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6538                             (len << TX_DESC_TR_LEN_SHIFT) |
6539                             (mapping & TX_DESC_SAD));
6540 }
6541
6542 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6543                                 u64 pad_bytes, u64 len)
6544 {
6545         u16 eth_proto, eth_proto_inner;
6546         u64 csum_bits, l3off, ihl, ret;
6547         u8 ip_proto;
6548         int ipv6;
6549
6550         eth_proto = be16_to_cpu(ehdr->h_proto);
6551         eth_proto_inner = eth_proto;
6552         if (eth_proto == ETH_P_8021Q) {
6553                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6554                 __be16 val = vp->h_vlan_encapsulated_proto;
6555
6556                 eth_proto_inner = be16_to_cpu(val);
6557         }
6558
6559         ipv6 = ihl = 0;
6560         switch (skb->protocol) {
6561         case cpu_to_be16(ETH_P_IP):
6562                 ip_proto = ip_hdr(skb)->protocol;
6563                 ihl = ip_hdr(skb)->ihl;
6564                 break;
6565         case cpu_to_be16(ETH_P_IPV6):
6566                 ip_proto = ipv6_hdr(skb)->nexthdr;
6567                 ihl = (40 >> 2);
6568                 ipv6 = 1;
6569                 break;
6570         default:
6571                 ip_proto = ihl = 0;
6572                 break;
6573         }
6574
6575         csum_bits = TXHDR_CSUM_NONE;
6576         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6577                 u64 start, stuff;
6578
6579                 csum_bits = (ip_proto == IPPROTO_TCP ?
6580                              TXHDR_CSUM_TCP :
6581                              (ip_proto == IPPROTO_UDP ?
6582                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6583
6584                 start = skb_checksum_start_offset(skb) -
6585                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6586                 stuff = start + skb->csum_offset;
6587
6588                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6589                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6590         }
6591
6592         l3off = skb_network_offset(skb) -
6593                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6594
6595         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6596                (len << TXHDR_LEN_SHIFT) |
6597                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6598                (ihl << TXHDR_IHL_SHIFT) |
6599                ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) |
6600                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6601                (ipv6 ? TXHDR_IP_VER : 0) |
6602                csum_bits);
6603
6604         return ret;
6605 }
6606
6607 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6608                                   struct net_device *dev)
6609 {
6610         struct niu *np = netdev_priv(dev);
6611         unsigned long align, headroom;
6612         struct netdev_queue *txq;
6613         struct tx_ring_info *rp;
6614         struct tx_pkt_hdr *tp;
6615         unsigned int len, nfg;
6616         struct ethhdr *ehdr;
6617         int prod, i, tlen;
6618         u64 mapping, mrk;
6619
6620         i = skb_get_queue_mapping(skb);
6621         rp = &np->tx_rings[i];
6622         txq = netdev_get_tx_queue(dev, i);
6623
6624         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6625                 netif_tx_stop_queue(txq);
6626                 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6627                 rp->tx_errors++;
6628                 return NETDEV_TX_BUSY;
6629         }
6630
6631         if (eth_skb_pad(skb))
6632                 goto out;
6633
6634         len = sizeof(struct tx_pkt_hdr) + 15;
6635         if (skb_headroom(skb) < len) {
6636                 struct sk_buff *skb_new;
6637
6638                 skb_new = skb_realloc_headroom(skb, len);
6639                 if (!skb_new)
6640                         goto out_drop;
6641                 kfree_skb(skb);
6642                 skb = skb_new;
6643         } else
6644                 skb_orphan(skb);
6645
6646         align = ((unsigned long) skb->data & (16 - 1));
6647         headroom = align + sizeof(struct tx_pkt_hdr);
6648
6649         ehdr = (struct ethhdr *) skb->data;
6650         tp = skb_push(skb, headroom);
6651
6652         len = skb->len - sizeof(struct tx_pkt_hdr);
6653         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6654         tp->resv = 0;
6655
6656         len = skb_headlen(skb);
6657         mapping = np->ops->map_single(np->device, skb->data,
6658                                       len, DMA_TO_DEVICE);
6659
6660         prod = rp->prod;
6661
6662         rp->tx_buffs[prod].skb = skb;
6663         rp->tx_buffs[prod].mapping = mapping;
6664
6665         mrk = TX_DESC_SOP;
6666         if (++rp->mark_counter == rp->mark_freq) {
6667                 rp->mark_counter = 0;
6668                 mrk |= TX_DESC_MARK;
6669                 rp->mark_pending++;
6670         }
6671
6672         tlen = len;
6673         nfg = skb_shinfo(skb)->nr_frags;
6674         while (tlen > 0) {
6675                 tlen -= MAX_TX_DESC_LEN;
6676                 nfg++;
6677         }
6678
6679         while (len > 0) {
6680                 unsigned int this_len = len;
6681
6682                 if (this_len > MAX_TX_DESC_LEN)
6683                         this_len = MAX_TX_DESC_LEN;
6684
6685                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6686                 mrk = nfg = 0;
6687
6688                 prod = NEXT_TX(rp, prod);
6689                 mapping += this_len;
6690                 len -= this_len;
6691         }
6692
6693         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6694                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6695
6696                 len = skb_frag_size(frag);
6697                 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6698                                             frag->page_offset, len,
6699                                             DMA_TO_DEVICE);
6700
6701                 rp->tx_buffs[prod].skb = NULL;
6702                 rp->tx_buffs[prod].mapping = mapping;
6703
6704                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6705
6706                 prod = NEXT_TX(rp, prod);
6707         }
6708
6709         if (prod < rp->prod)
6710                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6711         rp->prod = prod;
6712
6713         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6714
6715         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6716                 netif_tx_stop_queue(txq);
6717                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6718                         netif_tx_wake_queue(txq);
6719         }
6720
6721 out:
6722         return NETDEV_TX_OK;
6723
6724 out_drop:
6725         rp->tx_errors++;
6726         kfree_skb(skb);
6727         goto out;
6728 }
6729
6730 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6731 {
6732         struct niu *np = netdev_priv(dev);
6733         int err, orig_jumbo, new_jumbo;
6734
6735         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6736         new_jumbo = (new_mtu > ETH_DATA_LEN);
6737
6738         dev->mtu = new_mtu;
6739
6740         if (!netif_running(dev) ||
6741             (orig_jumbo == new_jumbo))
6742                 return 0;
6743
6744         niu_full_shutdown(np, dev);
6745
6746         niu_free_channels(np);
6747
6748         niu_enable_napi(np);
6749
6750         err = niu_alloc_channels(np);
6751         if (err)
6752                 return err;
6753
6754         spin_lock_irq(&np->lock);
6755
6756         err = niu_init_hw(np);
6757         if (!err) {
6758                 timer_setup(&np->timer, niu_timer, 0);
6759                 np->timer.expires = jiffies + HZ;
6760
6761                 err = niu_enable_interrupts(np, 1);
6762                 if (err)
6763                         niu_stop_hw(np);
6764         }
6765
6766         spin_unlock_irq(&np->lock);
6767
6768         if (!err) {
6769                 netif_tx_start_all_queues(dev);
6770                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6771                         netif_carrier_on(dev);
6772
6773                 add_timer(&np->timer);
6774         }
6775
6776         return err;
6777 }
6778
6779 static void niu_get_drvinfo(struct net_device *dev,
6780                             struct ethtool_drvinfo *info)
6781 {
6782         struct niu *np = netdev_priv(dev);
6783         struct niu_vpd *vpd = &np->vpd;
6784
6785         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6786         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6787         snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6788                 vpd->fcode_major, vpd->fcode_minor);
6789         if (np->parent->plat_type != PLAT_TYPE_NIU)
6790                 strlcpy(info->bus_info, pci_name(np->pdev),
6791                         sizeof(info->bus_info));
6792 }
6793
6794 static int niu_get_link_ksettings(struct net_device *dev,
6795                                   struct ethtool_link_ksettings *cmd)
6796 {
6797         struct niu *np = netdev_priv(dev);
6798         struct niu_link_config *lp;
6799
6800         lp = &np->link_config;
6801
6802         memset(cmd, 0, sizeof(*cmd));
6803         cmd->base.phy_address = np->phy_addr;
6804         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6805                                                 lp->supported);
6806         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6807                                                 lp->active_advertising);
6808         cmd->base.autoneg = lp->active_autoneg;
6809         cmd->base.speed = lp->active_speed;
6810         cmd->base.duplex = lp->active_duplex;
6811         cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6812
6813         return 0;
6814 }
6815
6816 static int niu_set_link_ksettings(struct net_device *dev,
6817                                   const struct ethtool_link_ksettings *cmd)
6818 {
6819         struct niu *np = netdev_priv(dev);
6820         struct niu_link_config *lp = &np->link_config;
6821
6822         ethtool_convert_link_mode_to_legacy_u32(&lp->advertising,
6823                                                 cmd->link_modes.advertising);
6824         lp->speed = cmd->base.speed;
6825         lp->duplex = cmd->base.duplex;
6826         lp->autoneg = cmd->base.autoneg;
6827         return niu_init_link(np);
6828 }
6829
6830 static u32 niu_get_msglevel(struct net_device *dev)
6831 {
6832         struct niu *np = netdev_priv(dev);
6833         return np->msg_enable;
6834 }
6835
6836 static void niu_set_msglevel(struct net_device *dev, u32 value)
6837 {
6838         struct niu *np = netdev_priv(dev);
6839         np->msg_enable = value;
6840 }
6841
6842 static int niu_nway_reset(struct net_device *dev)
6843 {
6844         struct niu *np = netdev_priv(dev);
6845
6846         if (np->link_config.autoneg)
6847                 return niu_init_link(np);
6848
6849         return 0;
6850 }
6851
6852 static int niu_get_eeprom_len(struct net_device *dev)
6853 {
6854         struct niu *np = netdev_priv(dev);
6855
6856         return np->eeprom_len;
6857 }
6858
6859 static int niu_get_eeprom(struct net_device *dev,
6860                           struct ethtool_eeprom *eeprom, u8 *data)
6861 {
6862         struct niu *np = netdev_priv(dev);
6863         u32 offset, len, val;
6864
6865         offset = eeprom->offset;
6866         len = eeprom->len;
6867
6868         if (offset + len < offset)
6869                 return -EINVAL;
6870         if (offset >= np->eeprom_len)
6871                 return -EINVAL;
6872         if (offset + len > np->eeprom_len)
6873                 len = eeprom->len = np->eeprom_len - offset;
6874
6875         if (offset & 3) {
6876                 u32 b_offset, b_count;
6877
6878                 b_offset = offset & 3;
6879                 b_count = 4 - b_offset;
6880                 if (b_count > len)
6881                         b_count = len;
6882
6883                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6884                 memcpy(data, ((char *)&val) + b_offset, b_count);
6885                 data += b_count;
6886                 len -= b_count;
6887                 offset += b_count;
6888         }
6889         while (len >= 4) {
6890                 val = nr64(ESPC_NCR(offset / 4));
6891                 memcpy(data, &val, 4);
6892                 data += 4;
6893                 len -= 4;
6894                 offset += 4;
6895         }
6896         if (len) {
6897                 val = nr64(ESPC_NCR(offset / 4));
6898                 memcpy(data, &val, len);
6899         }
6900         return 0;
6901 }
6902
6903 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6904 {
6905         switch (flow_type) {
6906         case TCP_V4_FLOW:
6907         case TCP_V6_FLOW:
6908                 *pid = IPPROTO_TCP;
6909                 break;
6910         case UDP_V4_FLOW:
6911         case UDP_V6_FLOW:
6912                 *pid = IPPROTO_UDP;
6913                 break;
6914         case SCTP_V4_FLOW:
6915         case SCTP_V6_FLOW:
6916                 *pid = IPPROTO_SCTP;
6917                 break;
6918         case AH_V4_FLOW:
6919         case AH_V6_FLOW:
6920                 *pid = IPPROTO_AH;
6921                 break;
6922         case ESP_V4_FLOW:
6923         case ESP_V6_FLOW:
6924                 *pid = IPPROTO_ESP;
6925                 break;
6926         default:
6927                 *pid = 0;
6928                 break;
6929         }
6930 }
6931
6932 static int niu_class_to_ethflow(u64 class, int *flow_type)
6933 {
6934         switch (class) {
6935         case CLASS_CODE_TCP_IPV4:
6936                 *flow_type = TCP_V4_FLOW;
6937                 break;
6938         case CLASS_CODE_UDP_IPV4:
6939                 *flow_type = UDP_V4_FLOW;
6940                 break;
6941         case CLASS_CODE_AH_ESP_IPV4:
6942                 *flow_type = AH_V4_FLOW;
6943                 break;
6944         case CLASS_CODE_SCTP_IPV4:
6945                 *flow_type = SCTP_V4_FLOW;
6946                 break;
6947         case CLASS_CODE_TCP_IPV6:
6948                 *flow_type = TCP_V6_FLOW;
6949                 break;
6950         case CLASS_CODE_UDP_IPV6:
6951                 *flow_type = UDP_V6_FLOW;
6952                 break;
6953         case CLASS_CODE_AH_ESP_IPV6:
6954                 *flow_type = AH_V6_FLOW;
6955                 break;
6956         case CLASS_CODE_SCTP_IPV6:
6957                 *flow_type = SCTP_V6_FLOW;
6958                 break;
6959         case CLASS_CODE_USER_PROG1:
6960         case CLASS_CODE_USER_PROG2:
6961         case CLASS_CODE_USER_PROG3:
6962         case CLASS_CODE_USER_PROG4:
6963                 *flow_type = IP_USER_FLOW;
6964                 break;
6965         default:
6966                 return -EINVAL;
6967         }
6968
6969         return 0;
6970 }
6971
6972 static int niu_ethflow_to_class(int flow_type, u64 *class)
6973 {
6974         switch (flow_type) {
6975         case TCP_V4_FLOW:
6976                 *class = CLASS_CODE_TCP_IPV4;
6977                 break;
6978         case UDP_V4_FLOW:
6979                 *class = CLASS_CODE_UDP_IPV4;
6980                 break;
6981         case AH_ESP_V4_FLOW:
6982         case AH_V4_FLOW:
6983         case ESP_V4_FLOW:
6984                 *class = CLASS_CODE_AH_ESP_IPV4;
6985                 break;
6986         case SCTP_V4_FLOW:
6987                 *class = CLASS_CODE_SCTP_IPV4;
6988                 break;
6989         case TCP_V6_FLOW:
6990                 *class = CLASS_CODE_TCP_IPV6;
6991                 break;
6992         case UDP_V6_FLOW:
6993                 *class = CLASS_CODE_UDP_IPV6;
6994                 break;
6995         case AH_ESP_V6_FLOW:
6996         case AH_V6_FLOW:
6997         case ESP_V6_FLOW:
6998                 *class = CLASS_CODE_AH_ESP_IPV6;
6999                 break;
7000         case SCTP_V6_FLOW:
7001                 *class = CLASS_CODE_SCTP_IPV6;
7002                 break;
7003         default:
7004                 return 0;
7005         }
7006
7007         return 1;
7008 }
7009
7010 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7011 {
7012         u64 ethflow = 0;
7013
7014         if (flow_key & FLOW_KEY_L2DA)
7015                 ethflow |= RXH_L2DA;
7016         if (flow_key & FLOW_KEY_VLAN)
7017                 ethflow |= RXH_VLAN;
7018         if (flow_key & FLOW_KEY_IPSA)
7019                 ethflow |= RXH_IP_SRC;
7020         if (flow_key & FLOW_KEY_IPDA)
7021                 ethflow |= RXH_IP_DST;
7022         if (flow_key & FLOW_KEY_PROTO)
7023                 ethflow |= RXH_L3_PROTO;
7024         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7025                 ethflow |= RXH_L4_B_0_1;
7026         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7027                 ethflow |= RXH_L4_B_2_3;
7028
7029         return ethflow;
7030
7031 }
7032
7033 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7034 {
7035         u64 key = 0;
7036
7037         if (ethflow & RXH_L2DA)
7038                 key |= FLOW_KEY_L2DA;
7039         if (ethflow & RXH_VLAN)
7040                 key |= FLOW_KEY_VLAN;
7041         if (ethflow & RXH_IP_SRC)
7042                 key |= FLOW_KEY_IPSA;
7043         if (ethflow & RXH_IP_DST)
7044                 key |= FLOW_KEY_IPDA;
7045         if (ethflow & RXH_L3_PROTO)
7046                 key |= FLOW_KEY_PROTO;
7047         if (ethflow & RXH_L4_B_0_1)
7048                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7049         if (ethflow & RXH_L4_B_2_3)
7050                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7051
7052         *flow_key = key;
7053
7054         return 1;
7055
7056 }
7057
7058 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7059 {
7060         u64 class;
7061
7062         nfc->data = 0;
7063
7064         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7065                 return -EINVAL;
7066
7067         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7068             TCAM_KEY_DISC)
7069                 nfc->data = RXH_DISCARD;
7070         else
7071                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7072                                                       CLASS_CODE_USER_PROG1]);
7073         return 0;
7074 }
7075
7076 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7077                                         struct ethtool_rx_flow_spec *fsp)
7078 {
7079         u32 tmp;
7080         u16 prt;
7081
7082         tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7083         fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7084
7085         tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7086         fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7087
7088         tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7089         fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7090
7091         tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7092         fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7093
7094         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7095                 TCAM_V4KEY2_TOS_SHIFT;
7096         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7097                 TCAM_V4KEY2_TOS_SHIFT;
7098
7099         switch (fsp->flow_type) {
7100         case TCP_V4_FLOW:
7101         case UDP_V4_FLOW:
7102         case SCTP_V4_FLOW:
7103                 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7104                         TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7105                 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7106
7107                 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7108                         TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7109                 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7110
7111                 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7112                         TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7113                 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7114
7115                 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7116                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7117                 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7118                 break;
7119         case AH_V4_FLOW:
7120         case ESP_V4_FLOW:
7121                 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7122                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7123                 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7124
7125                 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7126                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7127                 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7128                 break;
7129         case IP_USER_FLOW:
7130                 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7131                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7132                 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7133
7134                 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7135                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7136                 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7137
7138                 fsp->h_u.usr_ip4_spec.proto =
7139                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7140                         TCAM_V4KEY2_PROTO_SHIFT;
7141                 fsp->m_u.usr_ip4_spec.proto =
7142                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7143                         TCAM_V4KEY2_PROTO_SHIFT;
7144
7145                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7146                 break;
7147         default:
7148                 break;
7149         }
7150 }
7151
7152 static int niu_get_ethtool_tcam_entry(struct niu *np,
7153                                       struct ethtool_rxnfc *nfc)
7154 {
7155         struct niu_parent *parent = np->parent;
7156         struct niu_tcam_entry *tp;
7157         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7158         u16 idx;
7159         u64 class;
7160         int ret = 0;
7161
7162         idx = tcam_get_index(np, (u16)nfc->fs.location);
7163
7164         tp = &parent->tcam[idx];
7165         if (!tp->valid) {
7166                 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7167                             parent->index, (u16)nfc->fs.location, idx);
7168                 return -EINVAL;
7169         }
7170
7171         /* fill the flow spec entry */
7172         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7173                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7174         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7175         if (ret < 0) {
7176                 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7177                             parent->index);
7178                 goto out;
7179         }
7180
7181         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7182                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7183                         TCAM_V4KEY2_PROTO_SHIFT;
7184                 if (proto == IPPROTO_ESP) {
7185                         if (fsp->flow_type == AH_V4_FLOW)
7186                                 fsp->flow_type = ESP_V4_FLOW;
7187                         else
7188                                 fsp->flow_type = ESP_V6_FLOW;
7189                 }
7190         }
7191
7192         switch (fsp->flow_type) {
7193         case TCP_V4_FLOW:
7194         case UDP_V4_FLOW:
7195         case SCTP_V4_FLOW:
7196         case AH_V4_FLOW:
7197         case ESP_V4_FLOW:
7198                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7199                 break;
7200         case TCP_V6_FLOW:
7201         case UDP_V6_FLOW:
7202         case SCTP_V6_FLOW:
7203         case AH_V6_FLOW:
7204         case ESP_V6_FLOW:
7205                 /* Not yet implemented */
7206                 ret = -EINVAL;
7207                 break;
7208         case IP_USER_FLOW:
7209                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7210                 break;
7211         default:
7212                 ret = -EINVAL;
7213                 break;
7214         }
7215
7216         if (ret < 0)
7217                 goto out;
7218
7219         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7220                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7221         else
7222                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7223                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7224
7225         /* put the tcam size here */
7226         nfc->data = tcam_get_size(np);
7227 out:
7228         return ret;
7229 }
7230
7231 static int niu_get_ethtool_tcam_all(struct niu *np,
7232                                     struct ethtool_rxnfc *nfc,
7233                                     u32 *rule_locs)
7234 {
7235         struct niu_parent *parent = np->parent;
7236         struct niu_tcam_entry *tp;
7237         int i, idx, cnt;
7238         unsigned long flags;
7239         int ret = 0;
7240
7241         /* put the tcam size here */
7242         nfc->data = tcam_get_size(np);
7243
7244         niu_lock_parent(np, flags);
7245         for (cnt = 0, i = 0; i < nfc->data; i++) {
7246                 idx = tcam_get_index(np, i);
7247                 tp = &parent->tcam[idx];
7248                 if (!tp->valid)
7249                         continue;
7250                 if (cnt == nfc->rule_cnt) {
7251                         ret = -EMSGSIZE;
7252                         break;
7253                 }
7254                 rule_locs[cnt] = i;
7255                 cnt++;
7256         }
7257         niu_unlock_parent(np, flags);
7258
7259         nfc->rule_cnt = cnt;
7260
7261         return ret;
7262 }
7263
7264 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7265                        u32 *rule_locs)
7266 {
7267         struct niu *np = netdev_priv(dev);
7268         int ret = 0;
7269
7270         switch (cmd->cmd) {
7271         case ETHTOOL_GRXFH:
7272                 ret = niu_get_hash_opts(np, cmd);
7273                 break;
7274         case ETHTOOL_GRXRINGS:
7275                 cmd->data = np->num_rx_rings;
7276                 break;
7277         case ETHTOOL_GRXCLSRLCNT:
7278                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7279                 break;
7280         case ETHTOOL_GRXCLSRULE:
7281                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7282                 break;
7283         case ETHTOOL_GRXCLSRLALL:
7284                 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7285                 break;
7286         default:
7287                 ret = -EINVAL;
7288                 break;
7289         }
7290
7291         return ret;
7292 }
7293
7294 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7295 {
7296         u64 class;
7297         u64 flow_key = 0;
7298         unsigned long flags;
7299
7300         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7301                 return -EINVAL;
7302
7303         if (class < CLASS_CODE_USER_PROG1 ||
7304             class > CLASS_CODE_SCTP_IPV6)
7305                 return -EINVAL;
7306
7307         if (nfc->data & RXH_DISCARD) {
7308                 niu_lock_parent(np, flags);
7309                 flow_key = np->parent->tcam_key[class -
7310                                                CLASS_CODE_USER_PROG1];
7311                 flow_key |= TCAM_KEY_DISC;
7312                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7313                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7314                 niu_unlock_parent(np, flags);
7315                 return 0;
7316         } else {
7317                 /* Discard was set before, but is not set now */
7318                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7319                     TCAM_KEY_DISC) {
7320                         niu_lock_parent(np, flags);
7321                         flow_key = np->parent->tcam_key[class -
7322                                                CLASS_CODE_USER_PROG1];
7323                         flow_key &= ~TCAM_KEY_DISC;
7324                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7325                              flow_key);
7326                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7327                                 flow_key;
7328                         niu_unlock_parent(np, flags);
7329                 }
7330         }
7331
7332         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7333                 return -EINVAL;
7334
7335         niu_lock_parent(np, flags);
7336         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7337         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7338         niu_unlock_parent(np, flags);
7339
7340         return 0;
7341 }
7342
7343 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7344                                        struct niu_tcam_entry *tp,
7345                                        int l2_rdc_tab, u64 class)
7346 {
7347         u8 pid = 0;
7348         u32 sip, dip, sipm, dipm, spi, spim;
7349         u16 sport, dport, spm, dpm;
7350
7351         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7352         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7353         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7354         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7355
7356         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7357         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7358         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7359         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7360
7361         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7362         tp->key[3] |= dip;
7363
7364         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7365         tp->key_mask[3] |= dipm;
7366
7367         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7368                        TCAM_V4KEY2_TOS_SHIFT);
7369         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7370                             TCAM_V4KEY2_TOS_SHIFT);
7371         switch (fsp->flow_type) {
7372         case TCP_V4_FLOW:
7373         case UDP_V4_FLOW:
7374         case SCTP_V4_FLOW:
7375                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7376                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7377                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7378                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7379
7380                 tp->key[2] |= (((u64)sport << 16) | dport);
7381                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7382                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7383                 break;
7384         case AH_V4_FLOW:
7385         case ESP_V4_FLOW:
7386                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7387                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7388
7389                 tp->key[2] |= spi;
7390                 tp->key_mask[2] |= spim;
7391                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7392                 break;
7393         case IP_USER_FLOW:
7394                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7395                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7396
7397                 tp->key[2] |= spi;
7398                 tp->key_mask[2] |= spim;
7399                 pid = fsp->h_u.usr_ip4_spec.proto;
7400                 break;
7401         default:
7402                 break;
7403         }
7404
7405         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7406         if (pid) {
7407                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7408         }
7409 }
7410
7411 static int niu_add_ethtool_tcam_entry(struct niu *np,
7412                                       struct ethtool_rxnfc *nfc)
7413 {
7414         struct niu_parent *parent = np->parent;
7415         struct niu_tcam_entry *tp;
7416         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7417         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7418         int l2_rdc_table = rdc_table->first_table_num;
7419         u16 idx;
7420         u64 class;
7421         unsigned long flags;
7422         int err, ret;
7423
7424         ret = 0;
7425
7426         idx = nfc->fs.location;
7427         if (idx >= tcam_get_size(np))
7428                 return -EINVAL;
7429
7430         if (fsp->flow_type == IP_USER_FLOW) {
7431                 int i;
7432                 int add_usr_cls = 0;
7433                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7434                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7435
7436                 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7437                         return -EINVAL;
7438
7439                 niu_lock_parent(np, flags);
7440
7441                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7442                         if (parent->l3_cls[i]) {
7443                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7444                                         class = parent->l3_cls[i];
7445                                         parent->l3_cls_refcnt[i]++;
7446                                         add_usr_cls = 1;
7447                                         break;
7448                                 }
7449                         } else {
7450                                 /* Program new user IP class */
7451                                 switch (i) {
7452                                 case 0:
7453                                         class = CLASS_CODE_USER_PROG1;
7454                                         break;
7455                                 case 1:
7456                                         class = CLASS_CODE_USER_PROG2;
7457                                         break;
7458                                 case 2:
7459                                         class = CLASS_CODE_USER_PROG3;
7460                                         break;
7461                                 case 3:
7462                                         class = CLASS_CODE_USER_PROG4;
7463                                         break;
7464                                 default:
7465                                         break;
7466                                 }
7467                                 ret = tcam_user_ip_class_set(np, class, 0,
7468                                                              uspec->proto,
7469                                                              uspec->tos,
7470                                                              umask->tos);
7471                                 if (ret)
7472                                         goto out;
7473
7474                                 ret = tcam_user_ip_class_enable(np, class, 1);
7475                                 if (ret)
7476                                         goto out;
7477                                 parent->l3_cls[i] = class;
7478                                 parent->l3_cls_pid[i] = uspec->proto;
7479                                 parent->l3_cls_refcnt[i]++;
7480                                 add_usr_cls = 1;
7481                                 break;
7482                         }
7483                 }
7484                 if (!add_usr_cls) {
7485                         netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7486                                     parent->index, __func__, uspec->proto);
7487                         ret = -EINVAL;
7488                         goto out;
7489                 }
7490                 niu_unlock_parent(np, flags);
7491         } else {
7492                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7493                         return -EINVAL;
7494                 }
7495         }
7496
7497         niu_lock_parent(np, flags);
7498
7499         idx = tcam_get_index(np, idx);
7500         tp = &parent->tcam[idx];
7501
7502         memset(tp, 0, sizeof(*tp));
7503
7504         /* fill in the tcam key and mask */
7505         switch (fsp->flow_type) {
7506         case TCP_V4_FLOW:
7507         case UDP_V4_FLOW:
7508         case SCTP_V4_FLOW:
7509         case AH_V4_FLOW:
7510         case ESP_V4_FLOW:
7511                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7512                 break;
7513         case TCP_V6_FLOW:
7514         case UDP_V6_FLOW:
7515         case SCTP_V6_FLOW:
7516         case AH_V6_FLOW:
7517         case ESP_V6_FLOW:
7518                 /* Not yet implemented */
7519                 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7520                             parent->index, __func__, fsp->flow_type);
7521                 ret = -EINVAL;
7522                 goto out;
7523         case IP_USER_FLOW:
7524                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7525                 break;
7526         default:
7527                 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7528                             parent->index, __func__, fsp->flow_type);
7529                 ret = -EINVAL;
7530                 goto out;
7531         }
7532
7533         /* fill in the assoc data */
7534         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7535                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7536         } else {
7537                 if (fsp->ring_cookie >= np->num_rx_rings) {
7538                         netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7539                                     parent->index, __func__,
7540                                     (long long)fsp->ring_cookie);
7541                         ret = -EINVAL;
7542                         goto out;
7543                 }
7544                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7545                                   (fsp->ring_cookie <<
7546                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7547         }
7548
7549         err = tcam_write(np, idx, tp->key, tp->key_mask);
7550         if (err) {
7551                 ret = -EINVAL;
7552                 goto out;
7553         }
7554         err = tcam_assoc_write(np, idx, tp->assoc_data);
7555         if (err) {
7556                 ret = -EINVAL;
7557                 goto out;
7558         }
7559
7560         /* validate the entry */
7561         tp->valid = 1;
7562         np->clas.tcam_valid_entries++;
7563 out:
7564         niu_unlock_parent(np, flags);
7565
7566         return ret;
7567 }
7568
7569 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7570 {
7571         struct niu_parent *parent = np->parent;
7572         struct niu_tcam_entry *tp;
7573         u16 idx;
7574         unsigned long flags;
7575         u64 class;
7576         int ret = 0;
7577
7578         if (loc >= tcam_get_size(np))
7579                 return -EINVAL;
7580
7581         niu_lock_parent(np, flags);
7582
7583         idx = tcam_get_index(np, loc);
7584         tp = &parent->tcam[idx];
7585
7586         /* if the entry is of a user defined class, then update*/
7587         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7588                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7589
7590         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7591                 int i;
7592                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7593                         if (parent->l3_cls[i] == class) {
7594                                 parent->l3_cls_refcnt[i]--;
7595                                 if (!parent->l3_cls_refcnt[i]) {
7596                                         /* disable class */
7597                                         ret = tcam_user_ip_class_enable(np,
7598                                                                         class,
7599                                                                         0);
7600                                         if (ret)
7601                                                 goto out;
7602                                         parent->l3_cls[i] = 0;
7603                                         parent->l3_cls_pid[i] = 0;
7604                                 }
7605                                 break;
7606                         }
7607                 }
7608                 if (i == NIU_L3_PROG_CLS) {
7609                         netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7610                                     parent->index, __func__,
7611                                     (unsigned long long)class);
7612                         ret = -EINVAL;
7613                         goto out;
7614                 }
7615         }
7616
7617         ret = tcam_flush(np, idx);
7618         if (ret)
7619                 goto out;
7620
7621         /* invalidate the entry */
7622         tp->valid = 0;
7623         np->clas.tcam_valid_entries--;
7624 out:
7625         niu_unlock_parent(np, flags);
7626
7627         return ret;
7628 }
7629
7630 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7631 {
7632         struct niu *np = netdev_priv(dev);
7633         int ret = 0;
7634
7635         switch (cmd->cmd) {
7636         case ETHTOOL_SRXFH:
7637                 ret = niu_set_hash_opts(np, cmd);
7638                 break;
7639         case ETHTOOL_SRXCLSRLINS:
7640                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7641                 break;
7642         case ETHTOOL_SRXCLSRLDEL:
7643                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7644                 break;
7645         default:
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 static const struct {
7654         const char string[ETH_GSTRING_LEN];
7655 } niu_xmac_stat_keys[] = {
7656         { "tx_frames" },
7657         { "tx_bytes" },
7658         { "tx_fifo_errors" },
7659         { "tx_overflow_errors" },
7660         { "tx_max_pkt_size_errors" },
7661         { "tx_underflow_errors" },
7662         { "rx_local_faults" },
7663         { "rx_remote_faults" },
7664         { "rx_link_faults" },
7665         { "rx_align_errors" },
7666         { "rx_frags" },
7667         { "rx_mcasts" },
7668         { "rx_bcasts" },
7669         { "rx_hist_cnt1" },
7670         { "rx_hist_cnt2" },
7671         { "rx_hist_cnt3" },
7672         { "rx_hist_cnt4" },
7673         { "rx_hist_cnt5" },
7674         { "rx_hist_cnt6" },
7675         { "rx_hist_cnt7" },
7676         { "rx_octets" },
7677         { "rx_code_violations" },
7678         { "rx_len_errors" },
7679         { "rx_crc_errors" },
7680         { "rx_underflows" },
7681         { "rx_overflows" },
7682         { "pause_off_state" },
7683         { "pause_on_state" },
7684         { "pause_received" },
7685 };
7686
7687 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7688
7689 static const struct {
7690         const char string[ETH_GSTRING_LEN];
7691 } niu_bmac_stat_keys[] = {
7692         { "tx_underflow_errors" },
7693         { "tx_max_pkt_size_errors" },
7694         { "tx_bytes" },
7695         { "tx_frames" },
7696         { "rx_overflows" },
7697         { "rx_frames" },
7698         { "rx_align_errors" },
7699         { "rx_crc_errors" },
7700         { "rx_len_errors" },
7701         { "pause_off_state" },
7702         { "pause_on_state" },
7703         { "pause_received" },
7704 };
7705
7706 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7707
7708 static const struct {
7709         const char string[ETH_GSTRING_LEN];
7710 } niu_rxchan_stat_keys[] = {
7711         { "rx_channel" },
7712         { "rx_packets" },
7713         { "rx_bytes" },
7714         { "rx_dropped" },
7715         { "rx_errors" },
7716 };
7717
7718 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7719
7720 static const struct {
7721         const char string[ETH_GSTRING_LEN];
7722 } niu_txchan_stat_keys[] = {
7723         { "tx_channel" },
7724         { "tx_packets" },
7725         { "tx_bytes" },
7726         { "tx_errors" },
7727 };
7728
7729 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7730
7731 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7732 {
7733         struct niu *np = netdev_priv(dev);
7734         int i;
7735
7736         if (stringset != ETH_SS_STATS)
7737                 return;
7738
7739         if (np->flags & NIU_FLAGS_XMAC) {
7740                 memcpy(data, niu_xmac_stat_keys,
7741                        sizeof(niu_xmac_stat_keys));
7742                 data += sizeof(niu_xmac_stat_keys);
7743         } else {
7744                 memcpy(data, niu_bmac_stat_keys,
7745                        sizeof(niu_bmac_stat_keys));
7746                 data += sizeof(niu_bmac_stat_keys);
7747         }
7748         for (i = 0; i < np->num_rx_rings; i++) {
7749                 memcpy(data, niu_rxchan_stat_keys,
7750                        sizeof(niu_rxchan_stat_keys));
7751                 data += sizeof(niu_rxchan_stat_keys);
7752         }
7753         for (i = 0; i < np->num_tx_rings; i++) {
7754                 memcpy(data, niu_txchan_stat_keys,
7755                        sizeof(niu_txchan_stat_keys));
7756                 data += sizeof(niu_txchan_stat_keys);
7757         }
7758 }
7759
7760 static int niu_get_sset_count(struct net_device *dev, int stringset)
7761 {
7762         struct niu *np = netdev_priv(dev);
7763
7764         if (stringset != ETH_SS_STATS)
7765                 return -EINVAL;
7766
7767         return (np->flags & NIU_FLAGS_XMAC ?
7768                  NUM_XMAC_STAT_KEYS :
7769                  NUM_BMAC_STAT_KEYS) +
7770                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7771                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7772 }
7773
7774 static void niu_get_ethtool_stats(struct net_device *dev,
7775                                   struct ethtool_stats *stats, u64 *data)
7776 {
7777         struct niu *np = netdev_priv(dev);
7778         int i;
7779
7780         niu_sync_mac_stats(np);
7781         if (np->flags & NIU_FLAGS_XMAC) {
7782                 memcpy(data, &np->mac_stats.xmac,
7783                        sizeof(struct niu_xmac_stats));
7784                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7785         } else {
7786                 memcpy(data, &np->mac_stats.bmac,
7787                        sizeof(struct niu_bmac_stats));
7788                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7789         }
7790         for (i = 0; i < np->num_rx_rings; i++) {
7791                 struct rx_ring_info *rp = &np->rx_rings[i];
7792
7793                 niu_sync_rx_discard_stats(np, rp, 0);
7794
7795                 data[0] = rp->rx_channel;
7796                 data[1] = rp->rx_packets;
7797                 data[2] = rp->rx_bytes;
7798                 data[3] = rp->rx_dropped;
7799                 data[4] = rp->rx_errors;
7800                 data += 5;
7801         }
7802         for (i = 0; i < np->num_tx_rings; i++) {
7803                 struct tx_ring_info *rp = &np->tx_rings[i];
7804
7805                 data[0] = rp->tx_channel;
7806                 data[1] = rp->tx_packets;
7807                 data[2] = rp->tx_bytes;
7808                 data[3] = rp->tx_errors;
7809                 data += 4;
7810         }
7811 }
7812
7813 static u64 niu_led_state_save(struct niu *np)
7814 {
7815         if (np->flags & NIU_FLAGS_XMAC)
7816                 return nr64_mac(XMAC_CONFIG);
7817         else
7818                 return nr64_mac(BMAC_XIF_CONFIG);
7819 }
7820
7821 static void niu_led_state_restore(struct niu *np, u64 val)
7822 {
7823         if (np->flags & NIU_FLAGS_XMAC)
7824                 nw64_mac(XMAC_CONFIG, val);
7825         else
7826                 nw64_mac(BMAC_XIF_CONFIG, val);
7827 }
7828
7829 static void niu_force_led(struct niu *np, int on)
7830 {
7831         u64 val, reg, bit;
7832
7833         if (np->flags & NIU_FLAGS_XMAC) {
7834                 reg = XMAC_CONFIG;
7835                 bit = XMAC_CONFIG_FORCE_LED_ON;
7836         } else {
7837                 reg = BMAC_XIF_CONFIG;
7838                 bit = BMAC_XIF_CONFIG_LINK_LED;
7839         }
7840
7841         val = nr64_mac(reg);
7842         if (on)
7843                 val |= bit;
7844         else
7845                 val &= ~bit;
7846         nw64_mac(reg, val);
7847 }
7848
7849 static int niu_set_phys_id(struct net_device *dev,
7850                            enum ethtool_phys_id_state state)
7851
7852 {
7853         struct niu *np = netdev_priv(dev);
7854
7855         if (!netif_running(dev))
7856                 return -EAGAIN;
7857
7858         switch (state) {
7859         case ETHTOOL_ID_ACTIVE:
7860                 np->orig_led_state = niu_led_state_save(np);
7861                 return 1;       /* cycle on/off once per second */
7862
7863         case ETHTOOL_ID_ON:
7864                 niu_force_led(np, 1);
7865                 break;
7866
7867         case ETHTOOL_ID_OFF:
7868                 niu_force_led(np, 0);
7869                 break;
7870
7871         case ETHTOOL_ID_INACTIVE:
7872                 niu_led_state_restore(np, np->orig_led_state);
7873         }
7874
7875         return 0;
7876 }
7877
7878 static const struct ethtool_ops niu_ethtool_ops = {
7879         .get_drvinfo            = niu_get_drvinfo,
7880         .get_link               = ethtool_op_get_link,
7881         .get_msglevel           = niu_get_msglevel,
7882         .set_msglevel           = niu_set_msglevel,
7883         .nway_reset             = niu_nway_reset,
7884         .get_eeprom_len         = niu_get_eeprom_len,
7885         .get_eeprom             = niu_get_eeprom,
7886         .get_strings            = niu_get_strings,
7887         .get_sset_count         = niu_get_sset_count,
7888         .get_ethtool_stats      = niu_get_ethtool_stats,
7889         .set_phys_id            = niu_set_phys_id,
7890         .get_rxnfc              = niu_get_nfc,
7891         .set_rxnfc              = niu_set_nfc,
7892         .get_link_ksettings     = niu_get_link_ksettings,
7893         .set_link_ksettings     = niu_set_link_ksettings,
7894 };
7895
7896 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7897                               int ldg, int ldn)
7898 {
7899         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7900                 return -EINVAL;
7901         if (ldn < 0 || ldn > LDN_MAX)
7902                 return -EINVAL;
7903
7904         parent->ldg_map[ldn] = ldg;
7905
7906         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7907                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7908                  * the firmware, and we're not supposed to change them.
7909                  * Validate the mapping, because if it's wrong we probably
7910                  * won't get any interrupts and that's painful to debug.
7911                  */
7912                 if (nr64(LDG_NUM(ldn)) != ldg) {
7913                         dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7914                                 np->port, ldn, ldg,
7915                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7916                         return -EINVAL;
7917                 }
7918         } else
7919                 nw64(LDG_NUM(ldn), ldg);
7920
7921         return 0;
7922 }
7923
7924 static int niu_set_ldg_timer_res(struct niu *np, int res)
7925 {
7926         if (res < 0 || res > LDG_TIMER_RES_VAL)
7927                 return -EINVAL;
7928
7929
7930         nw64(LDG_TIMER_RES, res);
7931
7932         return 0;
7933 }
7934
7935 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7936 {
7937         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7938             (func < 0 || func > 3) ||
7939             (vector < 0 || vector > 0x1f))
7940                 return -EINVAL;
7941
7942         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7943
7944         return 0;
7945 }
7946
7947 static int niu_pci_eeprom_read(struct niu *np, u32 addr)
7948 {
7949         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7950                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7951         int limit;
7952
7953         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7954                 return -EINVAL;
7955
7956         frame = frame_base;
7957         nw64(ESPC_PIO_STAT, frame);
7958         limit = 64;
7959         do {
7960                 udelay(5);
7961                 frame = nr64(ESPC_PIO_STAT);
7962                 if (frame & ESPC_PIO_STAT_READ_END)
7963                         break;
7964         } while (limit--);
7965         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7966                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7967                         (unsigned long long) frame);
7968                 return -ENODEV;
7969         }
7970
7971         frame = frame_base;
7972         nw64(ESPC_PIO_STAT, frame);
7973         limit = 64;
7974         do {
7975                 udelay(5);
7976                 frame = nr64(ESPC_PIO_STAT);
7977                 if (frame & ESPC_PIO_STAT_READ_END)
7978                         break;
7979         } while (limit--);
7980         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7981                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7982                         (unsigned long long) frame);
7983                 return -ENODEV;
7984         }
7985
7986         frame = nr64(ESPC_PIO_STAT);
7987         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7988 }
7989
7990 static int niu_pci_eeprom_read16(struct niu *np, u32 off)
7991 {
7992         int err = niu_pci_eeprom_read(np, off);
7993         u16 val;
7994
7995         if (err < 0)
7996                 return err;
7997         val = (err << 8);
7998         err = niu_pci_eeprom_read(np, off + 1);
7999         if (err < 0)
8000                 return err;
8001         val |= (err & 0xff);
8002
8003         return val;
8004 }
8005
8006 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8007 {
8008         int err = niu_pci_eeprom_read(np, off);
8009         u16 val;
8010
8011         if (err < 0)
8012                 return err;
8013
8014         val = (err & 0xff);
8015         err = niu_pci_eeprom_read(np, off + 1);
8016         if (err < 0)
8017                 return err;
8018
8019         val |= (err & 0xff) << 8;
8020
8021         return val;
8022 }
8023
8024 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf,
8025                                     int namebuf_len)
8026 {
8027         int i;
8028
8029         for (i = 0; i < namebuf_len; i++) {
8030                 int err = niu_pci_eeprom_read(np, off + i);
8031                 if (err < 0)
8032                         return err;
8033                 *namebuf++ = err;
8034                 if (!err)
8035                         break;
8036         }
8037         if (i >= namebuf_len)
8038                 return -EINVAL;
8039
8040         return i + 1;
8041 }
8042
8043 static void niu_vpd_parse_version(struct niu *np)
8044 {
8045         struct niu_vpd *vpd = &np->vpd;
8046         int len = strlen(vpd->version) + 1;
8047         const char *s = vpd->version;
8048         int i;
8049
8050         for (i = 0; i < len - 5; i++) {
8051                 if (!strncmp(s + i, "FCode ", 6))
8052                         break;
8053         }
8054         if (i >= len - 5)
8055                 return;
8056
8057         s += i + 5;
8058         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8059
8060         netif_printk(np, probe, KERN_DEBUG, np->dev,
8061                      "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8062                      vpd->fcode_major, vpd->fcode_minor);
8063         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8064             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8065              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8066                 np->flags |= NIU_FLAGS_VPD_VALID;
8067 }
8068
8069 /* ESPC_PIO_EN_ENABLE must be set */
8070 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)
8071 {
8072         unsigned int found_mask = 0;
8073 #define FOUND_MASK_MODEL        0x00000001
8074 #define FOUND_MASK_BMODEL       0x00000002
8075 #define FOUND_MASK_VERS         0x00000004
8076 #define FOUND_MASK_MAC          0x00000008
8077 #define FOUND_MASK_NMAC         0x00000010
8078 #define FOUND_MASK_PHY          0x00000020
8079 #define FOUND_MASK_ALL          0x0000003f
8080
8081         netif_printk(np, probe, KERN_DEBUG, np->dev,
8082                      "VPD_SCAN: start[%x] end[%x]\n", start, end);
8083         while (start < end) {
8084                 int len, err, prop_len;
8085                 char namebuf[64];
8086                 u8 *prop_buf;
8087                 int max_len;
8088
8089                 if (found_mask == FOUND_MASK_ALL) {
8090                         niu_vpd_parse_version(np);
8091                         return 1;
8092                 }
8093
8094                 err = niu_pci_eeprom_read(np, start + 2);
8095                 if (err < 0)
8096                         return err;
8097                 len = err;
8098                 start += 3;
8099
8100                 prop_len = niu_pci_eeprom_read(np, start + 4);
8101                 if (prop_len < 0)
8102                         return prop_len;
8103                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8104                 if (err < 0)
8105                         return err;
8106
8107                 prop_buf = NULL;
8108                 max_len = 0;
8109                 if (!strcmp(namebuf, "model")) {
8110                         prop_buf = np->vpd.model;
8111                         max_len = NIU_VPD_MODEL_MAX;
8112                         found_mask |= FOUND_MASK_MODEL;
8113                 } else if (!strcmp(namebuf, "board-model")) {
8114                         prop_buf = np->vpd.board_model;
8115                         max_len = NIU_VPD_BD_MODEL_MAX;
8116                         found_mask |= FOUND_MASK_BMODEL;
8117                 } else if (!strcmp(namebuf, "version")) {
8118                         prop_buf = np->vpd.version;
8119                         max_len = NIU_VPD_VERSION_MAX;
8120                         found_mask |= FOUND_MASK_VERS;
8121                 } else if (!strcmp(namebuf, "local-mac-address")) {
8122                         prop_buf = np->vpd.local_mac;
8123                         max_len = ETH_ALEN;
8124                         found_mask |= FOUND_MASK_MAC;
8125                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8126                         prop_buf = &np->vpd.mac_num;
8127                         max_len = 1;
8128                         found_mask |= FOUND_MASK_NMAC;
8129                 } else if (!strcmp(namebuf, "phy-type")) {
8130                         prop_buf = np->vpd.phy_type;
8131                         max_len = NIU_VPD_PHY_TYPE_MAX;
8132                         found_mask |= FOUND_MASK_PHY;
8133                 }
8134
8135                 if (max_len && prop_len > max_len) {
8136                         dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8137                         return -EINVAL;
8138                 }
8139
8140                 if (prop_buf) {
8141                         u32 off = start + 5 + err;
8142                         int i;
8143
8144                         netif_printk(np, probe, KERN_DEBUG, np->dev,
8145                                      "VPD_SCAN: Reading in property [%s] len[%d]\n",
8146                                      namebuf, prop_len);
8147                         for (i = 0; i < prop_len; i++) {
8148                                 err =  niu_pci_eeprom_read(np, off + i);
8149                                 if (err < 0)
8150                                         return err;
8151                                 *prop_buf++ = err;
8152                         }
8153                 }
8154
8155                 start += len;
8156         }
8157
8158         return 0;
8159 }
8160
8161 /* ESPC_PIO_EN_ENABLE must be set */
8162 static int niu_pci_vpd_fetch(struct niu *np, u32 start)
8163 {
8164         u32 offset;
8165         int err;
8166
8167         err = niu_pci_eeprom_read16_swp(np, start + 1);
8168         if (err < 0)
8169                 return err;
8170
8171         offset = err + 3;
8172
8173         while (start + offset < ESPC_EEPROM_SIZE) {
8174                 u32 here = start + offset;
8175                 u32 end;
8176
8177                 err = niu_pci_eeprom_read(np, here);
8178                 if (err < 0)
8179                         return err;
8180                 if (err != 0x90)
8181                         return -EINVAL;
8182
8183                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8184                 if (err < 0)
8185                         return err;
8186
8187                 here = start + offset + 3;
8188                 end = start + offset + err;
8189
8190                 offset += err;
8191
8192                 err = niu_pci_vpd_scan_props(np, here, end);
8193                 if (err < 0)
8194                         return err;
8195                 /* ret == 1 is not an error */
8196                 if (err == 1)
8197                         return 0;
8198         }
8199         return 0;
8200 }
8201
8202 /* ESPC_PIO_EN_ENABLE must be set */
8203 static u32 niu_pci_vpd_offset(struct niu *np)
8204 {
8205         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8206         int err;
8207
8208         while (start < end) {
8209                 ret = start;
8210
8211                 /* ROM header signature?  */
8212                 err = niu_pci_eeprom_read16(np, start +  0);
8213                 if (err != 0x55aa)
8214                         return 0;
8215
8216                 /* Apply offset to PCI data structure.  */
8217                 err = niu_pci_eeprom_read16(np, start + 23);
8218                 if (err < 0)
8219                         return 0;
8220                 start += err;
8221
8222                 /* Check for "PCIR" signature.  */
8223                 err = niu_pci_eeprom_read16(np, start +  0);
8224                 if (err != 0x5043)
8225                         return 0;
8226                 err = niu_pci_eeprom_read16(np, start +  2);
8227                 if (err != 0x4952)
8228                         return 0;
8229
8230                 /* Check for OBP image type.  */
8231                 err = niu_pci_eeprom_read(np, start + 20);
8232                 if (err < 0)
8233                         return 0;
8234                 if (err != 0x01) {
8235                         err = niu_pci_eeprom_read(np, ret + 2);
8236                         if (err < 0)
8237                                 return 0;
8238
8239                         start = ret + (err * 512);
8240                         continue;
8241                 }
8242
8243                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8244                 if (err < 0)
8245                         return err;
8246                 ret += err;
8247
8248                 err = niu_pci_eeprom_read(np, ret + 0);
8249                 if (err != 0x82)
8250                         return 0;
8251
8252                 return ret;
8253         }
8254
8255         return 0;
8256 }
8257
8258 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop)
8259 {
8260         if (!strcmp(phy_prop, "mif")) {
8261                 /* 1G copper, MII */
8262                 np->flags &= ~(NIU_FLAGS_FIBER |
8263                                NIU_FLAGS_10G);
8264                 np->mac_xcvr = MAC_XCVR_MII;
8265         } else if (!strcmp(phy_prop, "xgf")) {
8266                 /* 10G fiber, XPCS */
8267                 np->flags |= (NIU_FLAGS_10G |
8268                               NIU_FLAGS_FIBER);
8269                 np->mac_xcvr = MAC_XCVR_XPCS;
8270         } else if (!strcmp(phy_prop, "pcs")) {
8271                 /* 1G fiber, PCS */
8272                 np->flags &= ~NIU_FLAGS_10G;
8273                 np->flags |= NIU_FLAGS_FIBER;
8274                 np->mac_xcvr = MAC_XCVR_PCS;
8275         } else if (!strcmp(phy_prop, "xgc")) {
8276                 /* 10G copper, XPCS */
8277                 np->flags |= NIU_FLAGS_10G;
8278                 np->flags &= ~NIU_FLAGS_FIBER;
8279                 np->mac_xcvr = MAC_XCVR_XPCS;
8280         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8281                 /* 10G Serdes or 1G Serdes, default to 10G */
8282                 np->flags |= NIU_FLAGS_10G;
8283                 np->flags &= ~NIU_FLAGS_FIBER;
8284                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8285                 np->mac_xcvr = MAC_XCVR_XPCS;
8286         } else {
8287                 return -EINVAL;
8288         }
8289         return 0;
8290 }
8291
8292 static int niu_pci_vpd_get_nports(struct niu *np)
8293 {
8294         int ports = 0;
8295
8296         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8297             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8298             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8299             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8300             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8301                 ports = 4;
8302         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8303                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8304                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8305                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8306                 ports = 2;
8307         }
8308
8309         return ports;
8310 }
8311
8312 static void niu_pci_vpd_validate(struct niu *np)
8313 {
8314         struct net_device *dev = np->dev;
8315         struct niu_vpd *vpd = &np->vpd;
8316         u8 val8;
8317
8318         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8319                 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8320
8321                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8322                 return;
8323         }
8324
8325         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8326             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8327                 np->flags |= NIU_FLAGS_10G;
8328                 np->flags &= ~NIU_FLAGS_FIBER;
8329                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8330                 np->mac_xcvr = MAC_XCVR_PCS;
8331                 if (np->port > 1) {
8332                         np->flags |= NIU_FLAGS_FIBER;
8333                         np->flags &= ~NIU_FLAGS_10G;
8334                 }
8335                 if (np->flags & NIU_FLAGS_10G)
8336                         np->mac_xcvr = MAC_XCVR_XPCS;
8337         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8338                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8339                               NIU_FLAGS_HOTPLUG_PHY);
8340         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8341                 dev_err(np->device, "Illegal phy string [%s]\n",
8342                         np->vpd.phy_type);
8343                 dev_err(np->device, "Falling back to SPROM\n");
8344                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8345                 return;
8346         }
8347
8348         memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN);
8349
8350         val8 = dev->dev_addr[5];
8351         dev->dev_addr[5] += np->port;
8352         if (dev->dev_addr[5] < val8)
8353                 dev->dev_addr[4]++;
8354 }
8355
8356 static int niu_pci_probe_sprom(struct niu *np)
8357 {
8358         struct net_device *dev = np->dev;
8359         int len, i;
8360         u64 val, sum;
8361         u8 val8;
8362
8363         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8364         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8365         len = val / 4;
8366
8367         np->eeprom_len = len;
8368
8369         netif_printk(np, probe, KERN_DEBUG, np->dev,
8370                      "SPROM: Image size %llu\n", (unsigned long long)val);
8371
8372         sum = 0;
8373         for (i = 0; i < len; i++) {
8374                 val = nr64(ESPC_NCR(i));
8375                 sum += (val >>  0) & 0xff;
8376                 sum += (val >>  8) & 0xff;
8377                 sum += (val >> 16) & 0xff;
8378                 sum += (val >> 24) & 0xff;
8379         }
8380         netif_printk(np, probe, KERN_DEBUG, np->dev,
8381                      "SPROM: Checksum %x\n", (int)(sum & 0xff));
8382         if ((sum & 0xff) != 0xab) {
8383                 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8384                 return -EINVAL;
8385         }
8386
8387         val = nr64(ESPC_PHY_TYPE);
8388         switch (np->port) {
8389         case 0:
8390                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8391                         ESPC_PHY_TYPE_PORT0_SHIFT;
8392                 break;
8393         case 1:
8394                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8395                         ESPC_PHY_TYPE_PORT1_SHIFT;
8396                 break;
8397         case 2:
8398                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8399                         ESPC_PHY_TYPE_PORT2_SHIFT;
8400                 break;
8401         case 3:
8402                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8403                         ESPC_PHY_TYPE_PORT3_SHIFT;
8404                 break;
8405         default:
8406                 dev_err(np->device, "Bogus port number %u\n",
8407                         np->port);
8408                 return -EINVAL;
8409         }
8410         netif_printk(np, probe, KERN_DEBUG, np->dev,
8411                      "SPROM: PHY type %x\n", val8);
8412
8413         switch (val8) {
8414         case ESPC_PHY_TYPE_1G_COPPER:
8415                 /* 1G copper, MII */
8416                 np->flags &= ~(NIU_FLAGS_FIBER |
8417                                NIU_FLAGS_10G);
8418                 np->mac_xcvr = MAC_XCVR_MII;
8419                 break;
8420
8421         case ESPC_PHY_TYPE_1G_FIBER:
8422                 /* 1G fiber, PCS */
8423                 np->flags &= ~NIU_FLAGS_10G;
8424                 np->flags |= NIU_FLAGS_FIBER;
8425                 np->mac_xcvr = MAC_XCVR_PCS;
8426                 break;
8427
8428         case ESPC_PHY_TYPE_10G_COPPER:
8429                 /* 10G copper, XPCS */
8430                 np->flags |= NIU_FLAGS_10G;
8431                 np->flags &= ~NIU_FLAGS_FIBER;
8432                 np->mac_xcvr = MAC_XCVR_XPCS;
8433                 break;
8434
8435         case ESPC_PHY_TYPE_10G_FIBER:
8436                 /* 10G fiber, XPCS */
8437                 np->flags |= (NIU_FLAGS_10G |
8438                               NIU_FLAGS_FIBER);
8439                 np->mac_xcvr = MAC_XCVR_XPCS;
8440                 break;
8441
8442         default:
8443                 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8444                 return -EINVAL;
8445         }
8446
8447         val = nr64(ESPC_MAC_ADDR0);
8448         netif_printk(np, probe, KERN_DEBUG, np->dev,
8449                      "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8450         dev->dev_addr[0] = (val >>  0) & 0xff;
8451         dev->dev_addr[1] = (val >>  8) & 0xff;
8452         dev->dev_addr[2] = (val >> 16) & 0xff;
8453         dev->dev_addr[3] = (val >> 24) & 0xff;
8454
8455         val = nr64(ESPC_MAC_ADDR1);
8456         netif_printk(np, probe, KERN_DEBUG, np->dev,
8457                      "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8458         dev->dev_addr[4] = (val >>  0) & 0xff;
8459         dev->dev_addr[5] = (val >>  8) & 0xff;
8460
8461         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8462                 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8463                         dev->dev_addr);
8464                 return -EINVAL;
8465         }
8466
8467         val8 = dev->dev_addr[5];
8468         dev->dev_addr[5] += np->port;
8469         if (dev->dev_addr[5] < val8)
8470                 dev->dev_addr[4]++;
8471
8472         val = nr64(ESPC_MOD_STR_LEN);
8473         netif_printk(np, probe, KERN_DEBUG, np->dev,
8474                      "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8475         if (val >= 8 * 4)
8476                 return -EINVAL;
8477
8478         for (i = 0; i < val; i += 4) {
8479                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8480
8481                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8482                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8483                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8484                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8485         }
8486         np->vpd.model[val] = '\0';
8487
8488         val = nr64(ESPC_BD_MOD_STR_LEN);
8489         netif_printk(np, probe, KERN_DEBUG, np->dev,
8490                      "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8491         if (val >= 4 * 4)
8492                 return -EINVAL;
8493
8494         for (i = 0; i < val; i += 4) {
8495                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8496
8497                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8498                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8499                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8500                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8501         }
8502         np->vpd.board_model[val] = '\0';
8503
8504         np->vpd.mac_num =
8505                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8506         netif_printk(np, probe, KERN_DEBUG, np->dev,
8507                      "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8508
8509         return 0;
8510 }
8511
8512 static int niu_get_and_validate_port(struct niu *np)
8513 {
8514         struct niu_parent *parent = np->parent;
8515
8516         if (np->port <= 1)
8517                 np->flags |= NIU_FLAGS_XMAC;
8518
8519         if (!parent->num_ports) {
8520                 if (parent->plat_type == PLAT_TYPE_NIU) {
8521                         parent->num_ports = 2;
8522                 } else {
8523                         parent->num_ports = niu_pci_vpd_get_nports(np);
8524                         if (!parent->num_ports) {
8525                                 /* Fall back to SPROM as last resort.
8526                                  * This will fail on most cards.
8527                                  */
8528                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8529                                         ESPC_NUM_PORTS_MACS_VAL;
8530
8531                                 /* All of the current probing methods fail on
8532                                  * Maramba on-board parts.
8533                                  */
8534                                 if (!parent->num_ports)
8535                                         parent->num_ports = 4;
8536                         }
8537                 }
8538         }
8539
8540         if (np->port >= parent->num_ports)
8541                 return -ENODEV;
8542
8543         return 0;
8544 }
8545
8546 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p,
8547                       int dev_id_1, int dev_id_2, u8 phy_port, int type)
8548 {
8549         u32 id = (dev_id_1 << 16) | dev_id_2;
8550         u8 idx;
8551
8552         if (dev_id_1 < 0 || dev_id_2 < 0)
8553                 return 0;
8554         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8555                 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8556                  * test covers the 8706 as well.
8557                  */
8558                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8559                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8560                         return 0;
8561         } else {
8562                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8563                         return 0;
8564         }
8565
8566         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8567                 parent->index, id,
8568                 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8569                 type == PHY_TYPE_PCS ? "PCS" : "MII",
8570                 phy_port);
8571
8572         if (p->cur[type] >= NIU_MAX_PORTS) {
8573                 pr_err("Too many PHY ports\n");
8574                 return -EINVAL;
8575         }
8576         idx = p->cur[type];
8577         p->phy_id[type][idx] = id;
8578         p->phy_port[type][idx] = phy_port;
8579         p->cur[type] = idx + 1;
8580         return 0;
8581 }
8582
8583 static int port_has_10g(struct phy_probe_info *p, int port)
8584 {
8585         int i;
8586
8587         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8588                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8589                         return 1;
8590         }
8591         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8592                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8593                         return 1;
8594         }
8595
8596         return 0;
8597 }
8598
8599 static int count_10g_ports(struct phy_probe_info *p, int *lowest)
8600 {
8601         int port, cnt;
8602
8603         cnt = 0;
8604         *lowest = 32;
8605         for (port = 8; port < 32; port++) {
8606                 if (port_has_10g(p, port)) {
8607                         if (!cnt)
8608                                 *lowest = port;
8609                         cnt++;
8610                 }
8611         }
8612
8613         return cnt;
8614 }
8615
8616 static int count_1g_ports(struct phy_probe_info *p, int *lowest)
8617 {
8618         *lowest = 32;
8619         if (p->cur[PHY_TYPE_MII])
8620                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8621
8622         return p->cur[PHY_TYPE_MII];
8623 }
8624
8625 static void niu_n2_divide_channels(struct niu_parent *parent)
8626 {
8627         int num_ports = parent->num_ports;
8628         int i;
8629
8630         for (i = 0; i < num_ports; i++) {
8631                 parent->rxchan_per_port[i] = (16 / num_ports);
8632                 parent->txchan_per_port[i] = (16 / num_ports);
8633
8634                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8635                         parent->index, i,
8636                         parent->rxchan_per_port[i],
8637                         parent->txchan_per_port[i]);
8638         }
8639 }
8640
8641 static void niu_divide_channels(struct niu_parent *parent,
8642                                 int num_10g, int num_1g)
8643 {
8644         int num_ports = parent->num_ports;
8645         int rx_chans_per_10g, rx_chans_per_1g;
8646         int tx_chans_per_10g, tx_chans_per_1g;
8647         int i, tot_rx, tot_tx;
8648
8649         if (!num_10g || !num_1g) {
8650                 rx_chans_per_10g = rx_chans_per_1g =
8651                         (NIU_NUM_RXCHAN / num_ports);
8652                 tx_chans_per_10g = tx_chans_per_1g =
8653                         (NIU_NUM_TXCHAN / num_ports);
8654         } else {
8655                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8656                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8657                                     (rx_chans_per_1g * num_1g)) /
8658                         num_10g;
8659
8660                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8661                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8662                                     (tx_chans_per_1g * num_1g)) /
8663                         num_10g;
8664         }
8665
8666         tot_rx = tot_tx = 0;
8667         for (i = 0; i < num_ports; i++) {
8668                 int type = phy_decode(parent->port_phy, i);
8669
8670                 if (type == PORT_TYPE_10G) {
8671                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8672                         parent->txchan_per_port[i] = tx_chans_per_10g;
8673                 } else {
8674                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8675                         parent->txchan_per_port[i] = tx_chans_per_1g;
8676                 }
8677                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8678                         parent->index, i,
8679                         parent->rxchan_per_port[i],
8680                         parent->txchan_per_port[i]);
8681                 tot_rx += parent->rxchan_per_port[i];
8682                 tot_tx += parent->txchan_per_port[i];
8683         }
8684
8685         if (tot_rx > NIU_NUM_RXCHAN) {
8686                 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8687                        parent->index, tot_rx);
8688                 for (i = 0; i < num_ports; i++)
8689                         parent->rxchan_per_port[i] = 1;
8690         }
8691         if (tot_tx > NIU_NUM_TXCHAN) {
8692                 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8693                        parent->index, tot_tx);
8694                 for (i = 0; i < num_ports; i++)
8695                         parent->txchan_per_port[i] = 1;
8696         }
8697         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8698                 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8699                         parent->index, tot_rx, tot_tx);
8700         }
8701 }
8702
8703 static void niu_divide_rdc_groups(struct niu_parent *parent,
8704                                   int num_10g, int num_1g)
8705 {
8706         int i, num_ports = parent->num_ports;
8707         int rdc_group, rdc_groups_per_port;
8708         int rdc_channel_base;
8709
8710         rdc_group = 0;
8711         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8712
8713         rdc_channel_base = 0;
8714
8715         for (i = 0; i < num_ports; i++) {
8716                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8717                 int grp, num_channels = parent->rxchan_per_port[i];
8718                 int this_channel_offset;
8719
8720                 tp->first_table_num = rdc_group;
8721                 tp->num_tables = rdc_groups_per_port;
8722                 this_channel_offset = 0;
8723                 for (grp = 0; grp < tp->num_tables; grp++) {
8724                         struct rdc_table *rt = &tp->tables[grp];
8725                         int slot;
8726
8727                         pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8728                                 parent->index, i, tp->first_table_num + grp);
8729                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8730                                 rt->rxdma_channel[slot] =
8731                                         rdc_channel_base + this_channel_offset;
8732
8733                                 pr_cont("%d ", rt->rxdma_channel[slot]);
8734
8735                                 if (++this_channel_offset == num_channels)
8736                                         this_channel_offset = 0;
8737                         }
8738                         pr_cont("]\n");
8739                 }
8740
8741                 parent->rdc_default[i] = rdc_channel_base;
8742
8743                 rdc_channel_base += num_channels;
8744                 rdc_group += rdc_groups_per_port;
8745         }
8746 }
8747
8748 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent,
8749                                struct phy_probe_info *info)
8750 {
8751         unsigned long flags;
8752         int port, err;
8753
8754         memset(info, 0, sizeof(*info));
8755
8756         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8757         niu_lock_parent(np, flags);
8758         err = 0;
8759         for (port = 8; port < 32; port++) {
8760                 int dev_id_1, dev_id_2;
8761
8762                 dev_id_1 = mdio_read(np, port,
8763                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8764                 dev_id_2 = mdio_read(np, port,
8765                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8766                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8767                                  PHY_TYPE_PMA_PMD);
8768                 if (err)
8769                         break;
8770                 dev_id_1 = mdio_read(np, port,
8771                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8772                 dev_id_2 = mdio_read(np, port,
8773                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8774                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8775                                  PHY_TYPE_PCS);
8776                 if (err)
8777                         break;
8778                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8779                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8780                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8781                                  PHY_TYPE_MII);
8782                 if (err)
8783                         break;
8784         }
8785         niu_unlock_parent(np, flags);
8786
8787         return err;
8788 }
8789
8790 static int walk_phys(struct niu *np, struct niu_parent *parent)
8791 {
8792         struct phy_probe_info *info = &parent->phy_probe_info;
8793         int lowest_10g, lowest_1g;
8794         int num_10g, num_1g;
8795         u32 val;
8796         int err;
8797
8798         num_10g = num_1g = 0;
8799
8800         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8801             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8802                 num_10g = 0;
8803                 num_1g = 2;
8804                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8805                 parent->num_ports = 4;
8806                 val = (phy_encode(PORT_TYPE_1G, 0) |
8807                        phy_encode(PORT_TYPE_1G, 1) |
8808                        phy_encode(PORT_TYPE_1G, 2) |
8809                        phy_encode(PORT_TYPE_1G, 3));
8810         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8811                 num_10g = 2;
8812                 num_1g = 0;
8813                 parent->num_ports = 2;
8814                 val = (phy_encode(PORT_TYPE_10G, 0) |
8815                        phy_encode(PORT_TYPE_10G, 1));
8816         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8817                    (parent->plat_type == PLAT_TYPE_NIU)) {
8818                 /* this is the Monza case */
8819                 if (np->flags & NIU_FLAGS_10G) {
8820                         val = (phy_encode(PORT_TYPE_10G, 0) |
8821                                phy_encode(PORT_TYPE_10G, 1));
8822                 } else {
8823                         val = (phy_encode(PORT_TYPE_1G, 0) |
8824                                phy_encode(PORT_TYPE_1G, 1));
8825                 }
8826         } else {
8827                 err = fill_phy_probe_info(np, parent, info);
8828                 if (err)
8829                         return err;
8830
8831                 num_10g = count_10g_ports(info, &lowest_10g);
8832                 num_1g = count_1g_ports(info, &lowest_1g);
8833
8834                 switch ((num_10g << 4) | num_1g) {
8835                 case 0x24:
8836                         if (lowest_1g == 10)
8837                                 parent->plat_type = PLAT_TYPE_VF_P0;
8838                         else if (lowest_1g == 26)
8839                                 parent->plat_type = PLAT_TYPE_VF_P1;
8840                         else
8841                                 goto unknown_vg_1g_port;
8842
8843                         /* fallthru */
8844                 case 0x22:
8845                         val = (phy_encode(PORT_TYPE_10G, 0) |
8846                                phy_encode(PORT_TYPE_10G, 1) |
8847                                phy_encode(PORT_TYPE_1G, 2) |
8848                                phy_encode(PORT_TYPE_1G, 3));
8849                         break;
8850
8851                 case 0x20:
8852                         val = (phy_encode(PORT_TYPE_10G, 0) |
8853                                phy_encode(PORT_TYPE_10G, 1));
8854                         break;
8855
8856                 case 0x10:
8857                         val = phy_encode(PORT_TYPE_10G, np->port);
8858                         break;
8859
8860                 case 0x14:
8861                         if (lowest_1g == 10)
8862                                 parent->plat_type = PLAT_TYPE_VF_P0;
8863                         else if (lowest_1g == 26)
8864                                 parent->plat_type = PLAT_TYPE_VF_P1;
8865                         else
8866                                 goto unknown_vg_1g_port;
8867
8868                         /* fallthru */
8869                 case 0x13:
8870                         if ((lowest_10g & 0x7) == 0)
8871                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8872                                        phy_encode(PORT_TYPE_1G, 1) |
8873                                        phy_encode(PORT_TYPE_1G, 2) |
8874                                        phy_encode(PORT_TYPE_1G, 3));
8875                         else
8876                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8877                                        phy_encode(PORT_TYPE_10G, 1) |
8878                                        phy_encode(PORT_TYPE_1G, 2) |
8879                                        phy_encode(PORT_TYPE_1G, 3));
8880                         break;
8881
8882                 case 0x04:
8883                         if (lowest_1g == 10)
8884                                 parent->plat_type = PLAT_TYPE_VF_P0;
8885                         else if (lowest_1g == 26)
8886                                 parent->plat_type = PLAT_TYPE_VF_P1;
8887                         else
8888                                 goto unknown_vg_1g_port;
8889
8890                         val = (phy_encode(PORT_TYPE_1G, 0) |
8891                                phy_encode(PORT_TYPE_1G, 1) |
8892                                phy_encode(PORT_TYPE_1G, 2) |
8893                                phy_encode(PORT_TYPE_1G, 3));
8894                         break;
8895
8896                 default:
8897                         pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8898                                num_10g, num_1g);
8899                         return -EINVAL;
8900                 }
8901         }
8902
8903         parent->port_phy = val;
8904
8905         if (parent->plat_type == PLAT_TYPE_NIU)
8906                 niu_n2_divide_channels(parent);
8907         else
8908                 niu_divide_channels(parent, num_10g, num_1g);
8909
8910         niu_divide_rdc_groups(parent, num_10g, num_1g);
8911
8912         return 0;
8913
8914 unknown_vg_1g_port:
8915         pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8916         return -EINVAL;
8917 }
8918
8919 static int niu_probe_ports(struct niu *np)
8920 {
8921         struct niu_parent *parent = np->parent;
8922         int err, i;
8923
8924         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8925                 err = walk_phys(np, parent);
8926                 if (err)
8927                         return err;
8928
8929                 niu_set_ldg_timer_res(np, 2);
8930                 for (i = 0; i <= LDN_MAX; i++)
8931                         niu_ldn_irq_enable(np, i, 0);
8932         }
8933
8934         if (parent->port_phy == PORT_PHY_INVALID)
8935                 return -EINVAL;
8936
8937         return 0;
8938 }
8939
8940 static int niu_classifier_swstate_init(struct niu *np)
8941 {
8942         struct niu_classifier *cp = &np->clas;
8943
8944         cp->tcam_top = (u16) np->port;
8945         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8946         cp->h1_init = 0xffffffff;
8947         cp->h2_init = 0xffff;
8948
8949         return fflp_early_init(np);
8950 }
8951
8952 static void niu_link_config_init(struct niu *np)
8953 {
8954         struct niu_link_config *lp = &np->link_config;
8955
8956         lp->advertising = (ADVERTISED_10baseT_Half |
8957                            ADVERTISED_10baseT_Full |
8958                            ADVERTISED_100baseT_Half |
8959                            ADVERTISED_100baseT_Full |
8960                            ADVERTISED_1000baseT_Half |
8961                            ADVERTISED_1000baseT_Full |
8962                            ADVERTISED_10000baseT_Full |
8963                            ADVERTISED_Autoneg);
8964         lp->speed = lp->active_speed = SPEED_INVALID;
8965         lp->duplex = DUPLEX_FULL;
8966         lp->active_duplex = DUPLEX_INVALID;
8967         lp->autoneg = 1;
8968 #if 0
8969         lp->loopback_mode = LOOPBACK_MAC;
8970         lp->active_speed = SPEED_10000;
8971         lp->active_duplex = DUPLEX_FULL;
8972 #else
8973         lp->loopback_mode = LOOPBACK_DISABLED;
8974 #endif
8975 }
8976
8977 static int niu_init_mac_ipp_pcs_base(struct niu *np)
8978 {
8979         switch (np->port) {
8980         case 0:
8981                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8982                 np->ipp_off  = 0x00000;
8983                 np->pcs_off  = 0x04000;
8984                 np->xpcs_off = 0x02000;
8985                 break;
8986
8987         case 1:
8988                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8989                 np->ipp_off  = 0x08000;
8990                 np->pcs_off  = 0x0a000;
8991                 np->xpcs_off = 0x08000;
8992                 break;
8993
8994         case 2:
8995                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8996                 np->ipp_off  = 0x04000;
8997                 np->pcs_off  = 0x0e000;
8998                 np->xpcs_off = ~0UL;
8999                 break;
9000
9001         case 3:
9002                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9003                 np->ipp_off  = 0x0c000;
9004                 np->pcs_off  = 0x12000;
9005                 np->xpcs_off = ~0UL;
9006                 break;
9007
9008         default:
9009                 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9010                 return -EINVAL;
9011         }
9012
9013         return 0;
9014 }
9015
9016 static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
9017 {
9018         struct msix_entry msi_vec[NIU_NUM_LDG];
9019         struct niu_parent *parent = np->parent;
9020         struct pci_dev *pdev = np->pdev;
9021         int i, num_irqs;
9022         u8 first_ldg;
9023
9024         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9025         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9026                 ldg_num_map[i] = first_ldg + i;
9027
9028         num_irqs = (parent->rxchan_per_port[np->port] +
9029                     parent->txchan_per_port[np->port] +
9030                     (np->port == 0 ? 3 : 1));
9031         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9032
9033         for (i = 0; i < num_irqs; i++) {
9034                 msi_vec[i].vector = 0;
9035                 msi_vec[i].entry = i;
9036         }
9037
9038         num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
9039         if (num_irqs < 0) {
9040                 np->flags &= ~NIU_FLAGS_MSIX;
9041                 return;
9042         }
9043
9044         np->flags |= NIU_FLAGS_MSIX;
9045         for (i = 0; i < num_irqs; i++)
9046                 np->ldg[i].irq = msi_vec[i].vector;
9047         np->num_ldg = num_irqs;
9048 }
9049
9050 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9051 {
9052 #ifdef CONFIG_SPARC64
9053         struct platform_device *op = np->op;
9054         const u32 *int_prop;
9055         int i;
9056
9057         int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9058         if (!int_prop)
9059                 return -ENODEV;
9060
9061         for (i = 0; i < op->archdata.num_irqs; i++) {
9062                 ldg_num_map[i] = int_prop[i];
9063                 np->ldg[i].irq = op->archdata.irqs[i];
9064         }
9065
9066         np->num_ldg = op->archdata.num_irqs;
9067
9068         return 0;
9069 #else
9070         return -EINVAL;
9071 #endif
9072 }
9073
9074 static int niu_ldg_init(struct niu *np)
9075 {
9076         struct niu_parent *parent = np->parent;
9077         u8 ldg_num_map[NIU_NUM_LDG];
9078         int first_chan, num_chan;
9079         int i, err, ldg_rotor;
9080         u8 port;
9081
9082         np->num_ldg = 1;
9083         np->ldg[0].irq = np->dev->irq;
9084         if (parent->plat_type == PLAT_TYPE_NIU) {
9085                 err = niu_n2_irq_init(np, ldg_num_map);
9086                 if (err)
9087                         return err;
9088         } else
9089                 niu_try_msix(np, ldg_num_map);
9090
9091         port = np->port;
9092         for (i = 0; i < np->num_ldg; i++) {
9093                 struct niu_ldg *lp = &np->ldg[i];
9094
9095                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9096
9097                 lp->np = np;
9098                 lp->ldg_num = ldg_num_map[i];
9099                 lp->timer = 2; /* XXX */
9100
9101                 /* On N2 NIU the firmware has setup the SID mappings so they go
9102                  * to the correct values that will route the LDG to the proper
9103                  * interrupt in the NCU interrupt table.
9104                  */
9105                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9106                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9107                         if (err)
9108                                 return err;
9109                 }
9110         }
9111
9112         /* We adopt the LDG assignment ordering used by the N2 NIU
9113          * 'interrupt' properties because that simplifies a lot of
9114          * things.  This ordering is:
9115          *
9116          *      MAC
9117          *      MIF     (if port zero)
9118          *      SYSERR  (if port zero)
9119          *      RX channels
9120          *      TX channels
9121          */
9122
9123         ldg_rotor = 0;
9124
9125         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9126                                   LDN_MAC(port));
9127         if (err)
9128                 return err;
9129
9130         ldg_rotor++;
9131         if (ldg_rotor == np->num_ldg)
9132                 ldg_rotor = 0;
9133
9134         if (port == 0) {
9135                 err = niu_ldg_assign_ldn(np, parent,
9136                                          ldg_num_map[ldg_rotor],
9137                                          LDN_MIF);
9138                 if (err)
9139                         return err;
9140
9141                 ldg_rotor++;
9142                 if (ldg_rotor == np->num_ldg)
9143                         ldg_rotor = 0;
9144
9145                 err = niu_ldg_assign_ldn(np, parent,
9146                                          ldg_num_map[ldg_rotor],
9147                                          LDN_DEVICE_ERROR);
9148                 if (err)
9149                         return err;
9150
9151                 ldg_rotor++;
9152                 if (ldg_rotor == np->num_ldg)
9153                         ldg_rotor = 0;
9154
9155         }
9156
9157         first_chan = 0;
9158         for (i = 0; i < port; i++)
9159                 first_chan += parent->rxchan_per_port[i];
9160         num_chan = parent->rxchan_per_port[port];
9161
9162         for (i = first_chan; i < (first_chan + num_chan); i++) {
9163                 err = niu_ldg_assign_ldn(np, parent,
9164                                          ldg_num_map[ldg_rotor],
9165                                          LDN_RXDMA(i));
9166                 if (err)
9167                         return err;
9168                 ldg_rotor++;
9169                 if (ldg_rotor == np->num_ldg)
9170                         ldg_rotor = 0;
9171         }
9172
9173         first_chan = 0;
9174         for (i = 0; i < port; i++)
9175                 first_chan += parent->txchan_per_port[i];
9176         num_chan = parent->txchan_per_port[port];
9177         for (i = first_chan; i < (first_chan + num_chan); i++) {
9178                 err = niu_ldg_assign_ldn(np, parent,
9179                                          ldg_num_map[ldg_rotor],
9180                                          LDN_TXDMA(i));
9181                 if (err)
9182                         return err;
9183                 ldg_rotor++;
9184                 if (ldg_rotor == np->num_ldg)
9185                         ldg_rotor = 0;
9186         }
9187
9188         return 0;
9189 }
9190
9191 static void niu_ldg_free(struct niu *np)
9192 {
9193         if (np->flags & NIU_FLAGS_MSIX)
9194                 pci_disable_msix(np->pdev);
9195 }
9196
9197 static int niu_get_of_props(struct niu *np)
9198 {
9199 #ifdef CONFIG_SPARC64
9200         struct net_device *dev = np->dev;
9201         struct device_node *dp;
9202         const char *phy_type;
9203         const u8 *mac_addr;
9204         const char *model;
9205         int prop_len;
9206
9207         if (np->parent->plat_type == PLAT_TYPE_NIU)
9208                 dp = np->op->dev.of_node;
9209         else
9210                 dp = pci_device_to_OF_node(np->pdev);
9211
9212         phy_type = of_get_property(dp, "phy-type", &prop_len);
9213         if (!phy_type) {
9214                 netdev_err(dev, "%pOF: OF node lacks phy-type property\n", dp);
9215                 return -EINVAL;
9216         }
9217
9218         if (!strcmp(phy_type, "none"))
9219                 return -ENODEV;
9220
9221         strcpy(np->vpd.phy_type, phy_type);
9222
9223         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9224                 netdev_err(dev, "%pOF: Illegal phy string [%s]\n",
9225                            dp, np->vpd.phy_type);
9226                 return -EINVAL;
9227         }
9228
9229         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9230         if (!mac_addr) {
9231                 netdev_err(dev, "%pOF: OF node lacks local-mac-address property\n",
9232                            dp);
9233                 return -EINVAL;
9234         }
9235         if (prop_len != dev->addr_len) {
9236                 netdev_err(dev, "%pOF: OF MAC address prop len (%d) is wrong\n",
9237                            dp, prop_len);
9238         }
9239         memcpy(dev->dev_addr, mac_addr, dev->addr_len);
9240         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9241                 netdev_err(dev, "%pOF: OF MAC address is invalid\n", dp);
9242                 netdev_err(dev, "%pOF: [ %pM ]\n", dp, dev->dev_addr);
9243                 return -EINVAL;
9244         }
9245
9246         model = of_get_property(dp, "model", &prop_len);
9247
9248         if (model)
9249                 strcpy(np->vpd.model, model);
9250
9251         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9252                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9253                         NIU_FLAGS_HOTPLUG_PHY);
9254         }
9255
9256         return 0;
9257 #else
9258         return -EINVAL;
9259 #endif
9260 }
9261
9262 static int niu_get_invariants(struct niu *np)
9263 {
9264         int err, have_props;
9265         u32 offset;
9266
9267         err = niu_get_of_props(np);
9268         if (err == -ENODEV)
9269                 return err;
9270
9271         have_props = !err;
9272
9273         err = niu_init_mac_ipp_pcs_base(np);
9274         if (err)
9275                 return err;
9276
9277         if (have_props) {
9278                 err = niu_get_and_validate_port(np);
9279                 if (err)
9280                         return err;
9281
9282         } else  {
9283                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9284                         return -EINVAL;
9285
9286                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9287                 offset = niu_pci_vpd_offset(np);
9288                 netif_printk(np, probe, KERN_DEBUG, np->dev,
9289                              "%s() VPD offset [%08x]\n", __func__, offset);
9290                 if (offset) {
9291                         err = niu_pci_vpd_fetch(np, offset);
9292                         if (err < 0)
9293                                 return err;
9294                 }
9295                 nw64(ESPC_PIO_EN, 0);
9296
9297                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9298                         niu_pci_vpd_validate(np);
9299                         err = niu_get_and_validate_port(np);
9300                         if (err)
9301                                 return err;
9302                 }
9303
9304                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9305                         err = niu_get_and_validate_port(np);
9306                         if (err)
9307                                 return err;
9308                         err = niu_pci_probe_sprom(np);
9309                         if (err)
9310                                 return err;
9311                 }
9312         }
9313
9314         err = niu_probe_ports(np);
9315         if (err)
9316                 return err;
9317
9318         niu_ldg_init(np);
9319
9320         niu_classifier_swstate_init(np);
9321         niu_link_config_init(np);
9322
9323         err = niu_determine_phy_disposition(np);
9324         if (!err)
9325                 err = niu_init_link(np);
9326
9327         return err;
9328 }
9329
9330 static LIST_HEAD(niu_parent_list);
9331 static DEFINE_MUTEX(niu_parent_lock);
9332 static int niu_parent_index;
9333
9334 static ssize_t show_port_phy(struct device *dev,
9335                              struct device_attribute *attr, char *buf)
9336 {
9337         struct platform_device *plat_dev = to_platform_device(dev);
9338         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9339         u32 port_phy = p->port_phy;
9340         char *orig_buf = buf;
9341         int i;
9342
9343         if (port_phy == PORT_PHY_UNKNOWN ||
9344             port_phy == PORT_PHY_INVALID)
9345                 return 0;
9346
9347         for (i = 0; i < p->num_ports; i++) {
9348                 const char *type_str;
9349                 int type;
9350
9351                 type = phy_decode(port_phy, i);
9352                 if (type == PORT_TYPE_10G)
9353                         type_str = "10G";
9354                 else
9355                         type_str = "1G";
9356                 buf += sprintf(buf,
9357                                (i == 0) ? "%s" : " %s",
9358                                type_str);
9359         }
9360         buf += sprintf(buf, "\n");
9361         return buf - orig_buf;
9362 }
9363
9364 static ssize_t show_plat_type(struct device *dev,
9365                               struct device_attribute *attr, char *buf)
9366 {
9367         struct platform_device *plat_dev = to_platform_device(dev);
9368         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9369         const char *type_str;
9370
9371         switch (p->plat_type) {
9372         case PLAT_TYPE_ATLAS:
9373                 type_str = "atlas";
9374                 break;
9375         case PLAT_TYPE_NIU:
9376                 type_str = "niu";
9377                 break;
9378         case PLAT_TYPE_VF_P0:
9379                 type_str = "vf_p0";
9380                 break;
9381         case PLAT_TYPE_VF_P1:
9382                 type_str = "vf_p1";
9383                 break;
9384         default:
9385                 type_str = "unknown";
9386                 break;
9387         }
9388
9389         return sprintf(buf, "%s\n", type_str);
9390 }
9391
9392 static ssize_t __show_chan_per_port(struct device *dev,
9393                                     struct device_attribute *attr, char *buf,
9394                                     int rx)
9395 {
9396         struct platform_device *plat_dev = to_platform_device(dev);
9397         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9398         char *orig_buf = buf;
9399         u8 *arr;
9400         int i;
9401
9402         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9403
9404         for (i = 0; i < p->num_ports; i++) {
9405                 buf += sprintf(buf,
9406                                (i == 0) ? "%d" : " %d",
9407                                arr[i]);
9408         }
9409         buf += sprintf(buf, "\n");
9410
9411         return buf - orig_buf;
9412 }
9413
9414 static ssize_t show_rxchan_per_port(struct device *dev,
9415                                     struct device_attribute *attr, char *buf)
9416 {
9417         return __show_chan_per_port(dev, attr, buf, 1);
9418 }
9419
9420 static ssize_t show_txchan_per_port(struct device *dev,
9421                                     struct device_attribute *attr, char *buf)
9422 {
9423         return __show_chan_per_port(dev, attr, buf, 1);
9424 }
9425
9426 static ssize_t show_num_ports(struct device *dev,
9427                               struct device_attribute *attr, char *buf)
9428 {
9429         struct platform_device *plat_dev = to_platform_device(dev);
9430         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9431
9432         return sprintf(buf, "%d\n", p->num_ports);
9433 }
9434
9435 static struct device_attribute niu_parent_attributes[] = {
9436         __ATTR(port_phy, 0444, show_port_phy, NULL),
9437         __ATTR(plat_type, 0444, show_plat_type, NULL),
9438         __ATTR(rxchan_per_port, 0444, show_rxchan_per_port, NULL),
9439         __ATTR(txchan_per_port, 0444, show_txchan_per_port, NULL),
9440         __ATTR(num_ports, 0444, show_num_ports, NULL),
9441         {}
9442 };
9443
9444 static struct niu_parent *niu_new_parent(struct niu *np,
9445                                          union niu_parent_id *id, u8 ptype)
9446 {
9447         struct platform_device *plat_dev;
9448         struct niu_parent *p;
9449         int i;
9450
9451         plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9452                                                    NULL, 0);
9453         if (IS_ERR(plat_dev))
9454                 return NULL;
9455
9456         for (i = 0; niu_parent_attributes[i].attr.name; i++) {
9457                 int err = device_create_file(&plat_dev->dev,
9458                                              &niu_parent_attributes[i]);
9459                 if (err)
9460                         goto fail_unregister;
9461         }
9462
9463         p = kzalloc(sizeof(*p), GFP_KERNEL);
9464         if (!p)
9465                 goto fail_unregister;
9466
9467         p->index = niu_parent_index++;
9468
9469         plat_dev->dev.platform_data = p;
9470         p->plat_dev = plat_dev;
9471
9472         memcpy(&p->id, id, sizeof(*id));
9473         p->plat_type = ptype;
9474         INIT_LIST_HEAD(&p->list);
9475         atomic_set(&p->refcnt, 0);
9476         list_add(&p->list, &niu_parent_list);
9477         spin_lock_init(&p->lock);
9478
9479         p->rxdma_clock_divider = 7500;
9480
9481         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9482         if (p->plat_type == PLAT_TYPE_NIU)
9483                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9484
9485         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9486                 int index = i - CLASS_CODE_USER_PROG1;
9487
9488                 p->tcam_key[index] = TCAM_KEY_TSEL;
9489                 p->flow_key[index] = (FLOW_KEY_IPSA |
9490                                       FLOW_KEY_IPDA |
9491                                       FLOW_KEY_PROTO |
9492                                       (FLOW_KEY_L4_BYTE12 <<
9493                                        FLOW_KEY_L4_0_SHIFT) |
9494                                       (FLOW_KEY_L4_BYTE12 <<
9495                                        FLOW_KEY_L4_1_SHIFT));
9496         }
9497
9498         for (i = 0; i < LDN_MAX + 1; i++)
9499                 p->ldg_map[i] = LDG_INVALID;
9500
9501         return p;
9502
9503 fail_unregister:
9504         platform_device_unregister(plat_dev);
9505         return NULL;
9506 }
9507
9508 static struct niu_parent *niu_get_parent(struct niu *np,
9509                                          union niu_parent_id *id, u8 ptype)
9510 {
9511         struct niu_parent *p, *tmp;
9512         int port = np->port;
9513
9514         mutex_lock(&niu_parent_lock);
9515         p = NULL;
9516         list_for_each_entry(tmp, &niu_parent_list, list) {
9517                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9518                         p = tmp;
9519                         break;
9520                 }
9521         }
9522         if (!p)
9523                 p = niu_new_parent(np, id, ptype);
9524
9525         if (p) {
9526                 char port_name[8];
9527                 int err;
9528
9529                 sprintf(port_name, "port%d", port);
9530                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9531                                         &np->device->kobj,
9532                                         port_name);
9533                 if (!err) {
9534                         p->ports[port] = np;
9535                         atomic_inc(&p->refcnt);
9536                 }
9537         }
9538         mutex_unlock(&niu_parent_lock);
9539
9540         return p;
9541 }
9542
9543 static void niu_put_parent(struct niu *np)
9544 {
9545         struct niu_parent *p = np->parent;
9546         u8 port = np->port;
9547         char port_name[8];
9548
9549         BUG_ON(!p || p->ports[port] != np);
9550
9551         netif_printk(np, probe, KERN_DEBUG, np->dev,
9552                      "%s() port[%u]\n", __func__, port);
9553
9554         sprintf(port_name, "port%d", port);
9555
9556         mutex_lock(&niu_parent_lock);
9557
9558         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9559
9560         p->ports[port] = NULL;
9561         np->parent = NULL;
9562
9563         if (atomic_dec_and_test(&p->refcnt)) {
9564                 list_del(&p->list);
9565                 platform_device_unregister(p->plat_dev);
9566         }
9567
9568         mutex_unlock(&niu_parent_lock);
9569 }
9570
9571 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9572                                     u64 *handle, gfp_t flag)
9573 {
9574         dma_addr_t dh;
9575         void *ret;
9576
9577         ret = dma_alloc_coherent(dev, size, &dh, flag);
9578         if (ret)
9579                 *handle = dh;
9580         return ret;
9581 }
9582
9583 static void niu_pci_free_coherent(struct device *dev, size_t size,
9584                                   void *cpu_addr, u64 handle)
9585 {
9586         dma_free_coherent(dev, size, cpu_addr, handle);
9587 }
9588
9589 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9590                             unsigned long offset, size_t size,
9591                             enum dma_data_direction direction)
9592 {
9593         return dma_map_page(dev, page, offset, size, direction);
9594 }
9595
9596 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9597                                size_t size, enum dma_data_direction direction)
9598 {
9599         dma_unmap_page(dev, dma_address, size, direction);
9600 }
9601
9602 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9603                               size_t size,
9604                               enum dma_data_direction direction)
9605 {
9606         return dma_map_single(dev, cpu_addr, size, direction);
9607 }
9608
9609 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9610                                  size_t size,
9611                                  enum dma_data_direction direction)
9612 {
9613         dma_unmap_single(dev, dma_address, size, direction);
9614 }
9615
9616 static const struct niu_ops niu_pci_ops = {
9617         .alloc_coherent = niu_pci_alloc_coherent,
9618         .free_coherent  = niu_pci_free_coherent,
9619         .map_page       = niu_pci_map_page,
9620         .unmap_page     = niu_pci_unmap_page,
9621         .map_single     = niu_pci_map_single,
9622         .unmap_single   = niu_pci_unmap_single,
9623 };
9624
9625 static void niu_driver_version(void)
9626 {
9627         static int niu_version_printed;
9628
9629         if (niu_version_printed++ == 0)
9630                 pr_info("%s", version);
9631 }
9632
9633 static struct net_device *niu_alloc_and_init(struct device *gen_dev,
9634                                              struct pci_dev *pdev,
9635                                              struct platform_device *op,
9636                                              const struct niu_ops *ops, u8 port)
9637 {
9638         struct net_device *dev;
9639         struct niu *np;
9640
9641         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9642         if (!dev)
9643                 return NULL;
9644
9645         SET_NETDEV_DEV(dev, gen_dev);
9646
9647         np = netdev_priv(dev);
9648         np->dev = dev;
9649         np->pdev = pdev;
9650         np->op = op;
9651         np->device = gen_dev;
9652         np->ops = ops;
9653
9654         np->msg_enable = niu_debug;
9655
9656         spin_lock_init(&np->lock);
9657         INIT_WORK(&np->reset_task, niu_reset_task);
9658
9659         np->port = port;
9660
9661         return dev;
9662 }
9663
9664 static const struct net_device_ops niu_netdev_ops = {
9665         .ndo_open               = niu_open,
9666         .ndo_stop               = niu_close,
9667         .ndo_start_xmit         = niu_start_xmit,
9668         .ndo_get_stats64        = niu_get_stats,
9669         .ndo_set_rx_mode        = niu_set_rx_mode,
9670         .ndo_validate_addr      = eth_validate_addr,
9671         .ndo_set_mac_address    = niu_set_mac_addr,
9672         .ndo_do_ioctl           = niu_ioctl,
9673         .ndo_tx_timeout         = niu_tx_timeout,
9674         .ndo_change_mtu         = niu_change_mtu,
9675 };
9676
9677 static void niu_assign_netdev_ops(struct net_device *dev)
9678 {
9679         dev->netdev_ops = &niu_netdev_ops;
9680         dev->ethtool_ops = &niu_ethtool_ops;
9681         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9682 }
9683
9684 static void niu_device_announce(struct niu *np)
9685 {
9686         struct net_device *dev = np->dev;
9687
9688         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9689
9690         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9691                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9692                                 dev->name,
9693                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9694                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9695                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9696                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9697                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9698                                 np->vpd.phy_type);
9699         } else {
9700                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9701                                 dev->name,
9702                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9703                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9704                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9705                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9706                                   "COPPER")),
9707                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9708                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9709                                 np->vpd.phy_type);
9710         }
9711 }
9712
9713 static void niu_set_basic_features(struct net_device *dev)
9714 {
9715         dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9716         dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9717 }
9718
9719 static int niu_pci_init_one(struct pci_dev *pdev,
9720                             const struct pci_device_id *ent)
9721 {
9722         union niu_parent_id parent_id;
9723         struct net_device *dev;
9724         struct niu *np;
9725         int err;
9726         u64 dma_mask;
9727
9728         niu_driver_version();
9729
9730         err = pci_enable_device(pdev);
9731         if (err) {
9732                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9733                 return err;
9734         }
9735
9736         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9737             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9738                 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9739                 err = -ENODEV;
9740                 goto err_out_disable_pdev;
9741         }
9742
9743         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9744         if (err) {
9745                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9746                 goto err_out_disable_pdev;
9747         }
9748
9749         if (!pci_is_pcie(pdev)) {
9750                 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9751                 err = -ENODEV;
9752                 goto err_out_free_res;
9753         }
9754
9755         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9756                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9757         if (!dev) {
9758                 err = -ENOMEM;
9759                 goto err_out_free_res;
9760         }
9761         np = netdev_priv(dev);
9762
9763         memset(&parent_id, 0, sizeof(parent_id));
9764         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9765         parent_id.pci.bus = pdev->bus->number;
9766         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9767
9768         np->parent = niu_get_parent(np, &parent_id,
9769                                     PLAT_TYPE_ATLAS);
9770         if (!np->parent) {
9771                 err = -ENOMEM;
9772                 goto err_out_free_dev;
9773         }
9774
9775         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
9776                 PCI_EXP_DEVCTL_NOSNOOP_EN,
9777                 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
9778                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
9779                 PCI_EXP_DEVCTL_RELAX_EN);
9780
9781         dma_mask = DMA_BIT_MASK(44);
9782         err = pci_set_dma_mask(pdev, dma_mask);
9783         if (!err) {
9784                 dev->features |= NETIF_F_HIGHDMA;
9785                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9786                 if (err) {
9787                         dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9788                         goto err_out_release_parent;
9789                 }
9790         }
9791         if (err) {
9792                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9793                 if (err) {
9794                         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9795                         goto err_out_release_parent;
9796                 }
9797         }
9798
9799         niu_set_basic_features(dev);
9800
9801         dev->priv_flags |= IFF_UNICAST_FLT;
9802
9803         np->regs = pci_ioremap_bar(pdev, 0);
9804         if (!np->regs) {
9805                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9806                 err = -ENOMEM;
9807                 goto err_out_release_parent;
9808         }
9809
9810         pci_set_master(pdev);
9811         pci_save_state(pdev);
9812
9813         dev->irq = pdev->irq;
9814
9815         /* MTU range: 68 - 9216 */
9816         dev->min_mtu = ETH_MIN_MTU;
9817         dev->max_mtu = NIU_MAX_MTU;
9818
9819         niu_assign_netdev_ops(dev);
9820
9821         err = niu_get_invariants(np);
9822         if (err) {
9823                 if (err != -ENODEV)
9824                         dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9825                 goto err_out_iounmap;
9826         }
9827
9828         err = register_netdev(dev);
9829         if (err) {
9830                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9831                 goto err_out_iounmap;
9832         }
9833
9834         pci_set_drvdata(pdev, dev);
9835
9836         niu_device_announce(np);
9837
9838         return 0;
9839
9840 err_out_iounmap:
9841         if (np->regs) {
9842                 iounmap(np->regs);
9843                 np->regs = NULL;
9844         }
9845
9846 err_out_release_parent:
9847         niu_put_parent(np);
9848
9849 err_out_free_dev:
9850         free_netdev(dev);
9851
9852 err_out_free_res:
9853         pci_release_regions(pdev);
9854
9855 err_out_disable_pdev:
9856         pci_disable_device(pdev);
9857
9858         return err;
9859 }
9860
9861 static void niu_pci_remove_one(struct pci_dev *pdev)
9862 {
9863         struct net_device *dev = pci_get_drvdata(pdev);
9864
9865         if (dev) {
9866                 struct niu *np = netdev_priv(dev);
9867
9868                 unregister_netdev(dev);
9869                 if (np->regs) {
9870                         iounmap(np->regs);
9871                         np->regs = NULL;
9872                 }
9873
9874                 niu_ldg_free(np);
9875
9876                 niu_put_parent(np);
9877
9878                 free_netdev(dev);
9879                 pci_release_regions(pdev);
9880                 pci_disable_device(pdev);
9881         }
9882 }
9883
9884 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9885 {
9886         struct net_device *dev = pci_get_drvdata(pdev);
9887         struct niu *np = netdev_priv(dev);
9888         unsigned long flags;
9889
9890         if (!netif_running(dev))
9891                 return 0;
9892
9893         flush_work(&np->reset_task);
9894         niu_netif_stop(np);
9895
9896         del_timer_sync(&np->timer);
9897
9898         spin_lock_irqsave(&np->lock, flags);
9899         niu_enable_interrupts(np, 0);
9900         spin_unlock_irqrestore(&np->lock, flags);
9901
9902         netif_device_detach(dev);
9903
9904         spin_lock_irqsave(&np->lock, flags);
9905         niu_stop_hw(np);
9906         spin_unlock_irqrestore(&np->lock, flags);
9907
9908         pci_save_state(pdev);
9909
9910         return 0;
9911 }
9912
9913 static int niu_resume(struct pci_dev *pdev)
9914 {
9915         struct net_device *dev = pci_get_drvdata(pdev);
9916         struct niu *np = netdev_priv(dev);
9917         unsigned long flags;
9918         int err;
9919
9920         if (!netif_running(dev))
9921                 return 0;
9922
9923         pci_restore_state(pdev);
9924
9925         netif_device_attach(dev);
9926
9927         spin_lock_irqsave(&np->lock, flags);
9928
9929         err = niu_init_hw(np);
9930         if (!err) {
9931                 np->timer.expires = jiffies + HZ;
9932                 add_timer(&np->timer);
9933                 niu_netif_start(np);
9934         }
9935
9936         spin_unlock_irqrestore(&np->lock, flags);
9937
9938         return err;
9939 }
9940
9941 static struct pci_driver niu_pci_driver = {
9942         .name           = DRV_MODULE_NAME,
9943         .id_table       = niu_pci_tbl,
9944         .probe          = niu_pci_init_one,
9945         .remove         = niu_pci_remove_one,
9946         .suspend        = niu_suspend,
9947         .resume         = niu_resume,
9948 };
9949
9950 #ifdef CONFIG_SPARC64
9951 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9952                                      u64 *dma_addr, gfp_t flag)
9953 {
9954         unsigned long order = get_order(size);
9955         unsigned long page = __get_free_pages(flag, order);
9956
9957         if (page == 0UL)
9958                 return NULL;
9959         memset((char *)page, 0, PAGE_SIZE << order);
9960         *dma_addr = __pa(page);
9961
9962         return (void *) page;
9963 }
9964
9965 static void niu_phys_free_coherent(struct device *dev, size_t size,
9966                                    void *cpu_addr, u64 handle)
9967 {
9968         unsigned long order = get_order(size);
9969
9970         free_pages((unsigned long) cpu_addr, order);
9971 }
9972
9973 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9974                              unsigned long offset, size_t size,
9975                              enum dma_data_direction direction)
9976 {
9977         return page_to_phys(page) + offset;
9978 }
9979
9980 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9981                                 size_t size, enum dma_data_direction direction)
9982 {
9983         /* Nothing to do.  */
9984 }
9985
9986 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9987                                size_t size,
9988                                enum dma_data_direction direction)
9989 {
9990         return __pa(cpu_addr);
9991 }
9992
9993 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9994                                   size_t size,
9995                                   enum dma_data_direction direction)
9996 {
9997         /* Nothing to do.  */
9998 }
9999
10000 static const struct niu_ops niu_phys_ops = {
10001         .alloc_coherent = niu_phys_alloc_coherent,
10002         .free_coherent  = niu_phys_free_coherent,
10003         .map_page       = niu_phys_map_page,
10004         .unmap_page     = niu_phys_unmap_page,
10005         .map_single     = niu_phys_map_single,
10006         .unmap_single   = niu_phys_unmap_single,
10007 };
10008
10009 static int niu_of_probe(struct platform_device *op)
10010 {
10011         union niu_parent_id parent_id;
10012         struct net_device *dev;
10013         struct niu *np;
10014         const u32 *reg;
10015         int err;
10016
10017         niu_driver_version();
10018
10019         reg = of_get_property(op->dev.of_node, "reg", NULL);
10020         if (!reg) {
10021                 dev_err(&op->dev, "%pOF: No 'reg' property, aborting\n",
10022                         op->dev.of_node);
10023                 return -ENODEV;
10024         }
10025
10026         dev = niu_alloc_and_init(&op->dev, NULL, op,
10027                                  &niu_phys_ops, reg[0] & 0x1);
10028         if (!dev) {
10029                 err = -ENOMEM;
10030                 goto err_out;
10031         }
10032         np = netdev_priv(dev);
10033
10034         memset(&parent_id, 0, sizeof(parent_id));
10035         parent_id.of = of_get_parent(op->dev.of_node);
10036
10037         np->parent = niu_get_parent(np, &parent_id,
10038                                     PLAT_TYPE_NIU);
10039         if (!np->parent) {
10040                 err = -ENOMEM;
10041                 goto err_out_free_dev;
10042         }
10043
10044         niu_set_basic_features(dev);
10045
10046         np->regs = of_ioremap(&op->resource[1], 0,
10047                               resource_size(&op->resource[1]),
10048                               "niu regs");
10049         if (!np->regs) {
10050                 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10051                 err = -ENOMEM;
10052                 goto err_out_release_parent;
10053         }
10054
10055         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10056                                     resource_size(&op->resource[2]),
10057                                     "niu vregs-1");
10058         if (!np->vir_regs_1) {
10059                 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10060                 err = -ENOMEM;
10061                 goto err_out_iounmap;
10062         }
10063
10064         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10065                                     resource_size(&op->resource[3]),
10066                                     "niu vregs-2");
10067         if (!np->vir_regs_2) {
10068                 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10069                 err = -ENOMEM;
10070                 goto err_out_iounmap;
10071         }
10072
10073         niu_assign_netdev_ops(dev);
10074
10075         err = niu_get_invariants(np);
10076         if (err) {
10077                 if (err != -ENODEV)
10078                         dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10079                 goto err_out_iounmap;
10080         }
10081
10082         err = register_netdev(dev);
10083         if (err) {
10084                 dev_err(&op->dev, "Cannot register net device, aborting\n");
10085                 goto err_out_iounmap;
10086         }
10087
10088         platform_set_drvdata(op, dev);
10089
10090         niu_device_announce(np);
10091
10092         return 0;
10093
10094 err_out_iounmap:
10095         if (np->vir_regs_1) {
10096                 of_iounmap(&op->resource[2], np->vir_regs_1,
10097                            resource_size(&op->resource[2]));
10098                 np->vir_regs_1 = NULL;
10099         }
10100
10101         if (np->vir_regs_2) {
10102                 of_iounmap(&op->resource[3], np->vir_regs_2,
10103                            resource_size(&op->resource[3]));
10104                 np->vir_regs_2 = NULL;
10105         }
10106
10107         if (np->regs) {
10108                 of_iounmap(&op->resource[1], np->regs,
10109                            resource_size(&op->resource[1]));
10110                 np->regs = NULL;
10111         }
10112
10113 err_out_release_parent:
10114         niu_put_parent(np);
10115
10116 err_out_free_dev:
10117         free_netdev(dev);
10118
10119 err_out:
10120         return err;
10121 }
10122
10123 static int niu_of_remove(struct platform_device *op)
10124 {
10125         struct net_device *dev = platform_get_drvdata(op);
10126
10127         if (dev) {
10128                 struct niu *np = netdev_priv(dev);
10129
10130                 unregister_netdev(dev);
10131
10132                 if (np->vir_regs_1) {
10133                         of_iounmap(&op->resource[2], np->vir_regs_1,
10134                                    resource_size(&op->resource[2]));
10135                         np->vir_regs_1 = NULL;
10136                 }
10137
10138                 if (np->vir_regs_2) {
10139                         of_iounmap(&op->resource[3], np->vir_regs_2,
10140                                    resource_size(&op->resource[3]));
10141                         np->vir_regs_2 = NULL;
10142                 }
10143
10144                 if (np->regs) {
10145                         of_iounmap(&op->resource[1], np->regs,
10146                                    resource_size(&op->resource[1]));
10147                         np->regs = NULL;
10148                 }
10149
10150                 niu_ldg_free(np);
10151
10152                 niu_put_parent(np);
10153
10154                 free_netdev(dev);
10155         }
10156         return 0;
10157 }
10158
10159 static const struct of_device_id niu_match[] = {
10160         {
10161                 .name = "network",
10162                 .compatible = "SUNW,niusl",
10163         },
10164         {},
10165 };
10166 MODULE_DEVICE_TABLE(of, niu_match);
10167
10168 static struct platform_driver niu_of_driver = {
10169         .driver = {
10170                 .name = "niu",
10171                 .of_match_table = niu_match,
10172         },
10173         .probe          = niu_of_probe,
10174         .remove         = niu_of_remove,
10175 };
10176
10177 #endif /* CONFIG_SPARC64 */
10178
10179 static int __init niu_init(void)
10180 {
10181         int err = 0;
10182
10183         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10184
10185         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10186
10187 #ifdef CONFIG_SPARC64
10188         err = platform_driver_register(&niu_of_driver);
10189 #endif
10190
10191         if (!err) {
10192                 err = pci_register_driver(&niu_pci_driver);
10193 #ifdef CONFIG_SPARC64
10194                 if (err)
10195                         platform_driver_unregister(&niu_of_driver);
10196 #endif
10197         }
10198
10199         return err;
10200 }
10201
10202 static void __exit niu_exit(void)
10203 {
10204         pci_unregister_driver(&niu_pci_driver);
10205 #ifdef CONFIG_SPARC64
10206         platform_driver_unregister(&niu_of_driver);
10207 #endif
10208 }
10209
10210 module_init(niu_init);
10211 module_exit(niu_exit);