drivers/net/ethernet/sun/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/delay.h>
  18 #include <linux/bitops.h>
  19 #include <linux/mii.h>
  20 #include <linux/if.h>
  21 #include <linux/if_ether.h>
  22 #include <linux/if_vlan.h>
  23 #include <linux/ip.h>
  24 #include <linux/in.h>
  25 #include <linux/ipv6.h>
  26 #include <linux/log2.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/crc32.h>
  29 #include <linux/list.h>
  30 #include <linux/slab.h>
  31
  32 #include <linux/io.h>
  33 #include <linux/of_device.h>
  34
  35 #include "niu.h"
  36
  37 #define DRV_MODULE_NAME         "niu"
  38 #define DRV_MODULE_VERSION      "1.1"
  39 #define DRV_MODULE_RELDATE      "Apr 22, 2010"
  40
  41 static char version[] =
  42         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  43
  44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  45 MODULE_DESCRIPTION("NIU ethernet driver");
  46 MODULE_LICENSE("GPL");
  47 MODULE_VERSION(DRV_MODULE_VERSION);
  48
  49 #ifndef readq
  50 static u64 readq(void __iomem *reg)
  51 {
  52         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  53 }
  54
  55 static void writeq(u64 val, void __iomem *reg)
  56 {
  57         writel(val & 0xffffffff, reg);
  58         writel(val >> 32, reg + 0x4UL);
  59 }
  60 #endif
  61
  62 static const struct pci_device_id niu_pci_tbl[] = {
  63         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  64         {}
  65 };
  66
  67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  68
  69 #define NIU_TX_TIMEOUT                  (5 * HZ)
  70
  71 #define nr64(reg)               readq(np->regs + (reg))
  72 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  73
  74 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  75 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  76
  77 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  78 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  79
  80 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  81 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  82
  83 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  84 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  85
  86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  87
  88 static int niu_debug;
  89 static int debug = -1;
  90 module_param(debug, int, 0);
  91 MODULE_PARM_DESC(debug, "NIU debug level");
  92
  93 #define niu_lock_parent(np, flags) \
  94         spin_lock_irqsave(&np->parent->lock, flags)
  95 #define niu_unlock_parent(np, flags) \
  96         spin_unlock_irqrestore(&np->parent->lock, flags)
  97
  98 static int serdes_init_10g_serdes(struct niu *np);
  99
 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 101                                      u64 bits, int limit, int delay)
 102 {
 103         while (--limit >= 0) {
 104                 u64 val = nr64_mac(reg);
 105
 106                 if (!(val & bits))
 107                         break;
 108                 udelay(delay);
 109         }
 110         if (limit < 0)
 111                 return -ENODEV;
 112         return 0;
 113 }
 114
 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 116                                         u64 bits, int limit, int delay,
 117                                         const char *reg_name)
 118 {
 119         int err;
 120
 121         nw64_mac(reg, bits);
 122         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 123         if (err)
 124                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 125                            (unsigned long long)bits, reg_name,
 126                            (unsigned long long)nr64_mac(reg));
 127         return err;
 128 }
 129
 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 131 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 132         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 133 })
 134
 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 136                                      u64 bits, int limit, int delay)
 137 {
 138         while (--limit >= 0) {
 139                 u64 val = nr64_ipp(reg);
 140
 141                 if (!(val & bits))
 142                         break;
 143                 udelay(delay);
 144         }
 145         if (limit < 0)
 146                 return -ENODEV;
 147         return 0;
 148 }
 149
 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 151                                         u64 bits, int limit, int delay,
 152                                         const char *reg_name)
 153 {
 154         int err;
 155         u64 val;
 156
 157         val = nr64_ipp(reg);
 158         val |= bits;
 159         nw64_ipp(reg, val);
 160
 161         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 162         if (err)
 163                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 164                            (unsigned long long)bits, reg_name,
 165                            (unsigned long long)nr64_ipp(reg));
 166         return err;
 167 }
 168
 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 170 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 171         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 172 })
 173
 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 175                                  u64 bits, int limit, int delay)
 176 {
 177         while (--limit >= 0) {
 178                 u64 val = nr64(reg);
 179
 180                 if (!(val & bits))
 181                         break;
 182                 udelay(delay);
 183         }
 184         if (limit < 0)
 185                 return -ENODEV;
 186         return 0;
 187 }
 188
 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 190 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 191         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 192 })
 193
 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 195                                     u64 bits, int limit, int delay,
 196                                     const char *reg_name)
 197 {
 198         int err;
 199
 200         nw64(reg, bits);
 201         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 202         if (err)
 203                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 204                            (unsigned long long)bits, reg_name,
 205                            (unsigned long long)nr64(reg));
 206         return err;
 207 }
 208
 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 210 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 211         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 212 })
 213
 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 215 {
 216         u64 val = (u64) lp->timer;
 217
 218         if (on)
 219                 val |= LDG_IMGMT_ARM;
 220
 221         nw64(LDG_IMGMT(lp->ldg_num), val);
 222 }
 223
 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 225 {
 226         unsigned long mask_reg, bits;
 227         u64 val;
 228
 229         if (ldn < 0 || ldn > LDN_MAX)
 230                 return -EINVAL;
 231
 232         if (ldn < 64) {
 233                 mask_reg = LD_IM0(ldn);
 234                 bits = LD_IM0_MASK;
 235         } else {
 236                 mask_reg = LD_IM1(ldn - 64);
 237                 bits = LD_IM1_MASK;
 238         }
 239
 240         val = nr64(mask_reg);
 241         if (on)
 242                 val &= ~bits;
 243         else
 244                 val |= bits;
 245         nw64(mask_reg, val);
 246
 247         return 0;
 248 }
 249
 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 251 {
 252         struct niu_parent *parent = np->parent;
 253         int i;
 254
 255         for (i = 0; i <= LDN_MAX; i++) {
 256                 int err;
 257
 258                 if (parent->ldg_map[i] != lp->ldg_num)
 259                         continue;
 260
 261                 err = niu_ldn_irq_enable(np, i, on);
 262                 if (err)
 263                         return err;
 264         }
 265         return 0;
 266 }
 267
 268 static int niu_enable_interrupts(struct niu *np, int on)
 269 {
 270         int i;
 271
 272         for (i = 0; i < np->num_ldg; i++) {
 273                 struct niu_ldg *lp = &np->ldg[i];
 274                 int err;
 275
 276                 err = niu_enable_ldn_in_ldg(np, lp, on);
 277                 if (err)
 278                         return err;
 279         }
 280         for (i = 0; i < np->num_ldg; i++)
 281                 niu_ldg_rearm(np, &np->ldg[i], on);
 282
 283         return 0;
 284 }
 285
 286 static u32 phy_encode(u32 type, int port)
 287 {
 288         return type << (port * 2);
 289 }
 290
 291 static u32 phy_decode(u32 val, int port)
 292 {
 293         return (val >> (port * 2)) & PORT_TYPE_MASK;
 294 }
 295
 296 static int mdio_wait(struct niu *np)
 297 {
 298         int limit = 1000;
 299         u64 val;
 300
 301         while (--limit > 0) {
 302                 val = nr64(MIF_FRAME_OUTPUT);
 303                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 304                         return val & MIF_FRAME_OUTPUT_DATA;
 305
 306                 udelay(10);
 307         }
 308
 309         return -ENODEV;
 310 }
 311
 312 static int mdio_read(struct niu *np, int port, int dev, int reg)
 313 {
 314         int err;
 315
 316         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 317         err = mdio_wait(np);
 318         if (err < 0)
 319                 return err;
 320
 321         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 322         return mdio_wait(np);
 323 }
 324
 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 326 {
 327         int err;
 328
 329         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 330         err = mdio_wait(np);
 331         if (err < 0)
 332                 return err;
 333
 334         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 335         err = mdio_wait(np);
 336         if (err < 0)
 337                 return err;
 338
 339         return 0;
 340 }
 341
 342 static int mii_read(struct niu *np, int port, int reg)
 343 {
 344         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 345         return mdio_wait(np);
 346 }
 347
 348 static int mii_write(struct niu *np, int port, int reg, int data)
 349 {
 350         int err;
 351
 352         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 353         err = mdio_wait(np);
 354         if (err < 0)
 355                 return err;
 356
 357         return 0;
 358 }
 359
 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 361 {
 362         int err;
 363
 364         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 365                          ESR2_TI_PLL_TX_CFG_L(channel),
 366                          val & 0xffff);
 367         if (!err)
 368                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 369                                  ESR2_TI_PLL_TX_CFG_H(channel),
 370                                  val >> 16);
 371         return err;
 372 }
 373
 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 375 {
 376         int err;
 377
 378         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 379                          ESR2_TI_PLL_RX_CFG_L(channel),
 380                          val & 0xffff);
 381         if (!err)
 382                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 383                                  ESR2_TI_PLL_RX_CFG_H(channel),
 384                                  val >> 16);
 385         return err;
 386 }
 387
 388 /* Mode is always 10G fiber.  */
 389 static int serdes_init_niu_10g_fiber(struct niu *np)
 390 {
 391         struct niu_link_config *lp = &np->link_config;
 392         u32 tx_cfg, rx_cfg;
 393         unsigned long i;
 394
 395         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 396         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 397                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 398                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 399
 400         if (lp->loopback_mode == LOOPBACK_PHY) {
 401                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 402
 403                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 404                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 405
 406                 tx_cfg |= PLL_TX_CFG_ENTEST;
 407                 rx_cfg |= PLL_RX_CFG_ENTEST;
 408         }
 409
 410         /* Initialize all 4 lanes of the SERDES.  */
 411         for (i = 0; i < 4; i++) {
 412                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 413                 if (err)
 414                         return err;
 415         }
 416
 417         for (i = 0; i < 4; i++) {
 418                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 419                 if (err)
 420                         return err;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int serdes_init_niu_1g_serdes(struct niu *np)
 427 {
 428         struct niu_link_config *lp = &np->link_config;
 429         u16 pll_cfg, pll_sts;
 430         int max_retry = 100;
 431         u64 uninitialized_var(sig), mask, val;
 432         u32 tx_cfg, rx_cfg;
 433         unsigned long i;
 434         int err;
 435
 436         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 437                   PLL_TX_CFG_RATE_HALF);
 438         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 439                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 440                   PLL_RX_CFG_RATE_HALF);
 441
 442         if (np->port == 0)
 443                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 444
 445         if (lp->loopback_mode == LOOPBACK_PHY) {
 446                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 447
 448                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 449                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 450
 451                 tx_cfg |= PLL_TX_CFG_ENTEST;
 452                 rx_cfg |= PLL_RX_CFG_ENTEST;
 453         }
 454
 455         /* Initialize PLL for 1G */
 456         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 457
 458         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 459                          ESR2_TI_PLL_CFG_L, pll_cfg);
 460         if (err) {
 461                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 462                            np->port, __func__);
 463                 return err;
 464         }
 465
 466         pll_sts = PLL_CFG_ENPLL;
 467
 468         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                          ESR2_TI_PLL_STS_L, pll_sts);
 470         if (err) {
 471                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 472                            np->port, __func__);
 473                 return err;
 474         }
 475
 476         udelay(200);
 477
 478         /* Initialize all 4 lanes of the SERDES.  */
 479         for (i = 0; i < 4; i++) {
 480                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 481                 if (err)
 482                         return err;
 483         }
 484
 485         for (i = 0; i < 4; i++) {
 486                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 487                 if (err)
 488                         return err;
 489         }
 490
 491         switch (np->port) {
 492         case 0:
 493                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 494                 mask = val;
 495                 break;
 496
 497         case 1:
 498                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 499                 mask = val;
 500                 break;
 501
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         while (max_retry--) {
 507                 sig = nr64(ESR_INT_SIGNALS);
 508                 if ((sig & mask) == val)
 509                         break;
 510
 511                 mdelay(500);
 512         }
 513
 514         if ((sig & mask) != val) {
 515                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 516                            np->port, (int)(sig & mask), (int)val);
 517                 return -ENODEV;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int serdes_init_niu_10g_serdes(struct niu *np)
 524 {
 525         struct niu_link_config *lp = &np->link_config;
 526         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 527         int max_retry = 100;
 528         u64 uninitialized_var(sig), mask, val;
 529         unsigned long i;
 530         int err;
 531
 532         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 533         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 534                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 535                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 536
 537         if (lp->loopback_mode == LOOPBACK_PHY) {
 538                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 539
 540                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 541                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 542
 543                 tx_cfg |= PLL_TX_CFG_ENTEST;
 544                 rx_cfg |= PLL_RX_CFG_ENTEST;
 545         }
 546
 547         /* Initialize PLL for 10G */
 548         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 549
 550         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 551                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 552         if (err) {
 553                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 554                            np->port, __func__);
 555                 return err;
 556         }
 557
 558         pll_sts = PLL_CFG_ENPLL;
 559
 560         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 561                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 562         if (err) {
 563                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 564                            np->port, __func__);
 565                 return err;
 566         }
 567
 568         udelay(200);
 569
 570         /* Initialize all 4 lanes of the SERDES.  */
 571         for (i = 0; i < 4; i++) {
 572                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 573                 if (err)
 574                         return err;
 575         }
 576
 577         for (i = 0; i < 4; i++) {
 578                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 579                 if (err)
 580                         return err;
 581         }
 582
 583         /* check if serdes is ready */
 584
 585         switch (np->port) {
 586         case 0:
 587                 mask = ESR_INT_SIGNALS_P0_BITS;
 588                 val = (ESR_INT_SRDY0_P0 |
 589                        ESR_INT_DET0_P0 |
 590                        ESR_INT_XSRDY_P0 |
 591                        ESR_INT_XDP_P0_CH3 |
 592                        ESR_INT_XDP_P0_CH2 |
 593                        ESR_INT_XDP_P0_CH1 |
 594                        ESR_INT_XDP_P0_CH0);
 595                 break;
 596
 597         case 1:
 598                 mask = ESR_INT_SIGNALS_P1_BITS;
 599                 val = (ESR_INT_SRDY0_P1 |
 600                        ESR_INT_DET0_P1 |
 601                        ESR_INT_XSRDY_P1 |
 602                        ESR_INT_XDP_P1_CH3 |
 603                        ESR_INT_XDP_P1_CH2 |
 604                        ESR_INT_XDP_P1_CH1 |
 605                        ESR_INT_XDP_P1_CH0);
 606                 break;
 607
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         while (max_retry--) {
 613                 sig = nr64(ESR_INT_SIGNALS);
 614                 if ((sig & mask) == val)
 615                         break;
 616
 617                 mdelay(500);
 618         }
 619
 620         if ((sig & mask) != val) {
 621                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
 622                         np->port, (int)(sig & mask), (int)val);
 623
 624                 /* 10G failed, try initializing at 1G */
 625                 err = serdes_init_niu_1g_serdes(np);
 626                 if (!err) {
 627                         np->flags &= ~NIU_FLAGS_10G;
 628                         np->mac_xcvr = MAC_XCVR_PCS;
 629                 }  else {
 630                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
 631                                    np->port);
 632                         return -ENODEV;
 633                 }
 634         }
 635         return 0;
 636 }
 637
 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 639 {
 640         int err;
 641
 642         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 643         if (err >= 0) {
 644                 *val = (err & 0xffff);
 645                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 646                                 ESR_RXTX_CTRL_H(chan));
 647                 if (err >= 0)
 648                         *val |= ((err & 0xffff) << 16);
 649                 err = 0;
 650         }
 651         return err;
 652 }
 653
 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 655 {
 656         int err;
 657
 658         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 659                         ESR_GLUE_CTRL0_L(chan));
 660         if (err >= 0) {
 661                 *val = (err & 0xffff);
 662                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 663                                 ESR_GLUE_CTRL0_H(chan));
 664                 if (err >= 0) {
 665                         *val |= ((err & 0xffff) << 16);
 666                         err = 0;
 667                 }
 668         }
 669         return err;
 670 }
 671
 672 static int esr_read_reset(struct niu *np, u32 *val)
 673 {
 674         int err;
 675
 676         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 677                         ESR_RXTX_RESET_CTRL_L);
 678         if (err >= 0) {
 679                 *val = (err & 0xffff);
 680                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 681                                 ESR_RXTX_RESET_CTRL_H);
 682                 if (err >= 0) {
 683                         *val |= ((err & 0xffff) << 16);
 684                         err = 0;
 685                 }
 686         }
 687         return err;
 688 }
 689
 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 691 {
 692         int err;
 693
 694         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 695                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 696         if (!err)
 697                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 698                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 699         return err;
 700 }
 701
 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 703 {
 704         int err;
 705
 706         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 707                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 708         if (!err)
 709                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 710                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 711         return err;
 712 }
 713
 714 static int esr_reset(struct niu *np)
 715 {
 716         u32 uninitialized_var(reset);
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 721         if (err)
 722                 return err;
 723         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 724                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 725         if (err)
 726                 return err;
 727         udelay(200);
 728
 729         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 730                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 731         if (err)
 732                 return err;
 733         udelay(200);
 734
 735         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 736                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 737         if (err)
 738                 return err;
 739         udelay(200);
 740
 741         err = esr_read_reset(np, &reset);
 742         if (err)
 743                 return err;
 744         if (reset != 0) {
 745                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
 746                            np->port, reset);
 747                 return -ENODEV;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int serdes_init_10g(struct niu *np)
 754 {
 755         struct niu_link_config *lp = &np->link_config;
 756         unsigned long ctrl_reg, test_cfg_reg, i;
 757         u64 ctrl_val, test_cfg_val, sig, mask, val;
 758         int err;
 759
 760         switch (np->port) {
 761         case 0:
 762                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 763                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 764                 break;
 765         case 1:
 766                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 767                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 768                 break;
 769
 770         default:
 771                 return -EINVAL;
 772         }
 773         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 774                     ENET_SERDES_CTRL_SDET_1 |
 775                     ENET_SERDES_CTRL_SDET_2 |
 776                     ENET_SERDES_CTRL_SDET_3 |
 777                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 778                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 779                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 780                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 781                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 782                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 783                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 784                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 785         test_cfg_val = 0;
 786
 787         if (lp->loopback_mode == LOOPBACK_PHY) {
 788                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 789                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 790                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 791                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 792                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 793                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 794                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 795                                   ENET_SERDES_TEST_MD_3_SHIFT));
 796         }
 797
 798         nw64(ctrl_reg, ctrl_val);
 799         nw64(test_cfg_reg, test_cfg_val);
 800
 801         /* Initialize all 4 lanes of the SERDES.  */
 802         for (i = 0; i < 4; i++) {
 803                 u32 rxtx_ctrl, glue0;
 804
 805                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 806                 if (err)
 807                         return err;
 808                 err = esr_read_glue0(np, i, &glue0);
 809                 if (err)
 810                         return err;
 811
 812                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 813                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 814                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 815
 816                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 817                            ESR_GLUE_CTRL0_THCNT |
 818                            ESR_GLUE_CTRL0_BLTIME);
 819                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 820                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 821                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 822                           (BLTIME_300_CYCLES <<
 823                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 824
 825                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 826                 if (err)
 827                         return err;
 828                 err = esr_write_glue0(np, i, glue0);
 829                 if (err)
 830                         return err;
 831         }
 832
 833         err = esr_reset(np);
 834         if (err)
 835                 return err;
 836
 837         sig = nr64(ESR_INT_SIGNALS);
 838         switch (np->port) {
 839         case 0:
 840                 mask = ESR_INT_SIGNALS_P0_BITS;
 841                 val = (ESR_INT_SRDY0_P0 |
 842                        ESR_INT_DET0_P0 |
 843                        ESR_INT_XSRDY_P0 |
 844                        ESR_INT_XDP_P0_CH3 |
 845                        ESR_INT_XDP_P0_CH2 |
 846                        ESR_INT_XDP_P0_CH1 |
 847                        ESR_INT_XDP_P0_CH0);
 848                 break;
 849
 850         case 1:
 851                 mask = ESR_INT_SIGNALS_P1_BITS;
 852                 val = (ESR_INT_SRDY0_P1 |
 853                        ESR_INT_DET0_P1 |
 854                        ESR_INT_XSRDY_P1 |
 855                        ESR_INT_XDP_P1_CH3 |
 856                        ESR_INT_XDP_P1_CH2 |
 857                        ESR_INT_XDP_P1_CH1 |
 858                        ESR_INT_XDP_P1_CH0);
 859                 break;
 860
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         if ((sig & mask) != val) {
 866                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 867                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 868                         return 0;
 869                 }
 870                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 871                            np->port, (int)(sig & mask), (int)val);
 872                 return -ENODEV;
 873         }
 874         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 875                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 876         return 0;
 877 }
 878
 879 static int serdes_init_1g(struct niu *np)
 880 {
 881         u64 val;
 882
 883         val = nr64(ENET_SERDES_1_PLL_CFG);
 884         val &= ~ENET_SERDES_PLL_FBDIV2;
 885         switch (np->port) {
 886         case 0:
 887                 val |= ENET_SERDES_PLL_HRATE0;
 888                 break;
 889         case 1:
 890                 val |= ENET_SERDES_PLL_HRATE1;
 891                 break;
 892         case 2:
 893                 val |= ENET_SERDES_PLL_HRATE2;
 894                 break;
 895         case 3:
 896                 val |= ENET_SERDES_PLL_HRATE3;
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901         nw64(ENET_SERDES_1_PLL_CFG, val);
 902
 903         return 0;
 904 }
 905
 906 static int serdes_init_1g_serdes(struct niu *np)
 907 {
 908         struct niu_link_config *lp = &np->link_config;
 909         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 910         u64 ctrl_val, test_cfg_val, sig, mask, val;
 911         int err;
 912         u64 reset_val, val_rd;
 913
 914         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 915                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 916                 ENET_SERDES_PLL_FBDIV0;
 917         switch (np->port) {
 918         case 0:
 919                 reset_val =  ENET_SERDES_RESET_0;
 920                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 921                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 922                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 923                 break;
 924         case 1:
 925                 reset_val =  ENET_SERDES_RESET_1;
 926                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 927                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 928                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 929                 break;
 930
 931         default:
 932                 return -EINVAL;
 933         }
 934         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 935                     ENET_SERDES_CTRL_SDET_1 |
 936                     ENET_SERDES_CTRL_SDET_2 |
 937                     ENET_SERDES_CTRL_SDET_3 |
 938                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 939                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 940                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 941                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 942                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 943                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 944                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 945                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 946         test_cfg_val = 0;
 947
 948         if (lp->loopback_mode == LOOPBACK_PHY) {
 949                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 950                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 951                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 952                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 953                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 954                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 955                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 956                                   ENET_SERDES_TEST_MD_3_SHIFT));
 957         }
 958
 959         nw64(ENET_SERDES_RESET, reset_val);
 960         mdelay(20);
 961         val_rd = nr64(ENET_SERDES_RESET);
 962         val_rd &= ~reset_val;
 963         nw64(pll_cfg, val);
 964         nw64(ctrl_reg, ctrl_val);
 965         nw64(test_cfg_reg, test_cfg_val);
 966         nw64(ENET_SERDES_RESET, val_rd);
 967         mdelay(2000);
 968
 969         /* Initialize all 4 lanes of the SERDES.  */
 970         for (i = 0; i < 4; i++) {
 971                 u32 rxtx_ctrl, glue0;
 972
 973                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 974                 if (err)
 975                         return err;
 976                 err = esr_read_glue0(np, i, &glue0);
 977                 if (err)
 978                         return err;
 979
 980                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 981                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 982                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 983
 984                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 985                            ESR_GLUE_CTRL0_THCNT |
 986                            ESR_GLUE_CTRL0_BLTIME);
 987                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 988                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 989                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 990                           (BLTIME_300_CYCLES <<
 991                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 992
 993                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 994                 if (err)
 995                         return err;
 996                 err = esr_write_glue0(np, i, glue0);
 997                 if (err)
 998                         return err;
 999         }
1000
1001
1002         sig = nr64(ESR_INT_SIGNALS);
1003         switch (np->port) {
1004         case 0:
1005                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006                 mask = val;
1007                 break;
1008
1009         case 1:
1010                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011                 mask = val;
1012                 break;
1013
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         if ((sig & mask) != val) {
1019                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020                            np->port, (int)(sig & mask), (int)val);
1021                 return -ENODEV;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028 {
1029         struct niu_link_config *lp = &np->link_config;
1030         int link_up;
1031         u64 val;
1032         u16 current_speed;
1033         unsigned long flags;
1034         u8 current_duplex;
1035
1036         link_up = 0;
1037         current_speed = SPEED_INVALID;
1038         current_duplex = DUPLEX_INVALID;
1039
1040         spin_lock_irqsave(&np->lock, flags);
1041
1042         val = nr64_pcs(PCS_MII_STAT);
1043
1044         if (val & PCS_MII_STAT_LINK_STATUS) {
1045                 link_up = 1;
1046                 current_speed = SPEED_1000;
1047                 current_duplex = DUPLEX_FULL;
1048         }
1049
1050         lp->active_speed = current_speed;
1051         lp->active_duplex = current_duplex;
1052         spin_unlock_irqrestore(&np->lock, flags);
1053
1054         *link_up_p = link_up;
1055         return 0;
1056 }
1057
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059 {
1060         unsigned long flags;
1061         struct niu_link_config *lp = &np->link_config;
1062         int link_up = 0;
1063         int link_ok = 1;
1064         u64 val, val2;
1065         u16 current_speed;
1066         u8 current_duplex;
1067
1068         if (!(np->flags & NIU_FLAGS_10G))
1069                 return link_status_1g_serdes(np, link_up_p);
1070
1071         current_speed = SPEED_INVALID;
1072         current_duplex = DUPLEX_INVALID;
1073         spin_lock_irqsave(&np->lock, flags);
1074
1075         val = nr64_xpcs(XPCS_STATUS(0));
1076         val2 = nr64_mac(XMAC_INTER2);
1077         if (val2 & 0x01000000)
1078                 link_ok = 0;
1079
1080         if ((val & 0x1000ULL) && link_ok) {
1081                 link_up = 1;
1082                 current_speed = SPEED_10000;
1083                 current_duplex = DUPLEX_FULL;
1084         }
1085         lp->active_speed = current_speed;
1086         lp->active_duplex = current_duplex;
1087         spin_unlock_irqrestore(&np->lock, flags);
1088         *link_up_p = link_up;
1089         return 0;
1090 }
1091
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1093 {
1094         struct niu_link_config *lp = &np->link_config;
1095         int err;
1096         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097         int supported, advertising, active_speed, active_duplex;
1098
1099         err = mii_read(np, np->phy_addr, MII_BMCR);
1100         if (unlikely(err < 0))
1101                 return err;
1102         bmcr = err;
1103
1104         err = mii_read(np, np->phy_addr, MII_BMSR);
1105         if (unlikely(err < 0))
1106                 return err;
1107         bmsr = err;
1108
1109         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110         if (unlikely(err < 0))
1111                 return err;
1112         advert = err;
1113
1114         err = mii_read(np, np->phy_addr, MII_LPA);
1115         if (unlikely(err < 0))
1116                 return err;
1117         lpa = err;
1118
1119         if (likely(bmsr & BMSR_ESTATEN)) {
1120                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121                 if (unlikely(err < 0))
1122                         return err;
1123                 estatus = err;
1124
1125                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126                 if (unlikely(err < 0))
1127                         return err;
1128                 ctrl1000 = err;
1129
1130                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131                 if (unlikely(err < 0))
1132                         return err;
1133                 stat1000 = err;
1134         } else
1135                 estatus = ctrl1000 = stat1000 = 0;
1136
1137         supported = 0;
1138         if (bmsr & BMSR_ANEGCAPABLE)
1139                 supported |= SUPPORTED_Autoneg;
1140         if (bmsr & BMSR_10HALF)
1141                 supported |= SUPPORTED_10baseT_Half;
1142         if (bmsr & BMSR_10FULL)
1143                 supported |= SUPPORTED_10baseT_Full;
1144         if (bmsr & BMSR_100HALF)
1145                 supported |= SUPPORTED_100baseT_Half;
1146         if (bmsr & BMSR_100FULL)
1147                 supported |= SUPPORTED_100baseT_Full;
1148         if (estatus & ESTATUS_1000_THALF)
1149                 supported |= SUPPORTED_1000baseT_Half;
1150         if (estatus & ESTATUS_1000_TFULL)
1151                 supported |= SUPPORTED_1000baseT_Full;
1152         lp->supported = supported;
1153
1154         advertising = mii_adv_to_ethtool_adv_t(advert);
1155         advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1156
1157         if (bmcr & BMCR_ANENABLE) {
1158                 int neg, neg1000;
1159
1160                 lp->active_autoneg = 1;
1161                 advertising |= ADVERTISED_Autoneg;
1162
1163                 neg = advert & lpa;
1164                 neg1000 = (ctrl1000 << 2) & stat1000;
1165
1166                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1167                         active_speed = SPEED_1000;
1168                 else if (neg & LPA_100)
1169                         active_speed = SPEED_100;
1170                 else if (neg & (LPA_10HALF | LPA_10FULL))
1171                         active_speed = SPEED_10;
1172                 else
1173                         active_speed = SPEED_INVALID;
1174
1175                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1176                         active_duplex = DUPLEX_FULL;
1177                 else if (active_speed != SPEED_INVALID)
1178                         active_duplex = DUPLEX_HALF;
1179                 else
1180                         active_duplex = DUPLEX_INVALID;
1181         } else {
1182                 lp->active_autoneg = 0;
1183
1184                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1185                         active_speed = SPEED_1000;
1186                 else if (bmcr & BMCR_SPEED100)
1187                         active_speed = SPEED_100;
1188                 else
1189                         active_speed = SPEED_10;
1190
1191                 if (bmcr & BMCR_FULLDPLX)
1192                         active_duplex = DUPLEX_FULL;
1193                 else
1194                         active_duplex = DUPLEX_HALF;
1195         }
1196
1197         lp->active_advertising = advertising;
1198         lp->active_speed = active_speed;
1199         lp->active_duplex = active_duplex;
1200         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1201
1202         return 0;
1203 }
1204
1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1206 {
1207         struct niu_link_config *lp = &np->link_config;
1208         u16 current_speed, bmsr;
1209         unsigned long flags;
1210         u8 current_duplex;
1211         int err, link_up;
1212
1213         link_up = 0;
1214         current_speed = SPEED_INVALID;
1215         current_duplex = DUPLEX_INVALID;
1216
1217         spin_lock_irqsave(&np->lock, flags);
1218
1219         err = -EINVAL;
1220
1221         err = mii_read(np, np->phy_addr, MII_BMSR);
1222         if (err < 0)
1223                 goto out;
1224
1225         bmsr = err;
1226         if (bmsr & BMSR_LSTATUS) {
1227                 u16 adv, lpa;
1228
1229                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1230                 if (err < 0)
1231                         goto out;
1232                 adv = err;
1233
1234                 err = mii_read(np, np->phy_addr, MII_LPA);
1235                 if (err < 0)
1236                         goto out;
1237                 lpa = err;
1238
1239                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1240                 if (err < 0)
1241                         goto out;
1242                 link_up = 1;
1243                 current_speed = SPEED_1000;
1244                 current_duplex = DUPLEX_FULL;
1245
1246         }
1247         lp->active_speed = current_speed;
1248         lp->active_duplex = current_duplex;
1249         err = 0;
1250
1251 out:
1252         spin_unlock_irqrestore(&np->lock, flags);
1253
1254         *link_up_p = link_up;
1255         return err;
1256 }
1257
1258 static int link_status_1g(struct niu *np, int *link_up_p)
1259 {
1260         struct niu_link_config *lp = &np->link_config;
1261         unsigned long flags;
1262         int err;
1263
1264         spin_lock_irqsave(&np->lock, flags);
1265
1266         err = link_status_mii(np, link_up_p);
1267         lp->supported |= SUPPORTED_TP;
1268         lp->active_advertising |= ADVERTISED_TP;
1269
1270         spin_unlock_irqrestore(&np->lock, flags);
1271         return err;
1272 }
1273
1274 static int bcm8704_reset(struct niu *np)
1275 {
1276         int err, limit;
1277
1278         err = mdio_read(np, np->phy_addr,
1279                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1280         if (err < 0 || err == 0xffff)
1281                 return err;
1282         err |= BMCR_RESET;
1283         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1284                          MII_BMCR, err);
1285         if (err)
1286                 return err;
1287
1288         limit = 1000;
1289         while (--limit >= 0) {
1290                 err = mdio_read(np, np->phy_addr,
1291                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292                 if (err < 0)
1293                         return err;
1294                 if (!(err & BMCR_RESET))
1295                         break;
1296         }
1297         if (limit < 0) {
1298                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1299                            np->port, (err & 0xffff));
1300                 return -ENODEV;
1301         }
1302         return 0;
1303 }
1304
1305 /* When written, certain PHY registers need to be read back twice
1306  * in order for the bits to settle properly.
1307  */
1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1309 {
1310         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1311         if (err < 0)
1312                 return err;
1313         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1314         if (err < 0)
1315                 return err;
1316         return 0;
1317 }
1318
1319 static int bcm8706_init_user_dev3(struct niu *np)
1320 {
1321         int err;
1322
1323
1324         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1325                         BCM8704_USER_OPT_DIGITAL_CTRL);
1326         if (err < 0)
1327                 return err;
1328         err &= ~USER_ODIG_CTRL_GPIOS;
1329         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1330         err |=  USER_ODIG_CTRL_RESV2;
1331         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1332                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1333         if (err)
1334                 return err;
1335
1336         mdelay(1000);
1337
1338         return 0;
1339 }
1340
1341 static int bcm8704_init_user_dev3(struct niu *np)
1342 {
1343         int err;
1344
1345         err = mdio_write(np, np->phy_addr,
1346                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1347                          (USER_CONTROL_OPTXRST_LVL |
1348                           USER_CONTROL_OPBIASFLT_LVL |
1349                           USER_CONTROL_OBTMPFLT_LVL |
1350                           USER_CONTROL_OPPRFLT_LVL |
1351                           USER_CONTROL_OPTXFLT_LVL |
1352                           USER_CONTROL_OPRXLOS_LVL |
1353                           USER_CONTROL_OPRXFLT_LVL |
1354                           USER_CONTROL_OPTXON_LVL |
1355                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1356         if (err)
1357                 return err;
1358
1359         err = mdio_write(np, np->phy_addr,
1360                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1361                          (USER_PMD_TX_CTL_XFP_CLKEN |
1362                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1363                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1364                           USER_PMD_TX_CTL_TSCK_LPWREN));
1365         if (err)
1366                 return err;
1367
1368         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1369         if (err)
1370                 return err;
1371         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1372         if (err)
1373                 return err;
1374
1375         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1376                         BCM8704_USER_OPT_DIGITAL_CTRL);
1377         if (err < 0)
1378                 return err;
1379         err &= ~USER_ODIG_CTRL_GPIOS;
1380         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1381         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1382                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1383         if (err)
1384                 return err;
1385
1386         mdelay(1000);
1387
1388         return 0;
1389 }
1390
1391 static int mrvl88x2011_act_led(struct niu *np, int val)
1392 {
1393         int     err;
1394
1395         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1396                 MRVL88X2011_LED_8_TO_11_CTL);
1397         if (err < 0)
1398                 return err;
1399
1400         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1401         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1402
1403         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1404                           MRVL88X2011_LED_8_TO_11_CTL, err);
1405 }
1406
1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1408 {
1409         int     err;
1410
1411         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1412                         MRVL88X2011_LED_BLINK_CTL);
1413         if (err >= 0) {
1414                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1415                 err |= (rate << 4);
1416
1417                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418                                  MRVL88X2011_LED_BLINK_CTL, err);
1419         }
1420
1421         return err;
1422 }
1423
1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1425 {
1426         int     err;
1427
1428         /* Set LED functions */
1429         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1430         if (err)
1431                 return err;
1432
1433         /* led activity */
1434         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1435         if (err)
1436                 return err;
1437
1438         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1439                         MRVL88X2011_GENERAL_CTL);
1440         if (err < 0)
1441                 return err;
1442
1443         err |= MRVL88X2011_ENA_XFPREFCLK;
1444
1445         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1446                          MRVL88X2011_GENERAL_CTL, err);
1447         if (err < 0)
1448                 return err;
1449
1450         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1451                         MRVL88X2011_PMA_PMD_CTL_1);
1452         if (err < 0)
1453                 return err;
1454
1455         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1456                 err |= MRVL88X2011_LOOPBACK;
1457         else
1458                 err &= ~MRVL88X2011_LOOPBACK;
1459
1460         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1461                          MRVL88X2011_PMA_PMD_CTL_1, err);
1462         if (err < 0)
1463                 return err;
1464
1465         /* Enable PMD  */
1466         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1467                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1468 }
1469
1470
1471 static int xcvr_diag_bcm870x(struct niu *np)
1472 {
1473         u16 analog_stat0, tx_alarm_status;
1474         int err = 0;
1475
1476 #if 1
1477         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1478                         MII_STAT1000);
1479         if (err < 0)
1480                 return err;
1481         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1482
1483         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1484         if (err < 0)
1485                 return err;
1486         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1487
1488         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1489                         MII_NWAYTEST);
1490         if (err < 0)
1491                 return err;
1492         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1493 #endif
1494
1495         /* XXX dig this out it might not be so useful XXX */
1496         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1497                         BCM8704_USER_ANALOG_STATUS0);
1498         if (err < 0)
1499                 return err;
1500         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1501                         BCM8704_USER_ANALOG_STATUS0);
1502         if (err < 0)
1503                 return err;
1504         analog_stat0 = err;
1505
1506         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1507                         BCM8704_USER_TX_ALARM_STATUS);
1508         if (err < 0)
1509                 return err;
1510         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511                         BCM8704_USER_TX_ALARM_STATUS);
1512         if (err < 0)
1513                 return err;
1514         tx_alarm_status = err;
1515
1516         if (analog_stat0 != 0x03fc) {
1517                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1518                         pr_info("Port %u cable not connected or bad cable\n",
1519                                 np->port);
1520                 } else if (analog_stat0 == 0x639c) {
1521                         pr_info("Port %u optical module is bad or missing\n",
1522                                 np->port);
1523                 }
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1530 {
1531         struct niu_link_config *lp = &np->link_config;
1532         int err;
1533
1534         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1535                         MII_BMCR);
1536         if (err < 0)
1537                 return err;
1538
1539         err &= ~BMCR_LOOPBACK;
1540
1541         if (lp->loopback_mode == LOOPBACK_MAC)
1542                 err |= BMCR_LOOPBACK;
1543
1544         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1545                          MII_BMCR, err);
1546         if (err)
1547                 return err;
1548
1549         return 0;
1550 }
1551
1552 static int xcvr_init_10g_bcm8706(struct niu *np)
1553 {
1554         int err = 0;
1555         u64 val;
1556
1557         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1558             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1559                         return err;
1560
1561         val = nr64_mac(XMAC_CONFIG);
1562         val &= ~XMAC_CONFIG_LED_POLARITY;
1563         val |= XMAC_CONFIG_FORCE_LED_ON;
1564         nw64_mac(XMAC_CONFIG, val);
1565
1566         val = nr64(MIF_CONFIG);
1567         val |= MIF_CONFIG_INDIRECT_MODE;
1568         nw64(MIF_CONFIG, val);
1569
1570         err = bcm8704_reset(np);
1571         if (err)
1572                 return err;
1573
1574         err = xcvr_10g_set_lb_bcm870x(np);
1575         if (err)
1576                 return err;
1577
1578         err = bcm8706_init_user_dev3(np);
1579         if (err)
1580                 return err;
1581
1582         err = xcvr_diag_bcm870x(np);
1583         if (err)
1584                 return err;
1585
1586         return 0;
1587 }
1588
1589 static int xcvr_init_10g_bcm8704(struct niu *np)
1590 {
1591         int err;
1592
1593         err = bcm8704_reset(np);
1594         if (err)
1595                 return err;
1596
1597         err = bcm8704_init_user_dev3(np);
1598         if (err)
1599                 return err;
1600
1601         err = xcvr_10g_set_lb_bcm870x(np);
1602         if (err)
1603                 return err;
1604
1605         err =  xcvr_diag_bcm870x(np);
1606         if (err)
1607                 return err;
1608
1609         return 0;
1610 }
1611
1612 static int xcvr_init_10g(struct niu *np)
1613 {
1614         int phy_id, err;
1615         u64 val;
1616
1617         val = nr64_mac(XMAC_CONFIG);
1618         val &= ~XMAC_CONFIG_LED_POLARITY;
1619         val |= XMAC_CONFIG_FORCE_LED_ON;
1620         nw64_mac(XMAC_CONFIG, val);
1621
1622         /* XXX shared resource, lock parent XXX */
1623         val = nr64(MIF_CONFIG);
1624         val |= MIF_CONFIG_INDIRECT_MODE;
1625         nw64(MIF_CONFIG, val);
1626
1627         phy_id = phy_decode(np->parent->port_phy, np->port);
1628         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1629
1630         /* handle different phy types */
1631         switch (phy_id & NIU_PHY_ID_MASK) {
1632         case NIU_PHY_ID_MRVL88X2011:
1633                 err = xcvr_init_10g_mrvl88x2011(np);
1634                 break;
1635
1636         default: /* bcom 8704 */
1637                 err = xcvr_init_10g_bcm8704(np);
1638                 break;
1639         }
1640
1641         return err;
1642 }
1643
1644 static int mii_reset(struct niu *np)
1645 {
1646         int limit, err;
1647
1648         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1649         if (err)
1650                 return err;
1651
1652         limit = 1000;
1653         while (--limit >= 0) {
1654                 udelay(500);
1655                 err = mii_read(np, np->phy_addr, MII_BMCR);
1656                 if (err < 0)
1657                         return err;
1658                 if (!(err & BMCR_RESET))
1659                         break;
1660         }
1661         if (limit < 0) {
1662                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1663                            np->port, err);
1664                 return -ENODEV;
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int xcvr_init_1g_rgmii(struct niu *np)
1671 {
1672         int err;
1673         u64 val;
1674         u16 bmcr, bmsr, estat;
1675
1676         val = nr64(MIF_CONFIG);
1677         val &= ~MIF_CONFIG_INDIRECT_MODE;
1678         nw64(MIF_CONFIG, val);
1679
1680         err = mii_reset(np);
1681         if (err)
1682                 return err;
1683
1684         err = mii_read(np, np->phy_addr, MII_BMSR);
1685         if (err < 0)
1686                 return err;
1687         bmsr = err;
1688
1689         estat = 0;
1690         if (bmsr & BMSR_ESTATEN) {
1691                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1692                 if (err < 0)
1693                         return err;
1694                 estat = err;
1695         }
1696
1697         bmcr = 0;
1698         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1699         if (err)
1700                 return err;
1701
1702         if (bmsr & BMSR_ESTATEN) {
1703                 u16 ctrl1000 = 0;
1704
1705                 if (estat & ESTATUS_1000_TFULL)
1706                         ctrl1000 |= ADVERTISE_1000FULL;
1707                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1708                 if (err)
1709                         return err;
1710         }
1711
1712         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1713
1714         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1715         if (err)
1716                 return err;
1717
1718         err = mii_read(np, np->phy_addr, MII_BMCR);
1719         if (err < 0)
1720                 return err;
1721         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1722
1723         err = mii_read(np, np->phy_addr, MII_BMSR);
1724         if (err < 0)
1725                 return err;
1726
1727         return 0;
1728 }
1729
1730 static int mii_init_common(struct niu *np)
1731 {
1732         struct niu_link_config *lp = &np->link_config;
1733         u16 bmcr, bmsr, adv, estat;
1734         int err;
1735
1736         err = mii_reset(np);
1737         if (err)
1738                 return err;
1739
1740         err = mii_read(np, np->phy_addr, MII_BMSR);
1741         if (err < 0)
1742                 return err;
1743         bmsr = err;
1744
1745         estat = 0;
1746         if (bmsr & BMSR_ESTATEN) {
1747                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1748                 if (err < 0)
1749                         return err;
1750                 estat = err;
1751         }
1752
1753         bmcr = 0;
1754         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1755         if (err)
1756                 return err;
1757
1758         if (lp->loopback_mode == LOOPBACK_MAC) {
1759                 bmcr |= BMCR_LOOPBACK;
1760                 if (lp->active_speed == SPEED_1000)
1761                         bmcr |= BMCR_SPEED1000;
1762                 if (lp->active_duplex == DUPLEX_FULL)
1763                         bmcr |= BMCR_FULLDPLX;
1764         }
1765
1766         if (lp->loopback_mode == LOOPBACK_PHY) {
1767                 u16 aux;
1768
1769                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1770                        BCM5464R_AUX_CTL_WRITE_1);
1771                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1772                 if (err)
1773                         return err;
1774         }
1775
1776         if (lp->autoneg) {
1777                 u16 ctrl1000;
1778
1779                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1780                 if ((bmsr & BMSR_10HALF) &&
1781                         (lp->advertising & ADVERTISED_10baseT_Half))
1782                         adv |= ADVERTISE_10HALF;
1783                 if ((bmsr & BMSR_10FULL) &&
1784                         (lp->advertising & ADVERTISED_10baseT_Full))
1785                         adv |= ADVERTISE_10FULL;
1786                 if ((bmsr & BMSR_100HALF) &&
1787                         (lp->advertising & ADVERTISED_100baseT_Half))
1788                         adv |= ADVERTISE_100HALF;
1789                 if ((bmsr & BMSR_100FULL) &&
1790                         (lp->advertising & ADVERTISED_100baseT_Full))
1791                         adv |= ADVERTISE_100FULL;
1792                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1793                 if (err)
1794                         return err;
1795
1796                 if (likely(bmsr & BMSR_ESTATEN)) {
1797                         ctrl1000 = 0;
1798                         if ((estat & ESTATUS_1000_THALF) &&
1799                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1800                                 ctrl1000 |= ADVERTISE_1000HALF;
1801                         if ((estat & ESTATUS_1000_TFULL) &&
1802                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1803                                 ctrl1000 |= ADVERTISE_1000FULL;
1804                         err = mii_write(np, np->phy_addr,
1805                                         MII_CTRL1000, ctrl1000);
1806                         if (err)
1807                                 return err;
1808                 }
1809
1810                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1811         } else {
1812                 /* !lp->autoneg */
1813                 int fulldpx;
1814
1815                 if (lp->duplex == DUPLEX_FULL) {
1816                         bmcr |= BMCR_FULLDPLX;
1817                         fulldpx = 1;
1818                 } else if (lp->duplex == DUPLEX_HALF)
1819                         fulldpx = 0;
1820                 else
1821                         return -EINVAL;
1822
1823                 if (lp->speed == SPEED_1000) {
1824                         /* if X-full requested while not supported, or
1825                            X-half requested while not supported... */
1826                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1827                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1828                                 return -EINVAL;
1829                         bmcr |= BMCR_SPEED1000;
1830                 } else if (lp->speed == SPEED_100) {
1831                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1832                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1833                                 return -EINVAL;
1834                         bmcr |= BMCR_SPEED100;
1835                 } else if (lp->speed == SPEED_10) {
1836                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1837                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1838                                 return -EINVAL;
1839                 } else
1840                         return -EINVAL;
1841         }
1842
1843         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1844         if (err)
1845                 return err;
1846
1847 #if 0
1848         err = mii_read(np, np->phy_addr, MII_BMCR);
1849         if (err < 0)
1850                 return err;
1851         bmcr = err;
1852
1853         err = mii_read(np, np->phy_addr, MII_BMSR);
1854         if (err < 0)
1855                 return err;
1856         bmsr = err;
1857
1858         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1859                 np->port, bmcr, bmsr);
1860 #endif
1861
1862         return 0;
1863 }
1864
1865 static int xcvr_init_1g(struct niu *np)
1866 {
1867         u64 val;
1868
1869         /* XXX shared resource, lock parent XXX */
1870         val = nr64(MIF_CONFIG);
1871         val &= ~MIF_CONFIG_INDIRECT_MODE;
1872         nw64(MIF_CONFIG, val);
1873
1874         return mii_init_common(np);
1875 }
1876
1877 static int niu_xcvr_init(struct niu *np)
1878 {
1879         const struct niu_phy_ops *ops = np->phy_ops;
1880         int err;
1881
1882         err = 0;
1883         if (ops->xcvr_init)
1884                 err = ops->xcvr_init(np);
1885
1886         return err;
1887 }
1888
1889 static int niu_serdes_init(struct niu *np)
1890 {
1891         const struct niu_phy_ops *ops = np->phy_ops;
1892         int err;
1893
1894         err = 0;
1895         if (ops->serdes_init)
1896                 err = ops->serdes_init(np);
1897
1898         return err;
1899 }
1900
1901 static void niu_init_xif(struct niu *);
1902 static void niu_handle_led(struct niu *, int status);
1903
1904 static int niu_link_status_common(struct niu *np, int link_up)
1905 {
1906         struct niu_link_config *lp = &np->link_config;
1907         struct net_device *dev = np->dev;
1908         unsigned long flags;
1909
1910         if (!netif_carrier_ok(dev) && link_up) {
1911                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1912                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1913                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1914                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1915                            "10Mbit/sec",
1916                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1917
1918                 spin_lock_irqsave(&np->lock, flags);
1919                 niu_init_xif(np);
1920                 niu_handle_led(np, 1);
1921                 spin_unlock_irqrestore(&np->lock, flags);
1922
1923                 netif_carrier_on(dev);
1924         } else if (netif_carrier_ok(dev) && !link_up) {
1925                 netif_warn(np, link, dev, "Link is down\n");
1926                 spin_lock_irqsave(&np->lock, flags);
1927                 niu_handle_led(np, 0);
1928                 spin_unlock_irqrestore(&np->lock, flags);
1929                 netif_carrier_off(dev);
1930         }
1931
1932         return 0;
1933 }
1934
1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1936 {
1937         int err, link_up, pma_status, pcs_status;
1938
1939         link_up = 0;
1940
1941         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1942                         MRVL88X2011_10G_PMD_STATUS_2);
1943         if (err < 0)
1944                 goto out;
1945
1946         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1947         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1948                         MRVL88X2011_PMA_PMD_STATUS_1);
1949         if (err < 0)
1950                 goto out;
1951
1952         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1953
1954         /* Check PMC Register : 3.0001.2 == 1: read twice */
1955         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1956                         MRVL88X2011_PMA_PMD_STATUS_1);
1957         if (err < 0)
1958                 goto out;
1959
1960         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1961                         MRVL88X2011_PMA_PMD_STATUS_1);
1962         if (err < 0)
1963                 goto out;
1964
1965         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1966
1967         /* Check XGXS Register : 4.0018.[0-3,12] */
1968         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1969                         MRVL88X2011_10G_XGXS_LANE_STAT);
1970         if (err < 0)
1971                 goto out;
1972
1973         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1974                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1975                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1976                     0x800))
1977                 link_up = (pma_status && pcs_status) ? 1 : 0;
1978
1979         np->link_config.active_speed = SPEED_10000;
1980         np->link_config.active_duplex = DUPLEX_FULL;
1981         err = 0;
1982 out:
1983         mrvl88x2011_act_led(np, (link_up ?
1984                                  MRVL88X2011_LED_CTL_PCS_ACT :
1985                                  MRVL88X2011_LED_CTL_OFF));
1986
1987         *link_up_p = link_up;
1988         return err;
1989 }
1990
1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1992 {
1993         int err, link_up;
1994         link_up = 0;
1995
1996         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1997                         BCM8704_PMD_RCV_SIGDET);
1998         if (err < 0 || err == 0xffff)
1999                 goto out;
2000         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2001                 err = 0;
2002                 goto out;
2003         }
2004
2005         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2006                         BCM8704_PCS_10G_R_STATUS);
2007         if (err < 0)
2008                 goto out;
2009
2010         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2011                 err = 0;
2012                 goto out;
2013         }
2014
2015         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2016                         BCM8704_PHYXS_XGXS_LANE_STAT);
2017         if (err < 0)
2018                 goto out;
2019         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2020                     PHYXS_XGXS_LANE_STAT_MAGIC |
2021                     PHYXS_XGXS_LANE_STAT_PATTEST |
2022                     PHYXS_XGXS_LANE_STAT_LANE3 |
2023                     PHYXS_XGXS_LANE_STAT_LANE2 |
2024                     PHYXS_XGXS_LANE_STAT_LANE1 |
2025                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2026                 err = 0;
2027                 np->link_config.active_speed = SPEED_INVALID;
2028                 np->link_config.active_duplex = DUPLEX_INVALID;
2029                 goto out;
2030         }
2031
2032         link_up = 1;
2033         np->link_config.active_speed = SPEED_10000;
2034         np->link_config.active_duplex = DUPLEX_FULL;
2035         err = 0;
2036
2037 out:
2038         *link_up_p = link_up;
2039         return err;
2040 }
2041
2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2043 {
2044         int err, link_up;
2045
2046         link_up = 0;
2047
2048         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2049                         BCM8704_PMD_RCV_SIGDET);
2050         if (err < 0)
2051                 goto out;
2052         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2053                 err = 0;
2054                 goto out;
2055         }
2056
2057         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2058                         BCM8704_PCS_10G_R_STATUS);
2059         if (err < 0)
2060                 goto out;
2061         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2062                 err = 0;
2063                 goto out;
2064         }
2065
2066         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2067                         BCM8704_PHYXS_XGXS_LANE_STAT);
2068         if (err < 0)
2069                 goto out;
2070
2071         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2072                     PHYXS_XGXS_LANE_STAT_MAGIC |
2073                     PHYXS_XGXS_LANE_STAT_LANE3 |
2074                     PHYXS_XGXS_LANE_STAT_LANE2 |
2075                     PHYXS_XGXS_LANE_STAT_LANE1 |
2076                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2077                 err = 0;
2078                 goto out;
2079         }
2080
2081         link_up = 1;
2082         np->link_config.active_speed = SPEED_10000;
2083         np->link_config.active_duplex = DUPLEX_FULL;
2084         err = 0;
2085
2086 out:
2087         *link_up_p = link_up;
2088         return err;
2089 }
2090
2091 static int link_status_10g(struct niu *np, int *link_up_p)
2092 {
2093         unsigned long flags;
2094         int err = -EINVAL;
2095
2096         spin_lock_irqsave(&np->lock, flags);
2097
2098         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2099                 int phy_id;
2100
2101                 phy_id = phy_decode(np->parent->port_phy, np->port);
2102                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2103
2104                 /* handle different phy types */
2105                 switch (phy_id & NIU_PHY_ID_MASK) {
2106                 case NIU_PHY_ID_MRVL88X2011:
2107                         err = link_status_10g_mrvl(np, link_up_p);
2108                         break;
2109
2110                 default: /* bcom 8704 */
2111                         err = link_status_10g_bcom(np, link_up_p);
2112                         break;
2113                 }
2114         }
2115
2116         spin_unlock_irqrestore(&np->lock, flags);
2117
2118         return err;
2119 }
2120
2121 static int niu_10g_phy_present(struct niu *np)
2122 {
2123         u64 sig, mask, val;
2124
2125         sig = nr64(ESR_INT_SIGNALS);
2126         switch (np->port) {
2127         case 0:
2128                 mask = ESR_INT_SIGNALS_P0_BITS;
2129                 val = (ESR_INT_SRDY0_P0 |
2130                        ESR_INT_DET0_P0 |
2131                        ESR_INT_XSRDY_P0 |
2132                        ESR_INT_XDP_P0_CH3 |
2133                        ESR_INT_XDP_P0_CH2 |
2134                        ESR_INT_XDP_P0_CH1 |
2135                        ESR_INT_XDP_P0_CH0);
2136                 break;
2137
2138         case 1:
2139                 mask = ESR_INT_SIGNALS_P1_BITS;
2140                 val = (ESR_INT_SRDY0_P1 |
2141                        ESR_INT_DET0_P1 |
2142                        ESR_INT_XSRDY_P1 |
2143                        ESR_INT_XDP_P1_CH3 |
2144                        ESR_INT_XDP_P1_CH2 |
2145                        ESR_INT_XDP_P1_CH1 |
2146                        ESR_INT_XDP_P1_CH0);
2147                 break;
2148
2149         default:
2150                 return 0;
2151         }
2152
2153         if ((sig & mask) != val)
2154                 return 0;
2155         return 1;
2156 }
2157
2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2159 {
2160         unsigned long flags;
2161         int err = 0;
2162         int phy_present;
2163         int phy_present_prev;
2164
2165         spin_lock_irqsave(&np->lock, flags);
2166
2167         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2168                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2169                         1 : 0;
2170                 phy_present = niu_10g_phy_present(np);
2171                 if (phy_present != phy_present_prev) {
2172                         /* state change */
2173                         if (phy_present) {
2174                                 /* A NEM was just plugged in */
2175                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2176                                 if (np->phy_ops->xcvr_init)
2177                                         err = np->phy_ops->xcvr_init(np);
2178                                 if (err) {
2179                                         err = mdio_read(np, np->phy_addr,
2180                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2181                                         if (err == 0xffff) {
2182                                                 /* No mdio, back-to-back XAUI */
2183                                                 goto out;
2184                                         }
2185                                         /* debounce */
2186                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2187                                 }
2188                         } else {
2189                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2190                                 *link_up_p = 0;
2191                                 netif_warn(np, link, np->dev,
2192                                            "Hotplug PHY Removed\n");
2193                         }
2194                 }
2195 out:
2196                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2197                         err = link_status_10g_bcm8706(np, link_up_p);
2198                         if (err == 0xffff) {
2199                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2200                                 *link_up_p = 1;
2201                                 np->link_config.active_speed = SPEED_10000;
2202                                 np->link_config.active_duplex = DUPLEX_FULL;
2203                         }
2204                 }
2205         }
2206
2207         spin_unlock_irqrestore(&np->lock, flags);
2208
2209         return 0;
2210 }
2211
2212 static int niu_link_status(struct niu *np, int *link_up_p)
2213 {
2214         const struct niu_phy_ops *ops = np->phy_ops;
2215         int err;
2216
2217         err = 0;
2218         if (ops->link_status)
2219                 err = ops->link_status(np, link_up_p);
2220
2221         return err;
2222 }
2223
2224 static void niu_timer(unsigned long __opaque)
2225 {
2226         struct niu *np = (struct niu *) __opaque;
2227         unsigned long off;
2228         int err, link_up;
2229
2230         err = niu_link_status(np, &link_up);
2231         if (!err)
2232                 niu_link_status_common(np, link_up);
2233
2234         if (netif_carrier_ok(np->dev))
2235                 off = 5 * HZ;
2236         else
2237                 off = 1 * HZ;
2238         np->timer.expires = jiffies + off;
2239
2240         add_timer(&np->timer);
2241 }
2242
2243 static const struct niu_phy_ops phy_ops_10g_serdes = {
2244         .serdes_init            = serdes_init_10g_serdes,
2245         .link_status            = link_status_10g_serdes,
2246 };
2247
2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2249         .serdes_init            = serdes_init_niu_10g_serdes,
2250         .link_status            = link_status_10g_serdes,
2251 };
2252
2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2254         .serdes_init            = serdes_init_niu_1g_serdes,
2255         .link_status            = link_status_1g_serdes,
2256 };
2257
2258 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2259         .xcvr_init              = xcvr_init_1g_rgmii,
2260         .link_status            = link_status_1g_rgmii,
2261 };
2262
2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2264         .serdes_init            = serdes_init_niu_10g_fiber,
2265         .xcvr_init              = xcvr_init_10g,
2266         .link_status            = link_status_10g,
2267 };
2268
2269 static const struct niu_phy_ops phy_ops_10g_fiber = {
2270         .serdes_init            = serdes_init_10g,
2271         .xcvr_init              = xcvr_init_10g,
2272         .link_status            = link_status_10g,
2273 };
2274
2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2276         .serdes_init            = serdes_init_10g,
2277         .xcvr_init              = xcvr_init_10g_bcm8706,
2278         .link_status            = link_status_10g_hotplug,
2279 };
2280
2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2282         .serdes_init            = serdes_init_niu_10g_fiber,
2283         .xcvr_init              = xcvr_init_10g_bcm8706,
2284         .link_status            = link_status_10g_hotplug,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_10g_copper = {
2288         .serdes_init            = serdes_init_10g,
2289         .link_status            = link_status_10g, /* XXX */
2290 };
2291
2292 static const struct niu_phy_ops phy_ops_1g_fiber = {
2293         .serdes_init            = serdes_init_1g,
2294         .xcvr_init              = xcvr_init_1g,
2295         .link_status            = link_status_1g,
2296 };
2297
2298 static const struct niu_phy_ops phy_ops_1g_copper = {
2299         .xcvr_init              = xcvr_init_1g,
2300         .link_status            = link_status_1g,
2301 };
2302
2303 struct niu_phy_template {
2304         const struct niu_phy_ops        *ops;
2305         u32                             phy_addr_base;
2306 };
2307
2308 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2309         .ops            = &phy_ops_10g_fiber_niu,
2310         .phy_addr_base  = 16,
2311 };
2312
2313 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2314         .ops            = &phy_ops_10g_serdes_niu,
2315         .phy_addr_base  = 0,
2316 };
2317
2318 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2319         .ops            = &phy_ops_1g_serdes_niu,
2320         .phy_addr_base  = 0,
2321 };
2322
2323 static const struct niu_phy_template phy_template_10g_fiber = {
2324         .ops            = &phy_ops_10g_fiber,
2325         .phy_addr_base  = 8,
2326 };
2327
2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2329         .ops            = &phy_ops_10g_fiber_hotplug,
2330         .phy_addr_base  = 8,
2331 };
2332
2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2334         .ops            = &phy_ops_niu_10g_hotplug,
2335         .phy_addr_base  = 8,
2336 };
2337
2338 static const struct niu_phy_template phy_template_10g_copper = {
2339         .ops            = &phy_ops_10g_copper,
2340         .phy_addr_base  = 10,
2341 };
2342
2343 static const struct niu_phy_template phy_template_1g_fiber = {
2344         .ops            = &phy_ops_1g_fiber,
2345         .phy_addr_base  = 0,
2346 };
2347
2348 static const struct niu_phy_template phy_template_1g_copper = {
2349         .ops            = &phy_ops_1g_copper,
2350         .phy_addr_base  = 0,
2351 };
2352
2353 static const struct niu_phy_template phy_template_1g_rgmii = {
2354         .ops            = &phy_ops_1g_rgmii,
2355         .phy_addr_base  = 0,
2356 };
2357
2358 static const struct niu_phy_template phy_template_10g_serdes = {
2359         .ops            = &phy_ops_10g_serdes,
2360         .phy_addr_base  = 0,
2361 };
2362
2363 static int niu_atca_port_num[4] = {
2364         0, 0,  11, 10
2365 };
2366
2367 static int serdes_init_10g_serdes(struct niu *np)
2368 {
2369         struct niu_link_config *lp = &np->link_config;
2370         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2371         u64 ctrl_val, test_cfg_val, sig, mask, val;
2372
2373         switch (np->port) {
2374         case 0:
2375                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2376                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2377                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2378                 break;
2379         case 1:
2380                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2381                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2382                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2383                 break;
2384
2385         default:
2386                 return -EINVAL;
2387         }
2388         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2389                     ENET_SERDES_CTRL_SDET_1 |
2390                     ENET_SERDES_CTRL_SDET_2 |
2391                     ENET_SERDES_CTRL_SDET_3 |
2392                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2393                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2394                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2395                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2396                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2397                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2398                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2399                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2400         test_cfg_val = 0;
2401
2402         if (lp->loopback_mode == LOOPBACK_PHY) {
2403                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2404                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2405                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2406                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2407                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2408                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2409                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2410                                   ENET_SERDES_TEST_MD_3_SHIFT));
2411         }
2412
2413         esr_reset(np);
2414         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2415         nw64(ctrl_reg, ctrl_val);
2416         nw64(test_cfg_reg, test_cfg_val);
2417
2418         /* Initialize all 4 lanes of the SERDES.  */
2419         for (i = 0; i < 4; i++) {
2420                 u32 rxtx_ctrl, glue0;
2421                 int err;
2422
2423                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2424                 if (err)
2425                         return err;
2426                 err = esr_read_glue0(np, i, &glue0);
2427                 if (err)
2428                         return err;
2429
2430                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2431                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2432                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2433
2434                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2435                            ESR_GLUE_CTRL0_THCNT |
2436                            ESR_GLUE_CTRL0_BLTIME);
2437                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2438                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2439                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2440                           (BLTIME_300_CYCLES <<
2441                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2442
2443                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2444                 if (err)
2445                         return err;
2446                 err = esr_write_glue0(np, i, glue0);
2447                 if (err)
2448                         return err;
2449         }
2450
2451
2452         sig = nr64(ESR_INT_SIGNALS);
2453         switch (np->port) {
2454         case 0:
2455                 mask = ESR_INT_SIGNALS_P0_BITS;
2456                 val = (ESR_INT_SRDY0_P0 |
2457                        ESR_INT_DET0_P0 |
2458                        ESR_INT_XSRDY_P0 |
2459                        ESR_INT_XDP_P0_CH3 |
2460                        ESR_INT_XDP_P0_CH2 |
2461                        ESR_INT_XDP_P0_CH1 |
2462                        ESR_INT_XDP_P0_CH0);
2463                 break;
2464
2465         case 1:
2466                 mask = ESR_INT_SIGNALS_P1_BITS;
2467                 val = (ESR_INT_SRDY0_P1 |
2468                        ESR_INT_DET0_P1 |
2469                        ESR_INT_XSRDY_P1 |
2470                        ESR_INT_XDP_P1_CH3 |
2471                        ESR_INT_XDP_P1_CH2 |
2472                        ESR_INT_XDP_P1_CH1 |
2473                        ESR_INT_XDP_P1_CH0);
2474                 break;
2475
2476         default:
2477                 return -EINVAL;
2478         }
2479
2480         if ((sig & mask) != val) {
2481                 int err;
2482                 err = serdes_init_1g_serdes(np);
2483                 if (!err) {
2484                         np->flags &= ~NIU_FLAGS_10G;
2485                         np->mac_xcvr = MAC_XCVR_PCS;
2486                 }  else {
2487                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2488                                    np->port);
2489                         return -ENODEV;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 static int niu_determine_phy_disposition(struct niu *np)
2497 {
2498         struct niu_parent *parent = np->parent;
2499         u8 plat_type = parent->plat_type;
2500         const struct niu_phy_template *tp;
2501         u32 phy_addr_off = 0;
2502
2503         if (plat_type == PLAT_TYPE_NIU) {
2504                 switch (np->flags &
2505                         (NIU_FLAGS_10G |
2506                          NIU_FLAGS_FIBER |
2507                          NIU_FLAGS_XCVR_SERDES)) {
2508                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2509                         /* 10G Serdes */
2510                         tp = &phy_template_niu_10g_serdes;
2511                         break;
2512                 case NIU_FLAGS_XCVR_SERDES:
2513                         /* 1G Serdes */
2514                         tp = &phy_template_niu_1g_serdes;
2515                         break;
2516                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2517                         /* 10G Fiber */
2518                 default:
2519                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2520                                 tp = &phy_template_niu_10g_hotplug;
2521                                 if (np->port == 0)
2522                                         phy_addr_off = 8;
2523                                 if (np->port == 1)
2524                                         phy_addr_off = 12;
2525                         } else {
2526                                 tp = &phy_template_niu_10g_fiber;
2527                                 phy_addr_off += np->port;
2528                         }
2529                         break;
2530                 }
2531         } else {
2532                 switch (np->flags &
2533                         (NIU_FLAGS_10G |
2534                          NIU_FLAGS_FIBER |
2535                          NIU_FLAGS_XCVR_SERDES)) {
2536                 case 0:
2537                         /* 1G copper */
2538                         tp = &phy_template_1g_copper;
2539                         if (plat_type == PLAT_TYPE_VF_P0)
2540                                 phy_addr_off = 10;
2541                         else if (plat_type == PLAT_TYPE_VF_P1)
2542                                 phy_addr_off = 26;
2543
2544                         phy_addr_off += (np->port ^ 0x3);
2545                         break;
2546
2547                 case NIU_FLAGS_10G:
2548                         /* 10G copper */
2549                         tp = &phy_template_10g_copper;
2550                         break;
2551
2552                 case NIU_FLAGS_FIBER:
2553                         /* 1G fiber */
2554                         tp = &phy_template_1g_fiber;
2555                         break;
2556
2557                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2558                         /* 10G fiber */
2559                         tp = &phy_template_10g_fiber;
2560                         if (plat_type == PLAT_TYPE_VF_P0 ||
2561                             plat_type == PLAT_TYPE_VF_P1)
2562                                 phy_addr_off = 8;
2563                         phy_addr_off += np->port;
2564                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2565                                 tp = &phy_template_10g_fiber_hotplug;
2566                                 if (np->port == 0)
2567                                         phy_addr_off = 8;
2568                                 if (np->port == 1)
2569                                         phy_addr_off = 12;
2570                         }
2571                         break;
2572
2573                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2574                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2575                 case NIU_FLAGS_XCVR_SERDES:
2576                         switch(np->port) {
2577                         case 0:
2578                         case 1:
2579                                 tp = &phy_template_10g_serdes;
2580                                 break;
2581                         case 2:
2582                         case 3:
2583                                 tp = &phy_template_1g_rgmii;
2584                                 break;
2585                         default:
2586                                 return -EINVAL;
2587                         }
2588                         phy_addr_off = niu_atca_port_num[np->port];
2589                         break;
2590
2591                 default:
2592                         return -EINVAL;
2593                 }
2594         }
2595
2596         np->phy_ops = tp->ops;
2597         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2598
2599         return 0;
2600 }
2601
2602 static int niu_init_link(struct niu *np)
2603 {
2604         struct niu_parent *parent = np->parent;
2605         int err, ignore;
2606
2607         if (parent->plat_type == PLAT_TYPE_NIU) {
2608                 err = niu_xcvr_init(np);
2609                 if (err)
2610                         return err;
2611                 msleep(200);
2612         }
2613         err = niu_serdes_init(np);
2614         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2615                 return err;
2616         msleep(200);
2617         err = niu_xcvr_init(np);
2618         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2619                 niu_link_status(np, &ignore);
2620         return 0;
2621 }
2622
2623 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2624 {
2625         u16 reg0 = addr[4] << 8 | addr[5];
2626         u16 reg1 = addr[2] << 8 | addr[3];
2627         u16 reg2 = addr[0] << 8 | addr[1];
2628
2629         if (np->flags & NIU_FLAGS_XMAC) {
2630                 nw64_mac(XMAC_ADDR0, reg0);
2631                 nw64_mac(XMAC_ADDR1, reg1);
2632                 nw64_mac(XMAC_ADDR2, reg2);
2633         } else {
2634                 nw64_mac(BMAC_ADDR0, reg0);
2635                 nw64_mac(BMAC_ADDR1, reg1);
2636                 nw64_mac(BMAC_ADDR2, reg2);
2637         }
2638 }
2639
2640 static int niu_num_alt_addr(struct niu *np)
2641 {
2642         if (np->flags & NIU_FLAGS_XMAC)
2643                 return XMAC_NUM_ALT_ADDR;
2644         else
2645                 return BMAC_NUM_ALT_ADDR;
2646 }
2647
2648 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2649 {
2650         u16 reg0 = addr[4] << 8 | addr[5];
2651         u16 reg1 = addr[2] << 8 | addr[3];
2652         u16 reg2 = addr[0] << 8 | addr[1];
2653
2654         if (index >= niu_num_alt_addr(np))
2655                 return -EINVAL;
2656
2657         if (np->flags & NIU_FLAGS_XMAC) {
2658                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2659                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2660                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2661         } else {
2662                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2663                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2664                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2671 {
2672         unsigned long reg;
2673         u64 val, mask;
2674
2675         if (index >= niu_num_alt_addr(np))
2676                 return -EINVAL;
2677
2678         if (np->flags & NIU_FLAGS_XMAC) {
2679                 reg = XMAC_ADDR_CMPEN;
2680                 mask = 1 << index;
2681         } else {
2682                 reg = BMAC_ADDR_CMPEN;
2683                 mask = 1 << (index + 1);
2684         }
2685
2686         val = nr64_mac(reg);
2687         if (on)
2688                 val |= mask;
2689         else
2690                 val &= ~mask;
2691         nw64_mac(reg, val);
2692
2693         return 0;
2694 }
2695
2696 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2697                                    int num, int mac_pref)
2698 {
2699         u64 val = nr64_mac(reg);
2700         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2701         val |= num;
2702         if (mac_pref)
2703                 val |= HOST_INFO_MPR;
2704         nw64_mac(reg, val);
2705 }
2706
2707 static int __set_rdc_table_num(struct niu *np,
2708                                int xmac_index, int bmac_index,
2709                                int rdc_table_num, int mac_pref)
2710 {
2711         unsigned long reg;
2712
2713         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2714                 return -EINVAL;
2715         if (np->flags & NIU_FLAGS_XMAC)
2716                 reg = XMAC_HOST_INFO(xmac_index);
2717         else
2718                 reg = BMAC_HOST_INFO(bmac_index);
2719         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2720         return 0;
2721 }
2722
2723 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2724                                          int mac_pref)
2725 {
2726         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2727 }
2728
2729 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2730                                            int mac_pref)
2731 {
2732         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2733 }
2734
2735 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2736                                      int table_num, int mac_pref)
2737 {
2738         if (idx >= niu_num_alt_addr(np))
2739                 return -EINVAL;
2740         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2741 }
2742
2743 static u64 vlan_entry_set_parity(u64 reg_val)
2744 {
2745         u64 port01_mask;
2746         u64 port23_mask;
2747
2748         port01_mask = 0x00ff;
2749         port23_mask = 0xff00;
2750
2751         if (hweight64(reg_val & port01_mask) & 1)
2752                 reg_val |= ENET_VLAN_TBL_PARITY0;
2753         else
2754                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2755
2756         if (hweight64(reg_val & port23_mask) & 1)
2757                 reg_val |= ENET_VLAN_TBL_PARITY1;
2758         else
2759                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2760
2761         return reg_val;
2762 }
2763
2764 static void vlan_tbl_write(struct niu *np, unsigned long index,
2765                            int port, int vpr, int rdc_table)
2766 {
2767         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2768
2769         reg_val &= ~((ENET_VLAN_TBL_VPR |
2770                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2771                      ENET_VLAN_TBL_SHIFT(port));
2772         if (vpr)
2773                 reg_val |= (ENET_VLAN_TBL_VPR <<
2774                             ENET_VLAN_TBL_SHIFT(port));
2775         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2776
2777         reg_val = vlan_entry_set_parity(reg_val);
2778
2779         nw64(ENET_VLAN_TBL(index), reg_val);
2780 }
2781
2782 static void vlan_tbl_clear(struct niu *np)
2783 {
2784         int i;
2785
2786         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2787                 nw64(ENET_VLAN_TBL(i), 0);
2788 }
2789
2790 static int tcam_wait_bit(struct niu *np, u64 bit)
2791 {
2792         int limit = 1000;
2793
2794         while (--limit > 0) {
2795                 if (nr64(TCAM_CTL) & bit)
2796                         break;
2797                 udelay(1);
2798         }
2799         if (limit <= 0)
2800                 return -ENODEV;
2801
2802         return 0;
2803 }
2804
2805 static int tcam_flush(struct niu *np, int index)
2806 {
2807         nw64(TCAM_KEY_0, 0x00);
2808         nw64(TCAM_KEY_MASK_0, 0xff);
2809         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2810
2811         return tcam_wait_bit(np, TCAM_CTL_STAT);
2812 }
2813
2814 #if 0
2815 static int tcam_read(struct niu *np, int index,
2816                      u64 *key, u64 *mask)
2817 {
2818         int err;
2819
2820         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2821         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2822         if (!err) {
2823                 key[0] = nr64(TCAM_KEY_0);
2824                 key[1] = nr64(TCAM_KEY_1);
2825                 key[2] = nr64(TCAM_KEY_2);
2826                 key[3] = nr64(TCAM_KEY_3);
2827                 mask[0] = nr64(TCAM_KEY_MASK_0);
2828                 mask[1] = nr64(TCAM_KEY_MASK_1);
2829                 mask[2] = nr64(TCAM_KEY_MASK_2);
2830                 mask[3] = nr64(TCAM_KEY_MASK_3);
2831         }
2832         return err;
2833 }
2834 #endif
2835
2836 static int tcam_write(struct niu *np, int index,
2837                       u64 *key, u64 *mask)
2838 {
2839         nw64(TCAM_KEY_0, key[0]);
2840         nw64(TCAM_KEY_1, key[1]);
2841         nw64(TCAM_KEY_2, key[2]);
2842         nw64(TCAM_KEY_3, key[3]);
2843         nw64(TCAM_KEY_MASK_0, mask[0]);
2844         nw64(TCAM_KEY_MASK_1, mask[1]);
2845         nw64(TCAM_KEY_MASK_2, mask[2]);
2846         nw64(TCAM_KEY_MASK_3, mask[3]);
2847         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2848
2849         return tcam_wait_bit(np, TCAM_CTL_STAT);
2850 }
2851
2852 #if 0
2853 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2854 {
2855         int err;
2856
2857         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2858         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2859         if (!err)
2860                 *data = nr64(TCAM_KEY_1);
2861
2862         return err;
2863 }
2864 #endif
2865
2866 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2867 {
2868         nw64(TCAM_KEY_1, assoc_data);
2869         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2870
2871         return tcam_wait_bit(np, TCAM_CTL_STAT);
2872 }
2873
2874 static void tcam_enable(struct niu *np, int on)
2875 {
2876         u64 val = nr64(FFLP_CFG_1);
2877
2878         if (on)
2879                 val &= ~FFLP_CFG_1_TCAM_DIS;
2880         else
2881                 val |= FFLP_CFG_1_TCAM_DIS;
2882         nw64(FFLP_CFG_1, val);
2883 }
2884
2885 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2886 {
2887         u64 val = nr64(FFLP_CFG_1);
2888
2889         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2890                  FFLP_CFG_1_CAMLAT |
2891                  FFLP_CFG_1_CAMRATIO);
2892         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2893         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2894         nw64(FFLP_CFG_1, val);
2895
2896         val = nr64(FFLP_CFG_1);
2897         val |= FFLP_CFG_1_FFLPINITDONE;
2898         nw64(FFLP_CFG_1, val);
2899 }
2900
2901 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2902                                       int on)
2903 {
2904         unsigned long reg;
2905         u64 val;
2906
2907         if (class < CLASS_CODE_ETHERTYPE1 ||
2908             class > CLASS_CODE_ETHERTYPE2)
2909                 return -EINVAL;
2910
2911         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2912         val = nr64(reg);
2913         if (on)
2914                 val |= L2_CLS_VLD;
2915         else
2916                 val &= ~L2_CLS_VLD;
2917         nw64(reg, val);
2918
2919         return 0;
2920 }
2921
2922 #if 0
2923 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2924                                    u64 ether_type)
2925 {
2926         unsigned long reg;
2927         u64 val;
2928
2929         if (class < CLASS_CODE_ETHERTYPE1 ||
2930             class > CLASS_CODE_ETHERTYPE2 ||
2931             (ether_type & ~(u64)0xffff) != 0)
2932                 return -EINVAL;
2933
2934         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2935         val = nr64(reg);
2936         val &= ~L2_CLS_ETYPE;
2937         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2938         nw64(reg, val);
2939
2940         return 0;
2941 }
2942 #endif
2943
2944 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2945                                      int on)
2946 {
2947         unsigned long reg;
2948         u64 val;
2949
2950         if (class < CLASS_CODE_USER_PROG1 ||
2951             class > CLASS_CODE_USER_PROG4)
2952                 return -EINVAL;
2953
2954         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2955         val = nr64(reg);
2956         if (on)
2957                 val |= L3_CLS_VALID;
2958         else
2959                 val &= ~L3_CLS_VALID;
2960         nw64(reg, val);
2961
2962         return 0;
2963 }
2964
2965 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2966                                   int ipv6, u64 protocol_id,
2967                                   u64 tos_mask, u64 tos_val)
2968 {
2969         unsigned long reg;
2970         u64 val;
2971
2972         if (class < CLASS_CODE_USER_PROG1 ||
2973             class > CLASS_CODE_USER_PROG4 ||
2974             (protocol_id & ~(u64)0xff) != 0 ||
2975             (tos_mask & ~(u64)0xff) != 0 ||
2976             (tos_val & ~(u64)0xff) != 0)
2977                 return -EINVAL;
2978
2979         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2980         val = nr64(reg);
2981         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2982                  L3_CLS_TOSMASK | L3_CLS_TOS);
2983         if (ipv6)
2984                 val |= L3_CLS_IPVER;
2985         val |= (protocol_id << L3_CLS_PID_SHIFT);
2986         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2987         val |= (tos_val << L3_CLS_TOS_SHIFT);
2988         nw64(reg, val);
2989
2990         return 0;
2991 }
2992
2993 static int tcam_early_init(struct niu *np)
2994 {
2995         unsigned long i;
2996         int err;
2997
2998         tcam_enable(np, 0);
2999         tcam_set_lat_and_ratio(np,
3000                                DEFAULT_TCAM_LATENCY,
3001                                DEFAULT_TCAM_ACCESS_RATIO);
3002         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3003                 err = tcam_user_eth_class_enable(np, i, 0);
3004                 if (err)
3005                         return err;
3006         }
3007         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3008                 err = tcam_user_ip_class_enable(np, i, 0);
3009                 if (err)
3010                         return err;
3011         }
3012
3013         return 0;
3014 }
3015
3016 static int tcam_flush_all(struct niu *np)
3017 {
3018         unsigned long i;
3019
3020         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3021                 int err = tcam_flush(np, i);
3022                 if (err)
3023                         return err;
3024         }
3025         return 0;
3026 }
3027
3028 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3029 {
3030         return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3031 }
3032
3033 #if 0
3034 static int hash_read(struct niu *np, unsigned long partition,
3035                      unsigned long index, unsigned long num_entries,
3036                      u64 *data)
3037 {
3038         u64 val = hash_addr_regval(index, num_entries);
3039         unsigned long i;
3040
3041         if (partition >= FCRAM_NUM_PARTITIONS ||
3042             index + num_entries > FCRAM_SIZE)
3043                 return -EINVAL;
3044
3045         nw64(HASH_TBL_ADDR(partition), val);
3046         for (i = 0; i < num_entries; i++)
3047                 data[i] = nr64(HASH_TBL_DATA(partition));
3048
3049         return 0;
3050 }
3051 #endif
3052
3053 static int hash_write(struct niu *np, unsigned long partition,
3054                       unsigned long index, unsigned long num_entries,
3055                       u64 *data)
3056 {
3057         u64 val = hash_addr_regval(index, num_entries);
3058         unsigned long i;
3059
3060         if (partition >= FCRAM_NUM_PARTITIONS ||
3061             index + (num_entries * 8) > FCRAM_SIZE)
3062                 return -EINVAL;
3063
3064         nw64(HASH_TBL_ADDR(partition), val);
3065         for (i = 0; i < num_entries; i++)
3066                 nw64(HASH_TBL_DATA(partition), data[i]);
3067
3068         return 0;
3069 }
3070
3071 static void fflp_reset(struct niu *np)
3072 {
3073         u64 val;
3074
3075         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3076         udelay(10);
3077         nw64(FFLP_CFG_1, 0);
3078
3079         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3080         nw64(FFLP_CFG_1, val);
3081 }
3082
3083 static void fflp_set_timings(struct niu *np)
3084 {
3085         u64 val = nr64(FFLP_CFG_1);
3086
3087         val &= ~FFLP_CFG_1_FFLPINITDONE;
3088         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3089         nw64(FFLP_CFG_1, val);
3090
3091         val = nr64(FFLP_CFG_1);
3092         val |= FFLP_CFG_1_FFLPINITDONE;
3093         nw64(FFLP_CFG_1, val);
3094
3095         val = nr64(FCRAM_REF_TMR);
3096         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3097         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3098         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3099         nw64(FCRAM_REF_TMR, val);
3100 }
3101
3102 static int fflp_set_partition(struct niu *np, u64 partition,
3103                               u64 mask, u64 base, int enable)
3104 {
3105         unsigned long reg;
3106         u64 val;
3107
3108         if (partition >= FCRAM_NUM_PARTITIONS ||
3109             (mask & ~(u64)0x1f) != 0 ||
3110             (base & ~(u64)0x1f) != 0)
3111                 return -EINVAL;
3112
3113         reg = FLW_PRT_SEL(partition);
3114
3115         val = nr64(reg);
3116         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3117         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3118         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3119         if (enable)
3120                 val |= FLW_PRT_SEL_EXT;
3121         nw64(reg, val);
3122
3123         return 0;
3124 }
3125
3126 static int fflp_disable_all_partitions(struct niu *np)
3127 {
3128         unsigned long i;
3129
3130         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3131                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3132                 if (err)
3133                         return err;
3134         }
3135         return 0;
3136 }
3137
3138 static void fflp_llcsnap_enable(struct niu *np, int on)
3139 {
3140         u64 val = nr64(FFLP_CFG_1);
3141
3142         if (on)
3143                 val |= FFLP_CFG_1_LLCSNAP;
3144         else
3145                 val &= ~FFLP_CFG_1_LLCSNAP;
3146         nw64(FFLP_CFG_1, val);
3147 }
3148
3149 static void fflp_errors_enable(struct niu *np, int on)
3150 {
3151         u64 val = nr64(FFLP_CFG_1);
3152
3153         if (on)
3154                 val &= ~FFLP_CFG_1_ERRORDIS;
3155         else
3156                 val |= FFLP_CFG_1_ERRORDIS;
3157         nw64(FFLP_CFG_1, val);
3158 }
3159
3160 static int fflp_hash_clear(struct niu *np)
3161 {
3162         struct fcram_hash_ipv4 ent;
3163         unsigned long i;
3164
3165         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3166         memset(&ent, 0, sizeof(ent));
3167         ent.header = HASH_HEADER_EXT;
3168
3169         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3170                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3171                 if (err)
3172                         return err;
3173         }
3174         return 0;
3175 }
3176
3177 static int fflp_early_init(struct niu *np)
3178 {
3179         struct niu_parent *parent;
3180         unsigned long flags;
3181         int err;
3182
3183         niu_lock_parent(np, flags);
3184
3185         parent = np->parent;
3186         err = 0;
3187         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3188                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3189                         fflp_reset(np);
3190                         fflp_set_timings(np);
3191                         err = fflp_disable_all_partitions(np);
3192                         if (err) {
3193                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3194                                              "fflp_disable_all_partitions failed, err=%d\n",
3195                                              err);
3196                                 goto out;
3197                         }
3198                 }
3199
3200                 err = tcam_early_init(np);
3201                 if (err) {
3202                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3203                                      "tcam_early_init failed, err=%d\n", err);
3204                         goto out;
3205                 }
3206                 fflp_llcsnap_enable(np, 1);
3207                 fflp_errors_enable(np, 0);
3208                 nw64(H1POLY, 0);
3209                 nw64(H2POLY, 0);
3210
3211                 err = tcam_flush_all(np);
3212                 if (err) {
3213                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3214                                      "tcam_flush_all failed, err=%d\n", err);
3215                         goto out;
3216                 }
3217                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3218                         err = fflp_hash_clear(np);
3219                         if (err) {
3220                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3221                                              "fflp_hash_clear failed, err=%d\n",
3222                                              err);
3223                                 goto out;
3224                         }
3225                 }
3226
3227                 vlan_tbl_clear(np);
3228
3229                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3230         }
3231 out:
3232         niu_unlock_parent(np, flags);
3233         return err;
3234 }
3235
3236 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3237 {
3238         if (class_code < CLASS_CODE_USER_PROG1 ||
3239             class_code > CLASS_CODE_SCTP_IPV6)
3240                 return -EINVAL;
3241
3242         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3243         return 0;
3244 }
3245
3246 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3247 {
3248         if (class_code < CLASS_CODE_USER_PROG1 ||
3249             class_code > CLASS_CODE_SCTP_IPV6)
3250                 return -EINVAL;
3251
3252         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3253         return 0;
3254 }
3255
3256 /* Entries for the ports are interleaved in the TCAM */
3257 static u16 tcam_get_index(struct niu *np, u16 idx)
3258 {
3259         /* One entry reserved for IP fragment rule */
3260         if (idx >= (np->clas.tcam_sz - 1))
3261                 idx = 0;
3262         return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3263 }
3264
3265 static u16 tcam_get_size(struct niu *np)
3266 {
3267         /* One entry reserved for IP fragment rule */
3268         return np->clas.tcam_sz - 1;
3269 }
3270
3271 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3272 {
3273         /* One entry reserved for IP fragment rule */
3274         return np->clas.tcam_valid_entries - 1;
3275 }
3276
3277 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3278                               u32 offset, u32 size, u32 truesize)
3279 {
3280         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3281
3282         skb->len += size;
3283         skb->data_len += size;
3284         skb->truesize += truesize;
3285 }
3286
3287 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3288 {
3289         a >>= PAGE_SHIFT;
3290         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3291
3292         return a & (MAX_RBR_RING_SIZE - 1);
3293 }
3294
3295 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3296                                     struct page ***link)
3297 {
3298         unsigned int h = niu_hash_rxaddr(rp, addr);
3299         struct page *p, **pp;
3300
3301         addr &= PAGE_MASK;
3302         pp = &rp->rxhash[h];
3303         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3304                 if (p->index == addr) {
3305                         *link = pp;
3306                         goto found;
3307                 }
3308         }
3309         BUG();
3310
3311 found:
3312         return p;
3313 }
3314
3315 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3316 {
3317         unsigned int h = niu_hash_rxaddr(rp, base);
3318
3319         page->index = base;
3320         page->mapping = (struct address_space *) rp->rxhash[h];
3321         rp->rxhash[h] = page;
3322 }
3323
3324 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3325                             gfp_t mask, int start_index)
3326 {
3327         struct page *page;
3328         u64 addr;
3329         int i;
3330
3331         page = alloc_page(mask);
3332         if (!page)
3333                 return -ENOMEM;
3334
3335         addr = np->ops->map_page(np->device, page, 0,
3336                                  PAGE_SIZE, DMA_FROM_DEVICE);
3337         if (!addr) {
3338                 __free_page(page);
3339                 return -ENOMEM;
3340         }
3341
3342         niu_hash_page(rp, page, addr);
3343         if (rp->rbr_blocks_per_page > 1)
3344                 atomic_add(rp->rbr_blocks_per_page - 1, &page->_count);
3345
3346         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3347                 __le32 *rbr = &rp->rbr[start_index + i];
3348
3349                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3350                 addr += rp->rbr_block_size;
3351         }
3352
3353         return 0;
3354 }
3355
3356 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3357 {
3358         int index = rp->rbr_index;
3359
3360         rp->rbr_pending++;
3361         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3362                 int err = niu_rbr_add_page(np, rp, mask, index);
3363
3364                 if (unlikely(err)) {
3365                         rp->rbr_pending--;
3366                         return;
3367                 }
3368
3369                 rp->rbr_index += rp->rbr_blocks_per_page;
3370                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3371                 if (rp->rbr_index == rp->rbr_table_size)
3372                         rp->rbr_index = 0;
3373
3374                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3375                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3376                         rp->rbr_pending = 0;
3377                 }
3378         }
3379 }
3380
3381 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3382 {
3383         unsigned int index = rp->rcr_index;
3384         int num_rcr = 0;
3385
3386         rp->rx_dropped++;
3387         while (1) {
3388                 struct page *page, **link;
3389                 u64 addr, val;
3390                 u32 rcr_size;
3391
3392                 num_rcr++;
3393
3394                 val = le64_to_cpup(&rp->rcr[index]);
3395                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3396                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3397                 page = niu_find_rxpage(rp, addr, &link);
3398
3399                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3400                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3401                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3402                         *link = (struct page *) page->mapping;
3403                         np->ops->unmap_page(np->device, page->index,
3404                                             PAGE_SIZE, DMA_FROM_DEVICE);
3405                         page->index = 0;
3406                         page->mapping = NULL;
3407                         __free_page(page);
3408                         rp->rbr_refill_pending++;
3409                 }
3410
3411                 index = NEXT_RCR(rp, index);
3412                 if (!(val & RCR_ENTRY_MULTI))
3413                         break;
3414
3415         }
3416         rp->rcr_index = index;
3417
3418         return num_rcr;
3419 }
3420
3421 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3422                               struct rx_ring_info *rp)
3423 {
3424         unsigned int index = rp->rcr_index;
3425         struct rx_pkt_hdr1 *rh;
3426         struct sk_buff *skb;
3427         int len, num_rcr;
3428
3429         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3430         if (unlikely(!skb))
3431                 return niu_rx_pkt_ignore(np, rp);
3432
3433         num_rcr = 0;
3434         while (1) {
3435                 struct page *page, **link;
3436                 u32 rcr_size, append_size;
3437                 u64 addr, val, off;
3438
3439                 num_rcr++;
3440
3441                 val = le64_to_cpup(&rp->rcr[index]);
3442
3443                 len = (val & RCR_ENTRY_L2_LEN) >>
3444                         RCR_ENTRY_L2_LEN_SHIFT;
3445                 append_size = len + ETH_HLEN + ETH_FCS_LEN;
3446
3447                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3448                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3449                 page = niu_find_rxpage(rp, addr, &link);
3450
3451                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3452                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3453
3454                 off = addr & ~PAGE_MASK;
3455                 if (num_rcr == 1) {
3456                         int ptype;
3457
3458                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3459                         if ((ptype == RCR_PKT_TYPE_TCP ||
3460                              ptype == RCR_PKT_TYPE_UDP) &&
3461                             !(val & (RCR_ENTRY_NOPORT |
3462                                      RCR_ENTRY_ERROR)))
3463                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3464                         else
3465                                 skb_checksum_none_assert(skb);
3466                 } else if (!(val & RCR_ENTRY_MULTI))
3467                         append_size = append_size - skb->len;
3468
3469                 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3470                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3471                         *link = (struct page *) page->mapping;
3472                         np->ops->unmap_page(np->device, page->index,
3473                                             PAGE_SIZE, DMA_FROM_DEVICE);
3474                         page->index = 0;
3475                         page->mapping = NULL;
3476                         rp->rbr_refill_pending++;
3477                 } else
3478                         get_page(page);
3479
3480                 index = NEXT_RCR(rp, index);
3481                 if (!(val & RCR_ENTRY_MULTI))
3482                         break;
3483
3484         }
3485         rp->rcr_index = index;
3486
3487         len += sizeof(*rh);
3488         len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3489         __pskb_pull_tail(skb, len);
3490
3491         rh = (struct rx_pkt_hdr1 *) skb->data;
3492         if (np->dev->features & NETIF_F_RXHASH)
3493                 skb_set_hash(skb,
3494                              ((u32)rh->hashval2_0 << 24 |
3495                               (u32)rh->hashval2_1 << 16 |
3496                               (u32)rh->hashval1_1 << 8 |
3497                               (u32)rh->hashval1_2 << 0),
3498                              PKT_HASH_TYPE_L3);
3499         skb_pull(skb, sizeof(*rh));
3500
3501         rp->rx_packets++;
3502         rp->rx_bytes += skb->len;
3503
3504         skb->protocol = eth_type_trans(skb, np->dev);
3505         skb_record_rx_queue(skb, rp->rx_channel);
3506         napi_gro_receive(napi, skb);
3507
3508         return num_rcr;
3509 }
3510
3511 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3512 {
3513         int blocks_per_page = rp->rbr_blocks_per_page;
3514         int err, index = rp->rbr_index;
3515
3516         err = 0;
3517         while (index < (rp->rbr_table_size - blocks_per_page)) {
3518                 err = niu_rbr_add_page(np, rp, mask, index);
3519                 if (unlikely(err))
3520                         break;
3521
3522                 index += blocks_per_page;
3523         }
3524
3525         rp->rbr_index = index;
3526         return err;
3527 }
3528
3529 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3530 {
3531         int i;
3532
3533         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3534                 struct page *page;
3535
3536                 page = rp->rxhash[i];
3537                 while (page) {
3538                         struct page *next = (struct page *) page->mapping;
3539                         u64 base = page->index;
3540
3541                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3542                                             DMA_FROM_DEVICE);
3543                         page->index = 0;
3544                         page->mapping = NULL;
3545
3546                         __free_page(page);
3547
3548                         page = next;
3549                 }
3550         }
3551
3552         for (i = 0; i < rp->rbr_table_size; i++)
3553                 rp->rbr[i] = cpu_to_le32(0);
3554         rp->rbr_index = 0;
3555 }
3556
3557 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3558 {
3559         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3560         struct sk_buff *skb = tb->skb;
3561         struct tx_pkt_hdr *tp;
3562         u64 tx_flags;
3563         int i, len;
3564
3565         tp = (struct tx_pkt_hdr *) skb->data;
3566         tx_flags = le64_to_cpup(&tp->flags);
3567
3568         rp->tx_packets++;
3569         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3570                          ((tx_flags & TXHDR_PAD) / 2));
3571
3572         len = skb_headlen(skb);
3573         np->ops->unmap_single(np->device, tb->mapping,
3574                               len, DMA_TO_DEVICE);
3575
3576         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3577                 rp->mark_pending--;
3578
3579         tb->skb = NULL;
3580         do {
3581                 idx = NEXT_TX(rp, idx);
3582                 len -= MAX_TX_DESC_LEN;
3583         } while (len > 0);
3584
3585         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3586                 tb = &rp->tx_buffs[idx];
3587                 BUG_ON(tb->skb != NULL);
3588                 np->ops->unmap_page(np->device, tb->mapping,
3589                                     skb_frag_size(&skb_shinfo(skb)->frags[i]),
3590                                     DMA_TO_DEVICE);
3591                 idx = NEXT_TX(rp, idx);
3592         }
3593
3594         dev_kfree_skb(skb);
3595
3596         return idx;
3597 }
3598
3599 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3600
3601 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3602 {
3603         struct netdev_queue *txq;
3604         u16 pkt_cnt, tmp;
3605         int cons, index;
3606         u64 cs;
3607
3608         index = (rp - np->tx_rings);
3609         txq = netdev_get_tx_queue(np->dev, index);
3610
3611         cs = rp->tx_cs;
3612         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3613                 goto out;
3614
3615         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3616         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3617                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3618
3619         rp->last_pkt_cnt = tmp;
3620
3621         cons = rp->cons;
3622
3623         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3624                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3625
3626         while (pkt_cnt--)
3627                 cons = release_tx_packet(np, rp, cons);
3628
3629         rp->cons = cons;
3630         smp_mb();
3631
3632 out:
3633         if (unlikely(netif_tx_queue_stopped(txq) &&
3634                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3635                 __netif_tx_lock(txq, smp_processor_id());
3636                 if (netif_tx_queue_stopped(txq) &&
3637                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3638                         netif_tx_wake_queue(txq);
3639                 __netif_tx_unlock(txq);
3640         }
3641 }
3642
3643 static inline void niu_sync_rx_discard_stats(struct niu *np,
3644                                              struct rx_ring_info *rp,
3645                                              const int limit)
3646 {
3647         /* This elaborate scheme is needed for reading the RX discard
3648          * counters, as they are only 16-bit and can overflow quickly,
3649          * and because the overflow indication bit is not usable as
3650          * the counter value does not wrap, but remains at max value
3651          * 0xFFFF.
3652          *
3653          * In theory and in practice counters can be lost in between
3654          * reading nr64() and clearing the counter nw64().  For this
3655          * reason, the number of counter clearings nw64() is
3656          * limited/reduced though the limit parameter.
3657          */
3658         int rx_channel = rp->rx_channel;
3659         u32 misc, wred;
3660
3661         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3662          * following discard events: IPP (Input Port Process),
3663          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3664          * Block Ring) prefetch buffer is empty.
3665          */
3666         misc = nr64(RXMISC(rx_channel));
3667         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3668                 nw64(RXMISC(rx_channel), 0);
3669                 rp->rx_errors += misc & RXMISC_COUNT;
3670
3671                 if (unlikely(misc & RXMISC_OFLOW))
3672                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3673                                 rx_channel);
3674
3675                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3676                              "rx-%d: MISC drop=%u over=%u\n",
3677                              rx_channel, misc, misc-limit);
3678         }
3679
3680         /* WRED (Weighted Random Early Discard) by hardware */
3681         wred = nr64(RED_DIS_CNT(rx_channel));
3682         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3683                 nw64(RED_DIS_CNT(rx_channel), 0);
3684                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3685
3686                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3687                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3688
3689                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3690                              "rx-%d: WRED drop=%u over=%u\n",
3691                              rx_channel, wred, wred-limit);
3692         }
3693 }
3694
3695 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3696                        struct rx_ring_info *rp, int budget)
3697 {
3698         int qlen, rcr_done = 0, work_done = 0;
3699         struct rxdma_mailbox *mbox = rp->mbox;
3700         u64 stat;
3701
3702 #if 1
3703         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3704         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3705 #else
3706         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3707         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3708 #endif
3709         mbox->rx_dma_ctl_stat = 0;
3710         mbox->rcrstat_a = 0;
3711
3712         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3713                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3714                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3715
3716         rcr_done = work_done = 0;
3717         qlen = min(qlen, budget);
3718         while (work_done < qlen) {
3719                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3720                 work_done++;
3721         }
3722
3723         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3724                 unsigned int i;
3725
3726                 for (i = 0; i < rp->rbr_refill_pending; i++)
3727                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3728                 rp->rbr_refill_pending = 0;
3729         }
3730
3731         stat = (RX_DMA_CTL_STAT_MEX |
3732                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3733                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3734
3735         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3736
3737         /* Only sync discards stats when qlen indicate potential for drops */
3738         if (qlen > 10)
3739                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3740
3741         return work_done;
3742 }
3743
3744 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3745 {
3746         u64 v0 = lp->v0;
3747         u32 tx_vec = (v0 >> 32);
3748         u32 rx_vec = (v0 & 0xffffffff);
3749         int i, work_done = 0;
3750
3751         netif_printk(np, intr, KERN_DEBUG, np->dev,
3752                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3753
3754         for (i = 0; i < np->num_tx_rings; i++) {
3755                 struct tx_ring_info *rp = &np->tx_rings[i];
3756                 if (tx_vec & (1 << rp->tx_channel))
3757                         niu_tx_work(np, rp);
3758                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3759         }
3760
3761         for (i = 0; i < np->num_rx_rings; i++) {
3762                 struct rx_ring_info *rp = &np->rx_rings[i];
3763
3764                 if (rx_vec & (1 << rp->rx_channel)) {
3765                         int this_work_done;
3766
3767                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3768                                                      budget);
3769
3770                         budget -= this_work_done;
3771                         work_done += this_work_done;
3772                 }
3773                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3774         }
3775
3776         return work_done;
3777 }
3778
3779 static int niu_poll(struct napi_struct *napi, int budget)
3780 {
3781         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3782         struct niu *np = lp->np;
3783         int work_done;
3784
3785         work_done = niu_poll_core(np, lp, budget);
3786
3787         if (work_done < budget) {
3788                 napi_complete(napi);
3789                 niu_ldg_rearm(np, lp, 1);
3790         }
3791         return work_done;
3792 }
3793
3794 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3795                                   u64 stat)
3796 {
3797         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3798
3799         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3800                 pr_cont("RBR_TMOUT ");
3801         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3802                 pr_cont("RSP_CNT ");
3803         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3804                 pr_cont("BYTE_EN_BUS ");
3805         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3806                 pr_cont("RSP_DAT ");
3807         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3808                 pr_cont("RCR_ACK ");
3809         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3810                 pr_cont("RCR_SHA_PAR ");
3811         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3812                 pr_cont("RBR_PRE_PAR ");
3813         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3814                 pr_cont("CONFIG ");
3815         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3816                 pr_cont("RCRINCON ");
3817         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3818                 pr_cont("RCRFULL ");
3819         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3820                 pr_cont("RBRFULL ");
3821         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3822                 pr_cont("RBRLOGPAGE ");
3823         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3824                 pr_cont("CFIGLOGPAGE ");
3825         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3826                 pr_cont("DC_FIDO ");
3827
3828         pr_cont(")\n");
3829 }
3830
3831 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3832 {
3833         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3834         int err = 0;
3835
3836
3837         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3838                     RX_DMA_CTL_STAT_PORT_FATAL))
3839                 err = -EINVAL;
3840
3841         if (err) {
3842                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3843                            rp->rx_channel,
3844                            (unsigned long long) stat);
3845
3846                 niu_log_rxchan_errors(np, rp, stat);
3847         }
3848
3849         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3850              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3851
3852         return err;
3853 }
3854
3855 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3856                                   u64 cs)
3857 {
3858         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3859
3860         if (cs & TX_CS_MBOX_ERR)
3861                 pr_cont("MBOX ");
3862         if (cs & TX_CS_PKT_SIZE_ERR)
3863                 pr_cont("PKT_SIZE ");
3864         if (cs & TX_CS_TX_RING_OFLOW)
3865                 pr_cont("TX_RING_OFLOW ");
3866         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3867                 pr_cont("PREF_BUF_PAR ");
3868         if (cs & TX_CS_NACK_PREF)
3869                 pr_cont("NACK_PREF ");
3870         if (cs & TX_CS_NACK_PKT_RD)
3871                 pr_cont("NACK_PKT_RD ");
3872         if (cs & TX_CS_CONF_PART_ERR)
3873                 pr_cont("CONF_PART ");
3874         if (cs & TX_CS_PKT_PRT_ERR)
3875                 pr_cont("PKT_PTR ");
3876
3877         pr_cont(")\n");
3878 }
3879
3880 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3881 {
3882         u64 cs, logh, logl;
3883
3884         cs = nr64(TX_CS(rp->tx_channel));
3885         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3886         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3887
3888         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3889                    rp->tx_channel,
3890                    (unsigned long long)cs,
3891                    (unsigned long long)logh,
3892                    (unsigned long long)logl);
3893
3894         niu_log_txchan_errors(np, rp, cs);
3895
3896         return -ENODEV;
3897 }
3898
3899 static int niu_mif_interrupt(struct niu *np)
3900 {
3901         u64 mif_status = nr64(MIF_STATUS);
3902         int phy_mdint = 0;
3903
3904         if (np->flags & NIU_FLAGS_XMAC) {
3905                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3906
3907                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3908                         phy_mdint = 1;
3909         }
3910
3911         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3912                    (unsigned long long)mif_status, phy_mdint);
3913
3914         return -ENODEV;
3915 }
3916
3917 static void niu_xmac_interrupt(struct niu *np)
3918 {
3919         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3920         u64 val;
3921
3922         val = nr64_mac(XTXMAC_STATUS);
3923         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3924                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3925         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3926                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3927         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3928                 mp->tx_fifo_errors++;
3929         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3930                 mp->tx_overflow_errors++;
3931         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3932                 mp->tx_max_pkt_size_errors++;
3933         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3934                 mp->tx_underflow_errors++;
3935
3936         val = nr64_mac(XRXMAC_STATUS);
3937         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3938                 mp->rx_local_faults++;
3939         if (val & XRXMAC_STATUS_RFLT_DET)
3940                 mp->rx_remote_faults++;
3941         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3942                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3943         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3944                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3945         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3946                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3947         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3948                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3949         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3950                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3951         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3952                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3953         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3954                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3955         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3956                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3957         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3958                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3959         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3960                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3961         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3962                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3963         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3964                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3965         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3966                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3967         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3968                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3969         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3970                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3971         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3972                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3973         if (val & XRXMAC_STATUS_RXUFLOW)
3974                 mp->rx_underflows++;
3975         if (val & XRXMAC_STATUS_RXOFLOW)
3976                 mp->rx_overflows++;
3977
3978         val = nr64_mac(XMAC_FC_STAT);
3979         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3980                 mp->pause_off_state++;
3981         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3982                 mp->pause_on_state++;
3983         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3984                 mp->pause_received++;
3985 }
3986
3987 static void niu_bmac_interrupt(struct niu *np)
3988 {
3989         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3990         u64 val;
3991
3992         val = nr64_mac(BTXMAC_STATUS);
3993         if (val & BTXMAC_STATUS_UNDERRUN)
3994                 mp->tx_underflow_errors++;
3995         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3996                 mp->tx_max_pkt_size_errors++;
3997         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3998                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3999         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4000                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4001
4002         val = nr64_mac(BRXMAC_STATUS);
4003         if (val & BRXMAC_STATUS_OVERFLOW)
4004                 mp->rx_overflows++;
4005         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4006                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4007         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4008                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4009         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4010                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4011         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4012                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4013
4014         val = nr64_mac(BMAC_CTRL_STATUS);
4015         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4016                 mp->pause_off_state++;
4017         if (val & BMAC_CTRL_STATUS_PAUSE)
4018                 mp->pause_on_state++;
4019         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4020                 mp->pause_received++;
4021 }
4022
4023 static int niu_mac_interrupt(struct niu *np)
4024 {
4025         if (np->flags & NIU_FLAGS_XMAC)
4026                 niu_xmac_interrupt(np);
4027         else
4028                 niu_bmac_interrupt(np);
4029
4030         return 0;
4031 }
4032
4033 static void niu_log_device_error(struct niu *np, u64 stat)
4034 {
4035         netdev_err(np->dev, "Core device errors ( ");
4036
4037         if (stat & SYS_ERR_MASK_META2)
4038                 pr_cont("META2 ");
4039         if (stat & SYS_ERR_MASK_META1)
4040                 pr_cont("META1 ");
4041         if (stat & SYS_ERR_MASK_PEU)
4042                 pr_cont("PEU ");
4043         if (stat & SYS_ERR_MASK_TXC)
4044                 pr_cont("TXC ");
4045         if (stat & SYS_ERR_MASK_RDMC)
4046                 pr_cont("RDMC ");
4047         if (stat & SYS_ERR_MASK_TDMC)
4048                 pr_cont("TDMC ");
4049         if (stat & SYS_ERR_MASK_ZCP)
4050                 pr_cont("ZCP ");
4051         if (stat & SYS_ERR_MASK_FFLP)
4052                 pr_cont("FFLP ");
4053         if (stat & SYS_ERR_MASK_IPP)
4054                 pr_cont("IPP ");
4055         if (stat & SYS_ERR_MASK_MAC)
4056                 pr_cont("MAC ");
4057         if (stat & SYS_ERR_MASK_SMX)
4058                 pr_cont("SMX ");
4059
4060         pr_cont(")\n");
4061 }
4062
4063 static int niu_device_error(struct niu *np)
4064 {
4065         u64 stat = nr64(SYS_ERR_STAT);
4066
4067         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4068                    (unsigned long long)stat);
4069
4070         niu_log_device_error(np, stat);
4071
4072         return -ENODEV;
4073 }
4074
4075 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4076                               u64 v0, u64 v1, u64 v2)
4077 {
4078
4079         int i, err = 0;
4080
4081         lp->v0 = v0;
4082         lp->v1 = v1;
4083         lp->v2 = v2;
4084
4085         if (v1 & 0x00000000ffffffffULL) {
4086                 u32 rx_vec = (v1 & 0xffffffff);
4087
4088                 for (i = 0; i < np->num_rx_rings; i++) {
4089                         struct rx_ring_info *rp = &np->rx_rings[i];
4090
4091                         if (rx_vec & (1 << rp->rx_channel)) {
4092                                 int r = niu_rx_error(np, rp);
4093                                 if (r) {
4094                                         err = r;
4095                                 } else {
4096                                         if (!v0)
4097                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4098                                                      RX_DMA_CTL_STAT_MEX);
4099                                 }
4100                         }
4101                 }
4102         }
4103         if (v1 & 0x7fffffff00000000ULL) {
4104                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4105
4106                 for (i = 0; i < np->num_tx_rings; i++) {
4107                         struct tx_ring_info *rp = &np->tx_rings[i];
4108
4109                         if (tx_vec & (1 << rp->tx_channel)) {
4110                                 int r = niu_tx_error(np, rp);
4111                                 if (r)
4112                                         err = r;
4113                         }
4114                 }
4115         }
4116         if ((v0 | v1) & 0x8000000000000000ULL) {
4117                 int r = niu_mif_interrupt(np);
4118                 if (r)
4119                         err = r;
4120         }
4121         if (v2) {
4122                 if (v2 & 0x01ef) {
4123                         int r = niu_mac_interrupt(np);
4124                         if (r)
4125                                 err = r;
4126                 }
4127                 if (v2 & 0x0210) {
4128                         int r = niu_device_error(np);
4129                         if (r)
4130                                 err = r;
4131                 }
4132         }
4133
4134         if (err)
4135                 niu_enable_interrupts(np, 0);
4136
4137         return err;
4138 }
4139
4140 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4141                             int ldn)
4142 {
4143         struct rxdma_mailbox *mbox = rp->mbox;
4144         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4145
4146         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4147                       RX_DMA_CTL_STAT_RCRTO);
4148         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4149
4150         netif_printk(np, intr, KERN_DEBUG, np->dev,
4151                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4152 }
4153
4154 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4155                             int ldn)
4156 {
4157         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4158
4159         netif_printk(np, intr, KERN_DEBUG, np->dev,
4160                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4161 }
4162
4163 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4164 {
4165         struct niu_parent *parent = np->parent;
4166         u32 rx_vec, tx_vec;
4167         int i;
4168
4169         tx_vec = (v0 >> 32);
4170         rx_vec = (v0 & 0xffffffff);
4171
4172         for (i = 0; i < np->num_rx_rings; i++) {
4173                 struct rx_ring_info *rp = &np->rx_rings[i];
4174                 int ldn = LDN_RXDMA(rp->rx_channel);
4175
4176                 if (parent->ldg_map[ldn] != ldg)
4177                         continue;
4178
4179                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4180                 if (rx_vec & (1 << rp->rx_channel))
4181                         niu_rxchan_intr(np, rp, ldn);
4182         }
4183
4184         for (i = 0; i < np->num_tx_rings; i++) {
4185                 struct tx_ring_info *rp = &np->tx_rings[i];
4186                 int ldn = LDN_TXDMA(rp->tx_channel);
4187
4188                 if (parent->ldg_map[ldn] != ldg)
4189                         continue;
4190
4191                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4192                 if (tx_vec & (1 << rp->tx_channel))
4193                         niu_txchan_intr(np, rp, ldn);
4194         }
4195 }
4196
4197 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4198                               u64 v0, u64 v1, u64 v2)
4199 {
4200         if (likely(napi_schedule_prep(&lp->napi))) {
4201                 lp->v0 = v0;
4202                 lp->v1 = v1;
4203                 lp->v2 = v2;
4204                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4205                 __napi_schedule(&lp->napi);
4206         }
4207 }
4208
4209 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4210 {
4211         struct niu_ldg *lp = dev_id;
4212         struct niu *np = lp->np;
4213         int ldg = lp->ldg_num;
4214         unsigned long flags;
4215         u64 v0, v1, v2;
4216
4217         if (netif_msg_intr(np))
4218                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4219                        __func__, lp, ldg);
4220
4221         spin_lock_irqsave(&np->lock, flags);
4222
4223         v0 = nr64(LDSV0(ldg));
4224         v1 = nr64(LDSV1(ldg));
4225         v2 = nr64(LDSV2(ldg));
4226
4227         if (netif_msg_intr(np))
4228                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4229                        (unsigned long long) v0,
4230                        (unsigned long long) v1,
4231                        (unsigned long long) v2);
4232
4233         if (unlikely(!v0 && !v1 && !v2)) {
4234                 spin_unlock_irqrestore(&np->lock, flags);
4235                 return IRQ_NONE;
4236         }
4237
4238         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4239                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4240                 if (err)
4241                         goto out;
4242         }
4243         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4244                 niu_schedule_napi(np, lp, v0, v1, v2);
4245         else
4246                 niu_ldg_rearm(np, lp, 1);
4247 out:
4248         spin_unlock_irqrestore(&np->lock, flags);
4249
4250         return IRQ_HANDLED;
4251 }
4252
4253 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4254 {
4255         if (rp->mbox) {
4256                 np->ops->free_coherent(np->device,
4257                                        sizeof(struct rxdma_mailbox),
4258                                        rp->mbox, rp->mbox_dma);
4259                 rp->mbox = NULL;
4260         }
4261         if (rp->rcr) {
4262                 np->ops->free_coherent(np->device,
4263                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4264                                        rp->rcr, rp->rcr_dma);
4265                 rp->rcr = NULL;
4266                 rp->rcr_table_size = 0;
4267                 rp->rcr_index = 0;
4268         }
4269         if (rp->rbr) {
4270                 niu_rbr_free(np, rp);
4271
4272                 np->ops->free_coherent(np->device,
4273                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4274                                        rp->rbr, rp->rbr_dma);
4275                 rp->rbr = NULL;
4276                 rp->rbr_table_size = 0;
4277                 rp->rbr_index = 0;
4278         }
4279         kfree(rp->rxhash);
4280         rp->rxhash = NULL;
4281 }
4282
4283 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4284 {
4285         if (rp->mbox) {
4286                 np->ops->free_coherent(np->device,
4287                                        sizeof(struct txdma_mailbox),
4288                                        rp->mbox, rp->mbox_dma);
4289                 rp->mbox = NULL;
4290         }
4291         if (rp->descr) {
4292                 int i;
4293
4294                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4295                         if (rp->tx_buffs[i].skb)
4296                                 (void) release_tx_packet(np, rp, i);
4297                 }
4298
4299                 np->ops->free_coherent(np->device,
4300                                        MAX_TX_RING_SIZE * sizeof(__le64),
4301                                        rp->descr, rp->descr_dma);
4302                 rp->descr = NULL;
4303                 rp->pending = 0;
4304                 rp->prod = 0;
4305                 rp->cons = 0;
4306                 rp->wrap_bit = 0;
4307         }
4308 }
4309
4310 static void niu_free_channels(struct niu *np)
4311 {
4312         int i;
4313
4314         if (np->rx_rings) {
4315                 for (i = 0; i < np->num_rx_rings; i++) {
4316                         struct rx_ring_info *rp = &np->rx_rings[i];
4317
4318                         niu_free_rx_ring_info(np, rp);
4319                 }
4320                 kfree(np->rx_rings);
4321                 np->rx_rings = NULL;
4322                 np->num_rx_rings = 0;
4323         }
4324
4325         if (np->tx_rings) {
4326                 for (i = 0; i < np->num_tx_rings; i++) {
4327                         struct tx_ring_info *rp = &np->tx_rings[i];
4328
4329                         niu_free_tx_ring_info(np, rp);
4330                 }
4331                 kfree(np->tx_rings);
4332                 np->tx_rings = NULL;
4333                 np->num_tx_rings = 0;
4334         }
4335 }
4336
4337 static int niu_alloc_rx_ring_info(struct niu *np,
4338                                   struct rx_ring_info *rp)
4339 {
4340         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4341
4342         rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *),
4343                              GFP_KERNEL);
4344         if (!rp->rxhash)
4345                 return -ENOMEM;
4346
4347         rp->mbox = np->ops->alloc_coherent(np->device,
4348                                            sizeof(struct rxdma_mailbox),
4349                                            &rp->mbox_dma, GFP_KERNEL);
4350         if (!rp->mbox)
4351                 return -ENOMEM;
4352         if ((unsigned long)rp->mbox & (64UL - 1)) {
4353                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4354                            rp->mbox);
4355                 return -EINVAL;
4356         }
4357
4358         rp->rcr = np->ops->alloc_coherent(np->device,
4359                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4360                                           &rp->rcr_dma, GFP_KERNEL);
4361         if (!rp->rcr)
4362                 return -ENOMEM;
4363         if ((unsigned long)rp->rcr & (64UL - 1)) {
4364                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4365                            rp->rcr);
4366                 return -EINVAL;
4367         }
4368         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4369         rp->rcr_index = 0;
4370
4371         rp->rbr = np->ops->alloc_coherent(np->device,
4372                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4373                                           &rp->rbr_dma, GFP_KERNEL);
4374         if (!rp->rbr)
4375                 return -ENOMEM;
4376         if ((unsigned long)rp->rbr & (64UL - 1)) {
4377                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4378                            rp->rbr);
4379                 return -EINVAL;
4380         }
4381         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4382         rp->rbr_index = 0;
4383         rp->rbr_pending = 0;
4384
4385         return 0;
4386 }
4387
4388 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4389 {
4390         int mtu = np->dev->mtu;
4391
4392         /* These values are recommended by the HW designers for fair
4393          * utilization of DRR amongst the rings.
4394          */
4395         rp->max_burst = mtu + 32;
4396         if (rp->max_burst > 4096)
4397                 rp->max_burst = 4096;
4398 }
4399
4400 static int niu_alloc_tx_ring_info(struct niu *np,
4401                                   struct tx_ring_info *rp)
4402 {
4403         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4404
4405         rp->mbox = np->ops->alloc_coherent(np->device,
4406                                            sizeof(struct txdma_mailbox),
4407                                            &rp->mbox_dma, GFP_KERNEL);
4408         if (!rp->mbox)
4409                 return -ENOMEM;
4410         if ((unsigned long)rp->mbox & (64UL - 1)) {
4411                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4412                            rp->mbox);
4413                 return -EINVAL;
4414         }
4415
4416         rp->descr = np->ops->alloc_coherent(np->device,
4417                                             MAX_TX_RING_SIZE * sizeof(__le64),
4418                                             &rp->descr_dma, GFP_KERNEL);
4419         if (!rp->descr)
4420                 return -ENOMEM;
4421         if ((unsigned long)rp->descr & (64UL - 1)) {
4422                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4423                            rp->descr);
4424                 return -EINVAL;
4425         }
4426
4427         rp->pending = MAX_TX_RING_SIZE;
4428         rp->prod = 0;
4429         rp->cons = 0;
4430         rp->wrap_bit = 0;
4431
4432         /* XXX make these configurable... XXX */
4433         rp->mark_freq = rp->pending / 4;
4434
4435         niu_set_max_burst(np, rp);
4436
4437         return 0;
4438 }
4439
4440 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4441 {
4442         u16 bss;
4443
4444         bss = min(PAGE_SHIFT, 15);
4445
4446         rp->rbr_block_size = 1 << bss;
4447         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4448
4449         rp->rbr_sizes[0] = 256;
4450         rp->rbr_sizes[1] = 1024;
4451         if (np->dev->mtu > ETH_DATA_LEN) {
4452                 switch (PAGE_SIZE) {
4453                 case 4 * 1024:
4454                         rp->rbr_sizes[2] = 4096;
4455                         break;
4456
4457                 default:
4458                         rp->rbr_sizes[2] = 8192;
4459                         break;
4460                 }
4461         } else {
4462                 rp->rbr_sizes[2] = 2048;
4463         }
4464         rp->rbr_sizes[3] = rp->rbr_block_size;
4465 }
4466
4467 static int niu_alloc_channels(struct niu *np)
4468 {
4469         struct niu_parent *parent = np->parent;
4470         int first_rx_channel, first_tx_channel;
4471         int num_rx_rings, num_tx_rings;
4472         struct rx_ring_info *rx_rings;
4473         struct tx_ring_info *tx_rings;
4474         int i, port, err;
4475
4476         port = np->port;
4477         first_rx_channel = first_tx_channel = 0;
4478         for (i = 0; i < port; i++) {
4479                 first_rx_channel += parent->rxchan_per_port[i];
4480                 first_tx_channel += parent->txchan_per_port[i];
4481         }
4482
4483         num_rx_rings = parent->rxchan_per_port[port];
4484         num_tx_rings = parent->txchan_per_port[port];
4485
4486         rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4487                            GFP_KERNEL);
4488         err = -ENOMEM;
4489         if (!rx_rings)
4490                 goto out_err;
4491
4492         np->num_rx_rings = num_rx_rings;
4493         smp_wmb();
4494         np->rx_rings = rx_rings;
4495
4496         netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4497
4498         for (i = 0; i < np->num_rx_rings; i++) {
4499                 struct rx_ring_info *rp = &np->rx_rings[i];
4500
4501                 rp->np = np;
4502                 rp->rx_channel = first_rx_channel + i;
4503
4504                 err = niu_alloc_rx_ring_info(np, rp);
4505                 if (err)
4506                         goto out_err;
4507
4508                 niu_size_rbr(np, rp);
4509
4510                 /* XXX better defaults, configurable, etc... XXX */
4511                 rp->nonsyn_window = 64;
4512                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4513                 rp->syn_window = 64;
4514                 rp->syn_threshold = rp->rcr_table_size - 64;
4515                 rp->rcr_pkt_threshold = 16;
4516                 rp->rcr_timeout = 8;
4517                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4518                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4519                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4520
4521                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4522                 if (err)
4523                         return err;
4524         }
4525
4526         tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4527                            GFP_KERNEL);
4528         err = -ENOMEM;
4529         if (!tx_rings)
4530                 goto out_err;
4531
4532         np->num_tx_rings = num_tx_rings;
4533         smp_wmb();
4534         np->tx_rings = tx_rings;
4535
4536         netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4537
4538         for (i = 0; i < np->num_tx_rings; i++) {
4539                 struct tx_ring_info *rp = &np->tx_rings[i];
4540
4541                 rp->np = np;
4542                 rp->tx_channel = first_tx_channel + i;
4543
4544                 err = niu_alloc_tx_ring_info(np, rp);
4545                 if (err)
4546                         goto out_err;
4547         }
4548
4549         return 0;
4550
4551 out_err:
4552         niu_free_channels(np);
4553         return err;
4554 }
4555
4556 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4557 {
4558         int limit = 1000;
4559
4560         while (--limit > 0) {
4561                 u64 val = nr64(TX_CS(channel));
4562                 if (val & TX_CS_SNG_STATE)
4563                         return 0;
4564         }
4565         return -ENODEV;
4566 }
4567
4568 static int niu_tx_channel_stop(struct niu *np, int channel)
4569 {
4570         u64 val = nr64(TX_CS(channel));
4571
4572         val |= TX_CS_STOP_N_GO;
4573         nw64(TX_CS(channel), val);
4574
4575         return niu_tx_cs_sng_poll(np, channel);
4576 }
4577
4578 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4579 {
4580         int limit = 1000;
4581
4582         while (--limit > 0) {
4583                 u64 val = nr64(TX_CS(channel));
4584                 if (!(val & TX_CS_RST))
4585                         return 0;
4586         }
4587         return -ENODEV;
4588 }
4589
4590 static int niu_tx_channel_reset(struct niu *np, int channel)
4591 {
4592         u64 val = nr64(TX_CS(channel));
4593         int err;
4594
4595         val |= TX_CS_RST;
4596         nw64(TX_CS(channel), val);
4597
4598         err = niu_tx_cs_reset_poll(np, channel);
4599         if (!err)
4600                 nw64(TX_RING_KICK(channel), 0);
4601
4602         return err;
4603 }
4604
4605 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4606 {
4607         u64 val;
4608
4609         nw64(TX_LOG_MASK1(channel), 0);
4610         nw64(TX_LOG_VAL1(channel), 0);
4611         nw64(TX_LOG_MASK2(channel), 0);
4612         nw64(TX_LOG_VAL2(channel), 0);
4613         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4614         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4615         nw64(TX_LOG_PAGE_HDL(channel), 0);
4616
4617         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4618         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4619         nw64(TX_LOG_PAGE_VLD(channel), val);
4620
4621         /* XXX TXDMA 32bit mode? XXX */
4622
4623         return 0;
4624 }
4625
4626 static void niu_txc_enable_port(struct niu *np, int on)
4627 {
4628         unsigned long flags;
4629         u64 val, mask;
4630
4631         niu_lock_parent(np, flags);
4632         val = nr64(TXC_CONTROL);
4633         mask = (u64)1 << np->port;
4634         if (on) {
4635                 val |= TXC_CONTROL_ENABLE | mask;
4636         } else {
4637                 val &= ~mask;
4638                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4639                         val &= ~TXC_CONTROL_ENABLE;
4640         }
4641         nw64(TXC_CONTROL, val);
4642         niu_unlock_parent(np, flags);
4643 }
4644
4645 static void niu_txc_set_imask(struct niu *np, u64 imask)
4646 {
4647         unsigned long flags;
4648         u64 val;
4649
4650         niu_lock_parent(np, flags);
4651         val = nr64(TXC_INT_MASK);
4652         val &= ~TXC_INT_MASK_VAL(np->port);
4653         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4654         niu_unlock_parent(np, flags);
4655 }
4656
4657 static void niu_txc_port_dma_enable(struct niu *np, int on)
4658 {
4659         u64 val = 0;
4660
4661         if (on) {
4662                 int i;
4663
4664                 for (i = 0; i < np->num_tx_rings; i++)
4665                         val |= (1 << np->tx_rings[i].tx_channel);
4666         }
4667         nw64(TXC_PORT_DMA(np->port), val);
4668 }
4669
4670 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4671 {
4672         int err, channel = rp->tx_channel;
4673         u64 val, ring_len;
4674
4675         err = niu_tx_channel_stop(np, channel);
4676         if (err)
4677                 return err;
4678
4679         err = niu_tx_channel_reset(np, channel);
4680         if (err)
4681                 return err;
4682
4683         err = niu_tx_channel_lpage_init(np, channel);
4684         if (err)
4685                 return err;
4686
4687         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4688         nw64(TX_ENT_MSK(channel), 0);
4689
4690         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4691                               TX_RNG_CFIG_STADDR)) {
4692                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4693                            channel, (unsigned long long)rp->descr_dma);
4694                 return -EINVAL;
4695         }
4696
4697         /* The length field in TX_RNG_CFIG is measured in 64-byte
4698          * blocks.  rp->pending is the number of TX descriptors in
4699          * our ring, 8 bytes each, thus we divide by 8 bytes more
4700          * to get the proper value the chip wants.
4701          */
4702         ring_len = (rp->pending / 8);
4703
4704         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4705                rp->descr_dma);
4706         nw64(TX_RNG_CFIG(channel), val);
4707
4708         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4709             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4710                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4711                             channel, (unsigned long long)rp->mbox_dma);
4712                 return -EINVAL;
4713         }
4714         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4715         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4716
4717         nw64(TX_CS(channel), 0);
4718
4719         rp->last_pkt_cnt = 0;
4720
4721         return 0;
4722 }
4723
4724 static void niu_init_rdc_groups(struct niu *np)
4725 {
4726         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4727         int i, first_table_num = tp->first_table_num;
4728
4729         for (i = 0; i < tp->num_tables; i++) {
4730                 struct rdc_table *tbl = &tp->tables[i];
4731                 int this_table = first_table_num + i;
4732                 int slot;
4733
4734                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4735                         nw64(RDC_TBL(this_table, slot),
4736                              tbl->rxdma_channel[slot]);
4737         }
4738
4739         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4740 }
4741
4742 static void niu_init_drr_weight(struct niu *np)
4743 {
4744         int type = phy_decode(np->parent->port_phy, np->port);
4745         u64 val;
4746
4747         switch (type) {
4748         case PORT_TYPE_10G:
4749                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4750                 break;
4751
4752         case PORT_TYPE_1G:
4753         default:
4754                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4755                 break;
4756         }
4757         nw64(PT_DRR_WT(np->port), val);
4758 }
4759
4760 static int niu_init_hostinfo(struct niu *np)
4761 {
4762         struct niu_parent *parent = np->parent;
4763         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4764         int i, err, num_alt = niu_num_alt_addr(np);
4765         int first_rdc_table = tp->first_table_num;
4766
4767         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4768         if (err)
4769                 return err;
4770
4771         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4772         if (err)
4773                 return err;
4774
4775         for (i = 0; i < num_alt; i++) {
4776                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4777                 if (err)
4778                         return err;
4779         }
4780
4781         return 0;
4782 }
4783
4784 static int niu_rx_channel_reset(struct niu *np, int channel)
4785 {
4786         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4787                                       RXDMA_CFIG1_RST, 1000, 10,
4788                                       "RXDMA_CFIG1");
4789 }
4790
4791 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4792 {
4793         u64 val;
4794
4795         nw64(RX_LOG_MASK1(channel), 0);
4796         nw64(RX_LOG_VAL1(channel), 0);
4797         nw64(RX_LOG_MASK2(channel), 0);
4798         nw64(RX_LOG_VAL2(channel), 0);
4799         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4800         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4801         nw64(RX_LOG_PAGE_HDL(channel), 0);
4802
4803         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4804         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4805         nw64(RX_LOG_PAGE_VLD(channel), val);
4806
4807         return 0;
4808 }
4809
4810 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4811 {
4812         u64 val;
4813
4814         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4815                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4816                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4817                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4818         nw64(RDC_RED_PARA(rp->rx_channel), val);
4819 }
4820
4821 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4822 {
4823         u64 val = 0;
4824
4825         *ret = 0;
4826         switch (rp->rbr_block_size) {
4827         case 4 * 1024:
4828                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4829                 break;
4830         case 8 * 1024:
4831                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4832                 break;
4833         case 16 * 1024:
4834                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4835                 break;
4836         case 32 * 1024:
4837                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838                 break;
4839         default:
4840                 return -EINVAL;
4841         }
4842         val |= RBR_CFIG_B_VLD2;
4843         switch (rp->rbr_sizes[2]) {
4844         case 2 * 1024:
4845                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4846                 break;
4847         case 4 * 1024:
4848                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4849                 break;
4850         case 8 * 1024:
4851                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4852                 break;
4853         case 16 * 1024:
4854                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855                 break;
4856
4857         default:
4858                 return -EINVAL;
4859         }
4860         val |= RBR_CFIG_B_VLD1;
4861         switch (rp->rbr_sizes[1]) {
4862         case 1 * 1024:
4863                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4864                 break;
4865         case 2 * 1024:
4866                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4867                 break;
4868         case 4 * 1024:
4869                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4870                 break;
4871         case 8 * 1024:
4872                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873                 break;
4874
4875         default:
4876                 return -EINVAL;
4877         }
4878         val |= RBR_CFIG_B_VLD0;
4879         switch (rp->rbr_sizes[0]) {
4880         case 256:
4881                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4882                 break;
4883         case 512:
4884                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4885                 break;
4886         case 1 * 1024:
4887                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4888                 break;
4889         case 2 * 1024:
4890                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4891                 break;
4892
4893         default:
4894                 return -EINVAL;
4895         }
4896
4897         *ret = val;
4898         return 0;
4899 }
4900
4901 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4902 {
4903         u64 val = nr64(RXDMA_CFIG1(channel));
4904         int limit;
4905
4906         if (on)
4907                 val |= RXDMA_CFIG1_EN;
4908         else
4909                 val &= ~RXDMA_CFIG1_EN;
4910         nw64(RXDMA_CFIG1(channel), val);
4911
4912         limit = 1000;
4913         while (--limit > 0) {
4914                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4915                         break;
4916                 udelay(10);
4917         }
4918         if (limit <= 0)
4919                 return -ENODEV;
4920         return 0;
4921 }
4922
4923 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4924 {
4925         int err, channel = rp->rx_channel;
4926         u64 val;
4927
4928         err = niu_rx_channel_reset(np, channel);
4929         if (err)
4930                 return err;
4931
4932         err = niu_rx_channel_lpage_init(np, channel);
4933         if (err)
4934                 return err;
4935
4936         niu_rx_channel_wred_init(np, rp);
4937
4938         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4939         nw64(RX_DMA_CTL_STAT(channel),
4940              (RX_DMA_CTL_STAT_MEX |
4941               RX_DMA_CTL_STAT_RCRTHRES |
4942               RX_DMA_CTL_STAT_RCRTO |
4943               RX_DMA_CTL_STAT_RBR_EMPTY));
4944         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4945         nw64(RXDMA_CFIG2(channel),
4946              ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4947               RXDMA_CFIG2_FULL_HDR));
4948         nw64(RBR_CFIG_A(channel),
4949              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4950              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4951         err = niu_compute_rbr_cfig_b(rp, &val);
4952         if (err)
4953                 return err;
4954         nw64(RBR_CFIG_B(channel), val);
4955         nw64(RCRCFIG_A(channel),
4956              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4957              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4958         nw64(RCRCFIG_B(channel),
4959              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4960              RCRCFIG_B_ENTOUT |
4961              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4962
4963         err = niu_enable_rx_channel(np, channel, 1);
4964         if (err)
4965                 return err;
4966
4967         nw64(RBR_KICK(channel), rp->rbr_index);
4968
4969         val = nr64(RX_DMA_CTL_STAT(channel));
4970         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4971         nw64(RX_DMA_CTL_STAT(channel), val);
4972
4973         return 0;
4974 }
4975
4976 static int niu_init_rx_channels(struct niu *np)
4977 {
4978         unsigned long flags;
4979         u64 seed = jiffies_64;
4980         int err, i;
4981
4982         niu_lock_parent(np, flags);
4983         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4984         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4985         niu_unlock_parent(np, flags);
4986
4987         /* XXX RXDMA 32bit mode? XXX */
4988
4989         niu_init_rdc_groups(np);
4990         niu_init_drr_weight(np);
4991
4992         err = niu_init_hostinfo(np);
4993         if (err)
4994                 return err;
4995
4996         for (i = 0; i < np->num_rx_rings; i++) {
4997                 struct rx_ring_info *rp = &np->rx_rings[i];
4998
4999                 err = niu_init_one_rx_channel(np, rp);
5000                 if (err)
5001                         return err;
5002         }
5003
5004         return 0;
5005 }
5006
5007 static int niu_set_ip_frag_rule(struct niu *np)
5008 {
5009         struct niu_parent *parent = np->parent;
5010         struct niu_classifier *cp = &np->clas;
5011         struct niu_tcam_entry *tp;
5012         int index, err;
5013
5014         index = cp->tcam_top;
5015         tp = &parent->tcam[index];
5016
5017         /* Note that the noport bit is the same in both ipv4 and
5018          * ipv6 format TCAM entries.
5019          */
5020         memset(tp, 0, sizeof(*tp));
5021         tp->key[1] = TCAM_V4KEY1_NOPORT;
5022         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5023         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5024                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5025         err = tcam_write(np, index, tp->key, tp->key_mask);
5026         if (err)
5027                 return err;
5028         err = tcam_assoc_write(np, index, tp->assoc_data);
5029         if (err)
5030                 return err;
5031         tp->valid = 1;
5032         cp->tcam_valid_entries++;
5033
5034         return 0;
5035 }
5036
5037 static int niu_init_classifier_hw(struct niu *np)
5038 {
5039         struct niu_parent *parent = np->parent;
5040         struct niu_classifier *cp = &np->clas;
5041         int i, err;
5042
5043         nw64(H1POLY, cp->h1_init);
5044         nw64(H2POLY, cp->h2_init);
5045
5046         err = niu_init_hostinfo(np);
5047         if (err)
5048                 return err;
5049
5050         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5051                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5052
5053                 vlan_tbl_write(np, i, np->port,
5054                                vp->vlan_pref, vp->rdc_num);
5055         }
5056
5057         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5058                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5059
5060                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5061                                                 ap->rdc_num, ap->mac_pref);
5062                 if (err)
5063                         return err;
5064         }
5065
5066         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5067                 int index = i - CLASS_CODE_USER_PROG1;
5068
5069                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5070                 if (err)
5071                         return err;
5072                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5073                 if (err)
5074                         return err;
5075         }
5076
5077         err = niu_set_ip_frag_rule(np);
5078         if (err)
5079                 return err;
5080
5081         tcam_enable(np, 1);
5082
5083         return 0;
5084 }
5085
5086 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5087 {
5088         nw64(ZCP_RAM_DATA0, data[0]);
5089         nw64(ZCP_RAM_DATA1, data[1]);
5090         nw64(ZCP_RAM_DATA2, data[2]);
5091         nw64(ZCP_RAM_DATA3, data[3]);
5092         nw64(ZCP_RAM_DATA4, data[4]);
5093         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5094         nw64(ZCP_RAM_ACC,
5095              (ZCP_RAM_ACC_WRITE |
5096               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5097               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5098
5099         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5100                                    1000, 100);
5101 }
5102
5103 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5104 {
5105         int err;
5106
5107         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5108                                   1000, 100);
5109         if (err) {
5110                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5111                            (unsigned long long)nr64(ZCP_RAM_ACC));
5112                 return err;
5113         }
5114
5115         nw64(ZCP_RAM_ACC,
5116              (ZCP_RAM_ACC_READ |
5117               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5118               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5119
5120         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5121                                   1000, 100);
5122         if (err) {
5123                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5124                            (unsigned long long)nr64(ZCP_RAM_ACC));
5125                 return err;
5126         }
5127
5128         data[0] = nr64(ZCP_RAM_DATA0);
5129         data[1] = nr64(ZCP_RAM_DATA1);
5130         data[2] = nr64(ZCP_RAM_DATA2);
5131         data[3] = nr64(ZCP_RAM_DATA3);
5132         data[4] = nr64(ZCP_RAM_DATA4);
5133
5134         return 0;
5135 }
5136
5137 static void niu_zcp_cfifo_reset(struct niu *np)
5138 {
5139         u64 val = nr64(RESET_CFIFO);
5140
5141         val |= RESET_CFIFO_RST(np->port);
5142         nw64(RESET_CFIFO, val);
5143         udelay(10);
5144
5145         val &= ~RESET_CFIFO_RST(np->port);
5146         nw64(RESET_CFIFO, val);
5147 }
5148
5149 static int niu_init_zcp(struct niu *np)
5150 {
5151         u64 data[5], rbuf[5];
5152         int i, max, err;
5153
5154         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5155                 if (np->port == 0 || np->port == 1)
5156                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5157                 else
5158                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5159         } else
5160                 max = NIU_CFIFO_ENTRIES;
5161
5162         data[0] = 0;
5163         data[1] = 0;
5164         data[2] = 0;
5165         data[3] = 0;
5166         data[4] = 0;
5167
5168         for (i = 0; i < max; i++) {
5169                 err = niu_zcp_write(np, i, data);
5170                 if (err)
5171                         return err;
5172                 err = niu_zcp_read(np, i, rbuf);
5173                 if (err)
5174                         return err;
5175         }
5176
5177         niu_zcp_cfifo_reset(np);
5178         nw64(CFIFO_ECC(np->port), 0);
5179         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5180         (void) nr64(ZCP_INT_STAT);
5181         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5182
5183         return 0;
5184 }
5185
5186 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5187 {
5188         u64 val = nr64_ipp(IPP_CFIG);
5189
5190         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5191         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5192         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5193         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5194         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5195         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5196         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5197         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5198 }
5199
5200 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5201 {
5202         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5203         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5204         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5205         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5206         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5207         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5208 }
5209
5210 static int niu_ipp_reset(struct niu *np)
5211 {
5212         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5213                                           1000, 100, "IPP_CFIG");
5214 }
5215
5216 static int niu_init_ipp(struct niu *np)
5217 {
5218         u64 data[5], rbuf[5], val;
5219         int i, max, err;
5220
5221         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5222                 if (np->port == 0 || np->port == 1)
5223                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5224                 else
5225                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5226         } else
5227                 max = NIU_DFIFO_ENTRIES;
5228
5229         data[0] = 0;
5230         data[1] = 0;
5231         data[2] = 0;
5232         data[3] = 0;
5233         data[4] = 0;
5234
5235         for (i = 0; i < max; i++) {
5236                 niu_ipp_write(np, i, data);
5237                 niu_ipp_read(np, i, rbuf);
5238         }
5239
5240         (void) nr64_ipp(IPP_INT_STAT);
5241         (void) nr64_ipp(IPP_INT_STAT);
5242
5243         err = niu_ipp_reset(np);
5244         if (err)
5245                 return err;
5246
5247         (void) nr64_ipp(IPP_PKT_DIS);
5248         (void) nr64_ipp(IPP_BAD_CS_CNT);
5249         (void) nr64_ipp(IPP_ECC);
5250
5251         (void) nr64_ipp(IPP_INT_STAT);
5252
5253         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5254
5255         val = nr64_ipp(IPP_CFIG);
5256         val &= ~IPP_CFIG_IP_MAX_PKT;
5257         val |= (IPP_CFIG_IPP_ENABLE |
5258                 IPP_CFIG_DFIFO_ECC_EN |
5259                 IPP_CFIG_DROP_BAD_CRC |
5260                 IPP_CFIG_CKSUM_EN |
5261                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5262         nw64_ipp(IPP_CFIG, val);
5263
5264         return 0;
5265 }
5266
5267 static void niu_handle_led(struct niu *np, int status)
5268 {
5269         u64 val;
5270         val = nr64_mac(XMAC_CONFIG);
5271
5272         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5273             (np->flags & NIU_FLAGS_FIBER) != 0) {
5274                 if (status) {
5275                         val |= XMAC_CONFIG_LED_POLARITY;
5276                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5277                 } else {
5278                         val |= XMAC_CONFIG_FORCE_LED_ON;
5279                         val &= ~XMAC_CONFIG_LED_POLARITY;
5280                 }
5281         }
5282
5283         nw64_mac(XMAC_CONFIG, val);
5284 }
5285
5286 static void niu_init_xif_xmac(struct niu *np)
5287 {
5288         struct niu_link_config *lp = &np->link_config;
5289         u64 val;
5290
5291         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5292                 val = nr64(MIF_CONFIG);
5293                 val |= MIF_CONFIG_ATCA_GE;
5294                 nw64(MIF_CONFIG, val);
5295         }
5296
5297         val = nr64_mac(XMAC_CONFIG);
5298         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5299
5300         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5301
5302         if (lp->loopback_mode == LOOPBACK_MAC) {
5303                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5304                 val |= XMAC_CONFIG_LOOPBACK;
5305         } else {
5306                 val &= ~XMAC_CONFIG_LOOPBACK;
5307         }
5308
5309         if (np->flags & NIU_FLAGS_10G) {
5310                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5311         } else {
5312                 val |= XMAC_CONFIG_LFS_DISABLE;
5313                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5314                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5315                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5316                 else
5317                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5318         }
5319
5320         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5321
5322         if (lp->active_speed == SPEED_100)
5323                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5324         else
5325                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5326
5327         nw64_mac(XMAC_CONFIG, val);
5328
5329         val = nr64_mac(XMAC_CONFIG);
5330         val &= ~XMAC_CONFIG_MODE_MASK;
5331         if (np->flags & NIU_FLAGS_10G) {
5332                 val |= XMAC_CONFIG_MODE_XGMII;
5333         } else {
5334                 if (lp->active_speed == SPEED_1000)
5335                         val |= XMAC_CONFIG_MODE_GMII;
5336                 else
5337                         val |= XMAC_CONFIG_MODE_MII;
5338         }
5339
5340         nw64_mac(XMAC_CONFIG, val);
5341 }
5342
5343 static void niu_init_xif_bmac(struct niu *np)
5344 {
5345         struct niu_link_config *lp = &np->link_config;
5346         u64 val;
5347
5348         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5349
5350         if (lp->loopback_mode == LOOPBACK_MAC)
5351                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5352         else
5353                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5354
5355         if (lp->active_speed == SPEED_1000)
5356                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5357         else
5358                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5359
5360         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5361                  BMAC_XIF_CONFIG_LED_POLARITY);
5362
5363         if (!(np->flags & NIU_FLAGS_10G) &&
5364             !(np->flags & NIU_FLAGS_FIBER) &&
5365             lp->active_speed == SPEED_100)
5366                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5367         else
5368                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5369
5370         nw64_mac(BMAC_XIF_CONFIG, val);
5371 }
5372
5373 static void niu_init_xif(struct niu *np)
5374 {
5375         if (np->flags & NIU_FLAGS_XMAC)
5376                 niu_init_xif_xmac(np);
5377         else
5378                 niu_init_xif_bmac(np);
5379 }
5380
5381 static void niu_pcs_mii_reset(struct niu *np)
5382 {
5383         int limit = 1000;
5384         u64 val = nr64_pcs(PCS_MII_CTL);
5385         val |= PCS_MII_CTL_RST;
5386         nw64_pcs(PCS_MII_CTL, val);
5387         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5388                 udelay(100);
5389                 val = nr64_pcs(PCS_MII_CTL);
5390         }
5391 }
5392
5393 static void niu_xpcs_reset(struct niu *np)
5394 {
5395         int limit = 1000;
5396         u64 val = nr64_xpcs(XPCS_CONTROL1);
5397         val |= XPCS_CONTROL1_RESET;
5398         nw64_xpcs(XPCS_CONTROL1, val);
5399         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5400                 udelay(100);
5401                 val = nr64_xpcs(XPCS_CONTROL1);
5402         }
5403 }
5404
5405 static int niu_init_pcs(struct niu *np)
5406 {
5407         struct niu_link_config *lp = &np->link_config;
5408         u64 val;
5409
5410         switch (np->flags & (NIU_FLAGS_10G |
5411                              NIU_FLAGS_FIBER |
5412                              NIU_FLAGS_XCVR_SERDES)) {
5413         case NIU_FLAGS_FIBER:
5414                 /* 1G fiber */
5415                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5416                 nw64_pcs(PCS_DPATH_MODE, 0);
5417                 niu_pcs_mii_reset(np);
5418                 break;
5419
5420         case NIU_FLAGS_10G:
5421         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5422         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5423                 /* 10G SERDES */
5424                 if (!(np->flags & NIU_FLAGS_XMAC))
5425                         return -EINVAL;
5426
5427                 /* 10G copper or fiber */
5428                 val = nr64_mac(XMAC_CONFIG);
5429                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5430                 nw64_mac(XMAC_CONFIG, val);
5431
5432                 niu_xpcs_reset(np);
5433
5434                 val = nr64_xpcs(XPCS_CONTROL1);
5435                 if (lp->loopback_mode == LOOPBACK_PHY)
5436                         val |= XPCS_CONTROL1_LOOPBACK;
5437                 else
5438                         val &= ~XPCS_CONTROL1_LOOPBACK;
5439                 nw64_xpcs(XPCS_CONTROL1, val);
5440
5441                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5442                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5443                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5444                 break;
5445
5446
5447         case NIU_FLAGS_XCVR_SERDES:
5448                 /* 1G SERDES */
5449                 niu_pcs_mii_reset(np);
5450                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5451                 nw64_pcs(PCS_DPATH_MODE, 0);
5452                 break;
5453
5454         case 0:
5455                 /* 1G copper */
5456         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5457                 /* 1G RGMII FIBER */
5458                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5459                 niu_pcs_mii_reset(np);
5460                 break;
5461
5462         default:
5463                 return -EINVAL;
5464         }
5465
5466         return 0;
5467 }
5468
5469 static int niu_reset_tx_xmac(struct niu *np)
5470 {
5471         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5472                                           (XTXMAC_SW_RST_REG_RS |
5473                                            XTXMAC_SW_RST_SOFT_RST),
5474                                           1000, 100, "XTXMAC_SW_RST");
5475 }
5476
5477 static int niu_reset_tx_bmac(struct niu *np)
5478 {
5479         int limit;
5480
5481         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5482         limit = 1000;
5483         while (--limit >= 0) {
5484                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5485                         break;
5486                 udelay(100);
5487         }
5488         if (limit < 0) {
5489                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5490                         np->port,
5491                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5492                 return -ENODEV;
5493         }
5494
5495         return 0;
5496 }
5497
5498 static int niu_reset_tx_mac(struct niu *np)
5499 {
5500         if (np->flags & NIU_FLAGS_XMAC)
5501                 return niu_reset_tx_xmac(np);
5502         else
5503                 return niu_reset_tx_bmac(np);
5504 }
5505
5506 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5507 {
5508         u64 val;
5509
5510         val = nr64_mac(XMAC_MIN);
5511         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5512                  XMAC_MIN_RX_MIN_PKT_SIZE);
5513         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5514         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5515         nw64_mac(XMAC_MIN, val);
5516
5517         nw64_mac(XMAC_MAX, max);
5518
5519         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5520
5521         val = nr64_mac(XMAC_IPG);
5522         if (np->flags & NIU_FLAGS_10G) {
5523                 val &= ~XMAC_IPG_IPG_XGMII;
5524                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5525         } else {
5526                 val &= ~XMAC_IPG_IPG_MII_GMII;
5527                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5528         }
5529         nw64_mac(XMAC_IPG, val);
5530
5531         val = nr64_mac(XMAC_CONFIG);
5532         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5533                  XMAC_CONFIG_STRETCH_MODE |
5534                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5535                  XMAC_CONFIG_TX_ENABLE);
5536         nw64_mac(XMAC_CONFIG, val);
5537
5538         nw64_mac(TXMAC_FRM_CNT, 0);
5539         nw64_mac(TXMAC_BYTE_CNT, 0);
5540 }
5541
5542 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5543 {
5544         u64 val;
5545
5546         nw64_mac(BMAC_MIN_FRAME, min);
5547         nw64_mac(BMAC_MAX_FRAME, max);
5548
5549         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5550         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5551         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5552
5553         val = nr64_mac(BTXMAC_CONFIG);
5554         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5555                  BTXMAC_CONFIG_ENABLE);
5556         nw64_mac(BTXMAC_CONFIG, val);
5557 }
5558
5559 static void niu_init_tx_mac(struct niu *np)
5560 {
5561         u64 min, max;
5562
5563         min = 64;
5564         if (np->dev->mtu > ETH_DATA_LEN)
5565                 max = 9216;
5566         else
5567                 max = 1522;
5568
5569         /* The XMAC_MIN register only accepts values for TX min which
5570          * have the low 3 bits cleared.
5571          */
5572         BUG_ON(min & 0x7);
5573
5574         if (np->flags & NIU_FLAGS_XMAC)
5575                 niu_init_tx_xmac(np, min, max);
5576         else
5577                 niu_init_tx_bmac(np, min, max);
5578 }
5579
5580 static int niu_reset_rx_xmac(struct niu *np)
5581 {
5582         int limit;
5583
5584         nw64_mac(XRXMAC_SW_RST,
5585                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5586         limit = 1000;
5587         while (--limit >= 0) {
5588                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5589                                                  XRXMAC_SW_RST_SOFT_RST)))
5590                         break;
5591                 udelay(100);
5592         }
5593         if (limit < 0) {
5594                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5595                         np->port,
5596                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5597                 return -ENODEV;
5598         }
5599
5600         return 0;
5601 }
5602
5603 static int niu_reset_rx_bmac(struct niu *np)
5604 {
5605         int limit;
5606
5607         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5608         limit = 1000;
5609         while (--limit >= 0) {
5610                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5611                         break;
5612                 udelay(100);
5613         }
5614         if (limit < 0) {
5615                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5616                         np->port,
5617                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5618                 return -ENODEV;
5619         }
5620
5621         return 0;
5622 }
5623
5624 static int niu_reset_rx_mac(struct niu *np)
5625 {
5626         if (np->flags & NIU_FLAGS_XMAC)
5627                 return niu_reset_rx_xmac(np);
5628         else
5629                 return niu_reset_rx_bmac(np);
5630 }
5631
5632 static void niu_init_rx_xmac(struct niu *np)
5633 {
5634         struct niu_parent *parent = np->parent;
5635         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5636         int first_rdc_table = tp->first_table_num;
5637         unsigned long i;
5638         u64 val;
5639
5640         nw64_mac(XMAC_ADD_FILT0, 0);
5641         nw64_mac(XMAC_ADD_FILT1, 0);
5642         nw64_mac(XMAC_ADD_FILT2, 0);
5643         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5644         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5645         for (i = 0; i < MAC_NUM_HASH; i++)
5646                 nw64_mac(XMAC_HASH_TBL(i), 0);
5647         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5648         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5649         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5650
5651         val = nr64_mac(XMAC_CONFIG);
5652         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5653                  XMAC_CONFIG_PROMISCUOUS |
5654                  XMAC_CONFIG_PROMISC_GROUP |
5655                  XMAC_CONFIG_ERR_CHK_DIS |
5656                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5657                  XMAC_CONFIG_RESERVED_MULTICAST |
5658                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5659                  XMAC_CONFIG_ADDR_FILTER_EN |
5660                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5661                  XMAC_CONFIG_STRIP_CRC |
5662                  XMAC_CONFIG_PASS_FLOW_CTRL |
5663                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5664         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5665         nw64_mac(XMAC_CONFIG, val);
5666
5667         nw64_mac(RXMAC_BT_CNT, 0);
5668         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5669         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5670         nw64_mac(RXMAC_FRAG_CNT, 0);
5671         nw64_mac(RXMAC_HIST_CNT1, 0);
5672         nw64_mac(RXMAC_HIST_CNT2, 0);
5673         nw64_mac(RXMAC_HIST_CNT3, 0);
5674         nw64_mac(RXMAC_HIST_CNT4, 0);
5675         nw64_mac(RXMAC_HIST_CNT5, 0);
5676         nw64_mac(RXMAC_HIST_CNT6, 0);
5677         nw64_mac(RXMAC_HIST_CNT7, 0);
5678         nw64_mac(RXMAC_MPSZER_CNT, 0);
5679         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5680         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5681         nw64_mac(LINK_FAULT_CNT, 0);
5682 }
5683
5684 static void niu_init_rx_bmac(struct niu *np)
5685 {
5686         struct niu_parent *parent = np->parent;
5687         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5688         int first_rdc_table = tp->first_table_num;
5689         unsigned long i;
5690         u64 val;
5691
5692         nw64_mac(BMAC_ADD_FILT0, 0);
5693         nw64_mac(BMAC_ADD_FILT1, 0);
5694         nw64_mac(BMAC_ADD_FILT2, 0);
5695         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5696         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5697         for (i = 0; i < MAC_NUM_HASH; i++)
5698                 nw64_mac(BMAC_HASH_TBL(i), 0);
5699         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5700         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5701         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5702
5703         val = nr64_mac(BRXMAC_CONFIG);
5704         val &= ~(BRXMAC_CONFIG_ENABLE |
5705                  BRXMAC_CONFIG_STRIP_PAD |
5706                  BRXMAC_CONFIG_STRIP_FCS |
5707                  BRXMAC_CONFIG_PROMISC |
5708                  BRXMAC_CONFIG_PROMISC_GRP |
5709                  BRXMAC_CONFIG_ADDR_FILT_EN |
5710                  BRXMAC_CONFIG_DISCARD_DIS);
5711         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5712         nw64_mac(BRXMAC_CONFIG, val);
5713
5714         val = nr64_mac(BMAC_ADDR_CMPEN);
5715         val |= BMAC_ADDR_CMPEN_EN0;
5716         nw64_mac(BMAC_ADDR_CMPEN, val);
5717 }
5718
5719 static void niu_init_rx_mac(struct niu *np)
5720 {
5721         niu_set_primary_mac(np, np->dev->dev_addr);
5722
5723         if (np->flags & NIU_FLAGS_XMAC)
5724                 niu_init_rx_xmac(np);
5725         else
5726                 niu_init_rx_bmac(np);
5727 }
5728
5729 static void niu_enable_tx_xmac(struct niu *np, int on)
5730 {
5731         u64 val = nr64_mac(XMAC_CONFIG);
5732
5733         if (on)
5734                 val |= XMAC_CONFIG_TX_ENABLE;
5735         else
5736                 val &= ~XMAC_CONFIG_TX_ENABLE;
5737         nw64_mac(XMAC_CONFIG, val);
5738 }
5739
5740 static void niu_enable_tx_bmac(struct niu *np, int on)
5741 {
5742         u64 val = nr64_mac(BTXMAC_CONFIG);
5743
5744         if (on)
5745                 val |= BTXMAC_CONFIG_ENABLE;
5746         else
5747                 val &= ~BTXMAC_CONFIG_ENABLE;
5748         nw64_mac(BTXMAC_CONFIG, val);
5749 }
5750
5751 static void niu_enable_tx_mac(struct niu *np, int on)
5752 {
5753         if (np->flags & NIU_FLAGS_XMAC)
5754                 niu_enable_tx_xmac(np, on);
5755         else
5756                 niu_enable_tx_bmac(np, on);
5757 }
5758
5759 static void niu_enable_rx_xmac(struct niu *np, int on)
5760 {
5761         u64 val = nr64_mac(XMAC_CONFIG);
5762
5763         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5764                  XMAC_CONFIG_PROMISCUOUS);
5765
5766         if (np->flags & NIU_FLAGS_MCAST)
5767                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5768         if (np->flags & NIU_FLAGS_PROMISC)
5769                 val |= XMAC_CONFIG_PROMISCUOUS;
5770
5771         if (on)
5772                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5773         else
5774                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5775         nw64_mac(XMAC_CONFIG, val);
5776 }
5777
5778 static void niu_enable_rx_bmac(struct niu *np, int on)
5779 {
5780         u64 val = nr64_mac(BRXMAC_CONFIG);
5781
5782         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5783                  BRXMAC_CONFIG_PROMISC);
5784
5785         if (np->flags & NIU_FLAGS_MCAST)
5786                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5787         if (np->flags & NIU_FLAGS_PROMISC)
5788                 val |= BRXMAC_CONFIG_PROMISC;
5789
5790         if (on)
5791                 val |= BRXMAC_CONFIG_ENABLE;
5792         else
5793                 val &= ~BRXMAC_CONFIG_ENABLE;
5794         nw64_mac(BRXMAC_CONFIG, val);
5795 }
5796
5797 static void niu_enable_rx_mac(struct niu *np, int on)
5798 {
5799         if (np->flags & NIU_FLAGS_XMAC)
5800                 niu_enable_rx_xmac(np, on);
5801         else
5802                 niu_enable_rx_bmac(np, on);
5803 }
5804
5805 static int niu_init_mac(struct niu *np)
5806 {
5807         int err;
5808
5809         niu_init_xif(np);
5810         err = niu_init_pcs(np);
5811         if (err)
5812                 return err;
5813
5814         err = niu_reset_tx_mac(np);
5815         if (err)
5816                 return err;
5817         niu_init_tx_mac(np);
5818         err = niu_reset_rx_mac(np);
5819         if (err)
5820                 return err;
5821         niu_init_rx_mac(np);
5822
5823         /* This looks hookey but the RX MAC reset we just did will
5824          * undo some of the state we setup in niu_init_tx_mac() so we
5825          * have to call it again.  In particular, the RX MAC reset will
5826          * set the XMAC_MAX register back to it's default value.
5827          */
5828         niu_init_tx_mac(np);
5829         niu_enable_tx_mac(np, 1);
5830
5831         niu_enable_rx_mac(np, 1);
5832
5833         return 0;
5834 }
5835
5836 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5837 {
5838         (void) niu_tx_channel_stop(np, rp->tx_channel);
5839 }
5840
5841 static void niu_stop_tx_channels(struct niu *np)
5842 {
5843         int i;
5844
5845         for (i = 0; i < np->num_tx_rings; i++) {
5846                 struct tx_ring_info *rp = &np->tx_rings[i];
5847
5848                 niu_stop_one_tx_channel(np, rp);
5849         }
5850 }
5851
5852 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5853 {
5854         (void) niu_tx_channel_reset(np, rp->tx_channel);
5855 }
5856
5857 static void niu_reset_tx_channels(struct niu *np)
5858 {
5859         int i;
5860
5861         for (i = 0; i < np->num_tx_rings; i++) {
5862                 struct tx_ring_info *rp = &np->tx_rings[i];
5863
5864                 niu_reset_one_tx_channel(np, rp);
5865         }
5866 }
5867
5868 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5869 {
5870         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5871 }
5872
5873 static void niu_stop_rx_channels(struct niu *np)
5874 {
5875         int i;
5876
5877         for (i = 0; i < np->num_rx_rings; i++) {
5878                 struct rx_ring_info *rp = &np->rx_rings[i];
5879
5880                 niu_stop_one_rx_channel(np, rp);
5881         }
5882 }
5883
5884 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5885 {
5886         int channel = rp->rx_channel;
5887
5888         (void) niu_rx_channel_reset(np, channel);
5889         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5890         nw64(RX_DMA_CTL_STAT(channel), 0);
5891         (void) niu_enable_rx_channel(np, channel, 0);
5892 }
5893
5894 static void niu_reset_rx_channels(struct niu *np)
5895 {
5896         int i;
5897
5898         for (i = 0; i < np->num_rx_rings; i++) {
5899                 struct rx_ring_info *rp = &np->rx_rings[i];
5900
5901                 niu_reset_one_rx_channel(np, rp);
5902         }
5903 }
5904
5905 static void niu_disable_ipp(struct niu *np)
5906 {
5907         u64 rd, wr, val;
5908         int limit;
5909
5910         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5911         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5912         limit = 100;
5913         while (--limit >= 0 && (rd != wr)) {
5914                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5915                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5916         }
5917         if (limit < 0 &&
5918             (rd != 0 && wr != 1)) {
5919                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5920                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5921                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5922         }
5923
5924         val = nr64_ipp(IPP_CFIG);
5925         val &= ~(IPP_CFIG_IPP_ENABLE |
5926                  IPP_CFIG_DFIFO_ECC_EN |
5927                  IPP_CFIG_DROP_BAD_CRC |
5928                  IPP_CFIG_CKSUM_EN);
5929         nw64_ipp(IPP_CFIG, val);
5930
5931         (void) niu_ipp_reset(np);
5932 }
5933
5934 static int niu_init_hw(struct niu *np)
5935 {
5936         int i, err;
5937
5938         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5939         niu_txc_enable_port(np, 1);
5940         niu_txc_port_dma_enable(np, 1);
5941         niu_txc_set_imask(np, 0);
5942
5943         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5944         for (i = 0; i < np->num_tx_rings; i++) {
5945                 struct tx_ring_info *rp = &np->tx_rings[i];
5946
5947                 err = niu_init_one_tx_channel(np, rp);
5948                 if (err)
5949                         return err;
5950         }
5951
5952         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5953         err = niu_init_rx_channels(np);
5954         if (err)
5955                 goto out_uninit_tx_channels;
5956
5957         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5958         err = niu_init_classifier_hw(np);
5959         if (err)
5960                 goto out_uninit_rx_channels;
5961
5962         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5963         err = niu_init_zcp(np);
5964         if (err)
5965                 goto out_uninit_rx_channels;
5966
5967         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5968         err = niu_init_ipp(np);
5969         if (err)
5970                 goto out_uninit_rx_channels;
5971
5972         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5973         err = niu_init_mac(np);
5974         if (err)
5975                 goto out_uninit_ipp;
5976
5977         return 0;
5978
5979 out_uninit_ipp:
5980         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5981         niu_disable_ipp(np);
5982
5983 out_uninit_rx_channels:
5984         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5985         niu_stop_rx_channels(np);
5986         niu_reset_rx_channels(np);
5987
5988 out_uninit_tx_channels:
5989         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5990         niu_stop_tx_channels(np);
5991         niu_reset_tx_channels(np);
5992
5993         return err;
5994 }
5995
5996 static void niu_stop_hw(struct niu *np)
5997 {
5998         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
5999         niu_enable_interrupts(np, 0);
6000
6001         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6002         niu_enable_rx_mac(np, 0);
6003
6004         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6005         niu_disable_ipp(np);
6006
6007         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6008         niu_stop_tx_channels(np);
6009
6010         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6011         niu_stop_rx_channels(np);
6012
6013         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6014         niu_reset_tx_channels(np);
6015
6016         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6017         niu_reset_rx_channels(np);
6018 }
6019
6020 static void niu_set_irq_name(struct niu *np)
6021 {
6022         int port = np->port;
6023         int i, j = 1;
6024
6025         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6026
6027         if (port == 0) {
6028                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6029                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6030                 j = 3;
6031         }
6032
6033         for (i = 0; i < np->num_ldg - j; i++) {
6034                 if (i < np->num_rx_rings)
6035                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6036                                 np->dev->name, i);
6037                 else if (i < np->num_tx_rings + np->num_rx_rings)
6038                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6039                                 i - np->num_rx_rings);
6040         }
6041 }
6042
6043 static int niu_request_irq(struct niu *np)
6044 {
6045         int i, j, err;
6046
6047         niu_set_irq_name(np);
6048
6049         err = 0;
6050         for (i = 0; i < np->num_ldg; i++) {
6051                 struct niu_ldg *lp = &np->ldg[i];
6052
6053                 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6054                                   np->irq_name[i], lp);
6055                 if (err)
6056                         goto out_free_irqs;
6057
6058         }
6059
6060         return 0;
6061
6062 out_free_irqs:
6063         for (j = 0; j < i; j++) {
6064                 struct niu_ldg *lp = &np->ldg[j];
6065
6066                 free_irq(lp->irq, lp);
6067         }
6068         return err;
6069 }
6070
6071 static void niu_free_irq(struct niu *np)
6072 {
6073         int i;
6074
6075         for (i = 0; i < np->num_ldg; i++) {
6076                 struct niu_ldg *lp = &np->ldg[i];
6077
6078                 free_irq(lp->irq, lp);
6079         }
6080 }
6081
6082 static void niu_enable_napi(struct niu *np)
6083 {
6084         int i;
6085
6086         for (i = 0; i < np->num_ldg; i++)
6087                 napi_enable(&np->ldg[i].napi);
6088 }
6089
6090 static void niu_disable_napi(struct niu *np)
6091 {
6092         int i;
6093
6094         for (i = 0; i < np->num_ldg; i++)
6095                 napi_disable(&np->ldg[i].napi);
6096 }
6097
6098 static int niu_open(struct net_device *dev)
6099 {
6100         struct niu *np = netdev_priv(dev);
6101         int err;
6102
6103         netif_carrier_off(dev);
6104
6105         err = niu_alloc_channels(np);
6106         if (err)
6107                 goto out_err;
6108
6109         err = niu_enable_interrupts(np, 0);
6110         if (err)
6111                 goto out_free_channels;
6112
6113         err = niu_request_irq(np);
6114         if (err)
6115                 goto out_free_channels;
6116
6117         niu_enable_napi(np);
6118
6119         spin_lock_irq(&np->lock);
6120
6121         err = niu_init_hw(np);
6122         if (!err) {
6123                 init_timer(&np->timer);
6124                 np->timer.expires = jiffies + HZ;
6125                 np->timer.data = (unsigned long) np;
6126                 np->timer.function = niu_timer;
6127
6128                 err = niu_enable_interrupts(np, 1);
6129                 if (err)
6130                         niu_stop_hw(np);
6131         }
6132
6133         spin_unlock_irq(&np->lock);
6134
6135         if (err) {
6136                 niu_disable_napi(np);
6137                 goto out_free_irq;
6138         }
6139
6140         netif_tx_start_all_queues(dev);
6141
6142         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6143                 netif_carrier_on(dev);
6144
6145         add_timer(&np->timer);
6146
6147         return 0;
6148
6149 out_free_irq:
6150         niu_free_irq(np);
6151
6152 out_free_channels:
6153         niu_free_channels(np);
6154
6155 out_err:
6156         return err;
6157 }
6158
6159 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6160 {
6161         cancel_work_sync(&np->reset_task);
6162
6163         niu_disable_napi(np);
6164         netif_tx_stop_all_queues(dev);
6165
6166         del_timer_sync(&np->timer);
6167
6168         spin_lock_irq(&np->lock);
6169
6170         niu_stop_hw(np);
6171
6172         spin_unlock_irq(&np->lock);
6173 }
6174
6175 static int niu_close(struct net_device *dev)
6176 {
6177         struct niu *np = netdev_priv(dev);
6178
6179         niu_full_shutdown(np, dev);
6180
6181         niu_free_irq(np);
6182
6183         niu_free_channels(np);
6184
6185         niu_handle_led(np, 0);
6186
6187         return 0;
6188 }
6189
6190 static void niu_sync_xmac_stats(struct niu *np)
6191 {
6192         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6193
6194         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6195         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6196
6197         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6198         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6199         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6200         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6201         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6202         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6203         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6204         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6205         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6206         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6207         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6208         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6209         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6210         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6211         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6212         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6213 }
6214
6215 static void niu_sync_bmac_stats(struct niu *np)
6216 {
6217         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6218
6219         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6220         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6221
6222         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6223         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6224         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6225         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6226 }
6227
6228 static void niu_sync_mac_stats(struct niu *np)
6229 {
6230         if (np->flags & NIU_FLAGS_XMAC)
6231                 niu_sync_xmac_stats(np);
6232         else
6233                 niu_sync_bmac_stats(np);
6234 }
6235
6236 static void niu_get_rx_stats(struct niu *np,
6237                              struct rtnl_link_stats64 *stats)
6238 {
6239         u64 pkts, dropped, errors, bytes;
6240         struct rx_ring_info *rx_rings;
6241         int i;
6242
6243         pkts = dropped = errors = bytes = 0;
6244
6245         rx_rings = ACCESS_ONCE(np->rx_rings);
6246         if (!rx_rings)
6247                 goto no_rings;
6248
6249         for (i = 0; i < np->num_rx_rings; i++) {
6250                 struct rx_ring_info *rp = &rx_rings[i];
6251
6252                 niu_sync_rx_discard_stats(np, rp, 0);
6253
6254                 pkts += rp->rx_packets;
6255                 bytes += rp->rx_bytes;
6256                 dropped += rp->rx_dropped;
6257                 errors += rp->rx_errors;
6258         }
6259
6260 no_rings:
6261         stats->rx_packets = pkts;
6262         stats->rx_bytes = bytes;
6263         stats->rx_dropped = dropped;
6264         stats->rx_errors = errors;
6265 }
6266
6267 static void niu_get_tx_stats(struct niu *np,
6268                              struct rtnl_link_stats64 *stats)
6269 {
6270         u64 pkts, errors, bytes;
6271         struct tx_ring_info *tx_rings;
6272         int i;
6273
6274         pkts = errors = bytes = 0;
6275
6276         tx_rings = ACCESS_ONCE(np->tx_rings);
6277         if (!tx_rings)
6278                 goto no_rings;
6279
6280         for (i = 0; i < np->num_tx_rings; i++) {
6281                 struct tx_ring_info *rp = &tx_rings[i];
6282
6283                 pkts += rp->tx_packets;
6284                 bytes += rp->tx_bytes;
6285                 errors += rp->tx_errors;
6286         }
6287
6288 no_rings:
6289         stats->tx_packets = pkts;
6290         stats->tx_bytes = bytes;
6291         stats->tx_errors = errors;
6292 }
6293
6294 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6295                                                struct rtnl_link_stats64 *stats)
6296 {
6297         struct niu *np = netdev_priv(dev);
6298
6299         if (netif_running(dev)) {
6300                 niu_get_rx_stats(np, stats);
6301                 niu_get_tx_stats(np, stats);
6302         }
6303
6304         return stats;
6305 }
6306
6307 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6308 {
6309         int i;
6310
6311         for (i = 0; i < 16; i++)
6312                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6313 }
6314
6315 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6316 {
6317         int i;
6318
6319         for (i = 0; i < 16; i++)
6320                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6321 }
6322
6323 static void niu_load_hash(struct niu *np, u16 *hash)
6324 {
6325         if (np->flags & NIU_FLAGS_XMAC)
6326                 niu_load_hash_xmac(np, hash);
6327         else
6328                 niu_load_hash_bmac(np, hash);
6329 }
6330
6331 static void niu_set_rx_mode(struct net_device *dev)
6332 {
6333         struct niu *np = netdev_priv(dev);
6334         int i, alt_cnt, err;
6335         struct netdev_hw_addr *ha;
6336         unsigned long flags;
6337         u16 hash[16] = { 0, };
6338
6339         spin_lock_irqsave(&np->lock, flags);
6340         niu_enable_rx_mac(np, 0);
6341
6342         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6343         if (dev->flags & IFF_PROMISC)
6344                 np->flags |= NIU_FLAGS_PROMISC;
6345         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6346                 np->flags |= NIU_FLAGS_MCAST;
6347
6348         alt_cnt = netdev_uc_count(dev);
6349         if (alt_cnt > niu_num_alt_addr(np)) {
6350                 alt_cnt = 0;
6351                 np->flags |= NIU_FLAGS_PROMISC;
6352         }
6353
6354         if (alt_cnt) {
6355                 int index = 0;
6356
6357                 netdev_for_each_uc_addr(ha, dev) {
6358                         err = niu_set_alt_mac(np, index, ha->addr);
6359                         if (err)
6360                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6361                                             err, index);
6362                         err = niu_enable_alt_mac(np, index, 1);
6363                         if (err)
6364                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6365                                             err, index);
6366
6367                         index++;
6368                 }
6369         } else {
6370                 int alt_start;
6371                 if (np->flags & NIU_FLAGS_XMAC)
6372                         alt_start = 0;
6373                 else
6374                         alt_start = 1;
6375                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6376                         err = niu_enable_alt_mac(np, i, 0);
6377                         if (err)
6378                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6379                                             err, i);
6380                 }
6381         }
6382         if (dev->flags & IFF_ALLMULTI) {
6383                 for (i = 0; i < 16; i++)
6384                         hash[i] = 0xffff;
6385         } else if (!netdev_mc_empty(dev)) {
6386                 netdev_for_each_mc_addr(ha, dev) {
6387                         u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6388
6389                         crc >>= 24;
6390                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6391                 }
6392         }
6393
6394         if (np->flags & NIU_FLAGS_MCAST)
6395                 niu_load_hash(np, hash);
6396
6397         niu_enable_rx_mac(np, 1);
6398         spin_unlock_irqrestore(&np->lock, flags);
6399 }
6400
6401 static int niu_set_mac_addr(struct net_device *dev, void *p)
6402 {
6403         struct niu *np = netdev_priv(dev);
6404         struct sockaddr *addr = p;
6405         unsigned long flags;
6406
6407         if (!is_valid_ether_addr(addr->sa_data))
6408                 return -EADDRNOTAVAIL;
6409
6410         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6411
6412         if (!netif_running(dev))
6413                 return 0;
6414
6415         spin_lock_irqsave(&np->lock, flags);
6416         niu_enable_rx_mac(np, 0);
6417         niu_set_primary_mac(np, dev->dev_addr);
6418         niu_enable_rx_mac(np, 1);
6419         spin_unlock_irqrestore(&np->lock, flags);
6420
6421         return 0;
6422 }
6423
6424 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6425 {
6426         return -EOPNOTSUPP;
6427 }
6428
6429 static void niu_netif_stop(struct niu *np)
6430 {
6431         np->dev->trans_start = jiffies; /* prevent tx timeout */
6432
6433         niu_disable_napi(np);
6434
6435         netif_tx_disable(np->dev);
6436 }
6437
6438 static void niu_netif_start(struct niu *np)
6439 {
6440         /* NOTE: unconditional netif_wake_queue is only appropriate
6441          * so long as all callers are assured to have free tx slots
6442          * (such as after niu_init_hw).
6443          */
6444         netif_tx_wake_all_queues(np->dev);
6445
6446         niu_enable_napi(np);
6447
6448         niu_enable_interrupts(np, 1);
6449 }
6450
6451 static void niu_reset_buffers(struct niu *np)
6452 {
6453         int i, j, k, err;
6454
6455         if (np->rx_rings) {
6456                 for (i = 0; i < np->num_rx_rings; i++) {
6457                         struct rx_ring_info *rp = &np->rx_rings[i];
6458
6459                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6460                                 struct page *page;
6461
6462                                 page = rp->rxhash[j];
6463                                 while (page) {
6464                                         struct page *next =
6465                                                 (struct page *) page->mapping;
6466                                         u64 base = page->index;
6467                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6468                                         rp->rbr[k++] = cpu_to_le32(base);
6469                                         page = next;
6470                                 }
6471                         }
6472                         for (; k < MAX_RBR_RING_SIZE; k++) {
6473                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6474                                 if (unlikely(err))
6475                                         break;
6476                         }
6477
6478                         rp->rbr_index = rp->rbr_table_size - 1;
6479                         rp->rcr_index = 0;
6480                         rp->rbr_pending = 0;
6481                         rp->rbr_refill_pending = 0;
6482                 }
6483         }
6484         if (np->tx_rings) {
6485                 for (i = 0; i < np->num_tx_rings; i++) {
6486                         struct tx_ring_info *rp = &np->tx_rings[i];
6487
6488                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6489                                 if (rp->tx_buffs[j].skb)
6490                                         (void) release_tx_packet(np, rp, j);
6491                         }
6492
6493                         rp->pending = MAX_TX_RING_SIZE;
6494                         rp->prod = 0;
6495                         rp->cons = 0;
6496                         rp->wrap_bit = 0;
6497                 }
6498         }
6499 }
6500
6501 static void niu_reset_task(struct work_struct *work)
6502 {
6503         struct niu *np = container_of(work, struct niu, reset_task);
6504         unsigned long flags;
6505         int err;
6506
6507         spin_lock_irqsave(&np->lock, flags);
6508         if (!netif_running(np->dev)) {
6509                 spin_unlock_irqrestore(&np->lock, flags);
6510                 return;
6511         }
6512
6513         spin_unlock_irqrestore(&np->lock, flags);
6514
6515         del_timer_sync(&np->timer);
6516
6517         niu_netif_stop(np);
6518
6519         spin_lock_irqsave(&np->lock, flags);
6520
6521         niu_stop_hw(np);
6522
6523         spin_unlock_irqrestore(&np->lock, flags);
6524
6525         niu_reset_buffers(np);
6526
6527         spin_lock_irqsave(&np->lock, flags);
6528
6529         err = niu_init_hw(np);
6530         if (!err) {
6531                 np->timer.expires = jiffies + HZ;
6532                 add_timer(&np->timer);
6533                 niu_netif_start(np);
6534         }
6535
6536         spin_unlock_irqrestore(&np->lock, flags);
6537 }
6538
6539 static void niu_tx_timeout(struct net_device *dev)
6540 {
6541         struct niu *np = netdev_priv(dev);
6542
6543         dev_err(np->device, "%s: Transmit timed out, resetting\n",
6544                 dev->name);
6545
6546         schedule_work(&np->reset_task);
6547 }
6548
6549 static void niu_set_txd(struct tx_ring_info *rp, int index,
6550                         u64 mapping, u64 len, u64 mark,
6551                         u64 n_frags)
6552 {
6553         __le64 *desc = &rp->descr[index];
6554
6555         *desc = cpu_to_le64(mark |
6556                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6557                             (len << TX_DESC_TR_LEN_SHIFT) |
6558                             (mapping & TX_DESC_SAD));
6559 }
6560
6561 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6562                                 u64 pad_bytes, u64 len)
6563 {
6564         u16 eth_proto, eth_proto_inner;
6565         u64 csum_bits, l3off, ihl, ret;
6566         u8 ip_proto;
6567         int ipv6;
6568
6569         eth_proto = be16_to_cpu(ehdr->h_proto);
6570         eth_proto_inner = eth_proto;
6571         if (eth_proto == ETH_P_8021Q) {
6572                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6573                 __be16 val = vp->h_vlan_encapsulated_proto;
6574
6575                 eth_proto_inner = be16_to_cpu(val);
6576         }
6577
6578         ipv6 = ihl = 0;
6579         switch (skb->protocol) {
6580         case cpu_to_be16(ETH_P_IP):
6581                 ip_proto = ip_hdr(skb)->protocol;
6582                 ihl = ip_hdr(skb)->ihl;
6583                 break;
6584         case cpu_to_be16(ETH_P_IPV6):
6585                 ip_proto = ipv6_hdr(skb)->nexthdr;
6586                 ihl = (40 >> 2);
6587                 ipv6 = 1;
6588                 break;
6589         default:
6590                 ip_proto = ihl = 0;
6591                 break;
6592         }
6593
6594         csum_bits = TXHDR_CSUM_NONE;
6595         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6596                 u64 start, stuff;
6597
6598                 csum_bits = (ip_proto == IPPROTO_TCP ?
6599                              TXHDR_CSUM_TCP :
6600                              (ip_proto == IPPROTO_UDP ?
6601                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6602
6603                 start = skb_checksum_start_offset(skb) -
6604                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6605                 stuff = start + skb->csum_offset;
6606
6607                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6608                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6609         }
6610
6611         l3off = skb_network_offset(skb) -
6612                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6613
6614         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6615                (len << TXHDR_LEN_SHIFT) |
6616                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6617                (ihl << TXHDR_IHL_SHIFT) |
6618                ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) |
6619                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6620                (ipv6 ? TXHDR_IP_VER : 0) |
6621                csum_bits);
6622
6623         return ret;
6624 }
6625
6626 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6627                                   struct net_device *dev)
6628 {
6629         struct niu *np = netdev_priv(dev);
6630         unsigned long align, headroom;
6631         struct netdev_queue *txq;
6632         struct tx_ring_info *rp;
6633         struct tx_pkt_hdr *tp;
6634         unsigned int len, nfg;
6635         struct ethhdr *ehdr;
6636         int prod, i, tlen;
6637         u64 mapping, mrk;
6638
6639         i = skb_get_queue_mapping(skb);
6640         rp = &np->tx_rings[i];
6641         txq = netdev_get_tx_queue(dev, i);
6642
6643         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6644                 netif_tx_stop_queue(txq);
6645                 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6646                 rp->tx_errors++;
6647                 return NETDEV_TX_BUSY;
6648         }
6649
6650         if (eth_skb_pad(skb))
6651                 goto out;
6652
6653         len = sizeof(struct tx_pkt_hdr) + 15;
6654         if (skb_headroom(skb) < len) {
6655                 struct sk_buff *skb_new;
6656
6657                 skb_new = skb_realloc_headroom(skb, len);
6658                 if (!skb_new)
6659                         goto out_drop;
6660                 kfree_skb(skb);
6661                 skb = skb_new;
6662         } else
6663                 skb_orphan(skb);
6664
6665         align = ((unsigned long) skb->data & (16 - 1));
6666         headroom = align + sizeof(struct tx_pkt_hdr);
6667
6668         ehdr = (struct ethhdr *) skb->data;
6669         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6670
6671         len = skb->len - sizeof(struct tx_pkt_hdr);
6672         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6673         tp->resv = 0;
6674
6675         len = skb_headlen(skb);
6676         mapping = np->ops->map_single(np->device, skb->data,
6677                                       len, DMA_TO_DEVICE);
6678
6679         prod = rp->prod;
6680
6681         rp->tx_buffs[prod].skb = skb;
6682         rp->tx_buffs[prod].mapping = mapping;
6683
6684         mrk = TX_DESC_SOP;
6685         if (++rp->mark_counter == rp->mark_freq) {
6686                 rp->mark_counter = 0;
6687                 mrk |= TX_DESC_MARK;
6688                 rp->mark_pending++;
6689         }
6690
6691         tlen = len;
6692         nfg = skb_shinfo(skb)->nr_frags;
6693         while (tlen > 0) {
6694                 tlen -= MAX_TX_DESC_LEN;
6695                 nfg++;
6696         }
6697
6698         while (len > 0) {
6699                 unsigned int this_len = len;
6700
6701                 if (this_len > MAX_TX_DESC_LEN)
6702                         this_len = MAX_TX_DESC_LEN;
6703
6704                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6705                 mrk = nfg = 0;
6706
6707                 prod = NEXT_TX(rp, prod);
6708                 mapping += this_len;
6709                 len -= this_len;
6710         }
6711
6712         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6713                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6714
6715                 len = skb_frag_size(frag);
6716                 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6717                                             frag->page_offset, len,
6718                                             DMA_TO_DEVICE);
6719
6720                 rp->tx_buffs[prod].skb = NULL;
6721                 rp->tx_buffs[prod].mapping = mapping;
6722
6723                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6724
6725                 prod = NEXT_TX(rp, prod);
6726         }
6727
6728         if (prod < rp->prod)
6729                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6730         rp->prod = prod;
6731
6732         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6733
6734         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6735                 netif_tx_stop_queue(txq);
6736                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6737                         netif_tx_wake_queue(txq);
6738         }
6739
6740 out:
6741         return NETDEV_TX_OK;
6742
6743 out_drop:
6744         rp->tx_errors++;
6745         kfree_skb(skb);
6746         goto out;
6747 }
6748
6749 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6750 {
6751         struct niu *np = netdev_priv(dev);
6752         int err, orig_jumbo, new_jumbo;
6753
6754         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6755                 return -EINVAL;
6756
6757         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6758         new_jumbo = (new_mtu > ETH_DATA_LEN);
6759
6760         dev->mtu = new_mtu;
6761
6762         if (!netif_running(dev) ||
6763             (orig_jumbo == new_jumbo))
6764                 return 0;
6765
6766         niu_full_shutdown(np, dev);
6767
6768         niu_free_channels(np);
6769
6770         niu_enable_napi(np);
6771
6772         err = niu_alloc_channels(np);
6773         if (err)
6774                 return err;
6775
6776         spin_lock_irq(&np->lock);
6777
6778         err = niu_init_hw(np);
6779         if (!err) {
6780                 init_timer(&np->timer);
6781                 np->timer.expires = jiffies + HZ;
6782                 np->timer.data = (unsigned long) np;
6783                 np->timer.function = niu_timer;
6784
6785                 err = niu_enable_interrupts(np, 1);
6786                 if (err)
6787                         niu_stop_hw(np);
6788         }
6789
6790         spin_unlock_irq(&np->lock);
6791
6792         if (!err) {
6793                 netif_tx_start_all_queues(dev);
6794                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6795                         netif_carrier_on(dev);
6796
6797                 add_timer(&np->timer);
6798         }
6799
6800         return err;
6801 }
6802
6803 static void niu_get_drvinfo(struct net_device *dev,
6804                             struct ethtool_drvinfo *info)
6805 {
6806         struct niu *np = netdev_priv(dev);
6807         struct niu_vpd *vpd = &np->vpd;
6808
6809         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6810         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6811         snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6812                 vpd->fcode_major, vpd->fcode_minor);
6813         if (np->parent->plat_type != PLAT_TYPE_NIU)
6814                 strlcpy(info->bus_info, pci_name(np->pdev),
6815                         sizeof(info->bus_info));
6816 }
6817
6818 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6819 {
6820         struct niu *np = netdev_priv(dev);
6821         struct niu_link_config *lp;
6822
6823         lp = &np->link_config;
6824
6825         memset(cmd, 0, sizeof(*cmd));
6826         cmd->phy_address = np->phy_addr;
6827         cmd->supported = lp->supported;
6828         cmd->advertising = lp->active_advertising;
6829         cmd->autoneg = lp->active_autoneg;
6830         ethtool_cmd_speed_set(cmd, lp->active_speed);
6831         cmd->duplex = lp->active_duplex;
6832         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6833         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6834                 XCVR_EXTERNAL : XCVR_INTERNAL;
6835
6836         return 0;
6837 }
6838
6839 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6840 {
6841         struct niu *np = netdev_priv(dev);
6842         struct niu_link_config *lp = &np->link_config;
6843
6844         lp->advertising = cmd->advertising;
6845         lp->speed = ethtool_cmd_speed(cmd);
6846         lp->duplex = cmd->duplex;
6847         lp->autoneg = cmd->autoneg;
6848         return niu_init_link(np);
6849 }
6850
6851 static u32 niu_get_msglevel(struct net_device *dev)
6852 {
6853         struct niu *np = netdev_priv(dev);
6854         return np->msg_enable;
6855 }
6856
6857 static void niu_set_msglevel(struct net_device *dev, u32 value)
6858 {
6859         struct niu *np = netdev_priv(dev);
6860         np->msg_enable = value;
6861 }
6862
6863 static int niu_nway_reset(struct net_device *dev)
6864 {
6865         struct niu *np = netdev_priv(dev);
6866
6867         if (np->link_config.autoneg)
6868                 return niu_init_link(np);
6869
6870         return 0;
6871 }
6872
6873 static int niu_get_eeprom_len(struct net_device *dev)
6874 {
6875         struct niu *np = netdev_priv(dev);
6876
6877         return np->eeprom_len;
6878 }
6879
6880 static int niu_get_eeprom(struct net_device *dev,
6881                           struct ethtool_eeprom *eeprom, u8 *data)
6882 {
6883         struct niu *np = netdev_priv(dev);
6884         u32 offset, len, val;
6885
6886         offset = eeprom->offset;
6887         len = eeprom->len;
6888
6889         if (offset + len < offset)
6890                 return -EINVAL;
6891         if (offset >= np->eeprom_len)
6892                 return -EINVAL;
6893         if (offset + len > np->eeprom_len)
6894                 len = eeprom->len = np->eeprom_len - offset;
6895
6896         if (offset & 3) {
6897                 u32 b_offset, b_count;
6898
6899                 b_offset = offset & 3;
6900                 b_count = 4 - b_offset;
6901                 if (b_count > len)
6902                         b_count = len;
6903
6904                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6905                 memcpy(data, ((char *)&val) + b_offset, b_count);
6906                 data += b_count;
6907                 len -= b_count;
6908                 offset += b_count;
6909         }
6910         while (len >= 4) {
6911                 val = nr64(ESPC_NCR(offset / 4));
6912                 memcpy(data, &val, 4);
6913                 data += 4;
6914                 len -= 4;
6915                 offset += 4;
6916         }
6917         if (len) {
6918                 val = nr64(ESPC_NCR(offset / 4));
6919                 memcpy(data, &val, len);
6920         }
6921         return 0;
6922 }
6923
6924 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6925 {
6926         switch (flow_type) {
6927         case TCP_V4_FLOW:
6928         case TCP_V6_FLOW:
6929                 *pid = IPPROTO_TCP;
6930                 break;
6931         case UDP_V4_FLOW:
6932         case UDP_V6_FLOW:
6933                 *pid = IPPROTO_UDP;
6934                 break;
6935         case SCTP_V4_FLOW:
6936         case SCTP_V6_FLOW:
6937                 *pid = IPPROTO_SCTP;
6938                 break;
6939         case AH_V4_FLOW:
6940         case AH_V6_FLOW:
6941                 *pid = IPPROTO_AH;
6942                 break;
6943         case ESP_V4_FLOW:
6944         case ESP_V6_FLOW:
6945                 *pid = IPPROTO_ESP;
6946                 break;
6947         default:
6948                 *pid = 0;
6949                 break;
6950         }
6951 }
6952
6953 static int niu_class_to_ethflow(u64 class, int *flow_type)
6954 {
6955         switch (class) {
6956         case CLASS_CODE_TCP_IPV4:
6957                 *flow_type = TCP_V4_FLOW;
6958                 break;
6959         case CLASS_CODE_UDP_IPV4:
6960                 *flow_type = UDP_V4_FLOW;
6961                 break;
6962         case CLASS_CODE_AH_ESP_IPV4:
6963                 *flow_type = AH_V4_FLOW;
6964                 break;
6965         case CLASS_CODE_SCTP_IPV4:
6966                 *flow_type = SCTP_V4_FLOW;
6967                 break;
6968         case CLASS_CODE_TCP_IPV6:
6969                 *flow_type = TCP_V6_FLOW;
6970                 break;
6971         case CLASS_CODE_UDP_IPV6:
6972                 *flow_type = UDP_V6_FLOW;
6973                 break;
6974         case CLASS_CODE_AH_ESP_IPV6:
6975                 *flow_type = AH_V6_FLOW;
6976                 break;
6977         case CLASS_CODE_SCTP_IPV6:
6978                 *flow_type = SCTP_V6_FLOW;
6979                 break;
6980         case CLASS_CODE_USER_PROG1:
6981         case CLASS_CODE_USER_PROG2:
6982         case CLASS_CODE_USER_PROG3:
6983         case CLASS_CODE_USER_PROG4:
6984                 *flow_type = IP_USER_FLOW;
6985                 break;
6986         default:
6987                 return -EINVAL;
6988         }
6989
6990         return 0;
6991 }
6992
6993 static int niu_ethflow_to_class(int flow_type, u64 *class)
6994 {
6995         switch (flow_type) {
6996         case TCP_V4_FLOW:
6997                 *class = CLASS_CODE_TCP_IPV4;
6998                 break;
6999         case UDP_V4_FLOW:
7000                 *class = CLASS_CODE_UDP_IPV4;
7001                 break;
7002         case AH_ESP_V4_FLOW:
7003         case AH_V4_FLOW:
7004         case ESP_V4_FLOW:
7005                 *class = CLASS_CODE_AH_ESP_IPV4;
7006                 break;
7007         case SCTP_V4_FLOW:
7008                 *class = CLASS_CODE_SCTP_IPV4;
7009                 break;
7010         case TCP_V6_FLOW:
7011                 *class = CLASS_CODE_TCP_IPV6;
7012                 break;
7013         case UDP_V6_FLOW:
7014                 *class = CLASS_CODE_UDP_IPV6;
7015                 break;
7016         case AH_ESP_V6_FLOW:
7017         case AH_V6_FLOW:
7018         case ESP_V6_FLOW:
7019                 *class = CLASS_CODE_AH_ESP_IPV6;
7020                 break;
7021         case SCTP_V6_FLOW:
7022                 *class = CLASS_CODE_SCTP_IPV6;
7023                 break;
7024         default:
7025                 return 0;
7026         }
7027
7028         return 1;
7029 }
7030
7031 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7032 {
7033         u64 ethflow = 0;
7034
7035         if (flow_key & FLOW_KEY_L2DA)
7036                 ethflow |= RXH_L2DA;
7037         if (flow_key & FLOW_KEY_VLAN)
7038                 ethflow |= RXH_VLAN;
7039         if (flow_key & FLOW_KEY_IPSA)
7040                 ethflow |= RXH_IP_SRC;
7041         if (flow_key & FLOW_KEY_IPDA)
7042                 ethflow |= RXH_IP_DST;
7043         if (flow_key & FLOW_KEY_PROTO)
7044                 ethflow |= RXH_L3_PROTO;
7045         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7046                 ethflow |= RXH_L4_B_0_1;
7047         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7048                 ethflow |= RXH_L4_B_2_3;
7049
7050         return ethflow;
7051
7052 }
7053
7054 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7055 {
7056         u64 key = 0;
7057
7058         if (ethflow & RXH_L2DA)
7059                 key |= FLOW_KEY_L2DA;
7060         if (ethflow & RXH_VLAN)
7061                 key |= FLOW_KEY_VLAN;
7062         if (ethflow & RXH_IP_SRC)
7063                 key |= FLOW_KEY_IPSA;
7064         if (ethflow & RXH_IP_DST)
7065                 key |= FLOW_KEY_IPDA;
7066         if (ethflow & RXH_L3_PROTO)
7067                 key |= FLOW_KEY_PROTO;
7068         if (ethflow & RXH_L4_B_0_1)
7069                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7070         if (ethflow & RXH_L4_B_2_3)
7071                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7072
7073         *flow_key = key;
7074
7075         return 1;
7076
7077 }
7078
7079 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7080 {
7081         u64 class;
7082
7083         nfc->data = 0;
7084
7085         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7086                 return -EINVAL;
7087
7088         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7089             TCAM_KEY_DISC)
7090                 nfc->data = RXH_DISCARD;
7091         else
7092                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7093                                                       CLASS_CODE_USER_PROG1]);
7094         return 0;
7095 }
7096
7097 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7098                                         struct ethtool_rx_flow_spec *fsp)
7099 {
7100         u32 tmp;
7101         u16 prt;
7102
7103         tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7104         fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7105
7106         tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7107         fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7108
7109         tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7110         fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7111
7112         tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7113         fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7114
7115         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7116                 TCAM_V4KEY2_TOS_SHIFT;
7117         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7118                 TCAM_V4KEY2_TOS_SHIFT;
7119
7120         switch (fsp->flow_type) {
7121         case TCP_V4_FLOW:
7122         case UDP_V4_FLOW:
7123         case SCTP_V4_FLOW:
7124                 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7125                         TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7126                 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7127
7128                 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7129                         TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7130                 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7131
7132                 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7133                         TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7134                 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7135
7136                 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7137                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7138                 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7139                 break;
7140         case AH_V4_FLOW:
7141         case ESP_V4_FLOW:
7142                 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7143                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7144                 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7145
7146                 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7147                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7148                 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7149                 break;
7150         case IP_USER_FLOW:
7151                 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7152                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7153                 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7154
7155                 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7156                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7157                 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7158
7159                 fsp->h_u.usr_ip4_spec.proto =
7160                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7161                         TCAM_V4KEY2_PROTO_SHIFT;
7162                 fsp->m_u.usr_ip4_spec.proto =
7163                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7164                         TCAM_V4KEY2_PROTO_SHIFT;
7165
7166                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7167                 break;
7168         default:
7169                 break;
7170         }
7171 }
7172
7173 static int niu_get_ethtool_tcam_entry(struct niu *np,
7174                                       struct ethtool_rxnfc *nfc)
7175 {
7176         struct niu_parent *parent = np->parent;
7177         struct niu_tcam_entry *tp;
7178         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7179         u16 idx;
7180         u64 class;
7181         int ret = 0;
7182
7183         idx = tcam_get_index(np, (u16)nfc->fs.location);
7184
7185         tp = &parent->tcam[idx];
7186         if (!tp->valid) {
7187                 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7188                             parent->index, (u16)nfc->fs.location, idx);
7189                 return -EINVAL;
7190         }
7191
7192         /* fill the flow spec entry */
7193         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7194                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7195         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7196         if (ret < 0) {
7197                 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7198                             parent->index);
7199                 goto out;
7200         }
7201
7202         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7203                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7204                         TCAM_V4KEY2_PROTO_SHIFT;
7205                 if (proto == IPPROTO_ESP) {
7206                         if (fsp->flow_type == AH_V4_FLOW)
7207                                 fsp->flow_type = ESP_V4_FLOW;
7208                         else
7209                                 fsp->flow_type = ESP_V6_FLOW;
7210                 }
7211         }
7212
7213         switch (fsp->flow_type) {
7214         case TCP_V4_FLOW:
7215         case UDP_V4_FLOW:
7216         case SCTP_V4_FLOW:
7217         case AH_V4_FLOW:
7218         case ESP_V4_FLOW:
7219                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7220                 break;
7221         case TCP_V6_FLOW:
7222         case UDP_V6_FLOW:
7223         case SCTP_V6_FLOW:
7224         case AH_V6_FLOW:
7225         case ESP_V6_FLOW:
7226                 /* Not yet implemented */
7227                 ret = -EINVAL;
7228                 break;
7229         case IP_USER_FLOW:
7230                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7231                 break;
7232         default:
7233                 ret = -EINVAL;
7234                 break;
7235         }
7236
7237         if (ret < 0)
7238                 goto out;
7239
7240         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7241                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7242         else
7243                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7244                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7245
7246         /* put the tcam size here */
7247         nfc->data = tcam_get_size(np);
7248 out:
7249         return ret;
7250 }
7251
7252 static int niu_get_ethtool_tcam_all(struct niu *np,
7253                                     struct ethtool_rxnfc *nfc,
7254                                     u32 *rule_locs)
7255 {
7256         struct niu_parent *parent = np->parent;
7257         struct niu_tcam_entry *tp;
7258         int i, idx, cnt;
7259         unsigned long flags;
7260         int ret = 0;
7261
7262         /* put the tcam size here */
7263         nfc->data = tcam_get_size(np);
7264
7265         niu_lock_parent(np, flags);
7266         for (cnt = 0, i = 0; i < nfc->data; i++) {
7267                 idx = tcam_get_index(np, i);
7268                 tp = &parent->tcam[idx];
7269                 if (!tp->valid)
7270                         continue;
7271                 if (cnt == nfc->rule_cnt) {
7272                         ret = -EMSGSIZE;
7273                         break;
7274                 }
7275                 rule_locs[cnt] = i;
7276                 cnt++;
7277         }
7278         niu_unlock_parent(np, flags);
7279
7280         nfc->rule_cnt = cnt;
7281
7282         return ret;
7283 }
7284
7285 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7286                        u32 *rule_locs)
7287 {
7288         struct niu *np = netdev_priv(dev);
7289         int ret = 0;
7290
7291         switch (cmd->cmd) {
7292         case ETHTOOL_GRXFH:
7293                 ret = niu_get_hash_opts(np, cmd);
7294                 break;
7295         case ETHTOOL_GRXRINGS:
7296                 cmd->data = np->num_rx_rings;
7297                 break;
7298         case ETHTOOL_GRXCLSRLCNT:
7299                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7300                 break;
7301         case ETHTOOL_GRXCLSRULE:
7302                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7303                 break;
7304         case ETHTOOL_GRXCLSRLALL:
7305                 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7306                 break;
7307         default:
7308                 ret = -EINVAL;
7309                 break;
7310         }
7311
7312         return ret;
7313 }
7314
7315 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7316 {
7317         u64 class;
7318         u64 flow_key = 0;
7319         unsigned long flags;
7320
7321         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7322                 return -EINVAL;
7323
7324         if (class < CLASS_CODE_USER_PROG1 ||
7325             class > CLASS_CODE_SCTP_IPV6)
7326                 return -EINVAL;
7327
7328         if (nfc->data & RXH_DISCARD) {
7329                 niu_lock_parent(np, flags);
7330                 flow_key = np->parent->tcam_key[class -
7331                                                CLASS_CODE_USER_PROG1];
7332                 flow_key |= TCAM_KEY_DISC;
7333                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7334                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7335                 niu_unlock_parent(np, flags);
7336                 return 0;
7337         } else {
7338                 /* Discard was set before, but is not set now */
7339                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7340                     TCAM_KEY_DISC) {
7341                         niu_lock_parent(np, flags);
7342                         flow_key = np->parent->tcam_key[class -
7343                                                CLASS_CODE_USER_PROG1];
7344                         flow_key &= ~TCAM_KEY_DISC;
7345                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7346                              flow_key);
7347                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7348                                 flow_key;
7349                         niu_unlock_parent(np, flags);
7350                 }
7351         }
7352
7353         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7354                 return -EINVAL;
7355
7356         niu_lock_parent(np, flags);
7357         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7358         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7359         niu_unlock_parent(np, flags);
7360
7361         return 0;
7362 }
7363
7364 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7365                                        struct niu_tcam_entry *tp,
7366                                        int l2_rdc_tab, u64 class)
7367 {
7368         u8 pid = 0;
7369         u32 sip, dip, sipm, dipm, spi, spim;
7370         u16 sport, dport, spm, dpm;
7371
7372         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7373         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7374         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7375         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7376
7377         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7378         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7379         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7380         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7381
7382         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7383         tp->key[3] |= dip;
7384
7385         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7386         tp->key_mask[3] |= dipm;
7387
7388         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7389                        TCAM_V4KEY2_TOS_SHIFT);
7390         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7391                             TCAM_V4KEY2_TOS_SHIFT);
7392         switch (fsp->flow_type) {
7393         case TCP_V4_FLOW:
7394         case UDP_V4_FLOW:
7395         case SCTP_V4_FLOW:
7396                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7397                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7398                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7399                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7400
7401                 tp->key[2] |= (((u64)sport << 16) | dport);
7402                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7403                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7404                 break;
7405         case AH_V4_FLOW:
7406         case ESP_V4_FLOW:
7407                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7408                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7409
7410                 tp->key[2] |= spi;
7411                 tp->key_mask[2] |= spim;
7412                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7413                 break;
7414         case IP_USER_FLOW:
7415                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7416                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7417
7418                 tp->key[2] |= spi;
7419                 tp->key_mask[2] |= spim;
7420                 pid = fsp->h_u.usr_ip4_spec.proto;
7421                 break;
7422         default:
7423                 break;
7424         }
7425
7426         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7427         if (pid) {
7428                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7429         }
7430 }
7431
7432 static int niu_add_ethtool_tcam_entry(struct niu *np,
7433                                       struct ethtool_rxnfc *nfc)
7434 {
7435         struct niu_parent *parent = np->parent;
7436         struct niu_tcam_entry *tp;
7437         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7438         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7439         int l2_rdc_table = rdc_table->first_table_num;
7440         u16 idx;
7441         u64 class;
7442         unsigned long flags;
7443         int err, ret;
7444
7445         ret = 0;
7446
7447         idx = nfc->fs.location;
7448         if (idx >= tcam_get_size(np))
7449                 return -EINVAL;
7450
7451         if (fsp->flow_type == IP_USER_FLOW) {
7452                 int i;
7453                 int add_usr_cls = 0;
7454                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7455                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7456
7457                 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7458                         return -EINVAL;
7459
7460                 niu_lock_parent(np, flags);
7461
7462                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7463                         if (parent->l3_cls[i]) {
7464                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7465                                         class = parent->l3_cls[i];
7466                                         parent->l3_cls_refcnt[i]++;
7467                                         add_usr_cls = 1;
7468                                         break;
7469                                 }
7470                         } else {
7471                                 /* Program new user IP class */
7472                                 switch (i) {
7473                                 case 0:
7474                                         class = CLASS_CODE_USER_PROG1;
7475                                         break;
7476                                 case 1:
7477                                         class = CLASS_CODE_USER_PROG2;
7478                                         break;
7479                                 case 2:
7480                                         class = CLASS_CODE_USER_PROG3;
7481                                         break;
7482                                 case 3:
7483                                         class = CLASS_CODE_USER_PROG4;
7484                                         break;
7485                                 default:
7486                                         break;
7487                                 }
7488                                 ret = tcam_user_ip_class_set(np, class, 0,
7489                                                              uspec->proto,
7490                                                              uspec->tos,
7491                                                              umask->tos);
7492                                 if (ret)
7493                                         goto out;
7494
7495                                 ret = tcam_user_ip_class_enable(np, class, 1);
7496                                 if (ret)
7497                                         goto out;
7498                                 parent->l3_cls[i] = class;
7499                                 parent->l3_cls_pid[i] = uspec->proto;
7500                                 parent->l3_cls_refcnt[i]++;
7501                                 add_usr_cls = 1;
7502                                 break;
7503                         }
7504                 }
7505                 if (!add_usr_cls) {
7506                         netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7507                                     parent->index, __func__, uspec->proto);
7508                         ret = -EINVAL;
7509                         goto out;
7510                 }
7511                 niu_unlock_parent(np, flags);
7512         } else {
7513                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7514                         return -EINVAL;
7515                 }
7516         }
7517
7518         niu_lock_parent(np, flags);
7519
7520         idx = tcam_get_index(np, idx);
7521         tp = &parent->tcam[idx];
7522
7523         memset(tp, 0, sizeof(*tp));
7524
7525         /* fill in the tcam key and mask */
7526         switch (fsp->flow_type) {
7527         case TCP_V4_FLOW:
7528         case UDP_V4_FLOW:
7529         case SCTP_V4_FLOW:
7530         case AH_V4_FLOW:
7531         case ESP_V4_FLOW:
7532                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7533                 break;
7534         case TCP_V6_FLOW:
7535         case UDP_V6_FLOW:
7536         case SCTP_V6_FLOW:
7537         case AH_V6_FLOW:
7538         case ESP_V6_FLOW:
7539                 /* Not yet implemented */
7540                 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7541                             parent->index, __func__, fsp->flow_type);
7542                 ret = -EINVAL;
7543                 goto out;
7544         case IP_USER_FLOW:
7545                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7546                 break;
7547         default:
7548                 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7549                             parent->index, __func__, fsp->flow_type);
7550                 ret = -EINVAL;
7551                 goto out;
7552         }
7553
7554         /* fill in the assoc data */
7555         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7556                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7557         } else {
7558                 if (fsp->ring_cookie >= np->num_rx_rings) {
7559                         netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7560                                     parent->index, __func__,
7561                                     (long long)fsp->ring_cookie);
7562                         ret = -EINVAL;
7563                         goto out;
7564                 }
7565                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7566                                   (fsp->ring_cookie <<
7567                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7568         }
7569
7570         err = tcam_write(np, idx, tp->key, tp->key_mask);
7571         if (err) {
7572                 ret = -EINVAL;
7573                 goto out;
7574         }
7575         err = tcam_assoc_write(np, idx, tp->assoc_data);
7576         if (err) {
7577                 ret = -EINVAL;
7578                 goto out;
7579         }
7580
7581         /* validate the entry */
7582         tp->valid = 1;
7583         np->clas.tcam_valid_entries++;
7584 out:
7585         niu_unlock_parent(np, flags);
7586
7587         return ret;
7588 }
7589
7590 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7591 {
7592         struct niu_parent *parent = np->parent;
7593         struct niu_tcam_entry *tp;
7594         u16 idx;
7595         unsigned long flags;
7596         u64 class;
7597         int ret = 0;
7598
7599         if (loc >= tcam_get_size(np))
7600                 return -EINVAL;
7601
7602         niu_lock_parent(np, flags);
7603
7604         idx = tcam_get_index(np, loc);
7605         tp = &parent->tcam[idx];
7606
7607         /* if the entry is of a user defined class, then update*/
7608         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7609                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7610
7611         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7612                 int i;
7613                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7614                         if (parent->l3_cls[i] == class) {
7615                                 parent->l3_cls_refcnt[i]--;
7616                                 if (!parent->l3_cls_refcnt[i]) {
7617                                         /* disable class */
7618                                         ret = tcam_user_ip_class_enable(np,
7619                                                                         class,
7620                                                                         0);
7621                                         if (ret)
7622                                                 goto out;
7623                                         parent->l3_cls[i] = 0;
7624                                         parent->l3_cls_pid[i] = 0;
7625                                 }
7626                                 break;
7627                         }
7628                 }
7629                 if (i == NIU_L3_PROG_CLS) {
7630                         netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7631                                     parent->index, __func__,
7632                                     (unsigned long long)class);
7633                         ret = -EINVAL;
7634                         goto out;
7635                 }
7636         }
7637
7638         ret = tcam_flush(np, idx);
7639         if (ret)
7640                 goto out;
7641
7642         /* invalidate the entry */
7643         tp->valid = 0;
7644         np->clas.tcam_valid_entries--;
7645 out:
7646         niu_unlock_parent(np, flags);
7647
7648         return ret;
7649 }
7650
7651 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7652 {
7653         struct niu *np = netdev_priv(dev);
7654         int ret = 0;
7655
7656         switch (cmd->cmd) {
7657         case ETHTOOL_SRXFH:
7658                 ret = niu_set_hash_opts(np, cmd);
7659                 break;
7660         case ETHTOOL_SRXCLSRLINS:
7661                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7662                 break;
7663         case ETHTOOL_SRXCLSRLDEL:
7664                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7665                 break;
7666         default:
7667                 ret = -EINVAL;
7668                 break;
7669         }
7670
7671         return ret;
7672 }
7673
7674 static const struct {
7675         const char string[ETH_GSTRING_LEN];
7676 } niu_xmac_stat_keys[] = {
7677         { "tx_frames" },
7678         { "tx_bytes" },
7679         { "tx_fifo_errors" },
7680         { "tx_overflow_errors" },
7681         { "tx_max_pkt_size_errors" },
7682         { "tx_underflow_errors" },
7683         { "rx_local_faults" },
7684         { "rx_remote_faults" },
7685         { "rx_link_faults" },
7686         { "rx_align_errors" },
7687         { "rx_frags" },
7688         { "rx_mcasts" },
7689         { "rx_bcasts" },
7690         { "rx_hist_cnt1" },
7691         { "rx_hist_cnt2" },
7692         { "rx_hist_cnt3" },
7693         { "rx_hist_cnt4" },
7694         { "rx_hist_cnt5" },
7695         { "rx_hist_cnt6" },
7696         { "rx_hist_cnt7" },
7697         { "rx_octets" },
7698         { "rx_code_violations" },
7699         { "rx_len_errors" },
7700         { "rx_crc_errors" },
7701         { "rx_underflows" },
7702         { "rx_overflows" },
7703         { "pause_off_state" },
7704         { "pause_on_state" },
7705         { "pause_received" },
7706 };
7707
7708 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7709
7710 static const struct {
7711         const char string[ETH_GSTRING_LEN];
7712 } niu_bmac_stat_keys[] = {
7713         { "tx_underflow_errors" },
7714         { "tx_max_pkt_size_errors" },
7715         { "tx_bytes" },
7716         { "tx_frames" },
7717         { "rx_overflows" },
7718         { "rx_frames" },
7719         { "rx_align_errors" },
7720         { "rx_crc_errors" },
7721         { "rx_len_errors" },
7722         { "pause_off_state" },
7723         { "pause_on_state" },
7724         { "pause_received" },
7725 };
7726
7727 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7728
7729 static const struct {
7730         const char string[ETH_GSTRING_LEN];
7731 } niu_rxchan_stat_keys[] = {
7732         { "rx_channel" },
7733         { "rx_packets" },
7734         { "rx_bytes" },
7735         { "rx_dropped" },
7736         { "rx_errors" },
7737 };
7738
7739 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7740
7741 static const struct {
7742         const char string[ETH_GSTRING_LEN];
7743 } niu_txchan_stat_keys[] = {
7744         { "tx_channel" },
7745         { "tx_packets" },
7746         { "tx_bytes" },
7747         { "tx_errors" },
7748 };
7749
7750 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7751
7752 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7753 {
7754         struct niu *np = netdev_priv(dev);
7755         int i;
7756
7757         if (stringset != ETH_SS_STATS)
7758                 return;
7759
7760         if (np->flags & NIU_FLAGS_XMAC) {
7761                 memcpy(data, niu_xmac_stat_keys,
7762                        sizeof(niu_xmac_stat_keys));
7763                 data += sizeof(niu_xmac_stat_keys);
7764         } else {
7765                 memcpy(data, niu_bmac_stat_keys,
7766                        sizeof(niu_bmac_stat_keys));
7767                 data += sizeof(niu_bmac_stat_keys);
7768         }
7769         for (i = 0; i < np->num_rx_rings; i++) {
7770                 memcpy(data, niu_rxchan_stat_keys,
7771                        sizeof(niu_rxchan_stat_keys));
7772                 data += sizeof(niu_rxchan_stat_keys);
7773         }
7774         for (i = 0; i < np->num_tx_rings; i++) {
7775                 memcpy(data, niu_txchan_stat_keys,
7776                        sizeof(niu_txchan_stat_keys));
7777                 data += sizeof(niu_txchan_stat_keys);
7778         }
7779 }
7780
7781 static int niu_get_sset_count(struct net_device *dev, int stringset)
7782 {
7783         struct niu *np = netdev_priv(dev);
7784
7785         if (stringset != ETH_SS_STATS)
7786                 return -EINVAL;
7787
7788         return (np->flags & NIU_FLAGS_XMAC ?
7789                  NUM_XMAC_STAT_KEYS :
7790                  NUM_BMAC_STAT_KEYS) +
7791                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7792                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7793 }
7794
7795 static void niu_get_ethtool_stats(struct net_device *dev,
7796                                   struct ethtool_stats *stats, u64 *data)
7797 {
7798         struct niu *np = netdev_priv(dev);
7799         int i;
7800
7801         niu_sync_mac_stats(np);
7802         if (np->flags & NIU_FLAGS_XMAC) {
7803                 memcpy(data, &np->mac_stats.xmac,
7804                        sizeof(struct niu_xmac_stats));
7805                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7806         } else {
7807                 memcpy(data, &np->mac_stats.bmac,
7808                        sizeof(struct niu_bmac_stats));
7809                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7810         }
7811         for (i = 0; i < np->num_rx_rings; i++) {
7812                 struct rx_ring_info *rp = &np->rx_rings[i];
7813
7814                 niu_sync_rx_discard_stats(np, rp, 0);
7815
7816                 data[0] = rp->rx_channel;
7817                 data[1] = rp->rx_packets;
7818                 data[2] = rp->rx_bytes;
7819                 data[3] = rp->rx_dropped;
7820                 data[4] = rp->rx_errors;
7821                 data += 5;
7822         }
7823         for (i = 0; i < np->num_tx_rings; i++) {
7824                 struct tx_ring_info *rp = &np->tx_rings[i];
7825
7826                 data[0] = rp->tx_channel;
7827                 data[1] = rp->tx_packets;
7828                 data[2] = rp->tx_bytes;
7829                 data[3] = rp->tx_errors;
7830                 data += 4;
7831         }
7832 }
7833
7834 static u64 niu_led_state_save(struct niu *np)
7835 {
7836         if (np->flags & NIU_FLAGS_XMAC)
7837                 return nr64_mac(XMAC_CONFIG);
7838         else
7839                 return nr64_mac(BMAC_XIF_CONFIG);
7840 }
7841
7842 static void niu_led_state_restore(struct niu *np, u64 val)
7843 {
7844         if (np->flags & NIU_FLAGS_XMAC)
7845                 nw64_mac(XMAC_CONFIG, val);
7846         else
7847                 nw64_mac(BMAC_XIF_CONFIG, val);
7848 }
7849
7850 static void niu_force_led(struct niu *np, int on)
7851 {
7852         u64 val, reg, bit;
7853
7854         if (np->flags & NIU_FLAGS_XMAC) {
7855                 reg = XMAC_CONFIG;
7856                 bit = XMAC_CONFIG_FORCE_LED_ON;
7857         } else {
7858                 reg = BMAC_XIF_CONFIG;
7859                 bit = BMAC_XIF_CONFIG_LINK_LED;
7860         }
7861
7862         val = nr64_mac(reg);
7863         if (on)
7864                 val |= bit;
7865         else
7866                 val &= ~bit;
7867         nw64_mac(reg, val);
7868 }
7869
7870 static int niu_set_phys_id(struct net_device *dev,
7871                            enum ethtool_phys_id_state state)
7872
7873 {
7874         struct niu *np = netdev_priv(dev);
7875
7876         if (!netif_running(dev))
7877                 return -EAGAIN;
7878
7879         switch (state) {
7880         case ETHTOOL_ID_ACTIVE:
7881                 np->orig_led_state = niu_led_state_save(np);
7882                 return 1;       /* cycle on/off once per second */
7883
7884         case ETHTOOL_ID_ON:
7885                 niu_force_led(np, 1);
7886                 break;
7887
7888         case ETHTOOL_ID_OFF:
7889                 niu_force_led(np, 0);
7890                 break;
7891
7892         case ETHTOOL_ID_INACTIVE:
7893                 niu_led_state_restore(np, np->orig_led_state);
7894         }
7895
7896         return 0;
7897 }
7898
7899 static const struct ethtool_ops niu_ethtool_ops = {
7900         .get_drvinfo            = niu_get_drvinfo,
7901         .get_link               = ethtool_op_get_link,
7902         .get_msglevel           = niu_get_msglevel,
7903         .set_msglevel           = niu_set_msglevel,
7904         .nway_reset             = niu_nway_reset,
7905         .get_eeprom_len         = niu_get_eeprom_len,
7906         .get_eeprom             = niu_get_eeprom,
7907         .get_settings           = niu_get_settings,
7908         .set_settings           = niu_set_settings,
7909         .get_strings            = niu_get_strings,
7910         .get_sset_count         = niu_get_sset_count,
7911         .get_ethtool_stats      = niu_get_ethtool_stats,
7912         .set_phys_id            = niu_set_phys_id,
7913         .get_rxnfc              = niu_get_nfc,
7914         .set_rxnfc              = niu_set_nfc,
7915 };
7916
7917 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7918                               int ldg, int ldn)
7919 {
7920         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7921                 return -EINVAL;
7922         if (ldn < 0 || ldn > LDN_MAX)
7923                 return -EINVAL;
7924
7925         parent->ldg_map[ldn] = ldg;
7926
7927         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7928                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7929                  * the firmware, and we're not supposed to change them.
7930                  * Validate the mapping, because if it's wrong we probably
7931                  * won't get any interrupts and that's painful to debug.
7932                  */
7933                 if (nr64(LDG_NUM(ldn)) != ldg) {
7934                         dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7935                                 np->port, ldn, ldg,
7936                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7937                         return -EINVAL;
7938                 }
7939         } else
7940                 nw64(LDG_NUM(ldn), ldg);
7941
7942         return 0;
7943 }
7944
7945 static int niu_set_ldg_timer_res(struct niu *np, int res)
7946 {
7947         if (res < 0 || res > LDG_TIMER_RES_VAL)
7948                 return -EINVAL;
7949
7950
7951         nw64(LDG_TIMER_RES, res);
7952
7953         return 0;
7954 }
7955
7956 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7957 {
7958         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7959             (func < 0 || func > 3) ||
7960             (vector < 0 || vector > 0x1f))
7961                 return -EINVAL;
7962
7963         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7964
7965         return 0;
7966 }
7967
7968 static int niu_pci_eeprom_read(struct niu *np, u32 addr)
7969 {
7970         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7971                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7972         int limit;
7973
7974         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7975                 return -EINVAL;
7976
7977         frame = frame_base;
7978         nw64(ESPC_PIO_STAT, frame);
7979         limit = 64;
7980         do {
7981                 udelay(5);
7982                 frame = nr64(ESPC_PIO_STAT);
7983                 if (frame & ESPC_PIO_STAT_READ_END)
7984                         break;
7985         } while (limit--);
7986         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7987                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7988                         (unsigned long long) frame);
7989                 return -ENODEV;
7990         }
7991
7992         frame = frame_base;
7993         nw64(ESPC_PIO_STAT, frame);
7994         limit = 64;
7995         do {
7996                 udelay(5);
7997                 frame = nr64(ESPC_PIO_STAT);
7998                 if (frame & ESPC_PIO_STAT_READ_END)
7999                         break;
8000         } while (limit--);
8001         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8002                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8003                         (unsigned long long) frame);
8004                 return -ENODEV;
8005         }
8006
8007         frame = nr64(ESPC_PIO_STAT);
8008         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8009 }
8010
8011 static int niu_pci_eeprom_read16(struct niu *np, u32 off)
8012 {
8013         int err = niu_pci_eeprom_read(np, off);
8014         u16 val;
8015
8016         if (err < 0)
8017                 return err;
8018         val = (err << 8);
8019         err = niu_pci_eeprom_read(np, off + 1);
8020         if (err < 0)
8021                 return err;
8022         val |= (err & 0xff);
8023
8024         return val;
8025 }
8026
8027 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8028 {
8029         int err = niu_pci_eeprom_read(np, off);
8030         u16 val;
8031
8032         if (err < 0)
8033                 return err;
8034
8035         val = (err & 0xff);
8036         err = niu_pci_eeprom_read(np, off + 1);
8037         if (err < 0)
8038                 return err;
8039
8040         val |= (err & 0xff) << 8;
8041
8042         return val;
8043 }
8044
8045 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf,
8046                                     int namebuf_len)
8047 {
8048         int i;
8049
8050         for (i = 0; i < namebuf_len; i++) {
8051                 int err = niu_pci_eeprom_read(np, off + i);
8052                 if (err < 0)
8053                         return err;
8054                 *namebuf++ = err;
8055                 if (!err)
8056                         break;
8057         }
8058         if (i >= namebuf_len)
8059                 return -EINVAL;
8060
8061         return i + 1;
8062 }
8063
8064 static void niu_vpd_parse_version(struct niu *np)
8065 {
8066         struct niu_vpd *vpd = &np->vpd;
8067         int len = strlen(vpd->version) + 1;
8068         const char *s = vpd->version;
8069         int i;
8070
8071         for (i = 0; i < len - 5; i++) {
8072                 if (!strncmp(s + i, "FCode ", 6))
8073                         break;
8074         }
8075         if (i >= len - 5)
8076                 return;
8077
8078         s += i + 5;
8079         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8080
8081         netif_printk(np, probe, KERN_DEBUG, np->dev,
8082                      "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8083                      vpd->fcode_major, vpd->fcode_minor);
8084         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8085             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8086              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8087                 np->flags |= NIU_FLAGS_VPD_VALID;
8088 }
8089
8090 /* ESPC_PIO_EN_ENABLE must be set */
8091 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)
8092 {
8093         unsigned int found_mask = 0;
8094 #define FOUND_MASK_MODEL        0x00000001
8095 #define FOUND_MASK_BMODEL       0x00000002
8096 #define FOUND_MASK_VERS         0x00000004
8097 #define FOUND_MASK_MAC          0x00000008
8098 #define FOUND_MASK_NMAC         0x00000010
8099 #define FOUND_MASK_PHY          0x00000020
8100 #define FOUND_MASK_ALL          0x0000003f
8101
8102         netif_printk(np, probe, KERN_DEBUG, np->dev,
8103                      "VPD_SCAN: start[%x] end[%x]\n", start, end);
8104         while (start < end) {
8105                 int len, err, prop_len;
8106                 char namebuf[64];
8107                 u8 *prop_buf;
8108                 int max_len;
8109
8110                 if (found_mask == FOUND_MASK_ALL) {
8111                         niu_vpd_parse_version(np);
8112                         return 1;
8113                 }
8114
8115                 err = niu_pci_eeprom_read(np, start + 2);
8116                 if (err < 0)
8117                         return err;
8118                 len = err;
8119                 start += 3;
8120
8121                 prop_len = niu_pci_eeprom_read(np, start + 4);
8122                 if (prop_len < 0)
8123                         return prop_len;
8124                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8125                 if (err < 0)
8126                         return err;
8127
8128                 prop_buf = NULL;
8129                 max_len = 0;
8130                 if (!strcmp(namebuf, "model")) {
8131                         prop_buf = np->vpd.model;
8132                         max_len = NIU_VPD_MODEL_MAX;
8133                         found_mask |= FOUND_MASK_MODEL;
8134                 } else if (!strcmp(namebuf, "board-model")) {
8135                         prop_buf = np->vpd.board_model;
8136                         max_len = NIU_VPD_BD_MODEL_MAX;
8137                         found_mask |= FOUND_MASK_BMODEL;
8138                 } else if (!strcmp(namebuf, "version")) {
8139                         prop_buf = np->vpd.version;
8140                         max_len = NIU_VPD_VERSION_MAX;
8141                         found_mask |= FOUND_MASK_VERS;
8142                 } else if (!strcmp(namebuf, "local-mac-address")) {
8143                         prop_buf = np->vpd.local_mac;
8144                         max_len = ETH_ALEN;
8145                         found_mask |= FOUND_MASK_MAC;
8146                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8147                         prop_buf = &np->vpd.mac_num;
8148                         max_len = 1;
8149                         found_mask |= FOUND_MASK_NMAC;
8150                 } else if (!strcmp(namebuf, "phy-type")) {
8151                         prop_buf = np->vpd.phy_type;
8152                         max_len = NIU_VPD_PHY_TYPE_MAX;
8153                         found_mask |= FOUND_MASK_PHY;
8154                 }
8155
8156                 if (max_len && prop_len > max_len) {
8157                         dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8158                         return -EINVAL;
8159                 }
8160
8161                 if (prop_buf) {
8162                         u32 off = start + 5 + err;
8163                         int i;
8164
8165                         netif_printk(np, probe, KERN_DEBUG, np->dev,
8166                                      "VPD_SCAN: Reading in property [%s] len[%d]\n",
8167                                      namebuf, prop_len);
8168                         for (i = 0; i < prop_len; i++) {
8169                                 err =  niu_pci_eeprom_read(np, off + i);
8170                                 if (err < 0)
8171                                         return err;
8172                                 *prop_buf++ = err;
8173                         }
8174                 }
8175
8176                 start += len;
8177         }
8178
8179         return 0;
8180 }
8181
8182 /* ESPC_PIO_EN_ENABLE must be set */
8183 static int niu_pci_vpd_fetch(struct niu *np, u32 start)
8184 {
8185         u32 offset;
8186         int err;
8187
8188         err = niu_pci_eeprom_read16_swp(np, start + 1);
8189         if (err < 0)
8190                 return err;
8191
8192         offset = err + 3;
8193
8194         while (start + offset < ESPC_EEPROM_SIZE) {
8195                 u32 here = start + offset;
8196                 u32 end;
8197
8198                 err = niu_pci_eeprom_read(np, here);
8199                 if (err < 0)
8200                         return err;
8201                 if (err != 0x90)
8202                         return -EINVAL;
8203
8204                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8205                 if (err < 0)
8206                         return err;
8207
8208                 here = start + offset + 3;
8209                 end = start + offset + err;
8210
8211                 offset += err;
8212
8213                 err = niu_pci_vpd_scan_props(np, here, end);
8214                 if (err < 0)
8215                         return err;
8216                 /* ret == 1 is not an error */
8217                 if (err == 1)
8218                         return 0;
8219         }
8220         return 0;
8221 }
8222
8223 /* ESPC_PIO_EN_ENABLE must be set */
8224 static u32 niu_pci_vpd_offset(struct niu *np)
8225 {
8226         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8227         int err;
8228
8229         while (start < end) {
8230                 ret = start;
8231
8232                 /* ROM header signature?  */
8233                 err = niu_pci_eeprom_read16(np, start +  0);
8234                 if (err != 0x55aa)
8235                         return 0;
8236
8237                 /* Apply offset to PCI data structure.  */
8238                 err = niu_pci_eeprom_read16(np, start + 23);
8239                 if (err < 0)
8240                         return 0;
8241                 start += err;
8242
8243                 /* Check for "PCIR" signature.  */
8244                 err = niu_pci_eeprom_read16(np, start +  0);
8245                 if (err != 0x5043)
8246                         return 0;
8247                 err = niu_pci_eeprom_read16(np, start +  2);
8248                 if (err != 0x4952)
8249                         return 0;
8250
8251                 /* Check for OBP image type.  */
8252                 err = niu_pci_eeprom_read(np, start + 20);
8253                 if (err < 0)
8254                         return 0;
8255                 if (err != 0x01) {
8256                         err = niu_pci_eeprom_read(np, ret + 2);
8257                         if (err < 0)
8258                                 return 0;
8259
8260                         start = ret + (err * 512);
8261                         continue;
8262                 }
8263
8264                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8265                 if (err < 0)
8266                         return err;
8267                 ret += err;
8268
8269                 err = niu_pci_eeprom_read(np, ret + 0);
8270                 if (err != 0x82)
8271                         return 0;
8272
8273                 return ret;
8274         }
8275
8276         return 0;
8277 }
8278
8279 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop)
8280 {
8281         if (!strcmp(phy_prop, "mif")) {
8282                 /* 1G copper, MII */
8283                 np->flags &= ~(NIU_FLAGS_FIBER |
8284                                NIU_FLAGS_10G);
8285                 np->mac_xcvr = MAC_XCVR_MII;
8286         } else if (!strcmp(phy_prop, "xgf")) {
8287                 /* 10G fiber, XPCS */
8288                 np->flags |= (NIU_FLAGS_10G |
8289                               NIU_FLAGS_FIBER);
8290                 np->mac_xcvr = MAC_XCVR_XPCS;
8291         } else if (!strcmp(phy_prop, "pcs")) {
8292                 /* 1G fiber, PCS */
8293                 np->flags &= ~NIU_FLAGS_10G;
8294                 np->flags |= NIU_FLAGS_FIBER;
8295                 np->mac_xcvr = MAC_XCVR_PCS;
8296         } else if (!strcmp(phy_prop, "xgc")) {
8297                 /* 10G copper, XPCS */
8298                 np->flags |= NIU_FLAGS_10G;
8299                 np->flags &= ~NIU_FLAGS_FIBER;
8300                 np->mac_xcvr = MAC_XCVR_XPCS;
8301         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8302                 /* 10G Serdes or 1G Serdes, default to 10G */
8303                 np->flags |= NIU_FLAGS_10G;
8304                 np->flags &= ~NIU_FLAGS_FIBER;
8305                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8306                 np->mac_xcvr = MAC_XCVR_XPCS;
8307         } else {
8308                 return -EINVAL;
8309         }
8310         return 0;
8311 }
8312
8313 static int niu_pci_vpd_get_nports(struct niu *np)
8314 {
8315         int ports = 0;
8316
8317         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8318             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8319             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8320             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8321             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8322                 ports = 4;
8323         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8324                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8325                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8326                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8327                 ports = 2;
8328         }
8329
8330         return ports;
8331 }
8332
8333 static void niu_pci_vpd_validate(struct niu *np)
8334 {
8335         struct net_device *dev = np->dev;
8336         struct niu_vpd *vpd = &np->vpd;
8337         u8 val8;
8338
8339         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8340                 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8341
8342                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8343                 return;
8344         }
8345
8346         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8347             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8348                 np->flags |= NIU_FLAGS_10G;
8349                 np->flags &= ~NIU_FLAGS_FIBER;
8350                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8351                 np->mac_xcvr = MAC_XCVR_PCS;
8352                 if (np->port > 1) {
8353                         np->flags |= NIU_FLAGS_FIBER;
8354                         np->flags &= ~NIU_FLAGS_10G;
8355                 }
8356                 if (np->flags & NIU_FLAGS_10G)
8357                         np->mac_xcvr = MAC_XCVR_XPCS;
8358         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8359                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8360                               NIU_FLAGS_HOTPLUG_PHY);
8361         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8362                 dev_err(np->device, "Illegal phy string [%s]\n",
8363                         np->vpd.phy_type);
8364                 dev_err(np->device, "Falling back to SPROM\n");
8365                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8366                 return;
8367         }
8368
8369         memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN);
8370
8371         val8 = dev->dev_addr[5];
8372         dev->dev_addr[5] += np->port;
8373         if (dev->dev_addr[5] < val8)
8374                 dev->dev_addr[4]++;
8375 }
8376
8377 static int niu_pci_probe_sprom(struct niu *np)
8378 {
8379         struct net_device *dev = np->dev;
8380         int len, i;
8381         u64 val, sum;
8382         u8 val8;
8383
8384         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8385         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8386         len = val / 4;
8387
8388         np->eeprom_len = len;
8389
8390         netif_printk(np, probe, KERN_DEBUG, np->dev,
8391                      "SPROM: Image size %llu\n", (unsigned long long)val);
8392
8393         sum = 0;
8394         for (i = 0; i < len; i++) {
8395                 val = nr64(ESPC_NCR(i));
8396                 sum += (val >>  0) & 0xff;
8397                 sum += (val >>  8) & 0xff;
8398                 sum += (val >> 16) & 0xff;
8399                 sum += (val >> 24) & 0xff;
8400         }
8401         netif_printk(np, probe, KERN_DEBUG, np->dev,
8402                      "SPROM: Checksum %x\n", (int)(sum & 0xff));
8403         if ((sum & 0xff) != 0xab) {
8404                 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8405                 return -EINVAL;
8406         }
8407
8408         val = nr64(ESPC_PHY_TYPE);
8409         switch (np->port) {
8410         case 0:
8411                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8412                         ESPC_PHY_TYPE_PORT0_SHIFT;
8413                 break;
8414         case 1:
8415                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8416                         ESPC_PHY_TYPE_PORT1_SHIFT;
8417                 break;
8418         case 2:
8419                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8420                         ESPC_PHY_TYPE_PORT2_SHIFT;
8421                 break;
8422         case 3:
8423                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8424                         ESPC_PHY_TYPE_PORT3_SHIFT;
8425                 break;
8426         default:
8427                 dev_err(np->device, "Bogus port number %u\n",
8428                         np->port);
8429                 return -EINVAL;
8430         }
8431         netif_printk(np, probe, KERN_DEBUG, np->dev,
8432                      "SPROM: PHY type %x\n", val8);
8433
8434         switch (val8) {
8435         case ESPC_PHY_TYPE_1G_COPPER:
8436                 /* 1G copper, MII */
8437                 np->flags &= ~(NIU_FLAGS_FIBER |
8438                                NIU_FLAGS_10G);
8439                 np->mac_xcvr = MAC_XCVR_MII;
8440                 break;
8441
8442         case ESPC_PHY_TYPE_1G_FIBER:
8443                 /* 1G fiber, PCS */
8444                 np->flags &= ~NIU_FLAGS_10G;
8445                 np->flags |= NIU_FLAGS_FIBER;
8446                 np->mac_xcvr = MAC_XCVR_PCS;
8447                 break;
8448
8449         case ESPC_PHY_TYPE_10G_COPPER:
8450                 /* 10G copper, XPCS */
8451                 np->flags |= NIU_FLAGS_10G;
8452                 np->flags &= ~NIU_FLAGS_FIBER;
8453                 np->mac_xcvr = MAC_XCVR_XPCS;
8454                 break;
8455
8456         case ESPC_PHY_TYPE_10G_FIBER:
8457                 /* 10G fiber, XPCS */
8458                 np->flags |= (NIU_FLAGS_10G |
8459                               NIU_FLAGS_FIBER);
8460                 np->mac_xcvr = MAC_XCVR_XPCS;
8461                 break;
8462
8463         default:
8464                 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8465                 return -EINVAL;
8466         }
8467
8468         val = nr64(ESPC_MAC_ADDR0);
8469         netif_printk(np, probe, KERN_DEBUG, np->dev,
8470                      "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8471         dev->dev_addr[0] = (val >>  0) & 0xff;
8472         dev->dev_addr[1] = (val >>  8) & 0xff;
8473         dev->dev_addr[2] = (val >> 16) & 0xff;
8474         dev->dev_addr[3] = (val >> 24) & 0xff;
8475
8476         val = nr64(ESPC_MAC_ADDR1);
8477         netif_printk(np, probe, KERN_DEBUG, np->dev,
8478                      "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8479         dev->dev_addr[4] = (val >>  0) & 0xff;
8480         dev->dev_addr[5] = (val >>  8) & 0xff;
8481
8482         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8483                 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8484                         dev->dev_addr);
8485                 return -EINVAL;
8486         }
8487
8488         val8 = dev->dev_addr[5];
8489         dev->dev_addr[5] += np->port;
8490         if (dev->dev_addr[5] < val8)
8491                 dev->dev_addr[4]++;
8492
8493         val = nr64(ESPC_MOD_STR_LEN);
8494         netif_printk(np, probe, KERN_DEBUG, np->dev,
8495                      "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8496         if (val >= 8 * 4)
8497                 return -EINVAL;
8498
8499         for (i = 0; i < val; i += 4) {
8500                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8501
8502                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8503                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8504                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8505                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8506         }
8507         np->vpd.model[val] = '\0';
8508
8509         val = nr64(ESPC_BD_MOD_STR_LEN);
8510         netif_printk(np, probe, KERN_DEBUG, np->dev,
8511                      "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8512         if (val >= 4 * 4)
8513                 return -EINVAL;
8514
8515         for (i = 0; i < val; i += 4) {
8516                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8517
8518                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8519                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8520                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8521                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8522         }
8523         np->vpd.board_model[val] = '\0';
8524
8525         np->vpd.mac_num =
8526                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8527         netif_printk(np, probe, KERN_DEBUG, np->dev,
8528                      "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8529
8530         return 0;
8531 }
8532
8533 static int niu_get_and_validate_port(struct niu *np)
8534 {
8535         struct niu_parent *parent = np->parent;
8536
8537         if (np->port <= 1)
8538                 np->flags |= NIU_FLAGS_XMAC;
8539
8540         if (!parent->num_ports) {
8541                 if (parent->plat_type == PLAT_TYPE_NIU) {
8542                         parent->num_ports = 2;
8543                 } else {
8544                         parent->num_ports = niu_pci_vpd_get_nports(np);
8545                         if (!parent->num_ports) {
8546                                 /* Fall back to SPROM as last resort.
8547                                  * This will fail on most cards.
8548                                  */
8549                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8550                                         ESPC_NUM_PORTS_MACS_VAL;
8551
8552                                 /* All of the current probing methods fail on
8553                                  * Maramba on-board parts.
8554                                  */
8555                                 if (!parent->num_ports)
8556                                         parent->num_ports = 4;
8557                         }
8558                 }
8559         }
8560
8561         if (np->port >= parent->num_ports)
8562                 return -ENODEV;
8563
8564         return 0;
8565 }
8566
8567 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p,
8568                       int dev_id_1, int dev_id_2, u8 phy_port, int type)
8569 {
8570         u32 id = (dev_id_1 << 16) | dev_id_2;
8571         u8 idx;
8572
8573         if (dev_id_1 < 0 || dev_id_2 < 0)
8574                 return 0;
8575         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8576                 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8577                  * test covers the 8706 as well.
8578                  */
8579                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8580                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8581                         return 0;
8582         } else {
8583                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8584                         return 0;
8585         }
8586
8587         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8588                 parent->index, id,
8589                 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8590                 type == PHY_TYPE_PCS ? "PCS" : "MII",
8591                 phy_port);
8592
8593         if (p->cur[type] >= NIU_MAX_PORTS) {
8594                 pr_err("Too many PHY ports\n");
8595                 return -EINVAL;
8596         }
8597         idx = p->cur[type];
8598         p->phy_id[type][idx] = id;
8599         p->phy_port[type][idx] = phy_port;
8600         p->cur[type] = idx + 1;
8601         return 0;
8602 }
8603
8604 static int port_has_10g(struct phy_probe_info *p, int port)
8605 {
8606         int i;
8607
8608         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8609                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8610                         return 1;
8611         }
8612         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8613                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8614                         return 1;
8615         }
8616
8617         return 0;
8618 }
8619
8620 static int count_10g_ports(struct phy_probe_info *p, int *lowest)
8621 {
8622         int port, cnt;
8623
8624         cnt = 0;
8625         *lowest = 32;
8626         for (port = 8; port < 32; port++) {
8627                 if (port_has_10g(p, port)) {
8628                         if (!cnt)
8629                                 *lowest = port;
8630                         cnt++;
8631                 }
8632         }
8633
8634         return cnt;
8635 }
8636
8637 static int count_1g_ports(struct phy_probe_info *p, int *lowest)
8638 {
8639         *lowest = 32;
8640         if (p->cur[PHY_TYPE_MII])
8641                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8642
8643         return p->cur[PHY_TYPE_MII];
8644 }
8645
8646 static void niu_n2_divide_channels(struct niu_parent *parent)
8647 {
8648         int num_ports = parent->num_ports;
8649         int i;
8650
8651         for (i = 0; i < num_ports; i++) {
8652                 parent->rxchan_per_port[i] = (16 / num_ports);
8653                 parent->txchan_per_port[i] = (16 / num_ports);
8654
8655                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8656                         parent->index, i,
8657                         parent->rxchan_per_port[i],
8658                         parent->txchan_per_port[i]);
8659         }
8660 }
8661
8662 static void niu_divide_channels(struct niu_parent *parent,
8663                                 int num_10g, int num_1g)
8664 {
8665         int num_ports = parent->num_ports;
8666         int rx_chans_per_10g, rx_chans_per_1g;
8667         int tx_chans_per_10g, tx_chans_per_1g;
8668         int i, tot_rx, tot_tx;
8669
8670         if (!num_10g || !num_1g) {
8671                 rx_chans_per_10g = rx_chans_per_1g =
8672                         (NIU_NUM_RXCHAN / num_ports);
8673                 tx_chans_per_10g = tx_chans_per_1g =
8674                         (NIU_NUM_TXCHAN / num_ports);
8675         } else {
8676                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8677                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8678                                     (rx_chans_per_1g * num_1g)) /
8679                         num_10g;
8680
8681                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8682                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8683                                     (tx_chans_per_1g * num_1g)) /
8684                         num_10g;
8685         }
8686
8687         tot_rx = tot_tx = 0;
8688         for (i = 0; i < num_ports; i++) {
8689                 int type = phy_decode(parent->port_phy, i);
8690
8691                 if (type == PORT_TYPE_10G) {
8692                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8693                         parent->txchan_per_port[i] = tx_chans_per_10g;
8694                 } else {
8695                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8696                         parent->txchan_per_port[i] = tx_chans_per_1g;
8697                 }
8698                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8699                         parent->index, i,
8700                         parent->rxchan_per_port[i],
8701                         parent->txchan_per_port[i]);
8702                 tot_rx += parent->rxchan_per_port[i];
8703                 tot_tx += parent->txchan_per_port[i];
8704         }
8705
8706         if (tot_rx > NIU_NUM_RXCHAN) {
8707                 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8708                        parent->index, tot_rx);
8709                 for (i = 0; i < num_ports; i++)
8710                         parent->rxchan_per_port[i] = 1;
8711         }
8712         if (tot_tx > NIU_NUM_TXCHAN) {
8713                 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8714                        parent->index, tot_tx);
8715                 for (i = 0; i < num_ports; i++)
8716                         parent->txchan_per_port[i] = 1;
8717         }
8718         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8719                 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8720                         parent->index, tot_rx, tot_tx);
8721         }
8722 }
8723
8724 static void niu_divide_rdc_groups(struct niu_parent *parent,
8725                                   int num_10g, int num_1g)
8726 {
8727         int i, num_ports = parent->num_ports;
8728         int rdc_group, rdc_groups_per_port;
8729         int rdc_channel_base;
8730
8731         rdc_group = 0;
8732         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8733
8734         rdc_channel_base = 0;
8735
8736         for (i = 0; i < num_ports; i++) {
8737                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8738                 int grp, num_channels = parent->rxchan_per_port[i];
8739                 int this_channel_offset;
8740
8741                 tp->first_table_num = rdc_group;
8742                 tp->num_tables = rdc_groups_per_port;
8743                 this_channel_offset = 0;
8744                 for (grp = 0; grp < tp->num_tables; grp++) {
8745                         struct rdc_table *rt = &tp->tables[grp];
8746                         int slot;
8747
8748                         pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8749                                 parent->index, i, tp->first_table_num + grp);
8750                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8751                                 rt->rxdma_channel[slot] =
8752                                         rdc_channel_base + this_channel_offset;
8753
8754                                 pr_cont("%d ", rt->rxdma_channel[slot]);
8755
8756                                 if (++this_channel_offset == num_channels)
8757                                         this_channel_offset = 0;
8758                         }
8759                         pr_cont("]\n");
8760                 }
8761
8762                 parent->rdc_default[i] = rdc_channel_base;
8763
8764                 rdc_channel_base += num_channels;
8765                 rdc_group += rdc_groups_per_port;
8766         }
8767 }
8768
8769 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent,
8770                                struct phy_probe_info *info)
8771 {
8772         unsigned long flags;
8773         int port, err;
8774
8775         memset(info, 0, sizeof(*info));
8776
8777         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8778         niu_lock_parent(np, flags);
8779         err = 0;
8780         for (port = 8; port < 32; port++) {
8781                 int dev_id_1, dev_id_2;
8782
8783                 dev_id_1 = mdio_read(np, port,
8784                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8785                 dev_id_2 = mdio_read(np, port,
8786                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8787                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8788                                  PHY_TYPE_PMA_PMD);
8789                 if (err)
8790                         break;
8791                 dev_id_1 = mdio_read(np, port,
8792                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8793                 dev_id_2 = mdio_read(np, port,
8794                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8795                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8796                                  PHY_TYPE_PCS);
8797                 if (err)
8798                         break;
8799                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8800                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8801                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8802                                  PHY_TYPE_MII);
8803                 if (err)
8804                         break;
8805         }
8806         niu_unlock_parent(np, flags);
8807
8808         return err;
8809 }
8810
8811 static int walk_phys(struct niu *np, struct niu_parent *parent)
8812 {
8813         struct phy_probe_info *info = &parent->phy_probe_info;
8814         int lowest_10g, lowest_1g;
8815         int num_10g, num_1g;
8816         u32 val;
8817         int err;
8818
8819         num_10g = num_1g = 0;
8820
8821         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8822             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8823                 num_10g = 0;
8824                 num_1g = 2;
8825                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8826                 parent->num_ports = 4;
8827                 val = (phy_encode(PORT_TYPE_1G, 0) |
8828                        phy_encode(PORT_TYPE_1G, 1) |
8829                        phy_encode(PORT_TYPE_1G, 2) |
8830                        phy_encode(PORT_TYPE_1G, 3));
8831         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8832                 num_10g = 2;
8833                 num_1g = 0;
8834                 parent->num_ports = 2;
8835                 val = (phy_encode(PORT_TYPE_10G, 0) |
8836                        phy_encode(PORT_TYPE_10G, 1));
8837         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8838                    (parent->plat_type == PLAT_TYPE_NIU)) {
8839                 /* this is the Monza case */
8840                 if (np->flags & NIU_FLAGS_10G) {
8841                         val = (phy_encode(PORT_TYPE_10G, 0) |
8842                                phy_encode(PORT_TYPE_10G, 1));
8843                 } else {
8844                         val = (phy_encode(PORT_TYPE_1G, 0) |
8845                                phy_encode(PORT_TYPE_1G, 1));
8846                 }
8847         } else {
8848                 err = fill_phy_probe_info(np, parent, info);
8849                 if (err)
8850                         return err;
8851
8852                 num_10g = count_10g_ports(info, &lowest_10g);
8853                 num_1g = count_1g_ports(info, &lowest_1g);
8854
8855                 switch ((num_10g << 4) | num_1g) {
8856                 case 0x24:
8857                         if (lowest_1g == 10)
8858                                 parent->plat_type = PLAT_TYPE_VF_P0;
8859                         else if (lowest_1g == 26)
8860                                 parent->plat_type = PLAT_TYPE_VF_P1;
8861                         else
8862                                 goto unknown_vg_1g_port;
8863
8864                         /* fallthru */
8865                 case 0x22:
8866                         val = (phy_encode(PORT_TYPE_10G, 0) |
8867                                phy_encode(PORT_TYPE_10G, 1) |
8868                                phy_encode(PORT_TYPE_1G, 2) |
8869                                phy_encode(PORT_TYPE_1G, 3));
8870                         break;
8871
8872                 case 0x20:
8873                         val = (phy_encode(PORT_TYPE_10G, 0) |
8874                                phy_encode(PORT_TYPE_10G, 1));
8875                         break;
8876
8877                 case 0x10:
8878                         val = phy_encode(PORT_TYPE_10G, np->port);
8879                         break;
8880
8881                 case 0x14:
8882                         if (lowest_1g == 10)
8883                                 parent->plat_type = PLAT_TYPE_VF_P0;
8884                         else if (lowest_1g == 26)
8885                                 parent->plat_type = PLAT_TYPE_VF_P1;
8886                         else
8887                                 goto unknown_vg_1g_port;
8888
8889                         /* fallthru */
8890                 case 0x13:
8891                         if ((lowest_10g & 0x7) == 0)
8892                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8893                                        phy_encode(PORT_TYPE_1G, 1) |
8894                                        phy_encode(PORT_TYPE_1G, 2) |
8895                                        phy_encode(PORT_TYPE_1G, 3));
8896                         else
8897                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8898                                        phy_encode(PORT_TYPE_10G, 1) |
8899                                        phy_encode(PORT_TYPE_1G, 2) |
8900                                        phy_encode(PORT_TYPE_1G, 3));
8901                         break;
8902
8903                 case 0x04:
8904                         if (lowest_1g == 10)
8905                                 parent->plat_type = PLAT_TYPE_VF_P0;
8906                         else if (lowest_1g == 26)
8907                                 parent->plat_type = PLAT_TYPE_VF_P1;
8908                         else
8909                                 goto unknown_vg_1g_port;
8910
8911                         val = (phy_encode(PORT_TYPE_1G, 0) |
8912                                phy_encode(PORT_TYPE_1G, 1) |
8913                                phy_encode(PORT_TYPE_1G, 2) |
8914                                phy_encode(PORT_TYPE_1G, 3));
8915                         break;
8916
8917                 default:
8918                         pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8919                                num_10g, num_1g);
8920                         return -EINVAL;
8921                 }
8922         }
8923
8924         parent->port_phy = val;
8925
8926         if (parent->plat_type == PLAT_TYPE_NIU)
8927                 niu_n2_divide_channels(parent);
8928         else
8929                 niu_divide_channels(parent, num_10g, num_1g);
8930
8931         niu_divide_rdc_groups(parent, num_10g, num_1g);
8932
8933         return 0;
8934
8935 unknown_vg_1g_port:
8936         pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8937         return -EINVAL;
8938 }
8939
8940 static int niu_probe_ports(struct niu *np)
8941 {
8942         struct niu_parent *parent = np->parent;
8943         int err, i;
8944
8945         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8946                 err = walk_phys(np, parent);
8947                 if (err)
8948                         return err;
8949
8950                 niu_set_ldg_timer_res(np, 2);
8951                 for (i = 0; i <= LDN_MAX; i++)
8952                         niu_ldn_irq_enable(np, i, 0);
8953         }
8954
8955         if (parent->port_phy == PORT_PHY_INVALID)
8956                 return -EINVAL;
8957
8958         return 0;
8959 }
8960
8961 static int niu_classifier_swstate_init(struct niu *np)
8962 {
8963         struct niu_classifier *cp = &np->clas;
8964
8965         cp->tcam_top = (u16) np->port;
8966         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8967         cp->h1_init = 0xffffffff;
8968         cp->h2_init = 0xffff;
8969
8970         return fflp_early_init(np);
8971 }
8972
8973 static void niu_link_config_init(struct niu *np)
8974 {
8975         struct niu_link_config *lp = &np->link_config;
8976
8977         lp->advertising = (ADVERTISED_10baseT_Half |
8978                            ADVERTISED_10baseT_Full |
8979                            ADVERTISED_100baseT_Half |
8980                            ADVERTISED_100baseT_Full |
8981                            ADVERTISED_1000baseT_Half |
8982                            ADVERTISED_1000baseT_Full |
8983                            ADVERTISED_10000baseT_Full |
8984                            ADVERTISED_Autoneg);
8985         lp->speed = lp->active_speed = SPEED_INVALID;
8986         lp->duplex = DUPLEX_FULL;
8987         lp->active_duplex = DUPLEX_INVALID;
8988         lp->autoneg = 1;
8989 #if 0
8990         lp->loopback_mode = LOOPBACK_MAC;
8991         lp->active_speed = SPEED_10000;
8992         lp->active_duplex = DUPLEX_FULL;
8993 #else
8994         lp->loopback_mode = LOOPBACK_DISABLED;
8995 #endif
8996 }
8997
8998 static int niu_init_mac_ipp_pcs_base(struct niu *np)
8999 {
9000         switch (np->port) {
9001         case 0:
9002                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9003                 np->ipp_off  = 0x00000;
9004                 np->pcs_off  = 0x04000;
9005                 np->xpcs_off = 0x02000;
9006                 break;
9007
9008         case 1:
9009                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9010                 np->ipp_off  = 0x08000;
9011                 np->pcs_off  = 0x0a000;
9012                 np->xpcs_off = 0x08000;
9013                 break;
9014
9015         case 2:
9016                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9017                 np->ipp_off  = 0x04000;
9018                 np->pcs_off  = 0x0e000;
9019                 np->xpcs_off = ~0UL;
9020                 break;
9021
9022         case 3:
9023                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9024                 np->ipp_off  = 0x0c000;
9025                 np->pcs_off  = 0x12000;
9026                 np->xpcs_off = ~0UL;
9027                 break;
9028
9029         default:
9030                 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9031                 return -EINVAL;
9032         }
9033
9034         return 0;
9035 }
9036
9037 static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
9038 {
9039         struct msix_entry msi_vec[NIU_NUM_LDG];
9040         struct niu_parent *parent = np->parent;
9041         struct pci_dev *pdev = np->pdev;
9042         int i, num_irqs;
9043         u8 first_ldg;
9044
9045         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9046         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9047                 ldg_num_map[i] = first_ldg + i;
9048
9049         num_irqs = (parent->rxchan_per_port[np->port] +
9050                     parent->txchan_per_port[np->port] +
9051                     (np->port == 0 ? 3 : 1));
9052         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9053
9054         for (i = 0; i < num_irqs; i++) {
9055                 msi_vec[i].vector = 0;
9056                 msi_vec[i].entry = i;
9057         }
9058
9059         num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
9060         if (num_irqs < 0) {
9061                 np->flags &= ~NIU_FLAGS_MSIX;
9062                 return;
9063         }
9064
9065         np->flags |= NIU_FLAGS_MSIX;
9066         for (i = 0; i < num_irqs; i++)
9067                 np->ldg[i].irq = msi_vec[i].vector;
9068         np->num_ldg = num_irqs;
9069 }
9070
9071 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9072 {
9073 #ifdef CONFIG_SPARC64
9074         struct platform_device *op = np->op;
9075         const u32 *int_prop;
9076         int i;
9077
9078         int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9079         if (!int_prop)
9080                 return -ENODEV;
9081
9082         for (i = 0; i < op->archdata.num_irqs; i++) {
9083                 ldg_num_map[i] = int_prop[i];
9084                 np->ldg[i].irq = op->archdata.irqs[i];
9085         }
9086
9087         np->num_ldg = op->archdata.num_irqs;
9088
9089         return 0;
9090 #else
9091         return -EINVAL;
9092 #endif
9093 }
9094
9095 static int niu_ldg_init(struct niu *np)
9096 {
9097         struct niu_parent *parent = np->parent;
9098         u8 ldg_num_map[NIU_NUM_LDG];
9099         int first_chan, num_chan;
9100         int i, err, ldg_rotor;
9101         u8 port;
9102
9103         np->num_ldg = 1;
9104         np->ldg[0].irq = np->dev->irq;
9105         if (parent->plat_type == PLAT_TYPE_NIU) {
9106                 err = niu_n2_irq_init(np, ldg_num_map);
9107                 if (err)
9108                         return err;
9109         } else
9110                 niu_try_msix(np, ldg_num_map);
9111
9112         port = np->port;
9113         for (i = 0; i < np->num_ldg; i++) {
9114                 struct niu_ldg *lp = &np->ldg[i];
9115
9116                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9117
9118                 lp->np = np;
9119                 lp->ldg_num = ldg_num_map[i];
9120                 lp->timer = 2; /* XXX */
9121
9122                 /* On N2 NIU the firmware has setup the SID mappings so they go
9123                  * to the correct values that will route the LDG to the proper
9124                  * interrupt in the NCU interrupt table.
9125                  */
9126                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9127                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9128                         if (err)
9129                                 return err;
9130                 }
9131         }
9132
9133         /* We adopt the LDG assignment ordering used by the N2 NIU
9134          * 'interrupt' properties because that simplifies a lot of
9135          * things.  This ordering is:
9136          *
9137          *      MAC
9138          *      MIF     (if port zero)
9139          *      SYSERR  (if port zero)
9140          *      RX channels
9141          *      TX channels
9142          */
9143
9144         ldg_rotor = 0;
9145
9146         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9147                                   LDN_MAC(port));
9148         if (err)
9149                 return err;
9150
9151         ldg_rotor++;
9152         if (ldg_rotor == np->num_ldg)
9153                 ldg_rotor = 0;
9154
9155         if (port == 0) {
9156                 err = niu_ldg_assign_ldn(np, parent,
9157                                          ldg_num_map[ldg_rotor],
9158                                          LDN_MIF);
9159                 if (err)
9160                         return err;
9161
9162                 ldg_rotor++;
9163                 if (ldg_rotor == np->num_ldg)
9164                         ldg_rotor = 0;
9165
9166                 err = niu_ldg_assign_ldn(np, parent,
9167                                          ldg_num_map[ldg_rotor],
9168                                          LDN_DEVICE_ERROR);
9169                 if (err)
9170                         return err;
9171
9172                 ldg_rotor++;
9173                 if (ldg_rotor == np->num_ldg)
9174                         ldg_rotor = 0;
9175
9176         }
9177
9178         first_chan = 0;
9179         for (i = 0; i < port; i++)
9180                 first_chan += parent->rxchan_per_port[i];
9181         num_chan = parent->rxchan_per_port[port];
9182
9183         for (i = first_chan; i < (first_chan + num_chan); i++) {
9184                 err = niu_ldg_assign_ldn(np, parent,
9185                                          ldg_num_map[ldg_rotor],
9186                                          LDN_RXDMA(i));
9187                 if (err)
9188                         return err;
9189                 ldg_rotor++;
9190                 if (ldg_rotor == np->num_ldg)
9191                         ldg_rotor = 0;
9192         }
9193
9194         first_chan = 0;
9195         for (i = 0; i < port; i++)
9196                 first_chan += parent->txchan_per_port[i];
9197         num_chan = parent->txchan_per_port[port];
9198         for (i = first_chan; i < (first_chan + num_chan); i++) {
9199                 err = niu_ldg_assign_ldn(np, parent,
9200                                          ldg_num_map[ldg_rotor],
9201                                          LDN_TXDMA(i));
9202                 if (err)
9203                         return err;
9204                 ldg_rotor++;
9205                 if (ldg_rotor == np->num_ldg)
9206                         ldg_rotor = 0;
9207         }
9208
9209         return 0;
9210 }
9211
9212 static void niu_ldg_free(struct niu *np)
9213 {
9214         if (np->flags & NIU_FLAGS_MSIX)
9215                 pci_disable_msix(np->pdev);
9216 }
9217
9218 static int niu_get_of_props(struct niu *np)
9219 {
9220 #ifdef CONFIG_SPARC64
9221         struct net_device *dev = np->dev;
9222         struct device_node *dp;
9223         const char *phy_type;
9224         const u8 *mac_addr;
9225         const char *model;
9226         int prop_len;
9227
9228         if (np->parent->plat_type == PLAT_TYPE_NIU)
9229                 dp = np->op->dev.of_node;
9230         else
9231                 dp = pci_device_to_OF_node(np->pdev);
9232
9233         phy_type = of_get_property(dp, "phy-type", &prop_len);
9234         if (!phy_type) {
9235                 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9236                            dp->full_name);
9237                 return -EINVAL;
9238         }
9239
9240         if (!strcmp(phy_type, "none"))
9241                 return -ENODEV;
9242
9243         strcpy(np->vpd.phy_type, phy_type);
9244
9245         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9246                 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9247                            dp->full_name, np->vpd.phy_type);
9248                 return -EINVAL;
9249         }
9250
9251         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9252         if (!mac_addr) {
9253                 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9254                            dp->full_name);
9255                 return -EINVAL;
9256         }
9257         if (prop_len != dev->addr_len) {
9258                 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9259                            dp->full_name, prop_len);
9260         }
9261         memcpy(dev->dev_addr, mac_addr, dev->addr_len);
9262         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9263                 netdev_err(dev, "%s: OF MAC address is invalid\n",
9264                            dp->full_name);
9265                 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->dev_addr);
9266                 return -EINVAL;
9267         }
9268
9269         model = of_get_property(dp, "model", &prop_len);
9270
9271         if (model)
9272                 strcpy(np->vpd.model, model);
9273
9274         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9275                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9276                         NIU_FLAGS_HOTPLUG_PHY);
9277         }
9278
9279         return 0;
9280 #else
9281         return -EINVAL;
9282 #endif
9283 }
9284
9285 static int niu_get_invariants(struct niu *np)
9286 {
9287         int err, have_props;
9288         u32 offset;
9289
9290         err = niu_get_of_props(np);
9291         if (err == -ENODEV)
9292                 return err;
9293
9294         have_props = !err;
9295
9296         err = niu_init_mac_ipp_pcs_base(np);
9297         if (err)
9298                 return err;
9299
9300         if (have_props) {
9301                 err = niu_get_and_validate_port(np);
9302                 if (err)
9303                         return err;
9304
9305         } else  {
9306                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9307                         return -EINVAL;
9308
9309                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9310                 offset = niu_pci_vpd_offset(np);
9311                 netif_printk(np, probe, KERN_DEBUG, np->dev,
9312                              "%s() VPD offset [%08x]\n", __func__, offset);
9313                 if (offset) {
9314                         err = niu_pci_vpd_fetch(np, offset);
9315                         if (err < 0)
9316                                 return err;
9317                 }
9318                 nw64(ESPC_PIO_EN, 0);
9319
9320                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9321                         niu_pci_vpd_validate(np);
9322                         err = niu_get_and_validate_port(np);
9323                         if (err)
9324                                 return err;
9325                 }
9326
9327                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9328                         err = niu_get_and_validate_port(np);
9329                         if (err)
9330                                 return err;
9331                         err = niu_pci_probe_sprom(np);
9332                         if (err)
9333                                 return err;
9334                 }
9335         }
9336
9337         err = niu_probe_ports(np);
9338         if (err)
9339                 return err;
9340
9341         niu_ldg_init(np);
9342
9343         niu_classifier_swstate_init(np);
9344         niu_link_config_init(np);
9345
9346         err = niu_determine_phy_disposition(np);
9347         if (!err)
9348                 err = niu_init_link(np);
9349
9350         return err;
9351 }
9352
9353 static LIST_HEAD(niu_parent_list);
9354 static DEFINE_MUTEX(niu_parent_lock);
9355 static int niu_parent_index;
9356
9357 static ssize_t show_port_phy(struct device *dev,
9358                              struct device_attribute *attr, char *buf)
9359 {
9360         struct platform_device *plat_dev = to_platform_device(dev);
9361         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9362         u32 port_phy = p->port_phy;
9363         char *orig_buf = buf;
9364         int i;
9365
9366         if (port_phy == PORT_PHY_UNKNOWN ||
9367             port_phy == PORT_PHY_INVALID)
9368                 return 0;
9369
9370         for (i = 0; i < p->num_ports; i++) {
9371                 const char *type_str;
9372                 int type;
9373
9374                 type = phy_decode(port_phy, i);
9375                 if (type == PORT_TYPE_10G)
9376                         type_str = "10G";
9377                 else
9378                         type_str = "1G";
9379                 buf += sprintf(buf,
9380                                (i == 0) ? "%s" : " %s",
9381                                type_str);
9382         }
9383         buf += sprintf(buf, "\n");
9384         return buf - orig_buf;
9385 }
9386
9387 static ssize_t show_plat_type(struct device *dev,
9388                               struct device_attribute *attr, char *buf)
9389 {
9390         struct platform_device *plat_dev = to_platform_device(dev);
9391         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9392         const char *type_str;
9393
9394         switch (p->plat_type) {
9395         case PLAT_TYPE_ATLAS:
9396                 type_str = "atlas";
9397                 break;
9398         case PLAT_TYPE_NIU:
9399                 type_str = "niu";
9400                 break;
9401         case PLAT_TYPE_VF_P0:
9402                 type_str = "vf_p0";
9403                 break;
9404         case PLAT_TYPE_VF_P1:
9405                 type_str = "vf_p1";
9406                 break;
9407         default:
9408                 type_str = "unknown";
9409                 break;
9410         }
9411
9412         return sprintf(buf, "%s\n", type_str);
9413 }
9414
9415 static ssize_t __show_chan_per_port(struct device *dev,
9416                                     struct device_attribute *attr, char *buf,
9417                                     int rx)
9418 {
9419         struct platform_device *plat_dev = to_platform_device(dev);
9420         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9421         char *orig_buf = buf;
9422         u8 *arr;
9423         int i;
9424
9425         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9426
9427         for (i = 0; i < p->num_ports; i++) {
9428                 buf += sprintf(buf,
9429                                (i == 0) ? "%d" : " %d",
9430                                arr[i]);
9431         }
9432         buf += sprintf(buf, "\n");
9433
9434         return buf - orig_buf;
9435 }
9436
9437 static ssize_t show_rxchan_per_port(struct device *dev,
9438                                     struct device_attribute *attr, char *buf)
9439 {
9440         return __show_chan_per_port(dev, attr, buf, 1);
9441 }
9442
9443 static ssize_t show_txchan_per_port(struct device *dev,
9444                                     struct device_attribute *attr, char *buf)
9445 {
9446         return __show_chan_per_port(dev, attr, buf, 1);
9447 }
9448
9449 static ssize_t show_num_ports(struct device *dev,
9450                               struct device_attribute *attr, char *buf)
9451 {
9452         struct platform_device *plat_dev = to_platform_device(dev);
9453         struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9454
9455         return sprintf(buf, "%d\n", p->num_ports);
9456 }
9457
9458 static struct device_attribute niu_parent_attributes[] = {
9459         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9460         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9461         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9462         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9463         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9464         {}
9465 };
9466
9467 static struct niu_parent *niu_new_parent(struct niu *np,
9468                                          union niu_parent_id *id, u8 ptype)
9469 {
9470         struct platform_device *plat_dev;
9471         struct niu_parent *p;
9472         int i;
9473
9474         plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9475                                                    NULL, 0);
9476         if (IS_ERR(plat_dev))
9477                 return NULL;
9478
9479         for (i = 0; niu_parent_attributes[i].attr.name; i++) {
9480                 int err = device_create_file(&plat_dev->dev,
9481                                              &niu_parent_attributes[i]);
9482                 if (err)
9483                         goto fail_unregister;
9484         }
9485
9486         p = kzalloc(sizeof(*p), GFP_KERNEL);
9487         if (!p)
9488                 goto fail_unregister;
9489
9490         p->index = niu_parent_index++;
9491
9492         plat_dev->dev.platform_data = p;
9493         p->plat_dev = plat_dev;
9494
9495         memcpy(&p->id, id, sizeof(*id));
9496         p->plat_type = ptype;
9497         INIT_LIST_HEAD(&p->list);
9498         atomic_set(&p->refcnt, 0);
9499         list_add(&p->list, &niu_parent_list);
9500         spin_lock_init(&p->lock);
9501
9502         p->rxdma_clock_divider = 7500;
9503
9504         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9505         if (p->plat_type == PLAT_TYPE_NIU)
9506                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9507
9508         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9509                 int index = i - CLASS_CODE_USER_PROG1;
9510
9511                 p->tcam_key[index] = TCAM_KEY_TSEL;
9512                 p->flow_key[index] = (FLOW_KEY_IPSA |
9513                                       FLOW_KEY_IPDA |
9514                                       FLOW_KEY_PROTO |
9515                                       (FLOW_KEY_L4_BYTE12 <<
9516                                        FLOW_KEY_L4_0_SHIFT) |
9517                                       (FLOW_KEY_L4_BYTE12 <<
9518                                        FLOW_KEY_L4_1_SHIFT));
9519         }
9520
9521         for (i = 0; i < LDN_MAX + 1; i++)
9522                 p->ldg_map[i] = LDG_INVALID;
9523
9524         return p;
9525
9526 fail_unregister:
9527         platform_device_unregister(plat_dev);
9528         return NULL;
9529 }
9530
9531 static struct niu_parent *niu_get_parent(struct niu *np,
9532                                          union niu_parent_id *id, u8 ptype)
9533 {
9534         struct niu_parent *p, *tmp;
9535         int port = np->port;
9536
9537         mutex_lock(&niu_parent_lock);
9538         p = NULL;
9539         list_for_each_entry(tmp, &niu_parent_list, list) {
9540                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9541                         p = tmp;
9542                         break;
9543                 }
9544         }
9545         if (!p)
9546                 p = niu_new_parent(np, id, ptype);
9547
9548         if (p) {
9549                 char port_name[6];
9550                 int err;
9551
9552                 sprintf(port_name, "port%d", port);
9553                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9554                                         &np->device->kobj,
9555                                         port_name);
9556                 if (!err) {
9557                         p->ports[port] = np;
9558                         atomic_inc(&p->refcnt);
9559                 }
9560         }
9561         mutex_unlock(&niu_parent_lock);
9562
9563         return p;
9564 }
9565
9566 static void niu_put_parent(struct niu *np)
9567 {
9568         struct niu_parent *p = np->parent;
9569         u8 port = np->port;
9570         char port_name[6];
9571
9572         BUG_ON(!p || p->ports[port] != np);
9573
9574         netif_printk(np, probe, KERN_DEBUG, np->dev,
9575                      "%s() port[%u]\n", __func__, port);
9576
9577         sprintf(port_name, "port%d", port);
9578
9579         mutex_lock(&niu_parent_lock);
9580
9581         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9582
9583         p->ports[port] = NULL;
9584         np->parent = NULL;
9585
9586         if (atomic_dec_and_test(&p->refcnt)) {
9587                 list_del(&p->list);
9588                 platform_device_unregister(p->plat_dev);
9589         }
9590
9591         mutex_unlock(&niu_parent_lock);
9592 }
9593
9594 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9595                                     u64 *handle, gfp_t flag)
9596 {
9597         dma_addr_t dh;
9598         void *ret;
9599
9600         ret = dma_alloc_coherent(dev, size, &dh, flag);
9601         if (ret)
9602                 *handle = dh;
9603         return ret;
9604 }
9605
9606 static void niu_pci_free_coherent(struct device *dev, size_t size,
9607                                   void *cpu_addr, u64 handle)
9608 {
9609         dma_free_coherent(dev, size, cpu_addr, handle);
9610 }
9611
9612 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9613                             unsigned long offset, size_t size,
9614                             enum dma_data_direction direction)
9615 {
9616         return dma_map_page(dev, page, offset, size, direction);
9617 }
9618
9619 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9620                                size_t size, enum dma_data_direction direction)
9621 {
9622         dma_unmap_page(dev, dma_address, size, direction);
9623 }
9624
9625 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9626                               size_t size,
9627                               enum dma_data_direction direction)
9628 {
9629         return dma_map_single(dev, cpu_addr, size, direction);
9630 }
9631
9632 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9633                                  size_t size,
9634                                  enum dma_data_direction direction)
9635 {
9636         dma_unmap_single(dev, dma_address, size, direction);
9637 }
9638
9639 static const struct niu_ops niu_pci_ops = {
9640         .alloc_coherent = niu_pci_alloc_coherent,
9641         .free_coherent  = niu_pci_free_coherent,
9642         .map_page       = niu_pci_map_page,
9643         .unmap_page     = niu_pci_unmap_page,
9644         .map_single     = niu_pci_map_single,
9645         .unmap_single   = niu_pci_unmap_single,
9646 };
9647
9648 static void niu_driver_version(void)
9649 {
9650         static int niu_version_printed;
9651
9652         if (niu_version_printed++ == 0)
9653                 pr_info("%s", version);
9654 }
9655
9656 static struct net_device *niu_alloc_and_init(struct device *gen_dev,
9657                                              struct pci_dev *pdev,
9658                                              struct platform_device *op,
9659                                              const struct niu_ops *ops, u8 port)
9660 {
9661         struct net_device *dev;
9662         struct niu *np;
9663
9664         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9665         if (!dev)
9666                 return NULL;
9667
9668         SET_NETDEV_DEV(dev, gen_dev);
9669
9670         np = netdev_priv(dev);
9671         np->dev = dev;
9672         np->pdev = pdev;
9673         np->op = op;
9674         np->device = gen_dev;
9675         np->ops = ops;
9676
9677         np->msg_enable = niu_debug;
9678
9679         spin_lock_init(&np->lock);
9680         INIT_WORK(&np->reset_task, niu_reset_task);
9681
9682         np->port = port;
9683
9684         return dev;
9685 }
9686
9687 static const struct net_device_ops niu_netdev_ops = {
9688         .ndo_open               = niu_open,
9689         .ndo_stop               = niu_close,
9690         .ndo_start_xmit         = niu_start_xmit,
9691         .ndo_get_stats64        = niu_get_stats,
9692         .ndo_set_rx_mode        = niu_set_rx_mode,
9693         .ndo_validate_addr      = eth_validate_addr,
9694         .ndo_set_mac_address    = niu_set_mac_addr,
9695         .ndo_do_ioctl           = niu_ioctl,
9696         .ndo_tx_timeout         = niu_tx_timeout,
9697         .ndo_change_mtu         = niu_change_mtu,
9698 };
9699
9700 static void niu_assign_netdev_ops(struct net_device *dev)
9701 {
9702         dev->netdev_ops = &niu_netdev_ops;
9703         dev->ethtool_ops = &niu_ethtool_ops;
9704         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9705 }
9706
9707 static void niu_device_announce(struct niu *np)
9708 {
9709         struct net_device *dev = np->dev;
9710
9711         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9712
9713         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9714                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9715                                 dev->name,
9716                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9717                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9718                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9719                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9720                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9721                                 np->vpd.phy_type);
9722         } else {
9723                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9724                                 dev->name,
9725                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9726                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9727                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9728                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9729                                   "COPPER")),
9730                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9731                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9732                                 np->vpd.phy_type);
9733         }
9734 }
9735
9736 static void niu_set_basic_features(struct net_device *dev)
9737 {
9738         dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9739         dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9740 }
9741
9742 static int niu_pci_init_one(struct pci_dev *pdev,
9743                             const struct pci_device_id *ent)
9744 {
9745         union niu_parent_id parent_id;
9746         struct net_device *dev;
9747         struct niu *np;
9748         int err;
9749         u64 dma_mask;
9750
9751         niu_driver_version();
9752
9753         err = pci_enable_device(pdev);
9754         if (err) {
9755                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9756                 return err;
9757         }
9758
9759         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9760             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9761                 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9762                 err = -ENODEV;
9763                 goto err_out_disable_pdev;
9764         }
9765
9766         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9767         if (err) {
9768                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9769                 goto err_out_disable_pdev;
9770         }
9771
9772         if (!pci_is_pcie(pdev)) {
9773                 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9774                 err = -ENODEV;
9775                 goto err_out_free_res;
9776         }
9777
9778         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9779                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9780         if (!dev) {
9781                 err = -ENOMEM;
9782                 goto err_out_free_res;
9783         }
9784         np = netdev_priv(dev);
9785
9786         memset(&parent_id, 0, sizeof(parent_id));
9787         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9788         parent_id.pci.bus = pdev->bus->number;
9789         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9790
9791         np->parent = niu_get_parent(np, &parent_id,
9792                                     PLAT_TYPE_ATLAS);
9793         if (!np->parent) {
9794                 err = -ENOMEM;
9795                 goto err_out_free_dev;
9796         }
9797
9798         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
9799                 PCI_EXP_DEVCTL_NOSNOOP_EN,
9800                 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
9801                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
9802                 PCI_EXP_DEVCTL_RELAX_EN);
9803
9804         dma_mask = DMA_BIT_MASK(44);
9805         err = pci_set_dma_mask(pdev, dma_mask);
9806         if (!err) {
9807                 dev->features |= NETIF_F_HIGHDMA;
9808                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9809                 if (err) {
9810                         dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9811                         goto err_out_release_parent;
9812                 }
9813         }
9814         if (err) {
9815                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9816                 if (err) {
9817                         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9818                         goto err_out_release_parent;
9819                 }
9820         }
9821
9822         niu_set_basic_features(dev);
9823
9824         dev->priv_flags |= IFF_UNICAST_FLT;
9825
9826         np->regs = pci_ioremap_bar(pdev, 0);
9827         if (!np->regs) {
9828                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9829                 err = -ENOMEM;
9830                 goto err_out_release_parent;
9831         }
9832
9833         pci_set_master(pdev);
9834         pci_save_state(pdev);
9835
9836         dev->irq = pdev->irq;
9837
9838         niu_assign_netdev_ops(dev);
9839
9840         err = niu_get_invariants(np);
9841         if (err) {
9842                 if (err != -ENODEV)
9843                         dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9844                 goto err_out_iounmap;
9845         }
9846
9847         err = register_netdev(dev);
9848         if (err) {
9849                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9850                 goto err_out_iounmap;
9851         }
9852
9853         pci_set_drvdata(pdev, dev);
9854
9855         niu_device_announce(np);
9856
9857         return 0;
9858
9859 err_out_iounmap:
9860         if (np->regs) {
9861                 iounmap(np->regs);
9862                 np->regs = NULL;
9863         }
9864
9865 err_out_release_parent:
9866         niu_put_parent(np);
9867
9868 err_out_free_dev:
9869         free_netdev(dev);
9870
9871 err_out_free_res:
9872         pci_release_regions(pdev);
9873
9874 err_out_disable_pdev:
9875         pci_disable_device(pdev);
9876
9877         return err;
9878 }
9879
9880 static void niu_pci_remove_one(struct pci_dev *pdev)
9881 {
9882         struct net_device *dev = pci_get_drvdata(pdev);
9883
9884         if (dev) {
9885                 struct niu *np = netdev_priv(dev);
9886
9887                 unregister_netdev(dev);
9888                 if (np->regs) {
9889                         iounmap(np->regs);
9890                         np->regs = NULL;
9891                 }
9892
9893                 niu_ldg_free(np);
9894
9895                 niu_put_parent(np);
9896
9897                 free_netdev(dev);
9898                 pci_release_regions(pdev);
9899                 pci_disable_device(pdev);
9900         }
9901 }
9902
9903 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9904 {
9905         struct net_device *dev = pci_get_drvdata(pdev);
9906         struct niu *np = netdev_priv(dev);
9907         unsigned long flags;
9908
9909         if (!netif_running(dev))
9910                 return 0;
9911
9912         flush_work(&np->reset_task);
9913         niu_netif_stop(np);
9914
9915         del_timer_sync(&np->timer);
9916
9917         spin_lock_irqsave(&np->lock, flags);
9918         niu_enable_interrupts(np, 0);
9919         spin_unlock_irqrestore(&np->lock, flags);
9920
9921         netif_device_detach(dev);
9922
9923         spin_lock_irqsave(&np->lock, flags);
9924         niu_stop_hw(np);
9925         spin_unlock_irqrestore(&np->lock, flags);
9926
9927         pci_save_state(pdev);
9928
9929         return 0;
9930 }
9931
9932 static int niu_resume(struct pci_dev *pdev)
9933 {
9934         struct net_device *dev = pci_get_drvdata(pdev);
9935         struct niu *np = netdev_priv(dev);
9936         unsigned long flags;
9937         int err;
9938
9939         if (!netif_running(dev))
9940                 return 0;
9941
9942         pci_restore_state(pdev);
9943
9944         netif_device_attach(dev);
9945
9946         spin_lock_irqsave(&np->lock, flags);
9947
9948         err = niu_init_hw(np);
9949         if (!err) {
9950                 np->timer.expires = jiffies + HZ;
9951                 add_timer(&np->timer);
9952                 niu_netif_start(np);
9953         }
9954
9955         spin_unlock_irqrestore(&np->lock, flags);
9956
9957         return err;
9958 }
9959
9960 static struct pci_driver niu_pci_driver = {
9961         .name           = DRV_MODULE_NAME,
9962         .id_table       = niu_pci_tbl,
9963         .probe          = niu_pci_init_one,
9964         .remove         = niu_pci_remove_one,
9965         .suspend        = niu_suspend,
9966         .resume         = niu_resume,
9967 };
9968
9969 #ifdef CONFIG_SPARC64
9970 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9971                                      u64 *dma_addr, gfp_t flag)
9972 {
9973         unsigned long order = get_order(size);
9974         unsigned long page = __get_free_pages(flag, order);
9975
9976         if (page == 0UL)
9977                 return NULL;
9978         memset((char *)page, 0, PAGE_SIZE << order);
9979         *dma_addr = __pa(page);
9980
9981         return (void *) page;
9982 }
9983
9984 static void niu_phys_free_coherent(struct device *dev, size_t size,
9985                                    void *cpu_addr, u64 handle)
9986 {
9987         unsigned long order = get_order(size);
9988
9989         free_pages((unsigned long) cpu_addr, order);
9990 }
9991
9992 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9993                              unsigned long offset, size_t size,
9994                              enum dma_data_direction direction)
9995 {
9996         return page_to_phys(page) + offset;
9997 }
9998
9999 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10000                                 size_t size, enum dma_data_direction direction)
10001 {
10002         /* Nothing to do.  */
10003 }
10004
10005 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10006                                size_t size,
10007                                enum dma_data_direction direction)
10008 {
10009         return __pa(cpu_addr);
10010 }
10011
10012 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10013                                   size_t size,
10014                                   enum dma_data_direction direction)
10015 {
10016         /* Nothing to do.  */
10017 }
10018
10019 static const struct niu_ops niu_phys_ops = {
10020         .alloc_coherent = niu_phys_alloc_coherent,
10021         .free_coherent  = niu_phys_free_coherent,
10022         .map_page       = niu_phys_map_page,
10023         .unmap_page     = niu_phys_unmap_page,
10024         .map_single     = niu_phys_map_single,
10025         .unmap_single   = niu_phys_unmap_single,
10026 };
10027
10028 static int niu_of_probe(struct platform_device *op)
10029 {
10030         union niu_parent_id parent_id;
10031         struct net_device *dev;
10032         struct niu *np;
10033         const u32 *reg;
10034         int err;
10035
10036         niu_driver_version();
10037
10038         reg = of_get_property(op->dev.of_node, "reg", NULL);
10039         if (!reg) {
10040                 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10041                         op->dev.of_node->full_name);
10042                 return -ENODEV;
10043         }
10044
10045         dev = niu_alloc_and_init(&op->dev, NULL, op,
10046                                  &niu_phys_ops, reg[0] & 0x1);
10047         if (!dev) {
10048                 err = -ENOMEM;
10049                 goto err_out;
10050         }
10051         np = netdev_priv(dev);
10052
10053         memset(&parent_id, 0, sizeof(parent_id));
10054         parent_id.of = of_get_parent(op->dev.of_node);
10055
10056         np->parent = niu_get_parent(np, &parent_id,
10057                                     PLAT_TYPE_NIU);
10058         if (!np->parent) {
10059                 err = -ENOMEM;
10060                 goto err_out_free_dev;
10061         }
10062
10063         niu_set_basic_features(dev);
10064
10065         np->regs = of_ioremap(&op->resource[1], 0,
10066                               resource_size(&op->resource[1]),
10067                               "niu regs");
10068         if (!np->regs) {
10069                 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10070                 err = -ENOMEM;
10071                 goto err_out_release_parent;
10072         }
10073
10074         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10075                                     resource_size(&op->resource[2]),
10076                                     "niu vregs-1");
10077         if (!np->vir_regs_1) {
10078                 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10079                 err = -ENOMEM;
10080                 goto err_out_iounmap;
10081         }
10082
10083         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10084                                     resource_size(&op->resource[3]),
10085                                     "niu vregs-2");
10086         if (!np->vir_regs_2) {
10087                 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10088                 err = -ENOMEM;
10089                 goto err_out_iounmap;
10090         }
10091
10092         niu_assign_netdev_ops(dev);
10093
10094         err = niu_get_invariants(np);
10095         if (err) {
10096                 if (err != -ENODEV)
10097                         dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10098                 goto err_out_iounmap;
10099         }
10100
10101         err = register_netdev(dev);
10102         if (err) {
10103                 dev_err(&op->dev, "Cannot register net device, aborting\n");
10104                 goto err_out_iounmap;
10105         }
10106
10107         platform_set_drvdata(op, dev);
10108
10109         niu_device_announce(np);
10110
10111         return 0;
10112
10113 err_out_iounmap:
10114         if (np->vir_regs_1) {
10115                 of_iounmap(&op->resource[2], np->vir_regs_1,
10116                            resource_size(&op->resource[2]));
10117                 np->vir_regs_1 = NULL;
10118         }
10119
10120         if (np->vir_regs_2) {
10121                 of_iounmap(&op->resource[3], np->vir_regs_2,
10122                            resource_size(&op->resource[3]));
10123                 np->vir_regs_2 = NULL;
10124         }
10125
10126         if (np->regs) {
10127                 of_iounmap(&op->resource[1], np->regs,
10128                            resource_size(&op->resource[1]));
10129                 np->regs = NULL;
10130         }
10131
10132 err_out_release_parent:
10133         niu_put_parent(np);
10134
10135 err_out_free_dev:
10136         free_netdev(dev);
10137
10138 err_out:
10139         return err;
10140 }
10141
10142 static int niu_of_remove(struct platform_device *op)
10143 {
10144         struct net_device *dev = platform_get_drvdata(op);
10145
10146         if (dev) {
10147                 struct niu *np = netdev_priv(dev);
10148
10149                 unregister_netdev(dev);
10150
10151                 if (np->vir_regs_1) {
10152                         of_iounmap(&op->resource[2], np->vir_regs_1,
10153                                    resource_size(&op->resource[2]));
10154                         np->vir_regs_1 = NULL;
10155                 }
10156
10157                 if (np->vir_regs_2) {
10158                         of_iounmap(&op->resource[3], np->vir_regs_2,
10159                                    resource_size(&op->resource[3]));
10160                         np->vir_regs_2 = NULL;
10161                 }
10162
10163                 if (np->regs) {
10164                         of_iounmap(&op->resource[1], np->regs,
10165                                    resource_size(&op->resource[1]));
10166                         np->regs = NULL;
10167                 }
10168
10169                 niu_ldg_free(np);
10170
10171                 niu_put_parent(np);
10172
10173                 free_netdev(dev);
10174         }
10175         return 0;
10176 }
10177
10178 static const struct of_device_id niu_match[] = {
10179         {
10180                 .name = "network",
10181                 .compatible = "SUNW,niusl",
10182         },
10183         {},
10184 };
10185 MODULE_DEVICE_TABLE(of, niu_match);
10186
10187 static struct platform_driver niu_of_driver = {
10188         .driver = {
10189                 .name = "niu",
10190                 .of_match_table = niu_match,
10191         },
10192         .probe          = niu_of_probe,
10193         .remove         = niu_of_remove,
10194 };
10195
10196 #endif /* CONFIG_SPARC64 */
10197
10198 static int __init niu_init(void)
10199 {
10200         int err = 0;
10201
10202         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10203
10204         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10205
10206 #ifdef CONFIG_SPARC64
10207         err = platform_driver_register(&niu_of_driver);
10208 #endif
10209
10210         if (!err) {
10211                 err = pci_register_driver(&niu_pci_driver);
10212 #ifdef CONFIG_SPARC64
10213                 if (err)
10214                         platform_driver_unregister(&niu_of_driver);
10215 #endif
10216         }
10217
10218         return err;
10219 }
10220
10221 static void __exit niu_exit(void)
10222 {
10223         pci_unregister_driver(&niu_pci_driver);
10224 #ifdef CONFIG_SPARC64
10225         platform_driver_unregister(&niu_of_driver);
10226 #endif
10227 }
10228
10229 module_init(niu_init);
10230 module_exit(niu_exit);