drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/kmemleak.h>
  39 #include <linux/sys_soc.h>
  40
  41 #include <linux/pinctrl/consumer.h>
  42 #include <net/pkt_cls.h>
  43
  44 #include "cpsw.h"
  45 #include "cpsw_ale.h"
  46 #include "cpts.h"
  47 #include "davinci_cpdma.h"
  48
  49 #include <net/pkt_sched.h>
  50
  51 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  52                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  53                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  54                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  55                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  56                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  57                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  58                          NETIF_MSG_RX_STATUS)
  59
  60 #define cpsw_info(priv, type, format, ...)              \
  61 do {                                                            \
  62         if (netif_msg_##type(priv) && net_ratelimit())          \
  63                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  64 } while (0)
  65
  66 #define cpsw_err(priv, type, format, ...)               \
  67 do {                                                            \
  68         if (netif_msg_##type(priv) && net_ratelimit())          \
  69                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  70 } while (0)
  71
  72 #define cpsw_dbg(priv, type, format, ...)               \
  73 do {                                                            \
  74         if (netif_msg_##type(priv) && net_ratelimit())          \
  75                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  76 } while (0)
  77
  78 #define cpsw_notice(priv, type, format, ...)            \
  79 do {                                                            \
  80         if (netif_msg_##type(priv) && net_ratelimit())          \
  81                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  82 } while (0)
  83
  84 #define ALE_ALL_PORTS           0x7
  85
  86 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  87 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  88 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  89
  90 #define CPSW_VERSION_1          0x19010a
  91 #define CPSW_VERSION_2          0x19010c
  92 #define CPSW_VERSION_3          0x19010f
  93 #define CPSW_VERSION_4          0x190112
  94
  95 #define HOST_PORT_NUM           0
  96 #define CPSW_ALE_PORTS_NUM      3
  97 #define SLIVER_SIZE             0x40
  98
  99 #define CPSW1_HOST_PORT_OFFSET  0x028
 100 #define CPSW1_SLAVE_OFFSET      0x050
 101 #define CPSW1_SLAVE_SIZE        0x040
 102 #define CPSW1_CPDMA_OFFSET      0x100
 103 #define CPSW1_STATERAM_OFFSET   0x200
 104 #define CPSW1_HW_STATS          0x400
 105 #define CPSW1_CPTS_OFFSET       0x500
 106 #define CPSW1_ALE_OFFSET        0x600
 107 #define CPSW1_SLIVER_OFFSET     0x700
 108
 109 #define CPSW2_HOST_PORT_OFFSET  0x108
 110 #define CPSW2_SLAVE_OFFSET      0x200
 111 #define CPSW2_SLAVE_SIZE        0x100
 112 #define CPSW2_CPDMA_OFFSET      0x800
 113 #define CPSW2_HW_STATS          0x900
 114 #define CPSW2_STATERAM_OFFSET   0xa00
 115 #define CPSW2_CPTS_OFFSET       0xc00
 116 #define CPSW2_ALE_OFFSET        0xd00
 117 #define CPSW2_SLIVER_OFFSET     0xd80
 118 #define CPSW2_BD_OFFSET         0x2000
 119
 120 #define CPDMA_RXTHRESH          0x0c0
 121 #define CPDMA_RXFREE            0x0e0
 122 #define CPDMA_TXHDP             0x00
 123 #define CPDMA_RXHDP             0x20
 124 #define CPDMA_TXCP              0x40
 125 #define CPDMA_RXCP              0x60
 126
 127 #define CPSW_POLL_WEIGHT        64
 128 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
 129 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
 130 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
 131                                  ETH_FCS_LEN +\
 132                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
 133
 134 #define RX_PRIORITY_MAPPING     0x76543210
 135 #define TX_PRIORITY_MAPPING     0x33221100
 136 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 137
 138 #define CPSW_VLAN_AWARE         BIT(1)
 139 #define CPSW_RX_VLAN_ENCAP      BIT(2)
 140 #define CPSW_ALE_VLAN_AWARE     1
 141
 142 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 143 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 144 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 145
 146 #define CPSW_INTPACEEN          (0x3f << 16)
 147 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 148 #define CPSW_CMINTMAX_CNT       63
 149 #define CPSW_CMINTMIN_CNT       2
 150 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 151 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 152
 153 #define cpsw_slave_index(cpsw, priv)                            \
 154                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 155                 cpsw->data.active_slave)
 156 #define IRQ_NUM                 2
 157 #define CPSW_MAX_QUEUES         8
 158 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 159 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
 160 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
 161 #define CPSW_FIFO_RATE_EN_SHIFT         20
 162 #define CPSW_TC_NUM                     4
 163 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
 164 #define CPSW_PCT_MASK                   0x7f
 165
 166 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
 167 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
 168 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
 169 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
 170 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
 171 enum {
 172         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
 173         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
 174         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
 175         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
 176 };
 177
 178 static int debug_level;
 179 module_param(debug_level, int, 0);
 180 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 181
 182 static int ale_ageout = 10;
 183 module_param(ale_ageout, int, 0);
 184 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 185
 186 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 187 module_param(rx_packet_max, int, 0);
 188 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 189
 190 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 191 module_param(descs_pool_size, int, 0444);
 192 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 193
 194 struct cpsw_wr_regs {
 195         u32     id_ver;
 196         u32     soft_reset;
 197         u32     control;
 198         u32     int_control;
 199         u32     rx_thresh_en;
 200         u32     rx_en;
 201         u32     tx_en;
 202         u32     misc_en;
 203         u32     mem_allign1[8];
 204         u32     rx_thresh_stat;
 205         u32     rx_stat;
 206         u32     tx_stat;
 207         u32     misc_stat;
 208         u32     mem_allign2[8];
 209         u32     rx_imax;
 210         u32     tx_imax;
 211
 212 };
 213
 214 struct cpsw_ss_regs {
 215         u32     id_ver;
 216         u32     control;
 217         u32     soft_reset;
 218         u32     stat_port_en;
 219         u32     ptype;
 220         u32     soft_idle;
 221         u32     thru_rate;
 222         u32     gap_thresh;
 223         u32     tx_start_wds;
 224         u32     flow_control;
 225         u32     vlan_ltype;
 226         u32     ts_ltype;
 227         u32     dlr_ltype;
 228 };
 229
 230 /* CPSW_PORT_V1 */
 231 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 232 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 233 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 234 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 235 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 236 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 237 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 238 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 239
 240 /* CPSW_PORT_V2 */
 241 #define CPSW2_CONTROL       0x00 /* Control Register */
 242 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 243 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 244 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 245 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 246 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 247 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 248
 249 /* CPSW_PORT_V1 and V2 */
 250 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 251 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 252 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 253
 254 /* CPSW_PORT_V2 only */
 255 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 256 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 257 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 258 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 259 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 260 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 261 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 262 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 263
 264 /* Bit definitions for the CPSW2_CONTROL register */
 265 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
 266 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
 267 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
 268 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
 269 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
 270 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
 271 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
 272 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
 273 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
 274 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
 275 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
 276 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
 277 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
 278 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
 279 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
 280 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
 281 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
 282 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
 283
 284 #define CTRL_V2_TS_BITS \
 285         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 286          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 287
 288 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 289 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 290 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 291
 292
 293 #define CTRL_V3_TS_BITS \
 294         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 295          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 296          TS_LTYPE1_EN)
 297
 298 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 299 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 300 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 301
 302 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 303 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 304 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 305 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 306 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 307
 308 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 309 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 310
 311 /* Bit definitions for the CPSW1_TS_CTL register */
 312 #define CPSW_V1_TS_RX_EN                BIT(0)
 313 #define CPSW_V1_TS_TX_EN                BIT(4)
 314 #define CPSW_V1_MSG_TYPE_OFS            16
 315
 316 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 317 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 318
 319 #define CPSW_MAX_BLKS_TX                15
 320 #define CPSW_MAX_BLKS_TX_SHIFT          4
 321 #define CPSW_MAX_BLKS_RX                5
 322
 323 struct cpsw_host_regs {
 324         u32     max_blks;
 325         u32     blk_cnt;
 326         u32     tx_in_ctl;
 327         u32     port_vlan;
 328         u32     tx_pri_map;
 329         u32     cpdma_tx_pri_map;
 330         u32     cpdma_rx_chan_map;
 331 };
 332
 333 struct cpsw_sliver_regs {
 334         u32     id_ver;
 335         u32     mac_control;
 336         u32     mac_status;
 337         u32     soft_reset;
 338         u32     rx_maxlen;
 339         u32     __reserved_0;
 340         u32     rx_pause;
 341         u32     tx_pause;
 342         u32     __reserved_1;
 343         u32     rx_pri_map;
 344 };
 345
 346 struct cpsw_hw_stats {
 347         u32     rxgoodframes;
 348         u32     rxbroadcastframes;
 349         u32     rxmulticastframes;
 350         u32     rxpauseframes;
 351         u32     rxcrcerrors;
 352         u32     rxaligncodeerrors;
 353         u32     rxoversizedframes;
 354         u32     rxjabberframes;
 355         u32     rxundersizedframes;
 356         u32     rxfragments;
 357         u32     __pad_0[2];
 358         u32     rxoctets;
 359         u32     txgoodframes;
 360         u32     txbroadcastframes;
 361         u32     txmulticastframes;
 362         u32     txpauseframes;
 363         u32     txdeferredframes;
 364         u32     txcollisionframes;
 365         u32     txsinglecollframes;
 366         u32     txmultcollframes;
 367         u32     txexcessivecollisions;
 368         u32     txlatecollisions;
 369         u32     txunderrun;
 370         u32     txcarriersenseerrors;
 371         u32     txoctets;
 372         u32     octetframes64;
 373         u32     octetframes65t127;
 374         u32     octetframes128t255;
 375         u32     octetframes256t511;
 376         u32     octetframes512t1023;
 377         u32     octetframes1024tup;
 378         u32     netoctets;
 379         u32     rxsofoverruns;
 380         u32     rxmofoverruns;
 381         u32     rxdmaoverruns;
 382 };
 383
 384 struct cpsw_slave_data {
 385         struct device_node *phy_node;
 386         char            phy_id[MII_BUS_ID_SIZE];
 387         int             phy_if;
 388         u8              mac_addr[ETH_ALEN];
 389         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 390 };
 391
 392 struct cpsw_platform_data {
 393         struct cpsw_slave_data  *slave_data;
 394         u32     ss_reg_ofs;     /* Subsystem control register offset */
 395         u32     channels;       /* number of cpdma channels (symmetric) */
 396         u32     slaves;         /* number of slave cpgmac ports */
 397         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 398         u32     ale_entries;    /* ale table size */
 399         u32     bd_ram_size;  /*buffer descriptor ram size */
 400         u32     mac_control;    /* Mac control register */
 401         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 402         bool    dual_emac;      /* Enable Dual EMAC mode */
 403 };
 404
 405 struct cpsw_slave {
 406         void __iomem                    *regs;
 407         struct cpsw_sliver_regs __iomem *sliver;
 408         int                             slave_num;
 409         u32                             mac_control;
 410         struct cpsw_slave_data          *data;
 411         struct phy_device               *phy;
 412         struct net_device               *ndev;
 413         u32                             port_vlan;
 414 };
 415
 416 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 417 {
 418         return readl_relaxed(slave->regs + offset);
 419 }
 420
 421 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 422 {
 423         writel_relaxed(val, slave->regs + offset);
 424 }
 425
 426 struct cpsw_vector {
 427         struct cpdma_chan *ch;
 428         int budget;
 429 };
 430
 431 struct cpsw_common {
 432         struct device                   *dev;
 433         struct cpsw_platform_data       data;
 434         struct napi_struct              napi_rx;
 435         struct napi_struct              napi_tx;
 436         struct cpsw_ss_regs __iomem     *regs;
 437         struct cpsw_wr_regs __iomem     *wr_regs;
 438         u8 __iomem                      *hw_stats;
 439         struct cpsw_host_regs __iomem   *host_port_regs;
 440         u32                             version;
 441         u32                             coal_intvl;
 442         u32                             bus_freq_mhz;
 443         int                             rx_packet_max;
 444         struct cpsw_slave               *slaves;
 445         struct cpdma_ctlr               *dma;
 446         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 447         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 448         struct cpsw_ale                 *ale;
 449         bool                            quirk_irq;
 450         bool                            rx_irq_disabled;
 451         bool                            tx_irq_disabled;
 452         u32 irqs_table[IRQ_NUM];
 453         struct cpts                     *cpts;
 454         int                             rx_ch_num, tx_ch_num;
 455         int                             speed;
 456         int                             usage_count;
 457 };
 458
 459 struct cpsw_priv {
 460         struct net_device               *ndev;
 461         struct device                   *dev;
 462         u32                             msg_enable;
 463         u8                              mac_addr[ETH_ALEN];
 464         bool                            rx_pause;
 465         bool                            tx_pause;
 466         bool                            mqprio_hw;
 467         int                             fifo_bw[CPSW_TC_NUM];
 468         int                             shp_cfg_speed;
 469         u32 emac_port;
 470         struct cpsw_common *cpsw;
 471 };
 472
 473 struct cpsw_stats {
 474         char stat_string[ETH_GSTRING_LEN];
 475         int type;
 476         int sizeof_stat;
 477         int stat_offset;
 478 };
 479
 480 enum {
 481         CPSW_STATS,
 482         CPDMA_RX_STATS,
 483         CPDMA_TX_STATS,
 484 };
 485
 486 #define CPSW_STAT(m)            CPSW_STATS,                             \
 487                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 488                                 offsetof(struct cpsw_hw_stats, m)
 489 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 490                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 491                                 offsetof(struct cpdma_chan_stats, m)
 492 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 493                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 494                                 offsetof(struct cpdma_chan_stats, m)
 495
 496 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 497         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 498         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 499         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 500         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 501         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 502         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 503         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 504         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 505         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 506         { "Rx Fragments", CPSW_STAT(rxfragments) },
 507         { "Rx Octets", CPSW_STAT(rxoctets) },
 508         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 509         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 510         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 511         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 512         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 513         { "Collisions", CPSW_STAT(txcollisionframes) },
 514         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 515         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 516         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 517         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 518         { "Tx Underrun", CPSW_STAT(txunderrun) },
 519         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 520         { "Tx Octets", CPSW_STAT(txoctets) },
 521         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 522         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 523         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 524         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 525         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 526         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 527         { "Net Octets", CPSW_STAT(netoctets) },
 528         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 529         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 530         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 531 };
 532
 533 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 534         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 535         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 536         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 537         { "misqueued", CPDMA_RX_STAT(misqueued) },
 538         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 539         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 540         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 541         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 542         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 543         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 544         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 545         { "requeue", CPDMA_RX_STAT(requeue) },
 546         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 547 };
 548
 549 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 550 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 551
 552 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 553 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 554 #define for_each_slave(priv, func, arg...)                              \
 555         do {                                                            \
 556                 struct cpsw_slave *slave;                               \
 557                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 558                 int n;                                                  \
 559                 if (cpsw->data.dual_emac)                               \
 560                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 561                 else                                                    \
 562                         for (n = cpsw->data.slaves,                     \
 563                                         slave = cpsw->slaves;           \
 564                                         n; n--)                         \
 565                                 (func)(slave++, ##arg);                 \
 566         } while (0)
 567
 568 static inline int cpsw_get_slave_port(u32 slave_num)
 569 {
 570         return slave_num + 1;
 571 }
 572
 573 static void cpsw_add_mcast(struct cpsw_priv *priv, u8 *addr)
 574 {
 575         struct cpsw_common *cpsw = priv->cpsw;
 576
 577         if (cpsw->data.dual_emac) {
 578                 struct cpsw_slave *slave = cpsw->slaves + priv->emac_port;
 579                 int slave_port = cpsw_get_slave_port(slave->slave_num);
 580
 581                 cpsw_ale_add_mcast(cpsw->ale, addr,
 582                                    1 << slave_port | ALE_PORT_HOST,
 583                                    ALE_VLAN, slave->port_vlan, 0);
 584                 return;
 585         }
 586
 587         cpsw_ale_add_mcast(cpsw->ale, addr, ALE_ALL_PORTS, 0, 0, 0);
 588 }
 589
 590 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 591 {
 592         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 593         struct cpsw_ale *ale = cpsw->ale;
 594         int i;
 595
 596         if (cpsw->data.dual_emac) {
 597                 bool flag = false;
 598
 599                 /* Enabling promiscuous mode for one interface will be
 600                  * common for both the interface as the interface shares
 601                  * the same hardware resource.
 602                  */
 603                 for (i = 0; i < cpsw->data.slaves; i++)
 604                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 605                                 flag = true;
 606
 607                 if (!enable && flag) {
 608                         enable = true;
 609                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 610                 }
 611
 612                 if (enable) {
 613                         /* Enable Bypass */
 614                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 615
 616                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 617                 } else {
 618                         /* Disable Bypass */
 619                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 620                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 621                 }
 622         } else {
 623                 if (enable) {
 624                         unsigned long timeout = jiffies + HZ;
 625
 626                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 627                         for (i = 0; i <= cpsw->data.slaves; i++) {
 628                                 cpsw_ale_control_set(ale, i,
 629                                                      ALE_PORT_NOLEARN, 1);
 630                                 cpsw_ale_control_set(ale, i,
 631                                                      ALE_PORT_NO_SA_UPDATE, 1);
 632                         }
 633
 634                         /* Clear All Untouched entries */
 635                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 636                         do {
 637                                 cpu_relax();
 638                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 639                                         break;
 640                         } while (time_after(timeout, jiffies));
 641                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 642
 643                         /* Clear all mcast from ALE */
 644                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 645                         __dev_mc_unsync(ndev, NULL);
 646
 647                         /* Flood All Unicast Packets to Host port */
 648                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 649                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 650                 } else {
 651                         /* Don't Flood All Unicast Packets to Host port */
 652                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 653
 654                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 655                         for (i = 0; i <= cpsw->data.slaves; i++) {
 656                                 cpsw_ale_control_set(ale, i,
 657                                                      ALE_PORT_NOLEARN, 0);
 658                                 cpsw_ale_control_set(ale, i,
 659                                                      ALE_PORT_NO_SA_UPDATE, 0);
 660                         }
 661                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 662                 }
 663         }
 664 }
 665
 666 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 667 {
 668         struct cpsw_priv *priv = netdev_priv(ndev);
 669         struct cpsw_common *cpsw = priv->cpsw;
 670         int vid;
 671
 672         if (cpsw->data.dual_emac)
 673                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 674         else
 675                 vid = cpsw->data.default_vlan;
 676
 677         if (ndev->flags & IFF_PROMISC) {
 678                 /* Enable promiscuous mode */
 679                 cpsw_set_promiscious(ndev, true);
 680                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 681                 return;
 682         } else {
 683                 /* Disable promiscuous mode */
 684                 cpsw_set_promiscious(ndev, false);
 685         }
 686
 687         /* Restore allmulti on vlans if necessary */
 688         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 689
 690         /* Clear all mcast from ALE */
 691         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 692
 693         if (!netdev_mc_empty(ndev)) {
 694                 struct netdev_hw_addr *ha;
 695
 696                 /* program multicast address list into ALE register */
 697                 netdev_for_each_mc_addr(ha, ndev) {
 698                         cpsw_add_mcast(priv, ha->addr);
 699                 }
 700         }
 701 }
 702
 703 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 704 {
 705         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
 706         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
 707
 708         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 709         return;
 710 }
 711
 712 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 713 {
 714         writel_relaxed(0, &cpsw->wr_regs->tx_en);
 715         writel_relaxed(0, &cpsw->wr_regs->rx_en);
 716
 717         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 718         return;
 719 }
 720
 721 static void cpsw_tx_handler(void *token, int len, int status)
 722 {
 723         struct netdev_queue     *txq;
 724         struct sk_buff          *skb = token;
 725         struct net_device       *ndev = skb->dev;
 726         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 727
 728         /* Check whether the queue is stopped due to stalled tx dma, if the
 729          * queue is stopped then start the queue as we have free desc for tx
 730          */
 731         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 732         if (unlikely(netif_tx_queue_stopped(txq)))
 733                 netif_tx_wake_queue(txq);
 734
 735         cpts_tx_timestamp(cpsw->cpts, skb);
 736         ndev->stats.tx_packets++;
 737         ndev->stats.tx_bytes += len;
 738         dev_kfree_skb_any(skb);
 739 }
 740
 741 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
 742 {
 743         struct cpsw_priv *priv = netdev_priv(skb->dev);
 744         struct cpsw_common *cpsw = priv->cpsw;
 745         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
 746         u16 vtag, vid, prio, pkt_type;
 747
 748         /* Remove VLAN header encapsulation word */
 749         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
 750
 751         pkt_type = (rx_vlan_encap_hdr >>
 752                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
 753                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
 754         /* Ignore unknown & Priority-tagged packets*/
 755         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
 756             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
 757                 return;
 758
 759         vid = (rx_vlan_encap_hdr >>
 760                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
 761                VLAN_VID_MASK;
 762         /* Ignore vid 0 and pass packet as is */
 763         if (!vid)
 764                 return;
 765         /* Ignore default vlans in dual mac mode */
 766         if (cpsw->data.dual_emac &&
 767             vid == cpsw->slaves[priv->emac_port].port_vlan)
 768                 return;
 769
 770         prio = (rx_vlan_encap_hdr >>
 771                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
 772                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
 773
 774         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
 775         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
 776
 777         /* strip vlan tag for VLAN-tagged packet */
 778         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
 779                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
 780                 skb_pull(skb, VLAN_HLEN);
 781         }
 782 }
 783
 784 static void cpsw_rx_handler(void *token, int len, int status)
 785 {
 786         struct cpdma_chan       *ch;
 787         struct sk_buff          *skb = token;
 788         struct sk_buff          *new_skb;
 789         struct net_device       *ndev = skb->dev;
 790         int                     ret = 0, port;
 791         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 792
 793         if (cpsw->data.dual_emac) {
 794                 port = CPDMA_RX_SOURCE_PORT(status);
 795                 if (port) {
 796                         ndev = cpsw->slaves[--port].ndev;
 797                         skb->dev = ndev;
 798                 }
 799         }
 800
 801         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 802                 /* In dual emac mode check for all interfaces */
 803                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 804                     (status >= 0)) {
 805                         /* The packet received is for the interface which
 806                          * is already down and the other interface is up
 807                          * and running, instead of freeing which results
 808                          * in reducing of the number of rx descriptor in
 809                          * DMA engine, requeue skb back to cpdma.
 810                          */
 811                         new_skb = skb;
 812                         goto requeue;
 813                 }
 814
 815                 /* the interface is going down, skbs are purged */
 816                 dev_kfree_skb_any(skb);
 817                 return;
 818         }
 819
 820         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 821         if (new_skb) {
 822                 skb_copy_queue_mapping(new_skb, skb);
 823                 skb_put(skb, len);
 824                 if (status & CPDMA_RX_VLAN_ENCAP)
 825                         cpsw_rx_vlan_encap(skb);
 826                 cpts_rx_timestamp(cpsw->cpts, skb);
 827                 skb->protocol = eth_type_trans(skb, ndev);
 828                 netif_receive_skb(skb);
 829                 ndev->stats.rx_bytes += len;
 830                 ndev->stats.rx_packets++;
 831                 kmemleak_not_leak(new_skb);
 832         } else {
 833                 ndev->stats.rx_dropped++;
 834                 new_skb = skb;
 835         }
 836
 837 requeue:
 838         if (netif_dormant(ndev)) {
 839                 dev_kfree_skb_any(new_skb);
 840                 return;
 841         }
 842
 843         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 844         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 845                                 skb_tailroom(new_skb), 0);
 846         if (WARN_ON(ret < 0))
 847                 dev_kfree_skb_any(new_skb);
 848 }
 849
 850 static void cpsw_split_res(struct net_device *ndev)
 851 {
 852         struct cpsw_priv *priv = netdev_priv(ndev);
 853         u32 consumed_rate = 0, bigest_rate = 0;
 854         struct cpsw_common *cpsw = priv->cpsw;
 855         struct cpsw_vector *txv = cpsw->txv;
 856         int i, ch_weight, rlim_ch_num = 0;
 857         int budget, bigest_rate_ch = 0;
 858         u32 ch_rate, max_rate;
 859         int ch_budget = 0;
 860
 861         for (i = 0; i < cpsw->tx_ch_num; i++) {
 862                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 863                 if (!ch_rate)
 864                         continue;
 865
 866                 rlim_ch_num++;
 867                 consumed_rate += ch_rate;
 868         }
 869
 870         if (cpsw->tx_ch_num == rlim_ch_num) {
 871                 max_rate = consumed_rate;
 872         } else if (!rlim_ch_num) {
 873                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 874                 bigest_rate = 0;
 875                 max_rate = consumed_rate;
 876         } else {
 877                 max_rate = cpsw->speed * 1000;
 878
 879                 /* if max_rate is less then expected due to reduced link speed,
 880                  * split proportionally according next potential max speed
 881                  */
 882                 if (max_rate < consumed_rate)
 883                         max_rate *= 10;
 884
 885                 if (max_rate < consumed_rate)
 886                         max_rate *= 10;
 887
 888                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 889                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 890                             (cpsw->tx_ch_num - rlim_ch_num);
 891                 bigest_rate = (max_rate - consumed_rate) /
 892                               (cpsw->tx_ch_num - rlim_ch_num);
 893         }
 894
 895         /* split tx weight/budget */
 896         budget = CPSW_POLL_WEIGHT;
 897         for (i = 0; i < cpsw->tx_ch_num; i++) {
 898                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 899                 if (ch_rate) {
 900                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 901                         if (!txv[i].budget)
 902                                 txv[i].budget++;
 903                         if (ch_rate > bigest_rate) {
 904                                 bigest_rate_ch = i;
 905                                 bigest_rate = ch_rate;
 906                         }
 907
 908                         ch_weight = (ch_rate * 100) / max_rate;
 909                         if (!ch_weight)
 910                                 ch_weight++;
 911                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 912                 } else {
 913                         txv[i].budget = ch_budget;
 914                         if (!bigest_rate_ch)
 915                                 bigest_rate_ch = i;
 916                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 917                 }
 918
 919                 budget -= txv[i].budget;
 920         }
 921
 922         if (budget)
 923                 txv[bigest_rate_ch].budget += budget;
 924
 925         /* split rx budget */
 926         budget = CPSW_POLL_WEIGHT;
 927         ch_budget = budget / cpsw->rx_ch_num;
 928         for (i = 0; i < cpsw->rx_ch_num; i++) {
 929                 cpsw->rxv[i].budget = ch_budget;
 930                 budget -= ch_budget;
 931         }
 932
 933         if (budget)
 934                 cpsw->rxv[0].budget += budget;
 935 }
 936
 937 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 938 {
 939         struct cpsw_common *cpsw = dev_id;
 940
 941         writel(0, &cpsw->wr_regs->tx_en);
 942         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 943
 944         if (cpsw->quirk_irq) {
 945                 disable_irq_nosync(cpsw->irqs_table[1]);
 946                 cpsw->tx_irq_disabled = true;
 947         }
 948
 949         napi_schedule(&cpsw->napi_tx);
 950         return IRQ_HANDLED;
 951 }
 952
 953 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 954 {
 955         struct cpsw_common *cpsw = dev_id;
 956
 957         writel(0, &cpsw->wr_regs->rx_en);
 958         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 959
 960         if (cpsw->quirk_irq) {
 961                 disable_irq_nosync(cpsw->irqs_table[0]);
 962                 cpsw->rx_irq_disabled = true;
 963         }
 964
 965         napi_schedule(&cpsw->napi_rx);
 966         return IRQ_HANDLED;
 967 }
 968
 969 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
 970 {
 971         u32                     ch_map;
 972         int                     num_tx, cur_budget, ch;
 973         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 974         struct cpsw_vector      *txv;
 975
 976         /* process every unprocessed channel */
 977         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 978         for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
 979                 if (!(ch_map & 0x80))
 980                         continue;
 981
 982                 txv = &cpsw->txv[ch];
 983                 if (unlikely(txv->budget > budget - num_tx))
 984                         cur_budget = budget - num_tx;
 985                 else
 986                         cur_budget = txv->budget;
 987
 988                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 989                 if (num_tx >= budget)
 990                         break;
 991         }
 992
 993         if (num_tx < budget) {
 994                 napi_complete(napi_tx);
 995                 writel(0xff, &cpsw->wr_regs->tx_en);
 996         }
 997
 998         return num_tx;
 999 }
1000
1001 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1002 {
1003         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1004         int num_tx;
1005
1006         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1007         if (num_tx < budget) {
1008                 napi_complete(napi_tx);
1009                 writel(0xff, &cpsw->wr_regs->tx_en);
1010                 if (cpsw->tx_irq_disabled) {
1011                         cpsw->tx_irq_disabled = false;
1012                         enable_irq(cpsw->irqs_table[1]);
1013                 }
1014         }
1015
1016         return num_tx;
1017 }
1018
1019 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1020 {
1021         u32                     ch_map;
1022         int                     num_rx, cur_budget, ch;
1023         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1024         struct cpsw_vector      *rxv;
1025
1026         /* process every unprocessed channel */
1027         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1028         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1029                 if (!(ch_map & 0x01))
1030                         continue;
1031
1032                 rxv = &cpsw->rxv[ch];
1033                 if (unlikely(rxv->budget > budget - num_rx))
1034                         cur_budget = budget - num_rx;
1035                 else
1036                         cur_budget = rxv->budget;
1037
1038                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1039                 if (num_rx >= budget)
1040                         break;
1041         }
1042
1043         if (num_rx < budget) {
1044                 napi_complete_done(napi_rx, num_rx);
1045                 writel(0xff, &cpsw->wr_regs->rx_en);
1046         }
1047
1048         return num_rx;
1049 }
1050
1051 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1052 {
1053         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1054         int num_rx;
1055
1056         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1057         if (num_rx < budget) {
1058                 napi_complete_done(napi_rx, num_rx);
1059                 writel(0xff, &cpsw->wr_regs->rx_en);
1060                 if (cpsw->rx_irq_disabled) {
1061                         cpsw->rx_irq_disabled = false;
1062                         enable_irq(cpsw->irqs_table[0]);
1063                 }
1064         }
1065
1066         return num_rx;
1067 }
1068
1069 static inline void soft_reset(const char *module, void __iomem *reg)
1070 {
1071         unsigned long timeout = jiffies + HZ;
1072
1073         writel_relaxed(1, reg);
1074         do {
1075                 cpu_relax();
1076         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1077
1078         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1079 }
1080
1081 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1082                                struct cpsw_priv *priv)
1083 {
1084         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1085         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1086 }
1087
1088 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1089 {
1090         struct cpsw_common *cpsw = priv->cpsw;
1091         struct cpsw_slave *slave;
1092         u32 shift, mask, val;
1093
1094         val = readl_relaxed(&cpsw->regs->ptype);
1095
1096         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1097         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1098         mask = 7 << shift;
1099         val = val & mask;
1100
1101         return !val;
1102 }
1103
1104 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1105 {
1106         struct cpsw_common *cpsw = priv->cpsw;
1107         struct cpsw_slave *slave;
1108         u32 shift, mask, val;
1109
1110         val = readl_relaxed(&cpsw->regs->ptype);
1111
1112         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1113         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1114         mask = (1 << --fifo) << shift;
1115         val = on ? val | mask : val & ~mask;
1116
1117         writel_relaxed(val, &cpsw->regs->ptype);
1118 }
1119
1120 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1121                               struct cpsw_priv *priv, bool *link)
1122 {
1123         struct phy_device       *phy = slave->phy;
1124         u32                     mac_control = 0;
1125         u32                     slave_port;
1126         struct cpsw_common *cpsw = priv->cpsw;
1127
1128         if (!phy)
1129                 return;
1130
1131         slave_port = cpsw_get_slave_port(slave->slave_num);
1132
1133         if (phy->link) {
1134                 mac_control = cpsw->data.mac_control;
1135
1136                 /* enable forwarding */
1137                 cpsw_ale_control_set(cpsw->ale, slave_port,
1138                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1139
1140                 if (phy->speed == 1000)
1141                         mac_control |= BIT(7);  /* GIGABITEN    */
1142                 if (phy->duplex)
1143                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1144
1145                 /* set speed_in input in case RMII mode is used in 100Mbps */
1146                 if (phy->speed == 100)
1147                         mac_control |= BIT(15);
1148                 /* in band mode only works in 10Mbps RGMII mode */
1149                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1150                         mac_control |= BIT(18); /* In Band mode */
1151
1152                 if (priv->rx_pause)
1153                         mac_control |= BIT(3);
1154
1155                 if (priv->tx_pause)
1156                         mac_control |= BIT(4);
1157
1158                 *link = true;
1159
1160                 if (priv->shp_cfg_speed &&
1161                     priv->shp_cfg_speed != slave->phy->speed &&
1162                     !cpsw_shp_is_off(priv))
1163                         dev_warn(priv->dev,
1164                                  "Speed was changed, CBS shaper speeds are changed!");
1165         } else {
1166                 mac_control = 0;
1167                 /* disable forwarding */
1168                 cpsw_ale_control_set(cpsw->ale, slave_port,
1169                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1170         }
1171
1172         if (mac_control != slave->mac_control) {
1173                 phy_print_status(phy);
1174                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1175         }
1176
1177         slave->mac_control = mac_control;
1178 }
1179
1180 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1181 {
1182         int i, speed;
1183
1184         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1185                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1186                         speed += cpsw->slaves[i].phy->speed;
1187
1188         return speed;
1189 }
1190
1191 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1192 {
1193         int i, rlim_ch_num;
1194         int speed, ch_rate;
1195
1196         /* re-split resources only in case speed was changed */
1197         speed = cpsw_get_common_speed(cpsw);
1198         if (speed == cpsw->speed || !speed)
1199                 return 0;
1200
1201         cpsw->speed = speed;
1202
1203         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1204                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1205                 if (!ch_rate)
1206                         break;
1207
1208                 rlim_ch_num++;
1209         }
1210
1211         /* cases not dependent on speed */
1212         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1213                 return 0;
1214
1215         return 1;
1216 }
1217
1218 static void cpsw_adjust_link(struct net_device *ndev)
1219 {
1220         struct cpsw_priv        *priv = netdev_priv(ndev);
1221         struct cpsw_common      *cpsw = priv->cpsw;
1222         bool                    link = false;
1223
1224         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1225
1226         if (link) {
1227                 if (cpsw_need_resplit(cpsw))
1228                         cpsw_split_res(ndev);
1229
1230                 netif_carrier_on(ndev);
1231                 if (netif_running(ndev))
1232                         netif_tx_wake_all_queues(ndev);
1233         } else {
1234                 netif_carrier_off(ndev);
1235                 netif_tx_stop_all_queues(ndev);
1236         }
1237 }
1238
1239 static int cpsw_get_coalesce(struct net_device *ndev,
1240                                 struct ethtool_coalesce *coal)
1241 {
1242         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1243
1244         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1245         return 0;
1246 }
1247
1248 static int cpsw_set_coalesce(struct net_device *ndev,
1249                                 struct ethtool_coalesce *coal)
1250 {
1251         struct cpsw_priv *priv = netdev_priv(ndev);
1252         u32 int_ctrl;
1253         u32 num_interrupts = 0;
1254         u32 prescale = 0;
1255         u32 addnl_dvdr = 1;
1256         u32 coal_intvl = 0;
1257         struct cpsw_common *cpsw = priv->cpsw;
1258
1259         coal_intvl = coal->rx_coalesce_usecs;
1260
1261         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1262         prescale = cpsw->bus_freq_mhz * 4;
1263
1264         if (!coal->rx_coalesce_usecs) {
1265                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1266                 goto update_return;
1267         }
1268
1269         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1270                 coal_intvl = CPSW_CMINTMIN_INTVL;
1271
1272         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1273                 /* Interrupt pacer works with 4us Pulse, we can
1274                  * throttle further by dilating the 4us pulse.
1275                  */
1276                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1277
1278                 if (addnl_dvdr > 1) {
1279                         prescale *= addnl_dvdr;
1280                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1281                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1282                                                 * addnl_dvdr);
1283                 } else {
1284                         addnl_dvdr = 1;
1285                         coal_intvl = CPSW_CMINTMAX_INTVL;
1286                 }
1287         }
1288
1289         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1290         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1291         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1292
1293         int_ctrl |= CPSW_INTPACEEN;
1294         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1295         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1296
1297 update_return:
1298         writel(int_ctrl, &cpsw->wr_regs->int_control);
1299
1300         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1301         cpsw->coal_intvl = coal_intvl;
1302
1303         return 0;
1304 }
1305
1306 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1307 {
1308         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1309
1310         switch (sset) {
1311         case ETH_SS_STATS:
1312                 return (CPSW_STATS_COMMON_LEN +
1313                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1314                        CPSW_STATS_CH_LEN);
1315         default:
1316                 return -EOPNOTSUPP;
1317         }
1318 }
1319
1320 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1321 {
1322         int ch_stats_len;
1323         int line;
1324         int i;
1325
1326         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1327         for (i = 0; i < ch_stats_len; i++) {
1328                 line = i % CPSW_STATS_CH_LEN;
1329                 snprintf(*p, ETH_GSTRING_LEN,
1330                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1331                          (long)(i / CPSW_STATS_CH_LEN),
1332                          cpsw_gstrings_ch_stats[line].stat_string);
1333                 *p += ETH_GSTRING_LEN;
1334         }
1335 }
1336
1337 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1338 {
1339         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1340         u8 *p = data;
1341         int i;
1342
1343         switch (stringset) {
1344         case ETH_SS_STATS:
1345                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1346                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1347                                ETH_GSTRING_LEN);
1348                         p += ETH_GSTRING_LEN;
1349                 }
1350
1351                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1352                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1353                 break;
1354         }
1355 }
1356
1357 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1358                                     struct ethtool_stats *stats, u64 *data)
1359 {
1360         u8 *p;
1361         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1362         struct cpdma_chan_stats ch_stats;
1363         int i, l, ch;
1364
1365         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1366         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1367                 data[l] = readl(cpsw->hw_stats +
1368                                 cpsw_gstrings_stats[l].stat_offset);
1369
1370         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1371                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1372                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1373                         p = (u8 *)&ch_stats +
1374                                 cpsw_gstrings_ch_stats[i].stat_offset;
1375                         data[l] = *(u32 *)p;
1376                 }
1377         }
1378
1379         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1380                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1381                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1382                         p = (u8 *)&ch_stats +
1383                                 cpsw_gstrings_ch_stats[i].stat_offset;
1384                         data[l] = *(u32 *)p;
1385                 }
1386         }
1387 }
1388
1389 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1390                                         struct sk_buff *skb,
1391                                         struct cpdma_chan *txch)
1392 {
1393         struct cpsw_common *cpsw = priv->cpsw;
1394
1395         skb_tx_timestamp(skb);
1396         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1397                                  priv->emac_port + cpsw->data.dual_emac);
1398 }
1399
1400 static inline void cpsw_add_dual_emac_def_ale_entries(
1401                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1402                 u32 slave_port)
1403 {
1404         struct cpsw_common *cpsw = priv->cpsw;
1405         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1406
1407         if (cpsw->version == CPSW_VERSION_1)
1408                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1409         else
1410                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1411         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1412                           port_mask, port_mask, 0);
1413         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1414                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1415         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1416                            HOST_PORT_NUM, ALE_VLAN |
1417                            ALE_SECURE, slave->port_vlan);
1418         cpsw_ale_control_set(cpsw->ale, slave_port,
1419                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1420 }
1421
1422 static void soft_reset_slave(struct cpsw_slave *slave)
1423 {
1424         char name[32];
1425
1426         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1427         soft_reset(name, &slave->sliver->soft_reset);
1428 }
1429
1430 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1431 {
1432         u32 slave_port;
1433         struct phy_device *phy;
1434         struct cpsw_common *cpsw = priv->cpsw;
1435
1436         soft_reset_slave(slave);
1437
1438         /* setup priority mapping */
1439         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1440
1441         switch (cpsw->version) {
1442         case CPSW_VERSION_1:
1443                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1444                 /* Increase RX FIFO size to 5 for supporting fullduplex
1445                  * flow control mode
1446                  */
1447                 slave_write(slave,
1448                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1449                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1450                 break;
1451         case CPSW_VERSION_2:
1452         case CPSW_VERSION_3:
1453         case CPSW_VERSION_4:
1454                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1455                 /* Increase RX FIFO size to 5 for supporting fullduplex
1456                  * flow control mode
1457                  */
1458                 slave_write(slave,
1459                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1460                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1461                 break;
1462         }
1463
1464         /* setup max packet size, and mac address */
1465         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1466         cpsw_set_slave_mac(slave, priv);
1467
1468         slave->mac_control = 0; /* no link yet */
1469
1470         slave_port = cpsw_get_slave_port(slave->slave_num);
1471
1472         if (cpsw->data.dual_emac)
1473                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1474         else
1475                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1476                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1477
1478         if (slave->data->phy_node) {
1479                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1480                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1481                 if (!phy) {
1482                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1483                                 slave->data->phy_node,
1484                                 slave->slave_num);
1485                         return;
1486                 }
1487         } else {
1488                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1489                                  &cpsw_adjust_link, slave->data->phy_if);
1490                 if (IS_ERR(phy)) {
1491                         dev_err(priv->dev,
1492                                 "phy \"%s\" not found on slave %d, err %ld\n",
1493                                 slave->data->phy_id, slave->slave_num,
1494                                 PTR_ERR(phy));
1495                         return;
1496                 }
1497         }
1498
1499         slave->phy = phy;
1500
1501         phy_attached_info(slave->phy);
1502
1503         phy_start(slave->phy);
1504
1505         /* Configure GMII_SEL register */
1506         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1507 }
1508
1509 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1510 {
1511         struct cpsw_common *cpsw = priv->cpsw;
1512         const int vlan = cpsw->data.default_vlan;
1513         u32 reg;
1514         int i;
1515         int unreg_mcast_mask;
1516
1517         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1518                CPSW2_PORT_VLAN;
1519
1520         writel(vlan, &cpsw->host_port_regs->port_vlan);
1521
1522         for (i = 0; i < cpsw->data.slaves; i++)
1523                 slave_write(cpsw->slaves + i, vlan, reg);
1524
1525         if (priv->ndev->flags & IFF_ALLMULTI)
1526                 unreg_mcast_mask = ALE_ALL_PORTS;
1527         else
1528                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1529
1530         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1531                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1532                           unreg_mcast_mask);
1533 }
1534
1535 static void cpsw_init_host_port(struct cpsw_priv *priv)
1536 {
1537         u32 fifo_mode;
1538         u32 control_reg;
1539         struct cpsw_common *cpsw = priv->cpsw;
1540
1541         /* soft reset the controller and initialize ale */
1542         soft_reset("cpsw", &cpsw->regs->soft_reset);
1543         cpsw_ale_start(cpsw->ale);
1544
1545         /* switch to vlan unaware mode */
1546         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1547                              CPSW_ALE_VLAN_AWARE);
1548         control_reg = readl(&cpsw->regs->control);
1549         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1550         writel(control_reg, &cpsw->regs->control);
1551         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1552                      CPSW_FIFO_NORMAL_MODE;
1553         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1554
1555         /* setup host port priority mapping */
1556         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1557                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1558         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1559
1560         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1561                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1562
1563         if (!cpsw->data.dual_emac) {
1564                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1565                                    0, 0);
1566                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1567                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1568         }
1569 }
1570
1571 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1572 {
1573         struct cpsw_common *cpsw = priv->cpsw;
1574         struct sk_buff *skb;
1575         int ch_buf_num;
1576         int ch, i, ret;
1577
1578         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1579                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1580                 for (i = 0; i < ch_buf_num; i++) {
1581                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1582                                                           cpsw->rx_packet_max,
1583                                                           GFP_KERNEL);
1584                         if (!skb) {
1585                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1586                                 return -ENOMEM;
1587                         }
1588
1589                         skb_set_queue_mapping(skb, ch);
1590                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1591                                                 skb->data, skb_tailroom(skb),
1592                                                 0);
1593                         if (ret < 0) {
1594                                 cpsw_err(priv, ifup,
1595                                          "cannot submit skb to channel %d rx, error %d\n",
1596                                          ch, ret);
1597                                 kfree_skb(skb);
1598                                 return ret;
1599                         }
1600                         kmemleak_not_leak(skb);
1601                 }
1602
1603                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1604                           ch, ch_buf_num);
1605         }
1606
1607         return 0;
1608 }
1609
1610 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1611 {
1612         u32 slave_port;
1613
1614         slave_port = cpsw_get_slave_port(slave->slave_num);
1615
1616         if (!slave->phy)
1617                 return;
1618         phy_stop(slave->phy);
1619         phy_disconnect(slave->phy);
1620         slave->phy = NULL;
1621         cpsw_ale_control_set(cpsw->ale, slave_port,
1622                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1623         soft_reset_slave(slave);
1624 }
1625
1626 static int cpsw_tc_to_fifo(int tc, int num_tc)
1627 {
1628         if (tc == num_tc - 1)
1629                 return 0;
1630
1631         return CPSW_FIFO_SHAPERS_NUM - tc;
1632 }
1633
1634 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1635 {
1636         struct cpsw_common *cpsw = priv->cpsw;
1637         u32 val = 0, send_pct, shift;
1638         struct cpsw_slave *slave;
1639         int pct = 0, i;
1640
1641         if (bw > priv->shp_cfg_speed * 1000)
1642                 goto err;
1643
1644         /* shaping has to stay enabled for highest fifos linearly
1645          * and fifo bw no more then interface can allow
1646          */
1647         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1648         send_pct = slave_read(slave, SEND_PERCENT);
1649         for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1650                 if (!bw) {
1651                         if (i >= fifo || !priv->fifo_bw[i])
1652                                 continue;
1653
1654                         dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1655                         continue;
1656                 }
1657
1658                 if (!priv->fifo_bw[i] && i > fifo) {
1659                         dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1660                         return -EINVAL;
1661                 }
1662
1663                 shift = (i - 1) * 8;
1664                 if (i == fifo) {
1665                         send_pct &= ~(CPSW_PCT_MASK << shift);
1666                         val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1667                         if (!val)
1668                                 val = 1;
1669
1670                         send_pct |= val << shift;
1671                         pct += val;
1672                         continue;
1673                 }
1674
1675                 if (priv->fifo_bw[i])
1676                         pct += (send_pct >> shift) & CPSW_PCT_MASK;
1677         }
1678
1679         if (pct >= 100)
1680                 goto err;
1681
1682         slave_write(slave, send_pct, SEND_PERCENT);
1683         priv->fifo_bw[fifo] = bw;
1684
1685         dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1686                  DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1687
1688         return 0;
1689 err:
1690         dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1691         return -EINVAL;
1692 }
1693
1694 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1695 {
1696         struct cpsw_common *cpsw = priv->cpsw;
1697         struct cpsw_slave *slave;
1698         u32 tx_in_ctl_rg, val;
1699         int ret;
1700
1701         ret = cpsw_set_fifo_bw(priv, fifo, bw);
1702         if (ret)
1703                 return ret;
1704
1705         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1706         tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1707                        CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1708
1709         if (!bw)
1710                 cpsw_fifo_shp_on(priv, fifo, bw);
1711
1712         val = slave_read(slave, tx_in_ctl_rg);
1713         if (cpsw_shp_is_off(priv)) {
1714                 /* disable FIFOs rate limited queues */
1715                 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1716
1717                 /* set type of FIFO queues to normal priority mode */
1718                 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1719
1720                 /* set type of FIFO queues to be rate limited */
1721                 if (bw)
1722                         val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1723                 else
1724                         priv->shp_cfg_speed = 0;
1725         }
1726
1727         /* toggle a FIFO rate limited queue */
1728         if (bw)
1729                 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1730         else
1731                 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1732         slave_write(slave, val, tx_in_ctl_rg);
1733
1734         /* FIFO transmit shape enable */
1735         cpsw_fifo_shp_on(priv, fifo, bw);
1736         return 0;
1737 }
1738
1739 /* Defaults:
1740  * class A - prio 3
1741  * class B - prio 2
1742  * shaping for class A should be set first
1743  */
1744 static int cpsw_set_cbs(struct net_device *ndev,
1745                         struct tc_cbs_qopt_offload *qopt)
1746 {
1747         struct cpsw_priv *priv = netdev_priv(ndev);
1748         struct cpsw_common *cpsw = priv->cpsw;
1749         struct cpsw_slave *slave;
1750         int prev_speed = 0;
1751         int tc, ret, fifo;
1752         u32 bw = 0;
1753
1754         tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1755
1756         /* enable channels in backward order, as highest FIFOs must be rate
1757          * limited first and for compliance with CPDMA rate limited channels
1758          * that also used in bacward order. FIFO0 cannot be rate limited.
1759          */
1760         fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1761         if (!fifo) {
1762                 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1763                 return -EINVAL;
1764         }
1765
1766         /* do nothing, it's disabled anyway */
1767         if (!qopt->enable && !priv->fifo_bw[fifo])
1768                 return 0;
1769
1770         /* shapers can be set if link speed is known */
1771         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1772         if (slave->phy && slave->phy->link) {
1773                 if (priv->shp_cfg_speed &&
1774                     priv->shp_cfg_speed != slave->phy->speed)
1775                         prev_speed = priv->shp_cfg_speed;
1776
1777                 priv->shp_cfg_speed = slave->phy->speed;
1778         }
1779
1780         if (!priv->shp_cfg_speed) {
1781                 dev_err(priv->dev, "Link speed is not known");
1782                 return -1;
1783         }
1784
1785         ret = pm_runtime_get_sync(cpsw->dev);
1786         if (ret < 0) {
1787                 pm_runtime_put_noidle(cpsw->dev);
1788                 return ret;
1789         }
1790
1791         bw = qopt->enable ? qopt->idleslope : 0;
1792         ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1793         if (ret) {
1794                 priv->shp_cfg_speed = prev_speed;
1795                 prev_speed = 0;
1796         }
1797
1798         if (bw && prev_speed)
1799                 dev_warn(priv->dev,
1800                          "Speed was changed, CBS shaper speeds are changed!");
1801
1802         pm_runtime_put_sync(cpsw->dev);
1803         return ret;
1804 }
1805
1806 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1807 {
1808         int fifo, bw;
1809
1810         for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1811                 bw = priv->fifo_bw[fifo];
1812                 if (!bw)
1813                         continue;
1814
1815                 cpsw_set_fifo_rlimit(priv, fifo, bw);
1816         }
1817 }
1818
1819 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1820 {
1821         struct cpsw_common *cpsw = priv->cpsw;
1822         u32 tx_prio_map = 0;
1823         int i, tc, fifo;
1824         u32 tx_prio_rg;
1825
1826         if (!priv->mqprio_hw)
1827                 return;
1828
1829         for (i = 0; i < 8; i++) {
1830                 tc = netdev_get_prio_tc_map(priv->ndev, i);
1831                 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1832                 tx_prio_map |= fifo << (4 * i);
1833         }
1834
1835         tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1836                      CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1837
1838         slave_write(slave, tx_prio_map, tx_prio_rg);
1839 }
1840
1841 /* restore resources after port reset */
1842 static void cpsw_restore(struct cpsw_priv *priv)
1843 {
1844         /* restore MQPRIO offload */
1845         for_each_slave(priv, cpsw_mqprio_resume, priv);
1846
1847         /* restore CBS offload */
1848         for_each_slave(priv, cpsw_cbs_resume, priv);
1849 }
1850
1851 static int cpsw_ndo_open(struct net_device *ndev)
1852 {
1853         struct cpsw_priv *priv = netdev_priv(ndev);
1854         struct cpsw_common *cpsw = priv->cpsw;
1855         int ret;
1856         u32 reg;
1857
1858         ret = pm_runtime_get_sync(cpsw->dev);
1859         if (ret < 0) {
1860                 pm_runtime_put_noidle(cpsw->dev);
1861                 return ret;
1862         }
1863
1864         netif_carrier_off(ndev);
1865
1866         /* Notify the stack of the actual queue counts. */
1867         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1868         if (ret) {
1869                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1870                 goto err_cleanup;
1871         }
1872
1873         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1874         if (ret) {
1875                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1876                 goto err_cleanup;
1877         }
1878
1879         reg = cpsw->version;
1880
1881         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1882                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1883                  CPSW_RTL_VERSION(reg));
1884
1885         /* Initialize host and slave ports */
1886         if (!cpsw->usage_count)
1887                 cpsw_init_host_port(priv);
1888         for_each_slave(priv, cpsw_slave_open, priv);
1889
1890         /* Add default VLAN */
1891         if (!cpsw->data.dual_emac)
1892                 cpsw_add_default_vlan(priv);
1893         else
1894                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1895                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1896
1897         /* initialize shared resources for every ndev */
1898         if (!cpsw->usage_count) {
1899                 /* disable priority elevation */
1900                 writel_relaxed(0, &cpsw->regs->ptype);
1901
1902                 /* enable statistics collection only on all ports */
1903                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1904
1905                 /* Enable internal fifo flow control */
1906                 writel(0x7, &cpsw->regs->flow_control);
1907
1908                 napi_enable(&cpsw->napi_rx);
1909                 napi_enable(&cpsw->napi_tx);
1910
1911                 if (cpsw->tx_irq_disabled) {
1912                         cpsw->tx_irq_disabled = false;
1913                         enable_irq(cpsw->irqs_table[1]);
1914                 }
1915
1916                 if (cpsw->rx_irq_disabled) {
1917                         cpsw->rx_irq_disabled = false;
1918                         enable_irq(cpsw->irqs_table[0]);
1919                 }
1920
1921                 ret = cpsw_fill_rx_channels(priv);
1922                 if (ret < 0)
1923                         goto err_cleanup;
1924
1925                 if (cpts_register(cpsw->cpts))
1926                         dev_err(priv->dev, "error registering cpts device\n");
1927
1928         }
1929
1930         cpsw_restore(priv);
1931
1932         /* Enable Interrupt pacing if configured */
1933         if (cpsw->coal_intvl != 0) {
1934                 struct ethtool_coalesce coal;
1935
1936                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1937                 cpsw_set_coalesce(ndev, &coal);
1938         }
1939
1940         cpdma_ctlr_start(cpsw->dma);
1941         cpsw_intr_enable(cpsw);
1942         cpsw->usage_count++;
1943
1944         return 0;
1945
1946 err_cleanup:
1947         cpdma_ctlr_stop(cpsw->dma);
1948         for_each_slave(priv, cpsw_slave_stop, cpsw);
1949         pm_runtime_put_sync(cpsw->dev);
1950         netif_carrier_off(priv->ndev);
1951         return ret;
1952 }
1953
1954 static int cpsw_ndo_stop(struct net_device *ndev)
1955 {
1956         struct cpsw_priv *priv = netdev_priv(ndev);
1957         struct cpsw_common *cpsw = priv->cpsw;
1958
1959         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1960         netif_tx_stop_all_queues(priv->ndev);
1961         netif_carrier_off(priv->ndev);
1962
1963         if (cpsw->usage_count <= 1) {
1964                 napi_disable(&cpsw->napi_rx);
1965                 napi_disable(&cpsw->napi_tx);
1966                 cpts_unregister(cpsw->cpts);
1967                 cpsw_intr_disable(cpsw);
1968                 cpdma_ctlr_stop(cpsw->dma);
1969                 cpsw_ale_stop(cpsw->ale);
1970         }
1971         for_each_slave(priv, cpsw_slave_stop, cpsw);
1972
1973         if (cpsw_need_resplit(cpsw))
1974                 cpsw_split_res(ndev);
1975
1976         cpsw->usage_count--;
1977         pm_runtime_put_sync(cpsw->dev);
1978         return 0;
1979 }
1980
1981 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1982                                        struct net_device *ndev)
1983 {
1984         struct cpsw_priv *priv = netdev_priv(ndev);
1985         struct cpsw_common *cpsw = priv->cpsw;
1986         struct cpts *cpts = cpsw->cpts;
1987         struct netdev_queue *txq;
1988         struct cpdma_chan *txch;
1989         int ret, q_idx;
1990
1991         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1992                 cpsw_err(priv, tx_err, "packet pad failed\n");
1993                 ndev->stats.tx_dropped++;
1994                 return NET_XMIT_DROP;
1995         }
1996
1997         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1998             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1999                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2000
2001         q_idx = skb_get_queue_mapping(skb);
2002         if (q_idx >= cpsw->tx_ch_num)
2003                 q_idx = q_idx % cpsw->tx_ch_num;
2004
2005         txch = cpsw->txv[q_idx].ch;
2006         txq = netdev_get_tx_queue(ndev, q_idx);
2007         ret = cpsw_tx_packet_submit(priv, skb, txch);
2008         if (unlikely(ret != 0)) {
2009                 cpsw_err(priv, tx_err, "desc submit failed\n");
2010                 goto fail;
2011         }
2012
2013         /* If there is no more tx desc left free then we need to
2014          * tell the kernel to stop sending us tx frames.
2015          */
2016         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2017                 netif_tx_stop_queue(txq);
2018
2019                 /* Barrier, so that stop_queue visible to other cpus */
2020                 smp_mb__after_atomic();
2021
2022                 if (cpdma_check_free_tx_desc(txch))
2023                         netif_tx_wake_queue(txq);
2024         }
2025
2026         return NETDEV_TX_OK;
2027 fail:
2028         ndev->stats.tx_dropped++;
2029         netif_tx_stop_queue(txq);
2030
2031         /* Barrier, so that stop_queue visible to other cpus */
2032         smp_mb__after_atomic();
2033
2034         if (cpdma_check_free_tx_desc(txch))
2035                 netif_tx_wake_queue(txq);
2036
2037         return NETDEV_TX_BUSY;
2038 }
2039
2040 #if IS_ENABLED(CONFIG_TI_CPTS)
2041
2042 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2043 {
2044         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2045         u32 ts_en, seq_id;
2046
2047         if (!cpts_is_tx_enabled(cpsw->cpts) &&
2048             !cpts_is_rx_enabled(cpsw->cpts)) {
2049                 slave_write(slave, 0, CPSW1_TS_CTL);
2050                 return;
2051         }
2052
2053         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2054         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2055
2056         if (cpts_is_tx_enabled(cpsw->cpts))
2057                 ts_en |= CPSW_V1_TS_TX_EN;
2058
2059         if (cpts_is_rx_enabled(cpsw->cpts))
2060                 ts_en |= CPSW_V1_TS_RX_EN;
2061
2062         slave_write(slave, ts_en, CPSW1_TS_CTL);
2063         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2064 }
2065
2066 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2067 {
2068         struct cpsw_slave *slave;
2069         struct cpsw_common *cpsw = priv->cpsw;
2070         u32 ctrl, mtype;
2071
2072         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2073
2074         ctrl = slave_read(slave, CPSW2_CONTROL);
2075         switch (cpsw->version) {
2076         case CPSW_VERSION_2:
2077                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2078
2079                 if (cpts_is_tx_enabled(cpsw->cpts))
2080                         ctrl |= CTRL_V2_TX_TS_BITS;
2081
2082                 if (cpts_is_rx_enabled(cpsw->cpts))
2083                         ctrl |= CTRL_V2_RX_TS_BITS;
2084                 break;
2085         case CPSW_VERSION_3:
2086         default:
2087                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2088
2089                 if (cpts_is_tx_enabled(cpsw->cpts))
2090                         ctrl |= CTRL_V3_TX_TS_BITS;
2091
2092                 if (cpts_is_rx_enabled(cpsw->cpts))
2093                         ctrl |= CTRL_V3_RX_TS_BITS;
2094                 break;
2095         }
2096
2097         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2098
2099         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2100         slave_write(slave, ctrl, CPSW2_CONTROL);
2101         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2102 }
2103
2104 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2105 {
2106         struct cpsw_priv *priv = netdev_priv(dev);
2107         struct hwtstamp_config cfg;
2108         struct cpsw_common *cpsw = priv->cpsw;
2109         struct cpts *cpts = cpsw->cpts;
2110
2111         if (cpsw->version != CPSW_VERSION_1 &&
2112             cpsw->version != CPSW_VERSION_2 &&
2113             cpsw->version != CPSW_VERSION_3)
2114                 return -EOPNOTSUPP;
2115
2116         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2117                 return -EFAULT;
2118
2119         /* reserved for future extensions */
2120         if (cfg.flags)
2121                 return -EINVAL;
2122
2123         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2124                 return -ERANGE;
2125
2126         switch (cfg.rx_filter) {
2127         case HWTSTAMP_FILTER_NONE:
2128                 cpts_rx_enable(cpts, 0);
2129                 break;
2130         case HWTSTAMP_FILTER_ALL:
2131         case HWTSTAMP_FILTER_NTP_ALL:
2132                 return -ERANGE;
2133         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2134         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2135         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2136                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2137                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2138                 break;
2139         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2140         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2141         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2142         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2143         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2144         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2145         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2146         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2147         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2148                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2149                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2150                 break;
2151         default:
2152                 return -ERANGE;
2153         }
2154
2155         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2156
2157         switch (cpsw->version) {
2158         case CPSW_VERSION_1:
2159                 cpsw_hwtstamp_v1(cpsw);
2160                 break;
2161         case CPSW_VERSION_2:
2162         case CPSW_VERSION_3:
2163                 cpsw_hwtstamp_v2(priv);
2164                 break;
2165         default:
2166                 WARN_ON(1);
2167         }
2168
2169         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2170 }
2171
2172 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2173 {
2174         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2175         struct cpts *cpts = cpsw->cpts;
2176         struct hwtstamp_config cfg;
2177
2178         if (cpsw->version != CPSW_VERSION_1 &&
2179             cpsw->version != CPSW_VERSION_2 &&
2180             cpsw->version != CPSW_VERSION_3)
2181                 return -EOPNOTSUPP;
2182
2183         cfg.flags = 0;
2184         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2185                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2186         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2187                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2188
2189         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2190 }
2191 #else
2192 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2193 {
2194         return -EOPNOTSUPP;
2195 }
2196
2197 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2198 {
2199         return -EOPNOTSUPP;
2200 }
2201 #endif /*CONFIG_TI_CPTS*/
2202
2203 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2204 {
2205         struct cpsw_priv *priv = netdev_priv(dev);
2206         struct cpsw_common *cpsw = priv->cpsw;
2207         int slave_no = cpsw_slave_index(cpsw, priv);
2208
2209         if (!netif_running(dev))
2210                 return -EINVAL;
2211
2212         switch (cmd) {
2213         case SIOCSHWTSTAMP:
2214                 return cpsw_hwtstamp_set(dev, req);
2215         case SIOCGHWTSTAMP:
2216                 return cpsw_hwtstamp_get(dev, req);
2217         }
2218
2219         if (!cpsw->slaves[slave_no].phy)
2220                 return -EOPNOTSUPP;
2221         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2222 }
2223
2224 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2225 {
2226         struct cpsw_priv *priv = netdev_priv(ndev);
2227         struct cpsw_common *cpsw = priv->cpsw;
2228         int ch;
2229
2230         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2231         ndev->stats.tx_errors++;
2232         cpsw_intr_disable(cpsw);
2233         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2234                 cpdma_chan_stop(cpsw->txv[ch].ch);
2235                 cpdma_chan_start(cpsw->txv[ch].ch);
2236         }
2237
2238         cpsw_intr_enable(cpsw);
2239         netif_trans_update(ndev);
2240         netif_tx_wake_all_queues(ndev);
2241 }
2242
2243 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2244 {
2245         struct cpsw_priv *priv = netdev_priv(ndev);
2246         struct sockaddr *addr = (struct sockaddr *)p;
2247         struct cpsw_common *cpsw = priv->cpsw;
2248         int flags = 0;
2249         u16 vid = 0;
2250         int ret;
2251
2252         if (!is_valid_ether_addr(addr->sa_data))
2253                 return -EADDRNOTAVAIL;
2254
2255         ret = pm_runtime_get_sync(cpsw->dev);
2256         if (ret < 0) {
2257                 pm_runtime_put_noidle(cpsw->dev);
2258                 return ret;
2259         }
2260
2261         if (cpsw->data.dual_emac) {
2262                 vid = cpsw->slaves[priv->emac_port].port_vlan;
2263                 flags = ALE_VLAN;
2264         }
2265
2266         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2267                            flags, vid);
2268         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2269                            flags, vid);
2270
2271         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2272         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2273         for_each_slave(priv, cpsw_set_slave_mac, priv);
2274
2275         pm_runtime_put(cpsw->dev);
2276
2277         return 0;
2278 }
2279
2280 #ifdef CONFIG_NET_POLL_CONTROLLER
2281 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2282 {
2283         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2284
2285         cpsw_intr_disable(cpsw);
2286         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2287         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2288         cpsw_intr_enable(cpsw);
2289 }
2290 #endif
2291
2292 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2293                                 unsigned short vid)
2294 {
2295         int ret;
2296         int unreg_mcast_mask = 0;
2297         u32 port_mask;
2298         struct cpsw_common *cpsw = priv->cpsw;
2299
2300         if (cpsw->data.dual_emac) {
2301                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2302
2303                 if (priv->ndev->flags & IFF_ALLMULTI)
2304                         unreg_mcast_mask = port_mask;
2305         } else {
2306                 port_mask = ALE_ALL_PORTS;
2307
2308                 if (priv->ndev->flags & IFF_ALLMULTI)
2309                         unreg_mcast_mask = ALE_ALL_PORTS;
2310                 else
2311                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2312         }
2313
2314         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2315                                 unreg_mcast_mask);
2316         if (ret != 0)
2317                 return ret;
2318
2319         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2320                                  HOST_PORT_NUM, ALE_VLAN, vid);
2321         if (ret != 0)
2322                 goto clean_vid;
2323
2324         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2325                                  port_mask, ALE_VLAN, vid, 0);
2326         if (ret != 0)
2327                 goto clean_vlan_ucast;
2328         return 0;
2329
2330 clean_vlan_ucast:
2331         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2332                            HOST_PORT_NUM, ALE_VLAN, vid);
2333 clean_vid:
2334         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2335         return ret;
2336 }
2337
2338 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2339                                     __be16 proto, u16 vid)
2340 {
2341         struct cpsw_priv *priv = netdev_priv(ndev);
2342         struct cpsw_common *cpsw = priv->cpsw;
2343         int ret;
2344
2345         if (vid == cpsw->data.default_vlan)
2346                 return 0;
2347
2348         ret = pm_runtime_get_sync(cpsw->dev);
2349         if (ret < 0) {
2350                 pm_runtime_put_noidle(cpsw->dev);
2351                 return ret;
2352         }
2353
2354         if (cpsw->data.dual_emac) {
2355                 /* In dual EMAC, reserved VLAN id should not be used for
2356                  * creating VLAN interfaces as this can break the dual
2357                  * EMAC port separation
2358                  */
2359                 int i;
2360
2361                 for (i = 0; i < cpsw->data.slaves; i++) {
2362                         if (vid == cpsw->slaves[i].port_vlan) {
2363                                 ret = -EINVAL;
2364                                 goto err;
2365                         }
2366                 }
2367         }
2368
2369         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2370         ret = cpsw_add_vlan_ale_entry(priv, vid);
2371 err:
2372         pm_runtime_put(cpsw->dev);
2373         return ret;
2374 }
2375
2376 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2377                                      __be16 proto, u16 vid)
2378 {
2379         struct cpsw_priv *priv = netdev_priv(ndev);
2380         struct cpsw_common *cpsw = priv->cpsw;
2381         int ret;
2382
2383         if (vid == cpsw->data.default_vlan)
2384                 return 0;
2385
2386         ret = pm_runtime_get_sync(cpsw->dev);
2387         if (ret < 0) {
2388                 pm_runtime_put_noidle(cpsw->dev);
2389                 return ret;
2390         }
2391
2392         if (cpsw->data.dual_emac) {
2393                 int i;
2394
2395                 for (i = 0; i < cpsw->data.slaves; i++) {
2396                         if (vid == cpsw->slaves[i].port_vlan)
2397                                 goto err;
2398                 }
2399         }
2400
2401         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2402         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2403         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2404                                   HOST_PORT_NUM, ALE_VLAN, vid);
2405         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2406                                   0, ALE_VLAN, vid);
2407 err:
2408         pm_runtime_put(cpsw->dev);
2409         return ret;
2410 }
2411
2412 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2413 {
2414         struct cpsw_priv *priv = netdev_priv(ndev);
2415         struct cpsw_common *cpsw = priv->cpsw;
2416         struct cpsw_slave *slave;
2417         u32 min_rate;
2418         u32 ch_rate;
2419         int i, ret;
2420
2421         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2422         if (ch_rate == rate)
2423                 return 0;
2424
2425         ch_rate = rate * 1000;
2426         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2427         if ((ch_rate < min_rate && ch_rate)) {
2428                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2429                         min_rate);
2430                 return -EINVAL;
2431         }
2432
2433         if (rate > cpsw->speed) {
2434                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2435                 return -EINVAL;
2436         }
2437
2438         ret = pm_runtime_get_sync(cpsw->dev);
2439         if (ret < 0) {
2440                 pm_runtime_put_noidle(cpsw->dev);
2441                 return ret;
2442         }
2443
2444         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2445         pm_runtime_put(cpsw->dev);
2446
2447         if (ret)
2448                 return ret;
2449
2450         /* update rates for slaves tx queues */
2451         for (i = 0; i < cpsw->data.slaves; i++) {
2452                 slave = &cpsw->slaves[i];
2453                 if (!slave->ndev)
2454                         continue;
2455
2456                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2457         }
2458
2459         cpsw_split_res(ndev);
2460         return ret;
2461 }
2462
2463 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2464 {
2465         struct tc_mqprio_qopt_offload *mqprio = type_data;
2466         struct cpsw_priv *priv = netdev_priv(ndev);
2467         struct cpsw_common *cpsw = priv->cpsw;
2468         int fifo, num_tc, count, offset;
2469         struct cpsw_slave *slave;
2470         u32 tx_prio_map = 0;
2471         int i, tc, ret;
2472
2473         num_tc = mqprio->qopt.num_tc;
2474         if (num_tc > CPSW_TC_NUM)
2475                 return -EINVAL;
2476
2477         if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2478                 return -EINVAL;
2479
2480         ret = pm_runtime_get_sync(cpsw->dev);
2481         if (ret < 0) {
2482                 pm_runtime_put_noidle(cpsw->dev);
2483                 return ret;
2484         }
2485
2486         if (num_tc) {
2487                 for (i = 0; i < 8; i++) {
2488                         tc = mqprio->qopt.prio_tc_map[i];
2489                         fifo = cpsw_tc_to_fifo(tc, num_tc);
2490                         tx_prio_map |= fifo << (4 * i);
2491                 }
2492
2493                 netdev_set_num_tc(ndev, num_tc);
2494                 for (i = 0; i < num_tc; i++) {
2495                         count = mqprio->qopt.count[i];
2496                         offset = mqprio->qopt.offset[i];
2497                         netdev_set_tc_queue(ndev, i, count, offset);
2498                 }
2499         }
2500
2501         if (!mqprio->qopt.hw) {
2502                 /* restore default configuration */
2503                 netdev_reset_tc(ndev);
2504                 tx_prio_map = TX_PRIORITY_MAPPING;
2505         }
2506
2507         priv->mqprio_hw = mqprio->qopt.hw;
2508
2509         offset = cpsw->version == CPSW_VERSION_1 ?
2510                  CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2511
2512         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2513         slave_write(slave, tx_prio_map, offset);
2514
2515         pm_runtime_put_sync(cpsw->dev);
2516
2517         return 0;
2518 }
2519
2520 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2521                              void *type_data)
2522 {
2523         switch (type) {
2524         case TC_SETUP_QDISC_CBS:
2525                 return cpsw_set_cbs(ndev, type_data);
2526
2527         case TC_SETUP_QDISC_MQPRIO:
2528                 return cpsw_set_mqprio(ndev, type_data);
2529
2530         default:
2531                 return -EOPNOTSUPP;
2532         }
2533 }
2534
2535 static const struct net_device_ops cpsw_netdev_ops = {
2536         .ndo_open               = cpsw_ndo_open,
2537         .ndo_stop               = cpsw_ndo_stop,
2538         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2539         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2540         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2541         .ndo_validate_addr      = eth_validate_addr,
2542         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2543         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2544         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2545 #ifdef CONFIG_NET_POLL_CONTROLLER
2546         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2547 #endif
2548         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2549         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2550         .ndo_setup_tc           = cpsw_ndo_setup_tc,
2551 };
2552
2553 static int cpsw_get_regs_len(struct net_device *ndev)
2554 {
2555         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2556
2557         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2558 }
2559
2560 static void cpsw_get_regs(struct net_device *ndev,
2561                           struct ethtool_regs *regs, void *p)
2562 {
2563         u32 *reg = p;
2564         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2565
2566         /* update CPSW IP version */
2567         regs->version = cpsw->version;
2568
2569         cpsw_ale_dump(cpsw->ale, reg);
2570 }
2571
2572 static void cpsw_get_drvinfo(struct net_device *ndev,
2573                              struct ethtool_drvinfo *info)
2574 {
2575         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2576         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2577
2578         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2579         strlcpy(info->version, "1.0", sizeof(info->version));
2580         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2581 }
2582
2583 static u32 cpsw_get_msglevel(struct net_device *ndev)
2584 {
2585         struct cpsw_priv *priv = netdev_priv(ndev);
2586         return priv->msg_enable;
2587 }
2588
2589 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2590 {
2591         struct cpsw_priv *priv = netdev_priv(ndev);
2592         priv->msg_enable = value;
2593 }
2594
2595 #if IS_ENABLED(CONFIG_TI_CPTS)
2596 static int cpsw_get_ts_info(struct net_device *ndev,
2597                             struct ethtool_ts_info *info)
2598 {
2599         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2600
2601         info->so_timestamping =
2602                 SOF_TIMESTAMPING_TX_HARDWARE |
2603                 SOF_TIMESTAMPING_TX_SOFTWARE |
2604                 SOF_TIMESTAMPING_RX_HARDWARE |
2605                 SOF_TIMESTAMPING_RX_SOFTWARE |
2606                 SOF_TIMESTAMPING_SOFTWARE |
2607                 SOF_TIMESTAMPING_RAW_HARDWARE;
2608         info->phc_index = cpsw->cpts->phc_index;
2609         info->tx_types =
2610                 (1 << HWTSTAMP_TX_OFF) |
2611                 (1 << HWTSTAMP_TX_ON);
2612         info->rx_filters =
2613                 (1 << HWTSTAMP_FILTER_NONE) |
2614                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2615                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2616         return 0;
2617 }
2618 #else
2619 static int cpsw_get_ts_info(struct net_device *ndev,
2620                             struct ethtool_ts_info *info)
2621 {
2622         info->so_timestamping =
2623                 SOF_TIMESTAMPING_TX_SOFTWARE |
2624                 SOF_TIMESTAMPING_RX_SOFTWARE |
2625                 SOF_TIMESTAMPING_SOFTWARE;
2626         info->phc_index = -1;
2627         info->tx_types = 0;
2628         info->rx_filters = 0;
2629         return 0;
2630 }
2631 #endif
2632
2633 static int cpsw_get_link_ksettings(struct net_device *ndev,
2634                                    struct ethtool_link_ksettings *ecmd)
2635 {
2636         struct cpsw_priv *priv = netdev_priv(ndev);
2637         struct cpsw_common *cpsw = priv->cpsw;
2638         int slave_no = cpsw_slave_index(cpsw, priv);
2639
2640         if (!cpsw->slaves[slave_no].phy)
2641                 return -EOPNOTSUPP;
2642
2643         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2644         return 0;
2645 }
2646
2647 static int cpsw_set_link_ksettings(struct net_device *ndev,
2648                                    const struct ethtool_link_ksettings *ecmd)
2649 {
2650         struct cpsw_priv *priv = netdev_priv(ndev);
2651         struct cpsw_common *cpsw = priv->cpsw;
2652         int slave_no = cpsw_slave_index(cpsw, priv);
2653
2654         if (cpsw->slaves[slave_no].phy)
2655                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2656                                                  ecmd);
2657         else
2658                 return -EOPNOTSUPP;
2659 }
2660
2661 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2662 {
2663         struct cpsw_priv *priv = netdev_priv(ndev);
2664         struct cpsw_common *cpsw = priv->cpsw;
2665         int slave_no = cpsw_slave_index(cpsw, priv);
2666
2667         wol->supported = 0;
2668         wol->wolopts = 0;
2669
2670         if (cpsw->slaves[slave_no].phy)
2671                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2672 }
2673
2674 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2675 {
2676         struct cpsw_priv *priv = netdev_priv(ndev);
2677         struct cpsw_common *cpsw = priv->cpsw;
2678         int slave_no = cpsw_slave_index(cpsw, priv);
2679
2680         if (cpsw->slaves[slave_no].phy)
2681                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2682         else
2683                 return -EOPNOTSUPP;
2684 }
2685
2686 static void cpsw_get_pauseparam(struct net_device *ndev,
2687                                 struct ethtool_pauseparam *pause)
2688 {
2689         struct cpsw_priv *priv = netdev_priv(ndev);
2690
2691         pause->autoneg = AUTONEG_DISABLE;
2692         pause->rx_pause = priv->rx_pause ? true : false;
2693         pause->tx_pause = priv->tx_pause ? true : false;
2694 }
2695
2696 static int cpsw_set_pauseparam(struct net_device *ndev,
2697                                struct ethtool_pauseparam *pause)
2698 {
2699         struct cpsw_priv *priv = netdev_priv(ndev);
2700         bool link;
2701
2702         priv->rx_pause = pause->rx_pause ? true : false;
2703         priv->tx_pause = pause->tx_pause ? true : false;
2704
2705         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2706         return 0;
2707 }
2708
2709 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2710 {
2711         struct cpsw_priv *priv = netdev_priv(ndev);
2712         struct cpsw_common *cpsw = priv->cpsw;
2713         int ret;
2714
2715         ret = pm_runtime_get_sync(cpsw->dev);
2716         if (ret < 0) {
2717                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2718                 pm_runtime_put_noidle(cpsw->dev);
2719         }
2720
2721         return ret;
2722 }
2723
2724 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2725 {
2726         struct cpsw_priv *priv = netdev_priv(ndev);
2727         int ret;
2728
2729         ret = pm_runtime_put(priv->cpsw->dev);
2730         if (ret < 0)
2731                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2732 }
2733
2734 static void cpsw_get_channels(struct net_device *ndev,
2735                               struct ethtool_channels *ch)
2736 {
2737         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2738
2739         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2740         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2741         ch->max_combined = 0;
2742         ch->max_other = 0;
2743         ch->other_count = 0;
2744         ch->rx_count = cpsw->rx_ch_num;
2745         ch->tx_count = cpsw->tx_ch_num;
2746         ch->combined_count = 0;
2747 }
2748
2749 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2750                                   struct ethtool_channels *ch)
2751 {
2752         if (cpsw->quirk_irq) {
2753                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2754                 return -EOPNOTSUPP;
2755         }
2756
2757         if (ch->combined_count)
2758                 return -EINVAL;
2759
2760         /* verify we have at least one channel in each direction */
2761         if (!ch->rx_count || !ch->tx_count)
2762                 return -EINVAL;
2763
2764         if (ch->rx_count > cpsw->data.channels ||
2765             ch->tx_count > cpsw->data.channels)
2766                 return -EINVAL;
2767
2768         return 0;
2769 }
2770
2771 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2772 {
2773         struct cpsw_common *cpsw = priv->cpsw;
2774         void (*handler)(void *, int, int);
2775         struct netdev_queue *queue;
2776         struct cpsw_vector *vec;
2777         int ret, *ch, vch;
2778
2779         if (rx) {
2780                 ch = &cpsw->rx_ch_num;
2781                 vec = cpsw->rxv;
2782                 handler = cpsw_rx_handler;
2783         } else {
2784                 ch = &cpsw->tx_ch_num;
2785                 vec = cpsw->txv;
2786                 handler = cpsw_tx_handler;
2787         }
2788
2789         while (*ch < ch_num) {
2790                 vch = rx ? *ch : 7 - *ch;
2791                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2792                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2793                 queue->tx_maxrate = 0;
2794
2795                 if (IS_ERR(vec[*ch].ch))
2796                         return PTR_ERR(vec[*ch].ch);
2797
2798                 if (!vec[*ch].ch)
2799                         return -EINVAL;
2800
2801                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2802                           (rx ? "rx" : "tx"));
2803                 (*ch)++;
2804         }
2805
2806         while (*ch > ch_num) {
2807                 (*ch)--;
2808
2809                 ret = cpdma_chan_destroy(vec[*ch].ch);
2810                 if (ret)
2811                         return ret;
2812
2813                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2814                           (rx ? "rx" : "tx"));
2815         }
2816
2817         return 0;
2818 }
2819
2820 static int cpsw_update_channels(struct cpsw_priv *priv,
2821                                 struct ethtool_channels *ch)
2822 {
2823         int ret;
2824
2825         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2826         if (ret)
2827                 return ret;
2828
2829         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2830         if (ret)
2831                 return ret;
2832
2833         return 0;
2834 }
2835
2836 static void cpsw_suspend_data_pass(struct net_device *ndev)
2837 {
2838         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2839         struct cpsw_slave *slave;
2840         int i;
2841
2842         /* Disable NAPI scheduling */
2843         cpsw_intr_disable(cpsw);
2844
2845         /* Stop all transmit queues for every network device.
2846          * Disable re-using rx descriptors with dormant_on.
2847          */
2848         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2849                 if (!(slave->ndev && netif_running(slave->ndev)))
2850                         continue;
2851
2852                 netif_tx_stop_all_queues(slave->ndev);
2853                 netif_dormant_on(slave->ndev);
2854         }
2855
2856         /* Handle rest of tx packets and stop cpdma channels */
2857         cpdma_ctlr_stop(cpsw->dma);
2858 }
2859
2860 static int cpsw_resume_data_pass(struct net_device *ndev)
2861 {
2862         struct cpsw_priv *priv = netdev_priv(ndev);
2863         struct cpsw_common *cpsw = priv->cpsw;
2864         struct cpsw_slave *slave;
2865         int i, ret;
2866
2867         /* Allow rx packets handling */
2868         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2869                 if (slave->ndev && netif_running(slave->ndev))
2870                         netif_dormant_off(slave->ndev);
2871
2872         /* After this receive is started */
2873         if (cpsw->usage_count) {
2874                 ret = cpsw_fill_rx_channels(priv);
2875                 if (ret)
2876                         return ret;
2877
2878                 cpdma_ctlr_start(cpsw->dma);
2879                 cpsw_intr_enable(cpsw);
2880         }
2881
2882         /* Resume transmit for every affected interface */
2883         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2884                 if (slave->ndev && netif_running(slave->ndev))
2885                         netif_tx_start_all_queues(slave->ndev);
2886
2887         return 0;
2888 }
2889
2890 static int cpsw_set_channels(struct net_device *ndev,
2891                              struct ethtool_channels *chs)
2892 {
2893         struct cpsw_priv *priv = netdev_priv(ndev);
2894         struct cpsw_common *cpsw = priv->cpsw;
2895         struct cpsw_slave *slave;
2896         int i, ret;
2897
2898         ret = cpsw_check_ch_settings(cpsw, chs);
2899         if (ret < 0)
2900                 return ret;
2901
2902         cpsw_suspend_data_pass(ndev);
2903         ret = cpsw_update_channels(priv, chs);
2904         if (ret)
2905                 goto err;
2906
2907         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2908                 if (!(slave->ndev && netif_running(slave->ndev)))
2909                         continue;
2910
2911                 /* Inform stack about new count of queues */
2912                 ret = netif_set_real_num_tx_queues(slave->ndev,
2913                                                    cpsw->tx_ch_num);
2914                 if (ret) {
2915                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2916                         goto err;
2917                 }
2918
2919                 ret = netif_set_real_num_rx_queues(slave->ndev,
2920                                                    cpsw->rx_ch_num);
2921                 if (ret) {
2922                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2923                         goto err;
2924                 }
2925         }
2926
2927         if (cpsw->usage_count)
2928                 cpsw_split_res(ndev);
2929
2930         ret = cpsw_resume_data_pass(ndev);
2931         if (!ret)
2932                 return 0;
2933 err:
2934         dev_err(priv->dev, "cannot update channels number, closing device\n");
2935         dev_close(ndev);
2936         return ret;
2937 }
2938
2939 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2940 {
2941         struct cpsw_priv *priv = netdev_priv(ndev);
2942         struct cpsw_common *cpsw = priv->cpsw;
2943         int slave_no = cpsw_slave_index(cpsw, priv);
2944
2945         if (cpsw->slaves[slave_no].phy)
2946                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2947         else
2948                 return -EOPNOTSUPP;
2949 }
2950
2951 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2952 {
2953         struct cpsw_priv *priv = netdev_priv(ndev);
2954         struct cpsw_common *cpsw = priv->cpsw;
2955         int slave_no = cpsw_slave_index(cpsw, priv);
2956
2957         if (cpsw->slaves[slave_no].phy)
2958                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2959         else
2960                 return -EOPNOTSUPP;
2961 }
2962
2963 static int cpsw_nway_reset(struct net_device *ndev)
2964 {
2965         struct cpsw_priv *priv = netdev_priv(ndev);
2966         struct cpsw_common *cpsw = priv->cpsw;
2967         int slave_no = cpsw_slave_index(cpsw, priv);
2968
2969         if (cpsw->slaves[slave_no].phy)
2970                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2971         else
2972                 return -EOPNOTSUPP;
2973 }
2974
2975 static void cpsw_get_ringparam(struct net_device *ndev,
2976                                struct ethtool_ringparam *ering)
2977 {
2978         struct cpsw_priv *priv = netdev_priv(ndev);
2979         struct cpsw_common *cpsw = priv->cpsw;
2980
2981         /* not supported */
2982         ering->tx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2983         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2984         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2985         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2986 }
2987
2988 static int cpsw_set_ringparam(struct net_device *ndev,
2989                               struct ethtool_ringparam *ering)
2990 {
2991         struct cpsw_priv *priv = netdev_priv(ndev);
2992         struct cpsw_common *cpsw = priv->cpsw;
2993         int ret;
2994
2995         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2996
2997         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2998             ering->rx_pending < CPSW_MAX_QUEUES ||
2999             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3000                 return -EINVAL;
3001
3002         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3003                 return 0;
3004
3005         cpsw_suspend_data_pass(ndev);
3006
3007         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3008
3009         if (cpsw->usage_count)
3010                 cpdma_chan_split_pool(cpsw->dma);
3011
3012         ret = cpsw_resume_data_pass(ndev);
3013         if (!ret)
3014                 return 0;
3015
3016         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3017         dev_close(ndev);
3018         return ret;
3019 }
3020
3021 static const struct ethtool_ops cpsw_ethtool_ops = {
3022         .get_drvinfo    = cpsw_get_drvinfo,
3023         .get_msglevel   = cpsw_get_msglevel,
3024         .set_msglevel   = cpsw_set_msglevel,
3025         .get_link       = ethtool_op_get_link,
3026         .get_ts_info    = cpsw_get_ts_info,
3027         .get_coalesce   = cpsw_get_coalesce,
3028         .set_coalesce   = cpsw_set_coalesce,
3029         .get_sset_count         = cpsw_get_sset_count,
3030         .get_strings            = cpsw_get_strings,
3031         .get_ethtool_stats      = cpsw_get_ethtool_stats,
3032         .get_pauseparam         = cpsw_get_pauseparam,
3033         .set_pauseparam         = cpsw_set_pauseparam,
3034         .get_wol        = cpsw_get_wol,
3035         .set_wol        = cpsw_set_wol,
3036         .get_regs_len   = cpsw_get_regs_len,
3037         .get_regs       = cpsw_get_regs,
3038         .begin          = cpsw_ethtool_op_begin,
3039         .complete       = cpsw_ethtool_op_complete,
3040         .get_channels   = cpsw_get_channels,
3041         .set_channels   = cpsw_set_channels,
3042         .get_link_ksettings     = cpsw_get_link_ksettings,
3043         .set_link_ksettings     = cpsw_set_link_ksettings,
3044         .get_eee        = cpsw_get_eee,
3045         .set_eee        = cpsw_set_eee,
3046         .nway_reset     = cpsw_nway_reset,
3047         .get_ringparam = cpsw_get_ringparam,
3048         .set_ringparam = cpsw_set_ringparam,
3049 };
3050
3051 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3052                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
3053 {
3054         void __iomem            *regs = cpsw->regs;
3055         int                     slave_num = slave->slave_num;
3056         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
3057
3058         slave->data     = data;
3059         slave->regs     = regs + slave_reg_ofs;
3060         slave->sliver   = regs + sliver_reg_ofs;
3061         slave->port_vlan = data->dual_emac_res_vlan;
3062 }
3063
3064 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3065                          struct platform_device *pdev)
3066 {
3067         struct device_node *node = pdev->dev.of_node;
3068         struct device_node *slave_node;
3069         int i = 0, ret;
3070         u32 prop;
3071
3072         if (!node)
3073                 return -EINVAL;
3074
3075         if (of_property_read_u32(node, "slaves", &prop)) {
3076                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3077                 return -EINVAL;
3078         }
3079         data->slaves = prop;
3080
3081         if (of_property_read_u32(node, "active_slave", &prop)) {
3082                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3083                 return -EINVAL;
3084         }
3085         data->active_slave = prop;
3086
3087         data->slave_data = devm_kcalloc(&pdev->dev,
3088                                         data->slaves,
3089                                         sizeof(struct cpsw_slave_data),
3090                                         GFP_KERNEL);
3091         if (!data->slave_data)
3092                 return -ENOMEM;
3093
3094         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3095                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3096                 return -EINVAL;
3097         }
3098         data->channels = prop;
3099
3100         if (of_property_read_u32(node, "ale_entries", &prop)) {
3101                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3102                 return -EINVAL;
3103         }
3104         data->ale_entries = prop;
3105
3106         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3107                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3108                 return -EINVAL;
3109         }
3110         data->bd_ram_size = prop;
3111
3112         if (of_property_read_u32(node, "mac_control", &prop)) {
3113                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3114                 return -EINVAL;
3115         }
3116         data->mac_control = prop;
3117
3118         if (of_property_read_bool(node, "dual_emac"))
3119                 data->dual_emac = 1;
3120
3121         /*
3122          * Populate all the child nodes here...
3123          */
3124         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3125         /* We do not want to force this, as in some cases may not have child */
3126         if (ret)
3127                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3128
3129         for_each_available_child_of_node(node, slave_node) {
3130                 struct cpsw_slave_data *slave_data = data->slave_data + i;
3131                 const void *mac_addr = NULL;
3132                 int lenp;
3133                 const __be32 *parp;
3134
3135                 /* This is no slave child node, continue */
3136                 if (strcmp(slave_node->name, "slave"))
3137                         continue;
3138
3139                 slave_data->phy_node = of_parse_phandle(slave_node,
3140                                                         "phy-handle", 0);
3141                 parp = of_get_property(slave_node, "phy_id", &lenp);
3142                 if (slave_data->phy_node) {
3143                         dev_dbg(&pdev->dev,
3144                                 "slave[%d] using phy-handle=\"%pOF\"\n",
3145                                 i, slave_data->phy_node);
3146                 } else if (of_phy_is_fixed_link(slave_node)) {
3147                         /* In the case of a fixed PHY, the DT node associated
3148                          * to the PHY is the Ethernet MAC DT node.
3149                          */
3150                         ret = of_phy_register_fixed_link(slave_node);
3151                         if (ret) {
3152                                 if (ret != -EPROBE_DEFER)
3153                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3154                                 return ret;
3155                         }
3156                         slave_data->phy_node = of_node_get(slave_node);
3157                 } else if (parp) {
3158                         u32 phyid;
3159                         struct device_node *mdio_node;
3160                         struct platform_device *mdio;
3161
3162                         if (lenp != (sizeof(__be32) * 2)) {
3163                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3164                                 goto no_phy_slave;
3165                         }
3166                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3167                         phyid = be32_to_cpup(parp+1);
3168                         mdio = of_find_device_by_node(mdio_node);
3169                         of_node_put(mdio_node);
3170                         if (!mdio) {
3171                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
3172                                 return -EINVAL;
3173                         }
3174                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3175                                  PHY_ID_FMT, mdio->name, phyid);
3176                         put_device(&mdio->dev);
3177                 } else {
3178                         dev_err(&pdev->dev,
3179                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3180                                 i);
3181                         goto no_phy_slave;
3182                 }
3183                 slave_data->phy_if = of_get_phy_mode(slave_node);
3184                 if (slave_data->phy_if < 0) {
3185                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3186                                 i);
3187                         return slave_data->phy_if;
3188                 }
3189
3190 no_phy_slave:
3191                 mac_addr = of_get_mac_address(slave_node);
3192                 if (mac_addr) {
3193                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3194                 } else {
3195                         ret = ti_cm_get_macid(&pdev->dev, i,
3196                                               slave_data->mac_addr);
3197                         if (ret)
3198                                 return ret;
3199                 }
3200                 if (data->dual_emac) {
3201                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3202                                                  &prop)) {
3203                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3204                                 slave_data->dual_emac_res_vlan = i+1;
3205                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3206                                         slave_data->dual_emac_res_vlan, i);
3207                         } else {
3208                                 slave_data->dual_emac_res_vlan = prop;
3209                         }
3210                 }
3211
3212                 i++;
3213                 if (i == data->slaves)
3214                         break;
3215         }
3216
3217         return 0;
3218 }
3219
3220 static void cpsw_remove_dt(struct platform_device *pdev)
3221 {
3222         struct net_device *ndev = platform_get_drvdata(pdev);
3223         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3224         struct cpsw_platform_data *data = &cpsw->data;
3225         struct device_node *node = pdev->dev.of_node;
3226         struct device_node *slave_node;
3227         int i = 0;
3228
3229         for_each_available_child_of_node(node, slave_node) {
3230                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3231
3232                 if (strcmp(slave_node->name, "slave"))
3233                         continue;
3234
3235                 if (of_phy_is_fixed_link(slave_node))
3236                         of_phy_deregister_fixed_link(slave_node);
3237
3238                 of_node_put(slave_data->phy_node);
3239
3240                 i++;
3241                 if (i == data->slaves)
3242                         break;
3243         }
3244
3245         of_platform_depopulate(&pdev->dev);
3246 }
3247
3248 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3249 {
3250         struct cpsw_common              *cpsw = priv->cpsw;
3251         struct cpsw_platform_data       *data = &cpsw->data;
3252         struct net_device               *ndev;
3253         struct cpsw_priv                *priv_sl2;
3254         int ret = 0;
3255
3256         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3257         if (!ndev) {
3258                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3259                 return -ENOMEM;
3260         }
3261
3262         priv_sl2 = netdev_priv(ndev);
3263         priv_sl2->cpsw = cpsw;
3264         priv_sl2->ndev = ndev;
3265         priv_sl2->dev  = &ndev->dev;
3266         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3267
3268         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3269                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3270                         ETH_ALEN);
3271                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3272                          priv_sl2->mac_addr);
3273         } else {
3274                 eth_random_addr(priv_sl2->mac_addr);
3275                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3276                          priv_sl2->mac_addr);
3277         }
3278         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3279
3280         priv_sl2->emac_port = 1;
3281         cpsw->slaves[1].ndev = ndev;
3282         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3283
3284         ndev->netdev_ops = &cpsw_netdev_ops;
3285         ndev->ethtool_ops = &cpsw_ethtool_ops;
3286
3287         /* register the network device */
3288         SET_NETDEV_DEV(ndev, cpsw->dev);
3289         ret = register_netdev(ndev);
3290         if (ret) {
3291                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3292                 free_netdev(ndev);
3293                 ret = -ENODEV;
3294         }
3295
3296         return ret;
3297 }
3298
3299 static const struct of_device_id cpsw_of_mtable[] = {
3300         { .compatible = "ti,cpsw"},
3301         { .compatible = "ti,am335x-cpsw"},
3302         { .compatible = "ti,am4372-cpsw"},
3303         { .compatible = "ti,dra7-cpsw"},
3304         { /* sentinel */ },
3305 };
3306 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
3307
3308 static const struct soc_device_attribute cpsw_soc_devices[] = {
3309         { .family = "AM33xx", .revision = "ES1.0"},
3310         { /* sentinel */ }
3311 };
3312
3313 static int cpsw_probe(struct platform_device *pdev)
3314 {
3315         struct clk                      *clk;
3316         struct cpsw_platform_data       *data;
3317         struct net_device               *ndev;
3318         struct cpsw_priv                *priv;
3319         struct cpdma_params             dma_params;
3320         struct cpsw_ale_params          ale_params;
3321         void __iomem                    *ss_regs;
3322         void __iomem                    *cpts_regs;
3323         struct resource                 *res, *ss_res;
3324         struct gpio_descs               *mode;
3325         u32 slave_offset, sliver_offset, slave_size;
3326         const struct soc_device_attribute *soc;
3327         struct cpsw_common              *cpsw;
3328         int ret = 0, i, ch;
3329         int irq;
3330
3331         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
3332         if (!cpsw)
3333                 return -ENOMEM;
3334
3335         cpsw->dev = &pdev->dev;
3336
3337         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3338         if (!ndev) {
3339                 dev_err(&pdev->dev, "error allocating net_device\n");
3340                 return -ENOMEM;
3341         }
3342
3343         platform_set_drvdata(pdev, ndev);
3344         priv = netdev_priv(ndev);
3345         priv->cpsw = cpsw;
3346         priv->ndev = ndev;
3347         priv->dev  = &ndev->dev;
3348         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3349         cpsw->rx_packet_max = max(rx_packet_max, 128);
3350
3351         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3352         if (IS_ERR(mode)) {
3353                 ret = PTR_ERR(mode);
3354                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
3355                 goto clean_ndev_ret;
3356         }
3357
3358         /*
3359          * This may be required here for child devices.
3360          */
3361         pm_runtime_enable(&pdev->dev);
3362
3363         /* Select default pin state */
3364         pinctrl_pm_select_default_state(&pdev->dev);
3365
3366         /* Need to enable clocks with runtime PM api to access module
3367          * registers
3368          */
3369         ret = pm_runtime_get_sync(&pdev->dev);
3370         if (ret < 0) {
3371                 pm_runtime_put_noidle(&pdev->dev);
3372                 goto clean_runtime_disable_ret;
3373         }
3374
3375         ret = cpsw_probe_dt(&cpsw->data, pdev);
3376         if (ret)
3377                 goto clean_dt_ret;
3378
3379         data = &cpsw->data;
3380         cpsw->rx_ch_num = 1;
3381         cpsw->tx_ch_num = 1;
3382
3383         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3384                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3385                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3386         } else {
3387                 eth_random_addr(priv->mac_addr);
3388                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3389         }
3390
3391         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3392
3393         cpsw->slaves = devm_kcalloc(&pdev->dev,
3394                                     data->slaves, sizeof(struct cpsw_slave),
3395                                     GFP_KERNEL);
3396         if (!cpsw->slaves) {
3397                 ret = -ENOMEM;
3398                 goto clean_dt_ret;
3399         }
3400         for (i = 0; i < data->slaves; i++)
3401                 cpsw->slaves[i].slave_num = i;
3402
3403         cpsw->slaves[0].ndev = ndev;
3404         priv->emac_port = 0;
3405
3406         clk = devm_clk_get(&pdev->dev, "fck");
3407         if (IS_ERR(clk)) {
3408                 dev_err(priv->dev, "fck is not found\n");
3409                 ret = -ENODEV;
3410                 goto clean_dt_ret;
3411         }
3412         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3413
3414         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3415         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
3416         if (IS_ERR(ss_regs)) {
3417                 ret = PTR_ERR(ss_regs);
3418                 goto clean_dt_ret;
3419         }
3420         cpsw->regs = ss_regs;
3421
3422         cpsw->version = readl(&cpsw->regs->id_ver);
3423
3424         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3425         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3426         if (IS_ERR(cpsw->wr_regs)) {
3427                 ret = PTR_ERR(cpsw->wr_regs);
3428                 goto clean_dt_ret;
3429         }
3430
3431         memset(&dma_params, 0, sizeof(dma_params));
3432         memset(&ale_params, 0, sizeof(ale_params));
3433
3434         switch (cpsw->version) {
3435         case CPSW_VERSION_1:
3436                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3437                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3438                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3439                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3440                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3441                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3442                 slave_offset         = CPSW1_SLAVE_OFFSET;
3443                 slave_size           = CPSW1_SLAVE_SIZE;
3444                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3445                 dma_params.desc_mem_phys = 0;
3446                 break;
3447         case CPSW_VERSION_2:
3448         case CPSW_VERSION_3:
3449         case CPSW_VERSION_4:
3450                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3451                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3452                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3453                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3454                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3455                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3456                 slave_offset         = CPSW2_SLAVE_OFFSET;
3457                 slave_size           = CPSW2_SLAVE_SIZE;
3458                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3459                 dma_params.desc_mem_phys =
3460                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3461                 break;
3462         default:
3463                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3464                 ret = -ENODEV;
3465                 goto clean_dt_ret;
3466         }
3467         for (i = 0; i < cpsw->data.slaves; i++) {
3468                 struct cpsw_slave *slave = &cpsw->slaves[i];
3469
3470                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3471                 slave_offset  += slave_size;
3472                 sliver_offset += SLIVER_SIZE;
3473         }
3474
3475         dma_params.dev          = &pdev->dev;
3476         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3477         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3478         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3479         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3480         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3481
3482         dma_params.num_chan             = data->channels;
3483         dma_params.has_soft_reset       = true;
3484         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3485         dma_params.desc_mem_size        = data->bd_ram_size;
3486         dma_params.desc_align           = 16;
3487         dma_params.has_ext_regs         = true;
3488         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3489         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3490         dma_params.descs_pool_size      = descs_pool_size;
3491
3492         cpsw->dma = cpdma_ctlr_create(&dma_params);
3493         if (!cpsw->dma) {
3494                 dev_err(priv->dev, "error initializing dma\n");
3495                 ret = -ENOMEM;
3496                 goto clean_dt_ret;
3497         }
3498
3499         soc = soc_device_match(cpsw_soc_devices);
3500         if (soc)
3501                 cpsw->quirk_irq = 1;
3502
3503         ch = cpsw->quirk_irq ? 0 : 7;
3504         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
3505         if (IS_ERR(cpsw->txv[0].ch)) {
3506                 dev_err(priv->dev, "error initializing tx dma channel\n");
3507                 ret = PTR_ERR(cpsw->txv[0].ch);
3508                 goto clean_dma_ret;
3509         }
3510
3511         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3512         if (IS_ERR(cpsw->rxv[0].ch)) {
3513                 dev_err(priv->dev, "error initializing rx dma channel\n");
3514                 ret = PTR_ERR(cpsw->rxv[0].ch);
3515                 goto clean_dma_ret;
3516         }
3517
3518         ale_params.dev                  = &pdev->dev;
3519         ale_params.ale_ageout           = ale_ageout;
3520         ale_params.ale_entries          = data->ale_entries;
3521         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3522
3523         cpsw->ale = cpsw_ale_create(&ale_params);
3524         if (!cpsw->ale) {
3525                 dev_err(priv->dev, "error initializing ale engine\n");
3526                 ret = -ENODEV;
3527                 goto clean_dma_ret;
3528         }
3529
3530         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3531         if (IS_ERR(cpsw->cpts)) {
3532                 ret = PTR_ERR(cpsw->cpts);
3533                 goto clean_dma_ret;
3534         }
3535
3536         ndev->irq = platform_get_irq(pdev, 1);
3537         if (ndev->irq < 0) {
3538                 dev_err(priv->dev, "error getting irq resource\n");
3539                 ret = ndev->irq;
3540                 goto clean_dma_ret;
3541         }
3542
3543         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3544
3545         ndev->netdev_ops = &cpsw_netdev_ops;
3546         ndev->ethtool_ops = &cpsw_ethtool_ops;
3547         netif_napi_add(ndev, &cpsw->napi_rx,
3548                        cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3549                        CPSW_POLL_WEIGHT);
3550         netif_tx_napi_add(ndev, &cpsw->napi_tx,
3551                           cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3552                           CPSW_POLL_WEIGHT);
3553         cpsw_split_res(ndev);
3554
3555         /* register the network device */
3556         SET_NETDEV_DEV(ndev, &pdev->dev);
3557         ret = register_netdev(ndev);
3558         if (ret) {
3559                 dev_err(priv->dev, "error registering net device\n");
3560                 ret = -ENODEV;
3561                 goto clean_dma_ret;
3562         }
3563
3564         if (cpsw->data.dual_emac) {
3565                 ret = cpsw_probe_dual_emac(priv);
3566                 if (ret) {
3567                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3568                         goto clean_unregister_netdev_ret;
3569                 }
3570         }
3571
3572         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3573          * MISC IRQs which are always kept disabled with this driver so
3574          * we will not request them.
3575          *
3576          * If anyone wants to implement support for those, make sure to
3577          * first request and append them to irqs_table array.
3578          */
3579
3580         /* RX IRQ */
3581         irq = platform_get_irq(pdev, 1);
3582         if (irq < 0) {
3583                 ret = irq;
3584                 goto clean_dma_ret;
3585         }
3586
3587         cpsw->irqs_table[0] = irq;
3588         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3589                                0, dev_name(&pdev->dev), cpsw);
3590         if (ret < 0) {
3591                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3592                 goto clean_dma_ret;
3593         }
3594
3595         /* TX IRQ */
3596         irq = platform_get_irq(pdev, 2);
3597         if (irq < 0) {
3598                 ret = irq;
3599                 goto clean_dma_ret;
3600         }
3601
3602         cpsw->irqs_table[1] = irq;
3603         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3604                                0, dev_name(&pdev->dev), cpsw);
3605         if (ret < 0) {
3606                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3607                 goto clean_dma_ret;
3608         }
3609
3610         cpsw_notice(priv, probe,
3611                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3612                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3613
3614         pm_runtime_put(&pdev->dev);
3615
3616         return 0;
3617
3618 clean_unregister_netdev_ret:
3619         unregister_netdev(ndev);
3620 clean_dma_ret:
3621         cpdma_ctlr_destroy(cpsw->dma);
3622 clean_dt_ret:
3623         cpsw_remove_dt(pdev);
3624         pm_runtime_put_sync(&pdev->dev);
3625 clean_runtime_disable_ret:
3626         pm_runtime_disable(&pdev->dev);
3627 clean_ndev_ret:
3628         free_netdev(priv->ndev);
3629         return ret;
3630 }
3631
3632 static int cpsw_remove(struct platform_device *pdev)
3633 {
3634         struct net_device *ndev = platform_get_drvdata(pdev);
3635         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3636         int ret;
3637
3638         ret = pm_runtime_get_sync(&pdev->dev);
3639         if (ret < 0) {
3640                 pm_runtime_put_noidle(&pdev->dev);
3641                 return ret;
3642         }
3643
3644         if (cpsw->data.dual_emac)
3645                 unregister_netdev(cpsw->slaves[1].ndev);
3646         unregister_netdev(ndev);
3647
3648         cpts_release(cpsw->cpts);
3649         cpdma_ctlr_destroy(cpsw->dma);
3650         cpsw_remove_dt(pdev);
3651         pm_runtime_put_sync(&pdev->dev);
3652         pm_runtime_disable(&pdev->dev);
3653         if (cpsw->data.dual_emac)
3654                 free_netdev(cpsw->slaves[1].ndev);
3655         free_netdev(ndev);
3656         return 0;
3657 }
3658
3659 #ifdef CONFIG_PM_SLEEP
3660 static int cpsw_suspend(struct device *dev)
3661 {
3662         struct platform_device  *pdev = to_platform_device(dev);
3663         struct net_device       *ndev = platform_get_drvdata(pdev);
3664         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3665
3666         if (cpsw->data.dual_emac) {
3667                 int i;
3668
3669                 for (i = 0; i < cpsw->data.slaves; i++) {
3670                         if (netif_running(cpsw->slaves[i].ndev))
3671                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3672                 }
3673         } else {
3674                 if (netif_running(ndev))
3675                         cpsw_ndo_stop(ndev);
3676         }
3677
3678         /* Select sleep pin state */
3679         pinctrl_pm_select_sleep_state(dev);
3680
3681         return 0;
3682 }
3683
3684 static int cpsw_resume(struct device *dev)
3685 {
3686         struct platform_device  *pdev = to_platform_device(dev);
3687         struct net_device       *ndev = platform_get_drvdata(pdev);
3688         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3689
3690         /* Select default pin state */
3691         pinctrl_pm_select_default_state(dev);
3692
3693         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3694         rtnl_lock();
3695         if (cpsw->data.dual_emac) {
3696                 int i;
3697
3698                 for (i = 0; i < cpsw->data.slaves; i++) {
3699                         if (netif_running(cpsw->slaves[i].ndev))
3700                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3701                 }
3702         } else {
3703                 if (netif_running(ndev))
3704                         cpsw_ndo_open(ndev);
3705         }
3706         rtnl_unlock();
3707
3708         return 0;
3709 }
3710 #endif
3711
3712 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3713
3714 static struct platform_driver cpsw_driver = {
3715         .driver = {
3716                 .name    = "cpsw",
3717                 .pm      = &cpsw_pm_ops,
3718                 .of_match_table = cpsw_of_mtable,
3719         },
3720         .probe = cpsw_probe,
3721         .remove = cpsw_remove,
3722 };
3723
3724 module_platform_driver(cpsw_driver);
3725
3726 MODULE_LICENSE("GPL");
3727 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3728 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3729 MODULE_DESCRIPTION("TI CPSW Ethernet driver");