2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x01234567
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
147 #define CPSW_MAX_QUEUES 8
149 static int debug_level;
150 module_param(debug_level, int, 0);
151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
153 static int ale_ageout = 10;
154 module_param(ale_ageout, int, 0);
155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
158 module_param(rx_packet_max, int, 0);
159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
161 struct cpsw_wr_regs {
181 struct cpsw_ss_regs {
198 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
199 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
200 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
201 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
202 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
203 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
204 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
205 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
208 #define CPSW2_CONTROL 0x00 /* Control Register */
209 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
210 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
211 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
212 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
213 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
216 /* CPSW_PORT_V1 and V2 */
217 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
218 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
219 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
221 /* CPSW_PORT_V2 only */
222 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
231 /* Bit definitions for the CPSW2_CONTROL register */
232 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
233 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
234 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
235 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
236 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
237 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
238 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
239 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
240 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
241 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
242 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
243 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
244 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
245 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
246 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
247 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
248 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
250 #define CTRL_V2_TS_BITS \
251 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
252 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
255 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
256 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
259 #define CTRL_V3_TS_BITS \
260 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
265 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
266 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
269 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
270 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
271 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
272 #define TS_MSG_TYPE_EN_MASK (0xffff)
274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
277 /* Bit definitions for the CPSW1_TS_CTL register */
278 #define CPSW_V1_TS_RX_EN BIT(0)
279 #define CPSW_V1_TS_TX_EN BIT(4)
280 #define CPSW_V1_MSG_TYPE_OFS 16
282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
283 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
285 struct cpsw_host_regs {
291 u32 cpdma_tx_pri_map;
292 u32 cpdma_rx_chan_map;
295 struct cpsw_sliver_regs {
308 struct cpsw_hw_stats {
310 u32 rxbroadcastframes;
311 u32 rxmulticastframes;
314 u32 rxaligncodeerrors;
315 u32 rxoversizedframes;
317 u32 rxundersizedframes;
322 u32 txbroadcastframes;
323 u32 txmulticastframes;
325 u32 txdeferredframes;
326 u32 txcollisionframes;
327 u32 txsinglecollframes;
328 u32 txmultcollframes;
329 u32 txexcessivecollisions;
330 u32 txlatecollisions;
332 u32 txcarriersenseerrors;
335 u32 octetframes65t127;
336 u32 octetframes128t255;
337 u32 octetframes256t511;
338 u32 octetframes512t1023;
339 u32 octetframes1024tup;
348 struct cpsw_sliver_regs __iomem *sliver;
351 struct cpsw_slave_data *data;
352 struct phy_device *phy;
353 struct net_device *ndev;
358 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
360 return __raw_readl(slave->regs + offset);
363 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
365 __raw_writel(val, slave->regs + offset);
370 struct cpsw_platform_data data;
371 struct napi_struct napi_rx;
372 struct napi_struct napi_tx;
373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
381 struct cpsw_slave *slaves;
382 struct cpdma_ctlr *dma;
383 struct cpdma_chan *txch[CPSW_MAX_QUEUES];
384 struct cpdma_chan *rxch[CPSW_MAX_QUEUES];
385 struct cpsw_ale *ale;
387 bool rx_irq_disabled;
388 bool tx_irq_disabled;
389 u32 irqs_table[IRQ_NUM];
391 int rx_ch_num, tx_ch_num;
395 struct net_device *ndev;
398 u8 mac_addr[ETH_ALEN];
402 struct cpsw_common *cpsw;
406 char stat_string[ETH_GSTRING_LEN];
418 #define CPSW_STAT(m) CPSW_STATS, \
419 sizeof(((struct cpsw_hw_stats *)0)->m), \
420 offsetof(struct cpsw_hw_stats, m)
421 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
422 sizeof(((struct cpdma_chan_stats *)0)->m), \
423 offsetof(struct cpdma_chan_stats, m)
424 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
425 sizeof(((struct cpdma_chan_stats *)0)->m), \
426 offsetof(struct cpdma_chan_stats, m)
428 static const struct cpsw_stats cpsw_gstrings_stats[] = {
429 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
430 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
431 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
432 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
433 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
434 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
435 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
436 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
437 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
438 { "Rx Fragments", CPSW_STAT(rxfragments) },
439 { "Rx Octets", CPSW_STAT(rxoctets) },
440 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
441 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
442 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
443 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
444 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
445 { "Collisions", CPSW_STAT(txcollisionframes) },
446 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
447 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
448 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
449 { "Late Collisions", CPSW_STAT(txlatecollisions) },
450 { "Tx Underrun", CPSW_STAT(txunderrun) },
451 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
452 { "Tx Octets", CPSW_STAT(txoctets) },
453 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
454 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
455 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
456 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
457 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
458 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
459 { "Net Octets", CPSW_STAT(netoctets) },
460 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
461 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
462 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
465 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
466 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
467 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
468 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
469 { "misqueued", CPDMA_RX_STAT(misqueued) },
470 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
471 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
472 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
473 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
474 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
475 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
476 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
477 { "requeue", CPDMA_RX_STAT(requeue) },
478 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
481 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
482 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
484 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
485 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
486 #define for_each_slave(priv, func, arg...) \
488 struct cpsw_slave *slave; \
489 struct cpsw_common *cpsw = (priv)->cpsw; \
491 if (cpsw->data.dual_emac) \
492 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
494 for (n = cpsw->data.slaves, \
495 slave = cpsw->slaves; \
497 (func)(slave++, ##arg); \
500 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
502 if (!cpsw->data.dual_emac) \
504 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
505 ndev = cpsw->slaves[0].ndev; \
507 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
508 ndev = cpsw->slaves[1].ndev; \
512 #define cpsw_add_mcast(cpsw, priv, addr) \
514 if (cpsw->data.dual_emac) { \
515 struct cpsw_slave *slave = cpsw->slaves + \
517 int slave_port = cpsw_get_slave_port( \
519 cpsw_ale_add_mcast(cpsw->ale, addr, \
520 1 << slave_port | ALE_PORT_HOST, \
521 ALE_VLAN, slave->port_vlan, 0); \
523 cpsw_ale_add_mcast(cpsw->ale, addr, \
529 static inline int cpsw_get_slave_port(u32 slave_num)
531 return slave_num + 1;
534 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
536 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
537 struct cpsw_ale *ale = cpsw->ale;
540 if (cpsw->data.dual_emac) {
543 /* Enabling promiscuous mode for one interface will be
544 * common for both the interface as the interface shares
545 * the same hardware resource.
547 for (i = 0; i < cpsw->data.slaves; i++)
548 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
551 if (!enable && flag) {
553 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
558 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
560 dev_dbg(&ndev->dev, "promiscuity enabled\n");
563 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
564 dev_dbg(&ndev->dev, "promiscuity disabled\n");
568 unsigned long timeout = jiffies + HZ;
570 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
571 for (i = 0; i <= cpsw->data.slaves; i++) {
572 cpsw_ale_control_set(ale, i,
573 ALE_PORT_NOLEARN, 1);
574 cpsw_ale_control_set(ale, i,
575 ALE_PORT_NO_SA_UPDATE, 1);
578 /* Clear All Untouched entries */
579 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
582 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
584 } while (time_after(timeout, jiffies));
585 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
587 /* Clear all mcast from ALE */
588 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
590 /* Flood All Unicast Packets to Host port */
591 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
592 dev_dbg(&ndev->dev, "promiscuity enabled\n");
594 /* Don't Flood All Unicast Packets to Host port */
595 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
597 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
598 for (i = 0; i <= cpsw->data.slaves; i++) {
599 cpsw_ale_control_set(ale, i,
600 ALE_PORT_NOLEARN, 0);
601 cpsw_ale_control_set(ale, i,
602 ALE_PORT_NO_SA_UPDATE, 0);
604 dev_dbg(&ndev->dev, "promiscuity disabled\n");
609 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
611 struct cpsw_priv *priv = netdev_priv(ndev);
612 struct cpsw_common *cpsw = priv->cpsw;
615 if (cpsw->data.dual_emac)
616 vid = cpsw->slaves[priv->emac_port].port_vlan;
618 vid = cpsw->data.default_vlan;
620 if (ndev->flags & IFF_PROMISC) {
621 /* Enable promiscuous mode */
622 cpsw_set_promiscious(ndev, true);
623 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
626 /* Disable promiscuous mode */
627 cpsw_set_promiscious(ndev, false);
630 /* Restore allmulti on vlans if necessary */
631 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
633 /* Clear all mcast from ALE */
634 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
636 if (!netdev_mc_empty(ndev)) {
637 struct netdev_hw_addr *ha;
639 /* program multicast address list into ALE register */
640 netdev_for_each_mc_addr(ha, ndev) {
641 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
646 static void cpsw_intr_enable(struct cpsw_common *cpsw)
648 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
649 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
651 cpdma_ctlr_int_ctrl(cpsw->dma, true);
655 static void cpsw_intr_disable(struct cpsw_common *cpsw)
657 __raw_writel(0, &cpsw->wr_regs->tx_en);
658 __raw_writel(0, &cpsw->wr_regs->rx_en);
660 cpdma_ctlr_int_ctrl(cpsw->dma, false);
664 static void cpsw_tx_handler(void *token, int len, int status)
666 struct netdev_queue *txq;
667 struct sk_buff *skb = token;
668 struct net_device *ndev = skb->dev;
669 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
671 /* Check whether the queue is stopped due to stalled tx dma, if the
672 * queue is stopped then start the queue as we have free desc for tx
674 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
675 if (unlikely(netif_tx_queue_stopped(txq)))
676 netif_tx_wake_queue(txq);
678 cpts_tx_timestamp(cpsw->cpts, skb);
679 ndev->stats.tx_packets++;
680 ndev->stats.tx_bytes += len;
681 dev_kfree_skb_any(skb);
684 static void cpsw_rx_handler(void *token, int len, int status)
686 struct cpdma_chan *ch;
687 struct sk_buff *skb = token;
688 struct sk_buff *new_skb;
689 struct net_device *ndev = skb->dev;
691 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
693 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
695 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
696 bool ndev_status = false;
697 struct cpsw_slave *slave = cpsw->slaves;
700 if (cpsw->data.dual_emac) {
701 /* In dual emac mode check for all interfaces */
702 for (n = cpsw->data.slaves; n; n--, slave++)
703 if (netif_running(slave->ndev))
707 if (ndev_status && (status >= 0)) {
708 /* The packet received is for the interface which
709 * is already down and the other interface is up
710 * and running, instead of freeing which results
711 * in reducing of the number of rx descriptor in
712 * DMA engine, requeue skb back to cpdma.
718 /* the interface is going down, skbs are purged */
719 dev_kfree_skb_any(skb);
723 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
725 skb_copy_queue_mapping(new_skb, skb);
727 cpts_rx_timestamp(cpsw->cpts, skb);
728 skb->protocol = eth_type_trans(skb, ndev);
729 netif_receive_skb(skb);
730 ndev->stats.rx_bytes += len;
731 ndev->stats.rx_packets++;
732 kmemleak_not_leak(new_skb);
734 ndev->stats.rx_dropped++;
739 if (netif_dormant(ndev)) {
740 dev_kfree_skb_any(new_skb);
744 ch = cpsw->rxch[skb_get_queue_mapping(new_skb)];
745 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
746 skb_tailroom(new_skb), 0);
747 if (WARN_ON(ret < 0))
748 dev_kfree_skb_any(new_skb);
751 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
753 struct cpsw_common *cpsw = dev_id;
755 writel(0, &cpsw->wr_regs->tx_en);
756 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
758 if (cpsw->quirk_irq) {
759 disable_irq_nosync(cpsw->irqs_table[1]);
760 cpsw->tx_irq_disabled = true;
763 napi_schedule(&cpsw->napi_tx);
767 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
769 struct cpsw_common *cpsw = dev_id;
771 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
772 writel(0, &cpsw->wr_regs->rx_en);
774 if (cpsw->quirk_irq) {
775 disable_irq_nosync(cpsw->irqs_table[0]);
776 cpsw->rx_irq_disabled = true;
779 napi_schedule(&cpsw->napi_rx);
783 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
787 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
789 /* process every unprocessed channel */
790 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
791 for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) {
793 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
800 if (!(ch_map & 0x01))
803 num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx);
806 if (num_tx < budget) {
807 napi_complete(napi_tx);
808 writel(0xff, &cpsw->wr_regs->tx_en);
809 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
810 cpsw->tx_irq_disabled = false;
811 enable_irq(cpsw->irqs_table[1]);
818 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
822 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
824 /* process every unprocessed channel */
825 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
826 for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) {
828 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
835 if (!(ch_map & 0x01))
838 num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx);
841 if (num_rx < budget) {
842 napi_complete(napi_rx);
843 writel(0xff, &cpsw->wr_regs->rx_en);
844 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
845 cpsw->rx_irq_disabled = false;
846 enable_irq(cpsw->irqs_table[0]);
853 static inline void soft_reset(const char *module, void __iomem *reg)
855 unsigned long timeout = jiffies + HZ;
857 __raw_writel(1, reg);
860 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
862 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
865 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
866 ((mac)[2] << 16) | ((mac)[3] << 24))
867 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
869 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
870 struct cpsw_priv *priv)
872 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
873 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
876 static void _cpsw_adjust_link(struct cpsw_slave *slave,
877 struct cpsw_priv *priv, bool *link)
879 struct phy_device *phy = slave->phy;
882 struct cpsw_common *cpsw = priv->cpsw;
887 slave_port = cpsw_get_slave_port(slave->slave_num);
890 mac_control = cpsw->data.mac_control;
892 /* enable forwarding */
893 cpsw_ale_control_set(cpsw->ale, slave_port,
894 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
896 if (phy->speed == 1000)
897 mac_control |= BIT(7); /* GIGABITEN */
899 mac_control |= BIT(0); /* FULLDUPLEXEN */
901 /* set speed_in input in case RMII mode is used in 100Mbps */
902 if (phy->speed == 100)
903 mac_control |= BIT(15);
904 else if (phy->speed == 10)
905 mac_control |= BIT(18); /* In Band mode */
908 mac_control |= BIT(3);
911 mac_control |= BIT(4);
916 /* disable forwarding */
917 cpsw_ale_control_set(cpsw->ale, slave_port,
918 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
921 if (mac_control != slave->mac_control) {
922 phy_print_status(phy);
923 __raw_writel(mac_control, &slave->sliver->mac_control);
926 slave->mac_control = mac_control;
929 static void cpsw_adjust_link(struct net_device *ndev)
931 struct cpsw_priv *priv = netdev_priv(ndev);
934 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
937 netif_carrier_on(ndev);
938 if (netif_running(ndev))
939 netif_tx_wake_all_queues(ndev);
941 netif_carrier_off(ndev);
942 netif_tx_stop_all_queues(ndev);
946 static int cpsw_get_coalesce(struct net_device *ndev,
947 struct ethtool_coalesce *coal)
949 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
951 coal->rx_coalesce_usecs = cpsw->coal_intvl;
955 static int cpsw_set_coalesce(struct net_device *ndev,
956 struct ethtool_coalesce *coal)
958 struct cpsw_priv *priv = netdev_priv(ndev);
960 u32 num_interrupts = 0;
964 struct cpsw_common *cpsw = priv->cpsw;
966 coal_intvl = coal->rx_coalesce_usecs;
968 int_ctrl = readl(&cpsw->wr_regs->int_control);
969 prescale = cpsw->bus_freq_mhz * 4;
971 if (!coal->rx_coalesce_usecs) {
972 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
976 if (coal_intvl < CPSW_CMINTMIN_INTVL)
977 coal_intvl = CPSW_CMINTMIN_INTVL;
979 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
980 /* Interrupt pacer works with 4us Pulse, we can
981 * throttle further by dilating the 4us pulse.
983 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
985 if (addnl_dvdr > 1) {
986 prescale *= addnl_dvdr;
987 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
988 coal_intvl = (CPSW_CMINTMAX_INTVL
992 coal_intvl = CPSW_CMINTMAX_INTVL;
996 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
997 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
998 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1000 int_ctrl |= CPSW_INTPACEEN;
1001 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1002 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1005 writel(int_ctrl, &cpsw->wr_regs->int_control);
1007 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1008 cpsw->coal_intvl = coal_intvl;
1013 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1015 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1019 return (CPSW_STATS_COMMON_LEN +
1020 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1027 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1033 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1034 for (i = 0; i < ch_stats_len; i++) {
1035 line = i % CPSW_STATS_CH_LEN;
1036 snprintf(*p, ETH_GSTRING_LEN,
1037 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1038 i / CPSW_STATS_CH_LEN,
1039 cpsw_gstrings_ch_stats[line].stat_string);
1040 *p += ETH_GSTRING_LEN;
1044 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1046 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1050 switch (stringset) {
1052 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1053 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1055 p += ETH_GSTRING_LEN;
1058 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1059 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1064 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1065 struct ethtool_stats *stats, u64 *data)
1068 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1069 struct cpdma_chan_stats ch_stats;
1072 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1073 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1074 data[l] = readl(cpsw->hw_stats +
1075 cpsw_gstrings_stats[l].stat_offset);
1077 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1078 cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats);
1079 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1080 p = (u8 *)&ch_stats +
1081 cpsw_gstrings_ch_stats[i].stat_offset;
1082 data[l] = *(u32 *)p;
1086 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1087 cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats);
1088 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1089 p = (u8 *)&ch_stats +
1090 cpsw_gstrings_ch_stats[i].stat_offset;
1091 data[l] = *(u32 *)p;
1096 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1099 u32 usage_count = 0;
1101 if (!cpsw->data.dual_emac)
1104 for (i = 0; i < cpsw->data.slaves; i++)
1105 if (cpsw->slaves[i].open_stat)
1111 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1112 struct sk_buff *skb,
1113 struct cpdma_chan *txch)
1115 struct cpsw_common *cpsw = priv->cpsw;
1117 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1118 priv->emac_port + cpsw->data.dual_emac);
1121 static inline void cpsw_add_dual_emac_def_ale_entries(
1122 struct cpsw_priv *priv, struct cpsw_slave *slave,
1125 struct cpsw_common *cpsw = priv->cpsw;
1126 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1128 if (cpsw->version == CPSW_VERSION_1)
1129 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1131 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1132 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1133 port_mask, port_mask, 0);
1134 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1135 port_mask, ALE_VLAN, slave->port_vlan, 0);
1136 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1137 HOST_PORT_NUM, ALE_VLAN |
1138 ALE_SECURE, slave->port_vlan);
1141 static void soft_reset_slave(struct cpsw_slave *slave)
1145 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1146 soft_reset(name, &slave->sliver->soft_reset);
1149 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1152 struct cpsw_common *cpsw = priv->cpsw;
1154 soft_reset_slave(slave);
1156 /* setup priority mapping */
1157 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1159 switch (cpsw->version) {
1160 case CPSW_VERSION_1:
1161 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1163 case CPSW_VERSION_2:
1164 case CPSW_VERSION_3:
1165 case CPSW_VERSION_4:
1166 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1170 /* setup max packet size, and mac address */
1171 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1172 cpsw_set_slave_mac(slave, priv);
1174 slave->mac_control = 0; /* no link yet */
1176 slave_port = cpsw_get_slave_port(slave->slave_num);
1178 if (cpsw->data.dual_emac)
1179 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1181 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1182 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1184 if (slave->data->phy_node) {
1185 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1186 &cpsw_adjust_link, 0, slave->data->phy_if);
1188 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1189 slave->data->phy_node->full_name,
1194 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1195 &cpsw_adjust_link, slave->data->phy_if);
1196 if (IS_ERR(slave->phy)) {
1198 "phy \"%s\" not found on slave %d, err %ld\n",
1199 slave->data->phy_id, slave->slave_num,
1200 PTR_ERR(slave->phy));
1206 phy_attached_info(slave->phy);
1208 phy_start(slave->phy);
1210 /* Configure GMII_SEL register */
1211 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1214 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1216 struct cpsw_common *cpsw = priv->cpsw;
1217 const int vlan = cpsw->data.default_vlan;
1220 int unreg_mcast_mask;
1222 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1225 writel(vlan, &cpsw->host_port_regs->port_vlan);
1227 for (i = 0; i < cpsw->data.slaves; i++)
1228 slave_write(cpsw->slaves + i, vlan, reg);
1230 if (priv->ndev->flags & IFF_ALLMULTI)
1231 unreg_mcast_mask = ALE_ALL_PORTS;
1233 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1235 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1236 ALE_ALL_PORTS, ALE_ALL_PORTS,
1240 static void cpsw_init_host_port(struct cpsw_priv *priv)
1244 struct cpsw_common *cpsw = priv->cpsw;
1246 /* soft reset the controller and initialize ale */
1247 soft_reset("cpsw", &cpsw->regs->soft_reset);
1248 cpsw_ale_start(cpsw->ale);
1250 /* switch to vlan unaware mode */
1251 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1252 CPSW_ALE_VLAN_AWARE);
1253 control_reg = readl(&cpsw->regs->control);
1254 control_reg |= CPSW_VLAN_AWARE;
1255 writel(control_reg, &cpsw->regs->control);
1256 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1257 CPSW_FIFO_NORMAL_MODE;
1258 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1260 /* setup host port priority mapping */
1261 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1262 &cpsw->host_port_regs->cpdma_tx_pri_map);
1263 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1265 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1266 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1268 if (!cpsw->data.dual_emac) {
1269 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1271 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1272 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1276 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1278 struct cpsw_common *cpsw = priv->cpsw;
1279 struct sk_buff *skb;
1283 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1284 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]);
1285 for (i = 0; i < ch_buf_num; i++) {
1286 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1287 cpsw->rx_packet_max,
1290 cpsw_err(priv, ifup, "cannot allocate skb\n");
1294 skb_set_queue_mapping(skb, ch);
1295 ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data,
1296 skb_tailroom(skb), 0);
1298 cpsw_err(priv, ifup,
1299 "cannot submit skb to channel %d rx, error %d\n",
1304 kmemleak_not_leak(skb);
1307 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1314 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1318 slave_port = cpsw_get_slave_port(slave->slave_num);
1322 phy_stop(slave->phy);
1323 phy_disconnect(slave->phy);
1325 cpsw_ale_control_set(cpsw->ale, slave_port,
1326 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1327 soft_reset_slave(slave);
1330 static int cpsw_ndo_open(struct net_device *ndev)
1332 struct cpsw_priv *priv = netdev_priv(ndev);
1333 struct cpsw_common *cpsw = priv->cpsw;
1337 ret = pm_runtime_get_sync(cpsw->dev);
1339 pm_runtime_put_noidle(cpsw->dev);
1343 if (!cpsw_common_res_usage_state(cpsw))
1344 cpsw_intr_disable(cpsw);
1345 netif_carrier_off(ndev);
1347 /* Notify the stack of the actual queue counts. */
1348 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1350 dev_err(priv->dev, "cannot set real number of tx queues\n");
1354 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1356 dev_err(priv->dev, "cannot set real number of rx queues\n");
1360 reg = cpsw->version;
1362 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1363 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1364 CPSW_RTL_VERSION(reg));
1366 /* initialize host and slave ports */
1367 if (!cpsw_common_res_usage_state(cpsw))
1368 cpsw_init_host_port(priv);
1369 for_each_slave(priv, cpsw_slave_open, priv);
1371 /* Add default VLAN */
1372 if (!cpsw->data.dual_emac)
1373 cpsw_add_default_vlan(priv);
1375 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1376 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1378 if (!cpsw_common_res_usage_state(cpsw)) {
1379 /* setup tx dma to fixed prio and zero offset */
1380 cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1);
1381 cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1383 /* disable priority elevation */
1384 __raw_writel(0, &cpsw->regs->ptype);
1386 /* enable statistics collection only on all ports */
1387 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1389 /* Enable internal fifo flow control */
1390 writel(0x7, &cpsw->regs->flow_control);
1392 napi_enable(&cpsw->napi_rx);
1393 napi_enable(&cpsw->napi_tx);
1395 if (cpsw->tx_irq_disabled) {
1396 cpsw->tx_irq_disabled = false;
1397 enable_irq(cpsw->irqs_table[1]);
1400 if (cpsw->rx_irq_disabled) {
1401 cpsw->rx_irq_disabled = false;
1402 enable_irq(cpsw->irqs_table[0]);
1405 ret = cpsw_fill_rx_channels(priv);
1409 if (cpts_register(cpsw->dev, cpsw->cpts,
1410 cpsw->data.cpts_clock_mult,
1411 cpsw->data.cpts_clock_shift))
1412 dev_err(priv->dev, "error registering cpts device\n");
1416 /* Enable Interrupt pacing if configured */
1417 if (cpsw->coal_intvl != 0) {
1418 struct ethtool_coalesce coal;
1420 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1421 cpsw_set_coalesce(ndev, &coal);
1424 cpdma_ctlr_start(cpsw->dma);
1425 cpsw_intr_enable(cpsw);
1427 if (cpsw->data.dual_emac)
1428 cpsw->slaves[priv->emac_port].open_stat = true;
1430 netif_tx_start_all_queues(ndev);
1435 cpdma_ctlr_stop(cpsw->dma);
1436 for_each_slave(priv, cpsw_slave_stop, cpsw);
1437 pm_runtime_put_sync(cpsw->dev);
1438 netif_carrier_off(priv->ndev);
1442 static int cpsw_ndo_stop(struct net_device *ndev)
1444 struct cpsw_priv *priv = netdev_priv(ndev);
1445 struct cpsw_common *cpsw = priv->cpsw;
1447 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1448 netif_tx_stop_all_queues(priv->ndev);
1449 netif_carrier_off(priv->ndev);
1451 if (cpsw_common_res_usage_state(cpsw) <= 1) {
1452 napi_disable(&cpsw->napi_rx);
1453 napi_disable(&cpsw->napi_tx);
1454 cpts_unregister(cpsw->cpts);
1455 cpsw_intr_disable(cpsw);
1456 cpdma_ctlr_stop(cpsw->dma);
1457 cpsw_ale_stop(cpsw->ale);
1459 for_each_slave(priv, cpsw_slave_stop, cpsw);
1460 pm_runtime_put_sync(cpsw->dev);
1461 if (cpsw->data.dual_emac)
1462 cpsw->slaves[priv->emac_port].open_stat = false;
1466 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1467 struct net_device *ndev)
1469 struct cpsw_priv *priv = netdev_priv(ndev);
1470 struct cpsw_common *cpsw = priv->cpsw;
1471 struct netdev_queue *txq;
1472 struct cpdma_chan *txch;
1475 netif_trans_update(ndev);
1477 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1478 cpsw_err(priv, tx_err, "packet pad failed\n");
1479 ndev->stats.tx_dropped++;
1480 return NETDEV_TX_OK;
1483 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1484 cpsw->cpts->tx_enable)
1485 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1487 skb_tx_timestamp(skb);
1489 q_idx = skb_get_queue_mapping(skb);
1490 if (q_idx >= cpsw->tx_ch_num)
1491 q_idx = q_idx % cpsw->tx_ch_num;
1493 txch = cpsw->txch[q_idx];
1494 ret = cpsw_tx_packet_submit(priv, skb, txch);
1495 if (unlikely(ret != 0)) {
1496 cpsw_err(priv, tx_err, "desc submit failed\n");
1500 /* If there is no more tx desc left free then we need to
1501 * tell the kernel to stop sending us tx frames.
1503 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1504 txq = netdev_get_tx_queue(ndev, q_idx);
1505 netif_tx_stop_queue(txq);
1508 return NETDEV_TX_OK;
1510 ndev->stats.tx_dropped++;
1511 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1512 netif_tx_stop_queue(txq);
1513 return NETDEV_TX_BUSY;
1516 #ifdef CONFIG_TI_CPTS
1518 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1520 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1523 if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) {
1524 slave_write(slave, 0, CPSW1_TS_CTL);
1528 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1529 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1531 if (cpsw->cpts->tx_enable)
1532 ts_en |= CPSW_V1_TS_TX_EN;
1534 if (cpsw->cpts->rx_enable)
1535 ts_en |= CPSW_V1_TS_RX_EN;
1537 slave_write(slave, ts_en, CPSW1_TS_CTL);
1538 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1541 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1543 struct cpsw_slave *slave;
1544 struct cpsw_common *cpsw = priv->cpsw;
1547 if (cpsw->data.dual_emac)
1548 slave = &cpsw->slaves[priv->emac_port];
1550 slave = &cpsw->slaves[cpsw->data.active_slave];
1552 ctrl = slave_read(slave, CPSW2_CONTROL);
1553 switch (cpsw->version) {
1554 case CPSW_VERSION_2:
1555 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1557 if (cpsw->cpts->tx_enable)
1558 ctrl |= CTRL_V2_TX_TS_BITS;
1560 if (cpsw->cpts->rx_enable)
1561 ctrl |= CTRL_V2_RX_TS_BITS;
1563 case CPSW_VERSION_3:
1565 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1567 if (cpsw->cpts->tx_enable)
1568 ctrl |= CTRL_V3_TX_TS_BITS;
1570 if (cpsw->cpts->rx_enable)
1571 ctrl |= CTRL_V3_RX_TS_BITS;
1575 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1577 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1578 slave_write(slave, ctrl, CPSW2_CONTROL);
1579 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1582 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1584 struct cpsw_priv *priv = netdev_priv(dev);
1585 struct hwtstamp_config cfg;
1586 struct cpsw_common *cpsw = priv->cpsw;
1587 struct cpts *cpts = cpsw->cpts;
1589 if (cpsw->version != CPSW_VERSION_1 &&
1590 cpsw->version != CPSW_VERSION_2 &&
1591 cpsw->version != CPSW_VERSION_3)
1594 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1597 /* reserved for future extensions */
1601 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1604 switch (cfg.rx_filter) {
1605 case HWTSTAMP_FILTER_NONE:
1606 cpts->rx_enable = 0;
1608 case HWTSTAMP_FILTER_ALL:
1609 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1610 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1611 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1613 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1614 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1616 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1617 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1618 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1619 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1620 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1621 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1622 cpts->rx_enable = 1;
1623 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1629 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1631 switch (cpsw->version) {
1632 case CPSW_VERSION_1:
1633 cpsw_hwtstamp_v1(cpsw);
1635 case CPSW_VERSION_2:
1636 case CPSW_VERSION_3:
1637 cpsw_hwtstamp_v2(priv);
1643 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1646 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1648 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1649 struct cpts *cpts = cpsw->cpts;
1650 struct hwtstamp_config cfg;
1652 if (cpsw->version != CPSW_VERSION_1 &&
1653 cpsw->version != CPSW_VERSION_2 &&
1654 cpsw->version != CPSW_VERSION_3)
1658 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1659 cfg.rx_filter = (cpts->rx_enable ?
1660 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1662 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1665 #endif /*CONFIG_TI_CPTS*/
1667 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1669 struct cpsw_priv *priv = netdev_priv(dev);
1670 struct cpsw_common *cpsw = priv->cpsw;
1671 int slave_no = cpsw_slave_index(cpsw, priv);
1673 if (!netif_running(dev))
1677 #ifdef CONFIG_TI_CPTS
1679 return cpsw_hwtstamp_set(dev, req);
1681 return cpsw_hwtstamp_get(dev, req);
1685 if (!cpsw->slaves[slave_no].phy)
1687 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1690 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1692 struct cpsw_priv *priv = netdev_priv(ndev);
1693 struct cpsw_common *cpsw = priv->cpsw;
1696 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1697 ndev->stats.tx_errors++;
1698 cpsw_intr_disable(cpsw);
1699 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1700 cpdma_chan_stop(cpsw->txch[ch]);
1701 cpdma_chan_start(cpsw->txch[ch]);
1704 cpsw_intr_enable(cpsw);
1707 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1709 struct cpsw_priv *priv = netdev_priv(ndev);
1710 struct sockaddr *addr = (struct sockaddr *)p;
1711 struct cpsw_common *cpsw = priv->cpsw;
1716 if (!is_valid_ether_addr(addr->sa_data))
1717 return -EADDRNOTAVAIL;
1719 ret = pm_runtime_get_sync(cpsw->dev);
1721 pm_runtime_put_noidle(cpsw->dev);
1725 if (cpsw->data.dual_emac) {
1726 vid = cpsw->slaves[priv->emac_port].port_vlan;
1730 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1732 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1735 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1736 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1737 for_each_slave(priv, cpsw_set_slave_mac, priv);
1739 pm_runtime_put(cpsw->dev);
1744 #ifdef CONFIG_NET_POLL_CONTROLLER
1745 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1747 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1749 cpsw_intr_disable(cpsw);
1750 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1751 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1752 cpsw_intr_enable(cpsw);
1756 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1760 int unreg_mcast_mask = 0;
1762 struct cpsw_common *cpsw = priv->cpsw;
1764 if (cpsw->data.dual_emac) {
1765 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1767 if (priv->ndev->flags & IFF_ALLMULTI)
1768 unreg_mcast_mask = port_mask;
1770 port_mask = ALE_ALL_PORTS;
1772 if (priv->ndev->flags & IFF_ALLMULTI)
1773 unreg_mcast_mask = ALE_ALL_PORTS;
1775 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1778 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1783 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1784 HOST_PORT_NUM, ALE_VLAN, vid);
1788 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1789 port_mask, ALE_VLAN, vid, 0);
1791 goto clean_vlan_ucast;
1795 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1796 HOST_PORT_NUM, ALE_VLAN, vid);
1798 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1802 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1803 __be16 proto, u16 vid)
1805 struct cpsw_priv *priv = netdev_priv(ndev);
1806 struct cpsw_common *cpsw = priv->cpsw;
1809 if (vid == cpsw->data.default_vlan)
1812 ret = pm_runtime_get_sync(cpsw->dev);
1814 pm_runtime_put_noidle(cpsw->dev);
1818 if (cpsw->data.dual_emac) {
1819 /* In dual EMAC, reserved VLAN id should not be used for
1820 * creating VLAN interfaces as this can break the dual
1821 * EMAC port separation
1825 for (i = 0; i < cpsw->data.slaves; i++) {
1826 if (vid == cpsw->slaves[i].port_vlan)
1831 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1832 ret = cpsw_add_vlan_ale_entry(priv, vid);
1834 pm_runtime_put(cpsw->dev);
1838 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1839 __be16 proto, u16 vid)
1841 struct cpsw_priv *priv = netdev_priv(ndev);
1842 struct cpsw_common *cpsw = priv->cpsw;
1845 if (vid == cpsw->data.default_vlan)
1848 ret = pm_runtime_get_sync(cpsw->dev);
1850 pm_runtime_put_noidle(cpsw->dev);
1854 if (cpsw->data.dual_emac) {
1857 for (i = 0; i < cpsw->data.slaves; i++) {
1858 if (vid == cpsw->slaves[i].port_vlan)
1863 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1864 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1868 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1869 HOST_PORT_NUM, ALE_VLAN, vid);
1873 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1875 pm_runtime_put(cpsw->dev);
1879 static const struct net_device_ops cpsw_netdev_ops = {
1880 .ndo_open = cpsw_ndo_open,
1881 .ndo_stop = cpsw_ndo_stop,
1882 .ndo_start_xmit = cpsw_ndo_start_xmit,
1883 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1884 .ndo_do_ioctl = cpsw_ndo_ioctl,
1885 .ndo_validate_addr = eth_validate_addr,
1886 .ndo_change_mtu = eth_change_mtu,
1887 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1888 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1889 #ifdef CONFIG_NET_POLL_CONTROLLER
1890 .ndo_poll_controller = cpsw_ndo_poll_controller,
1892 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1893 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1896 static int cpsw_get_regs_len(struct net_device *ndev)
1898 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1900 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1903 static void cpsw_get_regs(struct net_device *ndev,
1904 struct ethtool_regs *regs, void *p)
1907 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1909 /* update CPSW IP version */
1910 regs->version = cpsw->version;
1912 cpsw_ale_dump(cpsw->ale, reg);
1915 static void cpsw_get_drvinfo(struct net_device *ndev,
1916 struct ethtool_drvinfo *info)
1918 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1919 struct platform_device *pdev = to_platform_device(cpsw->dev);
1921 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1922 strlcpy(info->version, "1.0", sizeof(info->version));
1923 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
1926 static u32 cpsw_get_msglevel(struct net_device *ndev)
1928 struct cpsw_priv *priv = netdev_priv(ndev);
1929 return priv->msg_enable;
1932 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1934 struct cpsw_priv *priv = netdev_priv(ndev);
1935 priv->msg_enable = value;
1938 static int cpsw_get_ts_info(struct net_device *ndev,
1939 struct ethtool_ts_info *info)
1941 #ifdef CONFIG_TI_CPTS
1942 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1944 info->so_timestamping =
1945 SOF_TIMESTAMPING_TX_HARDWARE |
1946 SOF_TIMESTAMPING_TX_SOFTWARE |
1947 SOF_TIMESTAMPING_RX_HARDWARE |
1948 SOF_TIMESTAMPING_RX_SOFTWARE |
1949 SOF_TIMESTAMPING_SOFTWARE |
1950 SOF_TIMESTAMPING_RAW_HARDWARE;
1951 info->phc_index = cpsw->cpts->phc_index;
1953 (1 << HWTSTAMP_TX_OFF) |
1954 (1 << HWTSTAMP_TX_ON);
1956 (1 << HWTSTAMP_FILTER_NONE) |
1957 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1959 info->so_timestamping =
1960 SOF_TIMESTAMPING_TX_SOFTWARE |
1961 SOF_TIMESTAMPING_RX_SOFTWARE |
1962 SOF_TIMESTAMPING_SOFTWARE;
1963 info->phc_index = -1;
1965 info->rx_filters = 0;
1970 static int cpsw_get_settings(struct net_device *ndev,
1971 struct ethtool_cmd *ecmd)
1973 struct cpsw_priv *priv = netdev_priv(ndev);
1974 struct cpsw_common *cpsw = priv->cpsw;
1975 int slave_no = cpsw_slave_index(cpsw, priv);
1977 if (cpsw->slaves[slave_no].phy)
1978 return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd);
1983 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1985 struct cpsw_priv *priv = netdev_priv(ndev);
1986 struct cpsw_common *cpsw = priv->cpsw;
1987 int slave_no = cpsw_slave_index(cpsw, priv);
1989 if (cpsw->slaves[slave_no].phy)
1990 return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd);
1995 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1997 struct cpsw_priv *priv = netdev_priv(ndev);
1998 struct cpsw_common *cpsw = priv->cpsw;
1999 int slave_no = cpsw_slave_index(cpsw, priv);
2004 if (cpsw->slaves[slave_no].phy)
2005 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2008 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2010 struct cpsw_priv *priv = netdev_priv(ndev);
2011 struct cpsw_common *cpsw = priv->cpsw;
2012 int slave_no = cpsw_slave_index(cpsw, priv);
2014 if (cpsw->slaves[slave_no].phy)
2015 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2020 static void cpsw_get_pauseparam(struct net_device *ndev,
2021 struct ethtool_pauseparam *pause)
2023 struct cpsw_priv *priv = netdev_priv(ndev);
2025 pause->autoneg = AUTONEG_DISABLE;
2026 pause->rx_pause = priv->rx_pause ? true : false;
2027 pause->tx_pause = priv->tx_pause ? true : false;
2030 static int cpsw_set_pauseparam(struct net_device *ndev,
2031 struct ethtool_pauseparam *pause)
2033 struct cpsw_priv *priv = netdev_priv(ndev);
2036 priv->rx_pause = pause->rx_pause ? true : false;
2037 priv->tx_pause = pause->tx_pause ? true : false;
2039 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2043 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2045 struct cpsw_priv *priv = netdev_priv(ndev);
2046 struct cpsw_common *cpsw = priv->cpsw;
2049 ret = pm_runtime_get_sync(cpsw->dev);
2051 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2052 pm_runtime_put_noidle(cpsw->dev);
2058 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2060 struct cpsw_priv *priv = netdev_priv(ndev);
2063 ret = pm_runtime_put(priv->cpsw->dev);
2065 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2068 static void cpsw_get_channels(struct net_device *ndev,
2069 struct ethtool_channels *ch)
2071 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2073 ch->max_combined = 0;
2074 ch->max_rx = CPSW_MAX_QUEUES;
2075 ch->max_tx = CPSW_MAX_QUEUES;
2077 ch->other_count = 0;
2078 ch->rx_count = cpsw->rx_ch_num;
2079 ch->tx_count = cpsw->tx_ch_num;
2080 ch->combined_count = 0;
2083 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2084 struct ethtool_channels *ch)
2086 if (ch->combined_count)
2089 /* verify we have at least one channel in each direction */
2090 if (!ch->rx_count || !ch->tx_count)
2093 if (ch->rx_count > cpsw->data.channels ||
2094 ch->tx_count > cpsw->data.channels)
2100 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2102 int (*poll)(struct napi_struct *, int);
2103 struct cpsw_common *cpsw = priv->cpsw;
2104 void (*handler)(void *, int, int);
2105 struct cpdma_chan **chan;
2109 ch = &cpsw->rx_ch_num;
2111 handler = cpsw_rx_handler;
2112 poll = cpsw_rx_poll;
2114 ch = &cpsw->tx_ch_num;
2116 handler = cpsw_tx_handler;
2117 poll = cpsw_tx_poll;
2120 while (*ch < ch_num) {
2121 chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2123 if (IS_ERR(chan[*ch]))
2124 return PTR_ERR(chan[*ch]);
2129 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2130 (rx ? "rx" : "tx"));
2134 while (*ch > ch_num) {
2137 ret = cpdma_chan_destroy(chan[*ch]);
2141 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2142 (rx ? "rx" : "tx"));
2148 static int cpsw_update_channels(struct cpsw_priv *priv,
2149 struct ethtool_channels *ch)
2153 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2157 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2164 static int cpsw_set_channels(struct net_device *ndev,
2165 struct ethtool_channels *chs)
2167 struct cpsw_priv *priv = netdev_priv(ndev);
2168 struct cpsw_common *cpsw = priv->cpsw;
2169 struct cpsw_slave *slave;
2172 ret = cpsw_check_ch_settings(cpsw, chs);
2176 /* Disable NAPI scheduling */
2177 cpsw_intr_disable(cpsw);
2179 /* Stop all transmit queues for every network device.
2180 * Disable re-using rx descriptors with dormant_on.
2182 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2183 if (!(slave->ndev && netif_running(slave->ndev)))
2186 netif_tx_stop_all_queues(slave->ndev);
2187 netif_dormant_on(slave->ndev);
2190 /* Handle rest of tx packets and stop cpdma channels */
2191 cpdma_ctlr_stop(cpsw->dma);
2192 ret = cpsw_update_channels(priv, chs);
2196 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2197 if (!(slave->ndev && netif_running(slave->ndev)))
2200 /* Inform stack about new count of queues */
2201 ret = netif_set_real_num_tx_queues(slave->ndev,
2204 dev_err(priv->dev, "cannot set real number of tx queues\n");
2208 ret = netif_set_real_num_rx_queues(slave->ndev,
2211 dev_err(priv->dev, "cannot set real number of rx queues\n");
2215 /* Enable rx packets handling */
2216 netif_dormant_off(slave->ndev);
2219 if (cpsw_common_res_usage_state(cpsw)) {
2220 ret = cpsw_fill_rx_channels(priv);
2224 /* After this receive is started */
2225 cpdma_ctlr_start(cpsw->dma);
2226 cpsw_intr_enable(cpsw);
2229 /* Resume transmit for every affected interface */
2230 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2231 if (!(slave->ndev && netif_running(slave->ndev)))
2233 netif_tx_start_all_queues(slave->ndev);
2237 dev_err(priv->dev, "cannot update channels number, closing device\n");
2242 static const struct ethtool_ops cpsw_ethtool_ops = {
2243 .get_drvinfo = cpsw_get_drvinfo,
2244 .get_msglevel = cpsw_get_msglevel,
2245 .set_msglevel = cpsw_set_msglevel,
2246 .get_link = ethtool_op_get_link,
2247 .get_ts_info = cpsw_get_ts_info,
2248 .get_settings = cpsw_get_settings,
2249 .set_settings = cpsw_set_settings,
2250 .get_coalesce = cpsw_get_coalesce,
2251 .set_coalesce = cpsw_set_coalesce,
2252 .get_sset_count = cpsw_get_sset_count,
2253 .get_strings = cpsw_get_strings,
2254 .get_ethtool_stats = cpsw_get_ethtool_stats,
2255 .get_pauseparam = cpsw_get_pauseparam,
2256 .set_pauseparam = cpsw_set_pauseparam,
2257 .get_wol = cpsw_get_wol,
2258 .set_wol = cpsw_set_wol,
2259 .get_regs_len = cpsw_get_regs_len,
2260 .get_regs = cpsw_get_regs,
2261 .begin = cpsw_ethtool_op_begin,
2262 .complete = cpsw_ethtool_op_complete,
2263 .get_channels = cpsw_get_channels,
2264 .set_channels = cpsw_set_channels,
2267 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2268 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2270 void __iomem *regs = cpsw->regs;
2271 int slave_num = slave->slave_num;
2272 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2275 slave->regs = regs + slave_reg_ofs;
2276 slave->sliver = regs + sliver_reg_ofs;
2277 slave->port_vlan = data->dual_emac_res_vlan;
2280 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2281 struct platform_device *pdev)
2283 struct device_node *node = pdev->dev.of_node;
2284 struct device_node *slave_node;
2291 if (of_property_read_u32(node, "slaves", &prop)) {
2292 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2295 data->slaves = prop;
2297 if (of_property_read_u32(node, "active_slave", &prop)) {
2298 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2301 data->active_slave = prop;
2303 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2304 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2307 data->cpts_clock_mult = prop;
2309 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2310 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2313 data->cpts_clock_shift = prop;
2315 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2316 * sizeof(struct cpsw_slave_data),
2318 if (!data->slave_data)
2321 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2322 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2325 data->channels = prop;
2327 if (of_property_read_u32(node, "ale_entries", &prop)) {
2328 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2331 data->ale_entries = prop;
2333 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2334 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2337 data->bd_ram_size = prop;
2339 if (of_property_read_u32(node, "mac_control", &prop)) {
2340 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2343 data->mac_control = prop;
2345 if (of_property_read_bool(node, "dual_emac"))
2346 data->dual_emac = 1;
2349 * Populate all the child nodes here...
2351 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2352 /* We do not want to force this, as in some cases may not have child */
2354 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2356 for_each_available_child_of_node(node, slave_node) {
2357 struct cpsw_slave_data *slave_data = data->slave_data + i;
2358 const void *mac_addr = NULL;
2362 /* This is no slave child node, continue */
2363 if (strcmp(slave_node->name, "slave"))
2366 slave_data->phy_node = of_parse_phandle(slave_node,
2368 parp = of_get_property(slave_node, "phy_id", &lenp);
2369 if (slave_data->phy_node) {
2371 "slave[%d] using phy-handle=\"%s\"\n",
2372 i, slave_data->phy_node->full_name);
2373 } else if (of_phy_is_fixed_link(slave_node)) {
2374 /* In the case of a fixed PHY, the DT node associated
2375 * to the PHY is the Ethernet MAC DT node.
2377 ret = of_phy_register_fixed_link(slave_node);
2379 if (ret != -EPROBE_DEFER)
2380 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2383 slave_data->phy_node = of_node_get(slave_node);
2386 struct device_node *mdio_node;
2387 struct platform_device *mdio;
2389 if (lenp != (sizeof(__be32) * 2)) {
2390 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2393 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2394 phyid = be32_to_cpup(parp+1);
2395 mdio = of_find_device_by_node(mdio_node);
2396 of_node_put(mdio_node);
2398 dev_err(&pdev->dev, "Missing mdio platform device\n");
2401 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2402 PHY_ID_FMT, mdio->name, phyid);
2403 put_device(&mdio->dev);
2406 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2410 slave_data->phy_if = of_get_phy_mode(slave_node);
2411 if (slave_data->phy_if < 0) {
2412 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2414 return slave_data->phy_if;
2418 mac_addr = of_get_mac_address(slave_node);
2420 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2422 ret = ti_cm_get_macid(&pdev->dev, i,
2423 slave_data->mac_addr);
2427 if (data->dual_emac) {
2428 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2430 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2431 slave_data->dual_emac_res_vlan = i+1;
2432 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2433 slave_data->dual_emac_res_vlan, i);
2435 slave_data->dual_emac_res_vlan = prop;
2440 if (i == data->slaves)
2447 static void cpsw_remove_dt(struct platform_device *pdev)
2449 struct net_device *ndev = platform_get_drvdata(pdev);
2450 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2451 struct cpsw_platform_data *data = &cpsw->data;
2452 struct device_node *node = pdev->dev.of_node;
2453 struct device_node *slave_node;
2456 for_each_available_child_of_node(node, slave_node) {
2457 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2459 if (strcmp(slave_node->name, "slave"))
2462 if (of_phy_is_fixed_link(slave_node))
2463 of_phy_deregister_fixed_link(slave_node);
2465 of_node_put(slave_data->phy_node);
2468 if (i == data->slaves)
2472 of_platform_depopulate(&pdev->dev);
2475 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2477 struct cpsw_common *cpsw = priv->cpsw;
2478 struct cpsw_platform_data *data = &cpsw->data;
2479 struct net_device *ndev;
2480 struct cpsw_priv *priv_sl2;
2483 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2485 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2489 priv_sl2 = netdev_priv(ndev);
2490 priv_sl2->cpsw = cpsw;
2491 priv_sl2->ndev = ndev;
2492 priv_sl2->dev = &ndev->dev;
2493 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2495 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2496 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2498 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2499 priv_sl2->mac_addr);
2501 random_ether_addr(priv_sl2->mac_addr);
2502 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2503 priv_sl2->mac_addr);
2505 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2507 priv_sl2->emac_port = 1;
2508 cpsw->slaves[1].ndev = ndev;
2509 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2511 ndev->netdev_ops = &cpsw_netdev_ops;
2512 ndev->ethtool_ops = &cpsw_ethtool_ops;
2514 /* register the network device */
2515 SET_NETDEV_DEV(ndev, cpsw->dev);
2516 ret = register_netdev(ndev);
2518 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2526 #define CPSW_QUIRK_IRQ BIT(0)
2528 static struct platform_device_id cpsw_devtype[] = {
2530 /* keep it for existing comaptibles */
2532 .driver_data = CPSW_QUIRK_IRQ,
2534 .name = "am335x-cpsw",
2535 .driver_data = CPSW_QUIRK_IRQ,
2537 .name = "am4372-cpsw",
2540 .name = "dra7-cpsw",
2546 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2555 static const struct of_device_id cpsw_of_mtable[] = {
2556 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2557 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2558 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2559 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2562 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2564 static int cpsw_probe(struct platform_device *pdev)
2567 struct cpsw_platform_data *data;
2568 struct net_device *ndev;
2569 struct cpsw_priv *priv;
2570 struct cpdma_params dma_params;
2571 struct cpsw_ale_params ale_params;
2572 void __iomem *ss_regs;
2573 struct resource *res, *ss_res;
2574 const struct of_device_id *of_id;
2575 struct gpio_descs *mode;
2576 u32 slave_offset, sliver_offset, slave_size;
2577 struct cpsw_common *cpsw;
2581 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2585 cpsw->dev = &pdev->dev;
2587 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2589 dev_err(&pdev->dev, "error allocating net_device\n");
2593 platform_set_drvdata(pdev, ndev);
2594 priv = netdev_priv(ndev);
2597 priv->dev = &ndev->dev;
2598 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2599 cpsw->rx_packet_max = max(rx_packet_max, 128);
2600 cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2602 dev_err(&pdev->dev, "error allocating cpts\n");
2604 goto clean_ndev_ret;
2607 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2609 ret = PTR_ERR(mode);
2610 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2611 goto clean_ndev_ret;
2615 * This may be required here for child devices.
2617 pm_runtime_enable(&pdev->dev);
2619 /* Select default pin state */
2620 pinctrl_pm_select_default_state(&pdev->dev);
2622 /* Need to enable clocks with runtime PM api to access module
2625 ret = pm_runtime_get_sync(&pdev->dev);
2627 pm_runtime_put_noidle(&pdev->dev);
2628 goto clean_runtime_disable_ret;
2631 ret = cpsw_probe_dt(&cpsw->data, pdev);
2636 cpsw->rx_ch_num = 1;
2637 cpsw->tx_ch_num = 1;
2639 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2640 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2641 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2643 eth_random_addr(priv->mac_addr);
2644 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2647 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2649 cpsw->slaves = devm_kzalloc(&pdev->dev,
2650 sizeof(struct cpsw_slave) * data->slaves,
2652 if (!cpsw->slaves) {
2656 for (i = 0; i < data->slaves; i++)
2657 cpsw->slaves[i].slave_num = i;
2659 cpsw->slaves[0].ndev = ndev;
2660 priv->emac_port = 0;
2662 clk = devm_clk_get(&pdev->dev, "fck");
2664 dev_err(priv->dev, "fck is not found\n");
2668 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2670 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2671 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2672 if (IS_ERR(ss_regs)) {
2673 ret = PTR_ERR(ss_regs);
2676 cpsw->regs = ss_regs;
2678 cpsw->version = readl(&cpsw->regs->id_ver);
2680 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2681 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2682 if (IS_ERR(cpsw->wr_regs)) {
2683 ret = PTR_ERR(cpsw->wr_regs);
2687 memset(&dma_params, 0, sizeof(dma_params));
2688 memset(&ale_params, 0, sizeof(ale_params));
2690 switch (cpsw->version) {
2691 case CPSW_VERSION_1:
2692 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2693 cpsw->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2694 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
2695 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2696 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2697 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2698 slave_offset = CPSW1_SLAVE_OFFSET;
2699 slave_size = CPSW1_SLAVE_SIZE;
2700 sliver_offset = CPSW1_SLIVER_OFFSET;
2701 dma_params.desc_mem_phys = 0;
2703 case CPSW_VERSION_2:
2704 case CPSW_VERSION_3:
2705 case CPSW_VERSION_4:
2706 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2707 cpsw->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2708 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
2709 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2710 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2711 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2712 slave_offset = CPSW2_SLAVE_OFFSET;
2713 slave_size = CPSW2_SLAVE_SIZE;
2714 sliver_offset = CPSW2_SLIVER_OFFSET;
2715 dma_params.desc_mem_phys =
2716 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2719 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2723 for (i = 0; i < cpsw->data.slaves; i++) {
2724 struct cpsw_slave *slave = &cpsw->slaves[i];
2726 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2727 slave_offset += slave_size;
2728 sliver_offset += SLIVER_SIZE;
2731 dma_params.dev = &pdev->dev;
2732 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2733 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2734 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2735 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2736 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2738 dma_params.num_chan = data->channels;
2739 dma_params.has_soft_reset = true;
2740 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2741 dma_params.desc_mem_size = data->bd_ram_size;
2742 dma_params.desc_align = 16;
2743 dma_params.has_ext_regs = true;
2744 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2746 cpsw->dma = cpdma_ctlr_create(&dma_params);
2748 dev_err(priv->dev, "error initializing dma\n");
2753 cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2754 cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
2755 if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) {
2756 dev_err(priv->dev, "error initializing dma channels\n");
2761 ale_params.dev = &ndev->dev;
2762 ale_params.ale_ageout = ale_ageout;
2763 ale_params.ale_entries = data->ale_entries;
2764 ale_params.ale_ports = data->slaves;
2766 cpsw->ale = cpsw_ale_create(&ale_params);
2768 dev_err(priv->dev, "error initializing ale engine\n");
2773 ndev->irq = platform_get_irq(pdev, 1);
2774 if (ndev->irq < 0) {
2775 dev_err(priv->dev, "error getting irq resource\n");
2780 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2782 pdev->id_entry = of_id->data;
2783 if (pdev->id_entry->driver_data)
2784 cpsw->quirk_irq = true;
2787 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2788 * MISC IRQs which are always kept disabled with this driver so
2789 * we will not request them.
2791 * If anyone wants to implement support for those, make sure to
2792 * first request and append them to irqs_table array.
2796 irq = platform_get_irq(pdev, 1);
2802 cpsw->irqs_table[0] = irq;
2803 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2804 0, dev_name(&pdev->dev), cpsw);
2806 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2811 irq = platform_get_irq(pdev, 2);
2817 cpsw->irqs_table[1] = irq;
2818 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2819 0, dev_name(&pdev->dev), cpsw);
2821 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2825 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2827 ndev->netdev_ops = &cpsw_netdev_ops;
2828 ndev->ethtool_ops = &cpsw_ethtool_ops;
2829 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2830 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2832 /* register the network device */
2833 SET_NETDEV_DEV(ndev, &pdev->dev);
2834 ret = register_netdev(ndev);
2836 dev_err(priv->dev, "error registering net device\n");
2841 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2842 &ss_res->start, ndev->irq);
2844 if (cpsw->data.dual_emac) {
2845 ret = cpsw_probe_dual_emac(priv);
2847 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2848 goto clean_unregister_netdev_ret;
2852 pm_runtime_put(&pdev->dev);
2856 clean_unregister_netdev_ret:
2857 unregister_netdev(ndev);
2859 cpsw_ale_destroy(cpsw->ale);
2861 cpdma_ctlr_destroy(cpsw->dma);
2863 cpsw_remove_dt(pdev);
2864 pm_runtime_put_sync(&pdev->dev);
2865 clean_runtime_disable_ret:
2866 pm_runtime_disable(&pdev->dev);
2868 free_netdev(priv->ndev);
2872 static int cpsw_remove(struct platform_device *pdev)
2874 struct net_device *ndev = platform_get_drvdata(pdev);
2875 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2878 ret = pm_runtime_get_sync(&pdev->dev);
2880 pm_runtime_put_noidle(&pdev->dev);
2884 if (cpsw->data.dual_emac)
2885 unregister_netdev(cpsw->slaves[1].ndev);
2886 unregister_netdev(ndev);
2888 cpsw_ale_destroy(cpsw->ale);
2889 cpdma_ctlr_destroy(cpsw->dma);
2890 cpsw_remove_dt(pdev);
2891 pm_runtime_put_sync(&pdev->dev);
2892 pm_runtime_disable(&pdev->dev);
2893 if (cpsw->data.dual_emac)
2894 free_netdev(cpsw->slaves[1].ndev);
2899 #ifdef CONFIG_PM_SLEEP
2900 static int cpsw_suspend(struct device *dev)
2902 struct platform_device *pdev = to_platform_device(dev);
2903 struct net_device *ndev = platform_get_drvdata(pdev);
2904 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2906 if (cpsw->data.dual_emac) {
2909 for (i = 0; i < cpsw->data.slaves; i++) {
2910 if (netif_running(cpsw->slaves[i].ndev))
2911 cpsw_ndo_stop(cpsw->slaves[i].ndev);
2914 if (netif_running(ndev))
2915 cpsw_ndo_stop(ndev);
2918 /* Select sleep pin state */
2919 pinctrl_pm_select_sleep_state(dev);
2924 static int cpsw_resume(struct device *dev)
2926 struct platform_device *pdev = to_platform_device(dev);
2927 struct net_device *ndev = platform_get_drvdata(pdev);
2928 struct cpsw_common *cpsw = netdev_priv(ndev);
2930 /* Select default pin state */
2931 pinctrl_pm_select_default_state(dev);
2933 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
2935 if (cpsw->data.dual_emac) {
2938 for (i = 0; i < cpsw->data.slaves; i++) {
2939 if (netif_running(cpsw->slaves[i].ndev))
2940 cpsw_ndo_open(cpsw->slaves[i].ndev);
2943 if (netif_running(ndev))
2944 cpsw_ndo_open(ndev);
2952 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2954 static struct platform_driver cpsw_driver = {
2958 .of_match_table = cpsw_of_mtable,
2960 .probe = cpsw_probe,
2961 .remove = cpsw_remove,
2964 module_platform_driver(cpsw_driver);
2966 MODULE_LICENSE("GPL");
2967 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2968 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2969 MODULE_DESCRIPTION("TI CPSW Ethernet driver");