drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_RGMIICTL        0x0032
  36 #define DP83867_RGMIIDCTL       0x0086
  37
  38 #define DP83867_SW_RESET        BIT(15)
  39 #define DP83867_SW_RESTART      BIT(14)
  40
  41 /* MICR Interrupt bits */
  42 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  43 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  44 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  45 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  46 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  47 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  48 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  49 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  50 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  51 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  52 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  53 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  54
  55 /* RGMIICTL bits */
  56 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  57 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  58
  59 /* PHY CTRL bits */
  60 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  61
  62 /* RGMIIDCTL bits */
  63 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  64
  65 struct dp83867_private {
  66         int rx_id_delay;
  67         int tx_id_delay;
  68         int fifo_depth;
  69 };
  70
  71 static int dp83867_ack_interrupt(struct phy_device *phydev)
  72 {
  73         int err = phy_read(phydev, MII_DP83867_ISR);
  74
  75         if (err < 0)
  76                 return err;
  77
  78         return 0;
  79 }
  80
  81 static int dp83867_config_intr(struct phy_device *phydev)
  82 {
  83         int micr_status;
  84
  85         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  86                 micr_status = phy_read(phydev, MII_DP83867_MICR);
  87                 if (micr_status < 0)
  88                         return micr_status;
  89
  90                 micr_status |=
  91                         (MII_DP83867_MICR_AN_ERR_INT_EN |
  92                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
  93                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
  94                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
  95                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
  96                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
  97
  98                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
  99         }
 100
 101         micr_status = 0x0;
 102         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 103 }
 104
 105 #ifdef CONFIG_OF_MDIO
 106 static int dp83867_of_init(struct phy_device *phydev)
 107 {
 108         struct dp83867_private *dp83867 = phydev->priv;
 109         struct device *dev = &phydev->dev;
 110         struct device_node *of_node = dev->of_node;
 111         int ret;
 112
 113         if (!of_node && dev->parent->of_node)
 114                 of_node = dev->parent->of_node;
 115
 116         if (!phydev->dev.of_node)
 117                 return -ENODEV;
 118
 119         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 120                                    &dp83867->rx_id_delay);
 121         if (ret)
 122                 return ret;
 123
 124         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 125                                    &dp83867->tx_id_delay);
 126         if (ret)
 127                 return ret;
 128
 129         return of_property_read_u32(of_node, "ti,fifo-depth",
 130                                    &dp83867->fifo_depth);
 131 }
 132 #else
 133 static int dp83867_of_init(struct phy_device *phydev)
 134 {
 135         return 0;
 136 }
 137 #endif /* CONFIG_OF_MDIO */
 138
 139 static int dp83867_config_init(struct phy_device *phydev)
 140 {
 141         struct dp83867_private *dp83867;
 142         int ret;
 143         u16 val, delay;
 144
 145         if (!phydev->priv) {
 146                 dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867),
 147                                        GFP_KERNEL);
 148                 if (!dp83867)
 149                         return -ENOMEM;
 150
 151                 phydev->priv = dp83867;
 152                 ret = dp83867_of_init(phydev);
 153                 if (ret)
 154                         return ret;
 155         } else {
 156                 dp83867 = (struct dp83867_private *)phydev->priv;
 157         }
 158
 159         if (phy_interface_is_rgmii(phydev)) {
 160                 ret = phy_write(phydev, MII_DP83867_PHYCTRL,
 161                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 162                 if (ret)
 163                         return ret;
 164         }
 165
 166         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 167             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 168                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 169                                             DP83867_DEVADDR, phydev->addr);
 170
 171                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 172                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 173
 174                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 175                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 176
 177                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 178                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 179
 180                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 181                                        DP83867_DEVADDR, phydev->addr, val);
 182
 183                 delay = (dp83867->rx_id_delay |
 184                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 185
 186                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 187                                        DP83867_DEVADDR, phydev->addr, delay);
 188         }
 189
 190         /* Enable Interrupt output INT_OE in CFG3 register */
 191         if (phy_interrupt_is_valid(phydev)) {
 192                 val = phy_read(phydev, DP83867_CFG3);
 193                 val |= BIT(7);
 194                 phy_write(phydev, DP83867_CFG3, val);
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int dp83867_phy_reset(struct phy_device *phydev)
 201 {
 202         int err;
 203
 204         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 205         if (err < 0)
 206                 return err;
 207
 208         return dp83867_config_init(phydev);
 209 }
 210
 211 static struct phy_driver dp83867_driver[] = {
 212         {
 213                 .phy_id         = DP83867_PHY_ID,
 214                 .phy_id_mask    = 0xfffffff0,
 215                 .name           = "TI DP83867",
 216                 .features       = PHY_GBIT_FEATURES,
 217                 .flags          = PHY_HAS_INTERRUPT,
 218
 219                 .config_init    = dp83867_config_init,
 220                 .soft_reset     = dp83867_phy_reset,
 221
 222                 /* IRQ related */
 223                 .ack_interrupt  = dp83867_ack_interrupt,
 224                 .config_intr    = dp83867_config_intr,
 225
 226                 .config_aneg    = genphy_config_aneg,
 227                 .read_status    = genphy_read_status,
 228                 .suspend        = genphy_suspend,
 229                 .resume         = genphy_resume,
 230
 231                 .driver         = {.owner = THIS_MODULE,}
 232         },
 233 };
 234 module_phy_driver(dp83867_driver);
 235
 236 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 237         { DP83867_PHY_ID, 0xfffffff0 },
 238         { }
 239 };
 240
 241 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 242
 243 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 244 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 245 MODULE_LICENSE("GPL");