drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_RGMIICTL        0x0032
  36 #define DP83867_STRAP_STS1      0x006E
  37 #define DP83867_RGMIIDCTL       0x0086
  38
  39 #define DP83867_SW_RESET        BIT(15)
  40 #define DP83867_SW_RESTART      BIT(14)
  41
  42 /* MICR Interrupt bits */
  43 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  44 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  45 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  46 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  47 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  48 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  49 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  50 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  51 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  52 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  53 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  54 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  55
  56 /* RGMIICTL bits */
  57 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  58 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  59
  60 /* STRAP_STS1 bits */
  61 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  62
  63 /* PHY CTRL bits */
  64 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  65 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  66 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  67
  68 /* RGMIIDCTL bits */
  69 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  70
  71 struct dp83867_private {
  72         int rx_id_delay;
  73         int tx_id_delay;
  74         int fifo_depth;
  75 };
  76
  77 static int dp83867_ack_interrupt(struct phy_device *phydev)
  78 {
  79         int err = phy_read(phydev, MII_DP83867_ISR);
  80
  81         if (err < 0)
  82                 return err;
  83
  84         return 0;
  85 }
  86
  87 static int dp83867_config_intr(struct phy_device *phydev)
  88 {
  89         int micr_status;
  90
  91         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  92                 micr_status = phy_read(phydev, MII_DP83867_MICR);
  93                 if (micr_status < 0)
  94                         return micr_status;
  95
  96                 micr_status |=
  97                         (MII_DP83867_MICR_AN_ERR_INT_EN |
  98                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
  99                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 100                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 101                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 102                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 103
 104                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 105         }
 106
 107         micr_status = 0x0;
 108         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 109 }
 110
 111 #ifdef CONFIG_OF_MDIO
 112 static int dp83867_of_init(struct phy_device *phydev)
 113 {
 114         struct dp83867_private *dp83867 = phydev->priv;
 115         struct device *dev = &phydev->mdio.dev;
 116         struct device_node *of_node = dev->of_node;
 117         int ret;
 118
 119         if (!of_node)
 120                 return -ENODEV;
 121
 122         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 123                                    &dp83867->rx_id_delay);
 124         if (ret &&
 125             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 126              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 127                 return ret;
 128
 129         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 130                                    &dp83867->tx_id_delay);
 131         if (ret &&
 132             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 133              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 134                 return ret;
 135
 136         return of_property_read_u32(of_node, "ti,fifo-depth",
 137                                    &dp83867->fifo_depth);
 138 }
 139 #else
 140 static int dp83867_of_init(struct phy_device *phydev)
 141 {
 142         return 0;
 143 }
 144 #endif /* CONFIG_OF_MDIO */
 145
 146 static int dp83867_config_init(struct phy_device *phydev)
 147 {
 148         struct dp83867_private *dp83867;
 149         int ret, val, bs;
 150         u16 delay;
 151
 152         if (!phydev->priv) {
 153                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 154                                        GFP_KERNEL);
 155                 if (!dp83867)
 156                         return -ENOMEM;
 157
 158                 phydev->priv = dp83867;
 159                 ret = dp83867_of_init(phydev);
 160                 if (ret)
 161                         return ret;
 162         } else {
 163                 dp83867 = (struct dp83867_private *)phydev->priv;
 164         }
 165
 166         if (phy_interface_is_rgmii(phydev)) {
 167                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 168                 if (val < 0)
 169                         return val;
 170                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 171                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 172
 173                 /* The code below checks if "port mirroring" N/A MODE4 has been
 174                  * enabled during power on bootstrap.
 175                  *
 176                  * Such N/A mode enabled by mistake can put PHY IC in some
 177                  * internal testing mode and disable RGMII transmission.
 178                  *
 179                  * In this particular case one needs to check STRAP_STS1
 180                  * register's bit 11 (marked as RESERVED).
 181                  */
 182
 183                 bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
 184                                            DP83867_DEVADDR);
 185                 if (bs & DP83867_STRAP_STS1_RESERVED)
 186                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 187
 188                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 189                 if (ret)
 190                         return ret;
 191         }
 192
 193         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 194             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 195                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 196                                             DP83867_DEVADDR);
 197
 198                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 199                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 200
 201                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 202                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 203
 204                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 205                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 206
 207                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 208                                        DP83867_DEVADDR, val);
 209
 210                 delay = (dp83867->rx_id_delay |
 211                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 212
 213                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 214                                        DP83867_DEVADDR, delay);
 215         }
 216
 217         /* Enable Interrupt output INT_OE in CFG3 register */
 218         if (phy_interrupt_is_valid(phydev)) {
 219                 val = phy_read(phydev, DP83867_CFG3);
 220                 val |= BIT(7);
 221                 phy_write(phydev, DP83867_CFG3, val);
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int dp83867_phy_reset(struct phy_device *phydev)
 228 {
 229         int err;
 230
 231         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 232         if (err < 0)
 233                 return err;
 234
 235         return dp83867_config_init(phydev);
 236 }
 237
 238 static struct phy_driver dp83867_driver[] = {
 239         {
 240                 .phy_id         = DP83867_PHY_ID,
 241                 .phy_id_mask    = 0xfffffff0,
 242                 .name           = "TI DP83867",
 243                 .features       = PHY_GBIT_FEATURES,
 244                 .flags          = PHY_HAS_INTERRUPT,
 245
 246                 .config_init    = dp83867_config_init,
 247                 .soft_reset     = dp83867_phy_reset,
 248
 249                 /* IRQ related */
 250                 .ack_interrupt  = dp83867_ack_interrupt,
 251                 .config_intr    = dp83867_config_intr,
 252
 253                 .config_aneg    = genphy_config_aneg,
 254                 .read_status    = genphy_read_status,
 255                 .suspend        = genphy_suspend,
 256                 .resume         = genphy_resume,
 257         },
 258 };
 259 module_phy_driver(dp83867_driver);
 260
 261 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 262         { DP83867_PHY_ID, 0xfffffff0 },
 263         { }
 264 };
 265
 266 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 267
 268 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 269 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 270 MODULE_LICENSE("GPL");