drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31 #include <linux/delay.h>
  32
  33 /* Operation Mode Strap Override */
  34 #define MII_KSZPHY_OMSO                         0x16
  35 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  36 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  37 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  38 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  39
  40 /* general Interrupt control/status reg in vendor specific block. */
  41 #define MII_KSZPHY_INTCS                        0x1B
  42 #define KSZPHY_INTCS_JABBER                     BIT(15)
  43 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  44 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  45 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  46 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  47 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  48 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  49 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  50 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  51                                                 KSZPHY_INTCS_LINK_DOWN)
  52
  53 /* PHY Control 1 */
  54 #define MII_KSZPHY_CTRL_1                       0x1e
  55
  56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  57 #define MII_KSZPHY_CTRL_2                       0x1f
  58 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  59 /* bitmap of PHY register to set interrupt mode */
  60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  61 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  62
  63 /* Write/read to/from extended registers */
  64 #define MII_KSZPHY_EXTREG                       0x0b
  65 #define KSZPHY_EXTREG_WRITE                     0x8000
  66
  67 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  68 #define MII_KSZPHY_EXTREG_READ                  0x0d
  69
  70 /* Extended registers */
  71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  72 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  73 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  74
  75 #define PS_TO_REG                               200
  76
  77 struct kszphy_hw_stat {
  78         const char *string;
  79         u8 reg;
  80         u8 bits;
  81 };
  82
  83 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  84         { "phy_receive_errors", 21, 16},
  85         { "phy_idle_errors", 10, 8 },
  86 };
  87
  88 struct kszphy_type {
  89         u32 led_mode_reg;
  90         u16 interrupt_level_mask;
  91         bool has_broadcast_disable;
  92         bool has_nand_tree_disable;
  93         bool has_rmii_ref_clk_sel;
  94 };
  95
  96 struct kszphy_priv {
  97         const struct kszphy_type *type;
  98         int led_mode;
  99         bool rmii_ref_clk_sel;
 100         bool rmii_ref_clk_sel_val;
 101         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 102 };
 103
 104 static const struct kszphy_type ksz8021_type = {
 105         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 106         .has_broadcast_disable  = true,
 107         .has_nand_tree_disable  = true,
 108         .has_rmii_ref_clk_sel   = true,
 109 };
 110
 111 static const struct kszphy_type ksz8041_type = {
 112         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 113 };
 114
 115 static const struct kszphy_type ksz8051_type = {
 116         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 117         .has_nand_tree_disable  = true,
 118 };
 119
 120 static const struct kszphy_type ksz8081_type = {
 121         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 122         .has_broadcast_disable  = true,
 123         .has_nand_tree_disable  = true,
 124         .has_rmii_ref_clk_sel   = true,
 125 };
 126
 127 static const struct kszphy_type ks8737_type = {
 128         .interrupt_level_mask   = BIT(14),
 129 };
 130
 131 static const struct kszphy_type ksz9021_type = {
 132         .interrupt_level_mask   = BIT(14),
 133 };
 134
 135 static int kszphy_extended_write(struct phy_device *phydev,
 136                                 u32 regnum, u16 val)
 137 {
 138         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 139         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 140 }
 141
 142 static int kszphy_extended_read(struct phy_device *phydev,
 143                                 u32 regnum)
 144 {
 145         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 146         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 147 }
 148
 149 static int kszphy_ack_interrupt(struct phy_device *phydev)
 150 {
 151         /* bit[7..0] int status, which is a read and clear register. */
 152         int rc;
 153
 154         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 155
 156         return (rc < 0) ? rc : 0;
 157 }
 158
 159 static int kszphy_config_intr(struct phy_device *phydev)
 160 {
 161         const struct kszphy_type *type = phydev->drv->driver_data;
 162         int temp;
 163         u16 mask;
 164
 165         if (type && type->interrupt_level_mask)
 166                 mask = type->interrupt_level_mask;
 167         else
 168                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 169
 170         /* set the interrupt pin active low */
 171         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 172         if (temp < 0)
 173                 return temp;
 174         temp &= ~mask;
 175         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 176
 177         /* enable / disable interrupts */
 178         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 179                 temp = KSZPHY_INTCS_ALL;
 180         else
 181                 temp = 0;
 182
 183         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 184 }
 185
 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 187 {
 188         int ctrl;
 189
 190         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 191         if (ctrl < 0)
 192                 return ctrl;
 193
 194         if (val)
 195                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 196         else
 197                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 198
 199         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 200 }
 201
 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 203 {
 204         int rc, temp, shift;
 205
 206         switch (reg) {
 207         case MII_KSZPHY_CTRL_1:
 208                 shift = 14;
 209                 break;
 210         case MII_KSZPHY_CTRL_2:
 211                 shift = 4;
 212                 break;
 213         default:
 214                 return -EINVAL;
 215         }
 216
 217         temp = phy_read(phydev, reg);
 218         if (temp < 0) {
 219                 rc = temp;
 220                 goto out;
 221         }
 222
 223         temp &= ~(3 << shift);
 224         temp |= val << shift;
 225         rc = phy_write(phydev, reg, temp);
 226 out:
 227         if (rc < 0)
 228                 phydev_err(phydev, "failed to set led mode\n");
 229
 230         return rc;
 231 }
 232
 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 234  * unique (non-broadcast) address on a shared bus.
 235  */
 236 static int kszphy_broadcast_disable(struct phy_device *phydev)
 237 {
 238         int ret;
 239
 240         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 241         if (ret < 0)
 242                 goto out;
 243
 244         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 245 out:
 246         if (ret)
 247                 phydev_err(phydev, "failed to disable broadcast address\n");
 248
 249         return ret;
 250 }
 251
 252 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 253 {
 254         int ret;
 255
 256         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 257         if (ret < 0)
 258                 goto out;
 259
 260         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 261                 return 0;
 262
 263         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 264                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 265 out:
 266         if (ret)
 267                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 268
 269         return ret;
 270 }
 271
 272 static int kszphy_config_init(struct phy_device *phydev)
 273 {
 274         struct kszphy_priv *priv = phydev->priv;
 275         const struct kszphy_type *type;
 276         int ret;
 277
 278         if (!priv)
 279                 return 0;
 280
 281         type = priv->type;
 282
 283         if (type->has_broadcast_disable)
 284                 kszphy_broadcast_disable(phydev);
 285
 286         if (type->has_nand_tree_disable)
 287                 kszphy_nand_tree_disable(phydev);
 288
 289         if (priv->rmii_ref_clk_sel) {
 290                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 291                 if (ret) {
 292                         phydev_err(phydev,
 293                                    "failed to set rmii reference clock\n");
 294                         return ret;
 295                 }
 296         }
 297
 298         if (priv->led_mode >= 0)
 299                 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
 300
 301         if (phy_interrupt_is_valid(phydev)) {
 302                 int ctl = phy_read(phydev, MII_BMCR);
 303
 304                 if (ctl < 0)
 305                         return ctl;
 306
 307                 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
 308                 if (ret < 0)
 309                         return ret;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int ksz8041_config_init(struct phy_device *phydev)
 316 {
 317         struct device_node *of_node = phydev->mdio.dev.of_node;
 318
 319         /* Limit supported and advertised modes in fiber mode */
 320         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 321                 phydev->dev_flags |= MICREL_PHY_FXEN;
 322                 phydev->supported &= SUPPORTED_100baseT_Full |
 323                                      SUPPORTED_100baseT_Half;
 324                 phydev->supported |= SUPPORTED_FIBRE;
 325                 phydev->advertising &= ADVERTISED_100baseT_Full |
 326                                        ADVERTISED_100baseT_Half;
 327                 phydev->advertising |= ADVERTISED_FIBRE;
 328                 phydev->autoneg = AUTONEG_DISABLE;
 329         }
 330
 331         return kszphy_config_init(phydev);
 332 }
 333
 334 static int ksz8041_config_aneg(struct phy_device *phydev)
 335 {
 336         /* Skip auto-negotiation in fiber mode */
 337         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 338                 phydev->speed = SPEED_100;
 339                 return 0;
 340         }
 341
 342         return genphy_config_aneg(phydev);
 343 }
 344
 345 static int ksz8061_config_init(struct phy_device *phydev)
 346 {
 347         int ret;
 348
 349         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 350         if (ret)
 351                 return ret;
 352
 353         return kszphy_config_init(phydev);
 354 }
 355
 356 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 357                                        const struct device_node *of_node,
 358                                        u16 reg,
 359                                        const char *field1, const char *field2,
 360                                        const char *field3, const char *field4)
 361 {
 362         int val1 = -1;
 363         int val2 = -2;
 364         int val3 = -3;
 365         int val4 = -4;
 366         int newval;
 367         int matches = 0;
 368
 369         if (!of_property_read_u32(of_node, field1, &val1))
 370                 matches++;
 371
 372         if (!of_property_read_u32(of_node, field2, &val2))
 373                 matches++;
 374
 375         if (!of_property_read_u32(of_node, field3, &val3))
 376                 matches++;
 377
 378         if (!of_property_read_u32(of_node, field4, &val4))
 379                 matches++;
 380
 381         if (!matches)
 382                 return 0;
 383
 384         if (matches < 4)
 385                 newval = kszphy_extended_read(phydev, reg);
 386         else
 387                 newval = 0;
 388
 389         if (val1 != -1)
 390                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 391
 392         if (val2 != -2)
 393                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 394
 395         if (val3 != -3)
 396                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 397
 398         if (val4 != -4)
 399                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 400
 401         return kszphy_extended_write(phydev, reg, newval);
 402 }
 403
 404 static int ksz9021_config_init(struct phy_device *phydev)
 405 {
 406         const struct device *dev = &phydev->mdio.dev;
 407         const struct device_node *of_node = dev->of_node;
 408         const struct device *dev_walker;
 409
 410         /* The Micrel driver has a deprecated option to place phy OF
 411          * properties in the MAC node. Walk up the tree of devices to
 412          * find a device with an OF node.
 413          */
 414         dev_walker = &phydev->mdio.dev;
 415         do {
 416                 of_node = dev_walker->of_node;
 417                 dev_walker = dev_walker->parent;
 418
 419         } while (!of_node && dev_walker);
 420
 421         if (of_node) {
 422                 ksz9021_load_values_from_of(phydev, of_node,
 423                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 424                                     "txen-skew-ps", "txc-skew-ps",
 425                                     "rxdv-skew-ps", "rxc-skew-ps");
 426                 ksz9021_load_values_from_of(phydev, of_node,
 427                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 428                                     "rxd0-skew-ps", "rxd1-skew-ps",
 429                                     "rxd2-skew-ps", "rxd3-skew-ps");
 430                 ksz9021_load_values_from_of(phydev, of_node,
 431                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 432                                     "txd0-skew-ps", "txd1-skew-ps",
 433                                     "txd2-skew-ps", "txd3-skew-ps");
 434         }
 435         return 0;
 436 }
 437
 438 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 439 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 440 #define OP_DATA                         1
 441 #define KSZ9031_PS_TO_REG               60
 442
 443 /* Extended registers */
 444 /* MMD Address 0x0 */
 445 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 446 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 447
 448 /* MMD Address 0x2 */
 449 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 450 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 451 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 452 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 453
 454 /* MMD Address 0x1C */
 455 #define MII_KSZ9031RN_EDPD              0x23
 456 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 457
 458 static int ksz9031_extended_write(struct phy_device *phydev,
 459                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 460 {
 461         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 462         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 463         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 464         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 465 }
 466
 467 static int ksz9031_extended_read(struct phy_device *phydev,
 468                                  u8 mode, u32 dev_addr, u32 regnum)
 469 {
 470         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 471         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 472         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 473         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 474 }
 475
 476 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 477                                        const struct device_node *of_node,
 478                                        u16 reg, size_t field_sz,
 479                                        const char *field[], u8 numfields)
 480 {
 481         int val[4] = {-1, -2, -3, -4};
 482         int matches = 0;
 483         u16 mask;
 484         u16 maxval;
 485         u16 newval;
 486         int i;
 487
 488         for (i = 0; i < numfields; i++)
 489                 if (!of_property_read_u32(of_node, field[i], val + i))
 490                         matches++;
 491
 492         if (!matches)
 493                 return 0;
 494
 495         if (matches < numfields)
 496                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 497         else
 498                 newval = 0;
 499
 500         maxval = (field_sz == 4) ? 0xf : 0x1f;
 501         for (i = 0; i < numfields; i++)
 502                 if (val[i] != -(i + 1)) {
 503                         mask = 0xffff;
 504                         mask ^= maxval << (field_sz * i);
 505                         newval = (newval & mask) |
 506                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 507                                         << (field_sz * i));
 508                 }
 509
 510         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 511 }
 512
 513 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 514 {
 515         int result;
 516
 517         /* Center KSZ9031RNX FLP timing at 16ms. */
 518         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 519                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 520         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 521                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 522
 523         if (result)
 524                 return result;
 525
 526         return genphy_restart_aneg(phydev);
 527 }
 528
 529 /* Enable energy-detect power-down mode */
 530 static int ksz9031_enable_edpd(struct phy_device *phydev)
 531 {
 532         int reg;
 533
 534         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 535         if (reg < 0)
 536                 return reg;
 537         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 538                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 539 }
 540
 541 static int ksz9031_config_init(struct phy_device *phydev)
 542 {
 543         const struct device *dev = &phydev->mdio.dev;
 544         const struct device_node *of_node = dev->of_node;
 545         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 546         static const char *rx_data_skews[4] = {
 547                 "rxd0-skew-ps", "rxd1-skew-ps",
 548                 "rxd2-skew-ps", "rxd3-skew-ps"
 549         };
 550         static const char *tx_data_skews[4] = {
 551                 "txd0-skew-ps", "txd1-skew-ps",
 552                 "txd2-skew-ps", "txd3-skew-ps"
 553         };
 554         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 555         const struct device *dev_walker;
 556         int result;
 557
 558         result = ksz9031_enable_edpd(phydev);
 559         if (result < 0)
 560                 return result;
 561
 562         /* The Micrel driver has a deprecated option to place phy OF
 563          * properties in the MAC node. Walk up the tree of devices to
 564          * find a device with an OF node.
 565          */
 566         dev_walker = &phydev->mdio.dev;
 567         do {
 568                 of_node = dev_walker->of_node;
 569                 dev_walker = dev_walker->parent;
 570         } while (!of_node && dev_walker);
 571
 572         if (of_node) {
 573                 ksz9031_of_load_skew_values(phydev, of_node,
 574                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 575                                 clk_skews, 2);
 576
 577                 ksz9031_of_load_skew_values(phydev, of_node,
 578                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 579                                 control_skews, 2);
 580
 581                 ksz9031_of_load_skew_values(phydev, of_node,
 582                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 583                                 rx_data_skews, 4);
 584
 585                 ksz9031_of_load_skew_values(phydev, of_node,
 586                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 587                                 tx_data_skews, 4);
 588         }
 589
 590         return ksz9031_center_flp_timing(phydev);
 591 }
 592
 593 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 594 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 595 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 596 static int ksz8873mll_read_status(struct phy_device *phydev)
 597 {
 598         int regval;
 599
 600         /* dummy read */
 601         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 602
 603         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 604
 605         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 606                 phydev->duplex = DUPLEX_HALF;
 607         else
 608                 phydev->duplex = DUPLEX_FULL;
 609
 610         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 611                 phydev->speed = SPEED_10;
 612         else
 613                 phydev->speed = SPEED_100;
 614
 615         phydev->link = 1;
 616         phydev->pause = phydev->asym_pause = 0;
 617
 618         return 0;
 619 }
 620
 621 static int ksz9031_read_status(struct phy_device *phydev)
 622 {
 623         int err;
 624         int regval;
 625
 626         err = genphy_read_status(phydev);
 627         if (err)
 628                 return err;
 629
 630         /* Make sure the PHY is not broken. Read idle error count,
 631          * and reset the PHY if it is maxed out.
 632          */
 633         regval = phy_read(phydev, MII_STAT1000);
 634         if ((regval & 0xFF) == 0xFF) {
 635                 phy_init_hw(phydev);
 636                 phydev->link = 0;
 637                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 638                         phydev->drv->config_intr(phydev);
 639                 return genphy_config_aneg(phydev);
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 646 {
 647         return 0;
 648 }
 649
 650 /* This routine returns -1 as an indication to the caller that the
 651  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 652  * MMD extended PHY registers.
 653  */
 654 static int
 655 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 656                       int regnum)
 657 {
 658         return -1;
 659 }
 660
 661 /* This routine does nothing since the Micrel ksz9021 does not support
 662  * standard IEEE MMD extended PHY registers.
 663  */
 664 static void
 665 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 666                       int regnum, u32 val)
 667 {
 668 }
 669
 670 static int kszphy_get_sset_count(struct phy_device *phydev)
 671 {
 672         return ARRAY_SIZE(kszphy_hw_stats);
 673 }
 674
 675 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 676 {
 677         int i;
 678
 679         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 680                 strlcpy(data + i * ETH_GSTRING_LEN,
 681                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 682         }
 683 }
 684
 685 #ifndef UINT64_MAX
 686 #define UINT64_MAX              (u64)(~((u64)0))
 687 #endif
 688 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 689 {
 690         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 691         struct kszphy_priv *priv = phydev->priv;
 692         int val;
 693         u64 ret;
 694
 695         val = phy_read(phydev, stat.reg);
 696         if (val < 0) {
 697                 ret = UINT64_MAX;
 698         } else {
 699                 val = val & ((1 << stat.bits) - 1);
 700                 priv->stats[i] += val;
 701                 ret = priv->stats[i];
 702         }
 703
 704         return ret;
 705 }
 706
 707 static void kszphy_get_stats(struct phy_device *phydev,
 708                              struct ethtool_stats *stats, u64 *data)
 709 {
 710         int i;
 711
 712         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 713                 data[i] = kszphy_get_stat(phydev, i);
 714 }
 715
 716 static int kszphy_suspend(struct phy_device *phydev)
 717 {
 718         /* Disable PHY Interrupts */
 719         if (phy_interrupt_is_valid(phydev)) {
 720                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 721                 if (phydev->drv->config_intr)
 722                         phydev->drv->config_intr(phydev);
 723         }
 724
 725         return genphy_suspend(phydev);
 726 }
 727
 728 static int kszphy_resume(struct phy_device *phydev)
 729 {
 730         genphy_resume(phydev);
 731
 732         /* After switching from power-down to normal mode, an internal global
 733          * reset is automatically generated. Wait a minimum of 1 ms before
 734          * read/write access to the PHY registers.
 735          */
 736         usleep_range(1000, 2000);
 737
 738         /* Enable PHY Interrupts */
 739         if (phy_interrupt_is_valid(phydev)) {
 740                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 741                 if (phydev->drv->config_intr)
 742                         phydev->drv->config_intr(phydev);
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int kszphy_probe(struct phy_device *phydev)
 749 {
 750         const struct kszphy_type *type = phydev->drv->driver_data;
 751         const struct device_node *np = phydev->mdio.dev.of_node;
 752         struct kszphy_priv *priv;
 753         struct clk *clk;
 754         int ret;
 755
 756         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 757         if (!priv)
 758                 return -ENOMEM;
 759
 760         phydev->priv = priv;
 761
 762         priv->type = type;
 763
 764         if (type->led_mode_reg) {
 765                 ret = of_property_read_u32(np, "micrel,led-mode",
 766                                 &priv->led_mode);
 767                 if (ret)
 768                         priv->led_mode = -1;
 769
 770                 if (priv->led_mode > 3) {
 771                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 772                                    priv->led_mode);
 773                         priv->led_mode = -1;
 774                 }
 775         } else {
 776                 priv->led_mode = -1;
 777         }
 778
 779         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 780         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 781         if (!IS_ERR_OR_NULL(clk)) {
 782                 unsigned long rate = clk_get_rate(clk);
 783                 bool rmii_ref_clk_sel_25_mhz;
 784
 785                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 786                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 787                                 "micrel,rmii-reference-clock-select-25-mhz");
 788
 789                 if (rate > 24500000 && rate < 25500000) {
 790                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 791                 } else if (rate > 49500000 && rate < 50500000) {
 792                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 793                 } else {
 794                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 795                                    rate);
 796                         return -EINVAL;
 797                 }
 798         }
 799
 800         /* Support legacy board-file configuration */
 801         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 802                 priv->rmii_ref_clk_sel = true;
 803                 priv->rmii_ref_clk_sel_val = true;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static struct phy_driver ksphy_driver[] = {
 810 {
 811         .phy_id         = PHY_ID_KS8737,
 812         .phy_id_mask    = MICREL_PHY_ID_MASK,
 813         .name           = "Micrel KS8737",
 814         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 815         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 816         .driver_data    = &ks8737_type,
 817         .config_init    = kszphy_config_init,
 818         .config_aneg    = genphy_config_aneg,
 819         .read_status    = genphy_read_status,
 820         .ack_interrupt  = kszphy_ack_interrupt,
 821         .config_intr    = kszphy_config_intr,
 822         .suspend        = genphy_suspend,
 823         .resume         = genphy_resume,
 824 }, {
 825         .phy_id         = PHY_ID_KSZ8021,
 826         .phy_id_mask    = 0x00ffffff,
 827         .name           = "Micrel KSZ8021 or KSZ8031",
 828         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 829                            SUPPORTED_Asym_Pause),
 830         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 831         .driver_data    = &ksz8021_type,
 832         .probe          = kszphy_probe,
 833         .config_init    = kszphy_config_init,
 834         .config_aneg    = genphy_config_aneg,
 835         .read_status    = genphy_read_status,
 836         .ack_interrupt  = kszphy_ack_interrupt,
 837         .config_intr    = kszphy_config_intr,
 838         .get_sset_count = kszphy_get_sset_count,
 839         .get_strings    = kszphy_get_strings,
 840         .get_stats      = kszphy_get_stats,
 841         .suspend        = genphy_suspend,
 842         .resume         = genphy_resume,
 843 }, {
 844         .phy_id         = PHY_ID_KSZ8031,
 845         .phy_id_mask    = 0x00ffffff,
 846         .name           = "Micrel KSZ8031",
 847         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 848                            SUPPORTED_Asym_Pause),
 849         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 850         .driver_data    = &ksz8021_type,
 851         .probe          = kszphy_probe,
 852         .config_init    = kszphy_config_init,
 853         .config_aneg    = genphy_config_aneg,
 854         .read_status    = genphy_read_status,
 855         .ack_interrupt  = kszphy_ack_interrupt,
 856         .config_intr    = kszphy_config_intr,
 857         .get_sset_count = kszphy_get_sset_count,
 858         .get_strings    = kszphy_get_strings,
 859         .get_stats      = kszphy_get_stats,
 860         .suspend        = genphy_suspend,
 861         .resume         = genphy_resume,
 862 }, {
 863         .phy_id         = PHY_ID_KSZ8041,
 864         .phy_id_mask    = MICREL_PHY_ID_MASK,
 865         .name           = "Micrel KSZ8041",
 866         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 867                                 | SUPPORTED_Asym_Pause),
 868         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 869         .driver_data    = &ksz8041_type,
 870         .probe          = kszphy_probe,
 871         .config_init    = ksz8041_config_init,
 872         .config_aneg    = ksz8041_config_aneg,
 873         .read_status    = genphy_read_status,
 874         .ack_interrupt  = kszphy_ack_interrupt,
 875         .config_intr    = kszphy_config_intr,
 876         .get_sset_count = kszphy_get_sset_count,
 877         .get_strings    = kszphy_get_strings,
 878         .get_stats      = kszphy_get_stats,
 879         /* No suspend/resume callbacks because of errata DS80000700A,
 880          * receiver error following software power down.
 881          */
 882 }, {
 883         .phy_id         = PHY_ID_KSZ8041RNLI,
 884         .phy_id_mask    = MICREL_PHY_ID_MASK,
 885         .name           = "Micrel KSZ8041RNLI",
 886         .features       = PHY_BASIC_FEATURES |
 887                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 888         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 889         .driver_data    = &ksz8041_type,
 890         .probe          = kszphy_probe,
 891         .config_init    = kszphy_config_init,
 892         .config_aneg    = genphy_config_aneg,
 893         .read_status    = genphy_read_status,
 894         .ack_interrupt  = kszphy_ack_interrupt,
 895         .config_intr    = kszphy_config_intr,
 896         .get_sset_count = kszphy_get_sset_count,
 897         .get_strings    = kszphy_get_strings,
 898         .get_stats      = kszphy_get_stats,
 899         .suspend        = genphy_suspend,
 900         .resume         = genphy_resume,
 901 }, {
 902         .phy_id         = PHY_ID_KSZ8051,
 903         .phy_id_mask    = MICREL_PHY_ID_MASK,
 904         .name           = "Micrel KSZ8051",
 905         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 906                                 | SUPPORTED_Asym_Pause),
 907         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 908         .driver_data    = &ksz8051_type,
 909         .probe          = kszphy_probe,
 910         .config_init    = kszphy_config_init,
 911         .config_aneg    = genphy_config_aneg,
 912         .read_status    = genphy_read_status,
 913         .ack_interrupt  = kszphy_ack_interrupt,
 914         .config_intr    = kszphy_config_intr,
 915         .get_sset_count = kszphy_get_sset_count,
 916         .get_strings    = kszphy_get_strings,
 917         .get_stats      = kszphy_get_stats,
 918         .suspend        = genphy_suspend,
 919         .resume         = genphy_resume,
 920 }, {
 921         .phy_id         = PHY_ID_KSZ8001,
 922         .name           = "Micrel KSZ8001 or KS8721",
 923         .phy_id_mask    = 0x00fffffc,
 924         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 925         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 926         .driver_data    = &ksz8041_type,
 927         .probe          = kszphy_probe,
 928         .config_init    = kszphy_config_init,
 929         .config_aneg    = genphy_config_aneg,
 930         .read_status    = genphy_read_status,
 931         .ack_interrupt  = kszphy_ack_interrupt,
 932         .config_intr    = kszphy_config_intr,
 933         .get_sset_count = kszphy_get_sset_count,
 934         .get_strings    = kszphy_get_strings,
 935         .get_stats      = kszphy_get_stats,
 936         .suspend        = genphy_suspend,
 937         .resume         = genphy_resume,
 938 }, {
 939         .phy_id         = PHY_ID_KSZ8081,
 940         .name           = "Micrel KSZ8081 or KSZ8091",
 941         .phy_id_mask    = MICREL_PHY_ID_MASK,
 942         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 943         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 944         .driver_data    = &ksz8081_type,
 945         .probe          = kszphy_probe,
 946         .config_init    = kszphy_config_init,
 947         .config_aneg    = genphy_config_aneg,
 948         .read_status    = genphy_read_status,
 949         .ack_interrupt  = kszphy_ack_interrupt,
 950         .config_intr    = kszphy_config_intr,
 951         .get_sset_count = kszphy_get_sset_count,
 952         .get_strings    = kszphy_get_strings,
 953         .get_stats      = kszphy_get_stats,
 954         .suspend        = kszphy_suspend,
 955         .resume         = kszphy_resume,
 956 }, {
 957         .phy_id         = PHY_ID_KSZ8061,
 958         .name           = "Micrel KSZ8061",
 959         .phy_id_mask    = MICREL_PHY_ID_MASK,
 960         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 961         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 962         .config_init    = ksz8061_config_init,
 963         .config_aneg    = genphy_config_aneg,
 964         .read_status    = genphy_read_status,
 965         .ack_interrupt  = kszphy_ack_interrupt,
 966         .config_intr    = kszphy_config_intr,
 967         .suspend        = genphy_suspend,
 968         .resume         = genphy_resume,
 969 }, {
 970         .phy_id         = PHY_ID_KSZ9021,
 971         .phy_id_mask    = 0x000ffffe,
 972         .name           = "Micrel KSZ9021 Gigabit PHY",
 973         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 974         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 975         .driver_data    = &ksz9021_type,
 976         .probe          = kszphy_probe,
 977         .config_init    = ksz9021_config_init,
 978         .config_aneg    = genphy_config_aneg,
 979         .read_status    = genphy_read_status,
 980         .ack_interrupt  = kszphy_ack_interrupt,
 981         .config_intr    = kszphy_config_intr,
 982         .get_sset_count = kszphy_get_sset_count,
 983         .get_strings    = kszphy_get_strings,
 984         .get_stats      = kszphy_get_stats,
 985         .suspend        = genphy_suspend,
 986         .resume         = genphy_resume,
 987         .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
 988         .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
 989 }, {
 990         .phy_id         = PHY_ID_KSZ9031,
 991         .phy_id_mask    = MICREL_PHY_ID_MASK,
 992         .name           = "Micrel KSZ9031 Gigabit PHY",
 993         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 994         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 995         .driver_data    = &ksz9021_type,
 996         .probe          = kszphy_probe,
 997         .config_init    = ksz9031_config_init,
 998         .config_aneg    = genphy_config_aneg,
 999         .read_status    = ksz9031_read_status,
1000         .ack_interrupt  = kszphy_ack_interrupt,
1001         .config_intr    = kszphy_config_intr,
1002         .get_sset_count = kszphy_get_sset_count,
1003         .get_strings    = kszphy_get_strings,
1004         .get_stats      = kszphy_get_stats,
1005         .suspend        = genphy_suspend,
1006         .resume         = kszphy_resume,
1007 }, {
1008         .phy_id         = PHY_ID_KSZ8873MLL,
1009         .phy_id_mask    = MICREL_PHY_ID_MASK,
1010         .name           = "Micrel KSZ8873MLL Switch",
1011         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
1012         .flags          = PHY_HAS_MAGICANEG,
1013         .config_init    = kszphy_config_init,
1014         .config_aneg    = ksz8873mll_config_aneg,
1015         .read_status    = ksz8873mll_read_status,
1016         .suspend        = genphy_suspend,
1017         .resume         = genphy_resume,
1018 }, {
1019         .phy_id         = PHY_ID_KSZ886X,
1020         .phy_id_mask    = MICREL_PHY_ID_MASK,
1021         .name           = "Micrel KSZ886X Switch",
1022         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
1023         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1024         .config_init    = kszphy_config_init,
1025         .config_aneg    = genphy_config_aneg,
1026         .read_status    = genphy_read_status,
1027         .suspend        = genphy_suspend,
1028         .resume         = genphy_resume,
1029 }, {
1030         .phy_id         = PHY_ID_KSZ8795,
1031         .phy_id_mask    = MICREL_PHY_ID_MASK,
1032         .name           = "Micrel KSZ8795",
1033         .features       = PHY_BASIC_FEATURES,
1034         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1035         .config_init    = kszphy_config_init,
1036         .config_aneg    = ksz8873mll_config_aneg,
1037         .read_status    = ksz8873mll_read_status,
1038         .suspend        = genphy_suspend,
1039         .resume         = genphy_resume,
1040 } };
1041
1042 module_phy_driver(ksphy_driver);
1043
1044 MODULE_DESCRIPTION("Micrel PHY driver");
1045 MODULE_AUTHOR("David J. Choi");
1046 MODULE_LICENSE("GPL");
1047
1048 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1049         { PHY_ID_KSZ9021, 0x000ffffe },
1050         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1051         { PHY_ID_KSZ8001, 0x00fffffc },
1052         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1053         { PHY_ID_KSZ8021, 0x00ffffff },
1054         { PHY_ID_KSZ8031, 0x00ffffff },
1055         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1056         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1057         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1058         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1059         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1060         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1061         { }
1062 };
1063
1064 MODULE_DEVICE_TABLE(mdio, micrel_tbl);