drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31 #include <uapi/linux/mdio.h>
  32
  33 /* Operation Mode Strap Override */
  34 #define MII_KSZPHY_OMSO                         0x16
  35 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  36 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  37 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  38 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  39
  40 /* general Interrupt control/status reg in vendor specific block. */
  41 #define MII_KSZPHY_INTCS                        0x1B
  42 #define KSZPHY_INTCS_JABBER                     BIT(15)
  43 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  44 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  45 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  46 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  47 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  48 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  49 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  50 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  51                                                 KSZPHY_INTCS_LINK_DOWN)
  52
  53 /* PHY Control 1 */
  54 #define MII_KSZPHY_CTRL_1                       0x1e
  55
  56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  57 #define MII_KSZPHY_CTRL_2                       0x1f
  58 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  59 /* bitmap of PHY register to set interrupt mode */
  60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  61 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  62
  63 /* Write/read to/from extended registers */
  64 #define MII_KSZPHY_EXTREG                       0x0b
  65 #define KSZPHY_EXTREG_WRITE                     0x8000
  66
  67 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  68 #define MII_KSZPHY_EXTREG_READ                  0x0d
  69
  70 /* Extended registers */
  71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  72 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  73 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  74
  75 #define PS_TO_REG                               200
  76
  77 struct kszphy_type {
  78         u32 led_mode_reg;
  79         u16 interrupt_level_mask;
  80         bool has_broadcast_disable;
  81         bool has_nand_tree_disable;
  82         bool has_rmii_ref_clk_sel;
  83 };
  84
  85 struct kszphy_priv {
  86         const struct kszphy_type *type;
  87         int led_mode;
  88         bool rmii_ref_clk_sel;
  89         bool rmii_ref_clk_sel_val;
  90 };
  91
  92 static const struct kszphy_type ksz8021_type = {
  93         .led_mode_reg           = MII_KSZPHY_CTRL_2,
  94         .has_broadcast_disable  = true,
  95         .has_nand_tree_disable  = true,
  96         .has_rmii_ref_clk_sel   = true,
  97 };
  98
  99 static const struct kszphy_type ksz8041_type = {
 100         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 101 };
 102
 103 static const struct kszphy_type ksz8051_type = {
 104         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 105         .has_nand_tree_disable  = true,
 106 };
 107
 108 static const struct kszphy_type ksz8081_type = {
 109         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 110         .has_broadcast_disable  = true,
 111         .has_nand_tree_disable  = true,
 112         .has_rmii_ref_clk_sel   = true,
 113 };
 114
 115 static const struct kszphy_type ks8737_type = {
 116         .interrupt_level_mask   = BIT(14),
 117 };
 118
 119 static const struct kszphy_type ksz9021_type = {
 120         .interrupt_level_mask   = BIT(14),
 121 };
 122
 123 static int kszphy_extended_write(struct phy_device *phydev,
 124                                 u32 regnum, u16 val)
 125 {
 126         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 127         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 128 }
 129
 130 static int kszphy_extended_read(struct phy_device *phydev,
 131                                 u32 regnum)
 132 {
 133         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 134         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 135 }
 136
 137 static int kszphy_ack_interrupt(struct phy_device *phydev)
 138 {
 139         /* bit[7..0] int status, which is a read and clear register. */
 140         int rc;
 141
 142         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 143
 144         return (rc < 0) ? rc : 0;
 145 }
 146
 147 static int kszphy_config_intr(struct phy_device *phydev)
 148 {
 149         const struct kszphy_type *type = phydev->drv->driver_data;
 150         int temp;
 151         u16 mask;
 152
 153         if (type && type->interrupt_level_mask)
 154                 mask = type->interrupt_level_mask;
 155         else
 156                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 157
 158         /* set the interrupt pin active low */
 159         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 160         if (temp < 0)
 161                 return temp;
 162         temp &= ~mask;
 163         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 164
 165         /* enable / disable interrupts */
 166         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 167                 temp = KSZPHY_INTCS_ALL;
 168         else
 169                 temp = 0;
 170
 171         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 172 }
 173
 174 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 175 {
 176         int ctrl;
 177
 178         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 179         if (ctrl < 0)
 180                 return ctrl;
 181
 182         if (val)
 183                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 184         else
 185                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 186
 187         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 188 }
 189
 190 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 191 {
 192         int rc, temp, shift;
 193
 194         switch (reg) {
 195         case MII_KSZPHY_CTRL_1:
 196                 shift = 14;
 197                 break;
 198         case MII_KSZPHY_CTRL_2:
 199                 shift = 4;
 200                 break;
 201         default:
 202                 return -EINVAL;
 203         }
 204
 205         temp = phy_read(phydev, reg);
 206         if (temp < 0) {
 207                 rc = temp;
 208                 goto out;
 209         }
 210
 211         temp &= ~(3 << shift);
 212         temp |= val << shift;
 213         rc = phy_write(phydev, reg, temp);
 214 out:
 215         if (rc < 0)
 216                 dev_err(&phydev->dev, "failed to set led mode\n");
 217
 218         return rc;
 219 }
 220
 221 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 222  * unique (non-broadcast) address on a shared bus.
 223  */
 224 static int kszphy_broadcast_disable(struct phy_device *phydev)
 225 {
 226         int ret;
 227
 228         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 229         if (ret < 0)
 230                 goto out;
 231
 232         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 233 out:
 234         if (ret)
 235                 dev_err(&phydev->dev, "failed to disable broadcast address\n");
 236
 237         return ret;
 238 }
 239
 240 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 241 {
 242         int ret;
 243
 244         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 245         if (ret < 0)
 246                 goto out;
 247
 248         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 249                 return 0;
 250
 251         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 252                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 253 out:
 254         if (ret)
 255                 dev_err(&phydev->dev, "failed to disable NAND tree mode\n");
 256
 257         return ret;
 258 }
 259
 260 static int kszphy_config_init(struct phy_device *phydev)
 261 {
 262         struct kszphy_priv *priv = phydev->priv;
 263         const struct kszphy_type *type;
 264         int ret;
 265
 266         if (!priv)
 267                 return 0;
 268
 269         type = priv->type;
 270
 271         if (type->has_broadcast_disable)
 272                 kszphy_broadcast_disable(phydev);
 273
 274         if (type->has_nand_tree_disable)
 275                 kszphy_nand_tree_disable(phydev);
 276
 277         if (priv->rmii_ref_clk_sel) {
 278                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 279                 if (ret) {
 280                         dev_err(&phydev->dev, "failed to set rmii reference clock\n");
 281                         return ret;
 282                 }
 283         }
 284
 285         if (priv->led_mode >= 0)
 286                 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
 287
 288         return 0;
 289 }
 290
 291 static int ksz8061_config_init(struct phy_device *phydev)
 292 {
 293         int ret;
 294
 295         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 296         if (ret)
 297                 return ret;
 298
 299         return kszphy_config_init(phydev);
 300 }
 301
 302 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 303                                        const struct device_node *of_node,
 304                                        u16 reg,
 305                                        const char *field1, const char *field2,
 306                                        const char *field3, const char *field4)
 307 {
 308         int val1 = -1;
 309         int val2 = -2;
 310         int val3 = -3;
 311         int val4 = -4;
 312         int newval;
 313         int matches = 0;
 314
 315         if (!of_property_read_u32(of_node, field1, &val1))
 316                 matches++;
 317
 318         if (!of_property_read_u32(of_node, field2, &val2))
 319                 matches++;
 320
 321         if (!of_property_read_u32(of_node, field3, &val3))
 322                 matches++;
 323
 324         if (!of_property_read_u32(of_node, field4, &val4))
 325                 matches++;
 326
 327         if (!matches)
 328                 return 0;
 329
 330         if (matches < 4)
 331                 newval = kszphy_extended_read(phydev, reg);
 332         else
 333                 newval = 0;
 334
 335         if (val1 != -1)
 336                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 337
 338         if (val2 != -2)
 339                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 340
 341         if (val3 != -3)
 342                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 343
 344         if (val4 != -4)
 345                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 346
 347         return kszphy_extended_write(phydev, reg, newval);
 348 }
 349
 350 static int ksz9021_config_init(struct phy_device *phydev)
 351 {
 352         const struct device *dev = &phydev->dev;
 353         const struct device_node *of_node = dev->of_node;
 354         const struct device *dev_walker;
 355
 356         /* The Micrel driver has a deprecated option to place phy OF
 357          * properties in the MAC node. Walk up the tree of devices to
 358          * find a device with an OF node.
 359          */
 360         dev_walker = &phydev->dev;
 361         do {
 362                 of_node = dev_walker->of_node;
 363                 dev_walker = dev_walker->parent;
 364
 365         } while (!of_node && dev_walker);
 366
 367         if (of_node) {
 368                 ksz9021_load_values_from_of(phydev, of_node,
 369                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 370                                     "txen-skew-ps", "txc-skew-ps",
 371                                     "rxdv-skew-ps", "rxc-skew-ps");
 372                 ksz9021_load_values_from_of(phydev, of_node,
 373                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 374                                     "rxd0-skew-ps", "rxd1-skew-ps",
 375                                     "rxd2-skew-ps", "rxd3-skew-ps");
 376                 ksz9021_load_values_from_of(phydev, of_node,
 377                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 378                                     "txd0-skew-ps", "txd1-skew-ps",
 379                                     "txd2-skew-ps", "txd3-skew-ps");
 380         }
 381         return 0;
 382 }
 383
 384 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 385 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 386 #define OP_DATA                         1
 387 #define KSZ9031_PS_TO_REG               60
 388
 389 /* Extended registers */
 390 /* MMD Address 0x0 */
 391 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 392 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 393
 394 /* MMD Address 0x2 */
 395 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 396 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 397 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 398 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 399
 400 static int ksz9031_extended_write(struct phy_device *phydev,
 401                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 402 {
 403         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 404         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 405         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 406         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 407 }
 408
 409 static int ksz9031_extended_read(struct phy_device *phydev,
 410                                  u8 mode, u32 dev_addr, u32 regnum)
 411 {
 412         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 413         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 414         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 415         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 416 }
 417
 418 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 419                                        const struct device_node *of_node,
 420                                        u16 reg, size_t field_sz,
 421                                        const char *field[], u8 numfields)
 422 {
 423         int val[4] = {-1, -2, -3, -4};
 424         int matches = 0;
 425         u16 mask;
 426         u16 maxval;
 427         u16 newval;
 428         int i;
 429
 430         for (i = 0; i < numfields; i++)
 431                 if (!of_property_read_u32(of_node, field[i], val + i))
 432                         matches++;
 433
 434         if (!matches)
 435                 return 0;
 436
 437         if (matches < numfields)
 438                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 439         else
 440                 newval = 0;
 441
 442         maxval = (field_sz == 4) ? 0xf : 0x1f;
 443         for (i = 0; i < numfields; i++)
 444                 if (val[i] != -(i + 1)) {
 445                         mask = 0xffff;
 446                         mask ^= maxval << (field_sz * i);
 447                         newval = (newval & mask) |
 448                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 449                                         << (field_sz * i));
 450                 }
 451
 452         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 453 }
 454
 455 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 456 {
 457         int result;
 458
 459         /* Center KSZ9031RNX FLP timing at 16ms. */
 460         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 461                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 462         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 463                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 464
 465         if (result)
 466                 return result;
 467
 468         return genphy_restart_aneg(phydev);
 469 }
 470
 471 static int ksz9031_config_init(struct phy_device *phydev)
 472 {
 473         const struct device *dev = &phydev->dev;
 474         const struct device_node *of_node = dev->of_node;
 475         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 476         static const char *rx_data_skews[4] = {
 477                 "rxd0-skew-ps", "rxd1-skew-ps",
 478                 "rxd2-skew-ps", "rxd3-skew-ps"
 479         };
 480         static const char *tx_data_skews[4] = {
 481                 "txd0-skew-ps", "txd1-skew-ps",
 482                 "txd2-skew-ps", "txd3-skew-ps"
 483         };
 484         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 485         const struct device *dev_walker;
 486
 487         /* The Micrel driver has a deprecated option to place phy OF
 488          * properties in the MAC node. Walk up the tree of devices to
 489          * find a device with an OF node.
 490          */
 491         dev_walker = &phydev->dev;
 492         do {
 493                 of_node = dev_walker->of_node;
 494                 dev_walker = dev_walker->parent;
 495         } while (!of_node && dev_walker);
 496
 497         if (of_node) {
 498                 ksz9031_of_load_skew_values(phydev, of_node,
 499                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 500                                 clk_skews, 2);
 501
 502                 ksz9031_of_load_skew_values(phydev, of_node,
 503                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 504                                 control_skews, 2);
 505
 506                 ksz9031_of_load_skew_values(phydev, of_node,
 507                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 508                                 rx_data_skews, 4);
 509
 510                 ksz9031_of_load_skew_values(phydev, of_node,
 511                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 512                                 tx_data_skews, 4);
 513         }
 514
 515         return ksz9031_center_flp_timing(phydev);
 516 }
 517
 518 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 519 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 520 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 521 static int ksz8873mll_read_status(struct phy_device *phydev)
 522 {
 523         int regval;
 524
 525         /* dummy read */
 526         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 527
 528         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 529
 530         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 531                 phydev->duplex = DUPLEX_HALF;
 532         else
 533                 phydev->duplex = DUPLEX_FULL;
 534
 535         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 536                 phydev->speed = SPEED_10;
 537         else
 538                 phydev->speed = SPEED_100;
 539
 540         phydev->link = 1;
 541         phydev->pause = phydev->asym_pause = 0;
 542
 543         return 0;
 544 }
 545
 546 static int ksz9031_read_status(struct phy_device *phydev)
 547 {
 548         int err;
 549         int regval;
 550
 551         err = genphy_read_status(phydev);
 552         if (err)
 553                 return err;
 554
 555         /* Make sure the PHY is not broken. Read idle error count,
 556          * and reset the PHY if it is maxed out.
 557          */
 558         regval = phy_read(phydev, MII_STAT1000);
 559         if ((regval & 0xFF) == 0xFF) {
 560                 phy_init_hw(phydev);
 561                 phydev->link = 0;
 562                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 563                         phydev->drv->config_intr(phydev);
 564                 return genphy_config_aneg(phydev);
 565         }
 566
 567         return 0;
 568 }
 569
 570 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 571 {
 572         return 0;
 573 }
 574
 575 /* This routine returns -1 as an indication to the caller that the
 576  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 577  * MMD extended PHY registers.
 578  */
 579 static int
 580 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 581                       int regnum)
 582 {
 583         return -1;
 584 }
 585
 586 /* This routine does nothing since the Micrel ksz9021 does not support
 587  * standard IEEE MMD extended PHY registers.
 588  */
 589 static void
 590 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 591                       int regnum, u32 val)
 592 {
 593 }
 594
 595 static int kszphy_resume(struct phy_device *phydev)
 596 {
 597         int value;
 598
 599         mutex_lock(&phydev->lock);
 600
 601         value = phy_read(phydev, MII_BMCR);
 602         phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
 603
 604         kszphy_config_intr(phydev);
 605         mutex_unlock(&phydev->lock);
 606
 607         return 0;
 608 }
 609
 610 static int kszphy_probe(struct phy_device *phydev)
 611 {
 612         const struct kszphy_type *type = phydev->drv->driver_data;
 613         const struct device_node *np = phydev->dev.of_node;
 614         struct kszphy_priv *priv;
 615         struct clk *clk;
 616         int ret;
 617
 618         priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
 619         if (!priv)
 620                 return -ENOMEM;
 621
 622         phydev->priv = priv;
 623
 624         priv->type = type;
 625
 626         if (type->led_mode_reg) {
 627                 ret = of_property_read_u32(np, "micrel,led-mode",
 628                                 &priv->led_mode);
 629                 if (ret)
 630                         priv->led_mode = -1;
 631
 632                 if (priv->led_mode > 3) {
 633                         dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
 634                                         priv->led_mode);
 635                         priv->led_mode = -1;
 636                 }
 637         } else {
 638                 priv->led_mode = -1;
 639         }
 640
 641         clk = devm_clk_get(&phydev->dev, "rmii-ref");
 642         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 643         if (!IS_ERR_OR_NULL(clk)) {
 644                 unsigned long rate = clk_get_rate(clk);
 645                 bool rmii_ref_clk_sel_25_mhz;
 646
 647                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 648                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 649                                 "micrel,rmii-reference-clock-select-25-mhz");
 650
 651                 if (rate > 24500000 && rate < 25500000) {
 652                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 653                 } else if (rate > 49500000 && rate < 50500000) {
 654                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 655                 } else {
 656                         dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
 657                         return -EINVAL;
 658                 }
 659         }
 660
 661         /* Support legacy board-file configuration */
 662         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 663                 priv->rmii_ref_clk_sel = true;
 664                 priv->rmii_ref_clk_sel_val = true;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static struct phy_driver ksphy_driver[] = {
 671 {
 672         .phy_id         = PHY_ID_KS8737,
 673         .phy_id_mask    = 0x00fffff0,
 674         .name           = "Micrel KS8737",
 675         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 676         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 677         .driver_data    = &ks8737_type,
 678         .config_init    = kszphy_config_init,
 679         .config_aneg    = genphy_config_aneg,
 680         .read_status    = genphy_read_status,
 681         .ack_interrupt  = kszphy_ack_interrupt,
 682         .config_intr    = kszphy_config_intr,
 683         .suspend        = genphy_suspend,
 684         .resume         = genphy_resume,
 685         .driver         = { .owner = THIS_MODULE,},
 686 }, {
 687         .phy_id         = PHY_ID_KSZ8021,
 688         .phy_id_mask    = 0x00ffffff,
 689         .name           = "Micrel KSZ8021 or KSZ8031",
 690         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 691                            SUPPORTED_Asym_Pause),
 692         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 693         .driver_data    = &ksz8021_type,
 694         .probe          = kszphy_probe,
 695         .config_init    = kszphy_config_init,
 696         .config_aneg    = genphy_config_aneg,
 697         .read_status    = genphy_read_status,
 698         .ack_interrupt  = kszphy_ack_interrupt,
 699         .config_intr    = kszphy_config_intr,
 700         .suspend        = genphy_suspend,
 701         .resume         = genphy_resume,
 702         .driver         = { .owner = THIS_MODULE,},
 703 }, {
 704         .phy_id         = PHY_ID_KSZ8031,
 705         .phy_id_mask    = 0x00ffffff,
 706         .name           = "Micrel KSZ8031",
 707         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 708                            SUPPORTED_Asym_Pause),
 709         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 710         .driver_data    = &ksz8021_type,
 711         .probe          = kszphy_probe,
 712         .config_init    = kszphy_config_init,
 713         .config_aneg    = genphy_config_aneg,
 714         .read_status    = genphy_read_status,
 715         .ack_interrupt  = kszphy_ack_interrupt,
 716         .config_intr    = kszphy_config_intr,
 717         .suspend        = genphy_suspend,
 718         .resume         = genphy_resume,
 719         .driver         = { .owner = THIS_MODULE,},
 720 }, {
 721         .phy_id         = PHY_ID_KSZ8041,
 722         .phy_id_mask    = 0x00fffff0,
 723         .name           = "Micrel KSZ8041",
 724         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 725                                 | SUPPORTED_Asym_Pause),
 726         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 727         .driver_data    = &ksz8041_type,
 728         .probe          = kszphy_probe,
 729         .config_init    = kszphy_config_init,
 730         .config_aneg    = genphy_config_aneg,
 731         .read_status    = genphy_read_status,
 732         .ack_interrupt  = kszphy_ack_interrupt,
 733         .config_intr    = kszphy_config_intr,
 734         .suspend        = genphy_suspend,
 735         .resume         = genphy_resume,
 736         .driver         = { .owner = THIS_MODULE,},
 737 }, {
 738         .phy_id         = PHY_ID_KSZ8041RNLI,
 739         .phy_id_mask    = 0x00fffff0,
 740         .name           = "Micrel KSZ8041RNLI",
 741         .features       = PHY_BASIC_FEATURES |
 742                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 743         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 744         .driver_data    = &ksz8041_type,
 745         .probe          = kszphy_probe,
 746         .config_init    = kszphy_config_init,
 747         .config_aneg    = genphy_config_aneg,
 748         .read_status    = genphy_read_status,
 749         .ack_interrupt  = kszphy_ack_interrupt,
 750         .config_intr    = kszphy_config_intr,
 751         .suspend        = genphy_suspend,
 752         .resume         = genphy_resume,
 753         .driver         = { .owner = THIS_MODULE,},
 754 }, {
 755         .phy_id         = PHY_ID_KSZ8051,
 756         .phy_id_mask    = 0x00fffff0,
 757         .name           = "Micrel KSZ8051",
 758         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 759                                 | SUPPORTED_Asym_Pause),
 760         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 761         .driver_data    = &ksz8051_type,
 762         .probe          = kszphy_probe,
 763         .config_init    = kszphy_config_init,
 764         .config_aneg    = genphy_config_aneg,
 765         .read_status    = genphy_read_status,
 766         .ack_interrupt  = kszphy_ack_interrupt,
 767         .config_intr    = kszphy_config_intr,
 768         .suspend        = genphy_suspend,
 769         .resume         = genphy_resume,
 770         .driver         = { .owner = THIS_MODULE,},
 771 }, {
 772         .phy_id         = PHY_ID_KSZ8001,
 773         .name           = "Micrel KSZ8001 or KS8721",
 774         .phy_id_mask    = 0x00ffffff,
 775         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 776         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 777         .driver_data    = &ksz8041_type,
 778         .probe          = kszphy_probe,
 779         .config_init    = kszphy_config_init,
 780         .config_aneg    = genphy_config_aneg,
 781         .read_status    = genphy_read_status,
 782         .ack_interrupt  = kszphy_ack_interrupt,
 783         .config_intr    = kszphy_config_intr,
 784         .suspend        = genphy_suspend,
 785         .resume         = genphy_resume,
 786         .driver         = { .owner = THIS_MODULE,},
 787 }, {
 788         .phy_id         = PHY_ID_KSZ8081,
 789         .name           = "Micrel KSZ8081 or KSZ8091",
 790         .phy_id_mask    = 0x00fffff0,
 791         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 792         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 793         .driver_data    = &ksz8081_type,
 794         .probe          = kszphy_probe,
 795         .config_init    = kszphy_config_init,
 796         .config_aneg    = genphy_config_aneg,
 797         .read_status    = genphy_read_status,
 798         .ack_interrupt  = kszphy_ack_interrupt,
 799         .config_intr    = kszphy_config_intr,
 800         .suspend        = genphy_suspend,
 801         .resume         = kszphy_resume,
 802         .driver         = { .owner = THIS_MODULE,},
 803 }, {
 804         .phy_id         = PHY_ID_KSZ8061,
 805         .name           = "Micrel KSZ8061",
 806         .phy_id_mask    = 0x00fffff0,
 807         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 808         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 809         .config_init    = ksz8061_config_init,
 810         .config_aneg    = genphy_config_aneg,
 811         .read_status    = genphy_read_status,
 812         .ack_interrupt  = kszphy_ack_interrupt,
 813         .config_intr    = kszphy_config_intr,
 814         .suspend        = genphy_suspend,
 815         .resume         = genphy_resume,
 816         .driver         = { .owner = THIS_MODULE,},
 817 }, {
 818         .phy_id         = PHY_ID_KSZ9021,
 819         .phy_id_mask    = 0x000ffffe,
 820         .name           = "Micrel KSZ9021 Gigabit PHY",
 821         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 822         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 823         .driver_data    = &ksz9021_type,
 824         .config_init    = ksz9021_config_init,
 825         .config_aneg    = genphy_config_aneg,
 826         .read_status    = genphy_read_status,
 827         .ack_interrupt  = kszphy_ack_interrupt,
 828         .config_intr    = kszphy_config_intr,
 829         .suspend        = genphy_suspend,
 830         .resume         = genphy_resume,
 831         .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
 832         .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
 833         .driver         = { .owner = THIS_MODULE, },
 834 }, {
 835         .phy_id         = PHY_ID_KSZ9031,
 836         .phy_id_mask    = 0x00fffff0,
 837         .name           = "Micrel KSZ9031 Gigabit PHY",
 838         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 839         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 840         .driver_data    = &ksz9021_type,
 841         .config_init    = ksz9031_config_init,
 842         .config_aneg    = genphy_config_aneg,
 843         .read_status    = ksz9031_read_status,
 844         .ack_interrupt  = kszphy_ack_interrupt,
 845         .config_intr    = kszphy_config_intr,
 846         .suspend        = genphy_suspend,
 847         .resume         = genphy_resume,
 848         .driver         = { .owner = THIS_MODULE, },
 849 }, {
 850         .phy_id         = PHY_ID_KSZ8873MLL,
 851         .phy_id_mask    = 0x00fffff0,
 852         .name           = "Micrel KSZ8873MLL Switch",
 853         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
 854         .flags          = PHY_HAS_MAGICANEG,
 855         .config_init    = kszphy_config_init,
 856         .config_aneg    = ksz8873mll_config_aneg,
 857         .read_status    = ksz8873mll_read_status,
 858         .suspend        = genphy_suspend,
 859         .resume         = genphy_resume,
 860         .driver         = { .owner = THIS_MODULE, },
 861 }, {
 862         .phy_id         = PHY_ID_KSZ886X,
 863         .phy_id_mask    = 0x00fffff0,
 864         .name           = "Micrel KSZ886X Switch",
 865         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 866         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 867         .config_init    = kszphy_config_init,
 868         .config_aneg    = genphy_config_aneg,
 869         .read_status    = genphy_read_status,
 870         .suspend        = genphy_suspend,
 871         .resume         = genphy_resume,
 872         .driver         = { .owner = THIS_MODULE, },
 873 } };
 874
 875 module_phy_driver(ksphy_driver);
 876
 877 MODULE_DESCRIPTION("Micrel PHY driver");
 878 MODULE_AUTHOR("David J. Choi");
 879 MODULE_LICENSE("GPL");
 880
 881 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
 882         { PHY_ID_KSZ9021, 0x000ffffe },
 883         { PHY_ID_KSZ9031, 0x00fffff0 },
 884         { PHY_ID_KSZ8001, 0x00ffffff },
 885         { PHY_ID_KS8737, 0x00fffff0 },
 886         { PHY_ID_KSZ8021, 0x00ffffff },
 887         { PHY_ID_KSZ8031, 0x00ffffff },
 888         { PHY_ID_KSZ8041, 0x00fffff0 },
 889         { PHY_ID_KSZ8051, 0x00fffff0 },
 890         { PHY_ID_KSZ8061, 0x00fffff0 },
 891         { PHY_ID_KSZ8081, 0x00fffff0 },
 892         { PHY_ID_KSZ8873MLL, 0x00fffff0 },
 893         { PHY_ID_KSZ886X, 0x00fffff0 },
 894         { }
 895 };
 896
 897 MODULE_DEVICE_TABLE(mdio, micrel_tbl);