drivers/net/phy/vitesse.c

   1 /*
   2  * Driver for Vitesse PHYs
   3  *
   4  * Author: Kriston Carson
   5  *
   6  * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20
  21 /* Vitesse Extended Page Magic Register(s) */
  22 #define MII_VSC82X4_EXT_PAGE_16E        0x10
  23 #define MII_VSC82X4_EXT_PAGE_17E        0x11
  24 #define MII_VSC82X4_EXT_PAGE_18E        0x12
  25
  26 /* Vitesse Extended Control Register 1 */
  27 #define MII_VSC8244_EXT_CON1           0x17
  28 #define MII_VSC8244_EXTCON1_INIT       0x0000
  29 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK        0x0c00
  30 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK        0x0300
  31 #define MII_VSC8244_EXTCON1_TX_SKEW     0x0800
  32 #define MII_VSC8244_EXTCON1_RX_SKEW     0x0200
  33
  34 /* Vitesse Interrupt Mask Register */
  35 #define MII_VSC8244_IMASK               0x19
  36 #define MII_VSC8244_IMASK_IEN           0x8000
  37 #define MII_VSC8244_IMASK_SPEED         0x4000
  38 #define MII_VSC8244_IMASK_LINK          0x2000
  39 #define MII_VSC8244_IMASK_DUPLEX        0x1000
  40 #define MII_VSC8244_IMASK_MASK          0xf000
  41
  42 #define MII_VSC8221_IMASK_MASK          0xa000
  43
  44 /* Vitesse Interrupt Status Register */
  45 #define MII_VSC8244_ISTAT               0x1a
  46 #define MII_VSC8244_ISTAT_STATUS        0x8000
  47 #define MII_VSC8244_ISTAT_SPEED         0x4000
  48 #define MII_VSC8244_ISTAT_LINK          0x2000
  49 #define MII_VSC8244_ISTAT_DUPLEX        0x1000
  50
  51 /* Vitesse Auxiliary Control/Status Register */
  52 #define MII_VSC8244_AUX_CONSTAT         0x1c
  53 #define MII_VSC8244_AUXCONSTAT_INIT     0x0000
  54 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
  55 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
  56 #define MII_VSC8244_AUXCONSTAT_GBIT     0x0010
  57 #define MII_VSC8244_AUXCONSTAT_100      0x0008
  58
  59 #define MII_VSC8221_AUXCONSTAT_INIT     0x0004 /* need to set this bit? */
  60 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  61
  62 /* Vitesse Extended Page Access Register */
  63 #define MII_VSC82X4_EXT_PAGE_ACCESS     0x1f
  64
  65 /* Vitesse VSC8601 Extended PHY Control Register 1 */
  66 #define MII_VSC8601_EPHY_CTL            0x17
  67 #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
  68
  69 #define PHY_ID_VSC8234                  0x000fc620
  70 #define PHY_ID_VSC8244                  0x000fc6c0
  71 #define PHY_ID_VSC8514                  0x00070670
  72 #define PHY_ID_VSC8574                  0x000704a0
  73 #define PHY_ID_VSC8601                  0x00070420
  74 #define PHY_ID_VSC8662                  0x00070660
  75 #define PHY_ID_VSC8221                  0x000fc550
  76 #define PHY_ID_VSC8211                  0x000fc4b0
  77
  78 MODULE_DESCRIPTION("Vitesse PHY driver");
  79 MODULE_AUTHOR("Kriston Carson");
  80 MODULE_LICENSE("GPL");
  81
  82 static int vsc824x_add_skew(struct phy_device *phydev)
  83 {
  84         int err;
  85         int extcon;
  86
  87         extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  88
  89         if (extcon < 0)
  90                 return extcon;
  91
  92         extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  93                         MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  94
  95         extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  96                         MII_VSC8244_EXTCON1_RX_SKEW);
  97
  98         err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
  99
 100         return err;
 101 }
 102
 103 static int vsc824x_config_init(struct phy_device *phydev)
 104 {
 105         int err;
 106
 107         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 108                         MII_VSC8244_AUXCONSTAT_INIT);
 109         if (err < 0)
 110                 return err;
 111
 112         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 113                 err = vsc824x_add_skew(phydev);
 114
 115         return err;
 116 }
 117
 118 /* This adds a skew for both TX and RX clocks, so the skew should only be
 119  * applied to "rgmii-id" interfaces. It may not work as expected
 120  * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
 121 static int vsc8601_add_skew(struct phy_device *phydev)
 122 {
 123         int ret;
 124
 125         ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
 126         if (ret < 0)
 127                 return ret;
 128
 129         ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
 130         return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
 131 }
 132
 133 static int vsc8601_config_init(struct phy_device *phydev)
 134 {
 135         int ret = 0;
 136
 137         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 138                 ret = vsc8601_add_skew(phydev);
 139
 140         if (ret < 0)
 141                 return ret;
 142
 143         return genphy_config_init(phydev);
 144 }
 145
 146 static int vsc824x_ack_interrupt(struct phy_device *phydev)
 147 {
 148         int err = 0;
 149
 150         /* Don't bother to ACK the interrupts if interrupts
 151          * are disabled.  The 824x cannot clear the interrupts
 152          * if they are disabled.
 153          */
 154         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 155                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 156
 157         return (err < 0) ? err : 0;
 158 }
 159
 160 static int vsc82xx_config_intr(struct phy_device *phydev)
 161 {
 162         int err;
 163
 164         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 165                 err = phy_write(phydev, MII_VSC8244_IMASK,
 166                         (phydev->drv->phy_id == PHY_ID_VSC8234 ||
 167                          phydev->drv->phy_id == PHY_ID_VSC8244 ||
 168                          phydev->drv->phy_id == PHY_ID_VSC8514 ||
 169                          phydev->drv->phy_id == PHY_ID_VSC8574 ||
 170                          phydev->drv->phy_id == PHY_ID_VSC8601) ?
 171                                 MII_VSC8244_IMASK_MASK :
 172                                 MII_VSC8221_IMASK_MASK);
 173         else {
 174                 /* The Vitesse PHY cannot clear the interrupt
 175                  * once it has disabled them, so we clear them first
 176                  */
 177                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 178
 179                 if (err < 0)
 180                         return err;
 181
 182                 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
 183         }
 184
 185         return err;
 186 }
 187
 188 static int vsc8221_config_init(struct phy_device *phydev)
 189 {
 190         int err;
 191
 192         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 193                         MII_VSC8221_AUXCONSTAT_INIT);
 194         return err;
 195
 196         /* Perhaps we should set EXT_CON1 based on the interface?
 197          * Options are 802.3Z SerDes or SGMII
 198          */
 199 }
 200
 201 /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
 202  * @phydev: target phy_device struct
 203  *
 204  * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
 205  * special values in the VSC8234/VSC8244 extended reserved registers
 206  */
 207 static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
 208 {
 209         int ret;
 210
 211         if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
 212                 return 0;
 213
 214         /* map extended registers set 0x10 - 0x1e */
 215         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
 216         if (ret >= 0)
 217                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
 218         if (ret >= 0)
 219                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
 220         if (ret >= 0)
 221                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
 222         /* map standard registers set 0x10 - 0x1e */
 223         if (ret >= 0)
 224                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 225         else
 226                 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 227
 228         return ret;
 229 }
 230
 231 /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
 232  * @phydev: target phy_device struct
 233  *
 234  * Description: If auto-negotiation is enabled, we configure the
 235  *   advertising, and then restart auto-negotiation.  If it is not
 236  *   enabled, then we write the BMCR and also start the auto
 237  *   MDI/MDI-X feature
 238  */
 239 static int vsc82x4_config_aneg(struct phy_device *phydev)
 240 {
 241         int ret;
 242
 243         /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
 244          * writing special values in the VSC8234 extended reserved registers
 245          */
 246         if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
 247                 ret = genphy_setup_forced(phydev);
 248
 249                 if (ret < 0) /* error */
 250                         return ret;
 251
 252                 return vsc82x4_config_autocross_enable(phydev);
 253         }
 254
 255         return genphy_config_aneg(phydev);
 256 }
 257
 258 /* Vitesse 82xx */
 259 static struct phy_driver vsc82xx_driver[] = {
 260 {
 261         .phy_id         = PHY_ID_VSC8234,
 262         .name           = "Vitesse VSC8234",
 263         .phy_id_mask    = 0x000ffff0,
 264         .features       = PHY_GBIT_FEATURES,
 265         .flags          = PHY_HAS_INTERRUPT,
 266         .config_init    = &vsc824x_config_init,
 267         .config_aneg    = &vsc82x4_config_aneg,
 268         .read_status    = &genphy_read_status,
 269         .ack_interrupt  = &vsc824x_ack_interrupt,
 270         .config_intr    = &vsc82xx_config_intr,
 271 }, {
 272         .phy_id         = PHY_ID_VSC8244,
 273         .name           = "Vitesse VSC8244",
 274         .phy_id_mask    = 0x000fffc0,
 275         .features       = PHY_GBIT_FEATURES,
 276         .flags          = PHY_HAS_INTERRUPT,
 277         .config_init    = &vsc824x_config_init,
 278         .config_aneg    = &vsc82x4_config_aneg,
 279         .read_status    = &genphy_read_status,
 280         .ack_interrupt  = &vsc824x_ack_interrupt,
 281         .config_intr    = &vsc82xx_config_intr,
 282 }, {
 283         .phy_id         = PHY_ID_VSC8514,
 284         .name           = "Vitesse VSC8514",
 285         .phy_id_mask    = 0x000ffff0,
 286         .features       = PHY_GBIT_FEATURES,
 287         .flags          = PHY_HAS_INTERRUPT,
 288         .config_init    = &vsc824x_config_init,
 289         .config_aneg    = &vsc82x4_config_aneg,
 290         .read_status    = &genphy_read_status,
 291         .ack_interrupt  = &vsc824x_ack_interrupt,
 292         .config_intr    = &vsc82xx_config_intr,
 293 }, {
 294         .phy_id         = PHY_ID_VSC8574,
 295         .name           = "Vitesse VSC8574",
 296         .phy_id_mask    = 0x000ffff0,
 297         .features       = PHY_GBIT_FEATURES,
 298         .flags          = PHY_HAS_INTERRUPT,
 299         .config_init    = &vsc824x_config_init,
 300         .config_aneg    = &vsc82x4_config_aneg,
 301         .read_status    = &genphy_read_status,
 302         .ack_interrupt  = &vsc824x_ack_interrupt,
 303         .config_intr    = &vsc82xx_config_intr,
 304 }, {
 305         .phy_id         = PHY_ID_VSC8601,
 306         .name           = "Vitesse VSC8601",
 307         .phy_id_mask    = 0x000ffff0,
 308         .features       = PHY_GBIT_FEATURES,
 309         .flags          = PHY_HAS_INTERRUPT,
 310         .config_init    = &vsc8601_config_init,
 311         .config_aneg    = &genphy_config_aneg,
 312         .read_status    = &genphy_read_status,
 313         .ack_interrupt  = &vsc824x_ack_interrupt,
 314         .config_intr    = &vsc82xx_config_intr,
 315 }, {
 316         .phy_id         = PHY_ID_VSC8662,
 317         .name           = "Vitesse VSC8662",
 318         .phy_id_mask    = 0x000ffff0,
 319         .features       = PHY_GBIT_FEATURES,
 320         .flags          = PHY_HAS_INTERRUPT,
 321         .config_init    = &vsc824x_config_init,
 322         .config_aneg    = &vsc82x4_config_aneg,
 323         .read_status    = &genphy_read_status,
 324         .ack_interrupt  = &vsc824x_ack_interrupt,
 325         .config_intr    = &vsc82xx_config_intr,
 326 }, {
 327         /* Vitesse 8221 */
 328         .phy_id         = PHY_ID_VSC8221,
 329         .phy_id_mask    = 0x000ffff0,
 330         .name           = "Vitesse VSC8221",
 331         .features       = PHY_GBIT_FEATURES,
 332         .flags          = PHY_HAS_INTERRUPT,
 333         .config_init    = &vsc8221_config_init,
 334         .config_aneg    = &genphy_config_aneg,
 335         .read_status    = &genphy_read_status,
 336         .ack_interrupt  = &vsc824x_ack_interrupt,
 337         .config_intr    = &vsc82xx_config_intr,
 338 }, {
 339         /* Vitesse 8211 */
 340         .phy_id         = PHY_ID_VSC8211,
 341         .phy_id_mask    = 0x000ffff0,
 342         .name           = "Vitesse VSC8211",
 343         .features       = PHY_GBIT_FEATURES,
 344         .flags          = PHY_HAS_INTERRUPT,
 345         .config_init    = &vsc8221_config_init,
 346         .config_aneg    = &genphy_config_aneg,
 347         .read_status    = &genphy_read_status,
 348         .ack_interrupt  = &vsc824x_ack_interrupt,
 349         .config_intr    = &vsc82xx_config_intr,
 350 } };
 351
 352 module_phy_driver(vsc82xx_driver);
 353
 354 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
 355         { PHY_ID_VSC8234, 0x000ffff0 },
 356         { PHY_ID_VSC8244, 0x000fffc0 },
 357         { PHY_ID_VSC8514, 0x000ffff0 },
 358         { PHY_ID_VSC8574, 0x000ffff0 },
 359         { PHY_ID_VSC8662, 0x000ffff0 },
 360         { PHY_ID_VSC8221, 0x000ffff0 },
 361         { PHY_ID_VSC8211, 0x000ffff0 },
 362         { }
 363 };
 364
 365 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);