drivers/net/wan/fsl_ucc_hdlc.c

   1 /* Freescale QUICC Engine HDLC Device Driver
   2  *
   3  * Copyright 2016 Freescale Semiconductor Inc.
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/hdlc.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sched.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/stddef.h>
  30 #include <soc/fsl/qe/qe_tdm.h>
  31 #include <uapi/linux/if_arp.h>
  32
  33 #include "fsl_ucc_hdlc.h"
  34
  35 #define DRV_DESC "Freescale QE UCC HDLC Driver"
  36 #define DRV_NAME "ucc_hdlc"
  37
  38 #define TDM_PPPOHT_SLIC_MAXIN
  39
  40 static struct ucc_tdm_info utdm_primary_info = {
  41         .uf_info = {
  42                 .tsa = 0,
  43                 .cdp = 0,
  44                 .cds = 1,
  45                 .ctsp = 1,
  46                 .ctss = 1,
  47                 .revd = 0,
  48                 .urfs = 256,
  49                 .utfs = 256,
  50                 .urfet = 128,
  51                 .urfset = 192,
  52                 .utfet = 128,
  53                 .utftt = 0x40,
  54                 .ufpt = 256,
  55                 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
  56                 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  57                 .tenc = UCC_FAST_TX_ENCODING_NRZ,
  58                 .renc = UCC_FAST_RX_ENCODING_NRZ,
  59                 .tcrc = UCC_FAST_16_BIT_CRC,
  60                 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  61         },
  62
  63         .si_info = {
  64 #ifdef TDM_PPPOHT_SLIC_MAXIN
  65                 .simr_rfsd = 1,
  66                 .simr_tfsd = 2,
  67 #else
  68                 .simr_rfsd = 0,
  69                 .simr_tfsd = 0,
  70 #endif
  71                 .simr_crt = 0,
  72                 .simr_sl = 0,
  73                 .simr_ce = 1,
  74                 .simr_fe = 1,
  75                 .simr_gm = 0,
  76         },
  77 };
  78
  79 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
  80
  81 static int uhdlc_init(struct ucc_hdlc_private *priv)
  82 {
  83         struct ucc_tdm_info *ut_info;
  84         struct ucc_fast_info *uf_info;
  85         u32 cecr_subblock;
  86         u16 bd_status;
  87         int ret, i;
  88         void *bd_buffer;
  89         dma_addr_t bd_dma_addr;
  90         u32 riptr;
  91         u32 tiptr;
  92         u32 gumr;
  93
  94         ut_info = priv->ut_info;
  95         uf_info = &ut_info->uf_info;
  96
  97         if (priv->tsa) {
  98                 uf_info->tsa = 1;
  99                 uf_info->ctsp = 1;
 100         }
 101
 102         /* This sets HPM register in CMXUCR register which configures a
 103          * open drain connected HDLC bus
 104          */
 105         if (priv->hdlc_bus)
 106                 uf_info->brkpt_support = 1;
 107
 108         uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
 109                                 UCC_HDLC_UCCE_TXB) << 16);
 110
 111         ret = ucc_fast_init(uf_info, &priv->uccf);
 112         if (ret) {
 113                 dev_err(priv->dev, "Failed to init uccf.");
 114                 return ret;
 115         }
 116
 117         priv->uf_regs = priv->uccf->uf_regs;
 118         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 119
 120         /* Loopback mode */
 121         if (priv->loopback) {
 122                 dev_info(priv->dev, "Loopback Mode\n");
 123                 /* use the same clock when work in loopback */
 124                 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
 125
 126                 gumr = ioread32be(&priv->uf_regs->gumr);
 127                 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
 128                          UCC_FAST_GUMR_TCI);
 129                 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
 130                 iowrite32be(gumr, &priv->uf_regs->gumr);
 131         }
 132
 133         /* Initialize SI */
 134         if (priv->tsa)
 135                 ucc_tdm_init(priv->utdm, priv->ut_info);
 136
 137         /* Write to QE CECR, UCCx channel to Stop Transmission */
 138         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 139         ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 140                            QE_CR_PROTOCOL_UNSPECIFIED, 0);
 141
 142         /* Set UPSMR normal mode (need fixed)*/
 143         iowrite32be(0, &priv->uf_regs->upsmr);
 144
 145         /* hdlc_bus mode */
 146         if (priv->hdlc_bus) {
 147                 u32 upsmr;
 148
 149                 dev_info(priv->dev, "HDLC bus Mode\n");
 150                 upsmr = ioread32be(&priv->uf_regs->upsmr);
 151
 152                 /* bus mode and retransmit enable, with collision window
 153                  * set to 8 bytes
 154                  */
 155                 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
 156                                 UCC_HDLC_UPSMR_CW8;
 157                 iowrite32be(upsmr, &priv->uf_regs->upsmr);
 158
 159                 /* explicitly disable CDS & CTSP */
 160                 gumr = ioread32be(&priv->uf_regs->gumr);
 161                 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
 162                 /* set automatic sync to explicitly ignore CD signal */
 163                 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
 164                 iowrite32be(gumr, &priv->uf_regs->gumr);
 165         }
 166
 167         priv->rx_ring_size = RX_BD_RING_LEN;
 168         priv->tx_ring_size = TX_BD_RING_LEN;
 169         /* Alloc Rx BD */
 170         priv->rx_bd_base = dma_alloc_coherent(priv->dev,
 171                         RX_BD_RING_LEN * sizeof(struct qe_bd),
 172                         &priv->dma_rx_bd, GFP_KERNEL);
 173
 174         if (!priv->rx_bd_base) {
 175                 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
 176                 ret = -ENOMEM;
 177                 goto free_uccf;
 178         }
 179
 180         /* Alloc Tx BD */
 181         priv->tx_bd_base = dma_alloc_coherent(priv->dev,
 182                         TX_BD_RING_LEN * sizeof(struct qe_bd),
 183                         &priv->dma_tx_bd, GFP_KERNEL);
 184
 185         if (!priv->tx_bd_base) {
 186                 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
 187                 ret = -ENOMEM;
 188                 goto free_rx_bd;
 189         }
 190
 191         /* Alloc parameter ram for ucc hdlc */
 192         priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
 193                                 ALIGNMENT_OF_UCC_HDLC_PRAM);
 194
 195         if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
 196                 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
 197                 ret = -ENOMEM;
 198                 goto free_tx_bd;
 199         }
 200
 201         priv->rx_skbuff = kzalloc(priv->rx_ring_size * sizeof(*priv->rx_skbuff),
 202                                   GFP_KERNEL);
 203         if (!priv->rx_skbuff) {
 204                 ret = -ENOMEM;
 205                 goto free_ucc_pram;
 206         }
 207
 208         priv->tx_skbuff = kzalloc(priv->tx_ring_size * sizeof(*priv->tx_skbuff),
 209                                   GFP_KERNEL);
 210         if (!priv->tx_skbuff) {
 211                 ret = -ENOMEM;
 212                 goto free_rx_skbuff;
 213         }
 214
 215         priv->skb_curtx = 0;
 216         priv->skb_dirtytx = 0;
 217         priv->curtx_bd = priv->tx_bd_base;
 218         priv->dirty_tx = priv->tx_bd_base;
 219         priv->currx_bd = priv->rx_bd_base;
 220         priv->currx_bdnum = 0;
 221
 222         /* init parameter base */
 223         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 224         ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 225                            QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
 226
 227         priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
 228                                         qe_muram_addr(priv->ucc_pram_offset);
 229
 230         /* Zero out parameter ram */
 231         memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
 232
 233         /* Alloc riptr, tiptr */
 234         riptr = qe_muram_alloc(32, 32);
 235         if (IS_ERR_VALUE(riptr)) {
 236                 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
 237                 ret = -ENOMEM;
 238                 goto free_tx_skbuff;
 239         }
 240
 241         tiptr = qe_muram_alloc(32, 32);
 242         if (IS_ERR_VALUE(tiptr)) {
 243                 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
 244                 ret = -ENOMEM;
 245                 goto free_riptr;
 246         }
 247         if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
 248                 dev_err(priv->dev, "MURAM allocation out of addressable range\n");
 249                 ret = -ENOMEM;
 250                 goto free_tiptr;
 251         }
 252
 253         /* Set RIPTR, TIPTR */
 254         iowrite16be(riptr, &priv->ucc_pram->riptr);
 255         iowrite16be(tiptr, &priv->ucc_pram->tiptr);
 256
 257         /* Set MRBLR */
 258         iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
 259
 260         /* Set RBASE, TBASE */
 261         iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
 262         iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
 263
 264         /* Set RSTATE, TSTATE */
 265         iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
 266         iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
 267
 268         /* Set C_MASK, C_PRES for 16bit CRC */
 269         iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
 270         iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
 271
 272         iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
 273         iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
 274         iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
 275         iowrite16be(DEFAULT_ADDR_MASK, &priv->ucc_pram->hmask);
 276         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
 277         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
 278         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
 279         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
 280
 281         /* Get BD buffer */
 282         bd_buffer = dma_alloc_coherent(priv->dev,
 283                                        (RX_BD_RING_LEN + TX_BD_RING_LEN) *
 284                                        MAX_RX_BUF_LENGTH,
 285                                        &bd_dma_addr, GFP_KERNEL);
 286
 287         if (!bd_buffer) {
 288                 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
 289                 ret = -ENOMEM;
 290                 goto free_tiptr;
 291         }
 292
 293         memset(bd_buffer, 0, (RX_BD_RING_LEN + TX_BD_RING_LEN)
 294                         * MAX_RX_BUF_LENGTH);
 295
 296         priv->rx_buffer = bd_buffer;
 297         priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
 298
 299         priv->dma_rx_addr = bd_dma_addr;
 300         priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
 301
 302         for (i = 0; i < RX_BD_RING_LEN; i++) {
 303                 if (i < (RX_BD_RING_LEN - 1))
 304                         bd_status = R_E_S | R_I_S;
 305                 else
 306                         bd_status = R_E_S | R_I_S | R_W_S;
 307
 308                 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
 309                 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
 310                             &priv->rx_bd_base[i].buf);
 311         }
 312
 313         for (i = 0; i < TX_BD_RING_LEN; i++) {
 314                 if (i < (TX_BD_RING_LEN - 1))
 315                         bd_status =  T_I_S | T_TC_S;
 316                 else
 317                         bd_status =  T_I_S | T_TC_S | T_W_S;
 318
 319                 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
 320                 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
 321                             &priv->tx_bd_base[i].buf);
 322         }
 323
 324         return 0;
 325
 326 free_tiptr:
 327         qe_muram_free(tiptr);
 328 free_riptr:
 329         qe_muram_free(riptr);
 330 free_tx_skbuff:
 331         kfree(priv->tx_skbuff);
 332 free_rx_skbuff:
 333         kfree(priv->rx_skbuff);
 334 free_ucc_pram:
 335         qe_muram_free(priv->ucc_pram_offset);
 336 free_tx_bd:
 337         dma_free_coherent(priv->dev,
 338                           TX_BD_RING_LEN * sizeof(struct qe_bd),
 339                           priv->tx_bd_base, priv->dma_tx_bd);
 340 free_rx_bd:
 341         dma_free_coherent(priv->dev,
 342                           RX_BD_RING_LEN * sizeof(struct qe_bd),
 343                           priv->rx_bd_base, priv->dma_rx_bd);
 344 free_uccf:
 345         ucc_fast_free(priv->uccf);
 346
 347         return ret;
 348 }
 349
 350 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
 351 {
 352         hdlc_device *hdlc = dev_to_hdlc(dev);
 353         struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
 354         struct qe_bd __iomem *bd;
 355         u16 bd_status;
 356         unsigned long flags;
 357         u16 *proto_head;
 358
 359         switch (dev->type) {
 360         case ARPHRD_RAWHDLC:
 361                 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
 362                         dev->stats.tx_dropped++;
 363                         dev_kfree_skb(skb);
 364                         netdev_err(dev, "No enough space for hdlc head\n");
 365                         return -ENOMEM;
 366                 }
 367
 368                 skb_push(skb, HDLC_HEAD_LEN);
 369
 370                 proto_head = (u16 *)skb->data;
 371                 *proto_head = htons(DEFAULT_HDLC_HEAD);
 372
 373                 dev->stats.tx_bytes += skb->len;
 374                 break;
 375
 376         case ARPHRD_PPP:
 377                 proto_head = (u16 *)skb->data;
 378                 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
 379                         dev->stats.tx_dropped++;
 380                         dev_kfree_skb(skb);
 381                         netdev_err(dev, "Wrong ppp header\n");
 382                         return -ENOMEM;
 383                 }
 384
 385                 dev->stats.tx_bytes += skb->len;
 386                 break;
 387
 388         default:
 389                 dev->stats.tx_dropped++;
 390                 dev_kfree_skb(skb);
 391                 return -ENOMEM;
 392         }
 393         spin_lock_irqsave(&priv->lock, flags);
 394
 395         /* Start from the next BD that should be filled */
 396         bd = priv->curtx_bd;
 397         bd_status = ioread16be(&bd->status);
 398         /* Save the skb pointer so we can free it later */
 399         priv->tx_skbuff[priv->skb_curtx] = skb;
 400
 401         /* Update the current skb pointer (wrapping if this was the last) */
 402         priv->skb_curtx =
 403             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
 404
 405         /* copy skb data to tx buffer for sdma processing */
 406         memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
 407                skb->data, skb->len);
 408
 409         /* set bd status and length */
 410         bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
 411
 412         iowrite16be(skb->len, &bd->length);
 413         iowrite16be(bd_status, &bd->status);
 414
 415         /* Move to next BD in the ring */
 416         if (!(bd_status & T_W_S))
 417                 bd += 1;
 418         else
 419                 bd = priv->tx_bd_base;
 420
 421         if (bd == priv->dirty_tx) {
 422                 if (!netif_queue_stopped(dev))
 423                         netif_stop_queue(dev);
 424         }
 425
 426         priv->curtx_bd = bd;
 427
 428         spin_unlock_irqrestore(&priv->lock, flags);
 429
 430         return NETDEV_TX_OK;
 431 }
 432
 433 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
 434 {
 435         /* Start from the next BD that should be filled */
 436         struct net_device *dev = priv->ndev;
 437         struct qe_bd *bd;               /* BD pointer */
 438         u16 bd_status;
 439
 440         bd = priv->dirty_tx;
 441         bd_status = ioread16be(&bd->status);
 442
 443         /* Normal processing. */
 444         while ((bd_status & T_R_S) == 0) {
 445                 struct sk_buff *skb;
 446
 447                 /* BD contains already transmitted buffer.   */
 448                 /* Handle the transmitted buffer and release */
 449                 /* the BD to be used with the current frame  */
 450
 451                 skb = priv->tx_skbuff[priv->skb_dirtytx];
 452                 if (!skb)
 453                         break;
 454                 dev->stats.tx_packets++;
 455                 memset(priv->tx_buffer +
 456                        (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
 457                        0, skb->len);
 458                 dev_kfree_skb_irq(skb);
 459
 460                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
 461                 priv->skb_dirtytx =
 462                     (priv->skb_dirtytx +
 463                      1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
 464
 465                 /* We freed a buffer, so now we can restart transmission */
 466                 if (netif_queue_stopped(dev))
 467                         netif_wake_queue(dev);
 468
 469                 /* Advance the confirmation BD pointer */
 470                 if (!(bd_status & T_W_S))
 471                         bd += 1;
 472                 else
 473                         bd = priv->tx_bd_base;
 474                 bd_status = ioread16be(&bd->status);
 475         }
 476         priv->dirty_tx = bd;
 477
 478         return 0;
 479 }
 480
 481 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
 482 {
 483         struct net_device *dev = priv->ndev;
 484         struct sk_buff *skb = NULL;
 485         hdlc_device *hdlc = dev_to_hdlc(dev);
 486         struct qe_bd *bd;
 487         u16 bd_status;
 488         u16 length, howmany = 0;
 489         u8 *bdbuffer;
 490
 491         bd = priv->currx_bd;
 492         bd_status = ioread16be(&bd->status);
 493
 494         /* while there are received buffers and BD is full (~R_E) */
 495         while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
 496                 if (bd_status & R_OV_S)
 497                         dev->stats.rx_over_errors++;
 498                 if (bd_status & R_CR_S) {
 499                         dev->stats.rx_crc_errors++;
 500                         dev->stats.rx_dropped++;
 501                         goto recycle;
 502                 }
 503                 bdbuffer = priv->rx_buffer +
 504                         (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
 505                 length = ioread16be(&bd->length);
 506
 507                 switch (dev->type) {
 508                 case ARPHRD_RAWHDLC:
 509                         bdbuffer += HDLC_HEAD_LEN;
 510                         length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
 511
 512                         skb = dev_alloc_skb(length);
 513                         if (!skb) {
 514                                 dev->stats.rx_dropped++;
 515                                 return -ENOMEM;
 516                         }
 517
 518                         skb_put(skb, length);
 519                         skb->len = length;
 520                         skb->dev = dev;
 521                         memcpy(skb->data, bdbuffer, length);
 522                         break;
 523
 524                 case ARPHRD_PPP:
 525                         length -= HDLC_CRC_SIZE;
 526
 527                         skb = dev_alloc_skb(length);
 528                         if (!skb) {
 529                                 dev->stats.rx_dropped++;
 530                                 return -ENOMEM;
 531                         }
 532
 533                         skb_put(skb, length);
 534                         skb->len = length;
 535                         skb->dev = dev;
 536                         memcpy(skb->data, bdbuffer, length);
 537                         break;
 538                 }
 539
 540                 dev->stats.rx_packets++;
 541                 dev->stats.rx_bytes += skb->len;
 542                 howmany++;
 543                 if (hdlc->proto)
 544                         skb->protocol = hdlc_type_trans(skb, dev);
 545                 netif_receive_skb(skb);
 546
 547 recycle:
 548                 iowrite16be(bd_status | R_E_S | R_I_S, &bd->status);
 549
 550                 /* update to point at the next bd */
 551                 if (bd_status & R_W_S) {
 552                         priv->currx_bdnum = 0;
 553                         bd = priv->rx_bd_base;
 554                 } else {
 555                         if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
 556                                 priv->currx_bdnum += 1;
 557                         else
 558                                 priv->currx_bdnum = RX_BD_RING_LEN - 1;
 559
 560                         bd += 1;
 561                 }
 562
 563                 bd_status = ioread16be(&bd->status);
 564         }
 565
 566         priv->currx_bd = bd;
 567         return howmany;
 568 }
 569
 570 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
 571 {
 572         struct ucc_hdlc_private *priv = container_of(napi,
 573                                                      struct ucc_hdlc_private,
 574                                                      napi);
 575         int howmany;
 576
 577         /* Tx event processing */
 578         spin_lock(&priv->lock);
 579         hdlc_tx_done(priv);
 580         spin_unlock(&priv->lock);
 581
 582         howmany = 0;
 583         howmany += hdlc_rx_done(priv, budget - howmany);
 584
 585         if (howmany < budget) {
 586                 napi_complete_done(napi, howmany);
 587                 qe_setbits32(priv->uccf->p_uccm,
 588                              (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
 589         }
 590
 591         return howmany;
 592 }
 593
 594 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
 595 {
 596         struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
 597         struct net_device *dev = priv->ndev;
 598         struct ucc_fast_private *uccf;
 599         struct ucc_tdm_info *ut_info;
 600         u32 ucce;
 601         u32 uccm;
 602
 603         ut_info = priv->ut_info;
 604         uccf = priv->uccf;
 605
 606         ucce = ioread32be(uccf->p_ucce);
 607         uccm = ioread32be(uccf->p_uccm);
 608         ucce &= uccm;
 609         iowrite32be(ucce, uccf->p_ucce);
 610         if (!ucce)
 611                 return IRQ_NONE;
 612
 613         if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
 614                 if (napi_schedule_prep(&priv->napi)) {
 615                         uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
 616                                   << 16);
 617                         iowrite32be(uccm, uccf->p_uccm);
 618                         __napi_schedule(&priv->napi);
 619                 }
 620         }
 621
 622         /* Errors and other events */
 623         if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
 624                 dev->stats.rx_errors++;
 625         if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
 626                 dev->stats.tx_errors++;
 627
 628         return IRQ_HANDLED;
 629 }
 630
 631 static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 632 {
 633         const size_t size = sizeof(te1_settings);
 634         te1_settings line;
 635         struct ucc_hdlc_private *priv = netdev_priv(dev);
 636
 637         if (cmd != SIOCWANDEV)
 638                 return hdlc_ioctl(dev, ifr, cmd);
 639
 640         switch (ifr->ifr_settings.type) {
 641         case IF_GET_IFACE:
 642                 ifr->ifr_settings.type = IF_IFACE_E1;
 643                 if (ifr->ifr_settings.size < size) {
 644                         ifr->ifr_settings.size = size; /* data size wanted */
 645                         return -ENOBUFS;
 646                 }
 647                 memset(&line, 0, sizeof(line));
 648                 line.clock_type = priv->clocking;
 649
 650                 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
 651                         return -EFAULT;
 652                 return 0;
 653
 654         default:
 655                 return hdlc_ioctl(dev, ifr, cmd);
 656         }
 657 }
 658
 659 static int uhdlc_open(struct net_device *dev)
 660 {
 661         u32 cecr_subblock;
 662         hdlc_device *hdlc = dev_to_hdlc(dev);
 663         struct ucc_hdlc_private *priv = hdlc->priv;
 664         struct ucc_tdm *utdm = priv->utdm;
 665
 666         if (priv->hdlc_busy != 1) {
 667                 if (request_irq(priv->ut_info->uf_info.irq,
 668                                 ucc_hdlc_irq_handler, 0, "hdlc", priv))
 669                         return -ENODEV;
 670
 671                 cecr_subblock = ucc_fast_get_qe_cr_subblock(
 672                                         priv->ut_info->uf_info.ucc_num);
 673
 674                 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 675                              QE_CR_PROTOCOL_UNSPECIFIED, 0);
 676
 677                 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 678
 679                 /* Enable the TDM port */
 680                 if (priv->tsa)
 681                         utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
 682
 683                 priv->hdlc_busy = 1;
 684                 netif_device_attach(priv->ndev);
 685                 napi_enable(&priv->napi);
 686                 netif_start_queue(dev);
 687                 hdlc_open(dev);
 688         }
 689
 690         return 0;
 691 }
 692
 693 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
 694 {
 695         qe_muram_free(priv->ucc_pram->riptr);
 696         qe_muram_free(priv->ucc_pram->tiptr);
 697
 698         if (priv->rx_bd_base) {
 699                 dma_free_coherent(priv->dev,
 700                                   RX_BD_RING_LEN * sizeof(struct qe_bd),
 701                                   priv->rx_bd_base, priv->dma_rx_bd);
 702
 703                 priv->rx_bd_base = NULL;
 704                 priv->dma_rx_bd = 0;
 705         }
 706
 707         if (priv->tx_bd_base) {
 708                 dma_free_coherent(priv->dev,
 709                                   TX_BD_RING_LEN * sizeof(struct qe_bd),
 710                                   priv->tx_bd_base, priv->dma_tx_bd);
 711
 712                 priv->tx_bd_base = NULL;
 713                 priv->dma_tx_bd = 0;
 714         }
 715
 716         if (priv->ucc_pram) {
 717                 qe_muram_free(priv->ucc_pram_offset);
 718                 priv->ucc_pram = NULL;
 719                 priv->ucc_pram_offset = 0;
 720          }
 721
 722         kfree(priv->rx_skbuff);
 723         priv->rx_skbuff = NULL;
 724
 725         kfree(priv->tx_skbuff);
 726         priv->tx_skbuff = NULL;
 727
 728         if (priv->uf_regs) {
 729                 iounmap(priv->uf_regs);
 730                 priv->uf_regs = NULL;
 731         }
 732
 733         if (priv->uccf) {
 734                 ucc_fast_free(priv->uccf);
 735                 priv->uccf = NULL;
 736         }
 737
 738         if (priv->rx_buffer) {
 739                 dma_free_coherent(priv->dev,
 740                                   RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
 741                                   priv->rx_buffer, priv->dma_rx_addr);
 742                 priv->rx_buffer = NULL;
 743                 priv->dma_rx_addr = 0;
 744         }
 745
 746         if (priv->tx_buffer) {
 747                 dma_free_coherent(priv->dev,
 748                                   TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
 749                                   priv->tx_buffer, priv->dma_tx_addr);
 750                 priv->tx_buffer = NULL;
 751                 priv->dma_tx_addr = 0;
 752         }
 753 }
 754
 755 static int uhdlc_close(struct net_device *dev)
 756 {
 757         struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
 758         struct ucc_tdm *utdm = priv->utdm;
 759         u32 cecr_subblock;
 760
 761         napi_disable(&priv->napi);
 762         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 763                                 priv->ut_info->uf_info.ucc_num);
 764
 765         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 766                      (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 767         qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
 768                      (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 769
 770         if (priv->tsa)
 771                 utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port);
 772
 773         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 774
 775         free_irq(priv->ut_info->uf_info.irq, priv);
 776         netif_stop_queue(dev);
 777         priv->hdlc_busy = 0;
 778
 779         return 0;
 780 }
 781
 782 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
 783                            unsigned short parity)
 784 {
 785         struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
 786
 787         if (encoding != ENCODING_NRZ &&
 788             encoding != ENCODING_NRZI)
 789                 return -EINVAL;
 790
 791         if (parity != PARITY_NONE &&
 792             parity != PARITY_CRC32_PR1_CCITT &&
 793             parity != PARITY_CRC16_PR1_CCITT)
 794                 return -EINVAL;
 795
 796         priv->encoding = encoding;
 797         priv->parity = parity;
 798
 799         return 0;
 800 }
 801
 802 #ifdef CONFIG_PM
 803 static void store_clk_config(struct ucc_hdlc_private *priv)
 804 {
 805         struct qe_mux *qe_mux_reg = &qe_immr->qmx;
 806
 807         /* store si clk */
 808         priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
 809         priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
 810
 811         /* store si sync */
 812         priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
 813
 814         /* store ucc clk */
 815         memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
 816 }
 817
 818 static void resume_clk_config(struct ucc_hdlc_private *priv)
 819 {
 820         struct qe_mux *qe_mux_reg = &qe_immr->qmx;
 821
 822         memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
 823
 824         iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
 825         iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
 826
 827         iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
 828 }
 829
 830 static int uhdlc_suspend(struct device *dev)
 831 {
 832         struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
 833         struct ucc_tdm_info *ut_info;
 834         struct ucc_fast __iomem *uf_regs;
 835
 836         if (!priv)
 837                 return -EINVAL;
 838
 839         if (!netif_running(priv->ndev))
 840                 return 0;
 841
 842         netif_device_detach(priv->ndev);
 843         napi_disable(&priv->napi);
 844
 845         ut_info = priv->ut_info;
 846         uf_regs = priv->uf_regs;
 847
 848         /* backup gumr guemr*/
 849         priv->gumr = ioread32be(&uf_regs->gumr);
 850         priv->guemr = ioread8(&uf_regs->guemr);
 851
 852         priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
 853                                         GFP_KERNEL);
 854         if (!priv->ucc_pram_bak)
 855                 return -ENOMEM;
 856
 857         /* backup HDLC parameter */
 858         memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
 859                       sizeof(struct ucc_hdlc_param));
 860
 861         /* store the clk configuration */
 862         store_clk_config(priv);
 863
 864         /* save power */
 865         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 866
 867         return 0;
 868 }
 869
 870 static int uhdlc_resume(struct device *dev)
 871 {
 872         struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
 873         struct ucc_tdm *utdm;
 874         struct ucc_tdm_info *ut_info;
 875         struct ucc_fast __iomem *uf_regs;
 876         struct ucc_fast_private *uccf;
 877         struct ucc_fast_info *uf_info;
 878         int ret, i;
 879         u32 cecr_subblock;
 880         u16 bd_status;
 881
 882         if (!priv)
 883                 return -EINVAL;
 884
 885         if (!netif_running(priv->ndev))
 886                 return 0;
 887
 888         utdm = priv->utdm;
 889         ut_info = priv->ut_info;
 890         uf_info = &ut_info->uf_info;
 891         uf_regs = priv->uf_regs;
 892         uccf = priv->uccf;
 893
 894         /* restore gumr guemr */
 895         iowrite8(priv->guemr, &uf_regs->guemr);
 896         iowrite32be(priv->gumr, &uf_regs->gumr);
 897
 898         /* Set Virtual Fifo registers */
 899         iowrite16be(uf_info->urfs, &uf_regs->urfs);
 900         iowrite16be(uf_info->urfet, &uf_regs->urfet);
 901         iowrite16be(uf_info->urfset, &uf_regs->urfset);
 902         iowrite16be(uf_info->utfs, &uf_regs->utfs);
 903         iowrite16be(uf_info->utfet, &uf_regs->utfet);
 904         iowrite16be(uf_info->utftt, &uf_regs->utftt);
 905         /* utfb, urfb are offsets from MURAM base */
 906         iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
 907         iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
 908
 909         /* Rx Tx and sync clock routing */
 910         resume_clk_config(priv);
 911
 912         iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
 913         iowrite32be(0xffffffff, &uf_regs->ucce);
 914
 915         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 916
 917         /* rebuild SIRAM */
 918         if (priv->tsa)
 919                 ucc_tdm_init(priv->utdm, priv->ut_info);
 920
 921         /* Write to QE CECR, UCCx channel to Stop Transmission */
 922         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 923         ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 924                            (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 925
 926         /* Set UPSMR normal mode */
 927         iowrite32be(0, &uf_regs->upsmr);
 928
 929         /* init parameter base */
 930         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 931         ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 932                            QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
 933
 934         priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
 935                                 qe_muram_addr(priv->ucc_pram_offset);
 936
 937         /* restore ucc parameter */
 938         memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
 939                     sizeof(struct ucc_hdlc_param));
 940         kfree(priv->ucc_pram_bak);
 941
 942         /* rebuild BD entry */
 943         for (i = 0; i < RX_BD_RING_LEN; i++) {
 944                 if (i < (RX_BD_RING_LEN - 1))
 945                         bd_status = R_E_S | R_I_S;
 946                 else
 947                         bd_status = R_E_S | R_I_S | R_W_S;
 948
 949                 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
 950                 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
 951                             &priv->rx_bd_base[i].buf);
 952         }
 953
 954         for (i = 0; i < TX_BD_RING_LEN; i++) {
 955                 if (i < (TX_BD_RING_LEN - 1))
 956                         bd_status =  T_I_S | T_TC_S;
 957                 else
 958                         bd_status =  T_I_S | T_TC_S | T_W_S;
 959
 960                 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
 961                 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
 962                             &priv->tx_bd_base[i].buf);
 963         }
 964
 965         /* if hdlc is busy enable TX and RX */
 966         if (priv->hdlc_busy == 1) {
 967                 cecr_subblock = ucc_fast_get_qe_cr_subblock(
 968                                         priv->ut_info->uf_info.ucc_num);
 969
 970                 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 971                              (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 972
 973                 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 974
 975                 /* Enable the TDM port */
 976                 if (priv->tsa)
 977                         utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
 978         }
 979
 980         napi_enable(&priv->napi);
 981         netif_device_attach(priv->ndev);
 982
 983         return 0;
 984 }
 985
 986 static const struct dev_pm_ops uhdlc_pm_ops = {
 987         .suspend = uhdlc_suspend,
 988         .resume = uhdlc_resume,
 989         .freeze = uhdlc_suspend,
 990         .thaw = uhdlc_resume,
 991 };
 992
 993 #define HDLC_PM_OPS (&uhdlc_pm_ops)
 994
 995 #else
 996
 997 #define HDLC_PM_OPS NULL
 998
 999 #endif
1000 static const struct net_device_ops uhdlc_ops = {
1001         .ndo_open       = uhdlc_open,
1002         .ndo_stop       = uhdlc_close,
1003         .ndo_start_xmit = hdlc_start_xmit,
1004         .ndo_do_ioctl   = uhdlc_ioctl,
1005 };
1006
1007 static int ucc_hdlc_probe(struct platform_device *pdev)
1008 {
1009         struct device_node *np = pdev->dev.of_node;
1010         struct ucc_hdlc_private *uhdlc_priv = NULL;
1011         struct ucc_tdm_info *ut_info;
1012         struct ucc_tdm *utdm = NULL;
1013         struct resource res;
1014         struct net_device *dev;
1015         hdlc_device *hdlc;
1016         int ucc_num;
1017         const char *sprop;
1018         int ret;
1019         u32 val;
1020
1021         ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1022         if (ret) {
1023                 dev_err(&pdev->dev, "Invalid ucc property\n");
1024                 return -ENODEV;
1025         }
1026
1027         ucc_num = val - 1;
1028         if ((ucc_num > 3) || (ucc_num < 0)) {
1029                 dev_err(&pdev->dev, ": Invalid UCC num\n");
1030                 return -EINVAL;
1031         }
1032
1033         memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1034                sizeof(utdm_primary_info));
1035
1036         ut_info = &utdm_info[ucc_num];
1037         ut_info->uf_info.ucc_num = ucc_num;
1038
1039         sprop = of_get_property(np, "rx-clock-name", NULL);
1040         if (sprop) {
1041                 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1042                 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1043                     (ut_info->uf_info.rx_clock > QE_CLK24)) {
1044                         dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1045                         return -EINVAL;
1046                 }
1047         } else {
1048                 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1049                 return -EINVAL;
1050         }
1051
1052         sprop = of_get_property(np, "tx-clock-name", NULL);
1053         if (sprop) {
1054                 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1055                 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1056                     (ut_info->uf_info.tx_clock > QE_CLK24)) {
1057                         dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1058                         return -EINVAL;
1059                 }
1060         } else {
1061                 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1062                 return -EINVAL;
1063         }
1064
1065         ret = of_address_to_resource(np, 0, &res);
1066         if (ret)
1067                 return -EINVAL;
1068
1069         ut_info->uf_info.regs = res.start;
1070         ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1071
1072         uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1073         if (!uhdlc_priv) {
1074                 return -ENOMEM;
1075         }
1076
1077         dev_set_drvdata(&pdev->dev, uhdlc_priv);
1078         uhdlc_priv->dev = &pdev->dev;
1079         uhdlc_priv->ut_info = ut_info;
1080
1081         if (of_get_property(np, "fsl,tdm-interface", NULL))
1082                 uhdlc_priv->tsa = 1;
1083
1084         if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1085                 uhdlc_priv->loopback = 1;
1086
1087         if (of_get_property(np, "fsl,hdlc-bus", NULL))
1088                 uhdlc_priv->hdlc_bus = 1;
1089
1090         if (uhdlc_priv->tsa == 1) {
1091                 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1092                 if (!utdm) {
1093                         ret = -ENOMEM;
1094                         dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1095                         goto free_uhdlc_priv;
1096                 }
1097                 uhdlc_priv->utdm = utdm;
1098                 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1099                 if (ret)
1100                         goto free_utdm;
1101         }
1102
1103         ret = uhdlc_init(uhdlc_priv);
1104         if (ret) {
1105                 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1106                 goto free_utdm;
1107         }
1108
1109         dev = alloc_hdlcdev(uhdlc_priv);
1110         if (!dev) {
1111                 ret = -ENOMEM;
1112                 pr_err("ucc_hdlc: unable to allocate memory\n");
1113                 goto undo_uhdlc_init;
1114         }
1115
1116         uhdlc_priv->ndev = dev;
1117         hdlc = dev_to_hdlc(dev);
1118         dev->tx_queue_len = 16;
1119         dev->netdev_ops = &uhdlc_ops;
1120         hdlc->attach = ucc_hdlc_attach;
1121         hdlc->xmit = ucc_hdlc_tx;
1122         netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1123         if (register_hdlc_device(dev)) {
1124                 ret = -ENOBUFS;
1125                 pr_err("ucc_hdlc: unable to register hdlc device\n");
1126                 goto free_dev;
1127         }
1128
1129         return 0;
1130
1131 free_dev:
1132         free_netdev(dev);
1133 undo_uhdlc_init:
1134 free_utdm:
1135         if (uhdlc_priv->tsa)
1136                 kfree(utdm);
1137 free_uhdlc_priv:
1138         kfree(uhdlc_priv);
1139         return ret;
1140 }
1141
1142 static int ucc_hdlc_remove(struct platform_device *pdev)
1143 {
1144         struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1145
1146         uhdlc_memclean(priv);
1147
1148         if (priv->utdm->si_regs) {
1149                 iounmap(priv->utdm->si_regs);
1150                 priv->utdm->si_regs = NULL;
1151         }
1152
1153         if (priv->utdm->siram) {
1154                 iounmap(priv->utdm->siram);
1155                 priv->utdm->siram = NULL;
1156         }
1157         kfree(priv);
1158
1159         dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1160
1161         return 0;
1162 }
1163
1164 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1165         {
1166         .compatible = "fsl,ucc-hdlc",
1167         },
1168         {},
1169 };
1170
1171 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1172
1173 static struct platform_driver ucc_hdlc_driver = {
1174         .probe  = ucc_hdlc_probe,
1175         .remove = ucc_hdlc_remove,
1176         .driver = {
1177                 .name           = DRV_NAME,
1178                 .pm             = HDLC_PM_OPS,
1179                 .of_match_table = fsl_ucc_hdlc_of_match,
1180         },
1181 };
1182
1183 module_platform_driver(ucc_hdlc_driver);
1184 MODULE_LICENSE("GPL");