2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 static u8 ath10k_htt_tx_txq_calc_size(size_t count)
33 while (factor >= 64 && exp < 4) {
42 factor = max(1, factor);
44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) |
45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR);
48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
49 struct ieee80211_txq *txq)
51 struct ath10k *ar = hw->priv;
52 struct ath10k_sta *arsta;
53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv;
54 unsigned long frame_cnt;
55 unsigned long byte_cnt;
62 lockdep_assert_held(&ar->htt.tx_lock);
64 if (!ar->htt.tx_q_state.enabled)
67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
71 arsta = (void *)txq->sta->drv_priv;
72 peer_id = arsta->peer_id;
74 peer_id = arvif->peer_id;
78 bit = BIT(peer_id % 32);
81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
82 count = ath10k_htt_tx_txq_calc_size(byte_cnt);
84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) ||
85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) {
86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n",
91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count;
92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit;
93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0;
95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n",
99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar)
104 lockdep_assert_held(&ar->htt.tx_lock);
106 if (!ar->htt.tx_q_state.enabled)
109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq);
114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq);
116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n",
119 size = sizeof(*ar->htt.tx_q_state.vaddr);
120 dma_sync_single_for_device(ar->dev,
121 ar->htt.tx_q_state.paddr,
126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
127 struct ieee80211_txq *txq)
129 struct ath10k *ar = hw->priv;
131 spin_lock_bh(&ar->htt.tx_lock);
132 __ath10k_htt_tx_txq_recalc(hw, txq);
133 spin_unlock_bh(&ar->htt.tx_lock);
136 void ath10k_htt_tx_txq_sync(struct ath10k *ar)
138 spin_lock_bh(&ar->htt.tx_lock);
139 __ath10k_htt_tx_txq_sync(ar);
140 spin_unlock_bh(&ar->htt.tx_lock);
143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
144 struct ieee80211_txq *txq)
146 struct ath10k *ar = hw->priv;
148 spin_lock_bh(&ar->htt.tx_lock);
149 __ath10k_htt_tx_txq_recalc(hw, txq);
150 __ath10k_htt_tx_txq_sync(ar);
151 spin_unlock_bh(&ar->htt.tx_lock);
154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
156 lockdep_assert_held(&htt->tx_lock);
158 htt->num_pending_tx--;
159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
162 if (htt->num_pending_tx == 0)
163 wake_up(&htt->empty_tx_wq);
166 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
168 lockdep_assert_held(&htt->tx_lock);
170 if (htt->num_pending_tx >= htt->max_num_pending_tx)
173 htt->num_pending_tx++;
174 if (htt->num_pending_tx == htt->max_num_pending_tx)
175 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
180 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
183 struct ath10k *ar = htt->ar;
185 lockdep_assert_held(&htt->tx_lock);
187 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres)
191 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx)
194 htt->num_pending_mgmt_tx++;
199 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt)
201 lockdep_assert_held(&htt->tx_lock);
203 if (!htt->ar->hw_params.max_probe_resp_desc_thres)
206 htt->num_pending_mgmt_tx--;
209 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
211 struct ath10k *ar = htt->ar;
214 spin_lock_bh(&htt->tx_lock);
215 ret = idr_alloc(&htt->pending_tx, skb, 0,
216 htt->max_num_pending_tx, GFP_ATOMIC);
217 spin_unlock_bh(&htt->tx_lock);
219 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
224 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
226 struct ath10k *ar = htt->ar;
228 lockdep_assert_held(&htt->tx_lock);
230 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
232 idr_remove(&htt->pending_tx, msdu_id);
235 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt)
237 struct ath10k *ar = htt->ar;
240 if (!htt->txbuf.vaddr_txbuff_32)
243 size = htt->txbuf.size;
244 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32,
246 htt->txbuf.vaddr_txbuff_32 = NULL;
249 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt)
251 struct ath10k *ar = htt->ar;
254 size = htt->max_num_pending_tx *
255 sizeof(struct ath10k_htt_txbuf_32);
257 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size,
260 if (!htt->txbuf.vaddr_txbuff_32)
263 htt->txbuf.size = size;
268 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt)
270 struct ath10k *ar = htt->ar;
273 if (!htt->txbuf.vaddr_txbuff_64)
276 size = htt->txbuf.size;
277 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64,
279 htt->txbuf.vaddr_txbuff_64 = NULL;
282 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt)
284 struct ath10k *ar = htt->ar;
287 size = htt->max_num_pending_tx *
288 sizeof(struct ath10k_htt_txbuf_64);
290 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size,
293 if (!htt->txbuf.vaddr_txbuff_64)
296 htt->txbuf.size = size;
301 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt)
305 if (!htt->frag_desc.vaddr_desc_32)
308 size = htt->max_num_pending_tx *
309 sizeof(struct htt_msdu_ext_desc);
311 dma_free_coherent(htt->ar->dev,
313 htt->frag_desc.vaddr_desc_32,
314 htt->frag_desc.paddr);
316 htt->frag_desc.vaddr_desc_32 = NULL;
319 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt)
321 struct ath10k *ar = htt->ar;
324 if (!ar->hw_params.continuous_frag_desc)
327 size = htt->max_num_pending_tx *
328 sizeof(struct htt_msdu_ext_desc);
329 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size,
330 &htt->frag_desc.paddr,
332 if (!htt->frag_desc.vaddr_desc_32) {
333 ath10k_err(ar, "failed to alloc fragment desc memory\n");
336 htt->frag_desc.size = size;
341 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt)
345 if (!htt->frag_desc.vaddr_desc_64)
348 size = htt->max_num_pending_tx *
349 sizeof(struct htt_msdu_ext_desc_64);
351 dma_free_coherent(htt->ar->dev,
353 htt->frag_desc.vaddr_desc_64,
354 htt->frag_desc.paddr);
356 htt->frag_desc.vaddr_desc_64 = NULL;
359 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt)
361 struct ath10k *ar = htt->ar;
364 if (!ar->hw_params.continuous_frag_desc)
367 size = htt->max_num_pending_tx *
368 sizeof(struct htt_msdu_ext_desc_64);
370 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size,
371 &htt->frag_desc.paddr,
373 if (!htt->frag_desc.vaddr_desc_64) {
374 ath10k_err(ar, "failed to alloc fragment desc memory\n");
377 htt->frag_desc.size = size;
382 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt)
384 struct ath10k *ar = htt->ar;
387 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
388 ar->running_fw->fw_file.fw_features))
391 size = sizeof(*htt->tx_q_state.vaddr);
393 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE);
394 kfree(htt->tx_q_state.vaddr);
397 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt)
399 struct ath10k *ar = htt->ar;
403 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
404 ar->running_fw->fw_file.fw_features))
407 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS;
408 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS;
409 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES;
411 size = sizeof(*htt->tx_q_state.vaddr);
412 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL);
413 if (!htt->tx_q_state.vaddr)
416 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr,
417 size, DMA_TO_DEVICE);
418 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr);
420 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret);
421 kfree(htt->tx_q_state.vaddr);
428 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt)
430 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo));
431 kfifo_free(&htt->txdone_fifo);
434 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt)
439 size = roundup_pow_of_two(htt->max_num_pending_tx);
440 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL);
444 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
446 struct ath10k *ar = htt->ar;
449 ret = ath10k_htt_alloc_txbuff(htt);
451 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret);
455 ret = ath10k_htt_alloc_frag_desc(htt);
457 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);
461 ret = ath10k_htt_tx_alloc_txq(htt);
463 ath10k_err(ar, "failed to alloc txq: %d\n", ret);
467 ret = ath10k_htt_tx_alloc_txdone_fifo(htt);
469 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret);
476 ath10k_htt_tx_free_txq(htt);
479 ath10k_htt_free_frag_desc(htt);
482 ath10k_htt_free_txbuff(htt);
487 int ath10k_htt_tx_start(struct ath10k_htt *htt)
489 struct ath10k *ar = htt->ar;
492 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
493 htt->max_num_pending_tx);
495 spin_lock_init(&htt->tx_lock);
496 idr_init(&htt->pending_tx);
498 if (htt->tx_mem_allocated)
501 ret = ath10k_htt_tx_alloc_buf(htt);
503 goto free_idr_pending_tx;
505 htt->tx_mem_allocated = true;
510 idr_destroy(&htt->pending_tx);
515 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
517 struct ath10k *ar = ctx;
518 struct ath10k_htt *htt = &ar->htt;
519 struct htt_tx_done tx_done = {0};
521 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
523 tx_done.msdu_id = msdu_id;
524 tx_done.status = HTT_TX_COMPL_STATE_DISCARD;
526 ath10k_txrx_tx_unref(htt, &tx_done);
531 void ath10k_htt_tx_destroy(struct ath10k_htt *htt)
533 if (!htt->tx_mem_allocated)
536 ath10k_htt_free_txbuff(htt);
537 ath10k_htt_tx_free_txq(htt);
538 ath10k_htt_free_frag_desc(htt);
539 ath10k_htt_tx_free_txdone_fifo(htt);
540 htt->tx_mem_allocated = false;
543 void ath10k_htt_tx_stop(struct ath10k_htt *htt)
545 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
546 idr_destroy(&htt->pending_tx);
549 void ath10k_htt_tx_free(struct ath10k_htt *htt)
551 ath10k_htt_tx_stop(htt);
552 ath10k_htt_tx_destroy(htt);
555 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
557 dev_kfree_skb_any(skb);
560 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb)
562 dev_kfree_skb_any(skb);
564 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete);
566 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
568 struct ath10k *ar = htt->ar;
574 len += sizeof(cmd->hdr);
575 len += sizeof(cmd->ver_req);
577 skb = ath10k_htc_alloc_skb(ar, len);
582 cmd = (struct htt_cmd *)skb->data;
583 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
585 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
587 dev_kfree_skb_any(skb);
594 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
596 struct ath10k *ar = htt->ar;
597 struct htt_stats_req *req;
602 len += sizeof(cmd->hdr);
603 len += sizeof(cmd->stats_req);
605 skb = ath10k_htc_alloc_skb(ar, len);
610 cmd = (struct htt_cmd *)skb->data;
611 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
613 req = &cmd->stats_req;
615 memset(req, 0, sizeof(*req));
617 /* currently we support only max 8 bit masks so no need to worry
618 * about endian support
620 req->upload_types[0] = mask;
621 req->reset_types[0] = mask;
622 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
623 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
624 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
626 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
628 ath10k_warn(ar, "failed to send htt type stats request: %d",
630 dev_kfree_skb_any(skb);
637 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt)
639 struct ath10k *ar = htt->ar;
642 struct htt_frag_desc_bank_cfg32 *cfg;
646 if (!ar->hw_params.continuous_frag_desc)
649 if (!htt->frag_desc.paddr) {
650 ath10k_warn(ar, "invalid frag desc memory\n");
654 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32);
655 skb = ath10k_htc_alloc_skb(ar, size);
660 cmd = (struct htt_cmd *)skb->data;
661 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
664 info |= SM(htt->tx_q_state.type,
665 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
667 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
668 ar->running_fw->fw_file.fw_features))
669 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
671 cfg = &cmd->frag_desc_bank_cfg32;
674 cfg->desc_size = sizeof(struct htt_msdu_ext_desc);
675 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr);
676 cfg->bank_id[0].bank_min_id = 0;
677 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
680 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
681 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
682 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
683 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
684 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
686 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
688 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
690 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
692 dev_kfree_skb_any(skb);
699 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt)
701 struct ath10k *ar = htt->ar;
704 struct htt_frag_desc_bank_cfg64 *cfg;
708 if (!ar->hw_params.continuous_frag_desc)
711 if (!htt->frag_desc.paddr) {
712 ath10k_warn(ar, "invalid frag desc memory\n");
716 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64);
717 skb = ath10k_htc_alloc_skb(ar, size);
722 cmd = (struct htt_cmd *)skb->data;
723 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
726 info |= SM(htt->tx_q_state.type,
727 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
729 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
730 ar->running_fw->fw_file.fw_features))
731 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
733 cfg = &cmd->frag_desc_bank_cfg64;
736 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64);
737 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr);
738 cfg->bank_id[0].bank_min_id = 0;
739 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
742 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
743 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
744 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
745 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
746 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
748 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
750 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
752 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
754 dev_kfree_skb_any(skb);
761 static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring)
763 struct htt_rx_ring_setup_ring32 *ring =
764 (struct htt_rx_ring_setup_ring32 *)rx_ring;
766 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
767 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
768 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
769 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
770 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
771 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
772 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
773 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
774 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
775 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
776 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
780 static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring)
782 struct htt_rx_ring_setup_ring64 *ring =
783 (struct htt_rx_ring_setup_ring64 *)rx_ring;
785 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
786 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
787 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
788 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
789 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
790 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
791 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
792 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
793 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
794 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
795 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
799 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt)
801 struct ath10k *ar = htt->ar;
804 struct htt_rx_ring_setup_ring32 *ring;
805 const int num_rx_ring = 1;
812 * the HW expects the buffer to be an integral number of 4-byte
815 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
816 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
818 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr)
819 + (sizeof(*ring) * num_rx_ring);
820 skb = ath10k_htc_alloc_skb(ar, len);
826 cmd = (struct htt_cmd *)skb->data;
827 ring = &cmd->rx_setup_32.rings[0];
829 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
830 cmd->rx_setup_32.hdr.num_rings = 1;
832 /* FIXME: do we need all of this? */
834 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
835 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
836 flags |= HTT_RX_RING_FLAGS_PPDU_START;
837 flags |= HTT_RX_RING_FLAGS_PPDU_END;
838 flags |= HTT_RX_RING_FLAGS_MPDU_START;
839 flags |= HTT_RX_RING_FLAGS_MPDU_END;
840 flags |= HTT_RX_RING_FLAGS_MSDU_START;
841 flags |= HTT_RX_RING_FLAGS_MSDU_END;
842 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
843 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
844 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
845 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
846 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
847 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
848 flags |= HTT_RX_RING_FLAGS_NULL_RX;
849 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
851 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
853 ring->fw_idx_shadow_reg_paddr =
854 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
855 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
856 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
857 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
858 ring->flags = __cpu_to_le16(flags);
859 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
861 ath10k_htt_fill_rx_desc_offset_32(ring);
862 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
864 dev_kfree_skb_any(skb);
871 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt)
873 struct ath10k *ar = htt->ar;
876 struct htt_rx_ring_setup_ring64 *ring;
877 const int num_rx_ring = 1;
883 /* HW expects the buffer to be an integral number of 4-byte
886 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
887 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
889 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr)
890 + (sizeof(*ring) * num_rx_ring);
891 skb = ath10k_htc_alloc_skb(ar, len);
897 cmd = (struct htt_cmd *)skb->data;
898 ring = &cmd->rx_setup_64.rings[0];
900 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
901 cmd->rx_setup_64.hdr.num_rings = 1;
904 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
905 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
906 flags |= HTT_RX_RING_FLAGS_PPDU_START;
907 flags |= HTT_RX_RING_FLAGS_PPDU_END;
908 flags |= HTT_RX_RING_FLAGS_MPDU_START;
909 flags |= HTT_RX_RING_FLAGS_MPDU_END;
910 flags |= HTT_RX_RING_FLAGS_MSDU_START;
911 flags |= HTT_RX_RING_FLAGS_MSDU_END;
912 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
913 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
914 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
915 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
916 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
917 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
918 flags |= HTT_RX_RING_FLAGS_NULL_RX;
919 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
921 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
923 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr);
924 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr);
925 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
926 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
927 ring->flags = __cpu_to_le16(flags);
928 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
930 ath10k_htt_fill_rx_desc_offset_64(ring);
931 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
933 dev_kfree_skb_any(skb);
940 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
941 u8 max_subfrms_ampdu,
942 u8 max_subfrms_amsdu)
944 struct ath10k *ar = htt->ar;
945 struct htt_aggr_conf *aggr_conf;
951 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
953 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
956 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
959 len = sizeof(cmd->hdr);
960 len += sizeof(cmd->aggr_conf);
962 skb = ath10k_htc_alloc_skb(ar, len);
967 cmd = (struct htt_cmd *)skb->data;
968 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
970 aggr_conf = &cmd->aggr_conf;
971 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
972 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
974 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
975 aggr_conf->max_num_amsdu_subframes,
976 aggr_conf->max_num_ampdu_subframes);
978 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
980 dev_kfree_skb_any(skb);
987 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
989 __le16 fetch_seq_num,
990 struct htt_tx_fetch_record *records,
995 const u16 resp_id = 0;
999 /* Response IDs are echo-ed back only for host driver convienence
1000 * purposes. They aren't used for anything in the driver yet so use 0.
1003 len += sizeof(cmd->hdr);
1004 len += sizeof(cmd->tx_fetch_resp);
1005 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records;
1007 skb = ath10k_htc_alloc_skb(ar, len);
1012 cmd = (struct htt_cmd *)skb->data;
1013 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP;
1014 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id);
1015 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num;
1016 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records);
1017 cmd->tx_fetch_resp.token = token;
1019 memcpy(cmd->tx_fetch_resp.records, records,
1020 sizeof(records[0]) * num_records);
1022 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb);
1024 ath10k_warn(ar, "failed to submit htc command: %d\n", ret);
1031 dev_kfree_skb_any(skb);
1036 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb)
1038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1039 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
1040 struct ath10k_vif *arvif;
1042 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) {
1043 return ar->scan.vdev_id;
1044 } else if (cb->vif) {
1045 arvif = (void *)cb->vif->drv_priv;
1046 return arvif->vdev_id;
1047 } else if (ar->monitor_started) {
1048 return ar->monitor_vdev_id;
1054 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth)
1056 struct ieee80211_hdr *hdr = (void *)skb->data;
1057 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
1059 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control))
1060 return HTT_DATA_TX_EXT_TID_MGMT;
1061 else if (cb->flags & ATH10K_SKB_F_QOS)
1062 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
1064 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST;
1067 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
1069 struct ath10k *ar = htt->ar;
1070 struct device *dev = ar->dev;
1071 struct sk_buff *txdesc = NULL;
1072 struct htt_cmd *cmd;
1073 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1074 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1078 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1080 len += sizeof(cmd->hdr);
1081 len += sizeof(cmd->mgmt_tx);
1083 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1089 if ((ieee80211_is_action(hdr->frame_control) ||
1090 ieee80211_is_deauth(hdr->frame_control) ||
1091 ieee80211_is_disassoc(hdr->frame_control)) &&
1092 ieee80211_has_protected(hdr->frame_control)) {
1093 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1096 txdesc = ath10k_htc_alloc_skb(ar, len);
1099 goto err_free_msdu_id;
1102 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1104 res = dma_mapping_error(dev, skb_cb->paddr);
1107 goto err_free_txdesc;
1110 skb_put(txdesc, len);
1111 cmd = (struct htt_cmd *)txdesc->data;
1112 memset(cmd, 0, len);
1114 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
1115 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
1116 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
1117 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
1118 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
1119 memcpy(cmd->mgmt_tx.hdr, msdu->data,
1120 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
1122 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
1124 goto err_unmap_msdu;
1129 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1131 dev_kfree_skb_any(txdesc);
1133 spin_lock_bh(&htt->tx_lock);
1134 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1135 spin_unlock_bh(&htt->tx_lock);
1140 static int ath10k_htt_tx_32(struct ath10k_htt *htt,
1141 enum ath10k_hw_txrx_mode txmode,
1142 struct sk_buff *msdu)
1144 struct ath10k *ar = htt->ar;
1145 struct device *dev = ar->dev;
1146 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1147 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
1148 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1149 struct ath10k_hif_sg_item sg_items[2];
1150 struct ath10k_htt_txbuf_32 *txbuf;
1151 struct htt_data_tx_desc_frag *frags;
1152 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
1153 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1154 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
1158 u16 msdu_id, flags1 = 0;
1160 u32 frags_paddr = 0;
1162 struct htt_msdu_ext_desc *ext_desc = NULL;
1163 struct htt_msdu_ext_desc *ext_desc_t = NULL;
1165 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1171 prefetch_len = min(htt->prefetch_len, msdu->len);
1172 prefetch_len = roundup(prefetch_len, 4);
1174 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id;
1175 txbuf_paddr = htt->txbuf.paddr +
1176 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id);
1178 if ((ieee80211_is_action(hdr->frame_control) ||
1179 ieee80211_is_deauth(hdr->frame_control) ||
1180 ieee80211_is_disassoc(hdr->frame_control)) &&
1181 ieee80211_has_protected(hdr->frame_control)) {
1182 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1183 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
1184 txmode == ATH10K_HW_TXRX_RAW &&
1185 ieee80211_has_protected(hdr->frame_control)) {
1186 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1189 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1191 res = dma_mapping_error(dev, skb_cb->paddr);
1194 goto err_free_msdu_id;
1197 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
1198 freq = ar->scan.roc_freq;
1201 case ATH10K_HW_TXRX_RAW:
1202 case ATH10K_HW_TXRX_NATIVE_WIFI:
1203 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1205 case ATH10K_HW_TXRX_ETHERNET:
1206 if (ar->hw_params.continuous_frag_desc) {
1207 ext_desc_t = htt->frag_desc.vaddr_desc_32;
1208 memset(&ext_desc_t[msdu_id], 0,
1209 sizeof(struct htt_msdu_ext_desc));
1210 frags = (struct htt_data_tx_desc_frag *)
1211 &ext_desc_t[msdu_id].frags;
1212 ext_desc = &ext_desc_t[msdu_id];
1213 frags[0].tword_addr.paddr_lo =
1214 __cpu_to_le32(skb_cb->paddr);
1215 frags[0].tword_addr.paddr_hi = 0;
1216 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1218 frags_paddr = htt->frag_desc.paddr +
1219 (sizeof(struct htt_msdu_ext_desc) * msdu_id);
1221 frags = txbuf->frags;
1222 frags[0].dword_addr.paddr =
1223 __cpu_to_le32(skb_cb->paddr);
1224 frags[0].dword_addr.len = __cpu_to_le32(msdu->len);
1225 frags[1].dword_addr.paddr = 0;
1226 frags[1].dword_addr.len = 0;
1228 frags_paddr = txbuf_paddr;
1230 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1232 case ATH10K_HW_TXRX_MGMT:
1233 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
1234 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1235 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1237 frags_paddr = skb_cb->paddr;
1241 /* Normally all commands go through HTC which manages tx credits for
1242 * each endpoint and notifies when tx is completed.
1244 * HTT endpoint is creditless so there's no need to care about HTC
1245 * flags. In that case it is trivial to fill the HTC header here.
1247 * MSDU transmission is considered completed upon HTT event. This
1248 * implies no relevant resources can be freed until after the event is
1249 * received. That's why HTC tx completion handler itself is ignored by
1250 * setting NULL to transfer_context for all sg items.
1252 * There is simply no point in pushing HTT TX_FRM through HTC tx path
1253 * as it's a waste of resources. By bypassing HTC it is possible to
1254 * avoid extra memory allocations, compress data structures and thus
1255 * improve performance.
1258 txbuf->htc_hdr.eid = htt->eid;
1259 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
1260 sizeof(txbuf->cmd_tx) +
1262 txbuf->htc_hdr.flags = 0;
1264 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1265 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1267 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1268 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1269 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1270 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1271 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1272 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1273 if (ar->hw_params.continuous_frag_desc)
1274 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
1277 /* Prevent firmware from sending up tx inspection requests. There's
1278 * nothing ath10k can do with frames requested for inspection so force
1279 * it to simply rely a regular tx completion with discard status.
1281 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1283 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1284 txbuf->cmd_tx.flags0 = flags0;
1285 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
1286 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
1287 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
1288 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
1289 if (ath10k_mac_tx_frm_has_freq(ar)) {
1290 txbuf->cmd_tx.offchan_tx.peerid =
1291 __cpu_to_le16(HTT_INVALID_PEERID);
1292 txbuf->cmd_tx.offchan_tx.freq =
1293 __cpu_to_le16(freq);
1295 txbuf->cmd_tx.peerid =
1296 __cpu_to_le32(HTT_INVALID_PEERID);
1299 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1300 ath10k_dbg(ar, ATH10K_DBG_HTT,
1301 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n",
1302 flags0, flags1, msdu->len, msdu_id, &frags_paddr,
1303 &skb_cb->paddr, vdev_id, tid, freq);
1304 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1305 msdu->data, msdu->len);
1306 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1307 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1309 sg_items[0].transfer_id = 0;
1310 sg_items[0].transfer_context = NULL;
1311 sg_items[0].vaddr = &txbuf->htc_hdr;
1312 sg_items[0].paddr = txbuf_paddr +
1313 sizeof(txbuf->frags);
1314 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1315 sizeof(txbuf->cmd_hdr) +
1316 sizeof(txbuf->cmd_tx);
1318 sg_items[1].transfer_id = 0;
1319 sg_items[1].transfer_context = NULL;
1320 sg_items[1].vaddr = msdu->data;
1321 sg_items[1].paddr = skb_cb->paddr;
1322 sg_items[1].len = prefetch_len;
1324 res = ath10k_hif_tx_sg(htt->ar,
1325 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1326 sg_items, ARRAY_SIZE(sg_items));
1328 goto err_unmap_msdu;
1333 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1335 spin_lock_bh(&htt->tx_lock);
1336 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1337 spin_unlock_bh(&htt->tx_lock);
1342 static int ath10k_htt_tx_64(struct ath10k_htt *htt,
1343 enum ath10k_hw_txrx_mode txmode,
1344 struct sk_buff *msdu)
1346 struct ath10k *ar = htt->ar;
1347 struct device *dev = ar->dev;
1348 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1349 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
1350 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1351 struct ath10k_hif_sg_item sg_items[2];
1352 struct ath10k_htt_txbuf_64 *txbuf;
1353 struct htt_data_tx_desc_frag *frags;
1354 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
1355 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1356 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
1360 u16 msdu_id, flags1 = 0;
1362 dma_addr_t frags_paddr = 0;
1364 struct htt_msdu_ext_desc_64 *ext_desc = NULL;
1365 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL;
1367 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1373 prefetch_len = min(htt->prefetch_len, msdu->len);
1374 prefetch_len = roundup(prefetch_len, 4);
1376 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id;
1377 txbuf_paddr = htt->txbuf.paddr +
1378 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id);
1380 if ((ieee80211_is_action(hdr->frame_control) ||
1381 ieee80211_is_deauth(hdr->frame_control) ||
1382 ieee80211_is_disassoc(hdr->frame_control)) &&
1383 ieee80211_has_protected(hdr->frame_control)) {
1384 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1385 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
1386 txmode == ATH10K_HW_TXRX_RAW &&
1387 ieee80211_has_protected(hdr->frame_control)) {
1388 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1391 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1393 res = dma_mapping_error(dev, skb_cb->paddr);
1396 goto err_free_msdu_id;
1399 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
1400 freq = ar->scan.roc_freq;
1403 case ATH10K_HW_TXRX_RAW:
1404 case ATH10K_HW_TXRX_NATIVE_WIFI:
1405 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1407 case ATH10K_HW_TXRX_ETHERNET:
1408 if (ar->hw_params.continuous_frag_desc) {
1409 ext_desc_t = htt->frag_desc.vaddr_desc_64;
1410 memset(&ext_desc_t[msdu_id], 0,
1411 sizeof(struct htt_msdu_ext_desc_64));
1412 frags = (struct htt_data_tx_desc_frag *)
1413 &ext_desc_t[msdu_id].frags;
1414 ext_desc = &ext_desc_t[msdu_id];
1415 frags[0].tword_addr.paddr_lo =
1416 __cpu_to_le32(skb_cb->paddr);
1417 frags[0].tword_addr.paddr_hi =
1418 __cpu_to_le16(upper_32_bits(skb_cb->paddr));
1419 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1421 frags_paddr = htt->frag_desc.paddr +
1422 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id);
1424 frags = txbuf->frags;
1425 frags[0].tword_addr.paddr_lo =
1426 __cpu_to_le32(skb_cb->paddr);
1427 frags[0].tword_addr.paddr_hi =
1428 __cpu_to_le16(upper_32_bits(skb_cb->paddr));
1429 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1430 frags[1].tword_addr.paddr_lo = 0;
1431 frags[1].tword_addr.paddr_hi = 0;
1432 frags[1].tword_addr.len_16 = 0;
1434 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1436 case ATH10K_HW_TXRX_MGMT:
1437 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
1438 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1439 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1441 frags_paddr = skb_cb->paddr;
1445 /* Normally all commands go through HTC which manages tx credits for
1446 * each endpoint and notifies when tx is completed.
1448 * HTT endpoint is creditless so there's no need to care about HTC
1449 * flags. In that case it is trivial to fill the HTC header here.
1451 * MSDU transmission is considered completed upon HTT event. This
1452 * implies no relevant resources can be freed until after the event is
1453 * received. That's why HTC tx completion handler itself is ignored by
1454 * setting NULL to transfer_context for all sg items.
1456 * There is simply no point in pushing HTT TX_FRM through HTC tx path
1457 * as it's a waste of resources. By bypassing HTC it is possible to
1458 * avoid extra memory allocations, compress data structures and thus
1459 * improve performance.
1462 txbuf->htc_hdr.eid = htt->eid;
1463 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
1464 sizeof(txbuf->cmd_tx) +
1466 txbuf->htc_hdr.flags = 0;
1468 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1469 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1471 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1472 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1473 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1474 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1475 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1476 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1477 if (ar->hw_params.continuous_frag_desc) {
1478 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag));
1479 ext_desc->tso_flag[3] |=
1480 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64);
1484 /* Prevent firmware from sending up tx inspection requests. There's
1485 * nothing ath10k can do with frames requested for inspection so force
1486 * it to simply rely a regular tx completion with discard status.
1488 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1490 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1491 txbuf->cmd_tx.flags0 = flags0;
1492 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
1493 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
1494 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
1496 /* fill fragment descriptor */
1497 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr);
1498 if (ath10k_mac_tx_frm_has_freq(ar)) {
1499 txbuf->cmd_tx.offchan_tx.peerid =
1500 __cpu_to_le16(HTT_INVALID_PEERID);
1501 txbuf->cmd_tx.offchan_tx.freq =
1502 __cpu_to_le16(freq);
1504 txbuf->cmd_tx.peerid =
1505 __cpu_to_le32(HTT_INVALID_PEERID);
1508 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1509 ath10k_dbg(ar, ATH10K_DBG_HTT,
1510 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n",
1511 flags0, flags1, msdu->len, msdu_id, &frags_paddr,
1512 &skb_cb->paddr, vdev_id, tid, freq);
1513 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1514 msdu->data, msdu->len);
1515 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1516 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1518 sg_items[0].transfer_id = 0;
1519 sg_items[0].transfer_context = NULL;
1520 sg_items[0].vaddr = &txbuf->htc_hdr;
1521 sg_items[0].paddr = txbuf_paddr +
1522 sizeof(txbuf->frags);
1523 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1524 sizeof(txbuf->cmd_hdr) +
1525 sizeof(txbuf->cmd_tx);
1527 sg_items[1].transfer_id = 0;
1528 sg_items[1].transfer_context = NULL;
1529 sg_items[1].vaddr = msdu->data;
1530 sg_items[1].paddr = skb_cb->paddr;
1531 sg_items[1].len = prefetch_len;
1533 res = ath10k_hif_tx_sg(htt->ar,
1534 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1535 sg_items, ARRAY_SIZE(sg_items));
1537 goto err_unmap_msdu;
1542 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1544 spin_lock_bh(&htt->tx_lock);
1545 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1546 spin_unlock_bh(&htt->tx_lock);
1551 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = {
1552 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32,
1553 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32,
1554 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32,
1555 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32,
1556 .htt_tx = ath10k_htt_tx_32,
1557 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32,
1558 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32,
1561 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = {
1562 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64,
1563 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64,
1564 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64,
1565 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64,
1566 .htt_tx = ath10k_htt_tx_64,
1567 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64,
1568 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64,
1571 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt)
1573 struct ath10k *ar = htt->ar;
1575 if (ar->hw_params.target_64bit)
1576 htt->tx_ops = &htt_tx_ops_64;
1578 htt->tx_ops = &htt_tx_ops_32;