2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 static u8 ath10k_htt_tx_txq_calc_size(size_t count)
33 while (factor >= 64 && exp < 4) {
42 factor = max(1, factor);
44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) |
45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR);
48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
49 struct ieee80211_txq *txq)
51 struct ath10k *ar = hw->priv;
52 struct ath10k_sta *arsta;
53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv;
54 unsigned long frame_cnt;
55 unsigned long byte_cnt;
62 lockdep_assert_held(&ar->htt.tx_lock);
64 if (!ar->htt.tx_q_state.enabled)
67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
71 arsta = (void *)txq->sta->drv_priv;
72 peer_id = arsta->peer_id;
74 peer_id = arvif->peer_id;
78 bit = BIT(peer_id % 32);
81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
82 count = ath10k_htt_tx_txq_calc_size(byte_cnt);
84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) ||
85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) {
86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n",
91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count;
92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit;
93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0;
95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n",
99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar)
104 lockdep_assert_held(&ar->htt.tx_lock);
106 if (!ar->htt.tx_q_state.enabled)
109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq);
114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq);
116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n",
119 size = sizeof(*ar->htt.tx_q_state.vaddr);
120 dma_sync_single_for_device(ar->dev,
121 ar->htt.tx_q_state.paddr,
126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
127 struct ieee80211_txq *txq)
129 struct ath10k *ar = hw->priv;
131 spin_lock_bh(&ar->htt.tx_lock);
132 __ath10k_htt_tx_txq_recalc(hw, txq);
133 spin_unlock_bh(&ar->htt.tx_lock);
136 void ath10k_htt_tx_txq_sync(struct ath10k *ar)
138 spin_lock_bh(&ar->htt.tx_lock);
139 __ath10k_htt_tx_txq_sync(ar);
140 spin_unlock_bh(&ar->htt.tx_lock);
143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
144 struct ieee80211_txq *txq)
146 struct ath10k *ar = hw->priv;
148 spin_lock_bh(&ar->htt.tx_lock);
149 __ath10k_htt_tx_txq_recalc(hw, txq);
150 __ath10k_htt_tx_txq_sync(ar);
151 spin_unlock_bh(&ar->htt.tx_lock);
154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
156 lockdep_assert_held(&htt->tx_lock);
158 htt->num_pending_tx--;
159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
162 if (htt->num_pending_tx == 0)
163 wake_up(&htt->empty_tx_wq);
166 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
168 lockdep_assert_held(&htt->tx_lock);
170 if (htt->num_pending_tx >= htt->max_num_pending_tx)
173 htt->num_pending_tx++;
174 if (htt->num_pending_tx == htt->max_num_pending_tx)
175 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
180 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
183 struct ath10k *ar = htt->ar;
185 lockdep_assert_held(&htt->tx_lock);
187 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres)
191 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx)
194 htt->num_pending_mgmt_tx++;
199 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt)
201 lockdep_assert_held(&htt->tx_lock);
203 if (!htt->ar->hw_params.max_probe_resp_desc_thres)
206 htt->num_pending_mgmt_tx--;
209 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
211 struct ath10k *ar = htt->ar;
214 lockdep_assert_held(&htt->tx_lock);
216 ret = idr_alloc(&htt->pending_tx, skb, 0,
217 htt->max_num_pending_tx, GFP_ATOMIC);
219 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
224 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
226 struct ath10k *ar = htt->ar;
228 lockdep_assert_held(&htt->tx_lock);
230 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
232 idr_remove(&htt->pending_tx, msdu_id);
235 static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt)
239 if (!htt->frag_desc.vaddr)
242 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);
244 dma_free_coherent(htt->ar->dev,
246 htt->frag_desc.vaddr,
247 htt->frag_desc.paddr);
250 static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt)
252 struct ath10k *ar = htt->ar;
255 if (!ar->hw_params.continuous_frag_desc)
258 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);
259 htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size,
260 &htt->frag_desc.paddr,
262 if (!htt->frag_desc.vaddr) {
263 ath10k_err(ar, "failed to alloc fragment desc memory\n");
270 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt)
272 struct ath10k *ar = htt->ar;
275 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
276 ar->running_fw->fw_file.fw_features))
279 size = sizeof(*htt->tx_q_state.vaddr);
281 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE);
282 kfree(htt->tx_q_state.vaddr);
285 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt)
287 struct ath10k *ar = htt->ar;
291 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
292 ar->running_fw->fw_file.fw_features))
295 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS;
296 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS;
297 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES;
299 size = sizeof(*htt->tx_q_state.vaddr);
300 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL);
301 if (!htt->tx_q_state.vaddr)
304 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr,
305 size, DMA_TO_DEVICE);
306 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr);
308 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret);
309 kfree(htt->tx_q_state.vaddr);
316 int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
318 struct ath10k *ar = htt->ar;
321 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
322 htt->max_num_pending_tx);
324 spin_lock_init(&htt->tx_lock);
325 idr_init(&htt->pending_tx);
327 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf);
328 htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size,
331 if (!htt->txbuf.vaddr) {
332 ath10k_err(ar, "failed to alloc tx buffer\n");
334 goto free_idr_pending_tx;
337 ret = ath10k_htt_tx_alloc_cont_frag_desc(htt);
339 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);
343 ret = ath10k_htt_tx_alloc_txq(htt);
345 ath10k_err(ar, "failed to alloc txq: %d\n", ret);
349 size = roundup_pow_of_two(htt->max_num_pending_tx);
350 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL);
352 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret);
359 ath10k_htt_tx_free_txq(htt);
362 ath10k_htt_tx_free_cont_frag_desc(htt);
365 size = htt->max_num_pending_tx *
366 sizeof(struct ath10k_htt_txbuf);
367 dma_free_coherent(htt->ar->dev, size, htt->txbuf.vaddr,
371 idr_destroy(&htt->pending_tx);
376 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
378 struct ath10k *ar = ctx;
379 struct ath10k_htt *htt = &ar->htt;
380 struct htt_tx_done tx_done = {0};
382 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
384 tx_done.msdu_id = msdu_id;
385 tx_done.status = HTT_TX_COMPL_STATE_DISCARD;
387 ath10k_txrx_tx_unref(htt, &tx_done);
392 void ath10k_htt_tx_free(struct ath10k_htt *htt)
396 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
397 idr_destroy(&htt->pending_tx);
399 if (htt->txbuf.vaddr) {
400 size = htt->max_num_pending_tx *
401 sizeof(struct ath10k_htt_txbuf);
402 dma_free_coherent(htt->ar->dev, size, htt->txbuf.vaddr,
406 ath10k_htt_tx_free_txq(htt);
407 ath10k_htt_tx_free_cont_frag_desc(htt);
408 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo));
409 kfifo_free(&htt->txdone_fifo);
412 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
414 dev_kfree_skb_any(skb);
417 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb)
419 dev_kfree_skb_any(skb);
421 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete);
423 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
425 struct ath10k *ar = htt->ar;
431 len += sizeof(cmd->hdr);
432 len += sizeof(cmd->ver_req);
434 skb = ath10k_htc_alloc_skb(ar, len);
439 cmd = (struct htt_cmd *)skb->data;
440 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
442 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
444 dev_kfree_skb_any(skb);
451 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
453 struct ath10k *ar = htt->ar;
454 struct htt_stats_req *req;
459 len += sizeof(cmd->hdr);
460 len += sizeof(cmd->stats_req);
462 skb = ath10k_htc_alloc_skb(ar, len);
467 cmd = (struct htt_cmd *)skb->data;
468 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
470 req = &cmd->stats_req;
472 memset(req, 0, sizeof(*req));
474 /* currently we support only max 8 bit masks so no need to worry
475 * about endian support */
476 req->upload_types[0] = mask;
477 req->reset_types[0] = mask;
478 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
479 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
480 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
482 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
484 ath10k_warn(ar, "failed to send htt type stats request: %d",
486 dev_kfree_skb_any(skb);
493 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
495 struct ath10k *ar = htt->ar;
498 struct htt_frag_desc_bank_cfg *cfg;
502 if (!ar->hw_params.continuous_frag_desc)
505 if (!htt->frag_desc.paddr) {
506 ath10k_warn(ar, "invalid frag desc memory\n");
510 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg);
511 skb = ath10k_htc_alloc_skb(ar, size);
516 cmd = (struct htt_cmd *)skb->data;
517 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
520 info |= SM(htt->tx_q_state.type,
521 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
523 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
524 ar->running_fw->fw_file.fw_features))
525 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
527 cfg = &cmd->frag_desc_bank_cfg;
530 cfg->desc_size = sizeof(struct htt_msdu_ext_desc);
531 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr);
532 cfg->bank_id[0].bank_min_id = 0;
533 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
536 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
537 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
538 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
539 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
540 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
542 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
544 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
546 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
548 dev_kfree_skb_any(skb);
555 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
557 struct ath10k *ar = htt->ar;
560 struct htt_rx_ring_setup_ring *ring;
561 const int num_rx_ring = 1;
568 * the HW expects the buffer to be an integral number of 4-byte
571 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
572 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
574 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
575 + (sizeof(*ring) * num_rx_ring);
576 skb = ath10k_htc_alloc_skb(ar, len);
582 cmd = (struct htt_cmd *)skb->data;
583 ring = &cmd->rx_setup.rings[0];
585 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
586 cmd->rx_setup.hdr.num_rings = 1;
588 /* FIXME: do we need all of this? */
590 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
591 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
592 flags |= HTT_RX_RING_FLAGS_PPDU_START;
593 flags |= HTT_RX_RING_FLAGS_PPDU_END;
594 flags |= HTT_RX_RING_FLAGS_MPDU_START;
595 flags |= HTT_RX_RING_FLAGS_MPDU_END;
596 flags |= HTT_RX_RING_FLAGS_MSDU_START;
597 flags |= HTT_RX_RING_FLAGS_MSDU_END;
598 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
599 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
600 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
601 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
602 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
603 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
604 flags |= HTT_RX_RING_FLAGS_NULL_RX;
605 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
607 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
609 ring->fw_idx_shadow_reg_paddr =
610 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
611 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
612 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
613 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
614 ring->flags = __cpu_to_le16(flags);
615 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
617 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
619 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
620 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
621 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
622 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
623 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
624 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
625 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
626 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
627 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
628 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
632 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
634 dev_kfree_skb_any(skb);
641 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
642 u8 max_subfrms_ampdu,
643 u8 max_subfrms_amsdu)
645 struct ath10k *ar = htt->ar;
646 struct htt_aggr_conf *aggr_conf;
652 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
654 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
657 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
660 len = sizeof(cmd->hdr);
661 len += sizeof(cmd->aggr_conf);
663 skb = ath10k_htc_alloc_skb(ar, len);
668 cmd = (struct htt_cmd *)skb->data;
669 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
671 aggr_conf = &cmd->aggr_conf;
672 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
673 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
675 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
676 aggr_conf->max_num_amsdu_subframes,
677 aggr_conf->max_num_ampdu_subframes);
679 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
681 dev_kfree_skb_any(skb);
688 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
690 __le16 fetch_seq_num,
691 struct htt_tx_fetch_record *records,
696 const u16 resp_id = 0;
700 /* Response IDs are echo-ed back only for host driver convienence
701 * purposes. They aren't used for anything in the driver yet so use 0.
704 len += sizeof(cmd->hdr);
705 len += sizeof(cmd->tx_fetch_resp);
706 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records;
708 skb = ath10k_htc_alloc_skb(ar, len);
713 cmd = (struct htt_cmd *)skb->data;
714 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP;
715 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id);
716 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num;
717 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records);
718 cmd->tx_fetch_resp.token = token;
720 memcpy(cmd->tx_fetch_resp.records, records,
721 sizeof(records[0]) * num_records);
723 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb);
725 ath10k_warn(ar, "failed to submit htc command: %d\n", ret);
732 dev_kfree_skb_any(skb);
737 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb)
739 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
740 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
741 struct ath10k_vif *arvif;
743 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) {
744 return ar->scan.vdev_id;
745 } else if (cb->vif) {
746 arvif = (void *)cb->vif->drv_priv;
747 return arvif->vdev_id;
748 } else if (ar->monitor_started) {
749 return ar->monitor_vdev_id;
755 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth)
757 struct ieee80211_hdr *hdr = (void *)skb->data;
758 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
760 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control))
761 return HTT_DATA_TX_EXT_TID_MGMT;
762 else if (cb->flags & ATH10K_SKB_F_QOS)
763 return skb->priority % IEEE80211_QOS_CTL_TID_MASK;
765 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST;
768 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
770 struct ath10k *ar = htt->ar;
771 struct device *dev = ar->dev;
772 struct sk_buff *txdesc = NULL;
774 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
775 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
779 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
781 len += sizeof(cmd->hdr);
782 len += sizeof(cmd->mgmt_tx);
784 spin_lock_bh(&htt->tx_lock);
785 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
786 spin_unlock_bh(&htt->tx_lock);
792 if ((ieee80211_is_action(hdr->frame_control) ||
793 ieee80211_is_deauth(hdr->frame_control) ||
794 ieee80211_is_disassoc(hdr->frame_control)) &&
795 ieee80211_has_protected(hdr->frame_control)) {
796 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
799 txdesc = ath10k_htc_alloc_skb(ar, len);
802 goto err_free_msdu_id;
805 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
807 res = dma_mapping_error(dev, skb_cb->paddr);
810 goto err_free_txdesc;
813 skb_put(txdesc, len);
814 cmd = (struct htt_cmd *)txdesc->data;
817 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
818 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
819 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
820 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
821 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
822 memcpy(cmd->mgmt_tx.hdr, msdu->data,
823 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
825 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
832 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
834 dev_kfree_skb_any(txdesc);
836 spin_lock_bh(&htt->tx_lock);
837 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
838 spin_unlock_bh(&htt->tx_lock);
843 int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
844 struct sk_buff *msdu)
846 struct ath10k *ar = htt->ar;
847 struct device *dev = ar->dev;
848 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
849 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
850 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
851 struct ath10k_hif_sg_item sg_items[2];
852 struct ath10k_htt_txbuf *txbuf;
853 struct htt_data_tx_desc_frag *frags;
854 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
855 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
856 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
860 u16 msdu_id, flags1 = 0;
864 struct htt_msdu_ext_desc *ext_desc = NULL;
866 spin_lock_bh(&htt->tx_lock);
867 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
868 spin_unlock_bh(&htt->tx_lock);
874 prefetch_len = min(htt->prefetch_len, msdu->len);
875 prefetch_len = roundup(prefetch_len, 4);
877 txbuf = &htt->txbuf.vaddr[msdu_id];
878 txbuf_paddr = htt->txbuf.paddr +
879 (sizeof(struct ath10k_htt_txbuf) * msdu_id);
881 if ((ieee80211_is_action(hdr->frame_control) ||
882 ieee80211_is_deauth(hdr->frame_control) ||
883 ieee80211_is_disassoc(hdr->frame_control)) &&
884 ieee80211_has_protected(hdr->frame_control)) {
885 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
886 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
887 txmode == ATH10K_HW_TXRX_RAW &&
888 ieee80211_has_protected(hdr->frame_control)) {
889 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
892 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
894 res = dma_mapping_error(dev, skb_cb->paddr);
897 goto err_free_msdu_id;
900 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
901 freq = ar->scan.roc_freq;
904 case ATH10K_HW_TXRX_RAW:
905 case ATH10K_HW_TXRX_NATIVE_WIFI:
906 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
908 case ATH10K_HW_TXRX_ETHERNET:
909 if (ar->hw_params.continuous_frag_desc) {
910 memset(&htt->frag_desc.vaddr[msdu_id], 0,
911 sizeof(struct htt_msdu_ext_desc));
912 frags = (struct htt_data_tx_desc_frag *)
913 &htt->frag_desc.vaddr[msdu_id].frags;
914 ext_desc = &htt->frag_desc.vaddr[msdu_id];
915 frags[0].tword_addr.paddr_lo =
916 __cpu_to_le32(skb_cb->paddr);
917 frags[0].tword_addr.paddr_hi = 0;
918 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
920 frags_paddr = htt->frag_desc.paddr +
921 (sizeof(struct htt_msdu_ext_desc) * msdu_id);
923 frags = txbuf->frags;
924 frags[0].dword_addr.paddr =
925 __cpu_to_le32(skb_cb->paddr);
926 frags[0].dword_addr.len = __cpu_to_le32(msdu->len);
927 frags[1].dword_addr.paddr = 0;
928 frags[1].dword_addr.len = 0;
930 frags_paddr = txbuf_paddr;
932 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
934 case ATH10K_HW_TXRX_MGMT:
935 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
936 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
937 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
939 frags_paddr = skb_cb->paddr;
943 /* Normally all commands go through HTC which manages tx credits for
944 * each endpoint and notifies when tx is completed.
946 * HTT endpoint is creditless so there's no need to care about HTC
947 * flags. In that case it is trivial to fill the HTC header here.
949 * MSDU transmission is considered completed upon HTT event. This
950 * implies no relevant resources can be freed until after the event is
951 * received. That's why HTC tx completion handler itself is ignored by
952 * setting NULL to transfer_context for all sg items.
954 * There is simply no point in pushing HTT TX_FRM through HTC tx path
955 * as it's a waste of resources. By bypassing HTC it is possible to
956 * avoid extra memory allocations, compress data structures and thus
957 * improve performance. */
959 txbuf->htc_hdr.eid = htt->eid;
960 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
961 sizeof(txbuf->cmd_tx) +
963 txbuf->htc_hdr.flags = 0;
965 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
966 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
968 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
969 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
970 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
971 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
972 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
973 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
974 if (ar->hw_params.continuous_frag_desc)
975 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
978 /* Prevent firmware from sending up tx inspection requests. There's
979 * nothing ath10k can do with frames requested for inspection so force
980 * it to simply rely a regular tx completion with discard status.
982 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
984 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
985 txbuf->cmd_tx.flags0 = flags0;
986 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
987 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
988 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
989 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
990 if (ath10k_mac_tx_frm_has_freq(ar)) {
991 txbuf->cmd_tx.offchan_tx.peerid =
992 __cpu_to_le16(HTT_INVALID_PEERID);
993 txbuf->cmd_tx.offchan_tx.freq =
996 txbuf->cmd_tx.peerid =
997 __cpu_to_le32(HTT_INVALID_PEERID);
1000 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1001 ath10k_dbg(ar, ATH10K_DBG_HTT,
1002 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
1003 flags0, flags1, msdu->len, msdu_id, frags_paddr,
1004 (u32)skb_cb->paddr, vdev_id, tid, freq);
1005 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1006 msdu->data, msdu->len);
1007 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1008 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1010 sg_items[0].transfer_id = 0;
1011 sg_items[0].transfer_context = NULL;
1012 sg_items[0].vaddr = &txbuf->htc_hdr;
1013 sg_items[0].paddr = txbuf_paddr +
1014 sizeof(txbuf->frags);
1015 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1016 sizeof(txbuf->cmd_hdr) +
1017 sizeof(txbuf->cmd_tx);
1019 sg_items[1].transfer_id = 0;
1020 sg_items[1].transfer_context = NULL;
1021 sg_items[1].vaddr = msdu->data;
1022 sg_items[1].paddr = skb_cb->paddr;
1023 sg_items[1].len = prefetch_len;
1025 res = ath10k_hif_tx_sg(htt->ar,
1026 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1027 sg_items, ARRAY_SIZE(sg_items));
1029 goto err_unmap_msdu;
1034 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1036 ath10k_htt_tx_free_msdu_id(htt, msdu_id);