2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
96 ieee80211_tx_status_noskb(hw, sta, info);
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
116 void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
119 struct ath_chanctx *ctx = avp->chanctx;
121 struct list_head *tid_list;
122 u8 acno = TID_TO_WME_AC(tid->tidno);
124 if (!ctx || !list_empty(&tid->list))
128 acq = &ctx->acq[acno];
129 if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) &&
130 tid->an->airtime_deficit[acno] > 0)
131 tid_list = &acq->acq_new;
133 tid_list = &acq->acq_old;
135 list_add_tail(&tid->list, tid_list);
138 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
140 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
141 struct ath_chanctx *ctx = avp->chanctx;
144 if (!ctx || !list_empty(&tid->list))
147 acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
148 spin_lock_bh(&acq->lock);
149 __ath_tx_queue_tid(sc, tid);
150 spin_unlock_bh(&acq->lock);
154 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
156 struct ath_softc *sc = hw->priv;
157 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
158 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
159 struct ath_txq *txq = tid->txq;
161 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
162 queue->sta ? queue->sta->addr : queue->vif->addr,
165 ath_txq_lock(sc, txq);
167 tid->has_queued = true;
168 ath_tx_queue_tid(sc, tid);
169 ath_txq_schedule(sc, txq);
171 ath_txq_unlock(sc, txq);
174 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
176 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
177 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
178 sizeof(tx_info->rate_driver_data));
179 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
182 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
187 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
188 seqno << IEEE80211_SEQ_SEQ_SHIFT);
191 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
194 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
195 ARRAY_SIZE(bf->rates));
198 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
201 struct ath_frame_info *fi = get_frame_info(skb);
207 txq = sc->tx.txq_map[q];
208 if (WARN_ON(--txq->pending_frames < 0))
209 txq->pending_frames = 0;
213 static struct ath_atx_tid *
214 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
216 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
217 return ATH_AN_2_TID(an, tidno);
220 static struct sk_buff *
221 ath_tid_pull(struct ath_atx_tid *tid)
223 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
224 struct ath_softc *sc = tid->an->sc;
225 struct ieee80211_hw *hw = sc->hw;
226 struct ath_tx_control txctl = {
231 struct ath_frame_info *fi;
234 if (!tid->has_queued)
237 skb = ieee80211_tx_dequeue(hw, txq);
239 tid->has_queued = false;
243 if (ath_tx_prepare(hw, skb, &txctl)) {
244 ieee80211_free_txskb(hw, skb);
248 q = skb_get_queue_mapping(skb);
249 if (tid->txq == sc->tx.txq_map[q]) {
250 fi = get_frame_info(skb);
252 ++tid->txq->pending_frames;
259 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
261 return !skb_queue_empty(&tid->retry_q) || tid->has_queued;
264 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
268 skb = __skb_dequeue(&tid->retry_q);
270 skb = ath_tid_pull(tid);
275 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
277 struct ath_txq *txq = tid->txq;
280 struct list_head bf_head;
281 struct ath_tx_status ts;
282 struct ath_frame_info *fi;
283 bool sendbar = false;
285 INIT_LIST_HEAD(&bf_head);
287 memset(&ts, 0, sizeof(ts));
289 while ((skb = __skb_dequeue(&tid->retry_q))) {
290 fi = get_frame_info(skb);
293 ath_txq_skb_done(sc, txq, skb);
294 ieee80211_free_txskb(sc->hw, skb);
298 if (fi->baw_tracked) {
299 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
303 list_add_tail(&bf->list, &bf_head);
304 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
308 ath_txq_unlock(sc, txq);
309 ath_send_bar(tid, tid->seq_start);
310 ath_txq_lock(sc, txq);
314 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
319 index = ATH_BA_INDEX(tid->seq_start, seqno);
320 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
322 __clear_bit(cindex, tid->tx_buf);
324 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
325 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
326 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
327 if (tid->bar_index >= 0)
332 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
335 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
336 u16 seqno = bf->bf_state.seqno;
339 index = ATH_BA_INDEX(tid->seq_start, seqno);
340 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
341 __set_bit(cindex, tid->tx_buf);
344 if (index >= ((tid->baw_tail - tid->baw_head) &
345 (ATH_TID_MAX_BUFS - 1))) {
346 tid->baw_tail = cindex;
347 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
351 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
352 struct ath_atx_tid *tid)
357 struct list_head bf_head;
358 struct ath_tx_status ts;
359 struct ath_frame_info *fi;
361 memset(&ts, 0, sizeof(ts));
362 INIT_LIST_HEAD(&bf_head);
364 while ((skb = ath_tid_dequeue(tid))) {
365 fi = get_frame_info(skb);
369 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
373 list_add_tail(&bf->list, &bf_head);
374 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
378 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
379 struct sk_buff *skb, int count)
381 struct ath_frame_info *fi = get_frame_info(skb);
382 struct ath_buf *bf = fi->bf;
383 struct ieee80211_hdr *hdr;
384 int prev = fi->retries;
386 TX_STAT_INC(txq->axq_qnum, a_retries);
387 fi->retries += count;
392 hdr = (struct ieee80211_hdr *)skb->data;
393 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
394 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
395 sizeof(*hdr), DMA_TO_DEVICE);
398 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
400 struct ath_buf *bf = NULL;
402 spin_lock_bh(&sc->tx.txbuflock);
404 if (unlikely(list_empty(&sc->tx.txbuf))) {
405 spin_unlock_bh(&sc->tx.txbuflock);
409 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
412 spin_unlock_bh(&sc->tx.txbuflock);
417 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
419 spin_lock_bh(&sc->tx.txbuflock);
420 list_add_tail(&bf->list, &sc->tx.txbuf);
421 spin_unlock_bh(&sc->tx.txbuflock);
424 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
428 tbf = ath_tx_get_buffer(sc);
432 ATH_TXBUF_RESET(tbf);
434 tbf->bf_mpdu = bf->bf_mpdu;
435 tbf->bf_buf_addr = bf->bf_buf_addr;
436 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
437 tbf->bf_state = bf->bf_state;
438 tbf->bf_state.stale = false;
443 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
444 struct ath_tx_status *ts, int txok,
445 int *nframes, int *nbad)
447 struct ath_frame_info *fi;
449 u32 ba[WME_BA_BMP_SIZE >> 5];
456 isaggr = bf_isaggr(bf);
458 seq_st = ts->ts_seqnum;
459 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
463 fi = get_frame_info(bf->bf_mpdu);
464 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
467 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
475 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
476 struct ath_buf *bf, struct list_head *bf_q,
477 struct ieee80211_sta *sta,
478 struct ath_atx_tid *tid,
479 struct ath_tx_status *ts, int txok)
481 struct ath_node *an = NULL;
483 struct ieee80211_hdr *hdr;
484 struct ieee80211_tx_info *tx_info;
485 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
486 struct list_head bf_head;
487 struct sk_buff_head bf_pending;
488 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
489 u32 ba[WME_BA_BMP_SIZE >> 5];
490 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
491 bool rc_update = true, isba;
492 struct ieee80211_tx_rate rates[4];
493 struct ath_frame_info *fi;
495 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
500 hdr = (struct ieee80211_hdr *)skb->data;
502 tx_info = IEEE80211_SKB_CB(skb);
504 memcpy(rates, bf->rates, sizeof(rates));
506 retries = ts->ts_longretry + 1;
507 for (i = 0; i < ts->ts_rateindex; i++)
508 retries += rates[i].count;
511 INIT_LIST_HEAD(&bf_head);
513 bf_next = bf->bf_next;
515 if (!bf->bf_state.stale || bf_next != NULL)
516 list_move_tail(&bf->list, &bf_head);
518 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
525 an = (struct ath_node *)sta->drv_priv;
526 seq_first = tid->seq_start;
527 isba = ts->ts_flags & ATH9K_TX_BA;
530 * The hardware occasionally sends a tx status for the wrong TID.
531 * In this case, the BA status cannot be considered valid and all
532 * subframes need to be retransmitted
534 * Only BlockAcks have a TID and therefore normal Acks cannot be
537 if (isba && tid->tidno != ts->tid)
540 isaggr = bf_isaggr(bf);
541 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
543 if (isaggr && txok) {
544 if (ts->ts_flags & ATH9K_TX_BA) {
545 seq_st = ts->ts_seqnum;
546 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
549 * AR5416 can become deaf/mute when BA
550 * issue happens. Chip needs to be reset.
551 * But AP code may have sychronization issues
552 * when perform internal reset in this routine.
553 * Only enable reset in STA mode for now.
555 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
560 __skb_queue_head_init(&bf_pending);
562 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
564 u16 seqno = bf->bf_state.seqno;
566 txfail = txpending = sendbar = 0;
567 bf_next = bf->bf_next;
570 tx_info = IEEE80211_SKB_CB(skb);
571 fi = get_frame_info(skb);
573 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
576 * Outside of the current BlockAck window,
577 * maybe part of a previous session
580 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
581 /* transmit completion, subframe is
582 * acked by block ack */
584 } else if (!isaggr && txok) {
585 /* transmit completion */
589 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
590 if (txok || !an->sleeping)
591 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
598 bar_index = max_t(int, bar_index,
599 ATH_BA_INDEX(seq_first, seqno));
603 * Make sure the last desc is reclaimed if it
604 * not a holding desc.
606 INIT_LIST_HEAD(&bf_head);
607 if (bf_next != NULL || !bf_last->bf_state.stale)
608 list_move_tail(&bf->list, &bf_head);
612 * complete the acked-ones/xretried ones; update
615 ath_tx_update_baw(sc, tid, seqno);
617 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
618 memcpy(tx_info->control.rates, rates, sizeof(rates));
619 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
621 if (bf == bf->bf_lastbf)
622 ath_dynack_sample_tx_ts(sc->sc_ah,
627 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
630 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
631 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
632 ieee80211_sta_eosp(sta);
634 /* retry the un-acked ones */
635 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
638 tbf = ath_clone_txbuf(sc, bf_last);
640 * Update tx baw and complete the
641 * frame with failed status if we
645 ath_tx_update_baw(sc, tid, seqno);
647 ath_tx_complete_buf(sc, bf, txq,
650 bar_index = max_t(int, bar_index,
651 ATH_BA_INDEX(seq_first, seqno));
659 * Put this buffer to the temporary pending
660 * queue to retain ordering
662 __skb_queue_tail(&bf_pending, skb);
668 /* prepend un-acked frames to the beginning of the pending frame queue */
669 if (!skb_queue_empty(&bf_pending)) {
671 ieee80211_sta_set_buffered(sta, tid->tidno, true);
673 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
675 ath_tx_queue_tid(sc, tid);
677 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
678 tid->clear_ps_filter = true;
682 if (bar_index >= 0) {
683 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
685 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
686 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
688 ath_txq_unlock(sc, txq);
689 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
690 ath_txq_lock(sc, txq);
694 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
697 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
699 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
700 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
703 static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_node *an,
704 struct ath_atx_tid *tid, struct ath_buf *bf,
705 struct ath_tx_status *ts)
707 struct ath_txq *txq = tid->txq;
711 airtime += ts->duration * (ts->ts_longretry + 1);
712 for(i = 0; i < ts->ts_rateindex; i++) {
713 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
714 airtime += rate_dur * bf->rates[i].count;
717 if (sc->airtime_flags & AIRTIME_USE_TX) {
718 int q = txq->mac80211_qnum;
719 struct ath_acq *acq = &sc->cur_chan->acq[q];
721 spin_lock_bh(&acq->lock);
722 an->airtime_deficit[q] -= airtime;
723 if (an->airtime_deficit[q] <= 0)
724 __ath_tx_queue_tid(sc, tid);
725 spin_unlock_bh(&acq->lock);
727 ath_debug_airtime(sc, an, 0, airtime);
730 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
731 struct ath_tx_status *ts, struct ath_buf *bf,
732 struct list_head *bf_head)
734 struct ieee80211_hw *hw = sc->hw;
735 struct ieee80211_tx_info *info;
736 struct ieee80211_sta *sta;
737 struct ieee80211_hdr *hdr;
738 struct ath_atx_tid *tid = NULL;
741 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
742 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
743 txq->axq_tx_inprogress = false;
746 if (bf_is_ampdu_not_probing(bf))
747 txq->axq_ampdu_depth--;
749 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
752 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
753 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
755 struct ath_node *an = (struct ath_node *)sta->drv_priv;
756 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
757 ath_tx_count_airtime(sc, an, tid, bf, ts);
758 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
759 tid->clear_ps_filter = true;
762 if (!bf_isampdu(bf)) {
764 info = IEEE80211_SKB_CB(bf->bf_mpdu);
765 memcpy(info->control.rates, bf->rates,
766 sizeof(info->control.rates));
767 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
768 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
771 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
773 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
776 ath_txq_schedule(sc, txq);
779 static bool ath_lookup_legacy(struct ath_buf *bf)
782 struct ieee80211_tx_info *tx_info;
783 struct ieee80211_tx_rate *rates;
787 tx_info = IEEE80211_SKB_CB(skb);
788 rates = tx_info->control.rates;
790 for (i = 0; i < 4; i++) {
791 if (!rates[i].count || rates[i].idx < 0)
794 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
801 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
802 struct ath_atx_tid *tid)
805 struct ieee80211_tx_info *tx_info;
806 struct ieee80211_tx_rate *rates;
807 u32 max_4ms_framelen, frmlen;
808 u16 aggr_limit, bt_aggr_limit, legacy = 0;
809 int q = tid->txq->mac80211_qnum;
813 tx_info = IEEE80211_SKB_CB(skb);
817 * Find the lowest frame length among the rate series that will have a
818 * 4ms (or TXOP limited) transmit duration.
820 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
822 for (i = 0; i < 4; i++) {
828 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
833 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
838 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
841 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
842 max_4ms_framelen = min(max_4ms_framelen, frmlen);
846 * limit aggregate size by the minimum rate if rate selected is
847 * not a probe rate, if rate selected is a probe rate then
848 * avoid aggregation of this packet.
850 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
853 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
856 * Override the default aggregation limit for BTCOEX.
858 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
860 aggr_limit = bt_aggr_limit;
862 if (tid->an->maxampdu)
863 aggr_limit = min(aggr_limit, tid->an->maxampdu);
869 * Returns the number of delimiters to be added to
870 * meet the minimum required mpdudensity.
872 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
873 struct ath_buf *bf, u16 frmlen,
876 #define FIRST_DESC_NDELIMS 60
877 u32 nsymbits, nsymbols;
880 int width, streams, half_gi, ndelim, mindelim;
881 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
883 /* Select standard number of delimiters based on frame length alone */
884 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
887 * If encryption enabled, hardware requires some more padding between
889 * TODO - this could be improved to be dependent on the rate.
890 * The hardware can keep up at lower rates, but not higher rates
892 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
893 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
894 ndelim += ATH_AGGR_ENCRYPTDELIM;
897 * Add delimiter when using RTS/CTS with aggregation
898 * and non enterprise AR9003 card
900 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
901 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
902 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
905 * Convert desired mpdu density from microeconds to bytes based
906 * on highest rate in rate series (i.e. first rate) to determine
907 * required minimum length for subframe. Take into account
908 * whether high rate is 20 or 40Mhz and half or full GI.
910 * If there is no mpdu density restriction, no further calculation
914 if (tid->an->mpdudensity == 0)
917 rix = bf->rates[0].idx;
918 flags = bf->rates[0].flags;
919 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
920 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
923 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
925 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
930 streams = HT_RC_2_STREAMS(rix);
931 nsymbits = bits_per_symbol[rix % 8][width] * streams;
932 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
934 if (frmlen < minlen) {
935 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
936 ndelim = max(mindelim, ndelim);
942 static struct ath_buf *
943 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
944 struct ath_atx_tid *tid)
946 struct ieee80211_tx_info *tx_info;
947 struct ath_frame_info *fi;
948 struct sk_buff *skb, *first_skb = NULL;
953 skb = ath_tid_dequeue(tid);
957 fi = get_frame_info(skb);
960 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
962 bf->bf_state.stale = false;
965 ath_txq_skb_done(sc, txq, skb);
966 ieee80211_free_txskb(sc->hw, skb);
973 tx_info = IEEE80211_SKB_CB(skb);
974 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
977 * No aggregation session is running, but there may be frames
978 * from a previous session or a failed attempt in the queue.
979 * Send them out as normal data frames
982 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
984 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
985 bf->bf_state.bf_type = 0;
989 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
990 seqno = bf->bf_state.seqno;
992 /* do not step over block-ack window */
993 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
994 __skb_queue_tail(&tid->retry_q, skb);
996 /* If there are other skbs in the retry q, they are
997 * probably within the BAW, so loop immediately to get
998 * one of them. Otherwise the queue can get stuck. */
999 if (!skb_queue_is_first(&tid->retry_q, skb) &&
1000 !WARN_ON(skb == first_skb)) {
1001 if(!first_skb) /* infinite loop prevention */
1008 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1009 struct ath_tx_status ts = {};
1010 struct list_head bf_head;
1012 INIT_LIST_HEAD(&bf_head);
1013 list_add(&bf->list, &bf_head);
1014 ath_tx_update_baw(sc, tid, seqno);
1015 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1026 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1027 struct ath_atx_tid *tid, struct list_head *bf_q,
1028 struct ath_buf *bf_first)
1030 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1031 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1032 int nframes = 0, ndelim;
1033 u16 aggr_limit = 0, al = 0, bpad = 0,
1034 al_delta, h_baw = tid->baw_size / 2;
1035 struct ieee80211_tx_info *tx_info;
1036 struct ath_frame_info *fi;
1037 struct sk_buff *skb;
1041 aggr_limit = ath_lookup_rate(sc, bf, tid);
1046 fi = get_frame_info(skb);
1048 /* do not exceed aggregation limit */
1049 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1051 if (aggr_limit < al + bpad + al_delta ||
1052 ath_lookup_legacy(bf) || nframes >= h_baw)
1055 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1056 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1057 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1061 /* add padding for previous frame to aggregation length */
1062 al += bpad + al_delta;
1065 * Get the delimiters needed to meet the MPDU
1066 * density for this node.
1068 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1070 bpad = PADBYTES(al_delta) + (ndelim << 2);
1075 /* link buffers of this frame to the aggregate */
1076 if (!fi->baw_tracked)
1077 ath_tx_addto_baw(sc, tid, bf);
1078 bf->bf_state.ndelim = ndelim;
1080 list_add_tail(&bf->list, bf_q);
1082 bf_prev->bf_next = bf;
1086 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1090 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1093 bf->bf_lastbf = bf_prev;
1095 if (bf == bf_prev) {
1096 al = get_frame_info(bf->bf_mpdu)->framelen;
1097 bf->bf_state.bf_type = BUF_AMPDU;
1099 TX_STAT_INC(txq->axq_qnum, a_aggr);
1108 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1109 * width - 0 for 20 MHz, 1 for 40 MHz
1110 * half_gi - to use 4us v/s 3.6 us for symbol time
1112 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1113 int width, int half_gi, bool shortPreamble)
1115 u32 nbits, nsymbits, duration, nsymbols;
1118 /* find number of symbols: PLCP + data */
1119 streams = HT_RC_2_STREAMS(rix);
1120 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1121 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1122 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1125 duration = SYMBOL_TIME(nsymbols);
1127 duration = SYMBOL_TIME_HALFGI(nsymbols);
1129 /* addup duration for legacy/ht training and signal fields */
1130 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1135 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1137 int streams = HT_RC_2_STREAMS(mcs);
1141 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1142 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1143 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1144 bits -= OFDM_PLCP_BITS;
1152 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1154 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1157 /* 4ms is the default (and maximum) duration */
1158 if (!txop || txop > 4096)
1161 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1162 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1163 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1164 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1165 for (mcs = 0; mcs < 32; mcs++) {
1166 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1167 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1168 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1169 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1173 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1174 u8 rateidx, bool is_40, bool is_cck)
1177 struct sk_buff *skb;
1178 struct ath_frame_info *fi;
1179 struct ieee80211_tx_info *info;
1180 struct ath_hw *ah = sc->sc_ah;
1182 if (sc->tx99_state || !ah->tpc_enabled)
1183 return MAX_RATE_POWER;
1186 fi = get_frame_info(skb);
1187 info = IEEE80211_SKB_CB(skb);
1189 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1190 int txpower = fi->tx_power;
1194 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1195 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1197 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1199 struct modal_eep_header *pmodal;
1201 is_2ghz = info->band == NL80211_BAND_2GHZ;
1202 pmodal = &eep->modalHeader[is_2ghz];
1203 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1205 power_ht40delta = 2;
1207 txpower += power_ht40delta;
1210 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1212 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1213 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1216 power_offset = ah->eep_ops->get_eeprom(ah,
1217 EEP_PWR_TABLE_OFFSET);
1218 txpower -= 2 * power_offset;
1221 if (OLC_FOR_AR9280_20_LATER && is_cck)
1224 txpower = max(txpower, 0);
1225 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1227 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1228 * max_power is set to 0, frames are transmitted at max
1231 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1233 } else if (!bf->bf_state.bfs_paprd) {
1234 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1235 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1238 max_power = min_t(u8, ah->tx_power[rateidx],
1241 max_power = ah->paprd_training_power;
1247 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1248 struct ath_tx_info *info, int len, bool rts)
1250 struct ath_hw *ah = sc->sc_ah;
1251 struct ath_common *common = ath9k_hw_common(ah);
1252 struct sk_buff *skb;
1253 struct ieee80211_tx_info *tx_info;
1254 struct ieee80211_tx_rate *rates;
1255 const struct ieee80211_rate *rate;
1256 struct ieee80211_hdr *hdr;
1257 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1258 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1263 tx_info = IEEE80211_SKB_CB(skb);
1265 hdr = (struct ieee80211_hdr *)skb->data;
1267 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1268 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1269 info->rtscts_rate = fi->rtscts_rate;
1271 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1272 bool is_40, is_sgi, is_sp, is_cck;
1275 if (!rates[i].count || (rates[i].idx < 0))
1279 info->rates[i].Tries = rates[i].count;
1282 * Handle RTS threshold for unaggregated HT frames.
1284 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1285 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1286 unlikely(rts_thresh != (u32) -1)) {
1287 if (!rts_thresh || (len > rts_thresh))
1291 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1292 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1293 info->flags |= ATH9K_TXDESC_RTSENA;
1294 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1295 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1296 info->flags |= ATH9K_TXDESC_CTSENA;
1299 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1300 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1301 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1302 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1304 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1305 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1306 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1308 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1310 info->rates[i].Rate = rix | 0x80;
1311 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1312 ah->txchainmask, info->rates[i].Rate);
1313 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1314 is_40, is_sgi, is_sp);
1315 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1316 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1317 if (rix >= 8 && fi->dyn_smps) {
1318 info->rates[i].RateFlags |=
1319 ATH9K_RATESERIES_RTS_CTS;
1320 info->flags |= ATH9K_TXDESC_CTSENA;
1323 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1329 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1330 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1331 !(rate->flags & IEEE80211_RATE_ERP_G))
1332 phy = WLAN_RC_PHY_CCK;
1334 phy = WLAN_RC_PHY_OFDM;
1336 info->rates[i].Rate = rate->hw_value;
1337 if (rate->hw_value_short) {
1338 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1339 info->rates[i].Rate |= rate->hw_value_short;
1344 if (bf->bf_state.bfs_paprd)
1345 info->rates[i].ChSel = ah->txchainmask;
1347 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1348 ah->txchainmask, info->rates[i].Rate);
1350 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1351 phy, rate->bitrate * 100, len, rix, is_sp);
1353 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1354 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1358 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1359 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1360 info->flags &= ~ATH9K_TXDESC_RTSENA;
1362 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1363 if (info->flags & ATH9K_TXDESC_RTSENA)
1364 info->flags &= ~ATH9K_TXDESC_CTSENA;
1367 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1369 struct ieee80211_hdr *hdr;
1370 enum ath9k_pkt_type htype;
1373 hdr = (struct ieee80211_hdr *)skb->data;
1374 fc = hdr->frame_control;
1376 if (ieee80211_is_beacon(fc))
1377 htype = ATH9K_PKT_TYPE_BEACON;
1378 else if (ieee80211_is_probe_resp(fc))
1379 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1380 else if (ieee80211_is_atim(fc))
1381 htype = ATH9K_PKT_TYPE_ATIM;
1382 else if (ieee80211_is_pspoll(fc))
1383 htype = ATH9K_PKT_TYPE_PSPOLL;
1385 htype = ATH9K_PKT_TYPE_NORMAL;
1390 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1391 struct ath_txq *txq, int len)
1393 struct ath_hw *ah = sc->sc_ah;
1394 struct ath_buf *bf_first = NULL;
1395 struct ath_tx_info info;
1396 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1399 memset(&info, 0, sizeof(info));
1400 info.is_first = true;
1401 info.is_last = true;
1402 info.qcu = txq->axq_qnum;
1405 struct sk_buff *skb = bf->bf_mpdu;
1406 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1407 struct ath_frame_info *fi = get_frame_info(skb);
1408 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1410 info.type = get_hw_packet_type(skb);
1412 info.link = bf->bf_next->bf_daddr;
1414 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1419 if (!sc->tx99_state)
1420 info.flags = ATH9K_TXDESC_INTREQ;
1421 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1422 txq == sc->tx.uapsdq)
1423 info.flags |= ATH9K_TXDESC_CLRDMASK;
1425 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1426 info.flags |= ATH9K_TXDESC_NOACK;
1427 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1428 info.flags |= ATH9K_TXDESC_LDPC;
1430 if (bf->bf_state.bfs_paprd)
1431 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1432 ATH9K_TXDESC_PAPRD_S;
1435 * mac80211 doesn't handle RTS threshold for HT because
1436 * the decision has to be taken based on AMPDU length
1437 * and aggregation is done entirely inside ath9k.
1438 * Set the RTS/CTS flag for the first subframe based
1441 if (aggr && (bf == bf_first) &&
1442 unlikely(rts_thresh != (u32) -1)) {
1444 * "len" is the size of the entire AMPDU.
1446 if (!rts_thresh || (len > rts_thresh))
1453 ath_buf_set_rate(sc, bf, &info, len, rts);
1456 info.buf_addr[0] = bf->bf_buf_addr;
1457 info.buf_len[0] = skb->len;
1458 info.pkt_len = fi->framelen;
1459 info.keyix = fi->keyix;
1460 info.keytype = fi->keytype;
1464 info.aggr = AGGR_BUF_FIRST;
1465 else if (bf == bf_first->bf_lastbf)
1466 info.aggr = AGGR_BUF_LAST;
1468 info.aggr = AGGR_BUF_MIDDLE;
1470 info.ndelim = bf->bf_state.ndelim;
1471 info.aggr_len = len;
1474 if (bf == bf_first->bf_lastbf)
1477 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1483 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1484 struct ath_atx_tid *tid, struct list_head *bf_q,
1485 struct ath_buf *bf_first)
1487 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1491 struct ieee80211_tx_info *tx_info;
1494 list_add_tail(&bf->list, bf_q);
1496 bf_prev->bf_next = bf;
1502 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1506 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1507 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1508 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1512 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1516 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1517 struct ath_atx_tid *tid)
1520 struct ieee80211_tx_info *tx_info;
1521 struct list_head bf_q;
1525 if (!ath_tid_has_buffered(tid))
1528 INIT_LIST_HEAD(&bf_q);
1530 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1534 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1535 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1536 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1537 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1538 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1542 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1544 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1546 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1548 if (list_empty(&bf_q))
1551 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1552 tid->clear_ps_filter = false;
1553 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1556 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1557 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1561 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1564 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1565 struct ath_atx_tid *txtid;
1566 struct ath_txq *txq;
1567 struct ath_node *an;
1570 ath_dbg(common, XMIT, "%s called\n", __func__);
1572 an = (struct ath_node *)sta->drv_priv;
1573 txtid = ATH_AN_2_TID(an, tid);
1576 ath_txq_lock(sc, txq);
1578 /* update ampdu factor/density, they may have changed. This may happen
1579 * in HT IBSS when a beacon with HT-info is received after the station
1580 * has already been added.
1582 if (sta->ht_cap.ht_supported) {
1583 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1584 sta->ht_cap.ampdu_factor)) - 1;
1585 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1586 an->mpdudensity = density;
1589 txtid->active = true;
1590 *ssn = txtid->seq_start = txtid->seq_next;
1591 txtid->bar_index = -1;
1593 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1594 txtid->baw_head = txtid->baw_tail = 0;
1596 ath_txq_unlock_complete(sc, txq);
1601 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1604 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1605 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1606 struct ath_txq *txq = txtid->txq;
1608 ath_dbg(common, XMIT, "%s called\n", __func__);
1610 ath_txq_lock(sc, txq);
1611 txtid->active = false;
1612 ath_tx_flush_tid(sc, txtid);
1613 ath_txq_unlock_complete(sc, txq);
1616 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1617 struct ath_node *an)
1619 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1620 struct ath_atx_tid *tid;
1621 struct ath_txq *txq;
1624 ath_dbg(common, XMIT, "%s called\n", __func__);
1626 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1627 tid = ath_node_to_tid(an, tidno);
1630 ath_txq_lock(sc, txq);
1632 if (list_empty(&tid->list)) {
1633 ath_txq_unlock(sc, txq);
1637 if (!skb_queue_empty(&tid->retry_q))
1638 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1640 list_del_init(&tid->list);
1642 ath_txq_unlock(sc, txq);
1646 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1648 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1649 struct ath_atx_tid *tid;
1650 struct ath_txq *txq;
1653 ath_dbg(common, XMIT, "%s called\n", __func__);
1655 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1656 tid = ath_node_to_tid(an, tidno);
1659 ath_txq_lock(sc, txq);
1660 tid->clear_ps_filter = true;
1661 if (ath_tid_has_buffered(tid)) {
1662 ath_tx_queue_tid(sc, tid);
1663 ath_txq_schedule(sc, txq);
1665 ath_txq_unlock_complete(sc, txq);
1669 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1670 struct ieee80211_sta *sta,
1671 u16 tids, int nframes,
1672 enum ieee80211_frame_release_type reason,
1675 struct ath_softc *sc = hw->priv;
1676 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1677 struct ath_txq *txq = sc->tx.uapsdq;
1678 struct ieee80211_tx_info *info;
1679 struct list_head bf_q;
1680 struct ath_buf *bf_tail = NULL, *bf;
1684 INIT_LIST_HEAD(&bf_q);
1685 for (i = 0; tids && nframes; i++, tids >>= 1) {
1686 struct ath_atx_tid *tid;
1691 tid = ATH_AN_2_TID(an, i);
1693 ath_txq_lock(sc, tid->txq);
1694 while (nframes > 0) {
1695 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid);
1699 list_add_tail(&bf->list, &bf_q);
1700 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1701 if (bf_isampdu(bf)) {
1702 ath_tx_addto_baw(sc, tid, bf);
1703 bf->bf_state.bf_type &= ~BUF_AGGR;
1706 bf_tail->bf_next = bf;
1711 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1713 if (an->sta && skb_queue_empty(&tid->retry_q))
1714 ieee80211_sta_set_buffered(an->sta, i, false);
1716 ath_txq_unlock_complete(sc, tid->txq);
1719 if (list_empty(&bf_q))
1722 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1723 info->flags |= IEEE80211_TX_STATUS_EOSP;
1725 bf = list_first_entry(&bf_q, struct ath_buf, list);
1726 ath_txq_lock(sc, txq);
1727 ath_tx_fill_desc(sc, bf, txq, 0);
1728 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1729 ath_txq_unlock(sc, txq);
1732 /********************/
1733 /* Queue Management */
1734 /********************/
1736 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1738 struct ath_hw *ah = sc->sc_ah;
1739 struct ath9k_tx_queue_info qi;
1740 static const int subtype_txq_to_hwq[] = {
1741 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1742 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1743 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1744 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1748 memset(&qi, 0, sizeof(qi));
1749 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1750 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1751 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1752 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1753 qi.tqi_physCompBuf = 0;
1756 * Enable interrupts only for EOL and DESC conditions.
1757 * We mark tx descriptors to receive a DESC interrupt
1758 * when a tx queue gets deep; otherwise waiting for the
1759 * EOL to reap descriptors. Note that this is done to
1760 * reduce interrupt load and this only defers reaping
1761 * descriptors, never transmitting frames. Aside from
1762 * reducing interrupts this also permits more concurrency.
1763 * The only potential downside is if the tx queue backs
1764 * up in which case the top half of the kernel may backup
1765 * due to a lack of tx descriptors.
1767 * The UAPSD queue is an exception, since we take a desc-
1768 * based intr on the EOSP frames.
1770 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1771 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1773 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1774 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1776 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1777 TXQ_FLAG_TXDESCINT_ENABLE;
1779 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1780 if (axq_qnum == -1) {
1782 * NB: don't print a message, this happens
1783 * normally on parts with too few tx queues
1787 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1788 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1790 txq->axq_qnum = axq_qnum;
1791 txq->mac80211_qnum = -1;
1792 txq->axq_link = NULL;
1793 __skb_queue_head_init(&txq->complete_q);
1794 INIT_LIST_HEAD(&txq->axq_q);
1795 spin_lock_init(&txq->axq_lock);
1797 txq->axq_ampdu_depth = 0;
1798 txq->axq_tx_inprogress = false;
1799 sc->tx.txqsetup |= 1<<axq_qnum;
1801 txq->txq_headidx = txq->txq_tailidx = 0;
1802 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1803 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1805 return &sc->tx.txq[axq_qnum];
1808 int ath_txq_update(struct ath_softc *sc, int qnum,
1809 struct ath9k_tx_queue_info *qinfo)
1811 struct ath_hw *ah = sc->sc_ah;
1813 struct ath9k_tx_queue_info qi;
1815 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1817 ath9k_hw_get_txq_props(ah, qnum, &qi);
1818 qi.tqi_aifs = qinfo->tqi_aifs;
1819 qi.tqi_cwmin = qinfo->tqi_cwmin;
1820 qi.tqi_cwmax = qinfo->tqi_cwmax;
1821 qi.tqi_burstTime = qinfo->tqi_burstTime;
1822 qi.tqi_readyTime = qinfo->tqi_readyTime;
1824 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1825 ath_err(ath9k_hw_common(sc->sc_ah),
1826 "Unable to update hardware queue %u!\n", qnum);
1829 ath9k_hw_resettxqueue(ah, qnum);
1835 int ath_cabq_update(struct ath_softc *sc)
1837 struct ath9k_tx_queue_info qi;
1838 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1839 int qnum = sc->beacon.cabq->axq_qnum;
1841 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1843 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1844 ATH_CABQ_READY_TIME) / 100;
1845 ath_txq_update(sc, qnum, &qi);
1850 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1851 struct list_head *list)
1853 struct ath_buf *bf, *lastbf;
1854 struct list_head bf_head;
1855 struct ath_tx_status ts;
1857 memset(&ts, 0, sizeof(ts));
1858 ts.ts_status = ATH9K_TX_FLUSH;
1859 INIT_LIST_HEAD(&bf_head);
1861 while (!list_empty(list)) {
1862 bf = list_first_entry(list, struct ath_buf, list);
1864 if (bf->bf_state.stale) {
1865 list_del(&bf->list);
1867 ath_tx_return_buffer(sc, bf);
1871 lastbf = bf->bf_lastbf;
1872 list_cut_position(&bf_head, list, &lastbf->list);
1873 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1878 * Drain a given TX queue (could be Beacon or Data)
1880 * This assumes output has been stopped and
1881 * we do not need to block ath_tx_tasklet.
1883 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1886 ath_txq_lock(sc, txq);
1888 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1889 int idx = txq->txq_tailidx;
1891 while (!list_empty(&txq->txq_fifo[idx])) {
1892 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1894 INCR(idx, ATH_TXFIFO_DEPTH);
1896 txq->txq_tailidx = idx;
1899 txq->axq_link = NULL;
1900 txq->axq_tx_inprogress = false;
1901 ath_drain_txq_list(sc, txq, &txq->axq_q);
1903 ath_txq_unlock_complete(sc, txq);
1907 bool ath_drain_all_txq(struct ath_softc *sc)
1909 struct ath_hw *ah = sc->sc_ah;
1910 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1911 struct ath_txq *txq;
1915 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1918 ath9k_hw_abort_tx_dma(ah);
1920 /* Check if any queue remains active */
1921 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1922 if (!ATH_TXQ_SETUP(sc, i))
1925 if (!sc->tx.txq[i].axq_depth)
1928 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1933 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1934 ath_dbg(common, RESET,
1935 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1938 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1939 if (!ATH_TXQ_SETUP(sc, i))
1942 txq = &sc->tx.txq[i];
1943 ath_draintxq(sc, txq);
1949 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1951 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1952 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1955 /* For each acq entry, for each tid, try to schedule packets
1956 * for transmit until ampdu_depth has reached min Q depth.
1958 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1960 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1961 struct ath_atx_tid *tid;
1962 struct list_head *tid_list;
1963 struct ath_acq *acq;
1964 bool active = AIRTIME_ACTIVE(sc->airtime_flags);
1966 if (txq->mac80211_qnum < 0)
1969 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1972 spin_lock_bh(&sc->chan_lock);
1974 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
1976 if (sc->cur_chan->stopped)
1980 tid_list = &acq->acq_new;
1981 if (list_empty(tid_list)) {
1982 tid_list = &acq->acq_old;
1983 if (list_empty(tid_list))
1986 tid = list_first_entry(tid_list, struct ath_atx_tid, list);
1988 if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) {
1989 spin_lock_bh(&acq->lock);
1990 tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM;
1991 list_move_tail(&tid->list, &acq->acq_old);
1992 spin_unlock_bh(&acq->lock);
1996 if (!ath_tid_has_buffered(tid)) {
1997 spin_lock_bh(&acq->lock);
1998 if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old))
1999 list_move_tail(&tid->list, &acq->acq_old);
2001 list_del_init(&tid->list);
2003 spin_unlock_bh(&acq->lock);
2009 * If we succeed in scheduling something, immediately restart to make
2010 * sure we keep the HW busy.
2012 if(ath_tx_sched_aggr(sc, txq, tid)) {
2014 spin_lock_bh(&acq->lock);
2015 list_move_tail(&tid->list, &acq->acq_old);
2016 spin_unlock_bh(&acq->lock);
2023 spin_unlock_bh(&sc->chan_lock);
2026 void ath_txq_schedule_all(struct ath_softc *sc)
2028 struct ath_txq *txq;
2031 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2032 txq = sc->tx.txq_map[i];
2034 spin_lock_bh(&txq->axq_lock);
2035 ath_txq_schedule(sc, txq);
2036 spin_unlock_bh(&txq->axq_lock);
2045 * Insert a chain of ath_buf (descriptors) on a txq and
2046 * assume the descriptors are already chained together by caller.
2048 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2049 struct list_head *head, bool internal)
2051 struct ath_hw *ah = sc->sc_ah;
2052 struct ath_common *common = ath9k_hw_common(ah);
2053 struct ath_buf *bf, *bf_last;
2054 bool puttxbuf = false;
2058 * Insert the frame on the outbound list and
2059 * pass it on to the hardware.
2062 if (list_empty(head))
2065 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2066 bf = list_first_entry(head, struct ath_buf, list);
2067 bf_last = list_entry(head->prev, struct ath_buf, list);
2069 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2070 txq->axq_qnum, txq->axq_depth);
2072 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2073 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2074 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2077 list_splice_tail_init(head, &txq->axq_q);
2079 if (txq->axq_link) {
2080 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2081 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2082 txq->axq_qnum, txq->axq_link,
2083 ito64(bf->bf_daddr), bf->bf_desc);
2087 txq->axq_link = bf_last->bf_desc;
2091 TX_STAT_INC(txq->axq_qnum, puttxbuf);
2092 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2093 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2094 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2097 if (!edma || sc->tx99_state) {
2098 TX_STAT_INC(txq->axq_qnum, txstart);
2099 ath9k_hw_txstart(ah, txq->axq_qnum);
2105 if (bf_is_ampdu_not_probing(bf))
2106 txq->axq_ampdu_depth++;
2108 bf_last = bf->bf_lastbf;
2109 bf = bf_last->bf_next;
2110 bf_last->bf_next = NULL;
2115 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2116 struct ath_atx_tid *tid, struct sk_buff *skb)
2118 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2119 struct ath_frame_info *fi = get_frame_info(skb);
2120 struct list_head bf_head;
2121 struct ath_buf *bf = fi->bf;
2123 INIT_LIST_HEAD(&bf_head);
2124 list_add_tail(&bf->list, &bf_head);
2125 bf->bf_state.bf_type = 0;
2126 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2127 bf->bf_state.bf_type = BUF_AMPDU;
2128 ath_tx_addto_baw(sc, tid, bf);
2133 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2134 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2135 TX_STAT_INC(txq->axq_qnum, queued);
2138 static void setup_frame_info(struct ieee80211_hw *hw,
2139 struct ieee80211_sta *sta,
2140 struct sk_buff *skb,
2143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2144 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2145 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2146 const struct ieee80211_rate *rate;
2147 struct ath_frame_info *fi = get_frame_info(skb);
2148 struct ath_node *an = NULL;
2149 enum ath9k_key_type keytype;
2150 bool short_preamble = false;
2154 * We check if Short Preamble is needed for the CTS rate by
2155 * checking the BSS's global flag.
2156 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2158 if (tx_info->control.vif &&
2159 tx_info->control.vif->bss_conf.use_short_preamble)
2160 short_preamble = true;
2162 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2163 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2166 an = (struct ath_node *) sta->drv_priv;
2168 if (tx_info->control.vif) {
2169 struct ieee80211_vif *vif = tx_info->control.vif;
2171 txpower = 2 * vif->bss_conf.txpower;
2173 struct ath_softc *sc = hw->priv;
2175 txpower = sc->cur_chan->cur_txpower;
2178 memset(fi, 0, sizeof(*fi));
2181 fi->keyix = hw_key->hw_key_idx;
2182 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2183 fi->keyix = an->ps_key;
2185 fi->keyix = ATH9K_TXKEYIX_INVALID;
2186 fi->dyn_smps = sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC;
2187 fi->keytype = keytype;
2188 fi->framelen = framelen;
2189 fi->tx_power = txpower;
2193 fi->rtscts_rate = rate->hw_value;
2195 fi->rtscts_rate |= rate->hw_value_short;
2198 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2200 struct ath_hw *ah = sc->sc_ah;
2201 struct ath9k_channel *curchan = ah->curchan;
2203 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2204 (chainmask == 0x7) && (rate < 0x90))
2206 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2214 * Assign a descriptor (and sequence number if necessary,
2215 * and map buffer for DMA. Frees skb on error
2217 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2218 struct ath_txq *txq,
2219 struct ath_atx_tid *tid,
2220 struct sk_buff *skb)
2222 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2223 struct ath_frame_info *fi = get_frame_info(skb);
2224 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2229 bf = ath_tx_get_buffer(sc);
2231 ath_dbg(common, XMIT, "TX buffers are full\n");
2235 ATH_TXBUF_RESET(bf);
2237 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2238 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2239 seqno = tid->seq_next;
2240 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2243 hdr->seq_ctrl |= cpu_to_le16(fragno);
2245 if (!ieee80211_has_morefrags(hdr->frame_control))
2246 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2248 bf->bf_state.seqno = seqno;
2253 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2254 skb->len, DMA_TO_DEVICE);
2255 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2257 bf->bf_buf_addr = 0;
2258 ath_err(ath9k_hw_common(sc->sc_ah),
2259 "dma_mapping_error() on TX\n");
2260 ath_tx_return_buffer(sc, bf);
2269 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2271 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2272 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2273 struct ieee80211_vif *vif = info->control.vif;
2274 struct ath_vif *avp;
2276 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2282 avp = (struct ath_vif *)vif->drv_priv;
2284 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2285 avp->seq_no += 0x10;
2287 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2288 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2291 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2292 struct ath_tx_control *txctl)
2294 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2295 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2296 struct ieee80211_sta *sta = txctl->sta;
2297 struct ieee80211_vif *vif = info->control.vif;
2298 struct ath_vif *avp;
2299 struct ath_softc *sc = hw->priv;
2300 int frmlen = skb->len + FCS_LEN;
2301 int padpos, padsize;
2303 /* NOTE: sta can be NULL according to net/mac80211.h */
2305 txctl->an = (struct ath_node *)sta->drv_priv;
2306 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2307 avp = (void *)vif->drv_priv;
2308 txctl->an = &avp->mcast_node;
2311 if (info->control.hw_key)
2312 frmlen += info->control.hw_key->icv_len;
2314 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2316 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2317 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2318 !ieee80211_is_data(hdr->frame_control))
2319 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2321 /* Add the padding after the header if this is not already done */
2322 padpos = ieee80211_hdrlen(hdr->frame_control);
2323 padsize = padpos & 3;
2324 if (padsize && skb->len > padpos) {
2325 if (skb_headroom(skb) < padsize)
2328 skb_push(skb, padsize);
2329 memmove(skb->data, skb->data + padsize, padpos);
2332 setup_frame_info(hw, sta, skb, frmlen);
2337 /* Upon failure caller should free skb */
2338 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2339 struct ath_tx_control *txctl)
2341 struct ieee80211_hdr *hdr;
2342 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2343 struct ieee80211_sta *sta = txctl->sta;
2344 struct ieee80211_vif *vif = info->control.vif;
2345 struct ath_frame_info *fi = get_frame_info(skb);
2346 struct ath_vif *avp = NULL;
2347 struct ath_softc *sc = hw->priv;
2348 struct ath_txq *txq = txctl->txq;
2349 struct ath_atx_tid *tid = NULL;
2350 struct ath_node *an = NULL;
2356 avp = (void *)vif->drv_priv;
2358 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2360 ret = ath_tx_prepare(hw, skb, txctl);
2364 hdr = (struct ieee80211_hdr *) skb->data;
2366 * At this point, the vif, hw_key and sta pointers in the tx control
2367 * info are no longer valid (overwritten by the ath_frame_info data.
2370 q = skb_get_queue_mapping(skb);
2373 txq = sc->tx.uapsdq;
2376 an = (struct ath_node *) sta->drv_priv;
2377 tid = ath_get_skb_tid(sc, an, skb);
2380 ath_txq_lock(sc, txq);
2381 if (txq == sc->tx.txq_map[q]) {
2383 ++txq->pending_frames;
2386 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2388 ath_txq_skb_done(sc, txq, skb);
2390 dev_kfree_skb_any(skb);
2392 ieee80211_free_txskb(sc->hw, skb);
2396 bf->bf_state.bfs_paprd = txctl->paprd;
2399 bf->bf_state.bfs_paprd_timestamp = jiffies;
2401 ath_set_rates(vif, sta, bf);
2402 ath_tx_send_normal(sc, txq, tid, skb);
2405 ath_txq_unlock(sc, txq);
2410 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2411 struct sk_buff *skb)
2413 struct ath_softc *sc = hw->priv;
2414 struct ath_tx_control txctl = {
2415 .txq = sc->beacon.cabq
2417 struct ath_tx_info info = {};
2418 struct ieee80211_hdr *hdr;
2419 struct ath_buf *bf_tail = NULL;
2426 sc->cur_chan->beacon.beacon_interval * 1000 *
2427 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2430 struct ath_frame_info *fi = get_frame_info(skb);
2432 if (ath_tx_prepare(hw, skb, &txctl))
2435 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2440 ath_set_rates(vif, NULL, bf);
2441 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2442 duration += info.rates[0].PktDuration;
2444 bf_tail->bf_next = bf;
2446 list_add_tail(&bf->list, &bf_q);
2450 if (duration > max_duration)
2453 skb = ieee80211_get_buffered_bc(hw, vif);
2457 ieee80211_free_txskb(hw, skb);
2459 if (list_empty(&bf_q))
2462 bf = list_first_entry(&bf_q, struct ath_buf, list);
2463 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2465 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) {
2466 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA);
2467 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2468 sizeof(*hdr), DMA_TO_DEVICE);
2471 ath_txq_lock(sc, txctl.txq);
2472 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2473 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2474 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2475 ath_txq_unlock(sc, txctl.txq);
2482 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2483 int tx_flags, struct ath_txq *txq,
2484 struct ieee80211_sta *sta)
2486 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2487 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2488 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2489 int padpos, padsize;
2490 unsigned long flags;
2492 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2494 if (sc->sc_ah->caldata)
2495 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2497 if (!(tx_flags & ATH_TX_ERROR)) {
2498 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2499 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2501 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2504 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2505 padpos = ieee80211_hdrlen(hdr->frame_control);
2506 padsize = padpos & 3;
2507 if (padsize && skb->len>padpos+padsize) {
2509 * Remove MAC header padding before giving the frame back to
2512 memmove(skb->data + padsize, skb->data, padpos);
2513 skb_pull(skb, padsize);
2517 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2518 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2519 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2521 "Going back to sleep after having received TX status (0x%lx)\n",
2522 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2524 PS_WAIT_FOR_PSPOLL_DATA |
2525 PS_WAIT_FOR_TX_ACK));
2527 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2529 ath_txq_skb_done(sc, txq, skb);
2530 tx_info->status.status_driver_data[0] = sta;
2531 __skb_queue_tail(&txq->complete_q, skb);
2534 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2535 struct ath_txq *txq, struct list_head *bf_q,
2536 struct ieee80211_sta *sta,
2537 struct ath_tx_status *ts, int txok)
2539 struct sk_buff *skb = bf->bf_mpdu;
2540 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2541 unsigned long flags;
2545 tx_flags |= ATH_TX_ERROR;
2547 if (ts->ts_status & ATH9K_TXERR_FILT)
2548 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2550 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2551 bf->bf_buf_addr = 0;
2553 goto skip_tx_complete;
2555 if (bf->bf_state.bfs_paprd) {
2556 if (time_after(jiffies,
2557 bf->bf_state.bfs_paprd_timestamp +
2558 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2559 dev_kfree_skb_any(skb);
2561 complete(&sc->paprd_complete);
2563 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2564 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2567 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2568 * accidentally reference it later.
2573 * Return the list of ath_buf of this mpdu to free queue
2575 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2576 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2577 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2580 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2581 struct ath_tx_status *ts, int nframes, int nbad,
2584 struct sk_buff *skb = bf->bf_mpdu;
2585 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2586 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2587 struct ieee80211_hw *hw = sc->hw;
2588 struct ath_hw *ah = sc->sc_ah;
2592 tx_info->status.ack_signal = ts->ts_rssi;
2594 tx_rateindex = ts->ts_rateindex;
2595 WARN_ON(tx_rateindex >= hw->max_rates);
2597 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2598 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2600 BUG_ON(nbad > nframes);
2602 tx_info->status.ampdu_len = nframes;
2603 tx_info->status.ampdu_ack_len = nframes - nbad;
2605 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2606 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2608 * If an underrun error is seen assume it as an excessive
2609 * retry only if max frame trigger level has been reached
2610 * (2 KB for single stream, and 4 KB for dual stream).
2611 * Adjust the long retry as if the frame was tried
2612 * hw->max_rate_tries times to affect how rate control updates
2613 * PER for the failed rate.
2614 * In case of congestion on the bus penalizing this type of
2615 * underruns should help hardware actually transmit new frames
2616 * successfully by eventually preferring slower rates.
2617 * This itself should also alleviate congestion on the bus.
2619 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2620 ATH9K_TX_DELIM_UNDERRUN)) &&
2621 ieee80211_is_data(hdr->frame_control) &&
2622 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2623 tx_info->status.rates[tx_rateindex].count =
2627 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2628 tx_info->status.rates[i].count = 0;
2629 tx_info->status.rates[i].idx = -1;
2632 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2635 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2637 struct ath_hw *ah = sc->sc_ah;
2638 struct ath_common *common = ath9k_hw_common(ah);
2639 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2640 struct list_head bf_head;
2641 struct ath_desc *ds;
2642 struct ath_tx_status ts;
2645 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2646 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2649 ath_txq_lock(sc, txq);
2651 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2654 if (list_empty(&txq->axq_q)) {
2655 txq->axq_link = NULL;
2656 ath_txq_schedule(sc, txq);
2659 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2662 * There is a race condition that a BH gets scheduled
2663 * after sw writes TxE and before hw re-load the last
2664 * descriptor to get the newly chained one.
2665 * Software must keep the last DONE descriptor as a
2666 * holding descriptor - software does so by marking
2667 * it with the STALE flag.
2670 if (bf->bf_state.stale) {
2672 if (list_is_last(&bf_held->list, &txq->axq_q))
2675 bf = list_entry(bf_held->list.next, struct ath_buf,
2679 lastbf = bf->bf_lastbf;
2680 ds = lastbf->bf_desc;
2682 memset(&ts, 0, sizeof(ts));
2683 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2684 if (status == -EINPROGRESS)
2687 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2690 * Remove ath_buf's of the same transmit unit from txq,
2691 * however leave the last descriptor back as the holding
2692 * descriptor for hw.
2694 lastbf->bf_state.stale = true;
2695 INIT_LIST_HEAD(&bf_head);
2696 if (!list_is_singular(&lastbf->list))
2697 list_cut_position(&bf_head,
2698 &txq->axq_q, lastbf->list.prev);
2701 list_del(&bf_held->list);
2702 ath_tx_return_buffer(sc, bf_held);
2705 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2707 ath_txq_unlock_complete(sc, txq);
2710 void ath_tx_tasklet(struct ath_softc *sc)
2712 struct ath_hw *ah = sc->sc_ah;
2713 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2717 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2718 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2719 ath_tx_processq(sc, &sc->tx.txq[i]);
2724 void ath_tx_edma_tasklet(struct ath_softc *sc)
2726 struct ath_tx_status ts;
2727 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2728 struct ath_hw *ah = sc->sc_ah;
2729 struct ath_txq *txq;
2730 struct ath_buf *bf, *lastbf;
2731 struct list_head bf_head;
2732 struct list_head *fifo_list;
2737 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2740 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2741 if (status == -EINPROGRESS)
2743 if (status == -EIO) {
2744 ath_dbg(common, XMIT, "Error processing tx status\n");
2748 /* Process beacon completions separately */
2749 if (ts.qid == sc->beacon.beaconq) {
2750 sc->beacon.tx_processed = true;
2751 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2753 if (ath9k_is_chanctx_enabled()) {
2754 ath_chanctx_event(sc, NULL,
2755 ATH_CHANCTX_EVENT_BEACON_SENT);
2758 ath9k_csa_update(sc);
2762 txq = &sc->tx.txq[ts.qid];
2764 ath_txq_lock(sc, txq);
2766 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2768 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2769 if (list_empty(fifo_list)) {
2770 ath_txq_unlock(sc, txq);
2774 bf = list_first_entry(fifo_list, struct ath_buf, list);
2775 if (bf->bf_state.stale) {
2776 list_del(&bf->list);
2777 ath_tx_return_buffer(sc, bf);
2778 bf = list_first_entry(fifo_list, struct ath_buf, list);
2781 lastbf = bf->bf_lastbf;
2783 INIT_LIST_HEAD(&bf_head);
2784 if (list_is_last(&lastbf->list, fifo_list)) {
2785 list_splice_tail_init(fifo_list, &bf_head);
2786 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2788 if (!list_empty(&txq->axq_q)) {
2789 struct list_head bf_q;
2791 INIT_LIST_HEAD(&bf_q);
2792 txq->axq_link = NULL;
2793 list_splice_tail_init(&txq->axq_q, &bf_q);
2794 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2797 lastbf->bf_state.stale = true;
2799 list_cut_position(&bf_head, fifo_list,
2803 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2804 ath_txq_unlock_complete(sc, txq);
2813 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2815 struct ath_descdma *dd = &sc->txsdma;
2816 u8 txs_len = sc->sc_ah->caps.txs_len;
2818 dd->dd_desc_len = size * txs_len;
2819 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2820 &dd->dd_desc_paddr, GFP_KERNEL);
2827 static int ath_tx_edma_init(struct ath_softc *sc)
2831 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2833 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2834 sc->txsdma.dd_desc_paddr,
2835 ATH_TXSTATUS_RING_SIZE);
2840 int ath_tx_init(struct ath_softc *sc, int nbufs)
2842 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2845 spin_lock_init(&sc->tx.txbuflock);
2847 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2851 "Failed to allocate tx descriptors: %d\n", error);
2855 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2856 "beacon", ATH_BCBUF, 1, 1);
2859 "Failed to allocate beacon descriptors: %d\n", error);
2863 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2864 error = ath_tx_edma_init(sc);
2869 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2871 struct ath_atx_tid *tid;
2874 for (acno = 0; acno < IEEE80211_NUM_ACS; acno++)
2875 an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM;
2877 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2878 tid = ath_node_to_tid(an, tidno);
2881 tid->seq_start = tid->seq_next = 0;
2882 tid->baw_size = WME_MAX_BA;
2883 tid->baw_head = tid->baw_tail = 0;
2884 tid->active = false;
2885 tid->clear_ps_filter = true;
2886 tid->has_queued = false;
2887 __skb_queue_head_init(&tid->retry_q);
2888 INIT_LIST_HEAD(&tid->list);
2889 acno = TID_TO_WME_AC(tidno);
2890 tid->txq = sc->tx.txq_map[acno];
2893 break; /* just one multicast ath_atx_tid */
2897 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2899 struct ath_atx_tid *tid;
2900 struct ath_txq *txq;
2905 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2906 tid = ath_node_to_tid(an, tidno);
2909 ath_txq_lock(sc, txq);
2911 if (!list_empty(&tid->list))
2912 list_del_init(&tid->list);
2914 ath_tid_drain(sc, txq, tid);
2915 tid->active = false;
2917 ath_txq_unlock(sc, txq);
2920 break; /* just one multicast ath_atx_tid */
2926 #ifdef CONFIG_ATH9K_TX99
2928 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2929 struct ath_tx_control *txctl)
2931 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2932 struct ath_frame_info *fi = get_frame_info(skb);
2933 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2935 int padpos, padsize;
2937 padpos = ieee80211_hdrlen(hdr->frame_control);
2938 padsize = padpos & 3;
2940 if (padsize && skb->len > padpos) {
2941 if (skb_headroom(skb) < padsize) {
2942 ath_dbg(common, XMIT,
2943 "tx99 padding failed\n");
2947 skb_push(skb, padsize);
2948 memmove(skb->data, skb->data + padsize, padpos);
2951 fi->keyix = ATH9K_TXKEYIX_INVALID;
2952 fi->framelen = skb->len + FCS_LEN;
2953 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2955 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2957 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2961 ath_set_rates(sc->tx99_vif, NULL, bf);
2963 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2964 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2966 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2971 #endif /* CONFIG_ATH9K_TX99 */