drivers/net/wireless/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "/*(DEBLOBBED)*/"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "/*(DEBLOBBED)*/"
  50 #define BRCMF_PCIE_4350_FW_NAME                 "/*(DEBLOBBED)*/"
  51 #define BRCMF_PCIE_4350_NVRAM_NAME              "/*(DEBLOBBED)*/"
  52 #define BRCMF_PCIE_4356_FW_NAME                 "/*(DEBLOBBED)*/"
  53 #define BRCMF_PCIE_4356_NVRAM_NAME              "/*(DEBLOBBED)*/"
  54 #define BRCMF_PCIE_43570_FW_NAME                "/*(DEBLOBBED)*/"
  55 #define BRCMF_PCIE_43570_NVRAM_NAME             "/*(DEBLOBBED)*/"
  56 #define BRCMF_PCIE_4358_FW_NAME                 "/*(DEBLOBBED)*/"
  57 #define BRCMF_PCIE_4358_NVRAM_NAME              "/*(DEBLOBBED)*/"
  58 #define BRCMF_PCIE_4365_FW_NAME                 "/*(DEBLOBBED)*/"
  59 #define BRCMF_PCIE_4365_NVRAM_NAME              "/*(DEBLOBBED)*/"
  60 #define BRCMF_PCIE_4366_FW_NAME                 "/*(DEBLOBBED)*/"
  61 #define BRCMF_PCIE_4366_NVRAM_NAME              "/*(DEBLOBBED)*/"
  62 #define BRCMF_PCIE_4371_FW_NAME                 "/*(DEBLOBBED)*/"
  63 #define BRCMF_PCIE_4371_NVRAM_NAME              "/*(DEBLOBBED)*/"
  64
  65 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  66
  67 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  68 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  69
  70 /* backplane addres space accessed by BAR0 */
  71 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  72 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  73 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  74
  75 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  76 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  77
  78 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  79 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  80
  81 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  82 #define BRCMF_PCIE_REG_INTMASK                  0x94
  83 #define BRCMF_PCIE_REG_SBMBX                    0x98
  84
  85 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
  86
  87 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  88 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  89 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  90 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  91 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  92 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  93
  94 #define BRCMF_PCIE_GENREV1                      1
  95 #define BRCMF_PCIE_GENREV2                      2
  96
  97 #define BRCMF_PCIE2_INTA                        0x01
  98 #define BRCMF_PCIE2_INTB                        0x02
  99
 100 #define BRCMF_PCIE_INT_0                        0x01
 101 #define BRCMF_PCIE_INT_1                        0x02
 102 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 103                                                  BRCMF_PCIE_INT_1)
 104
 105 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 106 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 107 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 108 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 109 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 110 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 111 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 112 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 113 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 114 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 115
 116 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 117                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 118                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 119                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 120                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 121                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 122                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 123                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 124
 125 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 126 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 127 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 128 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 129 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 130
 131 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 132 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 133
 134 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 135 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 136 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 137 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 138 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 139 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 140 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 141 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 142 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 143 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 144 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 145
 146 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 147 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 148 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 149 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 150
 151 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 152 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 153 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 154 #define BRCMF_RING_MEM_SZ                       16
 155 #define BRCMF_RING_STATE_SZ                     8
 156
 157 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 158 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 159 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 160 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 161 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 162 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 163 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 164 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 165 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 166 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 167
 168 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 169
 170 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 171 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 172 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 173
 174 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 175 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 176
 177 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 178 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 179 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 180
 181 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 182 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 183 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 184 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 185
 186 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 187
 188 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 189 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 190 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 191 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 192 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 193 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 194 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 195 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 196 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 197 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 198 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 199 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 200 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 201
 202
 203 /*(DEBLOBBED)*/
 204
 205
 206 struct brcmf_pcie_console {
 207         u32 base_addr;
 208         u32 buf_addr;
 209         u32 bufsize;
 210         u32 read_idx;
 211         u8 log_str[256];
 212         u8 log_idx;
 213 };
 214
 215 struct brcmf_pcie_shared_info {
 216         u32 tcm_base_address;
 217         u32 flags;
 218         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 219         struct brcmf_pcie_ringbuf *flowrings;
 220         u16 max_rxbufpost;
 221         u32 nrof_flowrings;
 222         u32 rx_dataoffset;
 223         u32 htod_mb_data_addr;
 224         u32 dtoh_mb_data_addr;
 225         u32 ring_info_addr;
 226         struct brcmf_pcie_console console;
 227         void *scratch;
 228         dma_addr_t scratch_dmahandle;
 229         void *ringupd;
 230         dma_addr_t ringupd_dmahandle;
 231 };
 232
 233 struct brcmf_pcie_core_info {
 234         u32 base;
 235         u32 wrapbase;
 236 };
 237
 238 struct brcmf_pciedev_info {
 239         enum brcmf_pcie_state state;
 240         bool in_irq;
 241         bool irq_requested;
 242         struct pci_dev *pdev;
 243         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 244         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 245         void __iomem *regs;
 246         void __iomem *tcm;
 247         u32 tcm_size;
 248         u32 ram_base;
 249         u32 ram_size;
 250         struct brcmf_chip *ci;
 251         u32 coreid;
 252         u32 generic_corerev;
 253         struct brcmf_pcie_shared_info shared;
 254         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 255         wait_queue_head_t mbdata_resp_wait;
 256         bool mbdata_completed;
 257         bool irq_allocated;
 258         bool wowl_enabled;
 259         u8 dma_idx_sz;
 260         void *idxbuf;
 261         u32 idxbuf_sz;
 262         dma_addr_t idxbuf_dmahandle;
 263         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 264         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 265                           u16 value);
 266 };
 267
 268 struct brcmf_pcie_ringbuf {
 269         struct brcmf_commonring commonring;
 270         dma_addr_t dma_handle;
 271         u32 w_idx_addr;
 272         u32 r_idx_addr;
 273         struct brcmf_pciedev_info *devinfo;
 274         u8 id;
 275 };
 276
 277
 278 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 279         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 280         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 281         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 282         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 283         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 284 };
 285
 286 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 287         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 288         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 289         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 290         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 291         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 292 };
 293
 294
 295 static u32
 296 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 297 {
 298         void __iomem *address = devinfo->regs + reg_offset;
 299
 300         return (ioread32(address));
 301 }
 302
 303
 304 static void
 305 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 306                        u32 value)
 307 {
 308         void __iomem *address = devinfo->regs + reg_offset;
 309
 310         iowrite32(value, address);
 311 }
 312
 313
 314 static u8
 315 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 316 {
 317         void __iomem *address = devinfo->tcm + mem_offset;
 318
 319         return (ioread8(address));
 320 }
 321
 322
 323 static u16
 324 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 325 {
 326         void __iomem *address = devinfo->tcm + mem_offset;
 327
 328         return (ioread16(address));
 329 }
 330
 331
 332 static void
 333 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 334                        u16 value)
 335 {
 336         void __iomem *address = devinfo->tcm + mem_offset;
 337
 338         iowrite16(value, address);
 339 }
 340
 341
 342 static u16
 343 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 344 {
 345         u16 *address = devinfo->idxbuf + mem_offset;
 346
 347         return (*(address));
 348 }
 349
 350
 351 static void
 352 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 353                      u16 value)
 354 {
 355         u16 *address = devinfo->idxbuf + mem_offset;
 356
 357         *(address) = value;
 358 }
 359
 360
 361 static u32
 362 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 363 {
 364         void __iomem *address = devinfo->tcm + mem_offset;
 365
 366         return (ioread32(address));
 367 }
 368
 369
 370 static void
 371 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 372                        u32 value)
 373 {
 374         void __iomem *address = devinfo->tcm + mem_offset;
 375
 376         iowrite32(value, address);
 377 }
 378
 379
 380 static u32
 381 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 382 {
 383         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 384
 385         return (ioread32(addr));
 386 }
 387
 388
 389 static void
 390 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 391                        u32 value)
 392 {
 393         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 394
 395         iowrite32(value, addr);
 396 }
 397
 398
 399 static void
 400 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 401                           void *srcaddr, u32 len)
 402 {
 403         void __iomem *address = devinfo->tcm + mem_offset;
 404         __le32 *src32;
 405         __le16 *src16;
 406         u8 *src8;
 407
 408         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 409                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 410                         src8 = (u8 *)srcaddr;
 411                         while (len) {
 412                                 iowrite8(*src8, address);
 413                                 address++;
 414                                 src8++;
 415                                 len--;
 416                         }
 417                 } else {
 418                         len = len / 2;
 419                         src16 = (__le16 *)srcaddr;
 420                         while (len) {
 421                                 iowrite16(le16_to_cpu(*src16), address);
 422                                 address += 2;
 423                                 src16++;
 424                                 len--;
 425                         }
 426                 }
 427         } else {
 428                 len = len / 4;
 429                 src32 = (__le32 *)srcaddr;
 430                 while (len) {
 431                         iowrite32(le32_to_cpu(*src32), address);
 432                         address += 4;
 433                         src32++;
 434                         len--;
 435                 }
 436         }
 437 }
 438
 439
 440 static void
 441 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 442                           void *dstaddr, u32 len)
 443 {
 444         void __iomem *address = devinfo->tcm + mem_offset;
 445         __le32 *dst32;
 446         __le16 *dst16;
 447         u8 *dst8;
 448
 449         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 450                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 451                         dst8 = (u8 *)dstaddr;
 452                         while (len) {
 453                                 *dst8 = ioread8(address);
 454                                 address++;
 455                                 dst8++;
 456                                 len--;
 457                         }
 458                 } else {
 459                         len = len / 2;
 460                         dst16 = (__le16 *)dstaddr;
 461                         while (len) {
 462                                 *dst16 = cpu_to_le16(ioread16(address));
 463                                 address += 2;
 464                                 dst16++;
 465                                 len--;
 466                         }
 467                 }
 468         } else {
 469                 len = len / 4;
 470                 dst32 = (__le32 *)dstaddr;
 471                 while (len) {
 472                         *dst32 = cpu_to_le32(ioread32(address));
 473                         address += 4;
 474                         dst32++;
 475                         len--;
 476                 }
 477         }
 478 }
 479
 480
 481 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 482                 CHIPCREGOFFS(reg), value)
 483
 484
 485 static void
 486 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 487 {
 488         const struct pci_dev *pdev = devinfo->pdev;
 489         struct brcmf_core *core;
 490         u32 bar0_win;
 491
 492         core = brcmf_chip_get_core(devinfo->ci, coreid);
 493         if (core) {
 494                 bar0_win = core->base;
 495                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 496                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 497                                           &bar0_win) == 0) {
 498                         if (bar0_win != core->base) {
 499                                 bar0_win = core->base;
 500                                 pci_write_config_dword(pdev,
 501                                                        BRCMF_PCIE_BAR0_WINDOW,
 502                                                        bar0_win);
 503                         }
 504                 }
 505         } else {
 506                 brcmf_err("Unsupported core selected %x\n", coreid);
 507         }
 508 }
 509
 510
 511 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 512 {
 513         struct brcmf_core *core;
 514         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 515                              BRCMF_PCIE_CFGREG_PM_CSR,
 516                              BRCMF_PCIE_CFGREG_MSI_CAP,
 517                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 518                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 519                              BRCMF_PCIE_CFGREG_MSI_DATA,
 520                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 521                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 522                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 523                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 524                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 525         u32 i;
 526         u32 val;
 527         u32 lsc;
 528
 529         if (!devinfo->ci)
 530                 return;
 531
 532         /* Disable ASPM */
 533         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 534         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 535                               &lsc);
 536         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 537         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 538                                val);
 539
 540         /* Watchdog reset */
 541         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 542         WRITECC32(devinfo, watchdog, 4);
 543         msleep(100);
 544
 545         /* Restore ASPM */
 546         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 547         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 548                                lsc);
 549
 550         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 551         if (core->rev <= 13) {
 552                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 553                         brcmf_pcie_write_reg32(devinfo,
 554                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 555                                                cfg_offset[i]);
 556                         val = brcmf_pcie_read_reg32(devinfo,
 557                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 558                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 559                                   cfg_offset[i], val);
 560                         brcmf_pcie_write_reg32(devinfo,
 561                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 562                                                val);
 563                 }
 564         }
 565 }
 566
 567
 568 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 569 {
 570         u32 config;
 571
 572         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 573         /* BAR1 window may not be sized properly */
 574         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 575         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 576         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 577         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 578
 579         device_wakeup_enable(&devinfo->pdev->dev);
 580 }
 581
 582
 583 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 584 {
 585         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 586                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 587                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 588                                        5);
 589                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 590                                        0);
 591                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 592                                        7);
 593                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 594                                        0);
 595         }
 596         return 0;
 597 }
 598
 599
 600 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 601                                           u32 resetintr)
 602 {
 603         struct brcmf_core *core;
 604
 605         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 606                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 607                 brcmf_chip_resetcore(core, 0, 0, 0);
 608         }
 609
 610         return !brcmf_chip_set_active(devinfo->ci, resetintr);
 611 }
 612
 613
 614 static int
 615 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 616 {
 617         struct brcmf_pcie_shared_info *shared;
 618         u32 addr;
 619         u32 cur_htod_mb_data;
 620         u32 i;
 621
 622         shared = &devinfo->shared;
 623         addr = shared->htod_mb_data_addr;
 624         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 625
 626         if (cur_htod_mb_data != 0)
 627                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 628                           cur_htod_mb_data);
 629
 630         i = 0;
 631         while (cur_htod_mb_data != 0) {
 632                 msleep(10);
 633                 i++;
 634                 if (i > 100)
 635                         return -EIO;
 636                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 637         }
 638
 639         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 640         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 641         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 642
 643         return 0;
 644 }
 645
 646
 647 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 648 {
 649         struct brcmf_pcie_shared_info *shared;
 650         u32 addr;
 651         u32 dtoh_mb_data;
 652
 653         shared = &devinfo->shared;
 654         addr = shared->dtoh_mb_data_addr;
 655         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 656
 657         if (!dtoh_mb_data)
 658                 return;
 659
 660         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 661
 662         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 663         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 664                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 665                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 666                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 667         }
 668         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 669                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 670         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 671                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 672                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 673                         devinfo->mbdata_completed = true;
 674                         wake_up(&devinfo->mbdata_resp_wait);
 675                 }
 676         }
 677 }
 678
 679
 680 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 681 {
 682         struct brcmf_pcie_shared_info *shared;
 683         struct brcmf_pcie_console *console;
 684         u32 addr;
 685
 686         shared = &devinfo->shared;
 687         console = &shared->console;
 688         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 689         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 690
 691         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 692         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 693         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 694         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 695
 696         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 697                   console->base_addr, console->buf_addr, console->bufsize);
 698 }
 699
 700
 701 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 702 {
 703         struct brcmf_pcie_console *console;
 704         u32 addr;
 705         u8 ch;
 706         u32 newidx;
 707
 708         if (!BRCMF_FWCON_ON())
 709                 return;
 710
 711         console = &devinfo->shared.console;
 712         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 713         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 714         while (newidx != console->read_idx) {
 715                 addr = console->buf_addr + console->read_idx;
 716                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 717                 console->read_idx++;
 718                 if (console->read_idx == console->bufsize)
 719                         console->read_idx = 0;
 720                 if (ch == '\r')
 721                         continue;
 722                 console->log_str[console->log_idx] = ch;
 723                 console->log_idx++;
 724                 if ((ch != '\n') &&
 725                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 726                         ch = '\n';
 727                         console->log_str[console->log_idx] = ch;
 728                         console->log_idx++;
 729                 }
 730                 if (ch == '\n') {
 731                         console->log_str[console->log_idx] = 0;
 732                         pr_debug("CONSOLE: %s", console->log_str);
 733                         console->log_idx = 0;
 734                 }
 735         }
 736 }
 737
 738
 739 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 740 {
 741         u32 reg_value;
 742
 743         brcmf_dbg(PCIE, "RING !\n");
 744         reg_value = brcmf_pcie_read_reg32(devinfo,
 745                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 746         reg_value |= BRCMF_PCIE2_INTB;
 747         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 748                                reg_value);
 749 }
 750
 751
 752 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 753 {
 754         brcmf_dbg(PCIE, "RING !\n");
 755         /* Any arbitrary value will do, lets use 1 */
 756         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 757 }
 758
 759
 760 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 761 {
 762         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 763                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 764                                        0);
 765         else
 766                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 767                                        0);
 768 }
 769
 770
 771 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 772 {
 773         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 774                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 775                                        BRCMF_PCIE_INT_DEF);
 776         else
 777                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 778                                        BRCMF_PCIE_MB_INT_D2H_DB |
 779                                        BRCMF_PCIE_MB_INT_FN0_0 |
 780                                        BRCMF_PCIE_MB_INT_FN0_1);
 781 }
 782
 783
 784 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 785 {
 786         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 787         u32 status;
 788
 789         status = 0;
 790         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 791         if (status) {
 792                 brcmf_pcie_intr_disable(devinfo);
 793                 brcmf_dbg(PCIE, "Enter\n");
 794                 return IRQ_WAKE_THREAD;
 795         }
 796         return IRQ_NONE;
 797 }
 798
 799
 800 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 801 {
 802         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 803
 804         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 805                 brcmf_pcie_intr_disable(devinfo);
 806                 brcmf_dbg(PCIE, "Enter\n");
 807                 return IRQ_WAKE_THREAD;
 808         }
 809         return IRQ_NONE;
 810 }
 811
 812
 813 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 814 {
 815         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 816         const struct pci_dev *pdev = devinfo->pdev;
 817         u32 status;
 818
 819         devinfo->in_irq = true;
 820         status = 0;
 821         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 822         brcmf_dbg(PCIE, "Enter %x\n", status);
 823         if (status) {
 824                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 825                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 826                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 827         }
 828         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 829                 brcmf_pcie_intr_enable(devinfo);
 830         devinfo->in_irq = false;
 831         return IRQ_HANDLED;
 832 }
 833
 834
 835 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 836 {
 837         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 838         u32 status;
 839
 840         devinfo->in_irq = true;
 841         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 842         brcmf_dbg(PCIE, "Enter %x\n", status);
 843         if (status) {
 844                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 845                                        status);
 846                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 847                               BRCMF_PCIE_MB_INT_FN0_1))
 848                         brcmf_pcie_handle_mb_data(devinfo);
 849                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 850                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 851                                 brcmf_proto_msgbuf_rx_trigger(
 852                                                         &devinfo->pdev->dev);
 853                 }
 854         }
 855         brcmf_pcie_bus_console_read(devinfo);
 856         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 857                 brcmf_pcie_intr_enable(devinfo);
 858         devinfo->in_irq = false;
 859         return IRQ_HANDLED;
 860 }
 861
 862
 863 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 864 {
 865         struct pci_dev *pdev;
 866
 867         pdev = devinfo->pdev;
 868
 869         brcmf_pcie_intr_disable(devinfo);
 870
 871         brcmf_dbg(PCIE, "Enter\n");
 872         /* is it a v1 or v2 implementation */
 873         devinfo->irq_requested = false;
 874         pci_enable_msi(pdev);
 875         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 876                 if (request_threaded_irq(pdev->irq,
 877                                          brcmf_pcie_quick_check_isr_v1,
 878                                          brcmf_pcie_isr_thread_v1,
 879                                          IRQF_SHARED, "brcmf_pcie_intr",
 880                                          devinfo)) {
 881                         pci_disable_msi(pdev);
 882                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 883                         return -EIO;
 884                 }
 885         } else {
 886                 if (request_threaded_irq(pdev->irq,
 887                                          brcmf_pcie_quick_check_isr_v2,
 888                                          brcmf_pcie_isr_thread_v2,
 889                                          IRQF_SHARED, "brcmf_pcie_intr",
 890                                          devinfo)) {
 891                         pci_disable_msi(pdev);
 892                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 893                         return -EIO;
 894                 }
 895         }
 896         devinfo->irq_requested = true;
 897         devinfo->irq_allocated = true;
 898         return 0;
 899 }
 900
 901
 902 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 903 {
 904         struct pci_dev *pdev;
 905         u32 status;
 906         u32 count;
 907
 908         if (!devinfo->irq_allocated)
 909                 return;
 910
 911         pdev = devinfo->pdev;
 912
 913         brcmf_pcie_intr_disable(devinfo);
 914         if (!devinfo->irq_requested)
 915                 return;
 916         devinfo->irq_requested = false;
 917         free_irq(pdev->irq, devinfo);
 918         pci_disable_msi(pdev);
 919
 920         msleep(50);
 921         count = 0;
 922         while ((devinfo->in_irq) && (count < 20)) {
 923                 msleep(50);
 924                 count++;
 925         }
 926         if (devinfo->in_irq)
 927                 brcmf_err("Still in IRQ (processing) !!!\n");
 928
 929         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 930                 status = 0;
 931                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 932                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 933         } else {
 934                 status = brcmf_pcie_read_reg32(devinfo,
 935                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 936                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 937                                        status);
 938         }
 939         devinfo->irq_allocated = false;
 940 }
 941
 942
 943 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 944 {
 945         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 946         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 947         struct brcmf_commonring *commonring = &ring->commonring;
 948
 949         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 950                 return -EIO;
 951
 952         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 953                   commonring->w_ptr, ring->id);
 954
 955         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 956
 957         return 0;
 958 }
 959
 960
 961 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 962 {
 963         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 964         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 965         struct brcmf_commonring *commonring = &ring->commonring;
 966
 967         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 968                 return -EIO;
 969
 970         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 971                   commonring->r_ptr, ring->id);
 972
 973         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 974
 975         return 0;
 976 }
 977
 978
 979 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 980 {
 981         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 982         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 983
 984         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 985                 return -EIO;
 986
 987         devinfo->ringbell(devinfo);
 988
 989         return 0;
 990 }
 991
 992
 993 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 994 {
 995         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 996         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 997         struct brcmf_commonring *commonring = &ring->commonring;
 998
 999         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1000                 return -EIO;
1001
1002         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1003
1004         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1005                   commonring->w_ptr, ring->id);
1006
1007         return 0;
1008 }
1009
1010
1011 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1012 {
1013         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1014         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1015         struct brcmf_commonring *commonring = &ring->commonring;
1016
1017         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1018                 return -EIO;
1019
1020         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1021
1022         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1023                   commonring->r_ptr, ring->id);
1024
1025         return 0;
1026 }
1027
1028
1029 static void *
1030 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1031                                      u32 size, u32 tcm_dma_phys_addr,
1032                                      dma_addr_t *dma_handle)
1033 {
1034         void *ring;
1035         u64 address;
1036
1037         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1038                                   GFP_KERNEL);
1039         if (!ring)
1040                 return NULL;
1041
1042         address = (u64)*dma_handle;
1043         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1044                                address & 0xffffffff);
1045         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1046
1047         memset(ring, 0, size);
1048
1049         return (ring);
1050 }
1051
1052
1053 static struct brcmf_pcie_ringbuf *
1054 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1055                               u32 tcm_ring_phys_addr)
1056 {
1057         void *dma_buf;
1058         dma_addr_t dma_handle;
1059         struct brcmf_pcie_ringbuf *ring;
1060         u32 size;
1061         u32 addr;
1062
1063         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1064         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1065                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1066                         &dma_handle);
1067         if (!dma_buf)
1068                 return NULL;
1069
1070         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1071         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1072         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1073         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1074
1075         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1076         if (!ring) {
1077                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1078                                   dma_handle);
1079                 return NULL;
1080         }
1081         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1082                                 brcmf_ring_itemsize[ring_id], dma_buf);
1083         ring->dma_handle = dma_handle;
1084         ring->devinfo = devinfo;
1085         brcmf_commonring_register_cb(&ring->commonring,
1086                                      brcmf_pcie_ring_mb_ring_bell,
1087                                      brcmf_pcie_ring_mb_update_rptr,
1088                                      brcmf_pcie_ring_mb_update_wptr,
1089                                      brcmf_pcie_ring_mb_write_rptr,
1090                                      brcmf_pcie_ring_mb_write_wptr, ring);
1091
1092         return (ring);
1093 }
1094
1095
1096 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1097                                           struct brcmf_pcie_ringbuf *ring)
1098 {
1099         void *dma_buf;
1100         u32 size;
1101
1102         if (!ring)
1103                 return;
1104
1105         dma_buf = ring->commonring.buf_addr;
1106         if (dma_buf) {
1107                 size = ring->commonring.depth * ring->commonring.item_len;
1108                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1109         }
1110         kfree(ring);
1111 }
1112
1113
1114 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1115 {
1116         u32 i;
1117
1118         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1119                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1120                                               devinfo->shared.commonrings[i]);
1121                 devinfo->shared.commonrings[i] = NULL;
1122         }
1123         kfree(devinfo->shared.flowrings);
1124         devinfo->shared.flowrings = NULL;
1125         if (devinfo->idxbuf) {
1126                 dma_free_coherent(&devinfo->pdev->dev,
1127                                   devinfo->idxbuf_sz,
1128                                   devinfo->idxbuf,
1129                                   devinfo->idxbuf_dmahandle);
1130                 devinfo->idxbuf = NULL;
1131         }
1132 }
1133
1134
1135 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1136 {
1137         struct brcmf_pcie_ringbuf *ring;
1138         struct brcmf_pcie_ringbuf *rings;
1139         u32 ring_addr;
1140         u32 d2h_w_idx_ptr;
1141         u32 d2h_r_idx_ptr;
1142         u32 h2d_w_idx_ptr;
1143         u32 h2d_r_idx_ptr;
1144         u32 addr;
1145         u32 ring_mem_ptr;
1146         u32 i;
1147         u64 address;
1148         u32 bufsz;
1149         u16 max_sub_queues;
1150         u8 idx_offset;
1151
1152         ring_addr = devinfo->shared.ring_info_addr;
1153         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1154         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1155         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1156
1157         if (devinfo->dma_idx_sz != 0) {
1158                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1159                         devinfo->dma_idx_sz * 2;
1160                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1161                                                      &devinfo->idxbuf_dmahandle,
1162                                                      GFP_KERNEL);
1163                 if (!devinfo->idxbuf)
1164                         devinfo->dma_idx_sz = 0;
1165         }
1166
1167         if (devinfo->dma_idx_sz == 0) {
1168                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1169                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1170                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1171                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1172                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1173                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1174                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1175                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1176                 idx_offset = sizeof(u32);
1177                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1178                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1179                 brcmf_dbg(PCIE, "Using TCM indices\n");
1180         } else {
1181                 memset(devinfo->idxbuf, 0, bufsz);
1182                 devinfo->idxbuf_sz = bufsz;
1183                 idx_offset = devinfo->dma_idx_sz;
1184                 devinfo->write_ptr = brcmf_pcie_write_idx;
1185                 devinfo->read_ptr = brcmf_pcie_read_idx;
1186
1187                 h2d_w_idx_ptr = 0;
1188                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1189                 address = (u64)devinfo->idxbuf_dmahandle;
1190                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1191                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1192
1193                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1194                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1195                 address += max_sub_queues * idx_offset;
1196                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1197                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1198
1199                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1200                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1201                 address += max_sub_queues * idx_offset;
1202                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1203                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1204
1205                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1206                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1207                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1208                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1209                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1210                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1211                 brcmf_dbg(PCIE, "Using host memory indices\n");
1212         }
1213
1214         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1215         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1216
1217         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1218                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1219                 if (!ring)
1220                         goto fail;
1221                 ring->w_idx_addr = h2d_w_idx_ptr;
1222                 ring->r_idx_addr = h2d_r_idx_ptr;
1223                 ring->id = i;
1224                 devinfo->shared.commonrings[i] = ring;
1225
1226                 h2d_w_idx_ptr += idx_offset;
1227                 h2d_r_idx_ptr += idx_offset;
1228                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1229         }
1230
1231         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1232              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1233                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1234                 if (!ring)
1235                         goto fail;
1236                 ring->w_idx_addr = d2h_w_idx_ptr;
1237                 ring->r_idx_addr = d2h_r_idx_ptr;
1238                 ring->id = i;
1239                 devinfo->shared.commonrings[i] = ring;
1240
1241                 d2h_w_idx_ptr += idx_offset;
1242                 d2h_r_idx_ptr += idx_offset;
1243                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1244         }
1245
1246         devinfo->shared.nrof_flowrings =
1247                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1248         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1249                         GFP_KERNEL);
1250         if (!rings)
1251                 goto fail;
1252
1253         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1254                   devinfo->shared.nrof_flowrings);
1255
1256         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1257                 ring = &rings[i];
1258                 ring->devinfo = devinfo;
1259                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1260                 brcmf_commonring_register_cb(&ring->commonring,
1261                                              brcmf_pcie_ring_mb_ring_bell,
1262                                              brcmf_pcie_ring_mb_update_rptr,
1263                                              brcmf_pcie_ring_mb_update_wptr,
1264                                              brcmf_pcie_ring_mb_write_rptr,
1265                                              brcmf_pcie_ring_mb_write_wptr,
1266                                              ring);
1267                 ring->w_idx_addr = h2d_w_idx_ptr;
1268                 ring->r_idx_addr = h2d_r_idx_ptr;
1269                 h2d_w_idx_ptr += idx_offset;
1270                 h2d_r_idx_ptr += idx_offset;
1271         }
1272         devinfo->shared.flowrings = rings;
1273
1274         return 0;
1275
1276 fail:
1277         brcmf_err("Allocating ring buffers failed\n");
1278         brcmf_pcie_release_ringbuffers(devinfo);
1279         return -ENOMEM;
1280 }
1281
1282
1283 static void
1284 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1285 {
1286         if (devinfo->shared.scratch)
1287                 dma_free_coherent(&devinfo->pdev->dev,
1288                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1289                                   devinfo->shared.scratch,
1290                                   devinfo->shared.scratch_dmahandle);
1291         if (devinfo->shared.ringupd)
1292                 dma_free_coherent(&devinfo->pdev->dev,
1293                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1294                                   devinfo->shared.ringupd,
1295                                   devinfo->shared.ringupd_dmahandle);
1296 }
1297
1298 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1299 {
1300         u64 address;
1301         u32 addr;
1302
1303         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1304                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1305                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1306         if (!devinfo->shared.scratch)
1307                 goto fail;
1308
1309         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1310
1311         addr = devinfo->shared.tcm_base_address +
1312                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1313         address = (u64)devinfo->shared.scratch_dmahandle;
1314         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1315         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1316         addr = devinfo->shared.tcm_base_address +
1317                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1318         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1319
1320         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1321                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1322                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1323         if (!devinfo->shared.ringupd)
1324                 goto fail;
1325
1326         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1327
1328         addr = devinfo->shared.tcm_base_address +
1329                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1330         address = (u64)devinfo->shared.ringupd_dmahandle;
1331         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1332         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1333         addr = devinfo->shared.tcm_base_address +
1334                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1335         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1336         return 0;
1337
1338 fail:
1339         brcmf_err("Allocating scratch buffers failed\n");
1340         brcmf_pcie_release_scratchbuffers(devinfo);
1341         return -ENOMEM;
1342 }
1343
1344
1345 static void brcmf_pcie_down(struct device *dev)
1346 {
1347 }
1348
1349
1350 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1351 {
1352         return 0;
1353 }
1354
1355
1356 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1357                                 uint len)
1358 {
1359         return 0;
1360 }
1361
1362
1363 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1364                                 uint len)
1365 {
1366         return 0;
1367 }
1368
1369
1370 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1371 {
1372         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1373         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1374         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1375
1376         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1377         devinfo->wowl_enabled = enabled;
1378         if (enabled)
1379                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1380         else
1381                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1382 }
1383
1384
1385 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1386 {
1387         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1388         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1389         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1390
1391         return devinfo->ci->ramsize - devinfo->ci->srsize;
1392 }
1393
1394
1395 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1396 {
1397         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1398         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1399         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1400
1401         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1402         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1403         return 0;
1404 }
1405
1406
1407 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1408         .txdata = brcmf_pcie_tx,
1409         .stop = brcmf_pcie_down,
1410         .txctl = brcmf_pcie_tx_ctlpkt,
1411         .rxctl = brcmf_pcie_rx_ctlpkt,
1412         .wowl_config = brcmf_pcie_wowl_config,
1413         .get_ramsize = brcmf_pcie_get_ramsize,
1414         .get_memdump = brcmf_pcie_get_memdump,
1415 };
1416
1417
1418 static int
1419 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1420                                u32 sharedram_addr)
1421 {
1422         struct brcmf_pcie_shared_info *shared;
1423         u32 addr;
1424         u32 version;
1425
1426         shared = &devinfo->shared;
1427         shared->tcm_base_address = sharedram_addr;
1428
1429         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1430         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1431         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1432         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1433             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1434                 brcmf_err("Unsupported PCIE version %d\n", version);
1435                 return -EINVAL;
1436         }
1437
1438         /* check firmware support dma indicies */
1439         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1440                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1441                         devinfo->dma_idx_sz = sizeof(u16);
1442                 else
1443                         devinfo->dma_idx_sz = sizeof(u32);
1444         }
1445
1446         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1447         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1448         if (shared->max_rxbufpost == 0)
1449                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1450
1451         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1452         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1453
1454         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1455         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1456
1457         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1458         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1459
1460         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1461         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1462
1463         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1464                   shared->max_rxbufpost, shared->rx_dataoffset);
1465
1466         brcmf_pcie_bus_console_init(devinfo);
1467
1468         return 0;
1469 }
1470
1471
1472 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1473 {
1474         char *fw_name;
1475         char *nvram_name;
1476         uint fw_len, nv_len;
1477         char end;
1478
1479         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1480                   devinfo->ci->chiprev);
1481
1482         switch (devinfo->ci->chip) {
1483         case BRCM_CC_43602_CHIP_ID:
1484                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1485                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1486                 break;
1487         case BRCM_CC_4350_CHIP_ID:
1488                 fw_name = BRCMF_PCIE_4350_FW_NAME;
1489                 nvram_name = BRCMF_PCIE_4350_NVRAM_NAME;
1490                 break;
1491         case BRCM_CC_4356_CHIP_ID:
1492                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1493                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1494                 break;
1495         case BRCM_CC_43567_CHIP_ID:
1496         case BRCM_CC_43569_CHIP_ID:
1497         case BRCM_CC_43570_CHIP_ID:
1498                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1499                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1500                 break;
1501         case BRCM_CC_4358_CHIP_ID:
1502                 fw_name = BRCMF_PCIE_4358_FW_NAME;
1503                 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1504                 break;
1505         case BRCM_CC_4365_CHIP_ID:
1506                 fw_name = BRCMF_PCIE_4365_FW_NAME;
1507                 nvram_name = BRCMF_PCIE_4365_NVRAM_NAME;
1508                 break;
1509         case BRCM_CC_4366_CHIP_ID:
1510                 fw_name = BRCMF_PCIE_4366_FW_NAME;
1511                 nvram_name = BRCMF_PCIE_4366_NVRAM_NAME;
1512                 break;
1513         case BRCM_CC_4371_CHIP_ID:
1514                 fw_name = BRCMF_PCIE_4371_FW_NAME;
1515                 nvram_name = BRCMF_PCIE_4371_NVRAM_NAME;
1516                 break;
1517         default:
1518                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1519                 return -ENODEV;
1520         }
1521
1522         fw_len = sizeof(devinfo->fw_name) - 1;
1523         nv_len = sizeof(devinfo->nvram_name) - 1;
1524         /* check if firmware path is provided by module parameter */
1525         if (brcmf_firmware_path[0] != '\0') {
1526                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1527                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1528                 fw_len -= strlen(devinfo->fw_name);
1529                 nv_len -= strlen(devinfo->nvram_name);
1530
1531                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1532                 if (end != '/') {
1533                         strncat(devinfo->fw_name, "/", fw_len);
1534                         strncat(devinfo->nvram_name, "/", nv_len);
1535                         fw_len--;
1536                         nv_len--;
1537                 }
1538         }
1539         strncat(devinfo->fw_name, fw_name, fw_len);
1540         strncat(devinfo->nvram_name, nvram_name, nv_len);
1541
1542         return 0;
1543 }
1544
1545
1546 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1547                                         const struct firmware *fw, void *nvram,
1548                                         u32 nvram_len)
1549 {
1550         u32 sharedram_addr;
1551         u32 sharedram_addr_written;
1552         u32 loop_counter;
1553         int err;
1554         u32 address;
1555         u32 resetintr;
1556
1557         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1558         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1559
1560         brcmf_dbg(PCIE, "Halt ARM.\n");
1561         err = brcmf_pcie_enter_download_state(devinfo);
1562         if (err)
1563                 return err;
1564
1565         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1566         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1567                                   (void *)fw->data, fw->size);
1568
1569         resetintr = get_unaligned_le32(fw->data);
1570         release_firmware(fw);
1571
1572         /* reset last 4 bytes of RAM address. to be used for shared
1573          * area. This identifies when FW is running
1574          */
1575         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1576
1577         if (nvram) {
1578                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1579                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1580                           nvram_len;
1581                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1582                 brcmf_fw_nvram_free(nvram);
1583         } else {
1584                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1585                           devinfo->nvram_name);
1586         }
1587
1588         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1589                                                        devinfo->ci->ramsize -
1590                                                        4);
1591         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1592         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1593         if (err)
1594                 return err;
1595
1596         brcmf_dbg(PCIE, "Wait for FW init\n");
1597         sharedram_addr = sharedram_addr_written;
1598         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1599         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1600                 msleep(50);
1601                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1602                                                        devinfo->ci->ramsize -
1603                                                        4);
1604                 loop_counter--;
1605         }
1606         if (sharedram_addr == sharedram_addr_written) {
1607                 brcmf_err("FW failed to initialize\n");
1608                 return -ENODEV;
1609         }
1610         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1611
1612         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1613 }
1614
1615
1616 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1617 {
1618         struct pci_dev *pdev;
1619         int err;
1620         phys_addr_t  bar0_addr, bar1_addr;
1621         ulong bar1_size;
1622
1623         pdev = devinfo->pdev;
1624
1625         err = pci_enable_device(pdev);
1626         if (err) {
1627                 brcmf_err("pci_enable_device failed err=%d\n", err);
1628                 return err;
1629         }
1630
1631         pci_set_master(pdev);
1632
1633         /* Bar-0 mapped address */
1634         bar0_addr = pci_resource_start(pdev, 0);
1635         /* Bar-1 mapped address */
1636         bar1_addr = pci_resource_start(pdev, 2);
1637         /* read Bar-1 mapped memory range */
1638         bar1_size = pci_resource_len(pdev, 2);
1639         if ((bar1_size == 0) || (bar1_addr == 0)) {
1640                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1641                           bar1_size, (unsigned long long)bar1_addr);
1642                 return -EINVAL;
1643         }
1644
1645         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1646         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1647         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1648
1649         if (!devinfo->regs || !devinfo->tcm) {
1650                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1651                           devinfo->tcm);
1652                 return -EINVAL;
1653         }
1654         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1655                   devinfo->regs, (unsigned long long)bar0_addr);
1656         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1657                   devinfo->tcm, (unsigned long long)bar1_addr);
1658
1659         return 0;
1660 }
1661
1662
1663 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1664 {
1665         if (devinfo->tcm)
1666                 iounmap(devinfo->tcm);
1667         if (devinfo->regs)
1668                 iounmap(devinfo->regs);
1669
1670         pci_disable_device(devinfo->pdev);
1671 }
1672
1673
1674 static int brcmf_pcie_attach_bus(struct device *dev)
1675 {
1676         int ret;
1677
1678         /* Attach to the common driver interface */
1679         ret = brcmf_attach(dev);
1680         if (ret) {
1681                 brcmf_err("brcmf_attach failed\n");
1682         } else {
1683                 ret = brcmf_bus_start(dev);
1684                 if (ret)
1685                         brcmf_err("dongle is not responding\n");
1686         }
1687
1688         return ret;
1689 }
1690
1691
1692 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1693 {
1694         u32 ret_addr;
1695
1696         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1697         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1698         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1699
1700         return ret_addr;
1701 }
1702
1703
1704 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1705 {
1706         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1707
1708         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1709         return brcmf_pcie_read_reg32(devinfo, addr);
1710 }
1711
1712
1713 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1714 {
1715         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1716
1717         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1718         brcmf_pcie_write_reg32(devinfo, addr, value);
1719 }
1720
1721
1722 static int brcmf_pcie_buscoreprep(void *ctx)
1723 {
1724         return brcmf_pcie_get_resource(ctx);
1725 }
1726
1727
1728 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1729 {
1730         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1731         u32 val;
1732
1733         devinfo->ci = chip;
1734         brcmf_pcie_reset_device(devinfo);
1735
1736         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1737         if (val != 0xffffffff)
1738                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1739                                        val);
1740
1741         return 0;
1742 }
1743
1744
1745 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1746                                         u32 rstvec)
1747 {
1748         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1749
1750         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1751 }
1752
1753
1754 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1755         .prepare = brcmf_pcie_buscoreprep,
1756         .reset = brcmf_pcie_buscore_reset,
1757         .activate = brcmf_pcie_buscore_activate,
1758         .read32 = brcmf_pcie_buscore_read32,
1759         .write32 = brcmf_pcie_buscore_write32,
1760 };
1761
1762 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1763                              void *nvram, u32 nvram_len)
1764 {
1765         struct brcmf_bus *bus = dev_get_drvdata(dev);
1766         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1767         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1768         struct brcmf_commonring **flowrings;
1769         int ret;
1770         u32 i;
1771
1772         brcmf_pcie_attach(devinfo);
1773
1774         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1775         if (ret)
1776                 goto fail;
1777
1778         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1779
1780         ret = brcmf_pcie_init_ringbuffers(devinfo);
1781         if (ret)
1782                 goto fail;
1783
1784         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1785         if (ret)
1786                 goto fail;
1787
1788         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1789         ret = brcmf_pcie_request_irq(devinfo);
1790         if (ret)
1791                 goto fail;
1792
1793         /* hook the commonrings in the bus structure. */
1794         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1795                 bus->msgbuf->commonrings[i] =
1796                                 &devinfo->shared.commonrings[i]->commonring;
1797
1798         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1799                             GFP_KERNEL);
1800         if (!flowrings)
1801                 goto fail;
1802
1803         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1804                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1805         bus->msgbuf->flowrings = flowrings;
1806
1807         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1808         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1809         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1810
1811         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1812
1813         brcmf_pcie_intr_enable(devinfo);
1814         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1815                 return;
1816
1817         brcmf_pcie_bus_console_read(devinfo);
1818
1819 fail:
1820         device_release_driver(dev);
1821 }
1822
1823 static int
1824 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1825 {
1826         int ret;
1827         struct brcmf_pciedev_info *devinfo;
1828         struct brcmf_pciedev *pcie_bus_dev;
1829         struct brcmf_bus *bus;
1830         u16 domain_nr;
1831         u16 bus_nr;
1832
1833         domain_nr = pci_domain_nr(pdev->bus) + 1;
1834         bus_nr = pdev->bus->number;
1835         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1836                   domain_nr, bus_nr);
1837
1838         ret = -ENOMEM;
1839         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1840         if (devinfo == NULL)
1841                 return ret;
1842
1843         devinfo->pdev = pdev;
1844         pcie_bus_dev = NULL;
1845         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1846         if (IS_ERR(devinfo->ci)) {
1847                 ret = PTR_ERR(devinfo->ci);
1848                 devinfo->ci = NULL;
1849                 goto fail;
1850         }
1851
1852         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1853         if (pcie_bus_dev == NULL) {
1854                 ret = -ENOMEM;
1855                 goto fail;
1856         }
1857
1858         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1859         if (!bus) {
1860                 ret = -ENOMEM;
1861                 goto fail;
1862         }
1863         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1864         if (!bus->msgbuf) {
1865                 ret = -ENOMEM;
1866                 kfree(bus);
1867                 goto fail;
1868         }
1869
1870         /* hook it all together. */
1871         pcie_bus_dev->devinfo = devinfo;
1872         pcie_bus_dev->bus = bus;
1873         bus->dev = &pdev->dev;
1874         bus->bus_priv.pcie = pcie_bus_dev;
1875         bus->ops = &brcmf_pcie_bus_ops;
1876         bus->proto_type = BRCMF_PROTO_MSGBUF;
1877         bus->chip = devinfo->coreid;
1878         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1879         dev_set_drvdata(&pdev->dev, bus);
1880
1881         ret = brcmf_pcie_get_fwnames(devinfo);
1882         if (ret)
1883                 goto fail_bus;
1884
1885         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1886                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1887                                           devinfo->fw_name, devinfo->nvram_name,
1888                                           brcmf_pcie_setup, domain_nr, bus_nr);
1889         if (ret == 0)
1890                 return 0;
1891 fail_bus:
1892         kfree(bus->msgbuf);
1893         kfree(bus);
1894 fail:
1895         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1896         brcmf_pcie_release_resource(devinfo);
1897         if (devinfo->ci)
1898                 brcmf_chip_detach(devinfo->ci);
1899         kfree(pcie_bus_dev);
1900         kfree(devinfo);
1901         return ret;
1902 }
1903
1904
1905 static void
1906 brcmf_pcie_remove(struct pci_dev *pdev)
1907 {
1908         struct brcmf_pciedev_info *devinfo;
1909         struct brcmf_bus *bus;
1910
1911         brcmf_dbg(PCIE, "Enter\n");
1912
1913         bus = dev_get_drvdata(&pdev->dev);
1914         if (bus == NULL)
1915                 return;
1916
1917         devinfo = bus->bus_priv.pcie->devinfo;
1918
1919         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1920         if (devinfo->ci)
1921                 brcmf_pcie_intr_disable(devinfo);
1922
1923         brcmf_detach(&pdev->dev);
1924
1925         kfree(bus->bus_priv.pcie);
1926         kfree(bus->msgbuf->flowrings);
1927         kfree(bus->msgbuf);
1928         kfree(bus);
1929
1930         brcmf_pcie_release_irq(devinfo);
1931         brcmf_pcie_release_scratchbuffers(devinfo);
1932         brcmf_pcie_release_ringbuffers(devinfo);
1933         brcmf_pcie_reset_device(devinfo);
1934         brcmf_pcie_release_resource(devinfo);
1935
1936         if (devinfo->ci)
1937                 brcmf_chip_detach(devinfo->ci);
1938
1939         kfree(devinfo);
1940         dev_set_drvdata(&pdev->dev, NULL);
1941 }
1942
1943
1944 #ifdef CONFIG_PM
1945
1946
1947 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1948 {
1949         struct brcmf_pciedev_info *devinfo;
1950         struct brcmf_bus *bus;
1951         int err;
1952
1953         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1954
1955         bus = dev_get_drvdata(&pdev->dev);
1956         devinfo = bus->bus_priv.pcie->devinfo;
1957
1958         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1959
1960         devinfo->mbdata_completed = false;
1961         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1962
1963         wait_event_timeout(devinfo->mbdata_resp_wait,
1964                            devinfo->mbdata_completed,
1965                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1966         if (!devinfo->mbdata_completed) {
1967                 brcmf_err("Timeout on response for entering D3 substate\n");
1968                 return -EIO;
1969         }
1970         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1971
1972         err = pci_save_state(pdev);
1973         if (err)
1974                 brcmf_err("pci_save_state failed, err=%d\n", err);
1975         if ((err) || (!devinfo->wowl_enabled)) {
1976                 brcmf_chip_detach(devinfo->ci);
1977                 devinfo->ci = NULL;
1978                 brcmf_pcie_remove(pdev);
1979                 return 0;
1980         }
1981
1982         return pci_prepare_to_sleep(pdev);
1983 }
1984
1985 static int brcmf_pcie_resume(struct pci_dev *pdev)
1986 {
1987         struct brcmf_pciedev_info *devinfo;
1988         struct brcmf_bus *bus;
1989         int err;
1990
1991         bus = dev_get_drvdata(&pdev->dev);
1992         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
1993
1994         err = pci_set_power_state(pdev, PCI_D0);
1995         if (err) {
1996                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1997                 goto cleanup;
1998         }
1999         pci_restore_state(pdev);
2000         pci_enable_wake(pdev, PCI_D3hot, false);
2001         pci_enable_wake(pdev, PCI_D3cold, false);
2002
2003         /* Check if device is still up and running, if so we are ready */
2004         if (bus) {
2005                 devinfo = bus->bus_priv.pcie->devinfo;
2006                 if (brcmf_pcie_read_reg32(devinfo,
2007                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
2008                         if (brcmf_pcie_send_mb_data(devinfo,
2009                                                     BRCMF_H2D_HOST_D0_INFORM))
2010                                 goto cleanup;
2011                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
2012                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2013                         brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2014                         brcmf_pcie_intr_enable(devinfo);
2015                         return 0;
2016                 }
2017         }
2018
2019 cleanup:
2020         if (bus) {
2021                 devinfo = bus->bus_priv.pcie->devinfo;
2022                 brcmf_chip_detach(devinfo->ci);
2023                 devinfo->ci = NULL;
2024                 brcmf_pcie_remove(pdev);
2025         }
2026         err = brcmf_pcie_probe(pdev, NULL);
2027         if (err)
2028                 brcmf_err("probe after resume failed, err=%d\n", err);
2029
2030         return err;
2031 }
2032
2033
2034 #endif /* CONFIG_PM */
2035
2036
2037 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2038         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2039
2040 static struct pci_device_id brcmf_pcie_devid_table[] = {
2041         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
2042         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
2043         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
2044         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
2045         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
2046         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
2047         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
2048         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
2049         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
2050         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
2051         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
2052         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
2053         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
2054         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
2055         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
2056         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
2057         { /* end: all zeroes */ }
2058 };
2059
2060
2061 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2062
2063
2064 static struct pci_driver brcmf_pciedrvr = {
2065         .node = {},
2066         .name = KBUILD_MODNAME,
2067         .id_table = brcmf_pcie_devid_table,
2068         .probe = brcmf_pcie_probe,
2069         .remove = brcmf_pcie_remove,
2070 #ifdef CONFIG_PM
2071         .suspend = brcmf_pcie_suspend,
2072         .resume = brcmf_pcie_resume
2073 #endif /* CONFIG_PM */
2074 };
2075
2076
2077 void brcmf_pcie_register(void)
2078 {
2079         int err;
2080
2081         brcmf_dbg(PCIE, "Enter\n");
2082         err = pci_register_driver(&brcmf_pciedrvr);
2083         if (err)
2084                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2085 }
2086
2087
2088 void brcmf_pcie_exit(void)
2089 {
2090         brcmf_dbg(PCIE, "Enter\n");
2091         pci_unregister_driver(&brcmf_pciedrvr);
2092 }