2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/platform_data/brcmfmac-sdio.h>
37 #include <linux/moduleparam.h>
38 #include <asm/unaligned.h>
40 #include <brcmu_wifi.h>
41 #include <brcmu_utils.h>
42 #include <brcm_hw_ids.h>
48 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
49 #define CTL_DONE_TIMEOUT 2000 /* In milli second */
53 #define BRCMF_TRAP_INFO_SIZE 80
55 #define CBUF_LEN (128)
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
64 char *_buf_compat; /* Redundant pointer for backward compat. */
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
86 struct rte_log_le log_le;
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
99 #include <chipcommon.h>
103 #include "tracepoint.h"
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
110 #define TXRETRIES 2 /* # of retries for tx frames */
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120 #define MEMBLOCK 2048 /* Block size used for downloading
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
125 #define BRCMF_FIRSTREAD (1 << 6)
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129 /* SBSDIO_DEVICE_CTL */
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149 /* direct(mapped) cis space */
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
239 * Software allocation of To SB Mailbox resources
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
252 * Software allocation of To Host Mailbox resources
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
274 * Software-defined protocol header
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
312 #define BRCMF_IDLE_INTERVAL 1
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
318 * Conversion of 802.1D priority to precedence level
320 static uint prio2prec(u32 prio)
322 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
327 /* Device console log buffer state */
328 struct brcmf_console {
329 uint count; /* Poll interval msec counter */
330 uint log_addr; /* Log struct address (fixed) */
331 struct rte_log_le log_le; /* Log struct (host copy) */
332 uint bufsize; /* Size of log buffer */
333 u8 *buf; /* Log buffer (host copy) */
334 uint last; /* Last buffer read index */
337 struct brcmf_trap_info {
351 __le32 r9; /* sb/v6 */
352 __le32 r10; /* sl/v7 */
353 __le32 r11; /* fp/v8 */
361 struct sdpcm_shared {
365 u32 assert_file_addr;
367 u32 console_addr; /* Address of struct rte_console */
373 struct sdpcm_shared_le {
376 __le32 assert_exp_addr;
377 __le32 assert_file_addr;
379 __le32 console_addr; /* Address of struct rte_console */
380 __le32 msgtrace_addr;
385 /* dongle SDIO bus specific header info */
386 struct brcmf_sdio_hdrinfo {
398 * hold counter variables
400 struct brcmf_sdio_count {
401 uint intrcount; /* Count of device interrupt callbacks */
402 uint lastintrs; /* Count as of last watchdog timer */
403 uint pollcnt; /* Count of active polls */
404 uint regfails; /* Count of R_REG failures */
405 uint tx_sderrs; /* Count of tx attempts with sd errors */
406 uint fcqueued; /* Tx packets that got queued */
407 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
408 uint rx_toolong; /* Receive frames too long to receive */
409 uint rxc_errors; /* SDIO errors when reading control frames */
410 uint rx_hdrfail; /* SDIO errors on header reads */
411 uint rx_badhdr; /* Bad received headers (roosync?) */
412 uint rx_badseq; /* Mismatched rx sequence number */
413 uint fc_rcvd; /* Number of flow-control events received */
414 uint fc_xoff; /* Number which turned on flow-control */
415 uint fc_xon; /* Number which turned off flow-control */
416 uint rxglomfail; /* Failed deglom attempts */
417 uint rxglomframes; /* Number of glom frames (superframes) */
418 uint rxglompkts; /* Number of packets from glom frames */
419 uint f2rxhdrs; /* Number of header reads */
420 uint f2rxdata; /* Number of frame data reads */
421 uint f2txdata; /* Number of f2 frame writes */
422 uint f1regdata; /* Number of f1 register accesses */
423 uint tickcnt; /* Number of watchdog been schedule */
424 ulong tx_ctlerrs; /* Err of sending ctrl frames */
425 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
426 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
427 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
428 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
431 /* misc chip info needed by some of the routines */
432 /* Private data for SDIO bus interaction */
434 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
435 struct brcmf_chip *ci; /* Chip info struct */
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
463 uint glomerr; /* Glom packet read errors */
465 u8 *rxbuf; /* Buffer for receiving control packets */
466 uint rxblen; /* Allocated length of rxbuf */
467 u8 *rxctl; /* Aligned pointer into rxbuf */
468 u8 *rxctl_orig; /* pointer for freeing rxctl */
469 uint rxlen; /* Length of valid data in buffer */
470 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
472 u8 sdpcm_ver; /* Bus protocol reported by dongle */
474 bool intr; /* Use interrupts */
475 bool poll; /* Use polling */
476 atomic_t ipend; /* Device interrupt is pending */
477 uint spurious; /* Count of spurious interrupts */
478 uint pollrate; /* Ticks between device polls */
479 uint polltick; /* Tick counter */
482 uint console_interval;
483 struct brcmf_console console; /* Console output polling support */
484 uint console_addr; /* Console address from shared struct */
487 uint clkstate; /* State of sd and backplane clock(s) */
488 s32 idletime; /* Control for activity timeout */
489 s32 idlecount; /* Activity timeout counter */
490 s32 idleclock; /* How to set bus driver when idle */
491 bool rxflow_mode; /* Rx flow control mode */
492 bool rxflow; /* Is rx flow control on */
493 bool alp_only; /* Don't use HT clock (ALP only) */
497 bool ctrl_frame_stat;
500 spinlock_t txq_lock; /* protect bus->txq */
501 wait_queue_head_t ctrl_wait;
502 wait_queue_head_t dcmd_resp_wait;
504 struct timer_list timer;
505 struct completion watchdog_wait;
506 struct task_struct *watchdog_tsk;
510 struct workqueue_struct *brcmf_wq;
511 struct work_struct datawork;
515 bool txoff; /* Transmit flow-controlled */
516 struct brcmf_sdio_count sdcnt;
517 bool sr_enabled; /* SaveRestore enabled */
520 u8 tx_hdrlen; /* sdio bus header length for tx packet */
521 bool txglom; /* host tx glomming enable flag */
522 u16 head_align; /* buffer pointer alignment */
523 u16 sgentry_align; /* scatter-gather buffer alignment */
529 #define CLK_PENDING 2
533 static int qcount[NUMPRIO];
536 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
538 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
540 /* Retry count for register access failures */
541 static const uint retry_limit = 2;
543 /* Limit on rounding up frames */
544 static const uint max_roundup = 512;
548 enum brcmf_sdio_frmtype {
549 BRCMF_SDIO_FT_NORMAL,
554 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
556 /* SDIO Pad drive strength to select value mappings */
557 struct sdiod_drive_str {
558 u8 strength; /* Pad Drive Strength in mA */
559 u8 sel; /* Chip-specific select value */
562 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
563 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
574 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
575 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
585 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
586 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
592 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
593 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
600 #define BCM43143_FIRMWARE_NAME "/*(DEBLOBBED)*/"
601 #define BCM43143_NVRAM_NAME "/*(DEBLOBBED)*/"
602 #define BCM43241B0_FIRMWARE_NAME "/*(DEBLOBBED)*/"
603 #define BCM43241B0_NVRAM_NAME "/*(DEBLOBBED)*/"
604 #define BCM43241B4_FIRMWARE_NAME "/*(DEBLOBBED)*/"
605 #define BCM43241B4_NVRAM_NAME "/*(DEBLOBBED)*/"
606 #define BCM43241B5_FIRMWARE_NAME "/*(DEBLOBBED)*/"
607 #define BCM43241B5_NVRAM_NAME "/*(DEBLOBBED)*/"
608 #define BCM4329_FIRMWARE_NAME "/*(DEBLOBBED)*/"
609 #define BCM4329_NVRAM_NAME "/*(DEBLOBBED)*/"
610 #define BCM4330_FIRMWARE_NAME "/*(DEBLOBBED)*/"
611 #define BCM4330_NVRAM_NAME "/*(DEBLOBBED)*/"
612 #define BCM4334_FIRMWARE_NAME "/*(DEBLOBBED)*/"
613 #define BCM4334_NVRAM_NAME "/*(DEBLOBBED)*/"
614 #define BCM43340_FIRMWARE_NAME "/*(DEBLOBBED)*/"
615 #define BCM43340_NVRAM_NAME "/*(DEBLOBBED)*/"
616 #define BCM4335_FIRMWARE_NAME "/*(DEBLOBBED)*/"
617 #define BCM4335_NVRAM_NAME "/*(DEBLOBBED)*/"
618 #define BCM43362_FIRMWARE_NAME "/*(DEBLOBBED)*/"
619 #define BCM43362_NVRAM_NAME "/*(DEBLOBBED)*/"
620 #define BCM4339_FIRMWARE_NAME "/*(DEBLOBBED)*/"
621 #define BCM4339_NVRAM_NAME "/*(DEBLOBBED)*/"
622 #define BCM43430_FIRMWARE_NAME "/*(DEBLOBBED)*/"
623 #define BCM43430_NVRAM_NAME "/*(DEBLOBBED)*/"
624 #define BCM43455_FIRMWARE_NAME "/*(DEBLOBBED)*/"
625 #define BCM43455_NVRAM_NAME "/*(DEBLOBBED)*/"
626 #define BCM4354_FIRMWARE_NAME "/*(DEBLOBBED)*/"
627 #define BCM4354_NVRAM_NAME "/*(DEBLOBBED)*/"
631 struct brcmf_firmware_names {
638 enum brcmf_firmware_type {
643 #define BRCMF_FIRMWARE_NVRAM(name) \
644 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
646 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
647 { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
648 { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
649 { BRCM_CC_43241_CHIP_ID, 0x00000020, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
650 { BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43241B5) },
651 { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
652 { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
653 { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
654 { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
655 { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
656 { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
657 { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
658 { BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43430) },
659 { BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43455) },
660 { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
663 static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
664 struct brcmf_sdio_dev *sdiodev)
669 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
670 if (brcmf_fwname_data[i].chipid == ci->chip &&
671 brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
675 if (i == ARRAY_SIZE(brcmf_fwname_data)) {
676 brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
680 /* check if firmware path is provided by module parameter */
681 if (brcmf_firmware_path[0] != '\0') {
682 strlcpy(sdiodev->fw_name, brcmf_firmware_path,
683 sizeof(sdiodev->fw_name));
684 strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
685 sizeof(sdiodev->nvram_name));
687 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
689 strlcat(sdiodev->fw_name, "/",
690 sizeof(sdiodev->fw_name));
691 strlcat(sdiodev->nvram_name, "/",
692 sizeof(sdiodev->nvram_name));
695 strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
696 sizeof(sdiodev->fw_name));
697 strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
698 sizeof(sdiodev->nvram_name));
703 static void pkt_align(struct sk_buff *p, int len, int align)
706 datalign = (unsigned long)(p->data);
707 datalign = roundup(datalign, (align)) - datalign;
709 skb_pull(p, datalign);
713 /* To check if there's window offered */
714 static bool data_ok(struct brcmf_sdio *bus)
716 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
717 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
721 * Reads a register in the SDIO hardware block. This block occupies a series of
722 * adresses on the 32 bit backplane bus.
724 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
726 struct brcmf_core *core;
729 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
730 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
735 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
737 struct brcmf_core *core;
740 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
741 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
747 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
749 u8 wr_val = 0, rd_val, cmp_val, bmask;
753 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
755 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
756 /* 1st KSO write goes to AOS wake up core if device is asleep */
757 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
761 /* device WAKEUP through KSO:
762 * write bit 0 & read back until
763 * both bits 0 (kso bit) & 1 (dev on status) are set
765 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
766 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
768 usleep_range(2000, 3000);
770 /* Put device to sleep, turn off KSO */
772 /* only check for bit0, bit1(dev on status) may not
773 * get cleared right away
775 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
779 /* reliable KSO bit set/clr:
780 * the sdiod sleep write access is synced to PMU 32khz clk
781 * just one write attempt may fail,
782 * read it back until it matches written value
784 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
786 if (((rd_val & bmask) == cmp_val) && !err)
790 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
792 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
795 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
798 if (try_cnt > MAX_KSO_ATTEMPTS)
799 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
804 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
806 /* Turn backplane clock on or off */
807 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
810 u8 clkctl, clkreq, devctl;
811 unsigned long timeout;
813 brcmf_dbg(SDIO, "Enter\n");
817 if (bus->sr_enabled) {
818 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
823 /* Request HT Avail */
825 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
827 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
830 brcmf_err("HT Avail request error: %d\n", err);
834 /* Check current status */
835 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
836 SBSDIO_FUNC1_CHIPCLKCSR, &err);
838 brcmf_err("HT Avail read error: %d\n", err);
842 /* Go to pending and await interrupt if appropriate */
843 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
844 /* Allow only clock-available interrupt */
845 devctl = brcmf_sdiod_regrb(bus->sdiodev,
846 SBSDIO_DEVICE_CTL, &err);
848 brcmf_err("Devctl error setting CA: %d\n",
853 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
854 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
856 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
857 bus->clkstate = CLK_PENDING;
860 } else if (bus->clkstate == CLK_PENDING) {
861 /* Cancel CA-only interrupt filter */
862 devctl = brcmf_sdiod_regrb(bus->sdiodev,
863 SBSDIO_DEVICE_CTL, &err);
864 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
865 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
869 /* Otherwise, wait here (polling) for HT Avail */
871 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
872 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
873 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
874 SBSDIO_FUNC1_CHIPCLKCSR,
876 if (time_after(jiffies, timeout))
879 usleep_range(5000, 10000);
882 brcmf_err("HT Avail request error: %d\n", err);
885 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
886 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
887 PMU_MAX_TRANSITION_DLY, clkctl);
891 /* Mark clock available */
892 bus->clkstate = CLK_AVAIL;
893 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
896 if (!bus->alp_only) {
897 if (SBSDIO_ALPONLY(clkctl))
898 brcmf_err("HT Clock should be on\n");
900 #endif /* defined (DEBUG) */
905 if (bus->clkstate == CLK_PENDING) {
906 /* Cancel CA-only interrupt filter */
907 devctl = brcmf_sdiod_regrb(bus->sdiodev,
908 SBSDIO_DEVICE_CTL, &err);
909 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
910 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
914 bus->clkstate = CLK_SDONLY;
915 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
917 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
919 brcmf_err("Failed access turning clock off: %d\n",
927 /* Change idle/active SD state */
928 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
930 brcmf_dbg(SDIO, "Enter\n");
933 bus->clkstate = CLK_SDONLY;
935 bus->clkstate = CLK_NONE;
940 /* Transition SD and backplane clock readiness */
941 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
944 uint oldstate = bus->clkstate;
947 brcmf_dbg(SDIO, "Enter\n");
949 /* Early exit if we're already there */
950 if (bus->clkstate == target)
955 /* Make sure SD clock is available */
956 if (bus->clkstate == CLK_NONE)
957 brcmf_sdio_sdclk(bus, true);
958 /* Now request HT Avail on the backplane */
959 brcmf_sdio_htclk(bus, true, pendok);
963 /* Remove HT request, or bring up SD clock */
964 if (bus->clkstate == CLK_NONE)
965 brcmf_sdio_sdclk(bus, true);
966 else if (bus->clkstate == CLK_AVAIL)
967 brcmf_sdio_htclk(bus, false, false);
969 brcmf_err("request for %d -> %d\n",
970 bus->clkstate, target);
974 /* Make sure to remove HT request */
975 if (bus->clkstate == CLK_AVAIL)
976 brcmf_sdio_htclk(bus, false, false);
977 /* Now remove the SD clock */
978 brcmf_sdio_sdclk(bus, false);
982 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
989 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
994 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
995 (sleep ? "SLEEP" : "WAKE"),
996 (bus->sleeping ? "SLEEP" : "WAKE"));
998 /* If SR is enabled control bus state with KSO */
999 if (bus->sr_enabled) {
1000 /* Done if we're already in the requested state */
1001 if (sleep == bus->sleeping)
1004 /* Going to sleep */
1006 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
1007 SBSDIO_FUNC1_CHIPCLKCSR,
1009 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
1010 brcmf_dbg(SDIO, "no clock, set ALP\n");
1011 brcmf_sdiod_regwb(bus->sdiodev,
1012 SBSDIO_FUNC1_CHIPCLKCSR,
1013 SBSDIO_ALP_AVAIL_REQ, &err);
1015 err = brcmf_sdio_kso_control(bus, false);
1017 err = brcmf_sdio_kso_control(bus, true);
1020 brcmf_err("error while changing bus sleep state %d\n",
1027 /* control clocks */
1029 if (!bus->sr_enabled)
1030 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1032 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1033 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
1035 bus->sleeping = sleep;
1036 brcmf_dbg(SDIO, "new state %s\n",
1037 (sleep ? "SLEEP" : "WAKE"));
1039 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1045 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1047 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1050 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1051 struct sdpcm_shared *sh)
1056 struct sdpcm_shared_le sh_le;
1059 sdio_claim_host(bus->sdiodev->func[1]);
1060 brcmf_sdio_bus_sleep(bus, false, false);
1063 * Read last word in socram to determine
1064 * address of sdpcm_shared structure
1066 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1067 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1068 shaddr -= bus->ci->srsize;
1069 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1075 * Check if addr is valid.
1076 * NVRAM length at the end of memory should have been overwritten.
1078 addr = le32_to_cpu(addr_le);
1079 if (!brcmf_sdio_valid_shared_address(addr)) {
1080 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1085 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1087 /* Read hndrte_shared structure */
1088 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1089 sizeof(struct sdpcm_shared_le));
1093 sdio_release_host(bus->sdiodev->func[1]);
1096 sh->flags = le32_to_cpu(sh_le.flags);
1097 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1098 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1099 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1100 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1101 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1102 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1104 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1105 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1106 SDPCM_SHARED_VERSION,
1107 sh->flags & SDPCM_SHARED_VERSION_MASK);
1113 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1115 sdio_release_host(bus->sdiodev->func[1]);
1119 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1121 struct sdpcm_shared sh;
1123 if (brcmf_sdio_readshared(bus, &sh) == 0)
1124 bus->console_addr = sh.console_addr;
1127 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1132 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1139 brcmf_dbg(SDIO, "Enter\n");
1141 /* Read mailbox data and ack that we did so */
1142 ret = r_sdreg32(bus, &hmb_data,
1143 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1146 w_sdreg32(bus, SMB_INT_ACK,
1147 offsetof(struct sdpcmd_regs, tosbmailbox));
1148 bus->sdcnt.f1regdata += 2;
1150 /* Dongle recomposed rx frames, accept them again */
1151 if (hmb_data & HMB_DATA_NAKHANDLED) {
1152 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1155 brcmf_err("unexpected NAKHANDLED!\n");
1157 bus->rxskip = false;
1158 intstatus |= I_HMB_FRAME_IND;
1162 * DEVREADY does not occur with gSPI.
1164 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1166 (hmb_data & HMB_DATA_VERSION_MASK) >>
1167 HMB_DATA_VERSION_SHIFT;
1168 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1169 brcmf_err("Version mismatch, dongle reports %d, "
1171 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1173 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1177 * Retrieve console state address now that firmware should have
1180 brcmf_sdio_get_console_addr(bus);
1184 * Flow Control has been moved into the RX headers and this out of band
1185 * method isn't used any more.
1186 * remaining backward compatible with older dongles.
1188 if (hmb_data & HMB_DATA_FC) {
1189 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1190 HMB_DATA_FCDATA_SHIFT;
1192 if (fcbits & ~bus->flowcontrol)
1193 bus->sdcnt.fc_xoff++;
1195 if (bus->flowcontrol & ~fcbits)
1196 bus->sdcnt.fc_xon++;
1198 bus->sdcnt.fc_rcvd++;
1199 bus->flowcontrol = fcbits;
1202 /* Shouldn't be any others */
1203 if (hmb_data & ~(HMB_DATA_DEVREADY |
1204 HMB_DATA_NAKHANDLED |
1207 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1208 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1214 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1221 brcmf_err("%sterminate frame%s\n",
1222 abort ? "abort command, " : "",
1223 rtx ? ", send NAK" : "");
1226 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1228 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1230 bus->sdcnt.f1regdata++;
1232 /* Wait until the packet has been flushed (device/FIFO stable) */
1233 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1234 hi = brcmf_sdiod_regrb(bus->sdiodev,
1235 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1236 lo = brcmf_sdiod_regrb(bus->sdiodev,
1237 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1238 bus->sdcnt.f1regdata += 2;
1240 if ((hi == 0) && (lo == 0))
1243 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1244 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1245 lastrbc, (hi << 8) + lo);
1247 lastrbc = (hi << 8) + lo;
1251 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1253 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1257 err = w_sdreg32(bus, SMB_NAK,
1258 offsetof(struct sdpcmd_regs, tosbmailbox));
1260 bus->sdcnt.f1regdata++;
1265 /* Clear partial in any case */
1266 bus->cur_read.len = 0;
1269 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1271 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1274 /* On failure, abort the command and terminate the frame */
1275 brcmf_err("sdio error, abort command and terminate frame\n");
1276 bus->sdcnt.tx_sderrs++;
1278 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1279 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1280 bus->sdcnt.f1regdata++;
1282 for (i = 0; i < 3; i++) {
1283 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1284 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1285 bus->sdcnt.f1regdata += 2;
1286 if ((hi == 0) && (lo == 0))
1291 /* return total length of buffer chain */
1292 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1298 skb_queue_walk(&bus->glom, p)
1303 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1305 struct sk_buff *cur, *next;
1307 skb_queue_walk_safe(&bus->glom, cur, next) {
1308 skb_unlink(cur, &bus->glom);
1309 brcmu_pkt_buf_free_skb(cur);
1314 * brcmfmac sdio bus specific header
1315 * This is the lowest layer header wrapped on the packets transmitted between
1316 * host and WiFi dongle which contains information needed for SDIO core and
1319 * It consists of 3 parts: hardware header, hardware extension header and
1321 * hardware header (frame tag) - 4 bytes
1322 * Byte 0~1: Frame length
1323 * Byte 2~3: Checksum, bit-wise inverse of frame length
1324 * hardware extension header - 8 bytes
1325 * Tx glom mode only, N/A for Rx or normal Tx
1326 * Byte 0~1: Packet length excluding hw frame tag
1328 * Byte 3: Frame flags, bit 0: last frame indication
1329 * Byte 4~5: Reserved
1330 * Byte 6~7: Tail padding length
1331 * software header - 8 bytes
1332 * Byte 0: Rx/Tx sequence number
1333 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1334 * Byte 2: Length of next data frame, reserved for Tx
1335 * Byte 3: Data offset
1336 * Byte 4: Flow control bits, reserved for Tx
1337 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1338 * Byte 6~7: Reserved
1340 #define SDPCM_HWHDR_LEN 4
1341 #define SDPCM_HWEXT_LEN 8
1342 #define SDPCM_SWHDR_LEN 8
1343 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1344 /* software header */
1345 #define SDPCM_SEQ_MASK 0x000000ff
1346 #define SDPCM_SEQ_WRAP 256
1347 #define SDPCM_CHANNEL_MASK 0x00000f00
1348 #define SDPCM_CHANNEL_SHIFT 8
1349 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1350 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1351 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1352 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1353 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1354 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1355 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1356 #define SDPCM_NEXTLEN_SHIFT 16
1357 #define SDPCM_DOFFSET_MASK 0xff000000
1358 #define SDPCM_DOFFSET_SHIFT 24
1359 #define SDPCM_FCMASK_MASK 0x000000ff
1360 #define SDPCM_WINDOW_MASK 0x0000ff00
1361 #define SDPCM_WINDOW_SHIFT 8
1363 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1366 hdrvalue = *(u32 *)swheader;
1367 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1370 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1375 hdrvalue = *(u32 *)swheader;
1376 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1378 return (ret == SDPCM_EVENT_CHANNEL);
1381 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1382 struct brcmf_sdio_hdrinfo *rd,
1383 enum brcmf_sdio_frmtype type)
1386 u8 rx_seq, fc, tx_seq_max;
1389 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1392 len = get_unaligned_le16(header);
1393 checksum = get_unaligned_le16(header + sizeof(u16));
1394 /* All zero means no more to read */
1395 if (!(len | checksum)) {
1396 bus->rxpending = false;
1399 if ((u16)(~(len ^ checksum))) {
1400 brcmf_err("HW header checksum error\n");
1401 bus->sdcnt.rx_badhdr++;
1402 brcmf_sdio_rxfail(bus, false, false);
1405 if (len < SDPCM_HDRLEN) {
1406 brcmf_err("HW header length error\n");
1409 if (type == BRCMF_SDIO_FT_SUPER &&
1410 (roundup(len, bus->blocksize) != rd->len)) {
1411 brcmf_err("HW superframe header length error\n");
1414 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1415 brcmf_err("HW subframe header length error\n");
1420 /* software header */
1421 header += SDPCM_HWHDR_LEN;
1422 swheader = le32_to_cpu(*(__le32 *)header);
1423 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1424 brcmf_err("Glom descriptor found in superframe head\n");
1428 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1429 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1430 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1431 type != BRCMF_SDIO_FT_SUPER) {
1432 brcmf_err("HW header length too long\n");
1433 bus->sdcnt.rx_toolong++;
1434 brcmf_sdio_rxfail(bus, false, false);
1438 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1439 brcmf_err("Wrong channel for superframe\n");
1443 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1444 rd->channel != SDPCM_EVENT_CHANNEL) {
1445 brcmf_err("Wrong channel for subframe\n");
1449 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1450 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1451 brcmf_err("seq %d: bad data offset\n", rx_seq);
1452 bus->sdcnt.rx_badhdr++;
1453 brcmf_sdio_rxfail(bus, false, false);
1457 if (rd->seq_num != rx_seq) {
1458 brcmf_err("seq %d: sequence number error, expect %d\n",
1459 rx_seq, rd->seq_num);
1460 bus->sdcnt.rx_badseq++;
1461 rd->seq_num = rx_seq;
1463 /* no need to check the reset for subframe */
1464 if (type == BRCMF_SDIO_FT_SUB)
1466 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1467 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1468 /* only warm for NON glom packet */
1469 if (rd->channel != SDPCM_GLOM_CHANNEL)
1470 brcmf_err("seq %d: next length error\n", rx_seq);
1473 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1474 fc = swheader & SDPCM_FCMASK_MASK;
1475 if (bus->flowcontrol != fc) {
1476 if (~bus->flowcontrol & fc)
1477 bus->sdcnt.fc_xoff++;
1478 if (bus->flowcontrol & ~fc)
1479 bus->sdcnt.fc_xon++;
1480 bus->sdcnt.fc_rcvd++;
1481 bus->flowcontrol = fc;
1483 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1484 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1485 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1486 tx_seq_max = bus->tx_seq + 2;
1488 bus->tx_max = tx_seq_max;
1493 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1495 *(__le16 *)header = cpu_to_le16(frm_length);
1496 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1499 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1500 struct brcmf_sdio_hdrinfo *hd_info)
1505 brcmf_sdio_update_hwhdr(header, hd_info->len);
1506 hdr_offset = SDPCM_HWHDR_LEN;
1509 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1510 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1511 hdrval = (u16)hd_info->tail_pad << 16;
1512 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1513 hdr_offset += SDPCM_HWEXT_LEN;
1516 hdrval = hd_info->seq_num;
1517 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1519 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1521 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1522 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1523 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1526 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1531 struct sk_buff *pfirst, *pnext;
1536 struct brcmf_sdio_hdrinfo rd_new;
1538 /* If packets, issue read(s) and send up packet chain */
1539 /* Return sequence numbers consumed? */
1541 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1542 bus->glomd, skb_peek(&bus->glom));
1544 /* If there's a descriptor, generate the packet chain */
1546 pfirst = pnext = NULL;
1547 dlen = (u16) (bus->glomd->len);
1548 dptr = bus->glomd->data;
1549 if (!dlen || (dlen & 1)) {
1550 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1555 for (totlen = num = 0; dlen; num++) {
1556 /* Get (and move past) next length */
1557 sublen = get_unaligned_le16(dptr);
1558 dlen -= sizeof(u16);
1559 dptr += sizeof(u16);
1560 if ((sublen < SDPCM_HDRLEN) ||
1561 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1562 brcmf_err("descriptor len %d bad: %d\n",
1567 if (sublen % bus->sgentry_align) {
1568 brcmf_err("sublen %d not multiple of %d\n",
1569 sublen, bus->sgentry_align);
1573 /* For last frame, adjust read len so total
1574 is a block multiple */
1577 (roundup(totlen, bus->blocksize) - totlen);
1578 totlen = roundup(totlen, bus->blocksize);
1581 /* Allocate/chain packet for next subframe */
1582 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1583 if (pnext == NULL) {
1584 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1588 skb_queue_tail(&bus->glom, pnext);
1590 /* Adhere to start alignment requirements */
1591 pkt_align(pnext, sublen, bus->sgentry_align);
1594 /* If all allocations succeeded, save packet chain
1597 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1599 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1600 totlen != bus->cur_read.len) {
1601 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1602 bus->cur_read.len, totlen, rxseq);
1604 pfirst = pnext = NULL;
1606 brcmf_sdio_free_glom(bus);
1610 /* Done with descriptor packet */
1611 brcmu_pkt_buf_free_skb(bus->glomd);
1613 bus->cur_read.len = 0;
1616 /* Ok -- either we just generated a packet chain,
1617 or had one from before */
1618 if (!skb_queue_empty(&bus->glom)) {
1619 if (BRCMF_GLOM_ON()) {
1620 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1621 skb_queue_walk(&bus->glom, pnext) {
1622 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1623 pnext, (u8 *) (pnext->data),
1624 pnext->len, pnext->len);
1628 pfirst = skb_peek(&bus->glom);
1629 dlen = (u16) brcmf_sdio_glom_len(bus);
1631 /* Do an SDIO read for the superframe. Configurable iovar to
1632 * read directly into the chained packet, or allocate a large
1633 * packet and and copy into the chain.
1635 sdio_claim_host(bus->sdiodev->func[1]);
1636 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1638 sdio_release_host(bus->sdiodev->func[1]);
1639 bus->sdcnt.f2rxdata++;
1641 /* On failure, kill the superframe, allow a couple retries */
1643 brcmf_err("glom read of %d bytes failed: %d\n",
1646 sdio_claim_host(bus->sdiodev->func[1]);
1647 if (bus->glomerr++ < 3) {
1648 brcmf_sdio_rxfail(bus, true, true);
1651 brcmf_sdio_rxfail(bus, true, false);
1652 bus->sdcnt.rxglomfail++;
1653 brcmf_sdio_free_glom(bus);
1655 sdio_release_host(bus->sdiodev->func[1]);
1659 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1660 pfirst->data, min_t(int, pfirst->len, 48),
1663 rd_new.seq_num = rxseq;
1665 sdio_claim_host(bus->sdiodev->func[1]);
1666 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1667 BRCMF_SDIO_FT_SUPER);
1668 sdio_release_host(bus->sdiodev->func[1]);
1669 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1671 /* Remove superframe header, remember offset */
1672 skb_pull(pfirst, rd_new.dat_offset);
1673 sfdoff = rd_new.dat_offset;
1676 /* Validate all the subframe headers */
1677 skb_queue_walk(&bus->glom, pnext) {
1678 /* leave when invalid subframe is found */
1682 rd_new.len = pnext->len;
1683 rd_new.seq_num = rxseq++;
1684 sdio_claim_host(bus->sdiodev->func[1]);
1685 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1687 sdio_release_host(bus->sdiodev->func[1]);
1688 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1689 pnext->data, 32, "subframe:\n");
1695 /* Terminate frame on error, request
1697 sdio_claim_host(bus->sdiodev->func[1]);
1698 if (bus->glomerr++ < 3) {
1699 /* Restore superframe header space */
1700 skb_push(pfirst, sfdoff);
1701 brcmf_sdio_rxfail(bus, true, true);
1704 brcmf_sdio_rxfail(bus, true, false);
1705 bus->sdcnt.rxglomfail++;
1706 brcmf_sdio_free_glom(bus);
1708 sdio_release_host(bus->sdiodev->func[1]);
1709 bus->cur_read.len = 0;
1713 /* Basic SD framing looks ok - process each packet (header) */
1715 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1716 dptr = (u8 *) (pfirst->data);
1717 sublen = get_unaligned_le16(dptr);
1718 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1720 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1722 "Rx Subframe Data:\n");
1724 __skb_trim(pfirst, sublen);
1725 skb_pull(pfirst, doff);
1727 if (pfirst->len == 0) {
1728 skb_unlink(pfirst, &bus->glom);
1729 brcmu_pkt_buf_free_skb(pfirst);
1733 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1735 min_t(int, pfirst->len, 32),
1736 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1737 bus->glom.qlen, pfirst, pfirst->data,
1738 pfirst->len, pfirst->next,
1740 skb_unlink(pfirst, &bus->glom);
1741 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1742 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1744 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1746 bus->sdcnt.rxglompkts++;
1749 bus->sdcnt.rxglomframes++;
1754 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1757 DECLARE_WAITQUEUE(wait, current);
1758 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1760 /* Wait until control frame is available */
1761 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1762 set_current_state(TASK_INTERRUPTIBLE);
1764 while (!(*condition) && (!signal_pending(current) && timeout))
1765 timeout = schedule_timeout(timeout);
1767 if (signal_pending(current))
1770 set_current_state(TASK_RUNNING);
1771 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1776 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1778 if (waitqueue_active(&bus->dcmd_resp_wait))
1779 wake_up_interruptible(&bus->dcmd_resp_wait);
1784 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1787 u8 *buf = NULL, *rbuf;
1790 brcmf_dbg(TRACE, "Enter\n");
1793 buf = vzalloc(bus->rxblen);
1798 pad = ((unsigned long)rbuf % bus->head_align);
1800 rbuf += (bus->head_align - pad);
1802 /* Copy the already-read portion over */
1803 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1804 if (len <= BRCMF_FIRSTREAD)
1807 /* Raise rdlen to next SDIO block to avoid tail command */
1808 rdlen = len - BRCMF_FIRSTREAD;
1809 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1810 pad = bus->blocksize - (rdlen % bus->blocksize);
1811 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1812 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1814 } else if (rdlen % bus->head_align) {
1815 rdlen += bus->head_align - (rdlen % bus->head_align);
1818 /* Drop if the read is too big or it exceeds our maximum */
1819 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1820 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1821 rdlen, bus->sdiodev->bus_if->maxctl);
1822 brcmf_sdio_rxfail(bus, false, false);
1826 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1827 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1828 len, len - doff, bus->sdiodev->bus_if->maxctl);
1829 bus->sdcnt.rx_toolong++;
1830 brcmf_sdio_rxfail(bus, false, false);
1834 /* Read remain of frame body */
1835 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1836 bus->sdcnt.f2rxdata++;
1838 /* Control frame failures need retransmission */
1840 brcmf_err("read %d control bytes failed: %d\n",
1842 bus->sdcnt.rxc_errors++;
1843 brcmf_sdio_rxfail(bus, true, true);
1846 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1850 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1851 buf, len, "RxCtrl:\n");
1853 /* Point to valid data and indicate its length */
1854 spin_lock_bh(&bus->rxctl_lock);
1856 brcmf_err("last control frame is being processed.\n");
1857 spin_unlock_bh(&bus->rxctl_lock);
1861 bus->rxctl = buf + doff;
1862 bus->rxctl_orig = buf;
1863 bus->rxlen = len - doff;
1864 spin_unlock_bh(&bus->rxctl_lock);
1867 /* Awake any waiters */
1868 brcmf_sdio_dcmd_resp_wake(bus);
1871 /* Pad read to blocksize for efficiency */
1872 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1874 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1875 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1876 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1877 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1879 } else if (*rdlen % bus->head_align) {
1880 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1884 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1886 struct sk_buff *pkt; /* Packet for event or data frames */
1887 u16 pad; /* Number of pad bytes to read */
1888 uint rxleft = 0; /* Remaining number of frames allowed */
1889 int ret; /* Return code from calls */
1890 uint rxcount = 0; /* Total frames read */
1891 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1894 brcmf_dbg(TRACE, "Enter\n");
1896 /* Not finished unless we encounter no more frames indication */
1897 bus->rxpending = true;
1899 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1900 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1901 rd->seq_num++, rxleft--) {
1903 /* Handle glomming separately */
1904 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1906 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1907 bus->glomd, skb_peek(&bus->glom));
1908 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1909 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1910 rd->seq_num += cnt - 1;
1911 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1915 rd->len_left = rd->len;
1916 /* read header first for unknow frame length */
1917 sdio_claim_host(bus->sdiodev->func[1]);
1919 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1920 bus->rxhdr, BRCMF_FIRSTREAD);
1921 bus->sdcnt.f2rxhdrs++;
1923 brcmf_err("RXHEADER FAILED: %d\n",
1925 bus->sdcnt.rx_hdrfail++;
1926 brcmf_sdio_rxfail(bus, true, true);
1927 sdio_release_host(bus->sdiodev->func[1]);
1931 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1932 bus->rxhdr, SDPCM_HDRLEN,
1935 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1936 BRCMF_SDIO_FT_NORMAL)) {
1937 sdio_release_host(bus->sdiodev->func[1]);
1938 if (!bus->rxpending)
1944 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1945 brcmf_sdio_read_control(bus, bus->rxhdr,
1948 /* prepare the descriptor for the next read */
1949 rd->len = rd->len_nxtfrm << 4;
1951 /* treat all packet as event if we don't know */
1952 rd->channel = SDPCM_EVENT_CHANNEL;
1953 sdio_release_host(bus->sdiodev->func[1]);
1956 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1957 rd->len - BRCMF_FIRSTREAD : 0;
1958 head_read = BRCMF_FIRSTREAD;
1961 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1963 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1966 /* Give up on data, request rtx of events */
1967 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1968 brcmf_sdio_rxfail(bus, false,
1969 RETRYCHAN(rd->channel));
1970 sdio_release_host(bus->sdiodev->func[1]);
1973 skb_pull(pkt, head_read);
1974 pkt_align(pkt, rd->len_left, bus->head_align);
1976 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1977 bus->sdcnt.f2rxdata++;
1978 sdio_release_host(bus->sdiodev->func[1]);
1981 brcmf_err("read %d bytes from channel %d failed: %d\n",
1982 rd->len, rd->channel, ret);
1983 brcmu_pkt_buf_free_skb(pkt);
1984 sdio_claim_host(bus->sdiodev->func[1]);
1985 brcmf_sdio_rxfail(bus, true,
1986 RETRYCHAN(rd->channel));
1987 sdio_release_host(bus->sdiodev->func[1]);
1992 skb_push(pkt, head_read);
1993 memcpy(pkt->data, bus->rxhdr, head_read);
1996 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1997 rd_new.seq_num = rd->seq_num;
1998 sdio_claim_host(bus->sdiodev->func[1]);
1999 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
2000 BRCMF_SDIO_FT_NORMAL)) {
2002 brcmu_pkt_buf_free_skb(pkt);
2005 bus->sdcnt.rx_readahead_cnt++;
2006 if (rd->len != roundup(rd_new.len, 16)) {
2007 brcmf_err("frame length mismatch:read %d, should be %d\n",
2009 roundup(rd_new.len, 16) >> 4);
2011 brcmf_sdio_rxfail(bus, true, true);
2012 sdio_release_host(bus->sdiodev->func[1]);
2013 brcmu_pkt_buf_free_skb(pkt);
2016 sdio_release_host(bus->sdiodev->func[1]);
2017 rd->len_nxtfrm = rd_new.len_nxtfrm;
2018 rd->channel = rd_new.channel;
2019 rd->dat_offset = rd_new.dat_offset;
2021 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2024 bus->rxhdr, SDPCM_HDRLEN,
2027 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2028 brcmf_err("readahead on control packet %d?\n",
2030 /* Force retry w/normal header read */
2032 sdio_claim_host(bus->sdiodev->func[1]);
2033 brcmf_sdio_rxfail(bus, false, true);
2034 sdio_release_host(bus->sdiodev->func[1]);
2035 brcmu_pkt_buf_free_skb(pkt);
2040 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2041 pkt->data, rd->len, "Rx Data:\n");
2043 /* Save superframe descriptor and allocate packet frame */
2044 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2045 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2046 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2048 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2051 __skb_trim(pkt, rd->len);
2052 skb_pull(pkt, SDPCM_HDRLEN);
2055 brcmf_err("%s: glom superframe w/o "
2056 "descriptor!\n", __func__);
2057 sdio_claim_host(bus->sdiodev->func[1]);
2058 brcmf_sdio_rxfail(bus, false, false);
2059 sdio_release_host(bus->sdiodev->func[1]);
2061 /* prepare the descriptor for the next read */
2062 rd->len = rd->len_nxtfrm << 4;
2064 /* treat all packet as event if we don't know */
2065 rd->channel = SDPCM_EVENT_CHANNEL;
2069 /* Fill in packet len and prio, deliver upward */
2070 __skb_trim(pkt, rd->len);
2071 skb_pull(pkt, rd->dat_offset);
2074 brcmu_pkt_buf_free_skb(pkt);
2075 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2076 brcmf_rx_event(bus->sdiodev->dev, pkt);
2078 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2081 /* prepare the descriptor for the next read */
2082 rd->len = rd->len_nxtfrm << 4;
2084 /* treat all packet as event if we don't know */
2085 rd->channel = SDPCM_EVENT_CHANNEL;
2088 rxcount = maxframes - rxleft;
2089 /* Message if we hit the limit */
2091 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2093 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2094 /* Back off rxseq if awaiting rtx, update rx_seq */
2097 bus->rx_seq = rd->seq_num;
2103 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2105 if (waitqueue_active(&bus->ctrl_wait))
2106 wake_up_interruptible(&bus->ctrl_wait);
2110 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2115 dat_buf = (u8 *)(pkt->data);
2117 /* Check head padding */
2118 head_pad = ((unsigned long)dat_buf % bus->head_align);
2120 if (skb_headroom(pkt) < head_pad) {
2121 bus->sdiodev->bus_if->tx_realloc++;
2123 if (skb_cow(pkt, head_pad))
2126 skb_push(pkt, head_pad);
2127 dat_buf = (u8 *)(pkt->data);
2128 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2134 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2137 /* flag marking a dummy skb added for DMA alignment requirement */
2138 #define ALIGN_SKB_FLAG 0x8000
2139 /* bit mask of data length chopped from the previous packet */
2140 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2142 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2143 struct sk_buff_head *pktq,
2144 struct sk_buff *pkt, u16 total_len)
2146 struct brcmf_sdio_dev *sdiodev;
2147 struct sk_buff *pkt_pad;
2148 u16 tail_pad, tail_chop, chain_pad;
2149 unsigned int blksize;
2153 sdiodev = bus->sdiodev;
2154 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2155 /* sg entry alignment should be a divisor of block size */
2156 WARN_ON(blksize % bus->sgentry_align);
2158 /* Check tail padding */
2159 lastfrm = skb_queue_is_last(pktq, pkt);
2161 tail_chop = pkt->len % bus->sgentry_align;
2163 tail_pad = bus->sgentry_align - tail_chop;
2164 chain_pad = (total_len + tail_pad) % blksize;
2165 if (lastfrm && chain_pad)
2166 tail_pad += blksize - chain_pad;
2167 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2168 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2170 if (pkt_pad == NULL)
2172 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2173 if (unlikely(ret < 0)) {
2177 memcpy(pkt_pad->data,
2178 pkt->data + pkt->len - tail_chop,
2180 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2181 skb_trim(pkt, pkt->len - tail_chop);
2182 skb_trim(pkt_pad, tail_pad + tail_chop);
2183 __skb_queue_after(pktq, pkt, pkt_pad);
2185 ntail = pkt->data_len + tail_pad -
2186 (pkt->end - pkt->tail);
2187 if (skb_cloned(pkt) || ntail > 0)
2188 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2190 if (skb_linearize(pkt))
2192 __skb_put(pkt, tail_pad);
2199 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2200 * @bus: brcmf_sdio structure pointer
2201 * @pktq: packet list pointer
2202 * @chan: virtual channel to transmit the packet
2204 * Processes to be applied to the packet
2205 * - Align data buffer pointer
2206 * - Align data buffer length
2208 * Return: negative value if there is error
2211 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2214 u16 head_pad, total_len;
2215 struct sk_buff *pkt_next;
2218 struct brcmf_sdio_hdrinfo hd_info = {0};
2220 txseq = bus->tx_seq;
2222 skb_queue_walk(pktq, pkt_next) {
2223 /* alignment packet inserted in previous
2224 * loop cycle can be skipped as it is
2225 * already properly aligned and does not
2226 * need an sdpcm header.
2228 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2231 /* align packet data pointer */
2232 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2235 head_pad = (u16)ret;
2237 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2239 total_len += pkt_next->len;
2241 hd_info.len = pkt_next->len;
2242 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2243 if (bus->txglom && pktq->qlen > 1) {
2244 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2245 pkt_next, total_len);
2248 hd_info.tail_pad = (u16)ret;
2249 total_len += (u16)ret;
2252 hd_info.channel = chan;
2253 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2254 hd_info.seq_num = txseq++;
2256 /* Now fill the header */
2257 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2259 if (BRCMF_BYTES_ON() &&
2260 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2261 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2262 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2264 else if (BRCMF_HDRS_ON())
2265 brcmf_dbg_hex_dump(true, pkt_next->data,
2266 head_pad + bus->tx_hdrlen,
2269 /* Hardware length tag of the first packet should be total
2270 * length of the chain (including padding)
2273 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2278 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2279 * @bus: brcmf_sdio structure pointer
2280 * @pktq: packet list pointer
2282 * Processes to be applied to the packet
2283 * - Remove head padding
2284 * - Remove tail padding
2287 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2292 u16 dummy_flags, chop_len;
2293 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2295 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2296 dummy_flags = *(u16 *)(pkt_next->cb);
2297 if (dummy_flags & ALIGN_SKB_FLAG) {
2298 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2300 pkt_prev = pkt_next->prev;
2301 skb_put(pkt_prev, chop_len);
2303 __skb_unlink(pkt_next, pktq);
2304 brcmu_pkt_buf_free_skb(pkt_next);
2306 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2307 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2308 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2309 SDPCM_DOFFSET_SHIFT;
2310 skb_pull(pkt_next, dat_offset);
2312 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2313 skb_trim(pkt_next, pkt_next->len - tail_pad);
2319 /* Writes a HW/SW header into the packet and sends it. */
2320 /* Assumes: (a) header space already there, (b) caller holds lock */
2321 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2325 struct sk_buff *pkt_next, *tmp;
2327 brcmf_dbg(TRACE, "Enter\n");
2329 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2333 sdio_claim_host(bus->sdiodev->func[1]);
2334 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2335 bus->sdcnt.f2txdata++;
2338 brcmf_sdio_txfail(bus);
2340 sdio_release_host(bus->sdiodev->func[1]);
2343 brcmf_sdio_txpkt_postp(bus, pktq);
2345 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2346 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2347 __skb_unlink(pkt_next, pktq);
2348 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2353 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2355 struct sk_buff *pkt;
2356 struct sk_buff_head pktq;
2358 int ret = 0, prec_out, i;
2360 u8 tx_prec_map, pkt_num;
2362 brcmf_dbg(TRACE, "Enter\n");
2364 tx_prec_map = ~bus->flowcontrol;
2366 /* Send frames until the limit or some other event */
2367 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2370 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2371 bus->sdiodev->txglomsz);
2372 pkt_num = min_t(u32, pkt_num,
2373 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2374 __skb_queue_head_init(&pktq);
2375 spin_lock_bh(&bus->txq_lock);
2376 for (i = 0; i < pkt_num; i++) {
2377 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2381 __skb_queue_tail(&pktq, pkt);
2383 spin_unlock_bh(&bus->txq_lock);
2387 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2391 /* In poll mode, need to check for other events */
2393 /* Check device status, signal pending interrupt */
2394 sdio_claim_host(bus->sdiodev->func[1]);
2395 ret = r_sdreg32(bus, &intstatus,
2396 offsetof(struct sdpcmd_regs,
2398 sdio_release_host(bus->sdiodev->func[1]);
2399 bus->sdcnt.f2txdata++;
2402 if (intstatus & bus->hostintmask)
2403 atomic_set(&bus->ipend, 1);
2407 /* Deflow-control stack if needed */
2408 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2409 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2411 brcmf_txflowblock(bus->sdiodev->dev, false);
2417 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2422 struct brcmf_sdio_hdrinfo hd_info = {0};
2425 brcmf_dbg(TRACE, "Enter\n");
2427 /* Back the pointer to make room for bus header */
2428 frame -= bus->tx_hdrlen;
2429 len += bus->tx_hdrlen;
2431 /* Add alignment padding (optional for ctl frames) */
2432 doff = ((unsigned long)frame % bus->head_align);
2436 memset(frame + bus->tx_hdrlen, 0, doff);
2439 /* Round send length to next SDIO block */
2441 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2442 pad = bus->blocksize - (len % bus->blocksize);
2443 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2445 } else if (len % bus->head_align) {
2446 pad = bus->head_align - (len % bus->head_align);
2450 hd_info.len = len - pad;
2451 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2452 hd_info.dat_offset = doff + bus->tx_hdrlen;
2453 hd_info.seq_num = bus->tx_seq;
2454 hd_info.lastfrm = true;
2455 hd_info.tail_pad = pad;
2456 brcmf_sdio_hdpack(bus, frame, &hd_info);
2459 brcmf_sdio_update_hwhdr(frame, len);
2461 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2462 frame, len, "Tx Frame:\n");
2463 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2465 frame, min_t(u16, len, 16), "TxHdr:\n");
2468 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2471 brcmf_sdio_txfail(bus);
2473 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2474 } while (ret < 0 && retries++ < TXRETRIES);
2479 static void brcmf_sdio_bus_stop(struct device *dev)
2481 u32 local_hostintmask;
2484 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2485 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2486 struct brcmf_sdio *bus = sdiodev->bus;
2488 brcmf_dbg(TRACE, "Enter\n");
2490 if (bus->watchdog_tsk) {
2491 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2492 kthread_stop(bus->watchdog_tsk);
2493 bus->watchdog_tsk = NULL;
2496 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2497 sdio_claim_host(sdiodev->func[1]);
2499 /* Enable clock for device interrupts */
2500 brcmf_sdio_bus_sleep(bus, false, false);
2502 /* Disable and clear interrupts at the chip level also */
2503 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2504 local_hostintmask = bus->hostintmask;
2505 bus->hostintmask = 0;
2507 /* Force backplane clocks to assure F2 interrupt propagates */
2508 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2511 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2512 (saveclk | SBSDIO_FORCE_HT), &err);
2514 brcmf_err("Failed to force clock for F2: err %d\n",
2517 /* Turn off the bus (F2), free any pending packets */
2518 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2519 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2521 /* Clear any pending interrupts now that F2 is disabled */
2522 w_sdreg32(bus, local_hostintmask,
2523 offsetof(struct sdpcmd_regs, intstatus));
2525 sdio_release_host(sdiodev->func[1]);
2527 /* Clear the data packet queues */
2528 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2530 /* Clear any held glomming stuff */
2531 brcmu_pkt_buf_free_skb(bus->glomd);
2532 brcmf_sdio_free_glom(bus);
2534 /* Clear rx control and wake any waiters */
2535 spin_lock_bh(&bus->rxctl_lock);
2537 spin_unlock_bh(&bus->rxctl_lock);
2538 brcmf_sdio_dcmd_resp_wake(bus);
2540 /* Reset some F2 state stuff */
2541 bus->rxskip = false;
2542 bus->tx_seq = bus->rx_seq = 0;
2545 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2547 unsigned long flags;
2549 if (bus->sdiodev->oob_irq_requested) {
2550 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2551 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2552 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2553 bus->sdiodev->irq_en = true;
2555 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2559 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2561 struct brcmf_core *buscore;
2566 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2567 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2569 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2570 bus->sdcnt.f1regdata++;
2574 val &= bus->hostintmask;
2575 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2577 /* Clear interrupts */
2579 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2580 bus->sdcnt.f1regdata++;
2581 atomic_or(val, &bus->intstatus);
2587 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2590 unsigned long intstatus;
2591 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2592 uint framecnt; /* Temporary counter of tx/rx frames */
2595 brcmf_dbg(TRACE, "Enter\n");
2597 sdio_claim_host(bus->sdiodev->func[1]);
2599 /* If waiting for HTAVAIL, check status */
2600 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2601 u8 clkctl, devctl = 0;
2604 /* Check for inconsistent device control */
2605 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2606 SBSDIO_DEVICE_CTL, &err);
2609 /* Read CSR, if clock on switch to AVAIL, else ignore */
2610 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2611 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2613 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2616 if (SBSDIO_HTAV(clkctl)) {
2617 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2618 SBSDIO_DEVICE_CTL, &err);
2619 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2620 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2622 bus->clkstate = CLK_AVAIL;
2626 /* Make sure backplane clock is on */
2627 brcmf_sdio_bus_sleep(bus, false, true);
2629 /* Pending interrupt indicates new device status */
2630 if (atomic_read(&bus->ipend) > 0) {
2631 atomic_set(&bus->ipend, 0);
2632 err = brcmf_sdio_intr_rstatus(bus);
2635 /* Start with leftover status bits */
2636 intstatus = atomic_xchg(&bus->intstatus, 0);
2638 /* Handle flow-control change: read new state in case our ack
2639 * crossed another change interrupt. If change still set, assume
2640 * FC ON for safety, let next loop through do the debounce.
2642 if (intstatus & I_HMB_FC_CHANGE) {
2643 intstatus &= ~I_HMB_FC_CHANGE;
2644 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2645 offsetof(struct sdpcmd_regs, intstatus));
2647 err = r_sdreg32(bus, &newstatus,
2648 offsetof(struct sdpcmd_regs, intstatus));
2649 bus->sdcnt.f1regdata += 2;
2650 atomic_set(&bus->fcstate,
2651 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2652 intstatus |= (newstatus & bus->hostintmask);
2655 /* Handle host mailbox indication */
2656 if (intstatus & I_HMB_HOST_INT) {
2657 intstatus &= ~I_HMB_HOST_INT;
2658 intstatus |= brcmf_sdio_hostmail(bus);
2661 sdio_release_host(bus->sdiodev->func[1]);
2663 /* Generally don't ask for these, can get CRC errors... */
2664 if (intstatus & I_WR_OOSYNC) {
2665 brcmf_err("Dongle reports WR_OOSYNC\n");
2666 intstatus &= ~I_WR_OOSYNC;
2669 if (intstatus & I_RD_OOSYNC) {
2670 brcmf_err("Dongle reports RD_OOSYNC\n");
2671 intstatus &= ~I_RD_OOSYNC;
2674 if (intstatus & I_SBINT) {
2675 brcmf_err("Dongle reports SBINT\n");
2676 intstatus &= ~I_SBINT;
2679 /* Would be active due to wake-wlan in gSPI */
2680 if (intstatus & I_CHIPACTIVE) {
2681 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2682 intstatus &= ~I_CHIPACTIVE;
2685 /* Ignore frame indications if rxskip is set */
2687 intstatus &= ~I_HMB_FRAME_IND;
2689 /* On frame indication, read available frames */
2690 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2691 brcmf_sdio_readframes(bus, bus->rxbound);
2692 if (!bus->rxpending)
2693 intstatus &= ~I_HMB_FRAME_IND;
2696 /* Keep still-pending events for next scheduling */
2698 atomic_or(intstatus, &bus->intstatus);
2700 brcmf_sdio_clrintr(bus);
2702 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2704 sdio_claim_host(bus->sdiodev->func[1]);
2705 if (bus->ctrl_frame_stat) {
2706 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2707 bus->ctrl_frame_len);
2708 bus->ctrl_frame_err = err;
2710 bus->ctrl_frame_stat = false;
2712 sdio_release_host(bus->sdiodev->func[1]);
2713 brcmf_sdio_wait_event_wakeup(bus);
2715 /* Send queued frames (limit 1 if rx may still be pending) */
2716 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2717 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2719 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2721 brcmf_sdio_sendfromq(bus, framecnt);
2724 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2725 brcmf_err("failed backplane access over SDIO, halting operation\n");
2726 atomic_set(&bus->intstatus, 0);
2727 if (bus->ctrl_frame_stat) {
2728 sdio_claim_host(bus->sdiodev->func[1]);
2729 if (bus->ctrl_frame_stat) {
2730 bus->ctrl_frame_err = -ENODEV;
2732 bus->ctrl_frame_stat = false;
2733 brcmf_sdio_wait_event_wakeup(bus);
2735 sdio_release_host(bus->sdiodev->func[1]);
2737 } else if (atomic_read(&bus->intstatus) ||
2738 atomic_read(&bus->ipend) > 0 ||
2739 (!atomic_read(&bus->fcstate) &&
2740 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2742 bus->dpc_triggered = true;
2746 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2748 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2749 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2750 struct brcmf_sdio *bus = sdiodev->bus;
2755 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2758 int eprec = -1; /* precedence to evict from */
2760 /* Fast case, precedence queue is not full and we are also not
2761 * exceeding total queue length
2763 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2764 brcmu_pktq_penq(q, prec, pkt);
2768 /* Determine precedence from which to evict packet, if any */
2769 if (pktq_pfull(q, prec)) {
2771 } else if (pktq_full(q)) {
2772 p = brcmu_pktq_peek_tail(q, &eprec);
2777 /* Evict if needed */
2779 /* Detect queueing to unconfigured precedence */
2781 return false; /* refuse newer (incoming) packet */
2782 /* Evict packet according to discard policy */
2783 p = brcmu_pktq_pdeq_tail(q, eprec);
2785 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2786 brcmu_pkt_buf_free_skb(p);
2790 p = brcmu_pktq_penq(q, prec, pkt);
2792 brcmf_err("brcmu_pktq_penq() failed\n");
2797 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2801 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2802 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2803 struct brcmf_sdio *bus = sdiodev->bus;
2805 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2806 if (sdiodev->state != BRCMF_SDIOD_DATA)
2809 /* Add space for the header */
2810 skb_push(pkt, bus->tx_hdrlen);
2811 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2813 prec = prio2prec((pkt->priority & PRIOMASK));
2815 /* Check for existing queue, current flow-control,
2816 pending event, or pending clock */
2817 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2818 bus->sdcnt.fcqueued++;
2820 /* Priority based enq */
2821 spin_lock_bh(&bus->txq_lock);
2822 /* reset bus_flags in packet cb */
2823 *(u16 *)(pkt->cb) = 0;
2824 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2825 skb_pull(pkt, bus->tx_hdrlen);
2826 brcmf_err("out of bus->txq !!!\n");
2832 if (pktq_len(&bus->txq) >= TXHI) {
2834 brcmf_txflowblock(dev, true);
2836 spin_unlock_bh(&bus->txq_lock);
2839 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2840 qcount[prec] = pktq_plen(&bus->txq, prec);
2843 brcmf_sdio_trigger_dpc(bus);
2848 #define CONSOLE_LINE_MAX 192
2850 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2852 struct brcmf_console *c = &bus->console;
2853 u8 line[CONSOLE_LINE_MAX], ch;
2857 /* Don't do anything until FWREADY updates console address */
2858 if (bus->console_addr == 0)
2861 /* Read console log struct */
2862 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2863 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2868 /* Allocate console buffer (one time only) */
2869 if (c->buf == NULL) {
2870 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2871 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2876 idx = le32_to_cpu(c->log_le.idx);
2878 /* Protect against corrupt value */
2879 if (idx > c->bufsize)
2882 /* Skip reading the console buffer if the index pointer
2887 /* Read the console buffer */
2888 addr = le32_to_cpu(c->log_le.buf);
2889 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2893 while (c->last != idx) {
2894 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2895 if (c->last == idx) {
2896 /* This would output a partial line.
2898 * the buffer pointer and output this
2899 * line next time around.
2904 c->last = c->bufsize - n;
2907 ch = c->buf[c->last];
2908 c->last = (c->last + 1) % c->bufsize;
2915 if (line[n - 1] == '\r')
2918 pr_debug("CONSOLE: %s\n", line);
2928 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2930 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2931 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2932 struct brcmf_sdio *bus = sdiodev->bus;
2935 brcmf_dbg(TRACE, "Enter\n");
2936 if (sdiodev->state != BRCMF_SDIOD_DATA)
2940 bus->ctrl_frame_buf = msg;
2941 bus->ctrl_frame_len = msglen;
2943 bus->ctrl_frame_stat = true;
2945 brcmf_sdio_trigger_dpc(bus);
2946 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2947 msecs_to_jiffies(CTL_DONE_TIMEOUT));
2949 if (bus->ctrl_frame_stat) {
2950 sdio_claim_host(bus->sdiodev->func[1]);
2951 if (bus->ctrl_frame_stat) {
2952 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2953 bus->ctrl_frame_stat = false;
2956 sdio_release_host(bus->sdiodev->func[1]);
2959 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2960 bus->ctrl_frame_err);
2962 ret = bus->ctrl_frame_err;
2966 bus->sdcnt.tx_ctlerrs++;
2968 bus->sdcnt.tx_ctlpkts++;
2974 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2975 struct sdpcm_shared *sh)
2977 u32 addr, console_ptr, console_size, console_index;
2978 char *conbuf = NULL;
2982 /* obtain console information from device memory */
2983 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2984 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2985 (u8 *)&sh_val, sizeof(u32));
2988 console_ptr = le32_to_cpu(sh_val);
2990 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2991 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2992 (u8 *)&sh_val, sizeof(u32));
2995 console_size = le32_to_cpu(sh_val);
2997 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2998 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2999 (u8 *)&sh_val, sizeof(u32));
3002 console_index = le32_to_cpu(sh_val);
3004 /* allocate buffer for console data */
3005 if (console_size <= CONSOLE_BUFFER_MAX)
3006 conbuf = vzalloc(console_size+1);
3011 /* obtain the console data from device */
3012 conbuf[console_size] = '\0';
3013 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3018 rv = seq_write(seq, conbuf + console_index,
3019 console_size - console_index);
3023 if (console_index > 0)
3024 rv = seq_write(seq, conbuf, console_index - 1);
3031 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3032 struct sdpcm_shared *sh)
3035 struct brcmf_trap_info tr;
3037 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3038 brcmf_dbg(INFO, "no trap in firmware\n");
3042 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3043 sizeof(struct brcmf_trap_info));
3048 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3049 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3050 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3051 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3052 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3053 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3054 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3055 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3056 le32_to_cpu(tr.pc), sh->trap_addr,
3057 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3058 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3059 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3060 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3065 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3066 struct sdpcm_shared *sh)
3069 char file[80] = "?";
3070 char expr[80] = "<???>";
3072 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3073 brcmf_dbg(INFO, "firmware not built with -assert\n");
3075 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3076 brcmf_dbg(INFO, "no assert in dongle\n");
3080 sdio_claim_host(bus->sdiodev->func[1]);
3081 if (sh->assert_file_addr != 0) {
3082 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3083 sh->assert_file_addr, (u8 *)file, 80);
3087 if (sh->assert_exp_addr != 0) {
3088 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3089 sh->assert_exp_addr, (u8 *)expr, 80);
3093 sdio_release_host(bus->sdiodev->func[1]);
3095 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3096 file, sh->assert_line, expr);
3100 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3103 struct sdpcm_shared sh;
3105 error = brcmf_sdio_readshared(bus, &sh);
3110 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3111 brcmf_dbg(INFO, "firmware not built with -assert\n");
3112 else if (sh.flags & SDPCM_SHARED_ASSERT)
3113 brcmf_err("assertion in dongle\n");
3115 if (sh.flags & SDPCM_SHARED_TRAP)
3116 brcmf_err("firmware trap in dongle\n");
3121 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3124 struct sdpcm_shared sh;
3126 error = brcmf_sdio_readshared(bus, &sh);
3130 error = brcmf_sdio_assert_info(seq, bus, &sh);
3134 error = brcmf_sdio_trap_info(seq, bus, &sh);
3138 error = brcmf_sdio_dump_console(seq, bus, &sh);
3144 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3146 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3147 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3149 return brcmf_sdio_died_dump(seq, bus);
3152 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3154 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3155 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3156 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3159 "intrcount: %u\nlastintrs: %u\n"
3160 "pollcnt: %u\nregfails: %u\n"
3161 "tx_sderrs: %u\nfcqueued: %u\n"
3162 "rxrtx: %u\nrx_toolong: %u\n"
3163 "rxc_errors: %u\nrx_hdrfail: %u\n"
3164 "rx_badhdr: %u\nrx_badseq: %u\n"
3165 "fc_rcvd: %u\nfc_xoff: %u\n"
3166 "fc_xon: %u\nrxglomfail: %u\n"
3167 "rxglomframes: %u\nrxglompkts: %u\n"
3168 "f2rxhdrs: %u\nf2rxdata: %u\n"
3169 "f2txdata: %u\nf1regdata: %u\n"
3170 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3171 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3172 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3173 sdcnt->intrcount, sdcnt->lastintrs,
3174 sdcnt->pollcnt, sdcnt->regfails,
3175 sdcnt->tx_sderrs, sdcnt->fcqueued,
3176 sdcnt->rxrtx, sdcnt->rx_toolong,
3177 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3178 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3179 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3180 sdcnt->fc_xon, sdcnt->rxglomfail,
3181 sdcnt->rxglomframes, sdcnt->rxglompkts,
3182 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3183 sdcnt->f2txdata, sdcnt->f1regdata,
3184 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3185 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3186 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3191 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3193 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3194 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3196 if (IS_ERR_OR_NULL(dentry))
3199 bus->console_interval = BRCMF_CONSOLE;
3201 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3202 brcmf_debugfs_add_entry(drvr, "counters",
3203 brcmf_debugfs_sdio_count_read);
3204 debugfs_create_u32("console_interval", 0644, dentry,
3205 &bus->console_interval);
3208 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3213 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3219 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3225 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3226 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3227 struct brcmf_sdio *bus = sdiodev->bus;
3229 brcmf_dbg(TRACE, "Enter\n");
3230 if (sdiodev->state != BRCMF_SDIOD_DATA)
3233 /* Wait until control frame is available */
3234 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3236 spin_lock_bh(&bus->rxctl_lock);
3238 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3240 buf = bus->rxctl_orig;
3241 bus->rxctl_orig = NULL;
3243 spin_unlock_bh(&bus->rxctl_lock);
3247 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3249 } else if (timeleft == 0) {
3250 brcmf_err("resumed on timeout\n");
3251 brcmf_sdio_checkdied(bus);
3252 } else if (pending) {
3253 brcmf_dbg(CTL, "cancelled\n");
3254 return -ERESTARTSYS;
3256 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3257 brcmf_sdio_checkdied(bus);
3261 bus->sdcnt.rx_ctlpkts++;
3263 bus->sdcnt.rx_ctlerrs++;
3265 return rxlen ? (int)rxlen : -ETIMEDOUT;
3270 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3271 u8 *ram_data, uint ram_sz)
3280 /* read back and verify */
3281 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3283 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3284 /* do not proceed while no memory but */
3290 while (offset < ram_sz) {
3291 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3293 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3295 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3299 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3300 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3315 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3316 u8 *ram_data, uint ram_sz)
3322 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3323 const struct firmware *fw)
3327 brcmf_dbg(TRACE, "Enter\n");
3329 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3330 (u8 *)fw->data, fw->size);
3332 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3333 err, (int)fw->size, bus->ci->rambase);
3334 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3335 (u8 *)fw->data, fw->size))
3341 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3342 void *vars, u32 varsz)
3347 brcmf_dbg(TRACE, "Enter\n");
3349 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3350 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3352 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3353 err, varsz, address);
3354 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3360 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3361 const struct firmware *fw,
3362 void *nvram, u32 nvlen)
3364 int bcmerror = -EFAULT;
3367 sdio_claim_host(bus->sdiodev->func[1]);
3368 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3370 rstvec = get_unaligned_le32(fw->data);
3371 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3373 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3374 release_firmware(fw);
3376 brcmf_err("dongle image file download failed\n");
3377 brcmf_fw_nvram_free(nvram);
3381 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3382 brcmf_fw_nvram_free(nvram);
3384 brcmf_err("dongle nvram file download failed\n");
3388 /* Take arm out of reset */
3389 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3390 brcmf_err("error getting out of ARM core reset\n");
3394 /* Allow full data communication using DPC from now on. */
3395 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3399 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3400 sdio_release_host(bus->sdiodev->func[1]);
3404 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3409 brcmf_dbg(TRACE, "Enter\n");
3411 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3413 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3417 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3418 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3420 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3424 /* Add CMD14 Support */
3425 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3426 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3427 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3430 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3434 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3435 SBSDIO_FORCE_HT, &err);
3437 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3442 bus->sr_enabled = true;
3443 brcmf_dbg(INFO, "SR enabled\n");
3446 /* enable KSO bit */
3447 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3452 brcmf_dbg(TRACE, "Enter\n");
3454 /* KSO bit added in SDIO core rev 12 */
3455 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3458 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3460 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3464 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3465 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3466 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3467 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3470 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3479 static int brcmf_sdio_bus_preinit(struct device *dev)
3481 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3482 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3483 struct brcmf_sdio *bus = sdiodev->bus;
3488 /* the commands below use the terms tx and rx from
3489 * a device perspective, ie. bus:txglom affects the
3490 * bus transfers from device to host.
3492 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3493 /* for sdio core rev < 12, disable txgloming */
3495 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3498 /* otherwise, set txglomalign */
3501 value = sdiodev->pdata->sd_sgentry_align;
3502 /* SDIO ADMA requires at least 32 bit alignment */
3503 value = max_t(u32, value, 4);
3504 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3511 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3512 if (sdiodev->sg_support) {
3513 bus->txglom = false;
3515 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3516 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3517 &value, sizeof(u32));
3519 /* bus:rxglom is allowed to fail */
3523 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3526 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3532 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3534 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3535 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3536 struct brcmf_sdio *bus = sdiodev->bus;
3538 return bus->ci->ramsize - bus->ci->srsize;
3541 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3544 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3545 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3546 struct brcmf_sdio *bus = sdiodev->bus;
3552 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3555 address = bus->ci->rambase;
3557 sdio_claim_host(sdiodev->func[1]);
3558 while (offset < mem_size) {
3559 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3561 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3563 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3573 sdio_release_host(sdiodev->func[1]);
3577 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3579 if (!bus->dpc_triggered) {
3580 bus->dpc_triggered = true;
3581 queue_work(bus->brcmf_wq, &bus->datawork);
3585 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3587 brcmf_dbg(TRACE, "Enter\n");
3590 brcmf_err("bus is null pointer, exiting\n");
3594 /* Count the interrupt call */
3595 bus->sdcnt.intrcount++;
3597 atomic_set(&bus->ipend, 1);
3599 if (brcmf_sdio_intr_rstatus(bus)) {
3600 brcmf_err("failed backplane access\n");
3603 /* Disable additional interrupts (is this needed now)? */
3605 brcmf_err("isr w/o interrupt configured!\n");
3607 bus->dpc_triggered = true;
3608 queue_work(bus->brcmf_wq, &bus->datawork);
3611 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3613 brcmf_dbg(TIMER, "Enter\n");
3615 /* Poll period: check device if appropriate. */
3616 if (!bus->sr_enabled &&
3617 bus->poll && (++bus->polltick >= bus->pollrate)) {
3620 /* Reset poll tick */
3623 /* Check device if no interrupts */
3625 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3627 if (!bus->dpc_triggered) {
3630 sdio_claim_host(bus->sdiodev->func[1]);
3631 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3634 sdio_release_host(bus->sdiodev->func[1]);
3635 intstatus = devpend & (INTR_STATUS_FUNC1 |
3639 /* If there is something, make like the ISR and
3642 bus->sdcnt.pollcnt++;
3643 atomic_set(&bus->ipend, 1);
3645 bus->dpc_triggered = true;
3646 queue_work(bus->brcmf_wq, &bus->datawork);
3650 /* Update interrupt tracking */
3651 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3654 /* Poll for console output periodically */
3655 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3656 bus->console_interval != 0) {
3657 bus->console.count += BRCMF_WD_POLL_MS;
3658 if (bus->console.count >= bus->console_interval) {
3659 bus->console.count -= bus->console_interval;
3660 sdio_claim_host(bus->sdiodev->func[1]);
3661 /* Make sure backplane clock is on */
3662 brcmf_sdio_bus_sleep(bus, false, false);
3663 if (brcmf_sdio_readconsole(bus) < 0)
3665 bus->console_interval = 0;
3666 sdio_release_host(bus->sdiodev->func[1]);
3671 /* On idle timeout clear activity flag and/or turn off clock */
3672 if (!bus->dpc_triggered) {
3674 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3675 (bus->clkstate == CLK_AVAIL)) {
3677 if (bus->idlecount > bus->idletime) {
3678 brcmf_dbg(SDIO, "idle\n");
3679 sdio_claim_host(bus->sdiodev->func[1]);
3680 brcmf_sdio_wd_timer(bus, 0);
3682 brcmf_sdio_bus_sleep(bus, true, false);
3683 sdio_release_host(bus->sdiodev->func[1]);
3693 static void brcmf_sdio_dataworker(struct work_struct *work)
3695 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3698 bus->dpc_running = true;
3700 while (ACCESS_ONCE(bus->dpc_triggered)) {
3701 bus->dpc_triggered = false;
3702 brcmf_sdio_dpc(bus);
3705 bus->dpc_running = false;
3706 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3707 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3708 brcmf_sdiod_try_freeze(bus->sdiodev);
3709 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3714 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3715 struct brcmf_chip *ci, u32 drivestrength)
3717 const struct sdiod_drive_str *str_tab = NULL;
3722 u32 drivestrength_sel = 0;
3726 if (!(ci->cc_caps & CC_CAP_PMU))
3729 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3730 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3731 str_tab = sdiod_drvstr_tab1_1v8;
3732 str_mask = 0x00003800;
3735 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3736 str_tab = sdiod_drvstr_tab6_1v8;
3737 str_mask = 0x00001800;
3740 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3741 /* note: 43143 does not support tristate */
3742 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3743 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3744 str_tab = sdiod_drvstr_tab2_3v3;
3745 str_mask = 0x00000007;
3748 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3749 ci->name, drivestrength);
3751 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3752 str_tab = sdiod_drive_strength_tab5_1v8;
3753 str_mask = 0x00003800;
3757 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3758 ci->name, ci->chiprev, ci->pmurev);
3762 if (str_tab != NULL) {
3763 for (i = 0; str_tab[i].strength != 0; i++) {
3764 if (drivestrength >= str_tab[i].strength) {
3765 drivestrength_sel = str_tab[i].sel;
3769 base = brcmf_chip_get_chipcommon(ci)->base;
3770 addr = CORE_CC_REG(base, chipcontrol_addr);
3771 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3772 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3773 cc_data_temp &= ~str_mask;
3774 drivestrength_sel <<= str_shift;
3775 cc_data_temp |= drivestrength_sel;
3776 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3778 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3779 str_tab[i].strength, drivestrength, cc_data_temp);
3783 static int brcmf_sdio_buscoreprep(void *ctx)
3785 struct brcmf_sdio_dev *sdiodev = ctx;
3789 /* Try forcing SDIO core to do ALPAvail request only */
3790 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3791 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3793 brcmf_err("error writing for HT off\n");
3797 /* If register supported, wait for ALPAvail and then force ALP */
3798 /* This may take up to 15 milliseconds */
3799 clkval = brcmf_sdiod_regrb(sdiodev,
3800 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3802 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3803 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3808 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3809 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3810 !SBSDIO_ALPAV(clkval)),
3811 PMU_MAX_TRANSITION_DLY);
3812 if (!SBSDIO_ALPAV(clkval)) {
3813 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3818 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3819 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3822 /* Also, disable the extra SDIO pull-ups */
3823 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3828 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3831 struct brcmf_sdio_dev *sdiodev = ctx;
3832 struct brcmf_core *core;
3835 /* clear all interrupts */
3836 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3837 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3838 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3841 /* Write reset vector to address 0 */
3842 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3846 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3848 struct brcmf_sdio_dev *sdiodev = ctx;
3851 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3852 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3853 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3854 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3856 val &= ~CID_ID_MASK;
3857 val |= BRCM_CC_4339_CHIP_ID;
3863 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3865 struct brcmf_sdio_dev *sdiodev = ctx;
3867 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3870 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3871 .prepare = brcmf_sdio_buscoreprep,
3872 .activate = brcmf_sdio_buscore_activate,
3873 .read32 = brcmf_sdio_buscore_read32,
3874 .write32 = brcmf_sdio_buscore_write32,
3878 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3886 sdio_claim_host(bus->sdiodev->func[1]);
3888 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3889 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3892 * Force PLL off until brcmf_chip_attach()
3893 * programs PLL control regs
3896 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3897 BRCMF_INIT_CLKCTL1, &err);
3899 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3900 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3902 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3903 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3904 err, BRCMF_INIT_CLKCTL1, clkctl);
3908 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3909 if (IS_ERR(bus->ci)) {
3910 brcmf_err("brcmf_chip_attach failed!\n");
3915 if (brcmf_sdio_kso_init(bus)) {
3916 brcmf_err("error enabling KSO\n");
3920 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3921 drivestrength = bus->sdiodev->pdata->drive_strength;
3923 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3924 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3926 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3927 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3928 SDIO_CCCR_BRCM_CARDCTRL, &err);
3932 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3934 brcmf_sdiod_regwb(bus->sdiodev,
3935 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3939 /* set PMUControl so a backplane reset does PMU state reload */
3940 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
3942 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
3946 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3948 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
3952 sdio_release_host(bus->sdiodev->func[1]);
3954 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3956 /* allocate header buffer */
3957 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3960 /* Locate an appropriately-aligned portion of hdrbuf */
3961 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3964 /* Set the poll and/or interrupt flags */
3973 sdio_release_host(bus->sdiodev->func[1]);
3978 brcmf_sdio_watchdog_thread(void *data)
3980 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3983 allow_signal(SIGTERM);
3984 /* Run until signal received */
3985 brcmf_sdiod_freezer_count(bus->sdiodev);
3987 if (kthread_should_stop())
3989 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3990 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3991 brcmf_sdiod_freezer_count(bus->sdiodev);
3992 brcmf_sdiod_try_freeze(bus->sdiodev);
3994 brcmf_sdio_bus_watchdog(bus);
3995 /* Count the tick for reference */
3996 bus->sdcnt.tickcnt++;
3997 reinit_completion(&bus->watchdog_wait);
4005 brcmf_sdio_watchdog(unsigned long data)
4007 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4009 if (bus->watchdog_tsk) {
4010 complete(&bus->watchdog_wait);
4011 /* Reschedule the watchdog */
4012 if (bus->wd_timer_valid)
4013 mod_timer(&bus->timer,
4014 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
4018 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4019 .stop = brcmf_sdio_bus_stop,
4020 .preinit = brcmf_sdio_bus_preinit,
4021 .txdata = brcmf_sdio_bus_txdata,
4022 .txctl = brcmf_sdio_bus_txctl,
4023 .rxctl = brcmf_sdio_bus_rxctl,
4024 .gettxq = brcmf_sdio_bus_gettxq,
4025 .wowl_config = brcmf_sdio_wowl_config,
4026 .get_ramsize = brcmf_sdio_bus_get_ramsize,
4027 .get_memdump = brcmf_sdio_bus_get_memdump,
4030 static void brcmf_sdio_firmware_callback(struct device *dev,
4031 const struct firmware *code,
4032 void *nvram, u32 nvram_len)
4034 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4035 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
4036 struct brcmf_sdio *bus = sdiodev->bus;
4040 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
4045 /* try to download image and nvram to the dongle */
4046 bus->alp_only = true;
4047 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4050 bus->alp_only = false;
4052 /* Start the watchdog timer */
4053 bus->sdcnt.tickcnt = 0;
4054 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
4056 sdio_claim_host(sdiodev->func[1]);
4058 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4059 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4060 if (bus->clkstate != CLK_AVAIL)
4063 /* Force clocks on backplane to be sure F2 interrupt propagates */
4064 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4066 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4067 (saveclk | SBSDIO_FORCE_HT), &err);
4070 brcmf_err("Failed to force clock for F2: err %d\n", err);
4074 /* Enable function 2 (frame transfers) */
4075 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4076 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4077 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4080 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4082 /* If F2 successfully enabled, set core and enable interrupts */
4084 /* Set up the interrupt mask and enable interrupts */
4085 bus->hostintmask = HOSTINTMASK;
4086 w_sdreg32(bus, bus->hostintmask,
4087 offsetof(struct sdpcmd_regs, hostintmask));
4089 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4091 /* Disable F2 again */
4092 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4096 if (brcmf_chip_sr_capable(bus->ci)) {
4097 brcmf_sdio_sr_init(bus);
4099 /* Restore previous clock setting */
4100 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4105 err = brcmf_sdiod_intr_register(sdiodev);
4107 brcmf_err("intr register failed:%d\n", err);
4110 /* If we didn't come up, turn off backplane clock */
4112 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4114 sdio_release_host(sdiodev->func[1]);
4116 err = brcmf_bus_start(dev);
4118 brcmf_err("dongle is not responding\n");
4124 sdio_release_host(sdiodev->func[1]);
4126 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4127 device_release_driver(dev);
4130 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4133 struct brcmf_sdio *bus;
4134 struct workqueue_struct *wq;
4136 brcmf_dbg(TRACE, "Enter\n");
4138 /* Allocate private bus interface state */
4139 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4143 bus->sdiodev = sdiodev;
4145 skb_queue_head_init(&bus->glom);
4146 bus->txbound = BRCMF_TXBOUND;
4147 bus->rxbound = BRCMF_RXBOUND;
4148 bus->txminmax = BRCMF_TXMINMAX;
4149 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4151 /* platform specific configuration:
4152 * alignments must be at least 4 bytes for ADMA
4154 bus->head_align = ALIGNMENT;
4155 bus->sgentry_align = ALIGNMENT;
4156 if (sdiodev->pdata) {
4157 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4158 bus->head_align = sdiodev->pdata->sd_head_align;
4159 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4160 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4163 /* single-threaded workqueue */
4164 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4165 dev_name(&sdiodev->func[1]->dev));
4167 brcmf_err("insufficient memory to create txworkqueue\n");
4170 brcmf_sdiod_freezer_count(sdiodev);
4171 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4174 /* attempt to attach to the dongle */
4175 if (!(brcmf_sdio_probe_attach(bus))) {
4176 brcmf_err("brcmf_sdio_probe_attach failed\n");
4180 spin_lock_init(&bus->rxctl_lock);
4181 spin_lock_init(&bus->txq_lock);
4182 init_waitqueue_head(&bus->ctrl_wait);
4183 init_waitqueue_head(&bus->dcmd_resp_wait);
4185 /* Set up the watchdog timer */
4186 init_timer(&bus->timer);
4187 bus->timer.data = (unsigned long)bus;
4188 bus->timer.function = brcmf_sdio_watchdog;
4190 /* Initialize watchdog thread */
4191 init_completion(&bus->watchdog_wait);
4192 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4193 bus, "brcmf_wdog/%s",
4194 dev_name(&sdiodev->func[1]->dev));
4195 if (IS_ERR(bus->watchdog_tsk)) {
4196 pr_warn("brcmf_watchdog thread failed to start\n");
4197 bus->watchdog_tsk = NULL;
4199 /* Initialize DPC thread */
4200 bus->dpc_triggered = false;
4201 bus->dpc_running = false;
4203 /* Assign bus interface call back */
4204 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4205 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4206 bus->sdiodev->bus_if->chip = bus->ci->chip;
4207 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4209 /* default sdio bus header length for tx packet */
4210 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4212 /* Attach to the common layer, reserve hdr space */
4213 ret = brcmf_attach(bus->sdiodev->dev);
4215 brcmf_err("brcmf_attach failed\n");
4219 /* Query the F2 block size, set roundup accordingly */
4220 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4221 bus->roundup = min(max_roundup, bus->blocksize);
4223 /* Allocate buffers */
4224 if (bus->sdiodev->bus_if->maxctl) {
4225 bus->sdiodev->bus_if->maxctl += bus->roundup;
4227 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4228 ALIGNMENT) + bus->head_align;
4229 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4230 if (!(bus->rxbuf)) {
4231 brcmf_err("rxbuf allocation failed\n");
4236 sdio_claim_host(bus->sdiodev->func[1]);
4238 /* Disable F2 to clear any intermediate frame state on the dongle */
4239 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4241 bus->rxflow = false;
4243 /* Done with backplane-dependent accesses, can drop clock... */
4244 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4246 sdio_release_host(bus->sdiodev->func[1]);
4248 /* ...and initialize clock/power states */
4249 bus->clkstate = CLK_SDONLY;
4250 bus->idletime = BRCMF_IDLE_INTERVAL;
4251 bus->idleclock = BRCMF_IDLE_ACTIVE;
4254 bus->sr_enabled = false;
4256 brcmf_sdio_debugfs_create(bus);
4257 brcmf_dbg(INFO, "completed!!\n");
4259 ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
4263 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4264 sdiodev->fw_name, sdiodev->nvram_name,
4265 brcmf_sdio_firmware_callback);
4267 brcmf_err("async firmware request failed: %d\n", ret);
4274 brcmf_sdio_remove(bus);
4278 /* Detach and free everything */
4279 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4281 brcmf_dbg(TRACE, "Enter\n");
4284 /* Stop watchdog task */
4285 if (bus->watchdog_tsk) {
4286 send_sig(SIGTERM, bus->watchdog_tsk, 1);
4287 kthread_stop(bus->watchdog_tsk);
4288 bus->watchdog_tsk = NULL;
4291 /* De-register interrupt handler */
4292 brcmf_sdiod_intr_unregister(bus->sdiodev);
4294 brcmf_detach(bus->sdiodev->dev);
4296 cancel_work_sync(&bus->datawork);
4298 destroy_workqueue(bus->brcmf_wq);
4301 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4302 sdio_claim_host(bus->sdiodev->func[1]);
4303 brcmf_sdio_wd_timer(bus, 0);
4304 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4305 /* Leave the device in state where it is
4306 * 'passive'. This is done by resetting all
4310 brcmf_chip_set_passive(bus->ci);
4311 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4312 sdio_release_host(bus->sdiodev->func[1]);
4314 brcmf_chip_detach(bus->ci);
4322 brcmf_dbg(TRACE, "Disconnected\n");
4325 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4327 /* Totally stop the timer */
4328 if (!wdtick && bus->wd_timer_valid) {
4329 del_timer_sync(&bus->timer);
4330 bus->wd_timer_valid = false;
4331 bus->save_ms = wdtick;
4335 /* don't start the wd until fw is loaded */
4336 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4340 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4341 if (bus->wd_timer_valid)
4342 /* Stop timer and restart at new value */
4343 del_timer_sync(&bus->timer);
4345 /* Create timer again when watchdog period is
4346 dynamically changed or in the first instance
4348 bus->timer.expires =
4349 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS);
4350 add_timer(&bus->timer);
4353 /* Re arm the timer, at last watchdog period */
4354 mod_timer(&bus->timer,
4355 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
4358 bus->wd_timer_valid = true;
4359 bus->save_ms = wdtick;
4363 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4367 sdio_claim_host(bus->sdiodev->func[1]);
4368 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4369 sdio_release_host(bus->sdiodev->func[1]);
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