1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 * Copyright(c) 2018 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
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23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
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31 * Intel Linux Wireless <linuxwifi@intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
38 * Copyright(c) 2018 Intel Corporation
39 * All rights reserved.
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42 * modification, are permitted provided that the following conditions
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55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 *****************************************************************************/
71 * CSR (control and status registers)
73 * CSR registers are mapped directly into PCI bus space, and are accessible
74 * whenever platform supplies power to device, even when device is in
75 * low power states due to driver-invoked device resets
76 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
78 * Use iwl_write32() and iwl_read32() family to access these registers;
79 * these provide simple PCI bus access, without waking up the MAC.
80 * Do not use iwl_write_direct32() family for these registers;
81 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
82 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
85 * NOTE: Device does need to be awake in order to read this memory
86 * via CSR_EEPROM and CSR_OTP registers
88 #define CSR_BASE (0x000)
90 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
91 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
92 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
93 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
94 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
95 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
96 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
97 #define CSR_GP_CNTRL (CSR_BASE+0x024)
99 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
100 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
103 * Hardware revision info
106 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
110 #define CSR_HW_REV (CSR_BASE+0x028)
113 * RF ID revision info
115 * 31:24: Reserved (set to 0x0)
117 * 11:8: Step (A - 0x0, B - 0x1, etc)
121 #define CSR_HW_RF_ID (CSR_BASE+0x09c)
124 * EEPROM and OTP (one-time-programmable) memory reads
126 * NOTE: Device must be awake, initialized via apm_ops.init(),
129 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
130 #define CSR_EEPROM_GP (CSR_BASE+0x030)
131 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
133 #define CSR_GIO_REG (CSR_BASE+0x03C)
134 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
135 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
138 * UCODE-DRIVER GP (general purpose) mailbox registers.
139 * SET/CLR registers set/clear bit(s) if "1" is written.
141 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
142 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
143 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
144 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
146 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
148 #define CSR_LED_REG (CSR_BASE+0x094)
149 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
150 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
151 #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
152 #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
153 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
155 /* GIO Chicken Bits (PCI Express bus link power management) */
156 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
158 /* host chicken bits */
159 #define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
160 #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
162 /* Analog phase-lock-loop configuration */
163 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
166 * CSR HW resources monitor registers
168 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
169 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
170 #define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
173 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
174 * "step" determines CCK backoff for txpower calculation.
175 * See also CSR_HW_REV register.
177 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
178 * 1-0: "Dash" (-) value, as in C-1, etc.
180 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
182 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
183 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
185 /* Bits for CSR_HW_IF_CONFIG_REG */
186 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
187 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
188 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
189 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
190 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
191 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
192 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
193 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
195 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
196 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
197 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
198 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
199 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
200 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
202 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
203 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
204 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
205 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
206 #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
207 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
208 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
210 #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
212 #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
213 #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
215 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
216 * acknowledged (reset) by host writing "1" to flagged bits. */
217 #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
218 #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
219 #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
220 #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
221 #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
222 #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
223 #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
224 #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
225 #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
226 #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
227 #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
229 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
230 CSR_INT_BIT_HW_ERR | \
231 CSR_INT_BIT_FH_TX | \
232 CSR_INT_BIT_SW_ERR | \
233 CSR_INT_BIT_RF_KILL | \
234 CSR_INT_BIT_SW_RX | \
235 CSR_INT_BIT_WAKEUP | \
236 CSR_INT_BIT_ALIVE | \
237 CSR_INT_BIT_RX_PERIODIC)
239 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
240 #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
241 #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
242 #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
243 #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
244 #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
245 #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
247 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
248 CSR_FH_INT_BIT_RX_CHNL1 | \
249 CSR_FH_INT_BIT_RX_CHNL0)
251 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
252 CSR_FH_INT_BIT_TX_CHNL0)
255 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
256 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
257 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
260 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
261 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
262 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
263 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
264 #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
267 * GP (general purpose) CONTROL REGISTER
270 * Indicates state of (platform's) hardware RF-Kill switch
271 * 26-24: POWER_SAVE_TYPE
272 * Indicates current power-saving mode:
273 * 000 -- No power saving
274 * 001 -- MAC power-down
275 * 010 -- PHY (radio) power-down
277 * 10: XTAL ON request
279 * Indicates current system configuration, reflecting pins on chip
280 * as forced high/low by device circuit board.
282 * Indicates MAC is entering a power-saving sleep power-down.
283 * Not a good time to access device-internal resources.
285 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
286 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
288 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
289 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
290 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
294 #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
295 #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
298 #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
299 #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
300 #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
301 #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
313 #define CSR_HW_REV_TYPE_MSK (0x000FFF0)
314 #define CSR_HW_REV_TYPE_5300 (0x0000020)
315 #define CSR_HW_REV_TYPE_5350 (0x0000030)
316 #define CSR_HW_REV_TYPE_5100 (0x0000050)
317 #define CSR_HW_REV_TYPE_5150 (0x0000040)
318 #define CSR_HW_REV_TYPE_1000 (0x0000060)
319 #define CSR_HW_REV_TYPE_6x00 (0x0000070)
320 #define CSR_HW_REV_TYPE_6x50 (0x0000080)
321 #define CSR_HW_REV_TYPE_6150 (0x0000084)
322 #define CSR_HW_REV_TYPE_6x05 (0x00000B0)
323 #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
324 #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
325 #define CSR_HW_REV_TYPE_2x30 (0x00000C0)
326 #define CSR_HW_REV_TYPE_2x00 (0x0000100)
327 #define CSR_HW_REV_TYPE_105 (0x0000110)
328 #define CSR_HW_REV_TYPE_135 (0x0000120)
329 #define CSR_HW_REV_TYPE_7265D (0x0000210)
330 #define CSR_HW_REV_TYPE_NONE (0x00001F0)
331 #define CSR_HW_REV_TYPE_QNJ (0x0000360)
332 #define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
335 #define CSR_HW_RF_ID_TYPE_JF (0x00105100)
336 #define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
337 #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
340 #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
342 /* HW_RF CHIP STEP */
343 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
346 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
347 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
348 #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
349 #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
352 #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
353 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
354 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
355 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
356 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
357 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
359 /* One-time-programmable memory general purpose reg */
360 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
361 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
362 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
363 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
366 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
367 #define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
368 #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
369 #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
370 #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
374 #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
377 * UCODE-DRIVER GP (general purpose) mailbox register 1
378 * Host driver and uCode write and/or read this register to communicate with
382 * Host sets this to request permanent halt of uCode, same as
383 * sending CARD_STATE command with "halt" bit set.
385 * Host sets this to request exit from CT_KILL state, i.e. host thinks
386 * device temperature is low enough to continue normal operation.
388 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
389 * to release uCode to clear all Tx and command queues, enter
390 * unassociated mode, and power down.
391 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
393 * Host sets this when issuing CARD_STATE command to request
396 * uCode sets this when preparing a power-saving power-down.
397 * uCode resets this when power-up is complete and SRAM is sane.
398 * NOTE: device saves internal SRAM data to host when powering down,
399 * and must restore this data after powering back up.
400 * MAC_SLEEP is the best indication that restore is complete.
401 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
402 * do not need to save/restore it.
404 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
405 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
406 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
407 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
408 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
411 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
412 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
413 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
414 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
415 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
416 #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
418 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
420 /* GIO Chicken Bits (PCI Express bus link power management) */
421 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
422 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
425 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
426 #define CSR_LED_REG_TURN_ON (0x60)
427 #define CSR_LED_REG_TURN_OFF (0x20)
430 #define CSR50_ANA_PLL_CFG_VAL (0x00880300)
433 #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
436 #define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
437 #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
438 #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
441 * SHR target access (Shared block memory space)
443 * Shared internal registers can be accessed directly from PCI bus through SHR
444 * arbiter without need for the MAC HW to be powered up. This is possible due to
445 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
446 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
448 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
449 * need not be powered up so no "grab inc access" is required.
453 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
454 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
455 * first, write to the control register:
456 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
457 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
458 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
460 * To write the register, first, write to the data register
461 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
462 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
463 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
465 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
466 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
469 * HBUS (Host-side Bus)
471 * HBUS registers are mapped directly into PCI bus space, but are used
472 * to indirectly access device's internal memory or registers that
473 * may be powered-down.
475 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
476 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
477 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
478 * internal resources.
480 * Do not use iwl_write32()/iwl_read32() family to access these registers;
481 * these provide only simple PCI bus access, without waking up the MAC.
483 #define HBUS_BASE (0x400)
486 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
487 * structures, error log, event log, verifying uCode load).
488 * First write to address register, then read from or write to data register
489 * to complete the job. Once the address register is set up, accesses to
490 * data registers auto-increment the address by one dword.
491 * Bit usage for address registers (read or write):
492 * 0-31: memory address within device
494 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
495 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
496 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
497 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
499 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
500 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
501 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
504 * Registers for accessing device's internal peripheral registers
505 * (e.g. SCD, BSM, etc.). First write to address register,
506 * then read from or write to data register to complete the job.
507 * Bit usage for address registers (read or write):
508 * 0-15: register address (offset) within device
509 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
511 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
512 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
513 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
514 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
516 /* Used to enable DBGM */
517 #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
520 * Per-Tx-queue write pointer (index, really!)
521 * Indicates index to next TFD that driver will fill (1 past latest filled).
523 * 0-7: queue write index
524 * 11-8: queue selector
526 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
528 /**********************************************************
530 **********************************************************/
532 * host interrupt timeout value
533 * used with setting interrupt coalescing timer
534 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
536 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
538 #define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
539 #define IWL_HOST_INT_TIMEOUT_DEF (0x40)
540 #define IWL_HOST_INT_TIMEOUT_MIN (0x0)
541 #define IWL_HOST_INT_OPER_MODE BIT(31)
543 /*****************************************************************************
544 * 7000/3000 series SHR DTS addresses *
545 *****************************************************************************/
547 /* Diode Results Register Structure: */
549 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
550 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
551 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
552 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
553 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
554 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
555 /* Those are the masks INSIDE the flags bit-field: */
556 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
557 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
558 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
559 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
562 /*****************************************************************************
563 * MSIX related registers *
564 *****************************************************************************/
566 #define CSR_MSIX_BASE (0x2000)
567 #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
568 #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
569 #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
570 #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
571 #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
572 #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
573 #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
574 #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
575 #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
576 #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
578 #define MSIX_FH_INT_CAUSES_Q(q) (q)
581 * Causes for the FH register interrupts
583 enum msix_fh_int_causes {
584 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
585 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
586 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
587 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
588 MSIX_FH_INT_CAUSES_S2D = BIT(19),
589 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
593 * Causes for the HW register interrupts
595 enum msix_hw_int_causes {
596 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
597 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
598 MSIX_HW_INT_CAUSES_REG_IPC = BIT(1),
599 MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = BIT(5),
600 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
601 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
602 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
603 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
604 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
605 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
606 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
607 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
610 #define MSIX_MIN_INTERRUPT_VECTORS 2
611 #define MSIX_AUTO_CLEAR_CAUSE 0
612 #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
614 /*****************************************************************************
615 * HW address related registers *
616 *****************************************************************************/
618 #define CSR_ADDR_BASE (0x380)
619 #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
620 #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
621 #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
622 #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
624 #endif /* !__iwl_csr_h__ */