drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2018 Intel Corporation
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2018 Intel Corporation
  22  * All rights reserved.
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
  27  *
  28  *  * Redistributions of source code must retain the above copyright
  29  *    notice, this list of conditions and the following disclaimer.
  30  *  * Redistributions in binary form must reproduce the above copyright
  31  *    notice, this list of conditions and the following disclaimer in
  32  *    the documentation and/or other materials provided with the
  33  *    distribution.
  34  *  * Neither the name Intel Corporation nor the names of its
  35  *    contributors may be used to endorse or promote products derived
  36  *    from this software without specific prior written permission.
  37  *
  38  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  39  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  40  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  41  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  42  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  43  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  44  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  45  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  46  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  47  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  48  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  49  *
  50  *****************************************************************************/
  51
  52 #include "iwl-trans.h"
  53 #include "iwl-fh.h"
  54 #include "iwl-context-info-gen3.h"
  55 #include "internal.h"
  56 #include "iwl-prph.h"
  57
  58 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
  59                                  const struct fw_img *fw)
  60 {
  61         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  62         struct iwl_context_info_gen3 *ctxt_info_gen3;
  63         struct iwl_prph_scratch *prph_scratch;
  64         struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
  65         struct iwl_prph_info *prph_info;
  66         u32 control_flags = 0;
  67         int ret;
  68
  69         /* Allocate prph scratch */
  70         prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
  71                                           &trans_pcie->prph_scratch_dma_addr,
  72                                           GFP_KERNEL);
  73         if (!prph_scratch)
  74                 return -ENOMEM;
  75
  76         prph_sc_ctrl = &prph_scratch->ctrl_cfg;
  77
  78         prph_sc_ctrl->version.version = 0;
  79         prph_sc_ctrl->version.mac_id =
  80                 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
  81         prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
  82
  83         control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K |
  84                         IWL_PRPH_SCRATCH_MTR_MODE |
  85                         (IWL_PRPH_MTR_FORMAT_256B &
  86                          IWL_PRPH_SCRATCH_MTR_FORMAT) |
  87                         IWL_PRPH_SCRATCH_EARLY_DEBUG_EN |
  88                         IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
  89         prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
  90
  91         /* initialize RX default queue */
  92         prph_sc_ctrl->rbd_cfg.free_rbd_addr =
  93                 cpu_to_le64(trans_pcie->rxq->bd_dma);
  94
  95         /* Configure debug, for integration */
  96         iwl_pcie_alloc_fw_monitor(trans, 0);
  97         prph_sc_ctrl->hwm_cfg.hwm_base_addr =
  98                 cpu_to_le64(trans_pcie->fw_mon_phys);
  99         prph_sc_ctrl->hwm_cfg.hwm_size =
 100                 cpu_to_le32(trans_pcie->fw_mon_size);
 101
 102         /* allocate ucode sections in dram and set addresses */
 103         ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
 104         if (ret)
 105                 goto err_free_prph_scratch;
 106
 107
 108         /* Allocate prph information
 109          * currently we don't assign to the prph info anything, but it would get
 110          * assigned later */
 111         prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
 112                                        &trans_pcie->prph_info_dma_addr,
 113                                        GFP_KERNEL);
 114         if (!prph_info) {
 115                 ret = -ENOMEM;
 116                 goto err_free_prph_scratch;
 117         }
 118
 119         /* Allocate context info */
 120         ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
 121                                             sizeof(*ctxt_info_gen3),
 122                                             &trans_pcie->ctxt_info_dma_addr,
 123                                             GFP_KERNEL);
 124         if (!ctxt_info_gen3) {
 125                 ret = -ENOMEM;
 126                 goto err_free_prph_info;
 127         }
 128
 129         ctxt_info_gen3->prph_info_base_addr =
 130                 cpu_to_le64(trans_pcie->prph_info_dma_addr);
 131         ctxt_info_gen3->prph_scratch_base_addr =
 132                 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
 133         ctxt_info_gen3->prph_scratch_size =
 134                 cpu_to_le32(sizeof(*prph_scratch));
 135         ctxt_info_gen3->cr_head_idx_arr_base_addr =
 136                 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
 137         ctxt_info_gen3->tr_tail_idx_arr_base_addr =
 138                 cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
 139         ctxt_info_gen3->cr_tail_idx_arr_base_addr =
 140                 cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
 141         ctxt_info_gen3->cr_idx_arr_size =
 142                 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
 143         ctxt_info_gen3->tr_idx_arr_size =
 144                 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
 145         ctxt_info_gen3->mtr_base_addr =
 146                 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
 147         ctxt_info_gen3->mcr_base_addr =
 148                 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
 149         ctxt_info_gen3->mtr_size =
 150                 cpu_to_le16(TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS));
 151         ctxt_info_gen3->mcr_size =
 152                 cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE));
 153
 154         trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
 155         trans_pcie->prph_info = prph_info;
 156         trans_pcie->prph_scratch = prph_scratch;
 157
 158         /* Allocate IML */
 159         trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len,
 160                                              &trans_pcie->iml_dma_addr,
 161                                              GFP_KERNEL);
 162         if (!trans_pcie->iml) {
 163                 ret = -ENOMEM;
 164                 goto err_free_ctxt_info;
 165         }
 166
 167         memcpy(trans_pcie->iml, trans->iml, trans->iml_len);
 168
 169         iwl_enable_fw_load_int_ctx_info(trans);
 170
 171         /* kick FW self load */
 172         iwl_write64(trans, CSR_CTXT_INFO_ADDR,
 173                     trans_pcie->ctxt_info_dma_addr);
 174         iwl_write64(trans, CSR_IML_DATA_ADDR,
 175                     trans_pcie->iml_dma_addr);
 176         iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
 177         iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, CSR_AUTO_FUNC_BOOT_ENA);
 178         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
 179
 180         return 0;
 181
 182 err_free_ctxt_info:
 183         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
 184                           trans_pcie->ctxt_info_gen3,
 185                           trans_pcie->ctxt_info_dma_addr);
 186         trans_pcie->ctxt_info_gen3 = NULL;
 187 err_free_prph_info:
 188         dma_free_coherent(trans->dev,
 189                           sizeof(*prph_info),
 190                         prph_info,
 191                         trans_pcie->prph_info_dma_addr);
 192
 193 err_free_prph_scratch:
 194         dma_free_coherent(trans->dev,
 195                           sizeof(*prph_scratch),
 196                         prph_scratch,
 197                         trans_pcie->prph_scratch_dma_addr);
 198         return ret;
 199
 200 }
 201
 202 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
 203 {
 204         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 205
 206         if (!trans_pcie->ctxt_info_gen3)
 207                 return;
 208
 209         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
 210                           trans_pcie->ctxt_info_gen3,
 211                           trans_pcie->ctxt_info_dma_addr);
 212         trans_pcie->ctxt_info_dma_addr = 0;
 213         trans_pcie->ctxt_info_gen3 = NULL;
 214
 215         dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml,
 216                           trans_pcie->iml_dma_addr);
 217         trans_pcie->iml_dma_addr = 0;
 218         trans_pcie->iml = NULL;
 219
 220         iwl_pcie_ctxt_info_free_fw_img(trans);
 221
 222         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
 223                           trans_pcie->prph_scratch,
 224                           trans_pcie->prph_scratch_dma_addr);
 225         trans_pcie->prph_scratch_dma_addr = 0;
 226         trans_pcie->prph_scratch = NULL;
 227
 228         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
 229                           trans_pcie->prph_info,
 230                           trans_pcie->prph_info_dma_addr);
 231         trans_pcie->prph_info_dma_addr = 0;
 232         trans_pcie->prph_info = NULL;
 233 }