1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 Intel Corporation
24 * All rights reserved.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
36 * * Neither the name Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 *****************************************************************************/
53 #include <linux/pm_runtime.h>
55 #include <linux/tcp.h>
57 #include "iwl-debug.h"
61 #include "fw/api/tx.h"
64 * iwl_pcie_gen2_tx_stop - Stop all Tx DMA channels
66 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
68 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
72 * This function can be called before the op_mode disabled the
73 * queues. This happens when we have an rfkill interrupt.
74 * Since we stop Tx altogether - mark the queues as stopped.
76 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
77 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
79 /* Unmap DMA from host system and free skb's */
80 for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) {
81 if (!trans_pcie->txq[txq_id])
83 iwl_pcie_gen2_txq_unmap(trans, txq_id);
88 * iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array
90 static void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie,
91 struct iwl_txq *txq, u16 byte_cnt,
94 struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr;
95 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
96 struct iwl_gen3_bc_tbl *scd_bc_tbl_gen3 = txq->bc_tbl.addr;
97 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
98 u8 filled_tfd_size, num_fetch_chunks;
102 if (trans_pcie->bc_table_dword)
103 len = DIV_ROUND_UP(len, 4);
105 if (WARN_ON(len > 0xFFF || idx >= txq->n_window))
108 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
109 num_tbs * sizeof(struct iwl_tfh_tb);
111 * filled_tfd_size contains the number of filled bytes in the TFD.
112 * Dividing it by 64 will give the number of chunks to fetch
113 * to SRAM- 0 for one chunk, 1 for 2 and so on.
114 * If, for example, TFD contains only 3 TBs then 32 bytes
115 * of the TFD are used, and only one chunk of 64 bytes should
118 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
120 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
121 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
122 scd_bc_tbl_gen3->tfd_offset[idx] = bc_ent;
124 scd_bc_tbl->tfd_offset[idx] = bc_ent;
128 * iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware
130 static void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
133 lockdep_assert_held(&txq->lock);
135 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
138 * if not in power-save mode, uCode will never sleep when we're
139 * trying to tx (during RFKILL, we're not trying to tx).
141 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
144 static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans,
145 struct iwl_tfh_tfd *tfd)
147 return le16_to_cpu(tfd->num_tbs) & 0x1f;
150 static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
151 struct iwl_cmd_meta *meta,
152 struct iwl_tfh_tfd *tfd)
154 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
157 /* Sanity check on number of chunks */
158 num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
160 if (num_tbs > trans_pcie->max_tbs) {
161 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
165 /* first TB is never freed - it's the bidirectional DMA data */
166 for (i = 1; i < num_tbs; i++) {
167 if (meta->tbs & BIT(i))
168 dma_unmap_page(trans->dev,
169 le64_to_cpu(tfd->tbs[i].addr),
170 le16_to_cpu(tfd->tbs[i].tb_len),
173 dma_unmap_single(trans->dev,
174 le64_to_cpu(tfd->tbs[i].addr),
175 le16_to_cpu(tfd->tbs[i].tb_len),
182 static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
184 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
185 * idx is bounded by n_window
187 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
189 lockdep_assert_held(&txq->lock);
191 iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
192 iwl_pcie_get_tfd(trans, txq, idx));
198 skb = txq->entries[idx].skb;
200 /* Can be called from irqs-disabled context
201 * If skb is not NULL, it means that the whole queue is being
202 * freed and that the queue is not empty - free the skb
205 iwl_op_mode_free_skb(trans->op_mode, skb);
206 txq->entries[idx].skb = NULL;
211 static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans,
212 struct iwl_tfh_tfd *tfd, dma_addr_t addr,
215 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
216 int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd);
217 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
219 /* Each TFD can point to a maximum max_tbs Tx buffers */
220 if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) {
221 IWL_ERR(trans, "Error can not send more than %d chunks\n",
222 trans_pcie->max_tbs);
226 put_unaligned_le64(addr, &tb->addr);
227 tb->tb_len = cpu_to_le16(len);
229 tfd->num_tbs = cpu_to_le16(idx + 1);
234 static int iwl_pcie_gen2_build_amsdu(struct iwl_trans *trans,
236 struct iwl_tfh_tfd *tfd, int start_len,
237 u8 hdr_len, struct iwl_device_cmd *dev_cmd)
240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
241 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
242 struct ieee80211_hdr *hdr = (void *)skb->data;
243 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
244 unsigned int mss = skb_shinfo(skb)->gso_size;
245 u16 length, amsdu_pad;
247 struct iwl_tso_hdr_page *hdr_page;
248 struct page **page_ptr;
251 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd),
252 &dev_cmd->hdr, start_len, 0);
254 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
255 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
256 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len;
259 /* total amount of header we may need for this A-MSDU */
260 hdr_room = DIV_ROUND_UP(total_len, mss) *
261 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr));
263 /* Our device supports 9 segments at most, it will fit in 1 page */
264 hdr_page = get_page_hdr(trans, hdr_room);
268 get_page(hdr_page->page);
269 start_hdr = hdr_page->pos;
270 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
271 *page_ptr = hdr_page->page;
274 * Pull the ieee80211 header to be able to use TSO core,
275 * we will restore it for the tx_status flow.
277 skb_pull(skb, hdr_len);
280 * Remove the length of all the headers that we don't actually
281 * have in the MPDU by themselves, but that we duplicate into
282 * all the different MSDUs inside the A-MSDU.
284 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
286 tso_start(skb, &tso);
289 /* this is the data left for this subframe */
290 unsigned int data_left = min_t(unsigned int, mss, total_len);
291 struct sk_buff *csum_skb = NULL;
294 u8 *subf_hdrs_start = hdr_page->pos;
296 total_len -= data_left;
298 memset(hdr_page->pos, 0, amsdu_pad);
299 hdr_page->pos += amsdu_pad;
300 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
302 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
303 hdr_page->pos += ETH_ALEN;
304 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
305 hdr_page->pos += ETH_ALEN;
307 length = snap_ip_tcp_hdrlen + data_left;
308 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
309 hdr_page->pos += sizeof(length);
312 * This will copy the SNAP as well which will be considered
315 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
317 hdr_page->pos += snap_ip_tcp_hdrlen;
319 tb_len = hdr_page->pos - start_hdr;
320 tb_phys = dma_map_single(trans->dev, start_hdr,
321 tb_len, DMA_TO_DEVICE);
322 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
323 dev_kfree_skb(csum_skb);
326 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
327 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, tb_len);
328 /* add this subframe's headers' length to the tx_cmd */
329 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
331 /* prepare the start_hdr for the next subframe */
332 start_hdr = hdr_page->pos;
334 /* put the payload */
336 tb_len = min_t(unsigned int, tso.size, data_left);
337 tb_phys = dma_map_single(trans->dev, tso.data,
338 tb_len, DMA_TO_DEVICE);
339 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
340 dev_kfree_skb(csum_skb);
343 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
344 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
348 tso_build_data(skb, &tso, tb_len);
352 /* re -add the WiFi header */
353 skb_push(skb, hdr_len);
363 iwl_tfh_tfd *iwl_pcie_gen2_build_tx_amsdu(struct iwl_trans *trans,
365 struct iwl_device_cmd *dev_cmd,
367 struct iwl_cmd_meta *out_meta,
371 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
372 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
377 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
379 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
382 * The second TB (tb1) points to the remainder of the TX command
383 * and the 802.11 header - dword aligned size
384 * (This calculation modifies the TX command, so do it before the
385 * setup of the first TB)
387 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
390 /* do not align A-MSDU to dword as the subframe header aligns it */
392 /* map the data for TB1 */
393 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
394 tb_phys = dma_map_single(trans->dev, tb1_addr, len, DMA_TO_DEVICE);
395 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
397 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, len);
399 if (iwl_pcie_gen2_build_amsdu(trans, skb, tfd,
400 len + IWL_FIRST_TB_SIZE,
404 /* building the A-MSDU might have changed this data, memcpy it now */
405 memcpy(&txq->first_tb_bufs[idx], &dev_cmd->hdr, IWL_FIRST_TB_SIZE);
409 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
414 iwl_tfh_tfd *iwl_pcie_gen2_build_tx(struct iwl_trans *trans,
416 struct iwl_device_cmd *dev_cmd,
418 struct iwl_cmd_meta *out_meta,
422 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
423 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
425 int i, len, tb1_len, tb2_len;
428 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
430 /* The first TB points to bi-directional DMA data */
431 memcpy(&txq->first_tb_bufs[idx], &dev_cmd->hdr, IWL_FIRST_TB_SIZE);
433 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
436 * The second TB (tb1) points to the remainder of the TX command
437 * and the 802.11 header - dword aligned size
438 * (This calculation modifies the TX command, so do it before the
439 * setup of the first TB)
441 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
444 tb1_len = ALIGN(len, 4);
446 /* map the data for TB1 */
447 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
448 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
449 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
451 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len);
453 /* set up TFD's third entry to point to remainder of skb's head */
454 tb2_len = skb_headlen(skb) - hdr_len;
457 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len,
458 tb2_len, DMA_TO_DEVICE);
459 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
461 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len);
464 /* set up the remaining entries to point to the data */
465 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
466 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
469 if (!skb_frag_size(frag))
472 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
473 skb_frag_size(frag), DMA_TO_DEVICE);
475 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
477 tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys,
478 skb_frag_size(frag));
480 out_meta->tbs |= BIT(tb_idx);
483 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr,
484 IWL_FIRST_TB_SIZE + tb1_len, hdr_len);
485 trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len);
490 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
495 struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans,
497 struct iwl_device_cmd *dev_cmd,
499 struct iwl_cmd_meta *out_meta)
501 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
502 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
503 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
507 /* There must be data left over for TB1 or this code must be changed */
508 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE);
510 memset(tfd, 0, sizeof(*tfd));
512 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560)
513 len = sizeof(struct iwl_tx_cmd_gen2);
515 len = sizeof(struct iwl_tx_cmd_gen3);
517 amsdu = ieee80211_is_data_qos(hdr->frame_control) &&
518 (*ieee80211_get_qos_ctl(hdr) &
519 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
521 hdr_len = ieee80211_hdrlen(hdr->frame_control);
524 * Only build A-MSDUs here if doing so by GSO, otherwise it may be
525 * an A-MSDU for other reasons, e.g. NAN or an A-MSDU having been
526 * built in the higher layers already.
528 if (amsdu && skb_shinfo(skb)->gso_size)
529 return iwl_pcie_gen2_build_tx_amsdu(trans, txq, dev_cmd, skb,
530 out_meta, hdr_len, len);
532 return iwl_pcie_gen2_build_tx(trans, txq, dev_cmd, skb, out_meta,
536 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
537 struct iwl_device_cmd *dev_cmd, int txq_id)
539 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
540 struct iwl_cmd_meta *out_meta;
541 struct iwl_txq *txq = trans_pcie->txq[txq_id];
546 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
547 "TX on unused queue %d\n", txq_id))
550 if (skb_is_nonlinear(skb) &&
551 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
552 __skb_linearize(skb))
555 spin_lock(&txq->lock);
557 if (iwl_queue_space(trans, txq) < txq->high_mark) {
558 iwl_stop_queue(trans, txq);
560 /* don't put the packet on the ring, if there is no room */
561 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
562 struct iwl_device_cmd **dev_cmd_ptr;
564 dev_cmd_ptr = (void *)((u8 *)skb->cb +
565 trans_pcie->dev_cmd_offs);
567 *dev_cmd_ptr = dev_cmd;
568 __skb_queue_tail(&txq->overflow_q, skb);
569 spin_unlock(&txq->lock);
574 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
576 /* Set up driver data for this TFD */
577 txq->entries[idx].skb = skb;
578 txq->entries[idx].cmd = dev_cmd;
580 dev_cmd->hdr.sequence =
581 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
584 /* Set up first empty entry in queue's array of Tx/cmd buffers */
585 out_meta = &txq->entries[idx].meta;
588 tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta);
590 spin_unlock(&txq->lock);
594 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
595 struct iwl_tx_cmd_gen3 *tx_cmd_gen3 =
596 (void *)dev_cmd->payload;
598 cmd_len = le16_to_cpu(tx_cmd_gen3->len);
600 struct iwl_tx_cmd_gen2 *tx_cmd_gen2 =
601 (void *)dev_cmd->payload;
603 cmd_len = le16_to_cpu(tx_cmd_gen2->len);
606 /* Set up entry for this TFD in Tx byte-count array */
607 iwl_pcie_gen2_update_byte_tbl(trans_pcie, txq, cmd_len,
608 iwl_pcie_gen2_get_num_tbs(trans, tfd));
610 /* start timer if queue currently empty */
611 if (txq->read_ptr == txq->write_ptr) {
613 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
614 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
615 iwl_trans_ref(trans);
618 /* Tell device the write index *just past* this latest filled TFD */
619 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
620 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
622 * At this point the frame is "transmitted" successfully
623 * and we will get a TX status notification eventually.
625 spin_unlock(&txq->lock);
629 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
632 * iwl_pcie_gen2_enqueue_hcmd - enqueue a uCode command
633 * @priv: device private data point
634 * @cmd: a pointer to the ucode command structure
636 * The function returns < 0 values to indicate the operation
637 * failed. On success, it returns the index (>= 0) of command in the
640 static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
641 struct iwl_host_cmd *cmd)
643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
644 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
645 struct iwl_device_cmd *out_cmd;
646 struct iwl_cmd_meta *out_meta;
648 void *dup_buf = NULL;
649 dma_addr_t phys_addr;
651 u16 copy_size, cmd_size, tb0_size;
652 bool had_nocopy = false;
653 u8 group_id = iwl_cmd_groupid(cmd->id);
654 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
655 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
656 struct iwl_tfh_tfd *tfd;
657 unsigned long flags2;
659 copy_size = sizeof(struct iwl_cmd_header_wide);
660 cmd_size = sizeof(struct iwl_cmd_header_wide);
662 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
663 cmddata[i] = cmd->data[i];
664 cmdlen[i] = cmd->len[i];
669 /* need at least IWL_FIRST_TB_SIZE copied */
670 if (copy_size < IWL_FIRST_TB_SIZE) {
671 int copy = IWL_FIRST_TB_SIZE - copy_size;
673 if (copy > cmdlen[i])
680 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
682 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
686 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
688 * This is also a chunk that isn't copied
689 * to the static buffer so set had_nocopy.
693 /* only allowed once */
694 if (WARN_ON(dup_buf)) {
699 dup_buf = kmemdup(cmddata[i], cmdlen[i],
704 /* NOCOPY must not be followed by normal! */
705 if (WARN_ON(had_nocopy)) {
709 copy_size += cmdlen[i];
711 cmd_size += cmd->len[i];
715 * If any of the command structures end up being larger than the
716 * TFD_MAX_PAYLOAD_SIZE and they aren't dynamically allocated into
717 * separate TFDs, then we will need to increase the size of the buffers
719 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
720 "Command %s (%#x) is too large (%d bytes)\n",
721 iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) {
726 spin_lock_irqsave(&txq->lock, flags2);
728 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
729 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
730 memset(tfd, 0, sizeof(*tfd));
732 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
733 spin_unlock_irqrestore(&txq->lock, flags2);
735 IWL_ERR(trans, "No space in command queue\n");
736 iwl_op_mode_cmd_queue_full(trans->op_mode);
741 out_cmd = txq->entries[idx].cmd;
742 out_meta = &txq->entries[idx].meta;
744 /* re-initialize to NULL */
745 memset(out_meta, 0, sizeof(*out_meta));
746 if (cmd->flags & CMD_WANT_SKB)
747 out_meta->source = cmd;
749 /* set up the header */
750 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
751 out_cmd->hdr_wide.group_id = group_id;
752 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
753 out_cmd->hdr_wide.length =
754 cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide));
755 out_cmd->hdr_wide.reserved = 0;
756 out_cmd->hdr_wide.sequence =
757 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
758 INDEX_TO_SEQ(txq->write_ptr));
760 cmd_pos = sizeof(struct iwl_cmd_header_wide);
761 copy_size = sizeof(struct iwl_cmd_header_wide);
763 /* and copy the data that needs to be copied */
764 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
770 /* copy everything if not nocopy/dup */
771 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
772 IWL_HCMD_DFL_DUP))) {
775 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
782 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
783 * in total (for bi-directional DMA), but copy up to what
784 * we can fit into the payload for debug dump purposes.
786 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
788 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
791 /* However, treat copy_size the proper way, we need it below */
792 if (copy_size < IWL_FIRST_TB_SIZE) {
793 copy = IWL_FIRST_TB_SIZE - copy_size;
795 if (copy > cmd->len[i])
802 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
803 iwl_get_cmd_string(trans, cmd->id), group_id,
804 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
805 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
807 /* start the TFD with the minimum copy bytes */
808 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
809 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
810 iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx),
813 /* map first command fragment, if any remains */
814 if (copy_size > tb0_size) {
815 phys_addr = dma_map_single(trans->dev,
816 ((u8 *)&out_cmd->hdr) + tb0_size,
817 copy_size - tb0_size,
819 if (dma_mapping_error(trans->dev, phys_addr)) {
821 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
824 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr,
825 copy_size - tb0_size);
828 /* map the remaining (adjusted) nocopy/dup fragments */
829 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
830 const void *data = cmddata[i];
834 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
837 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
839 phys_addr = dma_map_single(trans->dev, (void *)data,
840 cmdlen[i], DMA_TO_DEVICE);
841 if (dma_mapping_error(trans->dev, phys_addr)) {
843 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
846 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]);
849 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
850 out_meta->flags = cmd->flags;
851 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
852 kzfree(txq->entries[idx].free_buf);
853 txq->entries[idx].free_buf = dup_buf;
855 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
857 /* start timer if queue currently empty */
858 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
859 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
861 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
862 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
863 !trans_pcie->ref_cmd_in_flight) {
864 trans_pcie->ref_cmd_in_flight = true;
865 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
866 iwl_trans_ref(trans);
868 /* Increment and update queue's write index */
869 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
870 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
871 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
874 spin_unlock_irqrestore(&txq->lock, flags2);
881 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
883 static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
884 struct iwl_host_cmd *cmd)
886 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
887 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
888 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
892 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
894 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
896 "Command %s: a command is already active!\n", cmd_str))
899 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
901 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
902 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
903 pm_runtime_active(&trans_pcie->pci_dev->dev),
904 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
906 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
911 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
914 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
915 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
920 ret = wait_event_timeout(trans_pcie->wait_command_queue,
921 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
923 HOST_COMPLETE_TIMEOUT);
925 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
926 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
928 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
929 txq->read_ptr, txq->write_ptr);
931 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
932 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
936 iwl_force_nmi(trans);
937 iwl_trans_fw_error(trans);
942 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
943 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
949 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
950 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
951 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
956 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
957 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
965 if (cmd->flags & CMD_WANT_SKB) {
967 * Cancel the CMD_WANT_SKB flag for the cmd in the
968 * TX cmd queue. Otherwise in case the cmd comes
969 * in later, it will possibly set an invalid
970 * address (cmd->meta.source).
972 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
977 cmd->resp_pkt = NULL;
983 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
984 struct iwl_host_cmd *cmd)
986 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
987 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
988 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
993 if (cmd->flags & CMD_ASYNC) {
996 /* An asynchronous command can not expect an SKB to be set. */
997 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1000 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
1003 "Error sending %s: enqueue_hcmd failed: %d\n",
1004 iwl_get_cmd_string(trans, cmd->id), ret);
1010 return iwl_pcie_gen2_send_hcmd_sync(trans, cmd);
1014 * iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's
1016 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
1018 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1019 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1021 spin_lock_bh(&txq->lock);
1022 while (txq->write_ptr != txq->read_ptr) {
1023 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
1024 txq_id, txq->read_ptr);
1026 if (txq_id != trans_pcie->cmd_queue) {
1027 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1028 struct sk_buff *skb = txq->entries[idx].skb;
1030 if (WARN_ON_ONCE(!skb))
1033 iwl_pcie_free_tso_page(trans_pcie, skb);
1035 iwl_pcie_gen2_free_tfd(trans, txq);
1036 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1038 if (txq->read_ptr == txq->write_ptr) {
1039 unsigned long flags;
1041 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1042 if (txq_id != trans_pcie->cmd_queue) {
1043 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
1045 iwl_trans_unref(trans);
1046 } else if (trans_pcie->ref_cmd_in_flight) {
1047 trans_pcie->ref_cmd_in_flight = false;
1048 IWL_DEBUG_RPM(trans,
1049 "clear ref_cmd_in_flight\n");
1050 iwl_trans_unref(trans);
1052 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1056 while (!skb_queue_empty(&txq->overflow_q)) {
1057 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
1059 iwl_op_mode_free_skb(trans->op_mode, skb);
1062 spin_unlock_bh(&txq->lock);
1064 /* just in case - this queue may have been stopped */
1065 iwl_wake_queue(trans, txq);
1068 static void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
1069 struct iwl_txq *txq)
1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1072 struct device *dev = trans->dev;
1074 /* De-alloc circular buffer of TFDs */
1076 dma_free_coherent(dev,
1077 trans_pcie->tfd_size * txq->n_window,
1078 txq->tfds, txq->dma_addr);
1079 dma_free_coherent(dev,
1080 sizeof(*txq->first_tb_bufs) * txq->n_window,
1081 txq->first_tb_bufs, txq->first_tb_dma);
1084 kfree(txq->entries);
1085 iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl);
1090 * iwl_pcie_txq_free - Deallocate DMA queue.
1091 * @txq: Transmit queue to deallocate.
1093 * Empty queue by removing and destroying all BD's.
1095 * 0-fill, but do not free "txq" descriptor structure.
1097 static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
1099 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1100 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1106 iwl_pcie_gen2_txq_unmap(trans, txq_id);
1108 /* De-alloc array of command/tx buffers */
1109 if (txq_id == trans_pcie->cmd_queue)
1110 for (i = 0; i < txq->n_window; i++) {
1111 kzfree(txq->entries[i].cmd);
1112 kzfree(txq->entries[i].free_buf);
1114 del_timer_sync(&txq->stuck_timer);
1116 iwl_pcie_gen2_txq_free_memory(trans, txq);
1118 trans_pcie->txq[txq_id] = NULL;
1120 clear_bit(txq_id, trans_pcie->queue_used);
1123 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
1124 struct iwl_tx_queue_cfg_cmd *cmd,
1125 int cmd_id, int size,
1126 unsigned int timeout)
1128 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129 struct iwl_tx_queue_cfg_rsp *rsp;
1130 struct iwl_txq *txq;
1131 struct iwl_host_cmd hcmd = {
1133 .len = { sizeof(*cmd) },
1135 .flags = CMD_WANT_SKB,
1140 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
1143 ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl,
1144 (trans->cfg->device_family >=
1145 IWL_DEVICE_FAMILY_22560) ?
1146 sizeof(struct iwl_gen3_bc_tbl) :
1147 sizeof(struct iwlagn_scd_bc_tbl));
1149 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
1154 ret = iwl_pcie_txq_alloc(trans, txq, size, false);
1156 IWL_ERR(trans, "Tx queue alloc failed\n");
1159 ret = iwl_pcie_txq_init(trans, txq, size, false);
1161 IWL_ERR(trans, "Tx queue init failed\n");
1165 txq->wd_timeout = msecs_to_jiffies(timeout);
1167 cmd->tfdq_addr = cpu_to_le64(txq->dma_addr);
1168 cmd->byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma);
1169 cmd->cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(size));
1171 ret = iwl_trans_send_cmd(trans, &hcmd);
1175 if (WARN_ON(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp))) {
1177 goto error_free_resp;
1180 rsp = (void *)hcmd.resp_pkt->data;
1181 qid = le16_to_cpu(rsp->queue_number);
1182 wr_ptr = le16_to_cpu(rsp->write_pointer);
1184 if (qid >= ARRAY_SIZE(trans_pcie->txq)) {
1185 WARN_ONCE(1, "queue index %d unsupported", qid);
1187 goto error_free_resp;
1190 if (test_and_set_bit(qid, trans_pcie->queue_used)) {
1191 WARN_ONCE(1, "queue %d already used", qid);
1193 goto error_free_resp;
1197 trans_pcie->txq[qid] = txq;
1198 wr_ptr &= (trans->cfg->base_params->max_tfd_queue_size - 1);
1200 /* Place first TFD at index corresponding to start sequence number */
1201 txq->read_ptr = wr_ptr;
1202 txq->write_ptr = wr_ptr;
1203 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1204 (txq->write_ptr) | (qid << 16));
1205 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
1207 iwl_free_resp(&hcmd);
1211 iwl_free_resp(&hcmd);
1213 iwl_pcie_gen2_txq_free_memory(trans, txq);
1217 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
1219 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222 * Upon HW Rfkill - we stop the device, and then stop the queues
1223 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1224 * allow the op_mode to call txq_disable after it already called
1227 if (!test_and_clear_bit(queue, trans_pcie->queue_used)) {
1228 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1229 "queue %d not used", queue);
1233 iwl_pcie_gen2_txq_unmap(trans, queue);
1235 iwl_pcie_gen2_txq_free_memory(trans, trans_pcie->txq[queue]);
1236 trans_pcie->txq[queue] = NULL;
1238 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
1241 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
1243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1246 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1248 /* Free all TX queues */
1249 for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) {
1250 if (!trans_pcie->txq[i])
1253 iwl_pcie_gen2_txq_free(trans, i);
1257 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
1259 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1260 struct iwl_txq *cmd_queue;
1261 int txq_id = trans_pcie->cmd_queue, ret;
1263 /* alloc and init the command queue */
1264 if (!trans_pcie->txq[txq_id]) {
1265 cmd_queue = kzalloc(sizeof(*cmd_queue), GFP_KERNEL);
1267 IWL_ERR(trans, "Not enough memory for command queue\n");
1270 trans_pcie->txq[txq_id] = cmd_queue;
1271 ret = iwl_pcie_txq_alloc(trans, cmd_queue, TFD_CMD_SLOTS, true);
1273 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1277 cmd_queue = trans_pcie->txq[txq_id];
1280 ret = iwl_pcie_txq_init(trans, cmd_queue, TFD_CMD_SLOTS, true);
1282 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1285 trans_pcie->txq[txq_id]->id = txq_id;
1286 set_bit(txq_id, trans_pcie->queue_used);
1291 iwl_pcie_gen2_tx_free(trans);