drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  * Copyright(c) 2018 Intel Corporation
   7  *
   8  * Portions of this file are derived from the ipw3945 project, as well
   9  * as portions of the ieee80211 subsystem header files.
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  23  *
  24  * The full GNU General Public License is included in this distribution in the
  25  * file called LICENSE.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <linuxwifi@intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  *****************************************************************************/
  32 #include <linux/etherdevice.h>
  33 #include <linux/ieee80211.h>
  34 #include <linux/slab.h>
  35 #include <linux/sched.h>
  36 #include <linux/pm_runtime.h>
  37 #include <net/ip6_checksum.h>
  38 #include <net/tso.h>
  39
  40 #include "iwl-debug.h"
  41 #include "iwl-csr.h"
  42 #include "iwl-prph.h"
  43 #include "iwl-io.h"
  44 #include "iwl-scd.h"
  45 #include "iwl-op-mode.h"
  46 #include "internal.h"
  47 #include "fw/api/tx.h"
  48
  49 #define IWL_TX_CRC_SIZE 4
  50 #define IWL_TX_DELIMITER_SIZE 4
  51
  52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  53  * DMA services
  54  *
  55  * Theory of operation
  56  *
  57  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  58  * of buffer descriptors, each of which points to one or more data buffers for
  59  * the device to read from or fill.  Driver and device exchange status of each
  60  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  61  * entries in each circular buffer, to protect against confusing empty and full
  62  * queue states.
  63  *
  64  * The device reads or writes the data in the queues via the device's several
  65  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  66  *
  67  * For Tx queue, there are low mark and high mark limits. If, after queuing
  68  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  69  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  70  * Tx queue resumed.
  71  *
  72  ***************************************************/
  73
  74 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
  75 {
  76         unsigned int max;
  77         unsigned int used;
  78
  79         /*
  80          * To avoid ambiguity between empty and completely full queues, there
  81          * should always be less than max_tfd_queue_size elements in the queue.
  82          * If q->n_window is smaller than max_tfd_queue_size, there is no need
  83          * to reserve any queue entries for this purpose.
  84          */
  85         if (q->n_window < trans->cfg->base_params->max_tfd_queue_size)
  86                 max = q->n_window;
  87         else
  88                 max = trans->cfg->base_params->max_tfd_queue_size - 1;
  89
  90         /*
  91          * max_tfd_queue_size is a power of 2, so the following is equivalent to
  92          * modulo by max_tfd_queue_size and is well defined.
  93          */
  94         used = (q->write_ptr - q->read_ptr) &
  95                 (trans->cfg->base_params->max_tfd_queue_size - 1);
  96
  97         if (WARN_ON(used > max))
  98                 return 0;
  99
 100         return max - used;
 101 }
 102
 103 /*
 104  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 105  */
 106 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
 107 {
 108         q->n_window = slots_num;
 109
 110         /* slots_num must be power-of-two size, otherwise
 111          * iwl_pcie_get_cmd_index is broken. */
 112         if (WARN_ON(!is_power_of_2(slots_num)))
 113                 return -EINVAL;
 114
 115         q->low_mark = q->n_window / 4;
 116         if (q->low_mark < 4)
 117                 q->low_mark = 4;
 118
 119         q->high_mark = q->n_window / 8;
 120         if (q->high_mark < 2)
 121                 q->high_mark = 2;
 122
 123         q->write_ptr = 0;
 124         q->read_ptr = 0;
 125
 126         return 0;
 127 }
 128
 129 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 130                            struct iwl_dma_ptr *ptr, size_t size)
 131 {
 132         if (WARN_ON(ptr->addr))
 133                 return -EINVAL;
 134
 135         ptr->addr = dma_alloc_coherent(trans->dev, size,
 136                                        &ptr->dma, GFP_KERNEL);
 137         if (!ptr->addr)
 138                 return -ENOMEM;
 139         ptr->size = size;
 140         return 0;
 141 }
 142
 143 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
 144 {
 145         if (unlikely(!ptr->addr))
 146                 return;
 147
 148         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 149         memset(ptr, 0, sizeof(*ptr));
 150 }
 151
 152 static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
 153 {
 154         struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
 155         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 156         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 157
 158         spin_lock(&txq->lock);
 159         /* check if triggered erroneously */
 160         if (txq->read_ptr == txq->write_ptr) {
 161                 spin_unlock(&txq->lock);
 162                 return;
 163         }
 164         spin_unlock(&txq->lock);
 165
 166         iwl_trans_pcie_log_scd_error(trans, txq);
 167
 168         iwl_force_nmi(trans);
 169 }
 170
 171 /*
 172  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 173  */
 174 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 175                                              struct iwl_txq *txq, u16 byte_cnt,
 176                                              int num_tbs)
 177 {
 178         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 179         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 180         int write_ptr = txq->write_ptr;
 181         int txq_id = txq->id;
 182         u8 sec_ctl = 0;
 183         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 184         __le16 bc_ent;
 185         struct iwl_tx_cmd *tx_cmd =
 186                 (void *)txq->entries[txq->write_ptr].cmd->payload;
 187         u8 sta_id = tx_cmd->sta_id;
 188
 189         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 190
 191         sec_ctl = tx_cmd->sec_ctl;
 192
 193         switch (sec_ctl & TX_CMD_SEC_MSK) {
 194         case TX_CMD_SEC_CCM:
 195                 len += IEEE80211_CCMP_MIC_LEN;
 196                 break;
 197         case TX_CMD_SEC_TKIP:
 198                 len += IEEE80211_TKIP_ICV_LEN;
 199                 break;
 200         case TX_CMD_SEC_WEP:
 201                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 202                 break;
 203         }
 204         if (trans_pcie->bc_table_dword)
 205                 len = DIV_ROUND_UP(len, 4);
 206
 207         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 208                 return;
 209
 210         bc_ent = cpu_to_le16(len | (sta_id << 12));
 211
 212         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 213
 214         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 215                 scd_bc_tbl[txq_id].
 216                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 217 }
 218
 219 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 220                                             struct iwl_txq *txq)
 221 {
 222         struct iwl_trans_pcie *trans_pcie =
 223                 IWL_TRANS_GET_PCIE_TRANS(trans);
 224         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 225         int txq_id = txq->id;
 226         int read_ptr = txq->read_ptr;
 227         u8 sta_id = 0;
 228         __le16 bc_ent;
 229         struct iwl_tx_cmd *tx_cmd =
 230                 (void *)txq->entries[read_ptr].cmd->payload;
 231
 232         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 233
 234         if (txq_id != trans_pcie->cmd_queue)
 235                 sta_id = tx_cmd->sta_id;
 236
 237         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 238
 239         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 240
 241         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 242                 scd_bc_tbl[txq_id].
 243                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 244 }
 245
 246 /*
 247  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 248  */
 249 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 250                                     struct iwl_txq *txq)
 251 {
 252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 253         u32 reg = 0;
 254         int txq_id = txq->id;
 255
 256         lockdep_assert_held(&txq->lock);
 257
 258         /*
 259          * explicitly wake up the NIC if:
 260          * 1. shadow registers aren't enabled
 261          * 2. NIC is woken up for CMD regardless of shadow outside this function
 262          * 3. there is a chance that the NIC is asleep
 263          */
 264         if (!trans->cfg->base_params->shadow_reg_enable &&
 265             txq_id != trans_pcie->cmd_queue &&
 266             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 267                 /*
 268                  * wake up nic if it's powered down ...
 269                  * uCode will wake up, and interrupt us again, so next
 270                  * time we'll skip this part.
 271                  */
 272                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 273
 274                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 275                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 276                                        txq_id, reg);
 277                         iwl_set_bit(trans, CSR_GP_CNTRL,
 278                                     BIT(trans->cfg->csr->flag_mac_access_req));
 279                         txq->need_update = true;
 280                         return;
 281                 }
 282         }
 283
 284         /*
 285          * if not in power-save mode, uCode will never sleep when we're
 286          * trying to tx (during RFKILL, we're not trying to tx).
 287          */
 288         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 289         if (!txq->block)
 290                 iwl_write32(trans, HBUS_TARG_WRPTR,
 291                             txq->write_ptr | (txq_id << 8));
 292 }
 293
 294 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 295 {
 296         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 297         int i;
 298
 299         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 300                 struct iwl_txq *txq = trans_pcie->txq[i];
 301
 302                 if (!test_bit(i, trans_pcie->queue_used))
 303                         continue;
 304
 305                 spin_lock_bh(&txq->lock);
 306                 if (txq->need_update) {
 307                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 308                         txq->need_update = false;
 309                 }
 310                 spin_unlock_bh(&txq->lock);
 311         }
 312 }
 313
 314 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
 315                                                   void *_tfd, u8 idx)
 316 {
 317
 318         if (trans->cfg->use_tfh) {
 319                 struct iwl_tfh_tfd *tfd = _tfd;
 320                 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
 321
 322                 return (dma_addr_t)(le64_to_cpu(tb->addr));
 323         } else {
 324                 struct iwl_tfd *tfd = _tfd;
 325                 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 326                 dma_addr_t addr = get_unaligned_le32(&tb->lo);
 327                 dma_addr_t hi_len;
 328
 329                 if (sizeof(dma_addr_t) <= sizeof(u32))
 330                         return addr;
 331
 332                 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
 333
 334                 /*
 335                  * shift by 16 twice to avoid warnings on 32-bit
 336                  * (where this code never runs anyway due to the
 337                  * if statement above)
 338                  */
 339                 return addr | ((hi_len << 16) << 16);
 340         }
 341 }
 342
 343 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
 344                                        u8 idx, dma_addr_t addr, u16 len)
 345 {
 346         struct iwl_tfd *tfd_fh = (void *)tfd;
 347         struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
 348
 349         u16 hi_n_len = len << 4;
 350
 351         put_unaligned_le32(addr, &tb->lo);
 352         hi_n_len |= iwl_get_dma_hi_addr(addr);
 353
 354         tb->hi_n_len = cpu_to_le16(hi_n_len);
 355
 356         tfd_fh->num_tbs = idx + 1;
 357 }
 358
 359 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
 360 {
 361         if (trans->cfg->use_tfh) {
 362                 struct iwl_tfh_tfd *tfd = _tfd;
 363
 364                 return le16_to_cpu(tfd->num_tbs) & 0x1f;
 365         } else {
 366                 struct iwl_tfd *tfd = _tfd;
 367
 368                 return tfd->num_tbs & 0x1f;
 369         }
 370 }
 371
 372 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 373                                struct iwl_cmd_meta *meta,
 374                                struct iwl_txq *txq, int index)
 375 {
 376         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 377         int i, num_tbs;
 378         void *tfd = iwl_pcie_get_tfd(trans, txq, index);
 379
 380         /* Sanity check on number of chunks */
 381         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 382
 383         if (num_tbs > trans_pcie->max_tbs) {
 384                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 385                 /* @todo issue fatal error, it is quite serious situation */
 386                 return;
 387         }
 388
 389         /* first TB is never freed - it's the bidirectional DMA data */
 390
 391         for (i = 1; i < num_tbs; i++) {
 392                 if (meta->tbs & BIT(i))
 393                         dma_unmap_page(trans->dev,
 394                                        iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
 395                                        iwl_pcie_tfd_tb_get_len(trans, tfd, i),
 396                                        DMA_TO_DEVICE);
 397                 else
 398                         dma_unmap_single(trans->dev,
 399                                          iwl_pcie_tfd_tb_get_addr(trans, tfd,
 400                                                                   i),
 401                                          iwl_pcie_tfd_tb_get_len(trans, tfd,
 402                                                                  i),
 403                                          DMA_TO_DEVICE);
 404         }
 405
 406         meta->tbs = 0;
 407
 408         if (trans->cfg->use_tfh) {
 409                 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
 410
 411                 tfd_fh->num_tbs = 0;
 412         } else {
 413                 struct iwl_tfd *tfd_fh = (void *)tfd;
 414
 415                 tfd_fh->num_tbs = 0;
 416         }
 417
 418 }
 419
 420 /*
 421  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 422  * @trans - transport private data
 423  * @txq - tx queue
 424  * @dma_dir - the direction of the DMA mapping
 425  *
 426  * Does NOT advance any TFD circular buffer read/write indexes
 427  * Does NOT free the TFD itself (which is within circular buffer)
 428  */
 429 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 430 {
 431         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 432          * idx is bounded by n_window
 433          */
 434         int rd_ptr = txq->read_ptr;
 435         int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
 436
 437         lockdep_assert_held(&txq->lock);
 438
 439         /* We have only q->n_window txq->entries, but we use
 440          * TFD_QUEUE_SIZE_MAX tfds
 441          */
 442         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
 443
 444         /* free SKB */
 445         if (txq->entries) {
 446                 struct sk_buff *skb;
 447
 448                 skb = txq->entries[idx].skb;
 449
 450                 /* Can be called from irqs-disabled context
 451                  * If skb is not NULL, it means that the whole queue is being
 452                  * freed and that the queue is not empty - free the skb
 453                  */
 454                 if (skb) {
 455                         iwl_op_mode_free_skb(trans->op_mode, skb);
 456                         txq->entries[idx].skb = NULL;
 457                 }
 458         }
 459 }
 460
 461 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 462                                   dma_addr_t addr, u16 len, bool reset)
 463 {
 464         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 465         void *tfd;
 466         u32 num_tbs;
 467
 468         tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
 469
 470         if (reset)
 471                 memset(tfd, 0, trans_pcie->tfd_size);
 472
 473         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 474
 475         /* Each TFD can point to a maximum max_tbs Tx buffers */
 476         if (num_tbs >= trans_pcie->max_tbs) {
 477                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 478                         trans_pcie->max_tbs);
 479                 return -EINVAL;
 480         }
 481
 482         if (WARN(addr & ~IWL_TX_DMA_MASK,
 483                  "Unaligned address = %llx\n", (unsigned long long)addr))
 484                 return -EINVAL;
 485
 486         iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
 487
 488         return num_tbs;
 489 }
 490
 491 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
 492                        int slots_num, bool cmd_queue)
 493 {
 494         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 495         size_t tfd_sz = trans_pcie->tfd_size *
 496                 trans->cfg->base_params->max_tfd_queue_size;
 497         size_t tb0_buf_sz;
 498         int i;
 499
 500         if (WARN_ON(txq->entries || txq->tfds))
 501                 return -EINVAL;
 502
 503         if (trans->cfg->use_tfh)
 504                 tfd_sz = trans_pcie->tfd_size * slots_num;
 505
 506         timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
 507         txq->trans_pcie = trans_pcie;
 508
 509         txq->n_window = slots_num;
 510
 511         txq->entries = kcalloc(slots_num,
 512                                sizeof(struct iwl_pcie_txq_entry),
 513                                GFP_KERNEL);
 514
 515         if (!txq->entries)
 516                 goto error;
 517
 518         if (cmd_queue)
 519                 for (i = 0; i < slots_num; i++) {
 520                         txq->entries[i].cmd =
 521                                 kmalloc(sizeof(struct iwl_device_cmd),
 522                                         GFP_KERNEL);
 523                         if (!txq->entries[i].cmd)
 524                                 goto error;
 525                 }
 526
 527         /* Circular buffer of transmit frame descriptors (TFDs),
 528          * shared with device */
 529         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 530                                        &txq->dma_addr, GFP_KERNEL);
 531         if (!txq->tfds)
 532                 goto error;
 533
 534         BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
 535
 536         tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
 537
 538         txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
 539                                               &txq->first_tb_dma,
 540                                               GFP_KERNEL);
 541         if (!txq->first_tb_bufs)
 542                 goto err_free_tfds;
 543
 544         return 0;
 545 err_free_tfds:
 546         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
 547 error:
 548         if (txq->entries && cmd_queue)
 549                 for (i = 0; i < slots_num; i++)
 550                         kfree(txq->entries[i].cmd);
 551         kfree(txq->entries);
 552         txq->entries = NULL;
 553
 554         return -ENOMEM;
 555
 556 }
 557
 558 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 559                       int slots_num, bool cmd_queue)
 560 {
 561         int ret;
 562         u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size;
 563
 564         txq->need_update = false;
 565
 566         /* max_tfd_queue_size must be power-of-two size, otherwise
 567          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 568         if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
 569                       "Max tfd queue size must be a power of two, but is %d",
 570                       tfd_queue_max_size))
 571                 return -EINVAL;
 572
 573         /* Initialize queue's high/low-water marks, and head/tail indexes */
 574         ret = iwl_queue_init(txq, slots_num);
 575         if (ret)
 576                 return ret;
 577
 578         spin_lock_init(&txq->lock);
 579
 580         if (cmd_queue) {
 581                 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
 582
 583                 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
 584         }
 585
 586         __skb_queue_head_init(&txq->overflow_q);
 587
 588         return 0;
 589 }
 590
 591 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
 592                             struct sk_buff *skb)
 593 {
 594         struct page **page_ptr;
 595
 596         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
 597
 598         if (*page_ptr) {
 599                 __free_page(*page_ptr);
 600                 *page_ptr = NULL;
 601         }
 602 }
 603
 604 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 605 {
 606         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 607
 608         lockdep_assert_held(&trans_pcie->reg_lock);
 609
 610         if (trans_pcie->ref_cmd_in_flight) {
 611                 trans_pcie->ref_cmd_in_flight = false;
 612                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
 613                 iwl_trans_unref(trans);
 614         }
 615
 616         if (!trans->cfg->base_params->apmg_wake_up_wa)
 617                 return;
 618         if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
 619                 return;
 620
 621         trans_pcie->cmd_hold_nic_awake = false;
 622         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 623                                    BIT(trans->cfg->csr->flag_mac_access_req));
 624 }
 625
 626 /*
 627  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 628  */
 629 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 630 {
 631         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 632         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 633
 634         if (!txq) {
 635                 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
 636                 return;
 637         }
 638
 639         spin_lock_bh(&txq->lock);
 640         while (txq->write_ptr != txq->read_ptr) {
 641                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 642                                    txq_id, txq->read_ptr);
 643
 644                 if (txq_id != trans_pcie->cmd_queue) {
 645                         struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
 646
 647                         if (WARN_ON_ONCE(!skb))
 648                                 continue;
 649
 650                         iwl_pcie_free_tso_page(trans_pcie, skb);
 651                 }
 652                 iwl_pcie_txq_free_tfd(trans, txq);
 653                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
 654
 655                 if (txq->read_ptr == txq->write_ptr) {
 656                         unsigned long flags;
 657
 658                         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
 659                         if (txq_id != trans_pcie->cmd_queue) {
 660                                 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
 661                                               txq->id);
 662                                 iwl_trans_unref(trans);
 663                         } else {
 664                                 iwl_pcie_clear_cmd_in_flight(trans);
 665                         }
 666                         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
 667                 }
 668         }
 669
 670         while (!skb_queue_empty(&txq->overflow_q)) {
 671                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 672
 673                 iwl_op_mode_free_skb(trans->op_mode, skb);
 674         }
 675
 676         spin_unlock_bh(&txq->lock);
 677
 678         /* just in case - this queue may have been stopped */
 679         iwl_wake_queue(trans, txq);
 680 }
 681
 682 /*
 683  * iwl_pcie_txq_free - Deallocate DMA queue.
 684  * @txq: Transmit queue to deallocate.
 685  *
 686  * Empty queue by removing and destroying all BD's.
 687  * Free all buffers.
 688  * 0-fill, but do not free "txq" descriptor structure.
 689  */
 690 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 691 {
 692         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 693         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 694         struct device *dev = trans->dev;
 695         int i;
 696
 697         if (WARN_ON(!txq))
 698                 return;
 699
 700         iwl_pcie_txq_unmap(trans, txq_id);
 701
 702         /* De-alloc array of command/tx buffers */
 703         if (txq_id == trans_pcie->cmd_queue)
 704                 for (i = 0; i < txq->n_window; i++) {
 705                         kzfree(txq->entries[i].cmd);
 706                         kzfree(txq->entries[i].free_buf);
 707                 }
 708
 709         /* De-alloc circular buffer of TFDs */
 710         if (txq->tfds) {
 711                 dma_free_coherent(dev,
 712                                   trans_pcie->tfd_size *
 713                                   trans->cfg->base_params->max_tfd_queue_size,
 714                                   txq->tfds, txq->dma_addr);
 715                 txq->dma_addr = 0;
 716                 txq->tfds = NULL;
 717
 718                 dma_free_coherent(dev,
 719                                   sizeof(*txq->first_tb_bufs) * txq->n_window,
 720                                   txq->first_tb_bufs, txq->first_tb_dma);
 721         }
 722
 723         kfree(txq->entries);
 724         txq->entries = NULL;
 725
 726         del_timer_sync(&txq->stuck_timer);
 727
 728         /* 0-fill queue descriptor structure */
 729         memset(txq, 0, sizeof(*txq));
 730 }
 731
 732 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 733 {
 734         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 735         int nq = trans->cfg->base_params->num_of_queues;
 736         int chan;
 737         u32 reg_val;
 738         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 739                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 740
 741         /* make sure all queue are not stopped/used */
 742         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 743         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 744
 745         trans_pcie->scd_base_addr =
 746                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 747
 748         WARN_ON(scd_base_addr != 0 &&
 749                 scd_base_addr != trans_pcie->scd_base_addr);
 750
 751         /* reset context data, TX status and translation data */
 752         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 753                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 754                             NULL, clear_dwords);
 755
 756         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 757                        trans_pcie->scd_bc_tbls.dma >> 10);
 758
 759         /* The chain extension of the SCD doesn't work well. This feature is
 760          * enabled by default by the HW, so we need to disable it manually.
 761          */
 762         if (trans->cfg->base_params->scd_chain_ext_wa)
 763                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 764
 765         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 766                                 trans_pcie->cmd_fifo,
 767                                 trans_pcie->cmd_q_wdg_timeout);
 768
 769         /* Activate all Tx DMA/FIFO channels */
 770         iwl_scd_activate_fifos(trans);
 771
 772         /* Enable DMA channel */
 773         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 774                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 775                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 776                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 777
 778         /* Update FH chicken bits */
 779         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 780         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 781                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 782
 783         /* Enable L1-Active */
 784         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 785                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 786                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 787 }
 788
 789 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 790 {
 791         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 792         int txq_id;
 793
 794         /*
 795          * we should never get here in gen2 trans mode return early to avoid
 796          * having invalid accesses
 797          */
 798         if (WARN_ON_ONCE(trans->cfg->gen2))
 799                 return;
 800
 801         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 802              txq_id++) {
 803                 struct iwl_txq *txq = trans_pcie->txq[txq_id];
 804                 if (trans->cfg->use_tfh)
 805                         iwl_write_direct64(trans,
 806                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 807                                            txq->dma_addr);
 808                 else
 809                         iwl_write_direct32(trans,
 810                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 811                                            txq->dma_addr >> 8);
 812                 iwl_pcie_txq_unmap(trans, txq_id);
 813                 txq->read_ptr = 0;
 814                 txq->write_ptr = 0;
 815         }
 816
 817         /* Tell NIC where to find the "keep warm" buffer */
 818         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 819                            trans_pcie->kw.dma >> 4);
 820
 821         /*
 822          * Send 0 as the scd_base_addr since the device may have be reset
 823          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 824          * contain garbage.
 825          */
 826         iwl_pcie_tx_start(trans, 0);
 827 }
 828
 829 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 830 {
 831         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 832         unsigned long flags;
 833         int ch, ret;
 834         u32 mask = 0;
 835
 836         spin_lock(&trans_pcie->irq_lock);
 837
 838         if (!iwl_trans_grab_nic_access(trans, &flags))
 839                 goto out;
 840
 841         /* Stop each Tx DMA channel */
 842         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 843                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 844                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 845         }
 846
 847         /* Wait for DMA channels to be idle */
 848         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 849         if (ret < 0)
 850                 IWL_ERR(trans,
 851                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 852                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 853
 854         iwl_trans_release_nic_access(trans, &flags);
 855
 856 out:
 857         spin_unlock(&trans_pcie->irq_lock);
 858 }
 859
 860 /*
 861  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 862  */
 863 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 864 {
 865         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 866         int txq_id;
 867
 868         /* Turn off all Tx DMA fifos */
 869         iwl_scd_deactivate_fifos(trans);
 870
 871         /* Turn off all Tx DMA channels */
 872         iwl_pcie_tx_stop_fh(trans);
 873
 874         /*
 875          * This function can be called before the op_mode disabled the
 876          * queues. This happens when we have an rfkill interrupt.
 877          * Since we stop Tx altogether - mark the queues as stopped.
 878          */
 879         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 880         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 881
 882         /* This can happen: start_hw, stop_device */
 883         if (!trans_pcie->txq_memory)
 884                 return 0;
 885
 886         /* Unmap DMA from host system and free skb's */
 887         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 888              txq_id++)
 889                 iwl_pcie_txq_unmap(trans, txq_id);
 890
 891         return 0;
 892 }
 893
 894 /*
 895  * iwl_trans_tx_free - Free TXQ Context
 896  *
 897  * Destroy all TX DMA queues and structures
 898  */
 899 void iwl_pcie_tx_free(struct iwl_trans *trans)
 900 {
 901         int txq_id;
 902         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 903
 904         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 905
 906         /* Tx queues */
 907         if (trans_pcie->txq_memory) {
 908                 for (txq_id = 0;
 909                      txq_id < trans->cfg->base_params->num_of_queues;
 910                      txq_id++) {
 911                         iwl_pcie_txq_free(trans, txq_id);
 912                         trans_pcie->txq[txq_id] = NULL;
 913                 }
 914         }
 915
 916         kfree(trans_pcie->txq_memory);
 917         trans_pcie->txq_memory = NULL;
 918
 919         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 920
 921         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 922 }
 923
 924 /*
 925  * iwl_pcie_tx_alloc - allocate TX context
 926  * Allocate all Tx DMA structures and initialize them
 927  */
 928 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 929 {
 930         int ret;
 931         int txq_id, slots_num;
 932         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 933         u16 bc_tbls_size = trans->cfg->base_params->num_of_queues;
 934
 935         bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
 936                 sizeof(struct iwl_gen3_bc_tbl) :
 937                 sizeof(struct iwlagn_scd_bc_tbl);
 938
 939         /*It is not allowed to alloc twice, so warn when this happens.
 940          * We cannot rely on the previous allocation, so free and fail */
 941         if (WARN_ON(trans_pcie->txq_memory)) {
 942                 ret = -EINVAL;
 943                 goto error;
 944         }
 945
 946         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 947                                      bc_tbls_size);
 948         if (ret) {
 949                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 950                 goto error;
 951         }
 952
 953         /* Alloc keep-warm buffer */
 954         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 955         if (ret) {
 956                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 957                 goto error;
 958         }
 959
 960         trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
 961                                          sizeof(struct iwl_txq), GFP_KERNEL);
 962         if (!trans_pcie->txq_memory) {
 963                 IWL_ERR(trans, "Not enough memory for txq\n");
 964                 ret = -ENOMEM;
 965                 goto error;
 966         }
 967
 968         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 969         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 970              txq_id++) {
 971                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
 972
 973                 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 974                 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
 975                 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
 976                                          slots_num, cmd_queue);
 977                 if (ret) {
 978                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 979                         goto error;
 980                 }
 981                 trans_pcie->txq[txq_id]->id = txq_id;
 982         }
 983
 984         return 0;
 985
 986 error:
 987         iwl_pcie_tx_free(trans);
 988
 989         return ret;
 990 }
 991
 992 int iwl_pcie_tx_init(struct iwl_trans *trans)
 993 {
 994         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 995         int ret;
 996         int txq_id, slots_num;
 997         bool alloc = false;
 998
 999         if (!trans_pcie->txq_memory) {
1000                 ret = iwl_pcie_tx_alloc(trans);
1001                 if (ret)
1002                         goto error;
1003                 alloc = true;
1004         }
1005
1006         spin_lock(&trans_pcie->irq_lock);
1007
1008         /* Turn off all Tx DMA fifos */
1009         iwl_scd_deactivate_fifos(trans);
1010
1011         /* Tell NIC where to find the "keep warm" buffer */
1012         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1013                            trans_pcie->kw.dma >> 4);
1014
1015         spin_unlock(&trans_pcie->irq_lock);
1016
1017         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1018         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1019              txq_id++) {
1020                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1021
1022                 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1023                 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1024                                         slots_num, cmd_queue);
1025                 if (ret) {
1026                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1027                         goto error;
1028                 }
1029
1030                 /*
1031                  * Tell nic where to find circular buffer of TFDs for a
1032                  * given Tx queue, and enable the DMA channel used for that
1033                  * queue.
1034                  * Circular buffer (TFD queue in DRAM) physical base address
1035                  */
1036                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1037                                    trans_pcie->txq[txq_id]->dma_addr >> 8);
1038         }
1039
1040         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1041         if (trans->cfg->base_params->num_of_queues > 20)
1042                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1043                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
1044
1045         return 0;
1046 error:
1047         /*Upon error, free only if we allocated something */
1048         if (alloc)
1049                 iwl_pcie_tx_free(trans);
1050         return ret;
1051 }
1052
1053 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1054 {
1055         lockdep_assert_held(&txq->lock);
1056
1057         if (!txq->wd_timeout)
1058                 return;
1059
1060         /*
1061          * station is asleep and we send data - that must
1062          * be uAPSD or PS-Poll. Don't rearm the timer.
1063          */
1064         if (txq->frozen)
1065                 return;
1066
1067         /*
1068          * if empty delete timer, otherwise move timer forward
1069          * since we're making progress on this queue
1070          */
1071         if (txq->read_ptr == txq->write_ptr)
1072                 del_timer(&txq->stuck_timer);
1073         else
1074                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1075 }
1076
1077 /* Frees buffers until index _not_ inclusive */
1078 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1079                             struct sk_buff_head *skbs)
1080 {
1081         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1082         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1083         int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1084         int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1085         int last_to_free;
1086
1087         /* This function is not meant to release cmd queue*/
1088         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1089                 return;
1090
1091         spin_lock_bh(&txq->lock);
1092
1093         if (!test_bit(txq_id, trans_pcie->queue_used)) {
1094                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1095                                     txq_id, ssn);
1096                 goto out;
1097         }
1098
1099         if (read_ptr == tfd_num)
1100                 goto out;
1101
1102         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1103                            txq_id, txq->read_ptr, tfd_num, ssn);
1104
1105         /*Since we free until index _not_ inclusive, the one before index is
1106          * the last we will free. This one must be used */
1107         last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1108
1109         if (!iwl_queue_used(txq, last_to_free)) {
1110                 IWL_ERR(trans,
1111                         "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1112                         __func__, txq_id, last_to_free,
1113                         trans->cfg->base_params->max_tfd_queue_size,
1114                         txq->write_ptr, txq->read_ptr);
1115                 goto out;
1116         }
1117
1118         if (WARN_ON(!skb_queue_empty(skbs)))
1119                 goto out;
1120
1121         for (;
1122              read_ptr != tfd_num;
1123              txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1124              read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1125                 struct sk_buff *skb = txq->entries[read_ptr].skb;
1126
1127                 if (WARN_ON_ONCE(!skb))
1128                         continue;
1129
1130                 iwl_pcie_free_tso_page(trans_pcie, skb);
1131
1132                 __skb_queue_tail(skbs, skb);
1133
1134                 txq->entries[read_ptr].skb = NULL;
1135
1136                 if (!trans->cfg->use_tfh)
1137                         iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1138
1139                 iwl_pcie_txq_free_tfd(trans, txq);
1140         }
1141
1142         iwl_pcie_txq_progress(txq);
1143
1144         if (iwl_queue_space(trans, txq) > txq->low_mark &&
1145             test_bit(txq_id, trans_pcie->queue_stopped)) {
1146                 struct sk_buff_head overflow_skbs;
1147
1148                 __skb_queue_head_init(&overflow_skbs);
1149                 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1150
1151                 /*
1152                  * This is tricky: we are in reclaim path which is non
1153                  * re-entrant, so noone will try to take the access the
1154                  * txq data from that path. We stopped tx, so we can't
1155                  * have tx as well. Bottom line, we can unlock and re-lock
1156                  * later.
1157                  */
1158                 spin_unlock_bh(&txq->lock);
1159
1160                 while (!skb_queue_empty(&overflow_skbs)) {
1161                         struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1162                         struct iwl_device_cmd *dev_cmd_ptr;
1163
1164                         dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1165                                                  trans_pcie->dev_cmd_offs);
1166
1167                         /*
1168                          * Note that we can very well be overflowing again.
1169                          * In that case, iwl_queue_space will be small again
1170                          * and we won't wake mac80211's queue.
1171                          */
1172                         iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1173                 }
1174                 spin_lock_bh(&txq->lock);
1175
1176                 if (iwl_queue_space(trans, txq) > txq->low_mark)
1177                         iwl_wake_queue(trans, txq);
1178         }
1179
1180         if (txq->read_ptr == txq->write_ptr) {
1181                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1182                 iwl_trans_unref(trans);
1183         }
1184
1185 out:
1186         spin_unlock_bh(&txq->lock);
1187 }
1188
1189 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1190                                       const struct iwl_host_cmd *cmd)
1191 {
1192         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1193         const struct iwl_cfg *cfg = trans->cfg;
1194         int ret;
1195
1196         lockdep_assert_held(&trans_pcie->reg_lock);
1197
1198         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1199             !trans_pcie->ref_cmd_in_flight) {
1200                 trans_pcie->ref_cmd_in_flight = true;
1201                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1202                 iwl_trans_ref(trans);
1203         }
1204
1205         /*
1206          * wake up the NIC to make sure that the firmware will see the host
1207          * command - we will let the NIC sleep once all the host commands
1208          * returned. This needs to be done only on NICs that have
1209          * apmg_wake_up_wa set.
1210          */
1211         if (cfg->base_params->apmg_wake_up_wa &&
1212             !trans_pcie->cmd_hold_nic_awake) {
1213                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1214                                          BIT(cfg->csr->flag_mac_access_req));
1215
1216                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1217                                    BIT(cfg->csr->flag_val_mac_access_en),
1218                                    (BIT(cfg->csr->flag_mac_clock_ready) |
1219                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1220                                    15000);
1221                 if (ret < 0) {
1222                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1223                                         BIT(cfg->csr->flag_mac_access_req));
1224                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1225                         return -EIO;
1226                 }
1227                 trans_pcie->cmd_hold_nic_awake = true;
1228         }
1229
1230         return 0;
1231 }
1232
1233 /*
1234  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1235  *
1236  * When FW advances 'R' index, all entries between old and new 'R' index
1237  * need to be reclaimed. As result, some free space forms.  If there is
1238  * enough free space (> low mark), wake the stack that feeds us.
1239  */
1240 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1241 {
1242         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1244         unsigned long flags;
1245         int nfreed = 0;
1246         u16 r;
1247
1248         lockdep_assert_held(&txq->lock);
1249
1250         idx = iwl_pcie_get_cmd_index(txq, idx);
1251         r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1252
1253         if (idx >= trans->cfg->base_params->max_tfd_queue_size ||
1254             (!iwl_queue_used(txq, idx))) {
1255                 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1256                           "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1257                           __func__, txq_id, idx,
1258                           trans->cfg->base_params->max_tfd_queue_size,
1259                           txq->write_ptr, txq->read_ptr);
1260                 return;
1261         }
1262
1263         for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1264              r = iwl_queue_inc_wrap(trans, r)) {
1265                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1266
1267                 if (nfreed++ > 0) {
1268                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1269                                 idx, txq->write_ptr, r);
1270                         iwl_force_nmi(trans);
1271                 }
1272         }
1273
1274         if (txq->read_ptr == txq->write_ptr) {
1275                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1276                 iwl_pcie_clear_cmd_in_flight(trans);
1277                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1278         }
1279
1280         iwl_pcie_txq_progress(txq);
1281 }
1282
1283 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1284                                  u16 txq_id)
1285 {
1286         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287         u32 tbl_dw_addr;
1288         u32 tbl_dw;
1289         u16 scd_q2ratid;
1290
1291         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1292
1293         tbl_dw_addr = trans_pcie->scd_base_addr +
1294                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1295
1296         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1297
1298         if (txq_id & 0x1)
1299                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1300         else
1301                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1302
1303         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1304
1305         return 0;
1306 }
1307
1308 /* Receiver address (actually, Rx station's index into station table),
1309  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1310 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1311
1312 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1313                                const struct iwl_trans_txq_scd_cfg *cfg,
1314                                unsigned int wdg_timeout)
1315 {
1316         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1317         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1318         int fifo = -1;
1319         bool scd_bug = false;
1320
1321         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1322                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1323
1324         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1325
1326         if (cfg) {
1327                 fifo = cfg->fifo;
1328
1329                 /* Disable the scheduler prior configuring the cmd queue */
1330                 if (txq_id == trans_pcie->cmd_queue &&
1331                     trans_pcie->scd_set_active)
1332                         iwl_scd_enable_set_active(trans, 0);
1333
1334                 /* Stop this Tx queue before configuring it */
1335                 iwl_scd_txq_set_inactive(trans, txq_id);
1336
1337                 /* Set this queue as a chain-building queue unless it is CMD */
1338                 if (txq_id != trans_pcie->cmd_queue)
1339                         iwl_scd_txq_set_chain(trans, txq_id);
1340
1341                 if (cfg->aggregate) {
1342                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1343
1344                         /* Map receiver-address / traffic-ID to this queue */
1345                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1346
1347                         /* enable aggregations for the queue */
1348                         iwl_scd_txq_enable_agg(trans, txq_id);
1349                         txq->ampdu = true;
1350                 } else {
1351                         /*
1352                          * disable aggregations for the queue, this will also
1353                          * make the ra_tid mapping configuration irrelevant
1354                          * since it is now a non-AGG queue.
1355                          */
1356                         iwl_scd_txq_disable_agg(trans, txq_id);
1357
1358                         ssn = txq->read_ptr;
1359                 }
1360         } else {
1361                 /*
1362                  * If we need to move the SCD write pointer by steps of
1363                  * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1364                  * the op_mode know by returning true later.
1365                  * Do this only in case cfg is NULL since this trick can
1366                  * be done only if we have DQA enabled which is true for mvm
1367                  * only. And mvm never sets a cfg pointer.
1368                  * This is really ugly, but this is the easiest way out for
1369                  * this sad hardware issue.
1370                  * This bug has been fixed on devices 9000 and up.
1371                  */
1372                 scd_bug = !trans->cfg->mq_rx_supported &&
1373                         !((ssn - txq->write_ptr) & 0x3f) &&
1374                         (ssn != txq->write_ptr);
1375                 if (scd_bug)
1376                         ssn++;
1377         }
1378
1379         /* Place first TFD at index corresponding to start sequence number.
1380          * Assumes that ssn_idx is valid (!= 0xFFF) */
1381         txq->read_ptr = (ssn & 0xff);
1382         txq->write_ptr = (ssn & 0xff);
1383         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1384                            (ssn & 0xff) | (txq_id << 8));
1385
1386         if (cfg) {
1387                 u8 frame_limit = cfg->frame_limit;
1388
1389                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1390
1391                 /* Set up Tx window size and frame limit for this queue */
1392                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1393                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1394                 iwl_trans_write_mem32(trans,
1395                         trans_pcie->scd_base_addr +
1396                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1397                         SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1398                         SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1399
1400                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1401                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1402                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1403                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1404                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1405                                SCD_QUEUE_STTS_REG_MSK);
1406
1407                 /* enable the scheduler for this queue (only) */
1408                 if (txq_id == trans_pcie->cmd_queue &&
1409                     trans_pcie->scd_set_active)
1410                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1411
1412                 IWL_DEBUG_TX_QUEUES(trans,
1413                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1414                                     txq_id, fifo, ssn & 0xff);
1415         } else {
1416                 IWL_DEBUG_TX_QUEUES(trans,
1417                                     "Activate queue %d WrPtr: %d\n",
1418                                     txq_id, ssn & 0xff);
1419         }
1420
1421         return scd_bug;
1422 }
1423
1424 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1425                                         bool shared_mode)
1426 {
1427         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1428         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1429
1430         txq->ampdu = !shared_mode;
1431 }
1432
1433 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1434                                 bool configure_scd)
1435 {
1436         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1437         u32 stts_addr = trans_pcie->scd_base_addr +
1438                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1439         static const u32 zero_val[4] = {};
1440
1441         trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1442         trans_pcie->txq[txq_id]->frozen = false;
1443
1444         /*
1445          * Upon HW Rfkill - we stop the device, and then stop the queues
1446          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1447          * allow the op_mode to call txq_disable after it already called
1448          * stop_device.
1449          */
1450         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1451                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1452                           "queue %d not used", txq_id);
1453                 return;
1454         }
1455
1456         if (configure_scd) {
1457                 iwl_scd_txq_set_inactive(trans, txq_id);
1458
1459                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1460                                     ARRAY_SIZE(zero_val));
1461         }
1462
1463         iwl_pcie_txq_unmap(trans, txq_id);
1464         trans_pcie->txq[txq_id]->ampdu = false;
1465
1466         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1467 }
1468
1469 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1470
1471 /*
1472  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1473  * @priv: device private data point
1474  * @cmd: a pointer to the ucode command structure
1475  *
1476  * The function returns < 0 values to indicate the operation
1477  * failed. On success, it returns the index (>= 0) of command in the
1478  * command queue.
1479  */
1480 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1481                                  struct iwl_host_cmd *cmd)
1482 {
1483         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1484         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1485         struct iwl_device_cmd *out_cmd;
1486         struct iwl_cmd_meta *out_meta;
1487         unsigned long flags;
1488         void *dup_buf = NULL;
1489         dma_addr_t phys_addr;
1490         int idx;
1491         u16 copy_size, cmd_size, tb0_size;
1492         bool had_nocopy = false;
1493         u8 group_id = iwl_cmd_groupid(cmd->id);
1494         int i, ret;
1495         u32 cmd_pos;
1496         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1497         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1498         unsigned long flags2;
1499
1500         if (WARN(!trans->wide_cmd_header &&
1501                  group_id > IWL_ALWAYS_LONG_GROUP,
1502                  "unsupported wide command %#x\n", cmd->id))
1503                 return -EINVAL;
1504
1505         if (group_id != 0) {
1506                 copy_size = sizeof(struct iwl_cmd_header_wide);
1507                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1508         } else {
1509                 copy_size = sizeof(struct iwl_cmd_header);
1510                 cmd_size = sizeof(struct iwl_cmd_header);
1511         }
1512
1513         /* need one for the header if the first is NOCOPY */
1514         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1515
1516         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1517                 cmddata[i] = cmd->data[i];
1518                 cmdlen[i] = cmd->len[i];
1519
1520                 if (!cmd->len[i])
1521                         continue;
1522
1523                 /* need at least IWL_FIRST_TB_SIZE copied */
1524                 if (copy_size < IWL_FIRST_TB_SIZE) {
1525                         int copy = IWL_FIRST_TB_SIZE - copy_size;
1526
1527                         if (copy > cmdlen[i])
1528                                 copy = cmdlen[i];
1529                         cmdlen[i] -= copy;
1530                         cmddata[i] += copy;
1531                         copy_size += copy;
1532                 }
1533
1534                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1535                         had_nocopy = true;
1536                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1537                                 idx = -EINVAL;
1538                                 goto free_dup_buf;
1539                         }
1540                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1541                         /*
1542                          * This is also a chunk that isn't copied
1543                          * to the static buffer so set had_nocopy.
1544                          */
1545                         had_nocopy = true;
1546
1547                         /* only allowed once */
1548                         if (WARN_ON(dup_buf)) {
1549                                 idx = -EINVAL;
1550                                 goto free_dup_buf;
1551                         }
1552
1553                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1554                                           GFP_ATOMIC);
1555                         if (!dup_buf)
1556                                 return -ENOMEM;
1557                 } else {
1558                         /* NOCOPY must not be followed by normal! */
1559                         if (WARN_ON(had_nocopy)) {
1560                                 idx = -EINVAL;
1561                                 goto free_dup_buf;
1562                         }
1563                         copy_size += cmdlen[i];
1564                 }
1565                 cmd_size += cmd->len[i];
1566         }
1567
1568         /*
1569          * If any of the command structures end up being larger than
1570          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1571          * allocated into separate TFDs, then we will need to
1572          * increase the size of the buffers.
1573          */
1574         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1575                  "Command %s (%#x) is too large (%d bytes)\n",
1576                  iwl_get_cmd_string(trans, cmd->id),
1577                  cmd->id, copy_size)) {
1578                 idx = -EINVAL;
1579                 goto free_dup_buf;
1580         }
1581
1582         spin_lock_irqsave(&txq->lock, flags2);
1583
1584         if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1585                 spin_unlock_irqrestore(&txq->lock, flags2);
1586
1587                 IWL_ERR(trans, "No space in command queue\n");
1588                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1589                 idx = -ENOSPC;
1590                 goto free_dup_buf;
1591         }
1592
1593         idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1594         out_cmd = txq->entries[idx].cmd;
1595         out_meta = &txq->entries[idx].meta;
1596
1597         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1598         if (cmd->flags & CMD_WANT_SKB)
1599                 out_meta->source = cmd;
1600
1601         /* set up the header */
1602         if (group_id != 0) {
1603                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1604                 out_cmd->hdr_wide.group_id = group_id;
1605                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1606                 out_cmd->hdr_wide.length =
1607                         cpu_to_le16(cmd_size -
1608                                     sizeof(struct iwl_cmd_header_wide));
1609                 out_cmd->hdr_wide.reserved = 0;
1610                 out_cmd->hdr_wide.sequence =
1611                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1612                                                  INDEX_TO_SEQ(txq->write_ptr));
1613
1614                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1615                 copy_size = sizeof(struct iwl_cmd_header_wide);
1616         } else {
1617                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1618                 out_cmd->hdr.sequence =
1619                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1620                                                  INDEX_TO_SEQ(txq->write_ptr));
1621                 out_cmd->hdr.group_id = 0;
1622
1623                 cmd_pos = sizeof(struct iwl_cmd_header);
1624                 copy_size = sizeof(struct iwl_cmd_header);
1625         }
1626
1627         /* and copy the data that needs to be copied */
1628         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1629                 int copy;
1630
1631                 if (!cmd->len[i])
1632                         continue;
1633
1634                 /* copy everything if not nocopy/dup */
1635                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1636                                            IWL_HCMD_DFL_DUP))) {
1637                         copy = cmd->len[i];
1638
1639                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1640                         cmd_pos += copy;
1641                         copy_size += copy;
1642                         continue;
1643                 }
1644
1645                 /*
1646                  * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1647                  * in total (for bi-directional DMA), but copy up to what
1648                  * we can fit into the payload for debug dump purposes.
1649                  */
1650                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1651
1652                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1653                 cmd_pos += copy;
1654
1655                 /* However, treat copy_size the proper way, we need it below */
1656                 if (copy_size < IWL_FIRST_TB_SIZE) {
1657                         copy = IWL_FIRST_TB_SIZE - copy_size;
1658
1659                         if (copy > cmd->len[i])
1660                                 copy = cmd->len[i];
1661                         copy_size += copy;
1662                 }
1663         }
1664
1665         IWL_DEBUG_HC(trans,
1666                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1667                      iwl_get_cmd_string(trans, cmd->id),
1668                      group_id, out_cmd->hdr.cmd,
1669                      le16_to_cpu(out_cmd->hdr.sequence),
1670                      cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1671
1672         /* start the TFD with the minimum copy bytes */
1673         tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1674         memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1675         iwl_pcie_txq_build_tfd(trans, txq,
1676                                iwl_pcie_get_first_tb_dma(txq, idx),
1677                                tb0_size, true);
1678
1679         /* map first command fragment, if any remains */
1680         if (copy_size > tb0_size) {
1681                 phys_addr = dma_map_single(trans->dev,
1682                                            ((u8 *)&out_cmd->hdr) + tb0_size,
1683                                            copy_size - tb0_size,
1684                                            DMA_TO_DEVICE);
1685                 if (dma_mapping_error(trans->dev, phys_addr)) {
1686                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1687                                            txq->write_ptr);
1688                         idx = -ENOMEM;
1689                         goto out;
1690                 }
1691
1692                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1693                                        copy_size - tb0_size, false);
1694         }
1695
1696         /* map the remaining (adjusted) nocopy/dup fragments */
1697         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1698                 const void *data = cmddata[i];
1699
1700                 if (!cmdlen[i])
1701                         continue;
1702                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1703                                            IWL_HCMD_DFL_DUP)))
1704                         continue;
1705                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1706                         data = dup_buf;
1707                 phys_addr = dma_map_single(trans->dev, (void *)data,
1708                                            cmdlen[i], DMA_TO_DEVICE);
1709                 if (dma_mapping_error(trans->dev, phys_addr)) {
1710                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1711                                            txq->write_ptr);
1712                         idx = -ENOMEM;
1713                         goto out;
1714                 }
1715
1716                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1717         }
1718
1719         BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1720         out_meta->flags = cmd->flags;
1721         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1722                 kzfree(txq->entries[idx].free_buf);
1723         txq->entries[idx].free_buf = dup_buf;
1724
1725         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1726
1727         /* start timer if queue currently empty */
1728         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1729                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1730
1731         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1732         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1733         if (ret < 0) {
1734                 idx = ret;
1735                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1736                 goto out;
1737         }
1738
1739         /* Increment and update queue's write index */
1740         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1741         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1742
1743         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1744
1745  out:
1746         spin_unlock_irqrestore(&txq->lock, flags2);
1747  free_dup_buf:
1748         if (idx < 0)
1749                 kfree(dup_buf);
1750         return idx;
1751 }
1752
1753 /*
1754  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1755  * @rxb: Rx buffer to reclaim
1756  */
1757 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1758                             struct iwl_rx_cmd_buffer *rxb)
1759 {
1760         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1761         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1762         u8 group_id;
1763         u32 cmd_id;
1764         int txq_id = SEQ_TO_QUEUE(sequence);
1765         int index = SEQ_TO_INDEX(sequence);
1766         int cmd_index;
1767         struct iwl_device_cmd *cmd;
1768         struct iwl_cmd_meta *meta;
1769         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1770         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1771
1772         /* If a Tx command is being handled and it isn't in the actual
1773          * command queue then there a command routing bug has been introduced
1774          * in the queue management code. */
1775         if (WARN(txq_id != trans_pcie->cmd_queue,
1776                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1777                  txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1778                  txq->write_ptr)) {
1779                 iwl_print_hex_error(trans, pkt, 32);
1780                 return;
1781         }
1782
1783         spin_lock_bh(&txq->lock);
1784
1785         cmd_index = iwl_pcie_get_cmd_index(txq, index);
1786         cmd = txq->entries[cmd_index].cmd;
1787         meta = &txq->entries[cmd_index].meta;
1788         group_id = cmd->hdr.group_id;
1789         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1790
1791         iwl_pcie_tfd_unmap(trans, meta, txq, index);
1792
1793         /* Input error checking is done when commands are added to queue. */
1794         if (meta->flags & CMD_WANT_SKB) {
1795                 struct page *p = rxb_steal_page(rxb);
1796
1797                 meta->source->resp_pkt = pkt;
1798                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1799                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1800         }
1801
1802         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1803                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1804
1805         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1806
1807         if (!(meta->flags & CMD_ASYNC)) {
1808                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1809                         IWL_WARN(trans,
1810                                  "HCMD_ACTIVE already clear for command %s\n",
1811                                  iwl_get_cmd_string(trans, cmd_id));
1812                 }
1813                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1814                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1815                                iwl_get_cmd_string(trans, cmd_id));
1816                 wake_up(&trans_pcie->wait_command_queue);
1817         }
1818
1819         if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1820                 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1821                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1822                 set_bit(STATUS_TRANS_IDLE, &trans->status);
1823                 wake_up(&trans_pcie->d0i3_waitq);
1824         }
1825
1826         if (meta->flags & CMD_WAKE_UP_TRANS) {
1827                 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1828                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1829                 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1830                 wake_up(&trans_pcie->d0i3_waitq);
1831         }
1832
1833         meta->flags = 0;
1834
1835         spin_unlock_bh(&txq->lock);
1836 }
1837
1838 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1839
1840 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1841                                     struct iwl_host_cmd *cmd)
1842 {
1843         int ret;
1844
1845         /* An asynchronous command can not expect an SKB to be set. */
1846         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1847                 return -EINVAL;
1848
1849         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1850         if (ret < 0) {
1851                 IWL_ERR(trans,
1852                         "Error sending %s: enqueue_hcmd failed: %d\n",
1853                         iwl_get_cmd_string(trans, cmd->id), ret);
1854                 return ret;
1855         }
1856         return 0;
1857 }
1858
1859 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1860                                    struct iwl_host_cmd *cmd)
1861 {
1862         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1863         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1864         int cmd_idx;
1865         int ret;
1866
1867         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1868                        iwl_get_cmd_string(trans, cmd->id));
1869
1870         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1871                                   &trans->status),
1872                  "Command %s: a command is already active!\n",
1873                  iwl_get_cmd_string(trans, cmd->id)))
1874                 return -EIO;
1875
1876         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1877                        iwl_get_cmd_string(trans, cmd->id));
1878
1879         if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1880                 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1881                                  pm_runtime_active(&trans_pcie->pci_dev->dev),
1882                                  msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1883                 if (!ret) {
1884                         IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1885                         return -ETIMEDOUT;
1886                 }
1887         }
1888
1889         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1890         if (cmd_idx < 0) {
1891                 ret = cmd_idx;
1892                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1893                 IWL_ERR(trans,
1894                         "Error sending %s: enqueue_hcmd failed: %d\n",
1895                         iwl_get_cmd_string(trans, cmd->id), ret);
1896                 return ret;
1897         }
1898
1899         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1900                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1901                                            &trans->status),
1902                                  HOST_COMPLETE_TIMEOUT);
1903         if (!ret) {
1904                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1905                         iwl_get_cmd_string(trans, cmd->id),
1906                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1907
1908                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1909                         txq->read_ptr, txq->write_ptr);
1910
1911                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1912                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1913                                iwl_get_cmd_string(trans, cmd->id));
1914                 ret = -ETIMEDOUT;
1915
1916                 iwl_force_nmi(trans);
1917                 iwl_trans_fw_error(trans);
1918
1919                 goto cancel;
1920         }
1921
1922         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1923                 iwl_trans_dump_regs(trans);
1924                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1925                         iwl_get_cmd_string(trans, cmd->id));
1926                 dump_stack();
1927                 ret = -EIO;
1928                 goto cancel;
1929         }
1930
1931         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1932             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1933                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1934                 ret = -ERFKILL;
1935                 goto cancel;
1936         }
1937
1938         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1939                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1940                         iwl_get_cmd_string(trans, cmd->id));
1941                 ret = -EIO;
1942                 goto cancel;
1943         }
1944
1945         return 0;
1946
1947 cancel:
1948         if (cmd->flags & CMD_WANT_SKB) {
1949                 /*
1950                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1951                  * TX cmd queue. Otherwise in case the cmd comes
1952                  * in later, it will possibly set an invalid
1953                  * address (cmd->meta.source).
1954                  */
1955                 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1956         }
1957
1958         if (cmd->resp_pkt) {
1959                 iwl_free_resp(cmd);
1960                 cmd->resp_pkt = NULL;
1961         }
1962
1963         return ret;
1964 }
1965
1966 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1967 {
1968         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1969             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1970                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1971                                   cmd->id);
1972                 return -ERFKILL;
1973         }
1974
1975         if (cmd->flags & CMD_ASYNC)
1976                 return iwl_pcie_send_hcmd_async(trans, cmd);
1977
1978         /* We still can fail on RFKILL that can be asserted while we wait */
1979         return iwl_pcie_send_hcmd_sync(trans, cmd);
1980 }
1981
1982 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1983                              struct iwl_txq *txq, u8 hdr_len,
1984                              struct iwl_cmd_meta *out_meta,
1985                              struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1986 {
1987         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1988         u16 tb2_len;
1989         int i;
1990
1991         /*
1992          * Set up TFD's third entry to point directly to remainder
1993          * of skb's head, if any
1994          */
1995         tb2_len = skb_headlen(skb) - hdr_len;
1996
1997         if (tb2_len > 0) {
1998                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1999                                                      skb->data + hdr_len,
2000                                                      tb2_len, DMA_TO_DEVICE);
2001                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
2002                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
2003                                            txq->write_ptr);
2004                         return -EINVAL;
2005                 }
2006                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
2007         }
2008
2009         /* set up the remaining entries to point to the data */
2010         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2011                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2012                 dma_addr_t tb_phys;
2013                 int tb_idx;
2014
2015                 if (!skb_frag_size(frag))
2016                         continue;
2017
2018                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2019                                            skb_frag_size(frag), DMA_TO_DEVICE);
2020
2021                 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2022                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
2023                                            txq->write_ptr);
2024                         return -EINVAL;
2025                 }
2026                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2027                                                 skb_frag_size(frag), false);
2028
2029                 out_meta->tbs |= BIT(tb_idx);
2030         }
2031
2032         trace_iwlwifi_dev_tx(trans->dev, skb,
2033                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2034                              trans_pcie->tfd_size,
2035                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2036                              hdr_len);
2037         trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len);
2038         return 0;
2039 }
2040
2041 #ifdef CONFIG_INET
2042 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2043 {
2044         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2045         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2046
2047         if (!p->page)
2048                 goto alloc;
2049
2050         /* enough room on this page */
2051         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2052                 return p;
2053
2054         /* We don't have enough room on this page, get a new one. */
2055         __free_page(p->page);
2056
2057 alloc:
2058         p->page = alloc_page(GFP_ATOMIC);
2059         if (!p->page)
2060                 return NULL;
2061         p->pos = page_address(p->page);
2062         return p;
2063 }
2064
2065 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2066                                         bool ipv6, unsigned int len)
2067 {
2068         if (ipv6) {
2069                 struct ipv6hdr *iphv6 = iph;
2070
2071                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2072                                                len + tcph->doff * 4,
2073                                                IPPROTO_TCP, 0);
2074         } else {
2075                 struct iphdr *iphv4 = iph;
2076
2077                 ip_send_check(iphv4);
2078                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2079                                                  len + tcph->doff * 4,
2080                                                  IPPROTO_TCP, 0);
2081         }
2082 }
2083
2084 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2085                                    struct iwl_txq *txq, u8 hdr_len,
2086                                    struct iwl_cmd_meta *out_meta,
2087                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2088 {
2089         struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2090         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2091         struct ieee80211_hdr *hdr = (void *)skb->data;
2092         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2093         unsigned int mss = skb_shinfo(skb)->gso_size;
2094         u16 length, iv_len, amsdu_pad;
2095         u8 *start_hdr;
2096         struct iwl_tso_hdr_page *hdr_page;
2097         struct page **page_ptr;
2098         int ret;
2099         struct tso_t tso;
2100
2101         /* if the packet is protected, then it must be CCMP or GCMP */
2102         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2103         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2104                 IEEE80211_CCMP_HDR_LEN : 0;
2105
2106         trace_iwlwifi_dev_tx(trans->dev, skb,
2107                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2108                              trans_pcie->tfd_size,
2109                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2110
2111         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2112         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2113         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2114         amsdu_pad = 0;
2115
2116         /* total amount of header we may need for this A-MSDU */
2117         hdr_room = DIV_ROUND_UP(total_len, mss) *
2118                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2119
2120         /* Our device supports 9 segments at most, it will fit in 1 page */
2121         hdr_page = get_page_hdr(trans, hdr_room);
2122         if (!hdr_page)
2123                 return -ENOMEM;
2124
2125         get_page(hdr_page->page);
2126         start_hdr = hdr_page->pos;
2127         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2128         *page_ptr = hdr_page->page;
2129         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2130         hdr_page->pos += iv_len;
2131
2132         /*
2133          * Pull the ieee80211 header + IV to be able to use TSO core,
2134          * we will restore it for the tx_status flow.
2135          */
2136         skb_pull(skb, hdr_len + iv_len);
2137
2138         /*
2139          * Remove the length of all the headers that we don't actually
2140          * have in the MPDU by themselves, but that we duplicate into
2141          * all the different MSDUs inside the A-MSDU.
2142          */
2143         le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2144
2145         tso_start(skb, &tso);
2146
2147         while (total_len) {
2148                 /* this is the data left for this subframe */
2149                 unsigned int data_left =
2150                         min_t(unsigned int, mss, total_len);
2151                 struct sk_buff *csum_skb = NULL;
2152                 unsigned int hdr_tb_len;
2153                 dma_addr_t hdr_tb_phys;
2154                 struct tcphdr *tcph;
2155                 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2156
2157                 total_len -= data_left;
2158
2159                 memset(hdr_page->pos, 0, amsdu_pad);
2160                 hdr_page->pos += amsdu_pad;
2161                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2162                                   data_left)) & 0x3;
2163                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2164                 hdr_page->pos += ETH_ALEN;
2165                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2166                 hdr_page->pos += ETH_ALEN;
2167
2168                 length = snap_ip_tcp_hdrlen + data_left;
2169                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2170                 hdr_page->pos += sizeof(length);
2171
2172                 /*
2173                  * This will copy the SNAP as well which will be considered
2174                  * as MAC header.
2175                  */
2176                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2177                 iph = hdr_page->pos + 8;
2178                 tcph = (void *)(iph + ip_hdrlen);
2179
2180                 /* For testing on current hardware only */
2181                 if (trans_pcie->sw_csum_tx) {
2182                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2183                                              GFP_ATOMIC);
2184                         if (!csum_skb) {
2185                                 ret = -ENOMEM;
2186                                 goto out_unmap;
2187                         }
2188
2189                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2190                                                     skb->protocol ==
2191                                                         htons(ETH_P_IPV6),
2192                                                     data_left);
2193
2194                         skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2195                         skb_reset_transport_header(csum_skb);
2196                         csum_skb->csum_start =
2197                                 (unsigned char *)tcp_hdr(csum_skb) -
2198                                                  csum_skb->head;
2199                 }
2200
2201                 hdr_page->pos += snap_ip_tcp_hdrlen;
2202
2203                 hdr_tb_len = hdr_page->pos - start_hdr;
2204                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2205                                              hdr_tb_len, DMA_TO_DEVICE);
2206                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2207                         dev_kfree_skb(csum_skb);
2208                         ret = -EINVAL;
2209                         goto out_unmap;
2210                 }
2211                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2212                                        hdr_tb_len, false);
2213                 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2214                                                hdr_tb_len);
2215                 /* add this subframe's headers' length to the tx_cmd */
2216                 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2217
2218                 /* prepare the start_hdr for the next subframe */
2219                 start_hdr = hdr_page->pos;
2220
2221                 /* put the payload */
2222                 while (data_left) {
2223                         unsigned int size = min_t(unsigned int, tso.size,
2224                                                   data_left);
2225                         dma_addr_t tb_phys;
2226
2227                         if (trans_pcie->sw_csum_tx)
2228                                 skb_put_data(csum_skb, tso.data, size);
2229
2230                         tb_phys = dma_map_single(trans->dev, tso.data,
2231                                                  size, DMA_TO_DEVICE);
2232                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2233                                 dev_kfree_skb(csum_skb);
2234                                 ret = -EINVAL;
2235                                 goto out_unmap;
2236                         }
2237
2238                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2239                                                size, false);
2240                         trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2241                                                        size);
2242
2243                         data_left -= size;
2244                         tso_build_data(skb, &tso, size);
2245                 }
2246
2247                 /* For testing on early hardware only */
2248                 if (trans_pcie->sw_csum_tx) {
2249                         __wsum csum;
2250
2251                         csum = skb_checksum(csum_skb,
2252                                             skb_checksum_start_offset(csum_skb),
2253                                             csum_skb->len -
2254                                             skb_checksum_start_offset(csum_skb),
2255                                             0);
2256                         dev_kfree_skb(csum_skb);
2257                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2258                                                 hdr_tb_len, DMA_TO_DEVICE);
2259                         tcph->check = csum_fold(csum);
2260                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2261                                                    hdr_tb_len, DMA_TO_DEVICE);
2262                 }
2263         }
2264
2265         /* re -add the WiFi header and IV */
2266         skb_push(skb, hdr_len + iv_len);
2267
2268         return 0;
2269
2270 out_unmap:
2271         iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2272         return ret;
2273 }
2274 #else /* CONFIG_INET */
2275 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2276                                    struct iwl_txq *txq, u8 hdr_len,
2277                                    struct iwl_cmd_meta *out_meta,
2278                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2279 {
2280         /* No A-MSDU without CONFIG_INET */
2281         WARN_ON(1);
2282
2283         return -1;
2284 }
2285 #endif /* CONFIG_INET */
2286
2287 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2288                       struct iwl_device_cmd *dev_cmd, int txq_id)
2289 {
2290         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2291         struct ieee80211_hdr *hdr;
2292         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2293         struct iwl_cmd_meta *out_meta;
2294         struct iwl_txq *txq;
2295         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2296         void *tb1_addr;
2297         void *tfd;
2298         u16 len, tb1_len;
2299         bool wait_write_ptr;
2300         __le16 fc;
2301         u8 hdr_len;
2302         u16 wifi_seq;
2303         bool amsdu;
2304
2305         txq = trans_pcie->txq[txq_id];
2306
2307         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2308                       "TX on unused queue %d\n", txq_id))
2309                 return -EINVAL;
2310
2311         if (unlikely(trans_pcie->sw_csum_tx &&
2312                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2313                 int offs = skb_checksum_start_offset(skb);
2314                 int csum_offs = offs + skb->csum_offset;
2315                 __wsum csum;
2316
2317                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2318                         return -1;
2319
2320                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2321                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2322
2323                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2324         }
2325
2326         if (skb_is_nonlinear(skb) &&
2327             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2328             __skb_linearize(skb))
2329                 return -ENOMEM;
2330
2331         /* mac80211 always puts the full header into the SKB's head,
2332          * so there's no need to check if it's readable there
2333          */
2334         hdr = (struct ieee80211_hdr *)skb->data;
2335         fc = hdr->frame_control;
2336         hdr_len = ieee80211_hdrlen(fc);
2337
2338         spin_lock(&txq->lock);
2339
2340         if (iwl_queue_space(trans, txq) < txq->high_mark) {
2341                 iwl_stop_queue(trans, txq);
2342
2343                 /* don't put the packet on the ring, if there is no room */
2344                 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2345                         struct iwl_device_cmd **dev_cmd_ptr;
2346
2347                         dev_cmd_ptr = (void *)((u8 *)skb->cb +
2348                                                trans_pcie->dev_cmd_offs);
2349
2350                         *dev_cmd_ptr = dev_cmd;
2351                         __skb_queue_tail(&txq->overflow_q, skb);
2352
2353                         spin_unlock(&txq->lock);
2354                         return 0;
2355                 }
2356         }
2357
2358         /* In AGG mode, the index in the ring must correspond to the WiFi
2359          * sequence number. This is a HW requirements to help the SCD to parse
2360          * the BA.
2361          * Check here that the packets are in the right place on the ring.
2362          */
2363         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2364         WARN_ONCE(txq->ampdu &&
2365                   (wifi_seq & 0xff) != txq->write_ptr,
2366                   "Q: %d WiFi Seq %d tfdNum %d",
2367                   txq_id, wifi_seq, txq->write_ptr);
2368
2369         /* Set up driver data for this TFD */
2370         txq->entries[txq->write_ptr].skb = skb;
2371         txq->entries[txq->write_ptr].cmd = dev_cmd;
2372
2373         dev_cmd->hdr.sequence =
2374                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2375                             INDEX_TO_SEQ(txq->write_ptr)));
2376
2377         tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2378         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2379                        offsetof(struct iwl_tx_cmd, scratch);
2380
2381         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2382         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2383
2384         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2385         out_meta = &txq->entries[txq->write_ptr].meta;
2386         out_meta->flags = 0;
2387
2388         /*
2389          * The second TB (tb1) points to the remainder of the TX command
2390          * and the 802.11 header - dword aligned size
2391          * (This calculation modifies the TX command, so do it before the
2392          * setup of the first TB)
2393          */
2394         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2395               hdr_len - IWL_FIRST_TB_SIZE;
2396         /* do not align A-MSDU to dword as the subframe header aligns it */
2397         amsdu = ieee80211_is_data_qos(fc) &&
2398                 (*ieee80211_get_qos_ctl(hdr) &
2399                  IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2400         if (trans_pcie->sw_csum_tx || !amsdu) {
2401                 tb1_len = ALIGN(len, 4);
2402                 /* Tell NIC about any 2-byte padding after MAC header */
2403                 if (tb1_len != len)
2404                         tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2405         } else {
2406                 tb1_len = len;
2407         }
2408
2409         /*
2410          * The first TB points to bi-directional DMA data, we'll
2411          * memcpy the data into it later.
2412          */
2413         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2414                                IWL_FIRST_TB_SIZE, true);
2415
2416         /* there must be data left over for TB1 or this code must be changed */
2417         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2418
2419         /* map the data for TB1 */
2420         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2421         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2422         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2423                 goto out_err;
2424         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2425
2426         /*
2427          * If gso_size wasn't set, don't give the frame "amsdu treatment"
2428          * (adding subframes, etc.).
2429          * This can happen in some testing flows when the amsdu was already
2430          * pre-built, and we just need to send the resulting skb.
2431          */
2432         if (amsdu && skb_shinfo(skb)->gso_size) {
2433                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2434                                                      out_meta, dev_cmd,
2435                                                      tb1_len)))
2436                         goto out_err;
2437         } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2438                                        out_meta, dev_cmd, tb1_len))) {
2439                 goto out_err;
2440         }
2441
2442         /* building the A-MSDU might have changed this data, so memcpy it now */
2443         memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
2444                IWL_FIRST_TB_SIZE);
2445
2446         tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2447         /* Set up entry for this TFD in Tx byte-count array */
2448         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2449                                          iwl_pcie_tfd_get_num_tbs(trans, tfd));
2450
2451         wait_write_ptr = ieee80211_has_morefrags(fc);
2452
2453         /* start timer if queue currently empty */
2454         if (txq->read_ptr == txq->write_ptr) {
2455                 if (txq->wd_timeout) {
2456                         /*
2457                          * If the TXQ is active, then set the timer, if not,
2458                          * set the timer in remainder so that the timer will
2459                          * be armed with the right value when the station will
2460                          * wake up.
2461                          */
2462                         if (!txq->frozen)
2463                                 mod_timer(&txq->stuck_timer,
2464                                           jiffies + txq->wd_timeout);
2465                         else
2466                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2467                 }
2468                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2469                 iwl_trans_ref(trans);
2470         }
2471
2472         /* Tell device the write index *just past* this latest filled TFD */
2473         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2474         if (!wait_write_ptr)
2475                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2476
2477         /*
2478          * At this point the frame is "transmitted" successfully
2479          * and we will get a TX status notification eventually.
2480          */
2481         spin_unlock(&txq->lock);
2482         return 0;
2483 out_err:
2484         spin_unlock(&txq->lock);
2485         return -1;
2486 }