2 * Copyright (c) 2015-2016 Quantenna Communications, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef _QTN_FMAC_PCIE_IPC_H_
18 #define _QTN_FMAC_PCIE_IPC_H_
20 #include <linux/types.h>
22 #include "shm_ipc_defs.h"
24 /* bitmap for EP status and flags: updated by EP, read by RC */
25 #define QTN_EP_HAS_UBOOT BIT(0)
26 #define QTN_EP_HAS_FIRMWARE BIT(1)
27 #define QTN_EP_REQ_UBOOT BIT(2)
28 #define QTN_EP_REQ_FIRMWARE BIT(3)
29 #define QTN_EP_ERROR_UBOOT BIT(4)
30 #define QTN_EP_ERROR_FIRMWARE BIT(5)
32 #define QTN_EP_FW_LOADRDY BIT(8)
33 #define QTN_EP_FW_SYNC BIT(9)
34 #define QTN_EP_FW_RETRY BIT(10)
35 #define QTN_EP_FW_QLINK_DONE BIT(15)
36 #define QTN_EP_FW_DONE BIT(16)
38 /* bitmap for RC status and flags: updated by RC, read by EP */
39 #define QTN_RC_PCIE_LINK BIT(0)
40 #define QTN_RC_NET_LINK BIT(1)
41 #define QTN_RC_FW_FLASHBOOT BIT(5)
42 #define QTN_RC_FW_QLINK BIT(7)
43 #define QTN_RC_FW_LOADRDY BIT(8)
44 #define QTN_RC_FW_SYNC BIT(9)
46 /* state transition timeouts */
47 #define QTN_FW_DL_TIMEOUT_MS 3000
48 #define QTN_FW_QLINK_TIMEOUT_MS 30000
49 #define QTN_EP_RESET_WAIT_MS 1000
51 #define PCIE_HDP_INT_RX_BITS (0 \
52 | PCIE_HDP_INT_EP_TXDMA \
53 | PCIE_HDP_INT_EP_TXEMPTY \
54 | PCIE_HDP_INT_HHBM_UF \
57 #define PCIE_HDP_INT_TX_BITS (0 \
58 | PCIE_HDP_INT_EP_RXDMA \
61 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
62 #define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32))
63 #define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL))
64 #define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l))
66 #define QTN_HOST_HI32(a) 0
67 #define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL))
68 #define QTN_HOST_ADDR(h, l) ((u32)l)
71 #define QTN_SYSCTL_BAR 0
72 #define QTN_SHMEM_BAR 2
75 #define QTN_PCIE_BDA_VERSION 0x1002
77 #define PCIE_BDA_NAMELEN 32
78 #define PCIE_HHBM_MAX_SIZE 2048
80 #define SKB_BUF_SIZE 2048
82 #define QTN_PCIE_BOARDFLG "PCIEQTN"
83 #define QTN_PCIE_FW_DLMASK 0xF
84 #define QTN_PCIE_FW_BUFSZ 2048
86 #define QTN_ENET_ADDR_LENGTH 6
88 #define QTN_TXDONE_MASK ((u32)0x80000000)
89 #define QTN_GET_LEN(x) ((x) & 0xFFFF)
91 #define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF
92 #define QTN_PCIE_TX_DESC_LEN_SHIFT 0
93 #define QTN_PCIE_TX_DESC_PORT_MASK 0xF
94 #define QTN_PCIE_TX_DESC_PORT_SHIFT 16
95 #define QTN_PCIE_TX_DESC_TQE_BIT BIT(24)
97 #define QTN_EP_LHOST_TQE_PORT 4
99 enum qtnf_pcie_bda_ipc_flags {
100 QTN_PCIE_IPC_FLAG_HBM_MAGIC = BIT(0),
101 QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1),
104 struct qtnf_pcie_bda {
107 __le32 bda_pci_endian;
113 u8 bda_boardname[PCIE_BDA_NAMELEN];
114 __le32 bda_rc_msi_enabled;
115 u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE];
116 __le32 bda_dsbw_start_index;
117 __le32 bda_dsbw_end_index;
118 __le32 bda_dsbw_total_bytes;
119 __le32 bda_rc_tx_bd_base;
120 __le32 bda_rc_tx_bd_num;
121 u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH];
122 struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
123 struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */
142 enum qtnf_fw_loadtype {
149 struct qtnf_pcie_fw_hdr {
158 #endif /* _QTN_FMAC_PCIE_IPC_H_ */