2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, see <http://www.gnu.org/licenses/>.
32 Abstract: rt2800 generic device routines.
35 #include <linux/crc-ccitt.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
41 #include "rt2800lib.h"
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
65 #define WAIT_FOR_RF(__dev, __reg) \
66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
67 #define WAIT_FOR_MCU(__dev, __reg) \
68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
69 H2M_MAILBOX_CSR_OWNER, (__reg))
71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
73 /* check for rt2872 on SoC */
74 if (!rt2x00_is_soc(rt2x00dev) ||
75 !rt2x00_rt(rt2x00dev, RT2872))
78 /* we know for sure that these rf chipsets are used on rt305x boards */
79 if (rt2x00_rf(rt2x00dev, RF3020) ||
80 rt2x00_rf(rt2x00dev, RF3021) ||
81 rt2x00_rf(rt2x00dev, RF3022))
84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
89 const unsigned int word, const u8 value)
93 mutex_lock(&rt2x00dev->csr_mutex);
96 * Wait until the BBP becomes available, afterwards we
97 * can safely write the new data into the register.
99 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
101 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
102 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
103 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
104 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
105 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
110 mutex_unlock(&rt2x00dev->csr_mutex);
113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
118 mutex_lock(&rt2x00dev->csr_mutex);
121 * Wait until the BBP becomes available, afterwards we
122 * can safely write the read request into the register.
123 * After the data has been written, we wait until hardware
124 * returns the correct value, if at any time the register
125 * doesn't become available in time, reg will be 0xffffffff
126 * which means we return 0xff to the caller.
128 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
130 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
131 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
132 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
133 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
137 WAIT_FOR_BBP(rt2x00dev, ®);
140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
142 mutex_unlock(&rt2x00dev->csr_mutex);
147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
148 const unsigned int word, const u8 value)
152 mutex_lock(&rt2x00dev->csr_mutex);
155 * Wait until the RFCSR becomes available, afterwards we
156 * can safely write the new data into the register.
158 switch (rt2x00dev->chip.rt) {
160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
162 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value);
163 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620,
165 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1);
166 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1);
168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
173 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
175 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
176 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
178 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
185 mutex_unlock(&rt2x00dev->csr_mutex);
188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
189 const unsigned int reg, const u8 value)
191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
195 const unsigned int reg, const u8 value)
197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
202 const unsigned int reg, const u8 value)
204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
209 const unsigned int word)
214 mutex_lock(&rt2x00dev->csr_mutex);
217 * Wait until the RFCSR becomes available, afterwards we
218 * can safely write the read request into the register.
219 * After the data has been written, we wait until hardware
220 * returns the correct value, if at any time the register
221 * doesn't become available in time, reg will be 0xffffffff
222 * which means we return 0xff to the caller.
224 switch (rt2x00dev->chip.rt) {
226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
228 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620,
230 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0);
231 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1);
233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®);
238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
242 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
244 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
245 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
246 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
250 WAIT_FOR_RFCSR(rt2x00dev, ®);
253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
257 mutex_unlock(&rt2x00dev->csr_mutex);
262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
263 const unsigned int reg)
265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
269 const unsigned int word, const u32 value)
273 mutex_lock(&rt2x00dev->csr_mutex);
276 * Wait until the RF becomes available, afterwards we
277 * can safely write the new data into the register.
279 if (WAIT_FOR_RF(rt2x00dev, ®)) {
281 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
282 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
283 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
284 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
287 rt2x00_rf_write(rt2x00dev, word, value);
290 mutex_unlock(&rt2x00dev->csr_mutex);
293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
294 [EEPROM_CHIP_ID] = 0x0000,
295 [EEPROM_VERSION] = 0x0001,
296 [EEPROM_MAC_ADDR_0] = 0x0002,
297 [EEPROM_MAC_ADDR_1] = 0x0003,
298 [EEPROM_MAC_ADDR_2] = 0x0004,
299 [EEPROM_NIC_CONF0] = 0x001a,
300 [EEPROM_NIC_CONF1] = 0x001b,
301 [EEPROM_FREQ] = 0x001d,
302 [EEPROM_LED_AG_CONF] = 0x001e,
303 [EEPROM_LED_ACT_CONF] = 0x001f,
304 [EEPROM_LED_POLARITY] = 0x0020,
305 [EEPROM_NIC_CONF2] = 0x0021,
306 [EEPROM_LNA] = 0x0022,
307 [EEPROM_RSSI_BG] = 0x0023,
308 [EEPROM_RSSI_BG2] = 0x0024,
309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
310 [EEPROM_RSSI_A] = 0x0025,
311 [EEPROM_RSSI_A2] = 0x0026,
312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
314 [EEPROM_TXPOWER_DELTA] = 0x0028,
315 [EEPROM_TXPOWER_BG1] = 0x0029,
316 [EEPROM_TXPOWER_BG2] = 0x0030,
317 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
318 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
319 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
320 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
321 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
322 [EEPROM_TXPOWER_A1] = 0x003c,
323 [EEPROM_TXPOWER_A2] = 0x0053,
324 [EEPROM_TXPOWER_INIT] = 0x0068,
325 [EEPROM_TSSI_BOUND_A1] = 0x006a,
326 [EEPROM_TSSI_BOUND_A2] = 0x006b,
327 [EEPROM_TSSI_BOUND_A3] = 0x006c,
328 [EEPROM_TSSI_BOUND_A4] = 0x006d,
329 [EEPROM_TSSI_BOUND_A5] = 0x006e,
330 [EEPROM_TXPOWER_BYRATE] = 0x006f,
331 [EEPROM_BBP_START] = 0x0078,
334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
335 [EEPROM_CHIP_ID] = 0x0000,
336 [EEPROM_VERSION] = 0x0001,
337 [EEPROM_MAC_ADDR_0] = 0x0002,
338 [EEPROM_MAC_ADDR_1] = 0x0003,
339 [EEPROM_MAC_ADDR_2] = 0x0004,
340 [EEPROM_NIC_CONF0] = 0x001a,
341 [EEPROM_NIC_CONF1] = 0x001b,
342 [EEPROM_NIC_CONF2] = 0x001c,
343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
344 [EEPROM_FREQ] = 0x0022,
345 [EEPROM_LED_AG_CONF] = 0x0023,
346 [EEPROM_LED_ACT_CONF] = 0x0024,
347 [EEPROM_LED_POLARITY] = 0x0025,
348 [EEPROM_LNA] = 0x0026,
349 [EEPROM_EXT_LNA2] = 0x0027,
350 [EEPROM_RSSI_BG] = 0x0028,
351 [EEPROM_RSSI_BG2] = 0x0029,
352 [EEPROM_RSSI_A] = 0x002a,
353 [EEPROM_RSSI_A2] = 0x002b,
354 [EEPROM_TXPOWER_BG1] = 0x0030,
355 [EEPROM_TXPOWER_BG2] = 0x0037,
356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
357 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
358 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
359 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
360 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
361 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
362 [EEPROM_TXPOWER_A1] = 0x004b,
363 [EEPROM_TXPOWER_A2] = 0x0065,
364 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
365 [EEPROM_TSSI_BOUND_A1] = 0x009a,
366 [EEPROM_TSSI_BOUND_A2] = 0x009b,
367 [EEPROM_TSSI_BOUND_A3] = 0x009c,
368 [EEPROM_TSSI_BOUND_A4] = 0x009d,
369 [EEPROM_TSSI_BOUND_A5] = 0x009e,
370 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
374 const enum rt2800_eeprom_word word)
376 const unsigned int *map;
379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
380 "%s: invalid EEPROM word %d\n",
381 wiphy_name(rt2x00dev->hw->wiphy), word))
384 if (rt2x00_rt(rt2x00dev, RT3593))
385 map = rt2800_eeprom_map_ext;
387 map = rt2800_eeprom_map;
391 /* Index 0 is valid only for EEPROM_CHIP_ID.
392 * Otherwise it means that the offset of the
393 * given word is not initialized in the map,
394 * or that the field is not usable on the
397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
398 "%s: invalid access of EEPROM word %d\n",
399 wiphy_name(rt2x00dev->hw->wiphy), word);
404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
405 const enum rt2800_eeprom_word word)
409 index = rt2800_eeprom_word_index(rt2x00dev, word);
410 return rt2x00_eeprom_addr(rt2x00dev, index);
413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
414 const enum rt2800_eeprom_word word)
418 index = rt2800_eeprom_word_index(rt2x00dev, word);
419 return rt2x00_eeprom_read(rt2x00dev, index);
422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
423 const enum rt2800_eeprom_word word, u16 data)
427 index = rt2800_eeprom_word_index(rt2x00dev, word);
428 rt2x00_eeprom_write(rt2x00dev, index, data);
431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
432 const enum rt2800_eeprom_word array,
437 index = rt2800_eeprom_word_index(rt2x00dev, array);
438 return rt2x00_eeprom_read(rt2x00dev, index + offset);
441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
447 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
448 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1);
449 rt2x00_set_field32(®, WLAN_CLK_EN, 0);
450 rt2x00_set_field32(®, WLAN_EN, 1);
451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
453 udelay(REGISTER_BUSY_DELAY);
458 * Check PLL_LD & XTAL_RDY.
460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
462 if (rt2x00_get_field32(reg, PLL_LD) &&
463 rt2x00_get_field32(reg, XTAL_RDY))
465 udelay(REGISTER_BUSY_DELAY);
468 if (i >= REGISTER_BUSY_COUNT) {
473 rt2800_register_write(rt2x00dev, 0x58, 0x018);
474 udelay(REGISTER_BUSY_DELAY);
475 rt2800_register_write(rt2x00dev, 0x58, 0x418);
476 udelay(REGISTER_BUSY_DELAY);
477 rt2800_register_write(rt2x00dev, 0x58, 0x618);
478 udelay(REGISTER_BUSY_DELAY);
484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
485 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0);
486 rt2x00_set_field32(®, WLAN_CLK_EN, 1);
487 rt2x00_set_field32(®, WLAN_RESET, 1);
488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
490 rt2x00_set_field32(®, WLAN_RESET, 0);
491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
494 } while (count != 0);
499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
500 const u8 command, const u8 token,
501 const u8 arg0, const u8 arg1)
506 * SOC devices don't support MCU requests.
508 if (rt2x00_is_soc(rt2x00dev))
511 mutex_lock(&rt2x00dev->csr_mutex);
514 * Wait until the MCU becomes available, afterwards we
515 * can safely write the new data into the register.
517 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
518 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
519 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
520 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
521 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
525 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
529 mutex_unlock(&rt2x00dev->csr_mutex);
531 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
540 if (reg && reg != ~0)
545 rt2x00_err(rt2x00dev, "Unstable hardware\n");
548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
556 * Some devices are really slow to respond here. Wait a whole second
559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
578 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
579 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
580 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
581 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
582 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
588 unsigned short *txwi_size,
589 unsigned short *rxwi_size)
591 switch (rt2x00dev->chip.rt) {
593 *txwi_size = TXWI_DESC_SIZE_4WORDS;
594 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
599 *txwi_size = TXWI_DESC_SIZE_5WORDS;
600 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
604 *txwi_size = TXWI_DESC_SIZE_4WORDS;
605 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
617 * The last 2 bytes in the firmware array are the crc checksum itself,
618 * this means that we should never pass those 2 bytes to the crc
621 fw_crc = (data[len - 2] << 8 | data[len - 1]);
624 * Use the crc ccitt algorithm.
625 * This will return the same value as the legacy driver which
626 * used bit ordering reversion on the both the firmware bytes
627 * before input input as well as on the final output.
628 * Obviously using crc ccitt directly is much more efficient.
630 crc = crc_ccitt(~0, data, len - 2);
633 * There is a small difference between the crc-itu-t + bitrev and
634 * the crc-ccitt crc calculation. In the latter method the 2 bytes
635 * will be swapped, use swab16 to convert the crc to the correct
640 return fw_crc == crc;
643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
644 const u8 *data, const size_t len)
651 * PCI(e) & SOC devices require firmware with a length
652 * of 8kb. USB devices require firmware files with a length
653 * of 4kb. Certain USB chipsets however require different firmware,
654 * which Ralink only provides attached to the original firmware
655 * file. Thus for USB devices, firmware files have a length
656 * which is a multiple of 4kb. The firmware for rt3290 chip also
657 * have a length which is a multiple of 4kb.
659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
666 * Validate the firmware length
668 if (len != fw_len && (!multiple || (len % fw_len) != 0))
669 return FW_BAD_LENGTH;
672 * Check if the chipset requires one of the upper parts
675 if (rt2x00_is_usb(rt2x00dev) &&
676 !rt2x00_rt(rt2x00dev, RT2860) &&
677 !rt2x00_rt(rt2x00dev, RT2872) &&
678 !rt2x00_rt(rt2x00dev, RT3070) &&
679 ((len / fw_len) == 1))
680 return FW_BAD_VERSION;
683 * 8kb firmware files must be checked as if it were
684 * 2 separate firmware files.
686 while (offset < len) {
687 if (!rt2800_check_firmware_crc(data + offset, fw_len))
695 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
698 const u8 *data, const size_t len)
704 if (rt2x00_rt(rt2x00dev, RT3290)) {
705 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
711 * If driver doesn't wake up firmware here,
712 * rt2800_load_firmware will hang forever when interface is up again.
714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
717 * Wait for stable hardware.
719 if (rt2800_wait_csr_ready(rt2x00dev))
722 if (rt2x00_is_pci(rt2x00dev)) {
723 if (rt2x00_rt(rt2x00dev, RT3290) ||
724 rt2x00_rt(rt2x00dev, RT3572) ||
725 rt2x00_rt(rt2x00dev, RT5390) ||
726 rt2x00_rt(rt2x00dev, RT5392)) {
727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
728 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
729 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
735 rt2800_disable_wpdma(rt2x00dev);
738 * Write firmware to the device.
740 rt2800_drv_write_firmware(rt2x00dev, data, len);
743 * Wait for device to stabilize.
745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
752 if (i == REGISTER_BUSY_COUNT) {
753 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
758 * Disable DMA, will be reenabled later when enabling
761 rt2800_disable_wpdma(rt2x00dev);
764 * Initialize firmware.
766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
768 if (rt2x00_is_usb(rt2x00dev)) {
769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
776 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
778 void rt2800_write_tx_data(struct queue_entry *entry,
779 struct txentry_desc *txdesc)
781 __le32 *txwi = rt2800_drv_get_txwi(entry);
786 * Initialize TX Info descriptor
788 word = rt2x00_desc_read(txwi, 0);
789 rt2x00_set_field32(&word, TXWI_W0_FRAG,
790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
794 rt2x00_set_field32(&word, TXWI_W0_TS,
795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
796 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
799 txdesc->u.ht.mpdu_density);
800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
802 rt2x00_set_field32(&word, TXWI_W0_BW,
803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
808 rt2x00_desc_write(txwi, 0, word);
810 word = rt2x00_desc_read(txwi, 1);
811 rt2x00_set_field32(&word, TXWI_W1_ACK,
812 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
813 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
818 txdesc->key_idx : txdesc->u.ht.wcid);
819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
823 rt2x00_desc_write(txwi, 1, word);
826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
828 * When TXD_W3_WIV is set to 1 it will use the IV data
829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
830 * crypto entry in the registers should be used to encrypt the frame.
832 * Nulify all remaining words as well, we don't know how to program them.
834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
835 _rt2x00_desc_write(txwi, i, 0);
837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
864 * Convert the value from the descriptor into the RSSI value
865 * If the value in the descriptor is 0, it is considered invalid
866 * and the default (extremely low) rssi value is assumed
868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
873 * mac80211 only accepts a single RSSI value. Calculating the
874 * average doesn't deliver a fair answer either since -60:-60 would
875 * be considered equally good as -50:-70 while the second is the one
876 * which gives less energy...
878 rssi0 = max(rssi0, rssi1);
879 return (int)max(rssi0, rssi2);
882 void rt2800_process_rxwi(struct queue_entry *entry,
883 struct rxdone_entry_desc *rxdesc)
885 __le32 *rxwi = (__le32 *) entry->skb->data;
888 word = rt2x00_desc_read(rxwi, 0);
890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
893 word = rt2x00_desc_read(rxwi, 1);
895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
898 if (rt2x00_get_field32(word, RXWI_W1_BW))
899 rxdesc->bw = RATE_INFO_BW_40;
902 * Detect RX rate, always use MCS as signal type.
904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
909 * Mask of 0x8 bit to remove the short preamble flag.
911 if (rxdesc->rate_mode == RATE_MODE_CCK)
912 rxdesc->signal &= ~0x8;
914 word = rt2x00_desc_read(rxwi, 2);
917 * Convert descriptor AGC value to RSSI value.
919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
921 * Remove RXWI descriptor from start of the buffer.
923 skb_pull(entry->skb, entry->queue->winfo_size);
925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
928 u32 status, enum nl80211_band band)
931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
934 case RATE_MODE_HT_GREENFIELD:
935 flags |= IEEE80211_TX_RC_GREEN_FIELD;
937 case RATE_MODE_HT_MIX:
938 flags |= IEEE80211_TX_RC_MCS;
941 if (band == NL80211_BAND_2GHZ)
950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
954 flags |= IEEE80211_TX_RC_SHORT_GI;
956 skbdesc->tx_rate_idx = idx;
957 skbdesc->tx_rate_flags = flags;
960 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
963 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
964 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
965 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
966 struct txdone_entry_desc txdesc;
969 int aggr, ampdu, wcid, ack_req;
972 * Obtain the status about this packet.
975 word = rt2x00_desc_read(txwi, 0);
977 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
978 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
980 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
981 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
982 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
983 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
986 * If a frame was meant to be sent as a single non-aggregated MPDU
987 * but ended up in an aggregate the used tx rate doesn't correlate
988 * with the one specified in the TXWI as the whole aggregate is sent
989 * with the same rate.
991 * For example: two frames are sent to rt2x00, the first one sets
992 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
993 * and requests MCS15. If the hw aggregates both frames into one
994 * AMDPU the tx status for both frames will contain MCS7 although
995 * the frame was sent successfully.
997 * Hence, replace the requested rate with the real tx rate to not
998 * confuse the rate control algortihm by providing clearly wrong
1001 * FIXME: if we do not find matching entry, we tell that frame was
1002 * posted without any retries. We need to find a way to fix that
1003 * and provide retry count.
1005 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1006 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1010 if (aggr == 1 || ampdu == 1)
1011 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1014 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1017 * Ralink has a retry mechanism using a global fallback
1018 * table. We setup this fallback table to try the immediate
1019 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1020 * always contains the MCS used for the last transmission, be
1021 * it successful or not.
1023 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1025 * Transmission succeeded. The number of retries is
1028 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1029 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1032 * Transmission failed. The number of retries is
1033 * always 7 in this case (for a total number of 8
1036 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1037 txdesc.retry = rt2x00dev->long_retry;
1041 * the frame was retried at least once
1042 * -> hw used fallback rates
1045 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1048 /* RCU assures non-null sta will not be freed by mac80211. */
1050 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1051 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1053 skbdesc->sta = NULL;
1054 rt2x00lib_txdone_nomatch(entry, &txdesc);
1057 rt2x00lib_txdone(entry, &txdesc);
1060 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1062 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1065 return HW_BEACON_BASE(index);
1068 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1071 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1074 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1076 struct data_queue *queue = rt2x00dev->bcn;
1077 struct queue_entry *entry;
1083 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1085 for (i = 0; i < queue->limit; i++) {
1086 entry = &queue->entries[i];
1087 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1089 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1090 reg |= off << (8 * bcn_num);
1094 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1095 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1098 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1100 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1101 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1102 bcn_num > 0 ? bcn_num - 1 : 0);
1103 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1106 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1108 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1109 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1110 unsigned int beacon_base;
1111 unsigned int padding_len;
1113 const int txwi_desc_size = entry->queue->winfo_size;
1116 * Disable beaconing while we are reloading the beacon data,
1117 * otherwise we might be sending out invalid data.
1119 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1121 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1122 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1125 * Add space for the TXWI in front of the skb.
1127 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1130 * Register descriptor details in skb frame descriptor.
1132 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1133 skbdesc->desc = entry->skb->data;
1134 skbdesc->desc_len = txwi_desc_size;
1137 * Add the TXWI for the beacon to the skb.
1139 rt2800_write_tx_data(entry, txdesc);
1142 * Dump beacon to userspace through debugfs.
1144 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1147 * Write entire beacon with TXWI and padding to register.
1149 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1150 if (padding_len && skb_pad(entry->skb, padding_len)) {
1151 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1152 /* skb freed by skb_pad() on failure */
1154 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1158 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1160 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1161 entry->skb->len + padding_len);
1162 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1165 * Change global beacons settings.
1167 rt2800_update_beacons_setup(rt2x00dev);
1170 * Restore beaconing state.
1172 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1175 * Clean up beacon skb.
1177 dev_kfree_skb_any(entry->skb);
1180 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1182 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1186 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1187 unsigned int beacon_base;
1189 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1192 * For the Beacon base registers we only need to clear
1193 * the whole TXWI which (when set to 0) will invalidate
1194 * the entire beacon.
1196 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1197 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1200 void rt2800_clear_beacon(struct queue_entry *entry)
1202 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1206 * Disable beaconing while we are reloading the beacon data,
1207 * otherwise we might be sending out invalid data.
1209 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1211 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1212 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1217 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1218 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1221 * Change global beacons settings.
1223 rt2800_update_beacons_setup(rt2x00dev);
1225 * Restore beaconing state.
1227 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1229 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1231 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1232 const struct rt2x00debug rt2800_rt2x00debug = {
1233 .owner = THIS_MODULE,
1235 .read = rt2800_register_read,
1236 .write = rt2800_register_write,
1237 .flags = RT2X00DEBUGFS_OFFSET,
1238 .word_base = CSR_REG_BASE,
1239 .word_size = sizeof(u32),
1240 .word_count = CSR_REG_SIZE / sizeof(u32),
1243 /* NOTE: The local EEPROM access functions can't
1244 * be used here, use the generic versions instead.
1246 .read = rt2x00_eeprom_read,
1247 .write = rt2x00_eeprom_write,
1248 .word_base = EEPROM_BASE,
1249 .word_size = sizeof(u16),
1250 .word_count = EEPROM_SIZE / sizeof(u16),
1253 .read = rt2800_bbp_read,
1254 .write = rt2800_bbp_write,
1255 .word_base = BBP_BASE,
1256 .word_size = sizeof(u8),
1257 .word_count = BBP_SIZE / sizeof(u8),
1260 .read = rt2x00_rf_read,
1261 .write = rt2800_rf_write,
1262 .word_base = RF_BASE,
1263 .word_size = sizeof(u32),
1264 .word_count = RF_SIZE / sizeof(u32),
1267 .read = rt2800_rfcsr_read,
1268 .write = rt2800_rfcsr_write,
1269 .word_base = RFCSR_BASE,
1270 .word_size = sizeof(u8),
1271 .word_count = RFCSR_SIZE / sizeof(u8),
1274 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1275 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1277 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1281 if (rt2x00_rt(rt2x00dev, RT3290)) {
1282 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1283 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1285 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1286 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1289 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1291 #ifdef CONFIG_RT2X00_LIB_LEDS
1292 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1293 enum led_brightness brightness)
1295 struct rt2x00_led *led =
1296 container_of(led_cdev, struct rt2x00_led, led_dev);
1297 unsigned int enabled = brightness != LED_OFF;
1298 unsigned int bg_mode =
1299 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1300 unsigned int polarity =
1301 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1302 EEPROM_FREQ_LED_POLARITY);
1303 unsigned int ledmode =
1304 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1305 EEPROM_FREQ_LED_MODE);
1308 /* Check for SoC (SOC devices don't support MCU requests) */
1309 if (rt2x00_is_soc(led->rt2x00dev)) {
1310 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1312 /* Set LED Polarity */
1313 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity);
1316 if (led->type == LED_TYPE_RADIO) {
1317 rt2x00_set_field32(®, LED_CFG_G_LED_MODE,
1319 } else if (led->type == LED_TYPE_ASSOC) {
1320 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE,
1322 } else if (led->type == LED_TYPE_QUALITY) {
1323 rt2x00_set_field32(®, LED_CFG_R_LED_MODE,
1327 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1330 if (led->type == LED_TYPE_RADIO) {
1331 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1332 enabled ? 0x20 : 0);
1333 } else if (led->type == LED_TYPE_ASSOC) {
1334 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1335 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1336 } else if (led->type == LED_TYPE_QUALITY) {
1338 * The brightness is divided into 6 levels (0 - 5),
1339 * The specs tell us the following levels:
1340 * 0, 1 ,3, 7, 15, 31
1341 * to determine the level in a simple way we can simply
1342 * work with bitshifting:
1345 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1346 (1 << brightness / (LED_FULL / 6)) - 1,
1352 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1353 struct rt2x00_led *led, enum led_type type)
1355 led->rt2x00dev = rt2x00dev;
1357 led->led_dev.brightness_set = rt2800_brightness_set;
1358 led->flags = LED_INITIALIZED;
1360 #endif /* CONFIG_RT2X00_LIB_LEDS */
1363 * Configuration handlers.
1365 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1369 struct mac_wcid_entry wcid_entry;
1372 offset = MAC_WCID_ENTRY(wcid);
1374 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1376 memcpy(wcid_entry.mac, address, ETH_ALEN);
1378 rt2800_register_multiwrite(rt2x00dev, offset,
1379 &wcid_entry, sizeof(wcid_entry));
1382 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1385 offset = MAC_WCID_ATTR_ENTRY(wcid);
1386 rt2800_register_write(rt2x00dev, offset, 0);
1389 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1390 int wcid, u32 bssidx)
1392 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1396 * The BSS Idx numbers is split in a main value of 3 bits,
1397 * and a extended field for adding one additional bit to the value.
1399 reg = rt2800_register_read(rt2x00dev, offset);
1400 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1401 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1402 (bssidx & 0x8) >> 3);
1403 rt2800_register_write(rt2x00dev, offset, reg);
1406 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1407 struct rt2x00lib_crypto *crypto,
1408 struct ieee80211_key_conf *key)
1410 struct mac_iveiv_entry iveiv_entry;
1414 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1416 if (crypto->cmd == SET_KEY) {
1417 reg = rt2800_register_read(rt2x00dev, offset);
1418 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
1419 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1421 * Both the cipher as the BSS Idx numbers are split in a main
1422 * value of 3 bits, and a extended field for adding one additional
1425 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
1426 (crypto->cipher & 0x7));
1427 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1428 (crypto->cipher & 0x8) >> 3);
1429 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1430 rt2800_register_write(rt2x00dev, offset, reg);
1432 /* Delete the cipher without touching the bssidx */
1433 reg = rt2800_register_read(rt2x00dev, offset);
1434 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1435 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1436 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1437 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1438 rt2800_register_write(rt2x00dev, offset, reg);
1441 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1443 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1444 if ((crypto->cipher == CIPHER_TKIP) ||
1445 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1446 (crypto->cipher == CIPHER_AES))
1447 iveiv_entry.iv[3] |= 0x20;
1448 iveiv_entry.iv[3] |= key->keyidx << 6;
1449 rt2800_register_multiwrite(rt2x00dev, offset,
1450 &iveiv_entry, sizeof(iveiv_entry));
1453 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1454 struct rt2x00lib_crypto *crypto,
1455 struct ieee80211_key_conf *key)
1457 struct hw_key_entry key_entry;
1458 struct rt2x00_field32 field;
1462 if (crypto->cmd == SET_KEY) {
1463 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1465 memcpy(key_entry.key, crypto->key,
1466 sizeof(key_entry.key));
1467 memcpy(key_entry.tx_mic, crypto->tx_mic,
1468 sizeof(key_entry.tx_mic));
1469 memcpy(key_entry.rx_mic, crypto->rx_mic,
1470 sizeof(key_entry.rx_mic));
1472 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1473 rt2800_register_multiwrite(rt2x00dev, offset,
1474 &key_entry, sizeof(key_entry));
1478 * The cipher types are stored over multiple registers
1479 * starting with SHARED_KEY_MODE_BASE each word will have
1480 * 32 bits and contains the cipher types for 2 bssidx each.
1481 * Using the correct defines correctly will cause overhead,
1482 * so just calculate the correct offset.
1484 field.bit_offset = 4 * (key->hw_key_idx % 8);
1485 field.bit_mask = 0x7 << field.bit_offset;
1487 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1489 reg = rt2800_register_read(rt2x00dev, offset);
1490 rt2x00_set_field32(®, field,
1491 (crypto->cmd == SET_KEY) * crypto->cipher);
1492 rt2800_register_write(rt2x00dev, offset, reg);
1495 * Update WCID information
1497 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1498 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1500 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1504 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1506 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1507 struct rt2x00lib_crypto *crypto,
1508 struct ieee80211_key_conf *key)
1510 struct hw_key_entry key_entry;
1513 if (crypto->cmd == SET_KEY) {
1515 * Allow key configuration only for STAs that are
1518 if (crypto->wcid > WCID_END)
1520 key->hw_key_idx = crypto->wcid;
1522 memcpy(key_entry.key, crypto->key,
1523 sizeof(key_entry.key));
1524 memcpy(key_entry.tx_mic, crypto->tx_mic,
1525 sizeof(key_entry.tx_mic));
1526 memcpy(key_entry.rx_mic, crypto->rx_mic,
1527 sizeof(key_entry.rx_mic));
1529 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1530 rt2800_register_multiwrite(rt2x00dev, offset,
1531 &key_entry, sizeof(key_entry));
1535 * Update WCID information
1537 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1541 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1543 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1547 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1549 for (i = 0; i < 3; i++)
1550 if (drv_data->ampdu_factor_cnt[i] > 0)
1553 max_psdu = min(drv_data->max_psdu, i);
1555 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1556 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1557 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1560 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1561 struct ieee80211_sta *sta)
1563 struct rt2x00_dev *rt2x00dev = hw->priv;
1564 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1565 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1569 * Limit global maximum TX AMPDU length to smallest value of all
1570 * connected stations. In AP mode this can be suboptimal, but we
1571 * do not have a choice if some connected STA is not capable to
1572 * receive the same amount of data like the others.
1574 if (sta->ht_cap.ht_supported) {
1575 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1576 rt2800_set_max_psdu_len(rt2x00dev);
1580 * Search for the first free WCID entry and return the corresponding
1583 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1586 * Store selected wcid even if it is invalid so that we can
1587 * later decide if the STA is uploaded into the hw.
1589 sta_priv->wcid = wcid;
1592 * No space left in the device, however, we can still communicate
1593 * with the STA -> No error.
1595 if (wcid > WCID_END)
1598 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1599 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1602 * Clean up WCID attributes and write STA address to the device.
1604 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1605 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1606 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1607 rt2x00lib_get_bssidx(rt2x00dev, vif));
1610 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1612 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1613 struct ieee80211_sta *sta)
1615 struct rt2x00_dev *rt2x00dev = hw->priv;
1616 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1617 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1618 int wcid = sta_priv->wcid;
1620 if (sta->ht_cap.ht_supported) {
1621 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1622 rt2800_set_max_psdu_len(rt2x00dev);
1625 if (wcid > WCID_END)
1628 * Remove WCID entry, no need to clean the attributes as they will
1629 * get renewed when the WCID is reused.
1631 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1632 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1633 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1637 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1639 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1640 const unsigned int filter_flags)
1645 * Start configuration steps.
1646 * Note that the version error will always be dropped
1647 * and broadcast frames will always be accepted since
1648 * there is no filter for it at this time.
1650 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1651 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1652 !(filter_flags & FIF_FCSFAIL));
1653 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1654 !(filter_flags & FIF_PLCPFAIL));
1655 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1656 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1657 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1658 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1659 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1660 !(filter_flags & FIF_ALLMULTI));
1661 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1662 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1663 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1664 !(filter_flags & FIF_CONTROL));
1665 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1666 !(filter_flags & FIF_CONTROL));
1667 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1668 !(filter_flags & FIF_CONTROL));
1669 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1670 !(filter_flags & FIF_CONTROL));
1671 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1672 !(filter_flags & FIF_CONTROL));
1673 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1674 !(filter_flags & FIF_PSPOLL));
1675 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0);
1676 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR,
1677 !(filter_flags & FIF_CONTROL));
1678 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1679 !(filter_flags & FIF_CONTROL));
1680 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1682 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1684 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1685 struct rt2x00intf_conf *conf, const unsigned int flags)
1688 bool update_bssid = false;
1690 if (flags & CONFIG_UPDATE_TYPE) {
1692 * Enable synchronisation.
1694 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1695 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1696 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1698 if (conf->sync == TSF_SYNC_AP_NONE) {
1700 * Tune beacon queue transmit parameters for AP mode
1702 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1703 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1704 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1705 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1706 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1707 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1709 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1710 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1711 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1712 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1713 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1714 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1718 if (flags & CONFIG_UPDATE_MAC) {
1719 if (flags & CONFIG_UPDATE_TYPE &&
1720 conf->sync == TSF_SYNC_AP_NONE) {
1722 * The BSSID register has to be set to our own mac
1723 * address in AP mode.
1725 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1726 update_bssid = true;
1729 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1730 reg = le32_to_cpu(conf->mac[1]);
1731 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1732 conf->mac[1] = cpu_to_le32(reg);
1735 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1736 conf->mac, sizeof(conf->mac));
1739 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1740 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1741 reg = le32_to_cpu(conf->bssid[1]);
1742 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1743 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1744 conf->bssid[1] = cpu_to_le32(reg);
1747 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1748 conf->bssid, sizeof(conf->bssid));
1751 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1753 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1754 struct rt2x00lib_erp *erp)
1756 bool any_sta_nongf = !!(erp->ht_opmode &
1757 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1758 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1759 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1760 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1763 /* default protection rate for HT20: OFDM 24M */
1764 mm20_rate = gf20_rate = 0x4004;
1766 /* default protection rate for HT40: duplicate OFDM 24M */
1767 mm40_rate = gf40_rate = 0x4084;
1769 switch (protection) {
1770 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1772 * All STAs in this BSS are HT20/40 but there might be
1773 * STAs not supporting greenfield mode.
1774 * => Disable protection for HT transmissions.
1776 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1779 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1781 * All STAs in this BSS are HT20 or HT20/40 but there
1782 * might be STAs not supporting greenfield mode.
1783 * => Protect all HT40 transmissions.
1785 mm20_mode = gf20_mode = 0;
1786 mm40_mode = gf40_mode = 1;
1789 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1791 * Nonmember protection:
1792 * According to 802.11n we _should_ protect all
1793 * HT transmissions (but we don't have to).
1795 * But if cts_protection is enabled we _shall_ protect
1796 * all HT transmissions using a CCK rate.
1798 * And if any station is non GF we _shall_ protect
1801 * We decide to protect everything
1802 * -> fall through to mixed mode.
1804 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1806 * Legacy STAs are present
1807 * => Protect all HT transmissions.
1809 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
1812 * If erp protection is needed we have to protect HT
1813 * transmissions with CCK 11M long preamble.
1815 if (erp->cts_protection) {
1816 /* don't duplicate RTS/CTS in CCK mode */
1817 mm20_rate = mm40_rate = 0x0003;
1818 gf20_rate = gf40_rate = 0x0003;
1823 /* check for STAs not supporting greenfield mode */
1825 gf20_mode = gf40_mode = 1;
1827 /* Update HT protection config */
1828 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
1829 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1830 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1831 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1833 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
1834 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1835 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1836 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1838 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
1839 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1840 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1841 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1843 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
1844 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1845 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1846 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1849 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1854 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1855 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
1856 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1857 !!erp->short_preamble);
1858 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1861 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1862 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
1863 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1864 erp->cts_protection ? 2 : 0);
1865 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1868 if (changed & BSS_CHANGED_BASIC_RATES) {
1869 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1870 0xff0 | erp->basic_rates);
1871 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1874 if (changed & BSS_CHANGED_ERP_SLOT) {
1875 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
1876 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
1878 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1880 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
1881 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1882 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1885 if (changed & BSS_CHANGED_BEACON_INT) {
1886 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1887 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1888 erp->beacon_int * 16);
1889 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1892 if (changed & BSS_CHANGED_HT)
1893 rt2800_config_ht_opmode(rt2x00dev, erp);
1895 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1897 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1901 u8 led_ctrl, led_g_mode, led_r_mode;
1903 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
1904 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1905 rt2x00_set_field32(®, GPIO_SWITCH_0, 1);
1906 rt2x00_set_field32(®, GPIO_SWITCH_1, 1);
1908 rt2x00_set_field32(®, GPIO_SWITCH_0, 0);
1909 rt2x00_set_field32(®, GPIO_SWITCH_1, 0);
1911 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1913 reg = rt2800_register_read(rt2x00dev, LED_CFG);
1914 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1915 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1916 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1917 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1918 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
1919 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1920 if (led_ctrl == 0 || led_ctrl > 0x40) {
1921 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode);
1922 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode);
1923 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1925 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1926 (led_g_mode << 2) | led_r_mode, 1);
1931 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1935 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1936 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1938 if (rt2x00_is_pci(rt2x00dev)) {
1939 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
1940 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1941 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1942 } else if (rt2x00_is_usb(rt2x00dev))
1943 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1946 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1947 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
1948 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3);
1949 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1952 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1958 r1 = rt2800_bbp_read(rt2x00dev, 1);
1959 r3 = rt2800_bbp_read(rt2x00dev, 3);
1961 if (rt2x00_rt(rt2x00dev, RT3572) &&
1962 rt2x00_has_cap_bt_coexist(rt2x00dev))
1963 rt2800_config_3572bt_ant(rt2x00dev);
1966 * Configure the TX antenna.
1968 switch (ant->tx_chain_num) {
1970 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1973 if (rt2x00_rt(rt2x00dev, RT3572) &&
1974 rt2x00_has_cap_bt_coexist(rt2x00dev))
1975 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1977 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1980 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1985 * Configure the RX antenna.
1987 switch (ant->rx_chain_num) {
1989 if (rt2x00_rt(rt2x00dev, RT3070) ||
1990 rt2x00_rt(rt2x00dev, RT3090) ||
1991 rt2x00_rt(rt2x00dev, RT3352) ||
1992 rt2x00_rt(rt2x00dev, RT3390)) {
1993 eeprom = rt2800_eeprom_read(rt2x00dev,
1995 if (rt2x00_get_field16(eeprom,
1996 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1997 rt2800_set_ant_diversity(rt2x00dev,
1998 rt2x00dev->default_ant.rx);
2000 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2003 if (rt2x00_rt(rt2x00dev, RT3572) &&
2004 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2005 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2006 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2007 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2008 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2010 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2014 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2018 rt2800_bbp_write(rt2x00dev, 3, r3);
2019 rt2800_bbp_write(rt2x00dev, 1, r1);
2021 if (rt2x00_rt(rt2x00dev, RT3593)) {
2022 if (ant->rx_chain_num == 1)
2023 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2025 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2028 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2030 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2031 struct rt2x00lib_conf *libconf)
2036 if (libconf->rf.channel <= 14) {
2037 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2038 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2039 } else if (libconf->rf.channel <= 64) {
2040 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2041 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2042 } else if (libconf->rf.channel <= 128) {
2043 if (rt2x00_rt(rt2x00dev, RT3593)) {
2044 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2045 lna_gain = rt2x00_get_field16(eeprom,
2046 EEPROM_EXT_LNA2_A1);
2048 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2049 lna_gain = rt2x00_get_field16(eeprom,
2050 EEPROM_RSSI_BG2_LNA_A1);
2053 if (rt2x00_rt(rt2x00dev, RT3593)) {
2054 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2055 lna_gain = rt2x00_get_field16(eeprom,
2056 EEPROM_EXT_LNA2_A2);
2058 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2059 lna_gain = rt2x00_get_field16(eeprom,
2060 EEPROM_RSSI_A2_LNA_A2);
2064 rt2x00dev->lna_gain = lna_gain;
2067 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2069 return clk_get_rate(rt2x00dev->clk) == 20000000;
2072 #define FREQ_OFFSET_BOUND 0x5f
2074 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2076 u8 freq_offset, prev_freq_offset;
2077 u8 rfcsr, prev_rfcsr;
2079 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2080 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2082 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2085 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2086 if (rfcsr == prev_rfcsr)
2089 if (rt2x00_is_usb(rt2x00dev)) {
2090 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2091 freq_offset, prev_rfcsr);
2095 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2096 while (prev_freq_offset != freq_offset) {
2097 if (prev_freq_offset < freq_offset)
2102 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2103 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2105 usleep_range(1000, 1500);
2109 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2110 struct ieee80211_conf *conf,
2111 struct rf_channel *rf,
2112 struct channel_info *info)
2114 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2116 if (rt2x00dev->default_ant.tx_chain_num == 1)
2117 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2119 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2120 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2121 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2122 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2123 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2125 if (rf->channel > 14) {
2127 * When TX power is below 0, we should increase it by 7 to
2128 * make it a positive value (Minimum value is -7).
2129 * However this means that values between 0 and 7 have
2130 * double meaning, and we should set a 7DBm boost flag.
2132 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2133 (info->default_power1 >= 0));
2135 if (info->default_power1 < 0)
2136 info->default_power1 += 7;
2138 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2140 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2141 (info->default_power2 >= 0));
2143 if (info->default_power2 < 0)
2144 info->default_power2 += 7;
2146 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2148 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2149 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2152 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2154 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2155 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2156 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2157 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2161 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2162 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2163 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2164 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2168 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2169 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2170 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2171 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2174 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2175 struct ieee80211_conf *conf,
2176 struct rf_channel *rf,
2177 struct channel_info *info)
2179 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2180 u8 rfcsr, calib_tx, calib_rx;
2182 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2185 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2186 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2188 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2189 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2190 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2192 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2193 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2194 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2196 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2197 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2198 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2200 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2201 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2202 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2203 rt2x00dev->default_ant.rx_chain_num <= 1);
2204 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2205 rt2x00dev->default_ant.rx_chain_num <= 2);
2206 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2207 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2208 rt2x00dev->default_ant.tx_chain_num <= 1);
2209 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2210 rt2x00dev->default_ant.tx_chain_num <= 2);
2211 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2213 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2214 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2215 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2217 if (rt2x00_rt(rt2x00dev, RT3390)) {
2218 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2219 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2221 if (conf_is_ht40(conf)) {
2222 calib_tx = drv_data->calibration_bw40;
2223 calib_rx = drv_data->calibration_bw40;
2225 calib_tx = drv_data->calibration_bw20;
2226 calib_rx = drv_data->calibration_bw20;
2230 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2231 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2232 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2234 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2235 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2236 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2238 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2239 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2240 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2242 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2243 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2244 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2246 usleep_range(1000, 1500);
2248 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2249 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2252 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2253 struct ieee80211_conf *conf,
2254 struct rf_channel *rf,
2255 struct channel_info *info)
2257 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2261 if (rf->channel <= 14) {
2262 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2263 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2265 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2266 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2269 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2270 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2272 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2273 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2274 if (rf->channel <= 14)
2275 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2277 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2278 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2280 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2281 if (rf->channel <= 14)
2282 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2284 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2285 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2287 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2288 if (rf->channel <= 14) {
2289 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2290 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2291 info->default_power1);
2293 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2294 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2295 (info->default_power1 & 0x3) |
2296 ((info->default_power1 & 0xC) << 1));
2298 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2300 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2301 if (rf->channel <= 14) {
2302 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2303 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2304 info->default_power2);
2306 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2307 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2308 (info->default_power2 & 0x3) |
2309 ((info->default_power2 & 0xC) << 1));
2311 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2313 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2314 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2315 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2316 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2317 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2318 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2319 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2320 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2321 if (rf->channel <= 14) {
2322 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2323 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2325 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2326 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2328 switch (rt2x00dev->default_ant.tx_chain_num) {
2330 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2332 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2336 switch (rt2x00dev->default_ant.rx_chain_num) {
2338 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2340 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2344 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2347 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2348 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2350 if (conf_is_ht40(conf)) {
2351 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2352 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2354 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2355 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2358 if (rf->channel <= 14) {
2359 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2360 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2361 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2362 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2363 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2365 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2366 drv_data->txmixer_gain_24g);
2367 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2368 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2369 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2370 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2371 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2372 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2373 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2374 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2376 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2377 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2378 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2379 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2380 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2381 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2382 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2383 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2384 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2385 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2387 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2388 drv_data->txmixer_gain_5g);
2389 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2390 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2391 if (rf->channel <= 64) {
2392 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2393 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2394 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2395 } else if (rf->channel <= 128) {
2396 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2397 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2398 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2400 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2401 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2402 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2404 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2405 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2406 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2409 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2410 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
2411 if (rf->channel <= 14)
2412 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
2414 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0);
2415 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2417 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2418 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2419 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2422 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2423 struct ieee80211_conf *conf,
2424 struct rf_channel *rf,
2425 struct channel_info *info)
2427 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2432 const bool txbf_enabled = false; /* TODO */
2434 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2435 bbp = rt2800_bbp_read(rt2x00dev, 109);
2436 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2437 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2438 rt2800_bbp_write(rt2x00dev, 109, bbp);
2440 bbp = rt2800_bbp_read(rt2x00dev, 110);
2441 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2442 rt2800_bbp_write(rt2x00dev, 110, bbp);
2444 if (rf->channel <= 14) {
2445 /* Restore BBP 25 & 26 for 2.4 GHz */
2446 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2447 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2449 /* Hard code BBP 25 & 26 for 5GHz */
2451 /* Enable IQ Phase correction */
2452 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2453 /* Setup IQ Phase correction value */
2454 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2457 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2458 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2460 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2461 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2462 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2464 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2465 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2466 if (rf->channel <= 14)
2467 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2469 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2470 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2472 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2473 if (rf->channel <= 14) {
2475 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2476 info->default_power1 & 0x1f);
2478 if (rt2x00_is_usb(rt2x00dev))
2481 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2482 ((info->default_power1 & 0x18) << 1) |
2483 (info->default_power1 & 7));
2485 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2487 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2488 if (rf->channel <= 14) {
2490 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2491 info->default_power2 & 0x1f);
2493 if (rt2x00_is_usb(rt2x00dev))
2496 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2497 ((info->default_power2 & 0x18) << 1) |
2498 (info->default_power2 & 7));
2500 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2503 if (rf->channel <= 14) {
2505 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2506 info->default_power3 & 0x1f);
2508 if (rt2x00_is_usb(rt2x00dev))
2511 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2512 ((info->default_power3 & 0x18) << 1) |
2513 (info->default_power3 & 7));
2515 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2517 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2518 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2519 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2520 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2522 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2523 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2524 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2525 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2527 switch (rt2x00dev->default_ant.tx_chain_num) {
2529 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2532 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2535 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2539 switch (rt2x00dev->default_ant.rx_chain_num) {
2541 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2544 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2547 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2550 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2552 rt2800_freq_cal_mode1(rt2x00dev);
2554 if (conf_is_ht40(conf)) {
2555 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2557 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2560 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2562 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2566 /* NOTE: the reference driver does not writes the new value
2569 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2570 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2572 if (rf->channel <= 14)
2576 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2578 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2579 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2580 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2581 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2583 /* Band selection */
2584 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2585 if (rf->channel <= 14)
2586 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2588 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2589 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2591 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2592 if (rf->channel <= 14)
2596 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2598 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2599 if (rf->channel <= 14)
2603 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2605 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2606 if (rf->channel >= 1 && rf->channel <= 14)
2607 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2608 else if (rf->channel >= 36 && rf->channel <= 64)
2609 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2610 else if (rf->channel >= 100 && rf->channel <= 128)
2611 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2613 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2614 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2616 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2617 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2618 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2620 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2622 if (rf->channel <= 14) {
2623 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2624 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2626 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2627 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2631 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2632 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2634 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2635 if (rf->channel <= 14) {
2636 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2637 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2639 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2640 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2642 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2644 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2645 if (rf->channel <= 14)
2646 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2648 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2651 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2653 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2655 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2656 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2657 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2660 if (rf->channel <= 14)
2661 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2663 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2664 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2666 if (rf->channel <= 14) {
2667 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2668 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2670 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2671 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2674 /* Initiate VCO calibration */
2675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2676 if (rf->channel <= 14) {
2677 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2679 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2680 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2681 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2682 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2683 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2684 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2686 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2688 if (rf->channel >= 1 && rf->channel <= 14) {
2691 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2692 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2694 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2695 } else if (rf->channel >= 36 && rf->channel <= 64) {
2698 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2699 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2701 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2702 } else if (rf->channel >= 100 && rf->channel <= 128) {
2705 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2706 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2708 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2712 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2713 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2715 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2719 #define POWER_BOUND 0x27
2720 #define POWER_BOUND_5G 0x2b
2722 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2723 struct ieee80211_conf *conf,
2724 struct rf_channel *rf,
2725 struct channel_info *info)
2729 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2730 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2731 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2732 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2733 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2735 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2736 if (info->default_power1 > POWER_BOUND)
2737 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2739 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2740 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2742 rt2800_freq_cal_mode1(rt2x00dev);
2744 if (rf->channel <= 14) {
2745 if (rf->channel == 6)
2746 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2748 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2750 if (rf->channel >= 1 && rf->channel <= 6)
2751 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2752 else if (rf->channel >= 7 && rf->channel <= 11)
2753 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2754 else if (rf->channel >= 12 && rf->channel <= 14)
2755 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2759 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2760 struct ieee80211_conf *conf,
2761 struct rf_channel *rf,
2762 struct channel_info *info)
2766 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2767 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2769 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2770 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2771 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2773 if (info->default_power1 > POWER_BOUND)
2774 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2776 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2778 if (info->default_power2 > POWER_BOUND)
2779 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2781 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2783 rt2800_freq_cal_mode1(rt2x00dev);
2785 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2786 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2787 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2789 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2790 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2792 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2794 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2795 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2797 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2799 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2800 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2802 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2804 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2807 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2808 struct ieee80211_conf *conf,
2809 struct rf_channel *rf,
2810 struct channel_info *info)
2814 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2815 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2816 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2817 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2818 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2820 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2821 if (info->default_power1 > POWER_BOUND)
2822 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2824 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2825 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2827 if (rt2x00_rt(rt2x00dev, RT5392)) {
2828 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2829 if (info->default_power2 > POWER_BOUND)
2830 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2832 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2833 info->default_power2);
2834 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2837 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2838 if (rt2x00_rt(rt2x00dev, RT5392)) {
2839 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2840 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2842 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2843 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2844 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2846 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2848 rt2800_freq_cal_mode1(rt2x00dev);
2850 if (rf->channel <= 14) {
2851 int idx = rf->channel-1;
2853 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2854 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2855 /* r55/r59 value array of channel 1~14 */
2856 static const char r55_bt_rev[] = {0x83, 0x83,
2857 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2858 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2859 static const char r59_bt_rev[] = {0x0e, 0x0e,
2860 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2861 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2863 rt2800_rfcsr_write(rt2x00dev, 55,
2865 rt2800_rfcsr_write(rt2x00dev, 59,
2868 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2869 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2870 0x88, 0x88, 0x86, 0x85, 0x84};
2872 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2875 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2876 static const char r55_nonbt_rev[] = {0x23, 0x23,
2877 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2878 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2879 static const char r59_nonbt_rev[] = {0x07, 0x07,
2880 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2881 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2883 rt2800_rfcsr_write(rt2x00dev, 55,
2884 r55_nonbt_rev[idx]);
2885 rt2800_rfcsr_write(rt2x00dev, 59,
2886 r59_nonbt_rev[idx]);
2887 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2888 rt2x00_rt(rt2x00dev, RT5392) ||
2889 rt2x00_rt(rt2x00dev, RT6352)) {
2890 static const char r59_non_bt[] = {0x8f, 0x8f,
2891 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2892 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2894 rt2800_rfcsr_write(rt2x00dev, 59,
2896 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
2897 static const char r59_non_bt[] = {0x0b, 0x0b,
2898 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
2899 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
2901 rt2800_rfcsr_write(rt2x00dev, 59,
2908 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2909 struct ieee80211_conf *conf,
2910 struct rf_channel *rf,
2911 struct channel_info *info)
2918 const bool is_11b = false;
2919 const bool is_type_ep = false;
2921 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
2922 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL,
2923 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2924 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2926 /* Order of values on rf_channel entry: N, K, mod, R */
2927 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2929 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
2930 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2931 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2932 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2933 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2935 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2936 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2937 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2938 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2940 if (rf->channel <= 14) {
2941 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2942 /* FIXME: RF11 owerwrite ? */
2943 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2944 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2945 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2946 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2947 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2948 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2949 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2950 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2951 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2952 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2953 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2954 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2955 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2956 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2957 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2958 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2959 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2960 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2961 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2962 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2963 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2964 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2965 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2966 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2967 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2968 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2969 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2970 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2972 /* TODO RF27 <- tssi */
2974 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2975 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2976 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2980 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2981 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2983 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2985 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2989 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2991 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2994 power_bound = POWER_BOUND;
2997 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2998 /* FIMXE: RF11 overwrite */
2999 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3000 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3001 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3002 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3003 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3004 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3005 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3006 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3007 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3008 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3009 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3010 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3011 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3012 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3014 /* TODO RF27 <- tssi */
3016 if (rf->channel >= 36 && rf->channel <= 64) {
3018 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3019 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3020 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3021 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3022 if (rf->channel <= 50)
3023 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3024 else if (rf->channel >= 52)
3025 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3026 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3027 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3028 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3029 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3030 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3031 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3032 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3033 if (rf->channel <= 50) {
3034 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3035 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3036 } else if (rf->channel >= 52) {
3037 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3038 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3041 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3042 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3043 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3045 } else if (rf->channel >= 100 && rf->channel <= 165) {
3047 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3048 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3049 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3050 if (rf->channel <= 153) {
3051 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3052 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3053 } else if (rf->channel >= 155) {
3054 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3055 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3057 if (rf->channel <= 138) {
3058 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3059 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3060 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3061 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3062 } else if (rf->channel >= 140) {
3063 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3064 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3065 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3066 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3068 if (rf->channel <= 124)
3069 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3070 else if (rf->channel >= 126)
3071 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3072 if (rf->channel <= 138)
3073 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3074 else if (rf->channel >= 140)
3075 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3076 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3077 if (rf->channel <= 138)
3078 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3079 else if (rf->channel >= 140)
3080 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3081 if (rf->channel <= 128)
3082 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3083 else if (rf->channel >= 130)
3084 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3085 if (rf->channel <= 116)
3086 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3087 else if (rf->channel >= 118)
3088 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3089 if (rf->channel <= 138)
3090 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3091 else if (rf->channel >= 140)
3092 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3093 if (rf->channel <= 116)
3094 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3095 else if (rf->channel >= 118)
3096 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3099 power_bound = POWER_BOUND_5G;
3103 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3104 if (info->default_power1 > power_bound)
3105 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3107 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3109 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3110 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3112 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3113 if (info->default_power2 > power_bound)
3114 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3116 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3118 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3119 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3121 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3122 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3123 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3125 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3126 rt2x00dev->default_ant.tx_chain_num >= 1);
3127 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3128 rt2x00dev->default_ant.tx_chain_num == 2);
3129 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3131 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3132 rt2x00dev->default_ant.rx_chain_num >= 1);
3133 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3134 rt2x00dev->default_ant.rx_chain_num == 2);
3135 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3137 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3138 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3140 if (conf_is_ht40(conf))
3141 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3143 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3146 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3147 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3150 /* TODO proper frequency adjustment */
3151 rt2800_freq_cal_mode1(rt2x00dev);
3153 /* TODO merge with others */
3154 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3155 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3156 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3159 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3160 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3161 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3163 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3164 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3165 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3166 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3168 /* GLRT band configuration */
3169 rt2800_bbp_write(rt2x00dev, 195, 128);
3170 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3171 rt2800_bbp_write(rt2x00dev, 195, 129);
3172 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3173 rt2800_bbp_write(rt2x00dev, 195, 130);
3174 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3175 rt2800_bbp_write(rt2x00dev, 195, 131);
3176 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3177 rt2800_bbp_write(rt2x00dev, 195, 133);
3178 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3179 rt2800_bbp_write(rt2x00dev, 195, 124);
3180 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3183 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3184 struct ieee80211_conf *conf,
3185 struct rf_channel *rf,
3186 struct channel_info *info)
3188 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3189 u8 rx_agc_fc, tx_agc_fc;
3192 /* Frequeny plan setting */
3193 /* Rdiv setting (set 0x03 if Xtal==20)
3196 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3197 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3198 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3199 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3202 * R20[7:0] in rf->rf1
3205 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3206 rfcsr = (rf->rf1 & 0x00ff);
3207 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3209 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3210 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3211 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3213 /* K setting (always 0)
3214 * R16[3:0] (RF PLL freq selection)
3216 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3217 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3218 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3220 /* D setting (always 0)
3221 * R22[2:0] (D=15, R22[2:0]=<111>)
3223 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3224 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3225 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3228 * Ksd: R17<7:0> in rf->rf2
3229 * R18<7:0> in rf->rf3
3230 * R19<1:0> in rf->rf4
3232 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3234 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3238 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3240 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3241 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3242 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3244 /* Default: XO=20MHz , SDM mode */
3245 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3246 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3247 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3249 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3250 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3251 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3253 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3254 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3255 rt2x00dev->default_ant.tx_chain_num != 1);
3256 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3259 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3260 rt2x00dev->default_ant.tx_chain_num != 1);
3261 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3262 rt2x00dev->default_ant.rx_chain_num != 1);
3263 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3265 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3266 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3267 rt2x00dev->default_ant.tx_chain_num != 1);
3268 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3270 /* RF for DC Cal BW */
3271 if (conf_is_ht40(conf)) {
3272 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3273 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3274 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3275 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3276 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3278 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3279 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3280 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3281 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3282 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3285 if (conf_is_ht40(conf)) {
3286 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3287 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3289 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3290 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3293 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3294 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3295 conf_is_ht40(conf) && (rf->channel == 11));
3296 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3298 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3299 if (conf_is_ht40(conf)) {
3300 rx_agc_fc = drv_data->rx_calibration_bw40;
3301 tx_agc_fc = drv_data->tx_calibration_bw40;
3303 rx_agc_fc = drv_data->rx_calibration_bw20;
3304 tx_agc_fc = drv_data->tx_calibration_bw20;
3306 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3310 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3313 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3314 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3317 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3318 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3321 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3323 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3326 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3327 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3330 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3331 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3334 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3335 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3338 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3342 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3343 struct ieee80211_channel *chan,
3345 u16 eeprom, target_power, max_power;
3346 u32 mac_sys_ctrl, mac_status;
3351 /* hardware unit is 0.5dBm, limited to 23.5dBm */
3353 if (power_level > 0x2f)
3356 max_power = chan->max_power * 2;
3357 if (max_power > 0x2f)
3360 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3361 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level);
3362 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level);
3363 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power);
3364 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power);
3366 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3367 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3368 /* init base power by eeprom target power */
3369 target_power = rt2800_eeprom_read(rt2x00dev,
3370 EEPROM_TXPOWER_INIT);
3371 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power);
3372 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power);
3374 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3376 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3377 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3378 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3380 /* Save MAC SYS CTRL registers */
3381 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3383 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3384 /* Check MAC Tx/Rx idle */
3385 for (i = 0; i < 10000; i++) {
3386 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3387 if (mac_status & 0x3)
3388 usleep_range(50, 200);
3394 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3396 if (chan->center_freq > 2457) {
3397 bbp = rt2800_bbp_read(rt2x00dev, 30);
3399 rt2800_bbp_write(rt2x00dev, 30, bbp);
3400 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3401 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3402 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3404 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3406 bbp = rt2800_bbp_read(rt2x00dev, 30);
3408 rt2800_bbp_write(rt2x00dev, 30, bbp);
3409 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3410 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3411 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3413 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3415 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3417 rt2800_vco_calibration(rt2x00dev);
3420 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3421 const unsigned int word,
3426 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3427 reg = rt2800_bbp_read(rt2x00dev, 27);
3428 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain);
3429 rt2800_bbp_write(rt2x00dev, 27, reg);
3431 rt2800_bbp_write(rt2x00dev, word, value);
3435 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3440 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3442 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3443 else if (channel >= 36 && channel <= 64)
3444 cal = rt2x00_eeprom_byte(rt2x00dev,
3445 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3446 else if (channel >= 100 && channel <= 138)
3447 cal = rt2x00_eeprom_byte(rt2x00dev,
3448 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3449 else if (channel >= 140 && channel <= 165)
3450 cal = rt2x00_eeprom_byte(rt2x00dev,
3451 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3454 rt2800_bbp_write(rt2x00dev, 159, cal);
3457 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3459 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3460 else if (channel >= 36 && channel <= 64)
3461 cal = rt2x00_eeprom_byte(rt2x00dev,
3462 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3463 else if (channel >= 100 && channel <= 138)
3464 cal = rt2x00_eeprom_byte(rt2x00dev,
3465 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3466 else if (channel >= 140 && channel <= 165)
3467 cal = rt2x00_eeprom_byte(rt2x00dev,
3468 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3471 rt2800_bbp_write(rt2x00dev, 159, cal);
3474 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3476 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3477 else if (channel >= 36 && channel <= 64)
3478 cal = rt2x00_eeprom_byte(rt2x00dev,
3479 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3480 else if (channel >= 100 && channel <= 138)
3481 cal = rt2x00_eeprom_byte(rt2x00dev,
3482 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3483 else if (channel >= 140 && channel <= 165)
3484 cal = rt2x00_eeprom_byte(rt2x00dev,
3485 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3488 rt2800_bbp_write(rt2x00dev, 159, cal);
3491 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3493 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3494 else if (channel >= 36 && channel <= 64)
3495 cal = rt2x00_eeprom_byte(rt2x00dev,
3496 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3497 else if (channel >= 100 && channel <= 138)
3498 cal = rt2x00_eeprom_byte(rt2x00dev,
3499 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3500 else if (channel >= 140 && channel <= 165)
3501 cal = rt2x00_eeprom_byte(rt2x00dev,
3502 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3505 rt2800_bbp_write(rt2x00dev, 159, cal);
3507 /* FIXME: possible RX0, RX1 callibration ? */
3509 /* RF IQ compensation control */
3510 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3511 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3512 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3514 /* RF IQ imbalance compensation control */
3515 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3516 cal = rt2x00_eeprom_byte(rt2x00dev,
3517 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3518 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3521 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3522 unsigned int channel,
3525 if (rt2x00_rt(rt2x00dev, RT3593))
3526 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3529 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3531 if (rt2x00_rt(rt2x00dev, RT3593))
3532 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3533 MAX_A_TXPOWER_3593);
3535 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3538 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3539 struct ieee80211_conf *conf,
3540 struct rf_channel *rf,
3541 struct channel_info *info)
3547 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3548 info->default_power1);
3549 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3550 info->default_power2);
3551 if (rt2x00dev->default_ant.tx_chain_num > 2)
3552 info->default_power3 =
3553 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3554 info->default_power3);
3556 switch (rt2x00dev->chip.rf) {
3562 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3565 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3568 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3571 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3574 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3584 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3587 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3590 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3593 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3596 if (rt2x00_rf(rt2x00dev, RF3070) ||
3597 rt2x00_rf(rt2x00dev, RF3290) ||
3598 rt2x00_rf(rt2x00dev, RF3322) ||
3599 rt2x00_rf(rt2x00dev, RF5350) ||
3600 rt2x00_rf(rt2x00dev, RF5360) ||
3601 rt2x00_rf(rt2x00dev, RF5362) ||
3602 rt2x00_rf(rt2x00dev, RF5370) ||
3603 rt2x00_rf(rt2x00dev, RF5372) ||
3604 rt2x00_rf(rt2x00dev, RF5390) ||
3605 rt2x00_rf(rt2x00dev, RF5392)) {
3606 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3607 if (rt2x00_rf(rt2x00dev, RF3322)) {
3608 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3609 conf_is_ht40(conf));
3610 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3611 conf_is_ht40(conf));
3613 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3614 conf_is_ht40(conf));
3615 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3616 conf_is_ht40(conf));
3618 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3620 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3621 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3622 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3626 * Change BBP settings
3629 if (rt2x00_rt(rt2x00dev, RT3352)) {
3630 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3631 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3632 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3634 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3635 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3636 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3637 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3638 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3639 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3640 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3641 if (rf->channel > 14) {
3642 /* Disable CCK Packet detection on 5GHz */
3643 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3645 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3648 if (conf_is_ht40(conf))
3649 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3651 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3653 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3654 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3655 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3656 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3658 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3659 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3660 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3661 if (rt2x00_rt(rt2x00dev, RT6352))
3662 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3664 rt2800_bbp_write(rt2x00dev, 86, 0);
3667 if (rf->channel <= 14) {
3668 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3669 !rt2x00_rt(rt2x00dev, RT5392) &&
3670 !rt2x00_rt(rt2x00dev, RT6352)) {
3671 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3672 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3673 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3675 if (rt2x00_rt(rt2x00dev, RT3593))
3676 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3678 rt2800_bbp_write(rt2x00dev, 82, 0x84);
3679 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3681 if (rt2x00_rt(rt2x00dev, RT3593))
3682 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3686 if (rt2x00_rt(rt2x00dev, RT3572))
3687 rt2800_bbp_write(rt2x00dev, 82, 0x94);
3688 else if (rt2x00_rt(rt2x00dev, RT3593))
3689 rt2800_bbp_write(rt2x00dev, 82, 0x82);
3690 else if (!rt2x00_rt(rt2x00dev, RT6352))
3691 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3693 if (rt2x00_rt(rt2x00dev, RT3593))
3694 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3696 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3697 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3699 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3702 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
3703 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3704 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
3705 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
3706 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3708 if (rt2x00_rt(rt2x00dev, RT3572))
3709 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3711 if (rt2x00_rt(rt2x00dev, RT6352))
3712 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
3716 switch (rt2x00dev->default_ant.tx_chain_num) {
3718 /* Turn on tertiary PAs */
3719 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3721 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3725 /* Turn on secondary PAs */
3726 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3728 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3732 /* Turn on primary PAs */
3733 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3735 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3736 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3738 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3743 switch (rt2x00dev->default_ant.rx_chain_num) {
3745 /* Turn on tertiary LNAs */
3746 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3747 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3750 /* Turn on secondary LNAs */
3751 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3752 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3755 /* Turn on primary LNAs */
3756 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3757 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3761 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3762 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3763 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
3765 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3767 if (rt2x00_rt(rt2x00dev, RT3572)) {
3768 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3771 if (rf->channel <= 14)
3772 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3774 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3776 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3779 if (rt2x00_rt(rt2x00dev, RT3593)) {
3780 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
3782 /* Band selection */
3783 if (rt2x00_is_usb(rt2x00dev) ||
3784 rt2x00_is_pcie(rt2x00dev)) {
3785 /* GPIO #8 controls all paths */
3786 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0);
3787 if (rf->channel <= 14)
3788 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1);
3790 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0);
3793 /* LNA PE control. */
3794 if (rt2x00_is_usb(rt2x00dev)) {
3795 /* GPIO #4 controls PE0 and PE1,
3796 * GPIO #7 controls PE2
3798 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
3799 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
3801 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
3802 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
3803 } else if (rt2x00_is_pcie(rt2x00dev)) {
3804 /* GPIO #4 controls PE0, PE1 and PE2 */
3805 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
3806 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
3809 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3812 if (rf->channel <= 14)
3813 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3815 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3817 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3819 usleep_range(1000, 1500);
3822 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
3824 if (!conf_is_ht40(conf)) {
3825 if (rt2x00_rt(rt2x00dev, RT6352) &&
3826 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3832 rt2800_bbp_write(rt2x00dev, 195, 141);
3833 rt2800_bbp_write(rt2x00dev, 196, reg);
3836 if (rt2x00_rt(rt2x00dev, RT6352))
3839 reg = rf->channel <= 14 ? 0x1c : 0x24;
3841 reg += 2 * rt2x00dev->lna_gain;
3842 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3844 if (rt2x00_rt(rt2x00dev, RT5592))
3845 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3848 bbp = rt2800_bbp_read(rt2x00dev, 4);
3849 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3850 rt2800_bbp_write(rt2x00dev, 4, bbp);
3852 bbp = rt2800_bbp_read(rt2x00dev, 3);
3853 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3854 rt2800_bbp_write(rt2x00dev, 3, bbp);
3856 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3857 if (conf_is_ht40(conf)) {
3858 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3859 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3860 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3862 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3863 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3864 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3868 usleep_range(1000, 1500);
3871 * Clear channel statistic counters
3873 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
3874 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
3875 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
3880 if (rt2x00_rt(rt2x00dev, RT3352) ||
3881 rt2x00_rt(rt2x00dev, RT5350)) {
3882 bbp = rt2800_bbp_read(rt2x00dev, 49);
3883 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3884 rt2800_bbp_write(rt2x00dev, 49, bbp);
3888 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3897 * First check if temperature compensation is supported.
3899 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3900 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3904 * Read TSSI boundaries for temperature compensation from
3907 * Array idx 0 1 2 3 4 5 6 7 8
3908 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3909 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3911 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3912 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
3913 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3914 EEPROM_TSSI_BOUND_BG1_MINUS4);
3915 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3916 EEPROM_TSSI_BOUND_BG1_MINUS3);
3918 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
3919 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3920 EEPROM_TSSI_BOUND_BG2_MINUS2);
3921 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3922 EEPROM_TSSI_BOUND_BG2_MINUS1);
3924 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
3925 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3926 EEPROM_TSSI_BOUND_BG3_REF);
3927 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3928 EEPROM_TSSI_BOUND_BG3_PLUS1);
3930 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
3931 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3932 EEPROM_TSSI_BOUND_BG4_PLUS2);
3933 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3934 EEPROM_TSSI_BOUND_BG4_PLUS3);
3936 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
3937 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3938 EEPROM_TSSI_BOUND_BG5_PLUS4);
3940 step = rt2x00_get_field16(eeprom,
3941 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3943 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
3944 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3945 EEPROM_TSSI_BOUND_A1_MINUS4);
3946 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3947 EEPROM_TSSI_BOUND_A1_MINUS3);
3949 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
3950 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3951 EEPROM_TSSI_BOUND_A2_MINUS2);
3952 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3953 EEPROM_TSSI_BOUND_A2_MINUS1);
3955 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
3956 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3957 EEPROM_TSSI_BOUND_A3_REF);
3958 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3959 EEPROM_TSSI_BOUND_A3_PLUS1);
3961 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
3962 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3963 EEPROM_TSSI_BOUND_A4_PLUS2);
3964 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3965 EEPROM_TSSI_BOUND_A4_PLUS3);
3967 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
3968 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3969 EEPROM_TSSI_BOUND_A5_PLUS4);
3971 step = rt2x00_get_field16(eeprom,
3972 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3976 * Check if temperature compensation is supported.
3978 if (tssi_bounds[4] == 0xff || step == 0xff)
3982 * Read current TSSI (BBP 49).
3984 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
3987 * Compare TSSI value (BBP49) with the compensation boundaries
3988 * from the EEPROM and increase or decrease tx power.
3990 for (i = 0; i <= 3; i++) {
3991 if (current_tssi > tssi_bounds[i])
3996 for (i = 8; i >= 5; i--) {
3997 if (current_tssi < tssi_bounds[i])
4002 return (i - 4) * step;
4005 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4006 enum nl80211_band band)
4013 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4016 * HT40 compensation not required.
4018 if (eeprom == 0xffff ||
4019 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4022 if (band == NL80211_BAND_2GHZ) {
4023 comp_en = rt2x00_get_field16(eeprom,
4024 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4026 comp_type = rt2x00_get_field16(eeprom,
4027 EEPROM_TXPOWER_DELTA_TYPE_2G);
4028 comp_value = rt2x00_get_field16(eeprom,
4029 EEPROM_TXPOWER_DELTA_VALUE_2G);
4031 comp_value = -comp_value;
4034 comp_en = rt2x00_get_field16(eeprom,
4035 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4037 comp_type = rt2x00_get_field16(eeprom,
4038 EEPROM_TXPOWER_DELTA_TYPE_5G);
4039 comp_value = rt2x00_get_field16(eeprom,
4040 EEPROM_TXPOWER_DELTA_VALUE_5G);
4042 comp_value = -comp_value;
4049 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4050 int power_level, int max_power)
4054 if (rt2x00_has_cap_power_limit(rt2x00dev))
4058 * XXX: We don't know the maximum transmit power of our hardware since
4059 * the EEPROM doesn't expose it. We only know that we are calibrated
4062 * Hence, we assume the regulatory limit that cfg80211 calulated for
4063 * the current channel is our maximum and if we are requested to lower
4064 * the value we just reduce our tx power accordingly.
4066 delta = power_level - max_power;
4067 return min(delta, 0);
4070 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4071 enum nl80211_band band, int power_level,
4072 u8 txpower, int delta)
4077 u8 eirp_txpower_criterion;
4080 if (rt2x00_rt(rt2x00dev, RT3593))
4081 return min_t(u8, txpower, 0xc);
4083 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4085 * Check if eirp txpower exceed txpower_limit.
4086 * We use OFDM 6M as criterion and its eirp txpower
4087 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4088 * .11b data rate need add additional 4dbm
4089 * when calculating eirp txpower.
4091 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4092 EEPROM_TXPOWER_BYRATE,
4094 criterion = rt2x00_get_field16(eeprom,
4095 EEPROM_TXPOWER_BYRATE_RATE0);
4097 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4099 if (band == NL80211_BAND_2GHZ)
4100 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4101 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4103 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4104 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4106 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4107 (is_rate_b ? 4 : 0) + delta;
4109 reg_limit = (eirp_txpower > power_level) ?
4110 (eirp_txpower - power_level) : 0;
4114 txpower = max(0, txpower + delta - reg_limit);
4115 return min_t(u8, txpower, 0xc);
4130 TX_PWR_CFG_0_EXT_IDX,
4131 TX_PWR_CFG_1_EXT_IDX,
4132 TX_PWR_CFG_2_EXT_IDX,
4133 TX_PWR_CFG_3_EXT_IDX,
4134 TX_PWR_CFG_4_EXT_IDX,
4135 TX_PWR_CFG_IDX_COUNT,
4138 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4139 struct ieee80211_channel *chan,
4144 u32 regs[TX_PWR_CFG_IDX_COUNT];
4145 unsigned int offset;
4146 enum nl80211_band band = chan->band;
4150 memset(regs, '\0', sizeof(regs));
4152 /* TODO: adapt TX power reduction from the rt28xx code */
4154 /* calculate temperature compensation delta */
4155 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4157 if (band == NL80211_BAND_5GHZ)
4162 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4165 /* read the next four txpower values */
4166 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4170 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4171 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4173 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4174 TX_PWR_CFG_0_CCK1_CH0, txpower);
4175 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4176 TX_PWR_CFG_0_CCK1_CH1, txpower);
4177 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4178 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4180 /* CCK 5.5MBS,11MBS */
4181 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4182 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4184 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4185 TX_PWR_CFG_0_CCK5_CH0, txpower);
4186 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4187 TX_PWR_CFG_0_CCK5_CH1, txpower);
4188 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4189 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4191 /* OFDM 6MBS,9MBS */
4192 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4193 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4195 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4196 TX_PWR_CFG_0_OFDM6_CH0, txpower);
4197 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4198 TX_PWR_CFG_0_OFDM6_CH1, txpower);
4199 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4200 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4202 /* OFDM 12MBS,18MBS */
4203 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4204 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4206 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4207 TX_PWR_CFG_0_OFDM12_CH0, txpower);
4208 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4209 TX_PWR_CFG_0_OFDM12_CH1, txpower);
4210 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4211 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4213 /* read the next four txpower values */
4214 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4217 /* OFDM 24MBS,36MBS */
4218 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4219 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4221 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4222 TX_PWR_CFG_1_OFDM24_CH0, txpower);
4223 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4224 TX_PWR_CFG_1_OFDM24_CH1, txpower);
4225 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4226 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4229 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4230 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4232 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4233 TX_PWR_CFG_1_OFDM48_CH0, txpower);
4234 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4235 TX_PWR_CFG_1_OFDM48_CH1, txpower);
4236 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4237 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4240 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4241 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4243 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4244 TX_PWR_CFG_7_OFDM54_CH0, txpower);
4245 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4246 TX_PWR_CFG_7_OFDM54_CH1, txpower);
4247 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4248 TX_PWR_CFG_7_OFDM54_CH2, txpower);
4250 /* read the next four txpower values */
4251 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4255 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4256 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4258 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4259 TX_PWR_CFG_1_MCS0_CH0, txpower);
4260 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4261 TX_PWR_CFG_1_MCS0_CH1, txpower);
4262 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4263 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4266 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4267 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4269 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4270 TX_PWR_CFG_1_MCS2_CH0, txpower);
4271 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4272 TX_PWR_CFG_1_MCS2_CH1, txpower);
4273 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4274 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4277 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4278 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4280 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4281 TX_PWR_CFG_2_MCS4_CH0, txpower);
4282 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4283 TX_PWR_CFG_2_MCS4_CH1, txpower);
4284 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4285 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4288 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4289 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4291 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4292 TX_PWR_CFG_2_MCS6_CH0, txpower);
4293 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4294 TX_PWR_CFG_2_MCS6_CH1, txpower);
4295 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4296 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4298 /* read the next four txpower values */
4299 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4303 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4304 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4306 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4307 TX_PWR_CFG_7_MCS7_CH0, txpower);
4308 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4309 TX_PWR_CFG_7_MCS7_CH1, txpower);
4310 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4311 TX_PWR_CFG_7_MCS7_CH2, txpower);
4314 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4315 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4317 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4318 TX_PWR_CFG_2_MCS8_CH0, txpower);
4319 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4320 TX_PWR_CFG_2_MCS8_CH1, txpower);
4321 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4322 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4325 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4326 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4328 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4329 TX_PWR_CFG_2_MCS10_CH0, txpower);
4330 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4331 TX_PWR_CFG_2_MCS10_CH1, txpower);
4332 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4333 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4336 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4337 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4339 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4340 TX_PWR_CFG_3_MCS12_CH0, txpower);
4341 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4342 TX_PWR_CFG_3_MCS12_CH1, txpower);
4343 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4344 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4346 /* read the next four txpower values */
4347 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4351 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4352 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4354 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4355 TX_PWR_CFG_3_MCS14_CH0, txpower);
4356 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4357 TX_PWR_CFG_3_MCS14_CH1, txpower);
4358 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4359 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4362 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4363 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4365 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4366 TX_PWR_CFG_8_MCS15_CH0, txpower);
4367 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4368 TX_PWR_CFG_8_MCS15_CH1, txpower);
4369 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4370 TX_PWR_CFG_8_MCS15_CH2, txpower);
4373 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4374 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4376 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4377 TX_PWR_CFG_5_MCS16_CH0, txpower);
4378 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4379 TX_PWR_CFG_5_MCS16_CH1, txpower);
4380 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4381 TX_PWR_CFG_5_MCS16_CH2, txpower);
4384 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4385 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4387 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4388 TX_PWR_CFG_5_MCS18_CH0, txpower);
4389 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4390 TX_PWR_CFG_5_MCS18_CH1, txpower);
4391 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4392 TX_PWR_CFG_5_MCS18_CH2, txpower);
4394 /* read the next four txpower values */
4395 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4399 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4400 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4402 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4403 TX_PWR_CFG_6_MCS20_CH0, txpower);
4404 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4405 TX_PWR_CFG_6_MCS20_CH1, txpower);
4406 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4407 TX_PWR_CFG_6_MCS20_CH2, txpower);
4410 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4411 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4413 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4414 TX_PWR_CFG_6_MCS22_CH0, txpower);
4415 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4416 TX_PWR_CFG_6_MCS22_CH1, txpower);
4417 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4418 TX_PWR_CFG_6_MCS22_CH2, txpower);
4421 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4422 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4424 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4425 TX_PWR_CFG_8_MCS23_CH0, txpower);
4426 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4427 TX_PWR_CFG_8_MCS23_CH1, txpower);
4428 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4429 TX_PWR_CFG_8_MCS23_CH2, txpower);
4431 /* read the next four txpower values */
4432 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4436 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4437 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4439 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4440 TX_PWR_CFG_3_STBC0_CH0, txpower);
4441 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4442 TX_PWR_CFG_3_STBC0_CH1, txpower);
4443 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4444 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4447 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4448 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4450 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4451 TX_PWR_CFG_3_STBC2_CH0, txpower);
4452 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4453 TX_PWR_CFG_3_STBC2_CH1, txpower);
4454 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4455 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4458 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4459 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4461 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4462 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4463 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4467 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4468 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4470 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4471 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4472 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4475 /* read the next four txpower values */
4476 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4480 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4481 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4483 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4484 TX_PWR_CFG_9_STBC7_CH0, txpower);
4485 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4486 TX_PWR_CFG_9_STBC7_CH1, txpower);
4487 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4488 TX_PWR_CFG_9_STBC7_CH2, txpower);
4490 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4491 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4492 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4493 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4494 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4495 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4496 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4497 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4498 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4499 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4501 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4502 regs[TX_PWR_CFG_0_EXT_IDX]);
4503 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4504 regs[TX_PWR_CFG_1_EXT_IDX]);
4505 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4506 regs[TX_PWR_CFG_2_EXT_IDX]);
4507 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4508 regs[TX_PWR_CFG_3_EXT_IDX]);
4509 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4510 regs[TX_PWR_CFG_4_EXT_IDX]);
4512 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4513 rt2x00_dbg(rt2x00dev,
4514 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4515 (band == NL80211_BAND_5GHZ) ? '5' : '2',
4516 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4518 (i > TX_PWR_CFG_9_IDX) ?
4519 (i - TX_PWR_CFG_9_IDX - 1) : i,
4520 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4521 (unsigned long) regs[i]);
4524 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4525 struct ieee80211_channel *chan,
4532 enum nl80211_band band = chan->band;
4535 /* Warn user if bw_comp is set in EEPROM */
4536 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4539 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4542 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4543 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4544 * driver does as well, though it looks kinda wrong.
4545 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4546 * the hardware has a problem handling 0x20, and as the code initially
4547 * used a fixed offset between HT20 and HT40 rates they had to work-
4548 * around that issue and most likely just forgot about it later on.
4549 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4550 * however, the corresponding EEPROM value is not respected by the
4551 * vendor driver, so maybe this is rather being taken care of the
4552 * TXALC and the driver doesn't need to handle it...?
4553 * Though this is all very awkward, just do as they did, as that's what
4554 * board vendors expected when they populated the EEPROM...
4556 for (i = 0; i < 5; i++) {
4557 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4558 EEPROM_TXPOWER_BYRATE,
4569 t = (eeprom & 0x3f00) >> 8;
4575 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4576 EEPROM_TXPOWER_BYRATE,
4585 t = (eeprom & 0x3f00) >> 8;
4590 data |= (eeprom << 16);
4592 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4594 if (data != 0xffffffff)
4595 rt2800_register_write(rt2x00dev,
4596 TX_PWR_CFG_0 + (i * 4),
4600 if (gdata != 0xffffffff)
4601 rt2800_register_write(rt2x00dev,
4602 TX_PWR_CFG_0 + (i * 4),
4607 /* Aparently Ralink ran out of space in the BYRATE calibration section
4608 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4609 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4610 * power-offsets more space would be needed. Ralink decided to keep the
4611 * EEPROM layout untouched and rather have some shared values covering
4612 * multiple bitrates.
4613 * Populate the registers not covered by the EEPROM in the same way the
4614 * vendor driver does.
4617 /* For OFDM 54MBS use value from OFDM 48MBS */
4619 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
4620 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4621 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4623 /* For MCS 7 use value from MCS 6 */
4624 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
4625 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4626 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4627 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4629 /* For MCS 15 use value from MCS 14 */
4631 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
4632 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4633 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4634 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4636 /* For STBC MCS 7 use value from STBC MCS 6 */
4638 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
4639 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4640 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4641 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4643 rt2800_config_alc(rt2x00dev, chan, power_level);
4645 /* TODO: temperature compensation code! */
4649 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4650 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4651 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4652 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4653 * Reference per rate transmit power values are located in the EEPROM at
4654 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4655 * current conditions (i.e. band, bandwidth, temperature, user settings).
4657 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4658 struct ieee80211_channel *chan,
4664 int i, is_rate_b, delta, power_ctrl;
4665 enum nl80211_band band = chan->band;
4668 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4669 * value read from EEPROM (different for 2GHz and for 5GHz).
4671 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4674 * Calculate temperature compensation. Depends on measurement of current
4675 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4676 * to temperature or maybe other factors) is smaller or bigger than
4677 * expected. We adjust it, based on TSSI reference and boundaries values
4678 * provided in EEPROM.
4680 switch (rt2x00dev->chip.rt) {
4688 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4691 /* TODO: temperature compensation code for other chips. */
4696 * Decrease power according to user settings, on devices with unknown
4697 * maximum tx power. For other devices we take user power_level into
4698 * consideration on rt2800_compensate_txpower().
4700 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4704 * BBP_R1 controls TX power for all rates, it allow to set the following
4705 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4707 * TODO: we do not use +6 dBm option to do not increase power beyond
4708 * regulatory limit, however this could be utilized for devices with
4709 * CAPABILITY_POWER_LIMIT.
4714 } else if (delta <= -6) {
4720 r1 = rt2800_bbp_read(rt2x00dev, 1);
4721 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4722 rt2800_bbp_write(rt2x00dev, 1, r1);
4724 offset = TX_PWR_CFG_0;
4726 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4727 /* just to be safe */
4728 if (offset > TX_PWR_CFG_4)
4731 reg = rt2800_register_read(rt2x00dev, offset);
4733 /* read the next four txpower values */
4734 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4735 EEPROM_TXPOWER_BYRATE,
4738 is_rate_b = i ? 0 : 1;
4740 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4741 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4742 * TX_PWR_CFG_4: unknown
4744 txpower = rt2x00_get_field16(eeprom,
4745 EEPROM_TXPOWER_BYRATE_RATE0);
4746 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4747 power_level, txpower, delta);
4748 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
4751 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4752 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4753 * TX_PWR_CFG_4: unknown
4755 txpower = rt2x00_get_field16(eeprom,
4756 EEPROM_TXPOWER_BYRATE_RATE1);
4757 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4758 power_level, txpower, delta);
4759 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
4762 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4763 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4764 * TX_PWR_CFG_4: unknown
4766 txpower = rt2x00_get_field16(eeprom,
4767 EEPROM_TXPOWER_BYRATE_RATE2);
4768 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4769 power_level, txpower, delta);
4770 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
4773 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4774 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4775 * TX_PWR_CFG_4: unknown
4777 txpower = rt2x00_get_field16(eeprom,
4778 EEPROM_TXPOWER_BYRATE_RATE3);
4779 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4780 power_level, txpower, delta);
4781 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
4783 /* read the next four txpower values */
4784 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4785 EEPROM_TXPOWER_BYRATE,
4790 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4791 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4792 * TX_PWR_CFG_4: unknown
4794 txpower = rt2x00_get_field16(eeprom,
4795 EEPROM_TXPOWER_BYRATE_RATE0);
4796 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4797 power_level, txpower, delta);
4798 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
4801 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4802 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4803 * TX_PWR_CFG_4: unknown
4805 txpower = rt2x00_get_field16(eeprom,
4806 EEPROM_TXPOWER_BYRATE_RATE1);
4807 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4808 power_level, txpower, delta);
4809 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
4812 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4813 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4814 * TX_PWR_CFG_4: unknown
4816 txpower = rt2x00_get_field16(eeprom,
4817 EEPROM_TXPOWER_BYRATE_RATE2);
4818 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4819 power_level, txpower, delta);
4820 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
4823 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4824 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4825 * TX_PWR_CFG_4: unknown
4827 txpower = rt2x00_get_field16(eeprom,
4828 EEPROM_TXPOWER_BYRATE_RATE3);
4829 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4830 power_level, txpower, delta);
4831 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
4833 rt2800_register_write(rt2x00dev, offset, reg);
4835 /* next TX_PWR_CFG register */
4840 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4841 struct ieee80211_channel *chan,
4844 if (rt2x00_rt(rt2x00dev, RT3593))
4845 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4846 else if (rt2x00_rt(rt2x00dev, RT6352))
4847 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
4849 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4852 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4854 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4855 rt2x00dev->tx_power);
4857 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4859 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4863 unsigned long min_sleep = 0;
4866 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4867 * designed to be controlled in oscillation frequency by a voltage
4868 * input. Maybe the temperature will affect the frequency of
4869 * oscillation to be shifted. The VCO calibration will be called
4870 * periodically to adjust the frequency to be precision.
4873 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4874 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4875 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4877 switch (rt2x00dev->chip.rf) {
4884 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
4885 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4886 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4899 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4900 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4901 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4905 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
4906 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
4907 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
4908 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
4909 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
4913 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
4914 rt2x00dev->chip.rf);
4919 usleep_range(min_sleep, min_sleep * 2);
4921 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4922 if (rt2x00dev->rf_channel <= 14) {
4923 switch (rt2x00dev->default_ant.tx_chain_num) {
4925 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4928 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4932 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4936 switch (rt2x00dev->default_ant.tx_chain_num) {
4938 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4941 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4945 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4949 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4951 if (rt2x00_rt(rt2x00dev, RT6352)) {
4952 if (rt2x00dev->default_ant.rx_chain_num == 1) {
4953 rt2800_bbp_write(rt2x00dev, 91, 0x07);
4954 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
4955 rt2800_bbp_write(rt2x00dev, 195, 128);
4956 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
4957 rt2800_bbp_write(rt2x00dev, 195, 170);
4958 rt2800_bbp_write(rt2x00dev, 196, 0x12);
4959 rt2800_bbp_write(rt2x00dev, 195, 171);
4960 rt2800_bbp_write(rt2x00dev, 196, 0x10);
4962 rt2800_bbp_write(rt2x00dev, 91, 0x06);
4963 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
4964 rt2800_bbp_write(rt2x00dev, 195, 128);
4965 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
4966 rt2800_bbp_write(rt2x00dev, 195, 170);
4967 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4968 rt2800_bbp_write(rt2x00dev, 195, 171);
4969 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4972 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4973 rt2800_bbp_write(rt2x00dev, 75, 0x68);
4974 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
4975 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
4976 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
4977 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
4980 /* On 11A, We should delay and wait RF/BBP to be stable
4981 * and the appropriate time should be 1000 micro seconds
4982 * 2005/06/05 - On 11G, we also need this delay time.
4983 * Otherwise it's difficult to pass the WHQL.
4985 usleep_range(1000, 1500);
4988 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4990 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4991 struct rt2x00lib_conf *libconf)
4995 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
4996 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
4997 libconf->conf->short_frame_max_tx_count);
4998 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
4999 libconf->conf->long_frame_max_tx_count);
5000 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5003 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5004 struct rt2x00lib_conf *libconf)
5006 enum dev_state state =
5007 (libconf->conf->flags & IEEE80211_CONF_PS) ?
5008 STATE_SLEEP : STATE_AWAKE;
5011 if (state == STATE_SLEEP) {
5012 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5014 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5015 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5016 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5017 libconf->conf->listen_interval - 1);
5018 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5019 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5021 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5023 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5024 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5025 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5026 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5027 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5029 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5033 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5034 struct rt2x00lib_conf *libconf,
5035 const unsigned int flags)
5037 /* Always recalculate LNA gain before changing configuration */
5038 rt2800_config_lna_gain(rt2x00dev, libconf);
5040 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5041 rt2800_config_channel(rt2x00dev, libconf->conf,
5042 &libconf->rf, &libconf->channel);
5043 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5044 libconf->conf->power_level);
5046 if (flags & IEEE80211_CONF_CHANGE_POWER)
5047 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5048 libconf->conf->power_level);
5049 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5050 rt2800_config_retry_limit(rt2x00dev, libconf);
5051 if (flags & IEEE80211_CONF_CHANGE_PS)
5052 rt2800_config_ps(rt2x00dev, libconf);
5054 EXPORT_SYMBOL_GPL(rt2800_config);
5059 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5064 * Update FCS error count from register.
5066 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5067 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5069 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5071 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5075 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5076 if (rt2x00_rt(rt2x00dev, RT3070) ||
5077 rt2x00_rt(rt2x00dev, RT3071) ||
5078 rt2x00_rt(rt2x00dev, RT3090) ||
5079 rt2x00_rt(rt2x00dev, RT3290) ||
5080 rt2x00_rt(rt2x00dev, RT3390) ||
5081 rt2x00_rt(rt2x00dev, RT3572) ||
5082 rt2x00_rt(rt2x00dev, RT3593) ||
5083 rt2x00_rt(rt2x00dev, RT5390) ||
5084 rt2x00_rt(rt2x00dev, RT5392) ||
5085 rt2x00_rt(rt2x00dev, RT5592) ||
5086 rt2x00_rt(rt2x00dev, RT6352))
5087 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5089 vgc = 0x2e + rt2x00dev->lna_gain;
5090 } else { /* 5GHZ band */
5091 if (rt2x00_rt(rt2x00dev, RT3593))
5092 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5093 else if (rt2x00_rt(rt2x00dev, RT5592))
5094 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5096 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5097 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5099 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5106 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5107 struct link_qual *qual, u8 vgc_level)
5109 if (qual->vgc_level != vgc_level) {
5110 if (rt2x00_rt(rt2x00dev, RT3572) ||
5111 rt2x00_rt(rt2x00dev, RT3593)) {
5112 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5114 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5115 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5116 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5118 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5121 qual->vgc_level = vgc_level;
5122 qual->vgc_level_reg = vgc_level;
5126 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5128 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5130 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5132 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5137 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5140 /* When RSSI is better than a certain threshold, increase VGC
5141 * with a chip specific value in order to improve the balance
5142 * between sensibility and noise isolation.
5145 vgc = rt2800_get_default_vgc(rt2x00dev);
5147 switch (rt2x00dev->chip.rt) {
5150 if (qual->rssi > -65) {
5151 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5159 if (qual->rssi > -65)
5164 if (qual->rssi > -80)
5169 rt2800_set_vgc(rt2x00dev, qual, vgc);
5171 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5174 * Initialization functions.
5176 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5178 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5184 rt2800_disable_wpdma(rt2x00dev);
5186 ret = rt2800_drv_init_registers(rt2x00dev);
5190 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5191 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5193 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5195 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5196 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5197 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
5198 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
5199 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
5200 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
5201 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5202 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5204 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5206 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5207 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5208 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5209 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5211 if (rt2x00_rt(rt2x00dev, RT3290)) {
5212 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5213 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5214 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1);
5215 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5218 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5219 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5220 rt2x00_set_field32(®, LDO0_EN, 1);
5221 rt2x00_set_field32(®, LDO_BGSEL, 3);
5222 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5225 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5226 rt2x00_set_field32(®, OSC_ROSC_EN, 1);
5227 rt2x00_set_field32(®, OSC_CAL_REQ, 1);
5228 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27);
5229 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5231 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5232 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e);
5233 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5235 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5236 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00);
5237 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17);
5238 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93);
5239 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f);
5240 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5242 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5243 rt2x00_set_field32(®, PLL_CONTROL, 1);
5244 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5247 if (rt2x00_rt(rt2x00dev, RT3071) ||
5248 rt2x00_rt(rt2x00dev, RT3090) ||
5249 rt2x00_rt(rt2x00dev, RT3290) ||
5250 rt2x00_rt(rt2x00dev, RT3390)) {
5252 if (rt2x00_rt(rt2x00dev, RT3290))
5253 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5256 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5259 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5260 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5261 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5262 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5263 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5264 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5265 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5268 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5271 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5273 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5274 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5276 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5277 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5278 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5280 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5281 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5283 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5284 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5285 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5286 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5287 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5288 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5289 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5290 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5291 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5292 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5293 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5294 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5295 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5296 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5297 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5298 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5299 if (rt2x00_get_field16(eeprom,
5300 EEPROM_NIC_CONF1_DAC_TEST))
5301 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5304 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5307 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5310 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5311 rt2x00_rt(rt2x00dev, RT5392) ||
5312 rt2x00_rt(rt2x00dev, RT6352)) {
5313 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5314 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5315 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5316 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5317 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5318 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5319 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5320 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5321 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5322 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5323 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5324 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
5325 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5326 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5327 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5328 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
5329 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5330 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5331 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5332 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5333 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5335 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5337 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5338 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5339 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5341 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5342 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5345 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5346 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5347 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
5348 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5349 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
5350 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
5351 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5352 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
5353 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
5354 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5356 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5357 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5358 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5359 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5360 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5362 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5363 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5364 if (rt2x00_is_usb(rt2x00dev)) {
5365 drv_data->max_psdu = 3;
5366 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5367 rt2x00_rt(rt2x00dev, RT2883) ||
5368 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5369 drv_data->max_psdu = 2;
5371 drv_data->max_psdu = 1;
5373 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5374 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10);
5375 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10);
5376 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5378 reg = rt2800_register_read(rt2x00dev, LED_CFG);
5379 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
5380 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
5381 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
5382 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
5383 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
5384 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
5385 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
5386 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5388 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5390 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5391 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5392 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5393 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5394 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5395 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
5396 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5397 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5399 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5400 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
5401 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5402 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5403 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
5404 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5405 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5406 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5407 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5409 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5410 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
5411 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
5412 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5413 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5414 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5415 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5416 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5417 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5418 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5419 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
5420 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5422 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5423 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
5424 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5425 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5426 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5427 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5428 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5429 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5430 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5431 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5432 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
5433 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5435 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5436 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5437 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1);
5438 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5439 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5440 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5441 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5442 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5443 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5444 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5445 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
5446 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5448 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5449 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5450 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1);
5451 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5452 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5453 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5454 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5455 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5456 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5457 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5458 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
5459 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5461 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5462 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5463 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1);
5464 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5465 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5466 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5467 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5468 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5469 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5470 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5471 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
5472 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5474 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
5475 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5476 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1);
5477 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5478 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5479 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5480 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5481 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5482 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5483 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5484 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
5485 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5487 if (rt2x00_is_usb(rt2x00dev)) {
5488 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5490 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
5491 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5492 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5493 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5494 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5495 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5496 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5497 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5498 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5499 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5500 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5504 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5505 * although it is reserved.
5507 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
5508 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5509 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5510 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5511 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5512 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5513 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5514 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5515 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5516 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5517 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5518 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5520 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5521 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
5523 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
5524 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
5525 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
5526 IEEE80211_MAX_RTS_THRESHOLD);
5527 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1);
5528 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5530 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5533 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5534 * time should be set to 16. However, the original Ralink driver uses
5535 * 16 for both and indeed using a value of 10 for CCK SIFS results in
5536 * connection problems with 11g + CTS protection. Hence, use the same
5537 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5539 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
5540 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5541 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
5542 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5543 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
5544 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5545 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5547 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5550 * ASIC will keep garbage value after boot, clear encryption keys.
5552 for (i = 0; i < 4; i++)
5553 rt2800_register_write(rt2x00dev,
5554 SHARED_KEY_MODE_ENTRY(i), 0);
5556 for (i = 0; i < 256; i++) {
5557 rt2800_config_wcid(rt2x00dev, NULL, i);
5558 rt2800_delete_wcid_attr(rt2x00dev, i);
5559 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5565 for (i = 0; i < 8; i++)
5566 rt2800_clear_beacon_register(rt2x00dev, i);
5568 if (rt2x00_is_usb(rt2x00dev)) {
5569 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5570 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
5571 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5572 } else if (rt2x00_is_pcie(rt2x00dev)) {
5573 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5574 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
5575 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5576 } else if (rt2x00_is_soc(rt2x00dev)) {
5577 struct clk *clk = clk_get_sys("bus", NULL);
5581 clk = clk_get_sys("cpu", NULL);
5586 rate = clk_get_rate(clk) / 3000000;
5590 rate = clk_get_rate(clk) / 1000000;
5594 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5595 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate);
5596 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5599 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
5600 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
5601 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
5602 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
5603 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
5604 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
5605 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
5606 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
5607 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
5608 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5610 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
5611 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
5612 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
5613 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
5614 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
5615 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
5616 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
5617 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
5618 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
5619 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5621 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
5622 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5623 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5624 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5625 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5626 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5627 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5628 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5629 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5630 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5632 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
5633 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
5634 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
5635 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
5636 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
5637 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5640 * Do not force the BA window size, we use the TXWI to set it
5642 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
5643 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5644 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5645 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5648 * We must clear the error counters.
5649 * These registers are cleared on read,
5650 * so we may pass a useless variable to store the value.
5652 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5653 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
5654 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
5655 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
5656 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
5657 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
5660 * Setup leadtime for pre tbtt interrupt to 6ms
5662 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
5663 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5664 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5667 * Set up channel statistics timer
5669 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
5670 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1);
5671 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1);
5672 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1);
5673 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1);
5674 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1);
5675 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5680 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5685 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5686 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
5687 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5690 udelay(REGISTER_BUSY_DELAY);
5693 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5697 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5703 * BBP was enabled after firmware was loaded,
5704 * but we need to reactivate it now.
5706 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5707 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5710 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5711 value = rt2800_bbp_read(rt2x00dev, 0);
5712 if ((value != 0xff) && (value != 0x00))
5714 udelay(REGISTER_BUSY_DELAY);
5717 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5721 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5725 value = rt2800_bbp_read(rt2x00dev, 4);
5726 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5727 rt2800_bbp_write(rt2x00dev, 4, value);
5730 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5732 rt2800_bbp_write(rt2x00dev, 142, 1);
5733 rt2800_bbp_write(rt2x00dev, 143, 57);
5736 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5738 static const u8 glrt_table[] = {
5739 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5740 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5741 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5742 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5743 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5744 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5746 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5747 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5751 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5752 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5753 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5757 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5759 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5760 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5761 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5762 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5763 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5764 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5765 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5766 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5767 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5768 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5769 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5770 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5771 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5772 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5773 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5774 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5777 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5782 value = rt2800_bbp_read(rt2x00dev, 138);
5783 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
5784 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5786 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5788 rt2800_bbp_write(rt2x00dev, 138, value);
5791 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5793 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5795 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5796 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5798 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5799 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5801 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5803 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5804 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5806 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5808 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5810 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5812 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5814 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5816 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5818 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5820 rt2800_bbp_write(rt2x00dev, 105, 0x01);
5822 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5825 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5827 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5828 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5830 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5831 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5832 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5834 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5835 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5838 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5840 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5842 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5844 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5846 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5847 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5849 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5851 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5853 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5855 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5857 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5859 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5861 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5864 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5866 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5867 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5869 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5870 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5872 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5874 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5875 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5876 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5878 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5880 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5882 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5884 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5886 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5888 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5890 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5891 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5892 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5893 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5895 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5897 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5899 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5901 if (rt2x00_rt(rt2x00dev, RT3071) ||
5902 rt2x00_rt(rt2x00dev, RT3090))
5903 rt2800_disable_unused_dac_adc(rt2x00dev);
5906 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5910 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5912 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5914 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5915 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5917 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5919 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5920 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5921 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5922 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5924 rt2800_bbp_write(rt2x00dev, 77, 0x58);
5926 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5928 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5929 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5930 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5931 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5933 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5935 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5937 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5939 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5941 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5943 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5945 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5947 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5949 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5951 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5953 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5955 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5956 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5957 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5958 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5959 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5960 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5961 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5962 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5963 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5964 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5966 value = rt2800_bbp_read(rt2x00dev, 47);
5967 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5968 rt2800_bbp_write(rt2x00dev, 47, value);
5970 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5971 value = rt2800_bbp_read(rt2x00dev, 3);
5972 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5973 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5974 rt2800_bbp_write(rt2x00dev, 3, value);
5977 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5979 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5980 rt2800_bbp_write(rt2x00dev, 4, 0x50);
5982 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5984 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5986 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5987 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5989 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5991 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5992 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5993 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5994 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5996 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5998 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6000 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6001 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6002 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6004 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6006 if (rt2x00_rt(rt2x00dev, RT5350)) {
6007 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6008 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6010 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6011 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6014 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6016 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6018 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6020 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6022 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6024 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6026 if (rt2x00_rt(rt2x00dev, RT5350)) {
6027 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6028 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6030 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6031 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6034 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6036 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6038 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6039 /* Set ITxBF timeout to 0x9c40=1000msec */
6040 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6041 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6042 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6043 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6044 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6045 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6046 /* Reprogram the inband interface to put right values in RXWI */
6047 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6048 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6049 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6050 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6051 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6052 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6053 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6054 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6056 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6058 if (rt2x00_rt(rt2x00dev, RT5350)) {
6059 /* Antenna Software OFDM */
6060 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6061 /* Antenna Software CCK */
6062 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6063 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6064 /* Clear previously selected antenna */
6065 rt2800_bbp_write(rt2x00dev, 154, 0);
6069 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6071 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6072 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6074 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6075 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6077 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6079 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6080 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6081 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6083 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6085 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6087 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6089 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6091 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6093 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6095 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6096 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6098 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6100 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6102 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6104 rt2800_disable_unused_dac_adc(rt2x00dev);
6107 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6109 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6111 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6112 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6114 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6115 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6117 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6119 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6120 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6121 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6123 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6125 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6127 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6129 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6131 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6133 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6135 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6137 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6139 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6141 rt2800_disable_unused_dac_adc(rt2x00dev);
6144 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6146 rt2800_init_bbp_early(rt2x00dev);
6148 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6149 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6150 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6151 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6153 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6155 /* Enable DC filter */
6156 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6157 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6160 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6166 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6168 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6170 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6171 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6173 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6175 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6176 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6177 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6178 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6180 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6182 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6184 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6185 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6186 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6188 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6190 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6192 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6194 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6196 if (rt2x00_rt(rt2x00dev, RT5392))
6197 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6199 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6201 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6203 if (rt2x00_rt(rt2x00dev, RT5392)) {
6204 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6205 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6208 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6210 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6212 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6214 if (rt2x00_rt(rt2x00dev, RT5390))
6215 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6216 else if (rt2x00_rt(rt2x00dev, RT5392))
6217 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6221 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6223 if (rt2x00_rt(rt2x00dev, RT5392)) {
6224 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6225 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6228 rt2800_disable_unused_dac_adc(rt2x00dev);
6230 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6231 div_mode = rt2x00_get_field16(eeprom,
6232 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6233 ant = (div_mode == 3) ? 1 : 0;
6235 /* check if this is a Bluetooth combo card */
6236 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6239 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6240 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
6241 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0);
6242 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0);
6243 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0);
6245 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1);
6247 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1);
6248 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6251 /* These chips have hardware RX antenna diversity */
6252 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6253 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6254 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6255 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6256 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6259 value = rt2800_bbp_read(rt2x00dev, 152);
6261 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6263 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6264 rt2800_bbp_write(rt2x00dev, 152, value);
6266 rt2800_init_freq_calibration(rt2x00dev);
6269 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6275 rt2800_init_bbp_early(rt2x00dev);
6277 value = rt2800_bbp_read(rt2x00dev, 105);
6278 rt2x00_set_field8(&value, BBP105_MLD,
6279 rt2x00dev->default_ant.rx_chain_num == 2);
6280 rt2800_bbp_write(rt2x00dev, 105, value);
6282 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6284 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6285 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6286 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6287 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6288 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6289 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6290 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6291 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6292 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6293 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6294 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6295 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6296 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6297 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6298 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6299 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6300 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6301 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6302 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6303 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6304 /* FIXME BBP105 owerwrite */
6305 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6306 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6307 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6308 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6309 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6310 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6312 /* Initialize GLRT (Generalized Likehood Radio Test) */
6313 rt2800_init_bbp_5592_glrt(rt2x00dev);
6315 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6317 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6318 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6319 ant = (div_mode == 3) ? 1 : 0;
6320 value = rt2800_bbp_read(rt2x00dev, 152);
6323 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6325 /* Auxiliary antenna */
6326 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6328 rt2800_bbp_write(rt2x00dev, 152, value);
6330 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6331 value = rt2800_bbp_read(rt2x00dev, 254);
6332 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6333 rt2800_bbp_write(rt2x00dev, 254, value);
6336 rt2800_init_freq_calibration(rt2x00dev);
6338 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6339 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6340 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6343 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6344 const u8 reg, const u8 value)
6346 rt2800_bbp_write(rt2x00dev, 195, reg);
6347 rt2800_bbp_write(rt2x00dev, 196, value);
6350 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6351 const u8 reg, const u8 value)
6353 rt2800_bbp_write(rt2x00dev, 158, reg);
6354 rt2800_bbp_write(rt2x00dev, 159, value);
6357 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6359 rt2800_bbp_write(rt2x00dev, 158, reg);
6360 return rt2800_bbp_read(rt2x00dev, 159);
6363 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6367 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6368 bbp = rt2800_bbp_read(rt2x00dev, 105);
6369 rt2x00_set_field8(&bbp, BBP105_MLD,
6370 rt2x00dev->default_ant.rx_chain_num == 2);
6371 rt2800_bbp_write(rt2x00dev, 105, bbp);
6373 /* Avoid data loss and CRC errors */
6374 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6376 /* Fix I/Q swap issue */
6377 bbp = rt2800_bbp_read(rt2x00dev, 1);
6379 rt2800_bbp_write(rt2x00dev, 1, bbp);
6381 /* BBP for G band */
6382 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6383 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6384 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6385 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6386 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6387 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6388 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6389 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6390 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6391 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6392 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6393 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6394 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6395 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6396 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6397 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6398 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6399 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6400 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6401 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6402 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6403 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6404 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6405 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6406 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6407 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6408 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6409 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6410 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6411 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6412 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6413 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6414 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6415 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6416 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6417 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6418 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6419 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6420 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6421 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6422 rt2800_bbp_write(rt2x00dev, 96, 0x00);
6423 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6424 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6425 /* FIXME BBP105 owerwrite */
6426 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6427 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6428 rt2800_bbp_write(rt2x00dev, 109, 0x00);
6429 rt2800_bbp_write(rt2x00dev, 134, 0x10);
6430 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6431 rt2800_bbp_write(rt2x00dev, 137, 0x04);
6432 rt2800_bbp_write(rt2x00dev, 142, 0x30);
6433 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6434 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6435 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6436 rt2800_bbp_write(rt2x00dev, 162, 0x77);
6437 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6438 rt2800_bbp_write(rt2x00dev, 164, 0x00);
6439 rt2800_bbp_write(rt2x00dev, 165, 0x00);
6440 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6441 rt2800_bbp_write(rt2x00dev, 187, 0x00);
6442 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6443 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6444 rt2800_bbp_write(rt2x00dev, 187, 0x01);
6445 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6446 rt2800_bbp_write(rt2x00dev, 189, 0x00);
6448 rt2800_bbp_write(rt2x00dev, 91, 0x06);
6449 rt2800_bbp_write(rt2x00dev, 92, 0x04);
6450 rt2800_bbp_write(rt2x00dev, 93, 0x54);
6451 rt2800_bbp_write(rt2x00dev, 99, 0x50);
6452 rt2800_bbp_write(rt2x00dev, 148, 0x84);
6453 rt2800_bbp_write(rt2x00dev, 167, 0x80);
6454 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6455 rt2800_bbp_write(rt2x00dev, 106, 0x13);
6457 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6458 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6459 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6460 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6461 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6462 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6463 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6464 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6465 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6466 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6467 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6468 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6469 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6470 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6471 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6472 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6473 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6474 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6475 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6476 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6477 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6478 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6479 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6480 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6481 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6482 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6483 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6484 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6485 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6486 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6487 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6488 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6489 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6490 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6491 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6492 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6493 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6494 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6495 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6496 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6497 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6498 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6499 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6500 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6501 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6502 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6503 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6504 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6505 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6506 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6507 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6508 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6509 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6510 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6511 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6512 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6513 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6514 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6515 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6516 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6517 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6518 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6519 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6520 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6521 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6522 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6523 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6524 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6525 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6526 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6527 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6528 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6529 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6530 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6531 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6532 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6533 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6534 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6535 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6536 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6537 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6538 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6539 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6540 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6542 /* BBP for G band DCOC function */
6543 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6544 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6545 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6546 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6547 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6548 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6549 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6550 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6551 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6552 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6553 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6554 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6555 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6556 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6557 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6558 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6559 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6560 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6561 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6562 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6564 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6567 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
6574 if (rt2800_is_305x_soc(rt2x00dev))
6575 rt2800_init_bbp_305x_soc(rt2x00dev);
6577 switch (rt2x00dev->chip.rt) {
6581 rt2800_init_bbp_28xx(rt2x00dev);
6586 rt2800_init_bbp_30xx(rt2x00dev);
6589 rt2800_init_bbp_3290(rt2x00dev);
6593 rt2800_init_bbp_3352(rt2x00dev);
6596 rt2800_init_bbp_3390(rt2x00dev);
6599 rt2800_init_bbp_3572(rt2x00dev);
6602 rt2800_init_bbp_3593(rt2x00dev);
6606 rt2800_init_bbp_53xx(rt2x00dev);
6609 rt2800_init_bbp_5592(rt2x00dev);
6612 rt2800_init_bbp_6352(rt2x00dev);
6616 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
6617 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
6618 EEPROM_BBP_START, i);
6620 if (eeprom != 0xffff && eeprom != 0x0000) {
6621 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6622 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6623 rt2800_bbp_write(rt2x00dev, reg_id, value);
6628 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6632 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
6633 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
6634 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6637 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6646 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
6648 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6650 bbp = rt2800_bbp_read(rt2x00dev, 4);
6651 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6652 rt2800_bbp_write(rt2x00dev, 4, bbp);
6654 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
6655 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6656 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6659 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6660 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6663 * Set power & frequency of passband test tone
6665 rt2800_bbp_write(rt2x00dev, 24, 0);
6667 for (i = 0; i < 100; i++) {
6668 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6671 passband = rt2800_bbp_read(rt2x00dev, 55);
6677 * Set power & frequency of stopband test tone
6679 rt2800_bbp_write(rt2x00dev, 24, 0x06);
6681 for (i = 0; i < 100; i++) {
6682 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6685 stopband = rt2800_bbp_read(rt2x00dev, 55);
6687 if ((passband - stopband) <= filter_target) {
6689 overtuned += ((passband - stopband) == filter_target);
6693 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6696 rfcsr24 -= !!overtuned;
6698 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6702 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6703 const unsigned int rf_reg)
6707 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
6708 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6709 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6711 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6712 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6715 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6717 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6723 * TODO: sync filter_tgt values with vendor driver
6725 if (rt2x00_rt(rt2x00dev, RT3070)) {
6726 filter_tgt_bw20 = 0x16;
6727 filter_tgt_bw40 = 0x19;
6729 filter_tgt_bw20 = 0x13;
6730 filter_tgt_bw40 = 0x15;
6733 drv_data->calibration_bw20 =
6734 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6735 drv_data->calibration_bw40 =
6736 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6739 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6741 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
6742 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
6745 * Set back to initial state
6747 rt2800_bbp_write(rt2x00dev, 24, 0);
6749 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6750 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6751 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6754 * Set BBP back to BW20
6756 bbp = rt2800_bbp_read(rt2x00dev, 4);
6757 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6758 rt2800_bbp_write(rt2x00dev, 4, bbp);
6761 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6763 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6764 u8 min_gain, rfcsr, bbp;
6767 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
6769 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6770 if (rt2x00_rt(rt2x00dev, RT3070) ||
6771 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6772 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6773 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
6774 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
6775 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6778 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6779 if (drv_data->txmixer_gain_24g >= min_gain) {
6780 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6781 drv_data->txmixer_gain_24g);
6784 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6786 if (rt2x00_rt(rt2x00dev, RT3090)) {
6787 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6788 bbp = rt2800_bbp_read(rt2x00dev, 138);
6789 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6790 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6791 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6792 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6793 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6794 rt2800_bbp_write(rt2x00dev, 138, bbp);
6797 if (rt2x00_rt(rt2x00dev, RT3070)) {
6798 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
6799 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6800 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6802 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6803 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6804 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6805 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6806 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6807 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6808 rt2x00_rt(rt2x00dev, RT3090) ||
6809 rt2x00_rt(rt2x00dev, RT3390)) {
6810 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6811 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6812 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6813 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6814 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6815 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6816 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6818 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
6819 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6820 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6822 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
6823 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6824 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6826 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
6827 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6828 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6832 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6834 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6838 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
6839 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6840 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6842 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
6843 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6844 RFCSR17_TXMIXER_GAIN);
6845 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6846 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6848 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
6849 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6850 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6852 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
6853 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6854 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6856 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6857 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6858 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6859 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6861 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
6862 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6863 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6865 /* TODO: enable stream mode */
6868 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
6873 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6874 reg = rt2800_bbp_read(rt2x00dev, 138);
6875 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6876 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6877 rt2x00_set_field8(®, BBP138_RX_ADC1, 0);
6878 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6879 rt2x00_set_field8(®, BBP138_TX_DAC1, 1);
6880 rt2800_bbp_write(rt2x00dev, 138, reg);
6882 reg = rt2800_rfcsr_read(rt2x00dev, 38);
6883 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0);
6884 rt2800_rfcsr_write(rt2x00dev, 38, reg);
6886 reg = rt2800_rfcsr_read(rt2x00dev, 39);
6887 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0);
6888 rt2800_rfcsr_write(rt2x00dev, 39, reg);
6890 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6892 reg = rt2800_rfcsr_read(rt2x00dev, 30);
6893 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2);
6894 rt2800_rfcsr_write(rt2x00dev, 30, reg);
6897 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6899 rt2800_rf_init_calibration(rt2x00dev, 30);
6901 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6902 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6903 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6904 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6905 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6906 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6907 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6908 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6909 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6910 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6911 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6912 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6913 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6914 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6915 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6916 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6917 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6918 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6919 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6920 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6921 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6922 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6923 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6924 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6925 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6926 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6927 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6928 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6929 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6930 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6931 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6932 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6935 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6941 /* XXX vendor driver do this only for 3070 */
6942 rt2800_rf_init_calibration(rt2x00dev, 30);
6944 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6945 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6946 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6947 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6948 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6949 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6950 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6951 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6952 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6953 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6954 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6955 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6956 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6957 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6958 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6959 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6960 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6961 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6962 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6964 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6965 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6966 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6967 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6968 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6969 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6970 rt2x00_rt(rt2x00dev, RT3090)) {
6971 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6973 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
6974 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6975 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6977 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6978 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6979 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6980 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6981 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6982 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6983 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6985 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6987 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6989 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
6990 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
6991 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6994 rt2800_rx_filter_calibration(rt2x00dev);
6996 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6997 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6998 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6999 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7001 rt2800_led_open_drain_enable(rt2x00dev);
7002 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7005 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7009 rt2800_rf_init_calibration(rt2x00dev, 2);
7011 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7012 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7013 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7014 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7015 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7016 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7017 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7018 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7019 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7020 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7021 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7022 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7023 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7024 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7025 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7026 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7027 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7028 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7029 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7030 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7031 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7032 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7033 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7034 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7035 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7036 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7037 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7038 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7039 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7040 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7041 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7042 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7043 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7044 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7045 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7046 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7047 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7048 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7049 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7050 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7051 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7052 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7053 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7054 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7055 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7056 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7058 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7059 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7060 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7062 rt2800_led_open_drain_enable(rt2x00dev);
7063 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7066 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7068 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7069 &rt2x00dev->cap_flags);
7070 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7071 &rt2x00dev->cap_flags);
7074 rt2800_rf_init_calibration(rt2x00dev, 30);
7076 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7077 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7078 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7079 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7080 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7081 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7082 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7083 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7084 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7085 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7086 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7087 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7088 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7089 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7090 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7091 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7092 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7093 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7094 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7095 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7096 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7097 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7098 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7099 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7100 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7101 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7102 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7103 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7104 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7105 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7106 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7107 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7108 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7111 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7113 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7114 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7115 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7116 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7117 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7118 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7119 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7120 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7123 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7124 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7126 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7129 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7130 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7132 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7133 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7134 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7135 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7136 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7137 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7138 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7139 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7142 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7144 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7145 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7146 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7147 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7148 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7149 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7150 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7151 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7152 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7153 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7154 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7155 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7156 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7157 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7158 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7160 rt2800_rx_filter_calibration(rt2x00dev);
7161 rt2800_led_open_drain_enable(rt2x00dev);
7162 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7165 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7169 rt2800_rf_init_calibration(rt2x00dev, 30);
7171 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7172 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7173 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7174 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7175 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7176 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7177 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7178 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7179 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7180 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7181 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7182 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7183 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7184 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7185 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7186 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7187 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7188 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7189 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7190 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7191 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7192 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7193 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7194 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7195 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7196 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7197 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7198 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7199 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7200 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7201 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7202 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7204 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7205 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
7206 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7208 rt2800_rx_filter_calibration(rt2x00dev);
7210 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7211 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7213 rt2800_led_open_drain_enable(rt2x00dev);
7214 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7217 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7222 rt2800_rf_init_calibration(rt2x00dev, 30);
7224 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7225 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7226 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7227 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7228 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7229 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7230 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7231 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7232 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7233 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7234 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7235 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7236 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7237 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7238 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7239 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7240 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7241 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7242 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7243 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7244 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7245 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7246 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7247 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7248 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7249 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7250 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7251 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7252 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7253 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7254 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7256 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7257 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7258 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7260 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7261 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7262 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7263 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7265 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7266 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7267 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7268 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7270 rt2800_rx_filter_calibration(rt2x00dev);
7271 rt2800_led_open_drain_enable(rt2x00dev);
7272 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7275 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7278 bool txbf_enabled = false; /* FIXME */
7280 bbp = rt2800_bbp_read(rt2x00dev, 105);
7281 if (rt2x00dev->default_ant.rx_chain_num == 1)
7282 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7284 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7285 rt2800_bbp_write(rt2x00dev, 105, bbp);
7287 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7289 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7290 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7291 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7292 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7293 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7294 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7295 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7296 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7299 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7301 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7304 rt2800_bbp_write(rt2x00dev, 142, 6);
7305 rt2800_bbp_write(rt2x00dev, 143, 160);
7306 rt2800_bbp_write(rt2x00dev, 142, 7);
7307 rt2800_bbp_write(rt2x00dev, 143, 161);
7308 rt2800_bbp_write(rt2x00dev, 142, 8);
7309 rt2800_bbp_write(rt2x00dev, 143, 162);
7311 /* ADC/DAC control */
7312 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7314 /* RX AGC energy lower bound in log2 */
7315 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7317 /* FIXME: BBP 105 owerwrite? */
7318 rt2800_bbp_write(rt2x00dev, 105, 0x04);
7322 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7324 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7328 /* Disable GPIO #4 and #7 function for LAN PE control */
7329 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7330 rt2x00_set_field32(®, GPIO_SWITCH_4, 0);
7331 rt2x00_set_field32(®, GPIO_SWITCH_7, 0);
7332 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7334 /* Initialize default register values */
7335 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7336 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7337 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7338 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7339 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7340 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7341 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7342 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7343 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7344 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7345 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7346 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7347 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7348 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7349 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7350 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7351 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7352 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7353 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7354 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7355 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7356 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7357 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7358 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7359 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7360 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7361 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7362 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7363 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7364 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7365 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7366 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7368 /* Initiate calibration */
7369 /* TODO: use rt2800_rf_init_calibration ? */
7370 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7371 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7372 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7374 rt2800_freq_cal_mode1(rt2x00dev);
7376 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7377 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7378 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7380 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7381 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7382 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7383 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7384 usleep_range(1000, 1500);
7385 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7386 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7387 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7389 /* Set initial values for RX filter calibration */
7390 drv_data->calibration_bw20 = 0x1f;
7391 drv_data->calibration_bw40 = 0x2f;
7393 /* Save BBP 25 & 26 values for later use in channel switching */
7394 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7395 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7397 rt2800_led_open_drain_enable(rt2x00dev);
7398 rt2800_normal_mode_setup_3593(rt2x00dev);
7400 rt3593_post_bbp_init(rt2x00dev);
7402 /* TODO: enable stream mode support */
7405 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7407 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7408 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7409 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7410 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7411 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7412 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7413 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7414 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7415 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7416 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7417 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7418 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7419 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7420 if (rt2800_clk_is_20mhz(rt2x00dev))
7421 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7423 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7424 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7425 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7426 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7427 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7428 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7429 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7430 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7431 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7432 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7433 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7434 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7435 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7436 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7437 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7438 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7439 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7440 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7441 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7442 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7443 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7444 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7445 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7446 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7447 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7448 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7449 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7450 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7451 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7452 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7453 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7454 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7455 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7456 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7457 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7458 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7459 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7460 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7461 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7462 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7463 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7464 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7465 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7466 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7467 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7468 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7469 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7470 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7471 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7472 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7475 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7477 rt2800_rf_init_calibration(rt2x00dev, 2);
7479 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7480 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7481 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7482 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7483 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7484 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7486 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7487 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7488 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7489 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7490 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7491 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7492 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7493 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7494 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7495 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7496 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7498 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7499 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7500 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7501 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7502 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7503 if (rt2x00_is_usb(rt2x00dev) &&
7504 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7505 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7507 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7508 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7509 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7510 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7511 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7513 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7514 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7515 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7516 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7517 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7518 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7519 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7520 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7521 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7522 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7524 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7525 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7526 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7527 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7528 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7529 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7530 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7531 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7533 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7534 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7535 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7536 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7538 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7539 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7540 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7542 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7543 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7544 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
7545 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7546 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7548 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
7549 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7550 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7551 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
7553 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7554 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7555 if (rt2x00_is_usb(rt2x00dev))
7556 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7558 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7560 if (rt2x00_is_usb(rt2x00dev))
7561 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7563 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7565 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7566 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7568 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7570 rt2800_led_open_drain_enable(rt2x00dev);
7573 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7575 rt2800_rf_init_calibration(rt2x00dev, 2);
7577 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
7578 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7579 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7580 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7581 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7582 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7583 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7584 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7585 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7586 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7587 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7588 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7589 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7590 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7591 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7592 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7593 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7594 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7595 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7596 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7597 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7598 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7599 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7600 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7601 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7602 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7603 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7604 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7605 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7606 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7607 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7608 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7609 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7610 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7611 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7612 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7613 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7614 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7615 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7616 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7617 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7618 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7619 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7620 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7621 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7622 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7623 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7624 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7625 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7626 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7627 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7628 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7629 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7630 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7631 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7632 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7633 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7634 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7636 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7638 rt2800_led_open_drain_enable(rt2x00dev);
7641 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7643 rt2800_rf_init_calibration(rt2x00dev, 30);
7645 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7646 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7647 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7648 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7649 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7650 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7651 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7652 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7653 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7654 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7655 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7656 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7657 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7658 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7659 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7660 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7661 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7662 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7663 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7664 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7665 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7667 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7670 rt2800_freq_cal_mode1(rt2x00dev);
7672 /* Enable DC filter */
7673 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7674 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7676 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7678 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7679 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7681 rt2800_led_open_drain_enable(rt2x00dev);
7684 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7685 bool set_bw, bool is_ht40)
7689 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7691 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7692 usleep_range(100, 200);
7695 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
7696 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7697 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7698 usleep_range(100, 200);
7701 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7703 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7704 usleep_range(100, 200);
7707 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7712 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7714 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7716 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7718 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7720 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7723 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7724 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7725 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7726 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7729 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7730 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7733 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7734 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7736 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7737 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7738 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7739 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7742 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7743 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7746 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7752 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7758 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7762 usleep_range(500, 2000);
7763 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
7764 if (bbp_val == 0x02 || cnt == 20)
7770 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
7771 cal_val = bbp_val & 0x7F;
7772 if (cal_val >= 0x40)
7778 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7781 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7782 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7784 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7785 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7786 int loop = 0, is_ht40, cnt;
7788 char cal_r32_init, cal_r32_val, cal_diff;
7789 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7790 u8 saverfb5r06, saverfb5r07;
7791 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7792 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7793 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7794 u8 saverfb5r58, saverfb5r59;
7795 u8 savebbp159r0, savebbp159r2, savebbpr23;
7796 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7798 /* Save MAC registers */
7799 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
7800 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
7802 /* save BBP registers */
7803 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
7805 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
7806 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7808 /* Save RF registers */
7809 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7810 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7811 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7812 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7813 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
7814 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7815 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7816 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7817 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7818 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
7819 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
7820 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
7822 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
7823 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
7824 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
7825 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
7826 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
7827 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
7828 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
7829 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
7830 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
7831 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
7833 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7834 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7836 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7838 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7840 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7842 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7846 usleep_range(500, 2000);
7847 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7848 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7853 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7856 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7859 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
7862 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7870 filter_target = tx_filter_target_20m;
7872 filter_target = rx_filter_target_20m;
7877 filter_target = tx_filter_target_40m;
7879 filter_target = rx_filter_target_40m;
7882 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7887 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
7889 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
7891 rt2800_rf_lp_config(rt2x00dev, btxcal);
7894 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7896 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7897 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7899 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7902 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7904 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7905 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7907 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7910 usleep_range(1000, 2000);
7912 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7914 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7916 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7918 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7920 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7922 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7925 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7927 rf_val |= tx_agc_fc;
7928 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7929 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7931 rf_val |= tx_agc_fc;
7932 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7934 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7936 rf_val |= rx_agc_fc;
7937 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7938 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7940 rf_val |= rx_agc_fc;
7941 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7944 usleep_range(500, 1000);
7946 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7948 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7950 cal_diff = cal_r32_init - cal_r32_val;
7953 cmm_agc_fc = tx_agc_fc;
7955 cmm_agc_fc = rx_agc_fc;
7957 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
7958 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
7963 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
7973 drv_data->tx_calibration_bw20 = tx_agc_fc;
7975 drv_data->tx_calibration_bw40 = tx_agc_fc;
7978 drv_data->rx_calibration_bw20 = rx_agc_fc;
7980 drv_data->rx_calibration_bw40 = rx_agc_fc;
7984 } while (loop <= 1);
7986 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
7987 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
7988 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
7989 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
7990 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
7991 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
7992 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
7993 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
7994 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
7995 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
7996 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
7997 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
7999 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8000 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8001 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8002 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8003 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8004 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8005 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8006 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8007 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8008 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8010 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8011 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8013 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8015 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8016 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8018 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8019 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8020 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8021 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8023 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8024 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8027 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8029 /* Initialize RF central register to default value */
8030 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8031 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8032 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8033 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8034 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8035 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8036 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8037 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8038 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8039 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8040 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8041 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8042 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8043 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8044 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8045 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8046 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8047 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8048 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8049 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8050 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8051 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8052 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8053 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8054 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8055 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8056 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8057 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8058 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8059 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8060 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8061 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8062 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8063 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8064 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8065 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8066 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8067 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8068 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8069 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8070 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8071 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8072 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8073 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8075 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8076 if (rt2800_clk_is_20mhz(rt2x00dev))
8077 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8079 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8080 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8081 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8082 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8083 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8084 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8085 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8086 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8087 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8088 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8089 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8090 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8091 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8092 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8093 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8094 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8095 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8097 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8098 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8099 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8101 /* Initialize RF channel register to default value */
8102 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8103 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8104 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8105 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8106 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8107 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8108 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8109 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8110 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8111 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8112 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8113 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8114 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8115 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8116 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8117 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8118 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8119 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8120 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8121 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8122 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8123 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8124 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8125 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8126 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8127 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8128 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8129 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8130 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8131 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8132 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8133 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8134 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8135 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8136 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8137 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8138 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8139 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8140 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8141 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8142 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8143 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8144 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8145 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8146 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8147 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8148 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8149 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8150 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8151 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8152 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8153 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8154 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8155 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8156 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8157 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8158 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8159 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8160 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8161 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8163 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8165 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8166 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8167 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8168 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8169 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8170 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8171 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8172 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8173 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8174 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8175 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8176 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8177 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8178 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8179 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8180 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8181 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8182 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8183 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8184 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8185 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8186 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8187 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8188 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8189 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8190 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8191 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8192 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8193 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8194 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8196 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8197 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8198 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8199 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8200 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8201 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8202 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8203 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8204 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8206 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8207 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8208 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8209 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8210 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8211 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8213 /* Initialize RF channel register for DRQFN */
8214 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8215 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8216 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8217 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8218 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8219 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8220 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8221 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8223 /* Initialize RF DC calibration register to default value */
8224 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8225 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8226 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8227 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8228 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8229 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8230 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8231 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8232 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8233 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8234 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8235 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8236 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8237 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8238 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8239 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8240 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8241 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8242 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8243 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8244 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8245 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8246 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8247 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8248 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8249 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8250 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8251 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8252 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8253 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8254 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8255 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8256 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8257 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8258 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8259 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8260 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8261 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8262 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8263 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8264 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8265 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8266 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8267 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8268 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8269 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8270 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8271 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8272 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8273 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8274 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8275 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8276 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8277 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8278 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8279 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8280 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8281 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8282 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8284 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8285 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8286 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8288 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8289 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8291 rt2800_bw_filter_calibration(rt2x00dev, true);
8292 rt2800_bw_filter_calibration(rt2x00dev, false);
8295 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8297 if (rt2800_is_305x_soc(rt2x00dev)) {
8298 rt2800_init_rfcsr_305x_soc(rt2x00dev);
8302 switch (rt2x00dev->chip.rt) {
8306 rt2800_init_rfcsr_30xx(rt2x00dev);
8309 rt2800_init_rfcsr_3290(rt2x00dev);
8312 rt2800_init_rfcsr_3352(rt2x00dev);
8315 rt2800_init_rfcsr_3390(rt2x00dev);
8318 rt2800_init_rfcsr_3572(rt2x00dev);
8321 rt2800_init_rfcsr_3593(rt2x00dev);
8324 rt2800_init_rfcsr_5350(rt2x00dev);
8327 rt2800_init_rfcsr_5390(rt2x00dev);
8330 rt2800_init_rfcsr_5392(rt2x00dev);
8333 rt2800_init_rfcsr_5592(rt2x00dev);
8336 rt2800_init_rfcsr_6352(rt2x00dev);
8341 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8347 * Initialize MAC registers.
8349 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
8350 rt2800_init_registers(rt2x00dev)))
8354 * Wait BBP/RF to wake up.
8356 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8360 * Send signal during boot time to initialize firmware.
8362 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8363 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8364 if (rt2x00_is_usb(rt2x00dev))
8365 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8366 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
8370 * Make sure BBP is up and running.
8372 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
8376 * Initialize BBP/RF registers.
8378 rt2800_init_bbp(rt2x00dev);
8379 rt2800_init_rfcsr(rt2x00dev);
8381 if (rt2x00_is_usb(rt2x00dev) &&
8382 (rt2x00_rt(rt2x00dev, RT3070) ||
8383 rt2x00_rt(rt2x00dev, RT3071) ||
8384 rt2x00_rt(rt2x00dev, RT3572))) {
8386 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8393 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8394 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
8395 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
8396 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8400 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
8401 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8402 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
8403 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8404 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8406 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8407 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
8408 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
8409 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8412 * Initialize LED control
8414 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
8415 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
8416 word & 0xff, (word >> 8) & 0xff);
8418 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
8419 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
8420 word & 0xff, (word >> 8) & 0xff);
8422 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
8423 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
8424 word & 0xff, (word >> 8) & 0xff);
8428 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8430 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8434 rt2800_disable_wpdma(rt2x00dev);
8436 /* Wait for DMA, ignore error */
8437 rt2800_wait_wpdma_ready(rt2x00dev);
8439 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8440 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
8441 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
8442 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8444 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
8446 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8451 if (rt2x00_rt(rt2x00dev, RT3290))
8452 efuse_ctrl_reg = EFUSE_CTRL_3290;
8454 efuse_ctrl_reg = EFUSE_CTRL;
8456 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
8457 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8459 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8461 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8465 u16 efuse_data0_reg;
8466 u16 efuse_data1_reg;
8467 u16 efuse_data2_reg;
8468 u16 efuse_data3_reg;
8470 if (rt2x00_rt(rt2x00dev, RT3290)) {
8471 efuse_ctrl_reg = EFUSE_CTRL_3290;
8472 efuse_data0_reg = EFUSE_DATA0_3290;
8473 efuse_data1_reg = EFUSE_DATA1_3290;
8474 efuse_data2_reg = EFUSE_DATA2_3290;
8475 efuse_data3_reg = EFUSE_DATA3_3290;
8477 efuse_ctrl_reg = EFUSE_CTRL;
8478 efuse_data0_reg = EFUSE_DATA0;
8479 efuse_data1_reg = EFUSE_DATA1;
8480 efuse_data2_reg = EFUSE_DATA2;
8481 efuse_data3_reg = EFUSE_DATA3;
8483 mutex_lock(&rt2x00dev->csr_mutex);
8485 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
8486 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
8487 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
8488 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
8489 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
8491 /* Wait until the EEPROM has been loaded */
8492 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
8493 /* Apparently the data is read from end to start */
8494 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
8495 /* The returned value is in CPU order, but eeprom is le */
8496 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
8497 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
8498 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
8499 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
8500 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
8501 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
8502 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
8504 mutex_unlock(&rt2x00dev->csr_mutex);
8507 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
8511 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8512 rt2800_efuse_read(rt2x00dev, i);
8516 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8518 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8522 if (rt2x00_rt(rt2x00dev, RT3593))
8525 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
8526 if ((word & 0x00ff) != 0x00ff)
8527 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8532 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8536 if (rt2x00_rt(rt2x00dev, RT3593))
8539 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
8540 if ((word & 0x00ff) != 0x00ff)
8541 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8546 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
8548 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8551 u8 default_lna_gain;
8557 retval = rt2800_read_eeprom(rt2x00dev);
8562 * Start validation of the data that has been read.
8564 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
8565 rt2x00lib_set_mac_address(rt2x00dev, mac);
8567 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8568 if (word == 0xffff) {
8569 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8570 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8571 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
8572 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8573 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
8574 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
8575 rt2x00_rt(rt2x00dev, RT2872)) {
8577 * There is a max of 2 RX streams for RT28x0 series
8579 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8580 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8581 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8584 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8585 if (word == 0xffff) {
8586 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8587 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8588 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8589 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8590 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8591 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8592 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8593 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8594 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8595 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8596 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8597 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8598 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8599 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8600 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
8601 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
8602 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
8605 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8606 if ((word & 0x00ff) == 0x00ff) {
8607 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
8608 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8609 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
8611 if ((word & 0xff00) == 0xff00) {
8612 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8613 LED_MODE_TXRX_ACTIVITY);
8614 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
8615 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8616 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8617 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8618 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
8619 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
8623 * During the LNA validation we are going to use
8624 * lna0 as correct value. Note that EEPROM_LNA
8625 * is never validated.
8627 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
8628 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8630 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
8631 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8632 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8633 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8634 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
8635 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
8637 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
8639 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
8640 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8641 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
8642 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8643 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8644 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8645 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8648 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
8650 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
8652 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
8653 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8654 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8655 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8656 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
8657 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
8659 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
8660 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8661 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
8662 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8663 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8664 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8665 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8668 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
8670 if (rt2x00_rt(rt2x00dev, RT3593)) {
8671 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
8672 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8673 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8674 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8676 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8677 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8678 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8680 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8686 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
8693 * Read EEPROM word for configuration.
8695 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8698 * Identify RF chipset by EEPROM value
8699 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8700 * RT53xx: defined in "EEPROM_CHIP_ID" field
8702 if (rt2x00_rt(rt2x00dev, RT3290) ||
8703 rt2x00_rt(rt2x00dev, RT5390) ||
8704 rt2x00_rt(rt2x00dev, RT5392) ||
8705 rt2x00_rt(rt2x00dev, RT6352))
8706 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
8707 else if (rt2x00_rt(rt2x00dev, RT3352))
8709 else if (rt2x00_rt(rt2x00dev, RT5350))
8712 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8740 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8745 rt2x00_set_rf(rt2x00dev, rf);
8748 * Identify default antenna configuration.
8750 rt2x00dev->default_ant.tx_chain_num =
8751 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
8752 rt2x00dev->default_ant.rx_chain_num =
8753 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
8755 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8757 if (rt2x00_rt(rt2x00dev, RT3070) ||
8758 rt2x00_rt(rt2x00dev, RT3090) ||
8759 rt2x00_rt(rt2x00dev, RT3352) ||
8760 rt2x00_rt(rt2x00dev, RT3390)) {
8761 value = rt2x00_get_field16(eeprom,
8762 EEPROM_NIC_CONF1_ANT_DIVERSITY);
8767 rt2x00dev->default_ant.tx = ANTENNA_A;
8768 rt2x00dev->default_ant.rx = ANTENNA_A;
8771 rt2x00dev->default_ant.tx = ANTENNA_A;
8772 rt2x00dev->default_ant.rx = ANTENNA_B;
8776 rt2x00dev->default_ant.tx = ANTENNA_A;
8777 rt2x00dev->default_ant.rx = ANTENNA_A;
8780 /* These chips have hardware RX antenna diversity */
8781 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
8782 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
8783 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8784 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8788 * Determine external LNA informations.
8790 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
8791 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
8792 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
8793 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
8796 * Detect if this device has an hardware controlled radio.
8798 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
8799 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
8802 * Detect if this device has Bluetooth co-existence.
8804 if (!rt2x00_rt(rt2x00dev, RT3352) &&
8805 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
8806 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8809 * Read frequency offset and RF programming sequence.
8811 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8812 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8815 * Store led settings, for correct led behaviour.
8817 #ifdef CONFIG_RT2X00_LIB_LEDS
8818 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8819 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8820 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8822 rt2x00dev->led_mcu_reg = eeprom;
8823 #endif /* CONFIG_RT2X00_LIB_LEDS */
8826 * Check if support EIRP tx power limit feature.
8828 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
8830 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8831 EIRP_MAX_TX_POWER_LIMIT)
8832 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
8835 * Detect if device uses internal or external PA
8837 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8839 if (rt2x00_rt(rt2x00dev, RT3352)) {
8840 if (rt2x00_get_field16(eeprom,
8841 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
8842 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
8843 &rt2x00dev->cap_flags);
8844 if (rt2x00_get_field16(eeprom,
8845 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
8846 __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
8847 &rt2x00dev->cap_flags);
8854 * RF value list for rt28xx
8855 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8857 static const struct rf_channel rf_vals[] = {
8858 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8859 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8860 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8861 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8862 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8863 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8864 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8865 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
8866 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
8867 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
8868 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
8869 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
8870 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
8871 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
8873 /* 802.11 UNI / HyperLan 2 */
8874 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
8875 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
8876 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
8877 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
8878 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
8879 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
8880 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
8881 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
8882 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
8883 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
8884 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
8885 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
8887 /* 802.11 HyperLan 2 */
8888 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
8889 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
8890 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
8891 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
8892 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
8893 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
8894 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
8895 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
8896 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
8897 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
8898 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
8899 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
8900 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
8901 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
8902 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
8903 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
8906 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
8907 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
8908 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
8909 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
8910 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
8911 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
8912 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
8913 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
8914 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
8915 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
8916 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
8919 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
8920 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
8921 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
8922 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
8923 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
8924 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
8925 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
8929 * RF value list for rt3xxx
8930 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
8932 static const struct rf_channel rf_vals_3x[] = {
8948 /* 802.11 UNI / HyperLan 2 */
8962 /* 802.11 HyperLan 2 */
8995 * RF value list for rt3xxx with Xtal20MHz
8996 * Supports: 2.4 GHz (all) (RF3322)
8998 static const struct rf_channel rf_vals_3x_xtal20[] = {
9008 {10, 0xEB, 2, 0x14},
9009 {11, 0xEC, 2, 0x14},
9010 {12, 0xED, 2, 0x14},
9011 {13, 0xEE, 2, 0x14},
9012 {14, 0xF0, 2, 0x18},
9015 static const struct rf_channel rf_vals_5592_xtal20[] = {
9016 /* Channel, N, K, mod, R */
9026 {10, 491, 4, 10, 3},
9027 {11, 492, 4, 10, 3},
9028 {12, 493, 4, 10, 3},
9029 {13, 494, 4, 10, 3},
9030 {14, 496, 8, 10, 3},
9031 {36, 172, 8, 12, 1},
9032 {38, 173, 0, 12, 1},
9033 {40, 173, 4, 12, 1},
9034 {42, 173, 8, 12, 1},
9035 {44, 174, 0, 12, 1},
9036 {46, 174, 4, 12, 1},
9037 {48, 174, 8, 12, 1},
9038 {50, 175, 0, 12, 1},
9039 {52, 175, 4, 12, 1},
9040 {54, 175, 8, 12, 1},
9041 {56, 176, 0, 12, 1},
9042 {58, 176, 4, 12, 1},
9043 {60, 176, 8, 12, 1},
9044 {62, 177, 0, 12, 1},
9045 {64, 177, 4, 12, 1},
9046 {100, 183, 4, 12, 1},
9047 {102, 183, 8, 12, 1},
9048 {104, 184, 0, 12, 1},
9049 {106, 184, 4, 12, 1},
9050 {108, 184, 8, 12, 1},
9051 {110, 185, 0, 12, 1},
9052 {112, 185, 4, 12, 1},
9053 {114, 185, 8, 12, 1},
9054 {116, 186, 0, 12, 1},
9055 {118, 186, 4, 12, 1},
9056 {120, 186, 8, 12, 1},
9057 {122, 187, 0, 12, 1},
9058 {124, 187, 4, 12, 1},
9059 {126, 187, 8, 12, 1},
9060 {128, 188, 0, 12, 1},
9061 {130, 188, 4, 12, 1},
9062 {132, 188, 8, 12, 1},
9063 {134, 189, 0, 12, 1},
9064 {136, 189, 4, 12, 1},
9065 {138, 189, 8, 12, 1},
9066 {140, 190, 0, 12, 1},
9067 {149, 191, 6, 12, 1},
9068 {151, 191, 10, 12, 1},
9069 {153, 192, 2, 12, 1},
9070 {155, 192, 6, 12, 1},
9071 {157, 192, 10, 12, 1},
9072 {159, 193, 2, 12, 1},
9073 {161, 193, 6, 12, 1},
9074 {165, 194, 2, 12, 1},
9075 {184, 164, 0, 12, 1},
9076 {188, 164, 4, 12, 1},
9077 {192, 165, 8, 12, 1},
9078 {196, 166, 0, 12, 1},
9081 static const struct rf_channel rf_vals_5592_xtal40[] = {
9082 /* Channel, N, K, mod, R */
9092 {10, 245, 7, 10, 3},
9093 {11, 246, 2, 10, 3},
9094 {12, 246, 7, 10, 3},
9095 {13, 247, 2, 10, 3},
9096 {14, 248, 4, 10, 3},
9100 {42, 86, 10, 12, 1},
9106 {54, 87, 10, 12, 1},
9112 {100, 91, 8, 12, 1},
9113 {102, 91, 10, 12, 1},
9114 {104, 92, 0, 12, 1},
9115 {106, 92, 2, 12, 1},
9116 {108, 92, 4, 12, 1},
9117 {110, 92, 6, 12, 1},
9118 {112, 92, 8, 12, 1},
9119 {114, 92, 10, 12, 1},
9120 {116, 93, 0, 12, 1},
9121 {118, 93, 2, 12, 1},
9122 {120, 93, 4, 12, 1},
9123 {122, 93, 6, 12, 1},
9124 {124, 93, 8, 12, 1},
9125 {126, 93, 10, 12, 1},
9126 {128, 94, 0, 12, 1},
9127 {130, 94, 2, 12, 1},
9128 {132, 94, 4, 12, 1},
9129 {134, 94, 6, 12, 1},
9130 {136, 94, 8, 12, 1},
9131 {138, 94, 10, 12, 1},
9132 {140, 95, 0, 12, 1},
9133 {149, 95, 9, 12, 1},
9134 {151, 95, 11, 12, 1},
9135 {153, 96, 1, 12, 1},
9136 {155, 96, 3, 12, 1},
9137 {157, 96, 5, 12, 1},
9138 {159, 96, 7, 12, 1},
9139 {161, 96, 9, 12, 1},
9140 {165, 97, 1, 12, 1},
9141 {184, 82, 0, 12, 1},
9142 {188, 82, 4, 12, 1},
9143 {192, 82, 8, 12, 1},
9144 {196, 83, 0, 12, 1},
9147 static const struct rf_channel rf_vals_7620[] = {
9148 {1, 0x50, 0x99, 0x99, 1},
9149 {2, 0x50, 0x44, 0x44, 2},
9150 {3, 0x50, 0xEE, 0xEE, 2},
9151 {4, 0x50, 0x99, 0x99, 3},
9152 {5, 0x51, 0x44, 0x44, 0},
9153 {6, 0x51, 0xEE, 0xEE, 0},
9154 {7, 0x51, 0x99, 0x99, 1},
9155 {8, 0x51, 0x44, 0x44, 2},
9156 {9, 0x51, 0xEE, 0xEE, 2},
9157 {10, 0x51, 0x99, 0x99, 3},
9158 {11, 0x52, 0x44, 0x44, 0},
9159 {12, 0x52, 0xEE, 0xEE, 0},
9160 {13, 0x52, 0x99, 0x99, 1},
9161 {14, 0x52, 0x33, 0x33, 3},
9164 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9166 struct hw_mode_spec *spec = &rt2x00dev->spec;
9167 struct channel_info *info;
9168 char *default_power1;
9169 char *default_power2;
9170 char *default_power3;
9171 unsigned int i, tx_chains, rx_chains;
9175 * Disable powersaving as default.
9177 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9180 * Change default retry settings to values corresponding more closely
9181 * to rate[0].count setting of minstrel rate control algorithm.
9183 rt2x00dev->hw->wiphy->retry_short = 2;
9184 rt2x00dev->hw->wiphy->retry_long = 2;
9187 * Initialize all hw fields.
9189 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9190 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9191 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9192 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9193 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9196 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9197 * unless we are capable of sending the buffered frames out after the
9198 * DTIM transmission using rt2x00lib_beacondone. This will send out
9199 * multicast and broadcast traffic immediately instead of buffering it
9200 * infinitly and thus dropping it after some time.
9202 if (!rt2x00_is_usb(rt2x00dev))
9203 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9205 /* Set MFP if HW crypto is disabled. */
9206 if (rt2800_hwcrypt_disabled(rt2x00dev))
9207 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9209 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9210 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9211 rt2800_eeprom_addr(rt2x00dev,
9212 EEPROM_MAC_ADDR_0));
9215 * As rt2800 has a global fallback table we cannot specify
9216 * more then one tx rate per frame but since the hw will
9217 * try several rates (based on the fallback table) we should
9218 * initialize max_report_rates to the maximum number of rates
9219 * we are going to try. Otherwise mac80211 will truncate our
9220 * reported tx rates and the rc algortihm will end up with
9223 rt2x00dev->hw->max_rates = 1;
9224 rt2x00dev->hw->max_report_rates = 7;
9225 rt2x00dev->hw->max_rate_tries = 1;
9228 * Initialize hw_mode information.
9230 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9232 switch (rt2x00dev->chip.rf) {
9235 spec->num_channels = 14;
9236 spec->channels = rf_vals;
9241 spec->num_channels = ARRAY_SIZE(rf_vals);
9242 spec->channels = rf_vals;
9260 spec->num_channels = 14;
9261 if (rt2800_clk_is_20mhz(rt2x00dev))
9262 spec->channels = rf_vals_3x_xtal20;
9264 spec->channels = rf_vals_3x;
9268 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9269 spec->channels = rf_vals_7620;
9274 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9275 spec->channels = rf_vals_3x;
9279 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
9280 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9281 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9282 spec->channels = rf_vals_5592_xtal40;
9284 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9285 spec->channels = rf_vals_5592_xtal20;
9290 if (WARN_ON_ONCE(!spec->channels))
9293 spec->supported_bands = SUPPORT_BAND_2GHZ;
9294 if (spec->num_channels > 14)
9295 spec->supported_bands |= SUPPORT_BAND_5GHZ;
9298 * Initialize HT information.
9300 if (!rt2x00_rf(rt2x00dev, RF2020))
9301 spec->ht.ht_supported = true;
9303 spec->ht.ht_supported = false;
9306 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
9307 IEEE80211_HT_CAP_GRN_FLD |
9308 IEEE80211_HT_CAP_SGI_20 |
9309 IEEE80211_HT_CAP_SGI_40;
9311 tx_chains = rt2x00dev->default_ant.tx_chain_num;
9312 rx_chains = rt2x00dev->default_ant.rx_chain_num;
9315 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9317 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
9319 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
9320 spec->ht.ampdu_density = 4;
9321 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9322 if (tx_chains != rx_chains) {
9323 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9324 spec->ht.mcs.tx_params |=
9325 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9328 switch (rx_chains) {
9330 spec->ht.mcs.rx_mask[2] = 0xff;
9332 spec->ht.mcs.rx_mask[1] = 0xff;
9334 spec->ht.mcs.rx_mask[0] = 0xff;
9335 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9340 * Create channel information array
9342 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
9346 spec->channels_info = info;
9348 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9349 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
9351 if (rt2x00dev->default_ant.tx_chain_num > 2)
9352 default_power3 = rt2800_eeprom_addr(rt2x00dev,
9353 EEPROM_EXT_TXPOWER_BG3);
9355 default_power3 = NULL;
9357 for (i = 0; i < 14; i++) {
9358 info[i].default_power1 = default_power1[i];
9359 info[i].default_power2 = default_power2[i];
9361 info[i].default_power3 = default_power3[i];
9364 if (spec->num_channels > 14) {
9365 default_power1 = rt2800_eeprom_addr(rt2x00dev,
9367 default_power2 = rt2800_eeprom_addr(rt2x00dev,
9370 if (rt2x00dev->default_ant.tx_chain_num > 2)
9372 rt2800_eeprom_addr(rt2x00dev,
9373 EEPROM_EXT_TXPOWER_A3);
9375 default_power3 = NULL;
9377 for (i = 14; i < spec->num_channels; i++) {
9378 info[i].default_power1 = default_power1[i - 14];
9379 info[i].default_power2 = default_power2[i - 14];
9381 info[i].default_power3 = default_power3[i - 14];
9385 switch (rt2x00dev->chip.rf) {
9404 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9411 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9417 if (rt2x00_rt(rt2x00dev, RT3290))
9418 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
9420 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
9422 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9423 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9443 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9448 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9451 rt2x00_set_rt(rt2x00dev, rt, rev);
9456 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9461 retval = rt2800_probe_rt(rt2x00dev);
9466 * Allocate eeprom data.
9468 retval = rt2800_validate_eeprom(rt2x00dev);
9472 retval = rt2800_init_eeprom(rt2x00dev);
9477 * Enable rfkill polling by setting GPIO direction of the
9478 * rfkill switch GPIO pin correctly.
9480 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
9481 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1);
9482 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9485 * Initialize hw specifications.
9487 retval = rt2800_probe_hw_mode(rt2x00dev);
9492 * Set device capabilities.
9494 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9495 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9496 if (!rt2x00_is_usb(rt2x00dev))
9497 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9500 * Set device requirements.
9502 if (!rt2x00_is_soc(rt2x00dev))
9503 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9504 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9505 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9506 if (!rt2800_hwcrypt_disabled(rt2x00dev))
9507 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9508 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9509 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9510 if (rt2x00_is_usb(rt2x00dev))
9511 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9513 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9514 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9518 * Set the rssi offset.
9520 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9524 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
9527 * IEEE80211 stack callback functions.
9529 void rt2800_get_key_seq(struct ieee80211_hw *hw,
9530 struct ieee80211_key_conf *key,
9531 struct ieee80211_key_seq *seq)
9533 struct rt2x00_dev *rt2x00dev = hw->priv;
9534 struct mac_iveiv_entry iveiv_entry;
9537 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9540 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
9541 rt2800_register_multiread(rt2x00dev, offset,
9542 &iveiv_entry, sizeof(iveiv_entry));
9544 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9545 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
9547 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
9549 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
9551 struct rt2x00_dev *rt2x00dev = hw->priv;
9553 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9555 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
9556 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
9557 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9559 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
9560 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
9561 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9563 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
9564 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9565 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9567 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
9568 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
9569 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9571 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
9572 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
9573 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9575 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
9576 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
9577 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9579 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
9580 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
9581 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9585 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
9587 int rt2800_conf_tx(struct ieee80211_hw *hw,
9588 struct ieee80211_vif *vif, u16 queue_idx,
9589 const struct ieee80211_tx_queue_params *params)
9591 struct rt2x00_dev *rt2x00dev = hw->priv;
9592 struct data_queue *queue;
9593 struct rt2x00_field32 field;
9599 * First pass the configuration through rt2x00lib, that will
9600 * update the queue settings and validate the input. After that
9601 * we are free to update the registers based on the value
9602 * in the queue parameter.
9604 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
9609 * We only need to perform additional register initialization
9615 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
9617 /* Update WMM TXOP register */
9618 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9619 field.bit_offset = (queue_idx & 1) * 16;
9620 field.bit_mask = 0xffff << field.bit_offset;
9622 reg = rt2800_register_read(rt2x00dev, offset);
9623 rt2x00_set_field32(®, field, queue->txop);
9624 rt2800_register_write(rt2x00dev, offset, reg);
9626 /* Update WMM registers */
9627 field.bit_offset = queue_idx * 4;
9628 field.bit_mask = 0xf << field.bit_offset;
9630 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
9631 rt2x00_set_field32(®, field, queue->aifs);
9632 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9634 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
9635 rt2x00_set_field32(®, field, queue->cw_min);
9636 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9638 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
9639 rt2x00_set_field32(®, field, queue->cw_max);
9640 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9642 /* Update EDCA registers */
9643 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9645 reg = rt2800_register_read(rt2x00dev, offset);
9646 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
9647 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
9648 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9649 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9650 rt2800_register_write(rt2x00dev, offset, reg);
9654 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
9656 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
9658 struct rt2x00_dev *rt2x00dev = hw->priv;
9662 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
9663 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9664 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
9665 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9669 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
9671 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
9672 struct ieee80211_ampdu_params *params)
9674 struct ieee80211_sta *sta = params->sta;
9675 enum ieee80211_ampdu_mlme_action action = params->action;
9676 u16 tid = params->tid;
9677 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
9681 * Don't allow aggregation for stations the hardware isn't aware
9682 * of because tx status reports for frames to an unknown station
9683 * always contain wcid=WCID_END+1 and thus we can't distinguish
9684 * between multiple stations which leads to unwanted situations
9685 * when the hw reorders frames due to aggregation.
9687 if (sta_priv->wcid > WCID_END)
9691 case IEEE80211_AMPDU_RX_START:
9692 case IEEE80211_AMPDU_RX_STOP:
9694 * The hw itself takes care of setting up BlockAck mechanisms.
9695 * So, we only have to allow mac80211 to nagotiate a BlockAck
9696 * agreement. Once that is done, the hw will BlockAck incoming
9697 * AMPDUs without further setup.
9700 case IEEE80211_AMPDU_TX_START:
9701 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9703 case IEEE80211_AMPDU_TX_STOP_CONT:
9704 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9705 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9706 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9708 case IEEE80211_AMPDU_TX_OPERATIONAL:
9711 rt2x00_warn((struct rt2x00_dev *)hw->priv,
9712 "Unknown AMPDU action\n");
9717 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
9719 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9720 struct survey_info *survey)
9722 struct rt2x00_dev *rt2x00dev = hw->priv;
9723 struct ieee80211_conf *conf = &hw->conf;
9724 u32 idle, busy, busy_ext;
9729 survey->channel = conf->chandef.chan;
9731 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
9732 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
9733 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
9736 survey->filled = SURVEY_INFO_TIME |
9737 SURVEY_INFO_TIME_BUSY |
9738 SURVEY_INFO_TIME_EXT_BUSY;
9740 survey->time = (idle + busy) / 1000;
9741 survey->time_busy = busy / 1000;
9742 survey->time_ext_busy = busy_ext / 1000;
9745 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9746 survey->filled |= SURVEY_INFO_IN_USE;
9751 EXPORT_SYMBOL_GPL(rt2800_get_survey);
9753 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9754 MODULE_VERSION(DRV_VERSION);
9755 MODULE_DESCRIPTION("Ralink RT2800 library");
9756 MODULE_LICENSE("GPL");