drivers/net/wireless/ralink/rt2x00/rt2800mmio.c

   1 /*      Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   2  *      Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   3  *      Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   4  *      Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   5  *      Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   6  *      Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   7  *      Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   8  *      Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
   9  *      <http://rt2x00.serialmonkey.com>
  10  *
  11  *      This program is free software; you can redistribute it and/or modify
  12  *      it under the terms of the GNU General Public License as published by
  13  *      the Free Software Foundation; either version 2 of the License, or
  14  *      (at your option) any later version.
  15  *
  16  *      This program is distributed in the hope that it will be useful,
  17  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  *      GNU General Public License for more details.
  20  *
  21  *      You should have received a copy of the GNU General Public License
  22  *      along with this program; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 /*      Module: rt2800mmio
  26  *      Abstract: rt2800 MMIO device routines.
  27  */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/export.h>
  32
  33 #include "rt2x00.h"
  34 #include "rt2x00mmio.h"
  35 #include "rt2800.h"
  36 #include "rt2800lib.h"
  37 #include "rt2800mmio.h"
  38
  39 /*
  40  * TX descriptor initialization
  41  */
  42 __le32 *rt2800mmio_get_txwi(struct queue_entry *entry)
  43 {
  44         return (__le32 *) entry->skb->data;
  45 }
  46 EXPORT_SYMBOL_GPL(rt2800mmio_get_txwi);
  47
  48 void rt2800mmio_write_tx_desc(struct queue_entry *entry,
  49                               struct txentry_desc *txdesc)
  50 {
  51         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  52         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  53         __le32 *txd = entry_priv->desc;
  54         u32 word;
  55         const unsigned int txwi_size = entry->queue->winfo_size;
  56
  57         /*
  58          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
  59          * must contains a TXWI structure + 802.11 header + padding + 802.11
  60          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
  61          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
  62          * data. It means that LAST_SEC0 is always 0.
  63          */
  64
  65         /*
  66          * Initialize TX descriptor
  67          */
  68         word = 0;
  69         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
  70         rt2x00_desc_write(txd, 0, word);
  71
  72         word = 0;
  73         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
  74         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
  75                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  76         rt2x00_set_field32(&word, TXD_W1_BURST,
  77                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
  78         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size);
  79         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
  80         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
  81         rt2x00_desc_write(txd, 1, word);
  82
  83         word = 0;
  84         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
  85                            skbdesc->skb_dma + txwi_size);
  86         rt2x00_desc_write(txd, 2, word);
  87
  88         word = 0;
  89         rt2x00_set_field32(&word, TXD_W3_WIV,
  90                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
  91         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
  92         rt2x00_desc_write(txd, 3, word);
  93
  94         /*
  95          * Register descriptor details in skb frame descriptor.
  96          */
  97         skbdesc->desc = txd;
  98         skbdesc->desc_len = TXD_DESC_SIZE;
  99 }
 100 EXPORT_SYMBOL_GPL(rt2800mmio_write_tx_desc);
 101
 102 /*
 103  * RX control handlers
 104  */
 105 void rt2800mmio_fill_rxdone(struct queue_entry *entry,
 106                             struct rxdone_entry_desc *rxdesc)
 107 {
 108         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 109         __le32 *rxd = entry_priv->desc;
 110         u32 word;
 111
 112         word = rt2x00_desc_read(rxd, 3);
 113
 114         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 115                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 116
 117         /*
 118          * Unfortunately we don't know the cipher type used during
 119          * decryption. This prevents us from correct providing
 120          * correct statistics through debugfs.
 121          */
 122         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 123
 124         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 125                 /*
 126                  * Hardware has stripped IV/EIV data from 802.11 frame during
 127                  * decryption. Unfortunately the descriptor doesn't contain
 128                  * any fields with the EIV/IV data either, so they can't
 129                  * be restored by rt2x00lib.
 130                  */
 131                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 132
 133                 /*
 134                  * The hardware has already checked the Michael Mic and has
 135                  * stripped it from the frame. Signal this to mac80211.
 136                  */
 137                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 138
 139                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) {
 140                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 141                 } else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) {
 142                         /*
 143                          * In order to check the Michael Mic, the packet must have
 144                          * been decrypted.  Mac80211 doesnt check the MMIC failure
 145                          * flag to initiate MMIC countermeasures if the decoded flag
 146                          * has not been set.
 147                          */
 148                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 149
 150                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 151                 }
 152         }
 153
 154         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 155                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 156
 157         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 158                 rxdesc->dev_flags |= RXDONE_L2PAD;
 159
 160         /*
 161          * Process the RXWI structure that is at the start of the buffer.
 162          */
 163         rt2800_process_rxwi(entry, rxdesc);
 164 }
 165 EXPORT_SYMBOL_GPL(rt2800mmio_fill_rxdone);
 166
 167 /*
 168  * Interrupt functions.
 169  */
 170 static void rt2800mmio_wakeup(struct rt2x00_dev *rt2x00dev)
 171 {
 172         struct ieee80211_conf conf = { .flags = 0 };
 173         struct rt2x00lib_conf libconf = { .conf = &conf };
 174
 175         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 176 }
 177
 178 static bool rt2800mmio_txdone_entry_check(struct queue_entry *entry, u32 status)
 179 {
 180         __le32 *txwi;
 181         u32 word;
 182         int wcid, tx_wcid;
 183
 184         wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
 185
 186         txwi = rt2800_drv_get_txwi(entry);
 187         word = rt2x00_desc_read(txwi, 1);
 188         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 189
 190         return (tx_wcid == wcid);
 191 }
 192
 193 static bool rt2800mmio_txdone_find_entry(struct queue_entry *entry, void *data)
 194 {
 195         u32 status = *(u32 *)data;
 196
 197         /*
 198          * rt2800pci hardware might reorder frames when exchanging traffic
 199          * with multiple BA enabled STAs.
 200          *
 201          * For example, a tx queue
 202          *    [ STA1 | STA2 | STA1 | STA2 ]
 203          * can result in tx status reports
 204          *    [ STA1 | STA1 | STA2 | STA2 ]
 205          * when the hw decides to aggregate the frames for STA1 into one AMPDU.
 206          *
 207          * To mitigate this effect, associate the tx status to the first frame
 208          * in the tx queue with a matching wcid.
 209          */
 210         if (rt2800mmio_txdone_entry_check(entry, status) &&
 211             !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
 212                 /*
 213                  * Got a matching frame, associate the tx status with
 214                  * the frame
 215                  */
 216                 entry->status = status;
 217                 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
 218                 return true;
 219         }
 220
 221         /* Check the next frame */
 222         return false;
 223 }
 224
 225 static bool rt2800mmio_txdone_match_first(struct queue_entry *entry, void *data)
 226 {
 227         u32 status = *(u32 *)data;
 228
 229         /*
 230          * Find the first frame without tx status and assign this status to it
 231          * regardless if it matches or not.
 232          */
 233         if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
 234                 /*
 235                  * Got a matching frame, associate the tx status with
 236                  * the frame
 237                  */
 238                 entry->status = status;
 239                 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
 240                 return true;
 241         }
 242
 243         /* Check the next frame */
 244         return false;
 245 }
 246 static bool rt2800mmio_txdone_release_entries(struct queue_entry *entry,
 247                                               void *data)
 248 {
 249         if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
 250                 rt2800_txdone_entry(entry, entry->status,
 251                                     rt2800mmio_get_txwi(entry), true);
 252                 return false;
 253         }
 254
 255         /* No more frames to release */
 256         return true;
 257 }
 258
 259 static bool rt2800mmio_txdone(struct rt2x00_dev *rt2x00dev)
 260 {
 261         struct data_queue *queue;
 262         u32 status;
 263         u8 qid;
 264         int max_tx_done = 16;
 265
 266         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 267                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 268                 if (unlikely(qid >= QID_RX)) {
 269                         /*
 270                          * Unknown queue, this shouldn't happen. Just drop
 271                          * this tx status.
 272                          */
 273                         rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
 274                                     qid);
 275                         break;
 276                 }
 277
 278                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 279                 if (unlikely(queue == NULL)) {
 280                         /*
 281                          * The queue is NULL, this shouldn't happen. Stop
 282                          * processing here and drop the tx status
 283                          */
 284                         rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
 285                                     qid);
 286                         break;
 287                 }
 288
 289                 if (unlikely(rt2x00queue_empty(queue))) {
 290                         /*
 291                          * The queue is empty. Stop processing here
 292                          * and drop the tx status.
 293                          */
 294                         rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
 295                                     qid);
 296                         break;
 297                 }
 298
 299                 /*
 300                  * Let's associate this tx status with the first
 301                  * matching frame.
 302                  */
 303                 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
 304                                                 Q_INDEX, &status,
 305                                                 rt2800mmio_txdone_find_entry)) {
 306                         /*
 307                          * We cannot match the tx status to any frame, so just
 308                          * use the first one.
 309                          */
 310                         if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
 311                                                         Q_INDEX, &status,
 312                                                         rt2800mmio_txdone_match_first)) {
 313                                 rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
 314                                             qid);
 315                                 break;
 316                         }
 317                 }
 318
 319                 /*
 320                  * Release all frames with a valid tx status.
 321                  */
 322                 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
 323                                            Q_INDEX, NULL,
 324                                            rt2800mmio_txdone_release_entries);
 325
 326                 if (--max_tx_done == 0)
 327                         break;
 328         }
 329
 330         return !max_tx_done;
 331 }
 332
 333 static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev,
 334                                                struct rt2x00_field32 irq_field)
 335 {
 336         u32 reg;
 337
 338         /*
 339          * Enable a single interrupt. The interrupt mask register
 340          * access needs locking.
 341          */
 342         spin_lock_irq(&rt2x00dev->irqmask_lock);
 343         reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
 344         rt2x00_set_field32(&reg, irq_field, 1);
 345         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
 346         spin_unlock_irq(&rt2x00dev->irqmask_lock);
 347 }
 348
 349 void rt2800mmio_txstatus_tasklet(unsigned long data)
 350 {
 351         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 352         if (rt2800mmio_txdone(rt2x00dev))
 353                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 354
 355         /*
 356          * No need to enable the tx status interrupt here as we always
 357          * leave it enabled to minimize the possibility of a tx status
 358          * register overflow. See comment in interrupt handler.
 359          */
 360 }
 361 EXPORT_SYMBOL_GPL(rt2800mmio_txstatus_tasklet);
 362
 363 void rt2800mmio_pretbtt_tasklet(unsigned long data)
 364 {
 365         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 366         rt2x00lib_pretbtt(rt2x00dev);
 367         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 368                 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
 369 }
 370 EXPORT_SYMBOL_GPL(rt2800mmio_pretbtt_tasklet);
 371
 372 void rt2800mmio_tbtt_tasklet(unsigned long data)
 373 {
 374         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 375         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 376         u32 reg;
 377
 378         rt2x00lib_beacondone(rt2x00dev);
 379
 380         if (rt2x00dev->intf_ap_count) {
 381                 /*
 382                  * The rt2800pci hardware tbtt timer is off by 1us per tbtt
 383                  * causing beacon skew and as a result causing problems with
 384                  * some powersaving clients over time. Shorten the beacon
 385                  * interval every 64 beacons by 64us to mitigate this effect.
 386                  */
 387                 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
 388                         reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
 389                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 390                                            (rt2x00dev->beacon_int * 16) - 1);
 391                         rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 392                 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
 393                         reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
 394                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 395                                            (rt2x00dev->beacon_int * 16));
 396                         rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 397                 }
 398                 drv_data->tbtt_tick++;
 399                 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
 400         }
 401
 402         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 403                 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
 404 }
 405 EXPORT_SYMBOL_GPL(rt2800mmio_tbtt_tasklet);
 406
 407 void rt2800mmio_rxdone_tasklet(unsigned long data)
 408 {
 409         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 410         if (rt2x00mmio_rxdone(rt2x00dev))
 411                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 412         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 413                 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
 414 }
 415 EXPORT_SYMBOL_GPL(rt2800mmio_rxdone_tasklet);
 416
 417 void rt2800mmio_autowake_tasklet(unsigned long data)
 418 {
 419         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 420         rt2800mmio_wakeup(rt2x00dev);
 421         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 422                 rt2800mmio_enable_interrupt(rt2x00dev,
 423                                             INT_MASK_CSR_AUTO_WAKEUP);
 424 }
 425 EXPORT_SYMBOL_GPL(rt2800mmio_autowake_tasklet);
 426
 427 static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 428 {
 429         u32 status;
 430         int i;
 431
 432         /*
 433          * The TX_FIFO_STATUS interrupt needs special care. We should
 434          * read TX_STA_FIFO but we should do it immediately as otherwise
 435          * the register can overflow and we would lose status reports.
 436          *
 437          * Hence, read the TX_STA_FIFO register and copy all tx status
 438          * reports into a kernel FIFO which is handled in the txstatus
 439          * tasklet. We use a tasklet to process the tx status reports
 440          * because we can schedule the tasklet multiple times (when the
 441          * interrupt fires again during tx status processing).
 442          *
 443          * Furthermore we don't disable the TX_FIFO_STATUS
 444          * interrupt here but leave it enabled so that the TX_STA_FIFO
 445          * can also be read while the tx status tasklet gets executed.
 446          *
 447          * Since we have only one producer and one consumer we don't
 448          * need to lock the kfifo.
 449          */
 450         for (i = 0; i < rt2x00dev->tx->limit; i++) {
 451                 status = rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO);
 452
 453                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 454                         break;
 455
 456                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, status)) {
 457                         rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
 458                         break;
 459                 }
 460         }
 461
 462         /* Schedule the tasklet for processing the tx status. */
 463         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 464 }
 465
 466 irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance)
 467 {
 468         struct rt2x00_dev *rt2x00dev = dev_instance;
 469         u32 reg, mask;
 470
 471         /* Read status and ACK all interrupts */
 472         reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
 473         rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 474
 475         if (!reg)
 476                 return IRQ_NONE;
 477
 478         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 479                 return IRQ_HANDLED;
 480
 481         /*
 482          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
 483          * for interrupts and interrupt masks we can just use the value of
 484          * INT_SOURCE_CSR to create the interrupt mask.
 485          */
 486         mask = ~reg;
 487
 488         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
 489                 rt2800mmio_txstatus_interrupt(rt2x00dev);
 490                 /*
 491                  * Never disable the TX_FIFO_STATUS interrupt.
 492                  */
 493                 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 494         }
 495
 496         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 497                 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
 498
 499         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 500                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
 501
 502         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 503                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 504
 505         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 506                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
 507
 508         /*
 509          * Disable all interrupts for which a tasklet was scheduled right now,
 510          * the tasklet will reenable the appropriate interrupts.
 511          */
 512         spin_lock(&rt2x00dev->irqmask_lock);
 513         reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
 514         reg &= mask;
 515         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
 516         spin_unlock(&rt2x00dev->irqmask_lock);
 517
 518         return IRQ_HANDLED;
 519 }
 520 EXPORT_SYMBOL_GPL(rt2800mmio_interrupt);
 521
 522 void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
 523                            enum dev_state state)
 524 {
 525         u32 reg;
 526         unsigned long flags;
 527
 528         /*
 529          * When interrupts are being enabled, the interrupt registers
 530          * should clear the register to assure a clean state.
 531          */
 532         if (state == STATE_RADIO_IRQ_ON) {
 533                 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
 534                 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 535         }
 536
 537         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 538         reg = 0;
 539         if (state == STATE_RADIO_IRQ_ON) {
 540                 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
 541                 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
 542                 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
 543                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 544                 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
 545         }
 546         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
 547         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 548
 549         if (state == STATE_RADIO_IRQ_OFF) {
 550                 /*
 551                  * Wait for possibly running tasklets to finish.
 552                  */
 553                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
 554                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
 555                 tasklet_kill(&rt2x00dev->autowake_tasklet);
 556                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 557                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 558         }
 559 }
 560 EXPORT_SYMBOL_GPL(rt2800mmio_toggle_irq);
 561
 562 /*
 563  * Queue handlers.
 564  */
 565 void rt2800mmio_start_queue(struct data_queue *queue)
 566 {
 567         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 568         u32 reg;
 569
 570         switch (queue->qid) {
 571         case QID_RX:
 572                 reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
 573                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 574                 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 575                 break;
 576         case QID_BEACON:
 577                 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
 578                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 579                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 580                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 581                 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 582
 583                 reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
 584                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
 585                 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
 586                 break;
 587         default:
 588                 break;
 589         }
 590 }
 591 EXPORT_SYMBOL_GPL(rt2800mmio_start_queue);
 592
 593 void rt2800mmio_kick_queue(struct data_queue *queue)
 594 {
 595         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 596         struct queue_entry *entry;
 597
 598         switch (queue->qid) {
 599         case QID_AC_VO:
 600         case QID_AC_VI:
 601         case QID_AC_BE:
 602         case QID_AC_BK:
 603                 WARN_ON_ONCE(rt2x00queue_empty(queue));
 604                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 605                 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
 606                                           entry->entry_idx);
 607                 break;
 608         case QID_MGMT:
 609                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 610                 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
 611                                           entry->entry_idx);
 612                 break;
 613         default:
 614                 break;
 615         }
 616 }
 617 EXPORT_SYMBOL_GPL(rt2800mmio_kick_queue);
 618
 619 void rt2800mmio_stop_queue(struct data_queue *queue)
 620 {
 621         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 622         u32 reg;
 623
 624         switch (queue->qid) {
 625         case QID_RX:
 626                 reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
 627                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 628                 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 629                 break;
 630         case QID_BEACON:
 631                 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
 632                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 633                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 634                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 635                 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 636
 637                 reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
 638                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
 639                 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
 640
 641                 /*
 642                  * Wait for current invocation to finish. The tasklet
 643                  * won't be scheduled anymore afterwards since we disabled
 644                  * the TBTT and PRE TBTT timer.
 645                  */
 646                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 647                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 648
 649                 break;
 650         default:
 651                 break;
 652         }
 653 }
 654 EXPORT_SYMBOL_GPL(rt2800mmio_stop_queue);
 655
 656 void rt2800mmio_queue_init(struct data_queue *queue)
 657 {
 658         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 659         unsigned short txwi_size, rxwi_size;
 660
 661         rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
 662
 663         switch (queue->qid) {
 664         case QID_RX:
 665                 queue->limit = 128;
 666                 queue->data_size = AGGREGATION_SIZE;
 667                 queue->desc_size = RXD_DESC_SIZE;
 668                 queue->winfo_size = rxwi_size;
 669                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
 670                 break;
 671
 672         case QID_AC_VO:
 673         case QID_AC_VI:
 674         case QID_AC_BE:
 675         case QID_AC_BK:
 676                 queue->limit = 64;
 677                 queue->data_size = AGGREGATION_SIZE;
 678                 queue->desc_size = TXD_DESC_SIZE;
 679                 queue->winfo_size = txwi_size;
 680                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
 681                 break;
 682
 683         case QID_BEACON:
 684                 queue->limit = 8;
 685                 queue->data_size = 0; /* No DMA required for beacons */
 686                 queue->desc_size = TXD_DESC_SIZE;
 687                 queue->winfo_size = txwi_size;
 688                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
 689                 break;
 690
 691         case QID_ATIM:
 692                 /* fallthrough */
 693         default:
 694                 BUG();
 695                 break;
 696         }
 697 }
 698 EXPORT_SYMBOL_GPL(rt2800mmio_queue_init);
 699
 700 /*
 701  * Initialization functions.
 702  */
 703 bool rt2800mmio_get_entry_state(struct queue_entry *entry)
 704 {
 705         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 706         u32 word;
 707
 708         if (entry->queue->qid == QID_RX) {
 709                 word = rt2x00_desc_read(entry_priv->desc, 1);
 710
 711                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 712         } else {
 713                 word = rt2x00_desc_read(entry_priv->desc, 1);
 714
 715                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 716         }
 717 }
 718 EXPORT_SYMBOL_GPL(rt2800mmio_get_entry_state);
 719
 720 void rt2800mmio_clear_entry(struct queue_entry *entry)
 721 {
 722         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 723         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 724         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 725         u32 word;
 726
 727         if (entry->queue->qid == QID_RX) {
 728                 word = rt2x00_desc_read(entry_priv->desc, 0);
 729                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 730                 rt2x00_desc_write(entry_priv->desc, 0, word);
 731
 732                 word = rt2x00_desc_read(entry_priv->desc, 1);
 733                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 734                 rt2x00_desc_write(entry_priv->desc, 1, word);
 735
 736                 /*
 737                  * Set RX IDX in register to inform hardware that we have
 738                  * handled this entry and it is available for reuse again.
 739                  */
 740                 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
 741                                           entry->entry_idx);
 742         } else {
 743                 word = rt2x00_desc_read(entry_priv->desc, 1);
 744                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 745                 rt2x00_desc_write(entry_priv->desc, 1, word);
 746         }
 747 }
 748 EXPORT_SYMBOL_GPL(rt2800mmio_clear_entry);
 749
 750 int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev)
 751 {
 752         struct queue_entry_priv_mmio *entry_priv;
 753
 754         /*
 755          * Initialize registers.
 756          */
 757         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 758         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
 759                                   entry_priv->desc_dma);
 760         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
 761                                   rt2x00dev->tx[0].limit);
 762         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 763         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 764
 765         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 766         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
 767                                   entry_priv->desc_dma);
 768         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
 769                                   rt2x00dev->tx[1].limit);
 770         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 771         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 772
 773         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 774         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
 775                                   entry_priv->desc_dma);
 776         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
 777                                   rt2x00dev->tx[2].limit);
 778         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 779         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 780
 781         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 782         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
 783                                   entry_priv->desc_dma);
 784         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
 785                                   rt2x00dev->tx[3].limit);
 786         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 787         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 788
 789         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
 790         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
 791         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
 792         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
 793
 794         rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
 795         rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
 796         rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
 797         rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
 798
 799         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 800         rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
 801                                   entry_priv->desc_dma);
 802         rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
 803                                   rt2x00dev->rx[0].limit);
 804         rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
 805                                   rt2x00dev->rx[0].limit - 1);
 806         rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
 807
 808         rt2800_disable_wpdma(rt2x00dev);
 809
 810         rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 811
 812         return 0;
 813 }
 814 EXPORT_SYMBOL_GPL(rt2800mmio_init_queues);
 815
 816 int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
 817 {
 818         u32 reg;
 819
 820         /*
 821          * Reset DMA indexes
 822          */
 823         reg = rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX);
 824         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 825         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 826         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 827         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 828         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 829         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 830         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 831         rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 832
 833         rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 834         rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 835
 836         if (rt2x00_is_pcie(rt2x00dev) &&
 837             (rt2x00_rt(rt2x00dev, RT3090) ||
 838              rt2x00_rt(rt2x00dev, RT3390) ||
 839              rt2x00_rt(rt2x00dev, RT3572) ||
 840              rt2x00_rt(rt2x00dev, RT3593) ||
 841              rt2x00_rt(rt2x00dev, RT5390) ||
 842              rt2x00_rt(rt2x00dev, RT5392) ||
 843              rt2x00_rt(rt2x00dev, RT5592))) {
 844                 reg = rt2x00mmio_register_read(rt2x00dev, AUX_CTRL);
 845                 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 846                 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 847                 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
 848         }
 849
 850         rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 851
 852         reg = 0;
 853         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 854         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 855         rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 856
 857         rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 858
 859         return 0;
 860 }
 861 EXPORT_SYMBOL_GPL(rt2800mmio_init_registers);
 862
 863 /*
 864  * Device state switch handlers.
 865  */
 866 int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev)
 867 {
 868         /* Wait for DMA, ignore error until we initialize queues. */
 869         rt2800_wait_wpdma_ready(rt2x00dev);
 870
 871         if (unlikely(rt2800mmio_init_queues(rt2x00dev)))
 872                 return -EIO;
 873
 874         return rt2800_enable_radio(rt2x00dev);
 875 }
 876 EXPORT_SYMBOL_GPL(rt2800mmio_enable_radio);
 877
 878 MODULE_AUTHOR(DRV_PROJECT);
 879 MODULE_VERSION(DRV_VERSION);
 880 MODULE_DESCRIPTION("rt2800 MMIO library");
 881 MODULE_LICENSE("GPL");