drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "../pwrseqcmd.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "dm.h"
  38 #include "fw.h"
  39 #include "led.h"
  40 #include "hw.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG              5
  44
  45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp1byte;
  61
  62         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp1byte &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  68 }
  69
  70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp1byte;
  74
  75         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp1byte |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  81 }
  82
  83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  96         while (skb_queue_len(&ring->queue)) {
  97                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  98                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  99
 100                 pci_unmap_single(rtlpci->pdev,
 101                                  rtlpriv->cfg->ops->get_desc(
 102                                  hw,
 103                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 104                                  skb->len, PCI_DMA_TODEVICE);
 105                 kfree_skb(skb);
 106                 ring->idx = (ring->idx + 1) % ring->entries;
 107         }
 108         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 109 }
 110
 111 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool schedule_timer = b_need_turn_off_ckk;
 124         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 125                                         (u8 *)(&b_support_remote_wake_up));
 126
 127         if (!rtlhal->fw_ready)
 128                 return;
 129         if (!rtlpriv->psc.fw_current_inpsmode)
 130                 return;
 131
 132         while (1) {
 133                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 134                 if (rtlhal->fw_clk_change_in_progress) {
 135                         while (rtlhal->fw_clk_change_in_progress) {
 136                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 137                                 count++;
 138                                 udelay(100);
 139                                 if (count > 1000)
 140                                         return;
 141                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 142                         }
 143                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 144                 } else {
 145                         rtlhal->fw_clk_change_in_progress = false;
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                         break;
 148                 }
 149         }
 150
 151         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 152                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 153                 if (FW_PS_IS_ACK(rpwm_val)) {
 154                         isr_regaddr = REG_HISR;
 155                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 156                         while (!(content & IMR_CPWM) && (count < 500)) {
 157                                 udelay(50);
 158                                 count++;
 159                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         }
 161
 162                         if (content & IMR_CPWM) {
 163                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 164                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 165                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 166                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 167                                          rtlhal->fw_ps_state);
 168                         }
 169                 }
 170
 171                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 172                 rtlhal->fw_clk_change_in_progress = false;
 173                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 if (schedule_timer) {
 175                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 176                                   jiffies + MSECS(10));
 177                 }
 178
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                       u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       &rpwm_val);
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 247         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 251 {
 252         u8 rpwm_val = 0;
 253         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 254         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 255 }
 256
 257 void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t)
 258 {
 259         struct rtl_priv *rtlpriv = from_timer(rtlpriv, t,
 260                                               works.fw_clockoff_timer);
 261         struct ieee80211_hw *hw = rtlpriv->hw;
 262
 263         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 264 }
 265
 266 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 267 {
 268         struct rtl_priv *rtlpriv = rtl_priv(hw);
 269         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 270         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 271         bool fw_current_inps = false;
 272         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 273
 274         if (ppsc->low_power_enable) {
 275                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 276                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 277                 rtlhal->allow_sw_to_change_hwclc = false;
 278                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 279                                               &fw_pwrmode);
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 281                                               (u8 *)(&fw_current_inps));
 282         } else {
 283                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 284                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 285                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 286                                               &fw_pwrmode);
 287                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 288                                               (u8 *)(&fw_current_inps));
 289         }
 290 }
 291
 292 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 293 {
 294         struct rtl_priv *rtlpriv = rtl_priv(hw);
 295         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 296         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 297         bool fw_current_inps = true;
 298         u8 rpwm_val;
 299
 300         if (ppsc->low_power_enable) {
 301                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 302                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 303                                               (u8 *)(&fw_current_inps));
 304                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 305                                               &ppsc->fwctrl_psmode);
 306                 rtlhal->allow_sw_to_change_hwclc = true;
 307                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 308         } else {
 309                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 311                                               (u8 *)(&fw_current_inps));
 312                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 313                                               &ppsc->fwctrl_psmode);
 314                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 315         }
 316 }
 317
 318 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 319 {
 320         struct rtl_priv *rtlpriv = rtl_priv(hw);
 321         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 322         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 323
 324         switch (variable) {
 325         case HW_VAR_RCR:
 326                 *((u32 *)(val)) = rtlpci->receive_config;
 327                 break;
 328         case HW_VAR_RF_STATE:
 329                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 330                 break;
 331         case HW_VAR_FWLPS_RF_ON:{
 332                 enum rf_pwrstate rfstate;
 333                 u32 val_rcr;
 334
 335                 rtlpriv->cfg->ops->get_hw_reg(hw,
 336                                               HW_VAR_RF_STATE,
 337                                               (u8 *)(&rfstate));
 338                 if (rfstate == ERFOFF) {
 339                         *((bool *)(val)) = true;
 340                 } else {
 341                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 342                         val_rcr &= 0x00070000;
 343                         if (val_rcr)
 344                                 *((bool *)(val)) = false;
 345                         else
 346                                 *((bool *)(val)) = true;
 347                 }
 348                 break; }
 349         case HW_VAR_FW_PSMODE_STATUS:
 350                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 351                 break;
 352         case HW_VAR_CORRECT_TSF:{
 353                 u64 tsf;
 354                 u32 *ptsf_low = (u32 *)&tsf;
 355                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 356
 357                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 358                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 359
 360                 *((u64 *)(val)) = tsf;
 361                 break; }
 362         case HAL_DEF_WOWLAN:
 363                 break;
 364         default:
 365                 pr_err("switch case %#x not processed\n", variable);
 366                 break;
 367         }
 368 }
 369
 370 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 371 {
 372         struct rtl_priv *rtlpriv = rtl_priv(hw);
 373         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 374         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 375         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 376         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 377         u8 idx;
 378
 379         switch (variable) {
 380         case HW_VAR_ETHER_ADDR:
 381                 for (idx = 0; idx < ETH_ALEN; idx++) {
 382                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 383                                        val[idx]);
 384                 }
 385                 break;
 386         case HW_VAR_BASIC_RATE:{
 387                 u16 b_rate_cfg = ((u16 *)val)[0];
 388                 u8 rate_index = 0;
 389                 b_rate_cfg = b_rate_cfg & 0x15f;
 390                 b_rate_cfg |= 0x01;
 391                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 392                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 393                                (b_rate_cfg >> 8) & 0xff);
 394                 while (b_rate_cfg > 0x1) {
 395                         b_rate_cfg = (b_rate_cfg >> 1);
 396                         rate_index++;
 397                 }
 398                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 399                                rate_index);
 400                 break;
 401                 }
 402         case HW_VAR_BSSID:
 403                 for (idx = 0; idx < ETH_ALEN; idx++) {
 404                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 405                                        val[idx]);
 406                 }
 407                 break;
 408         case HW_VAR_SIFS:
 409                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 410                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 411
 412                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 413                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 414
 415                 if (!mac->ht_enable)
 416                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 417                                        0x0e0e);
 418                 else
 419                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 420                                        *((u16 *)val));
 421                 break;
 422         case HW_VAR_SLOT_TIME:{
 423                 u8 e_aci;
 424
 425                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 426                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 427
 428                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 429
 430                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 431                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 432                                                       &e_aci);
 433                 }
 434                 break;
 435                 }
 436         case HW_VAR_ACK_PREAMBLE:{
 437                 u8 reg_tmp;
 438                 u8 short_preamble = (bool)*val;
 439                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 440                 if (short_preamble) {
 441                         reg_tmp |= 0x02;
 442                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 443                                        2, reg_tmp);
 444                 } else {
 445                         reg_tmp |= 0xFD;
 446                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 447                                        2, reg_tmp);
 448                 }
 449                 break; }
 450         case HW_VAR_WPA_CONFIG:
 451                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 452                 break;
 453         case HW_VAR_AMPDU_MIN_SPACE:{
 454                 u8 min_spacing_to_set;
 455                 u8 sec_min_space;
 456
 457                 min_spacing_to_set = *val;
 458                 if (min_spacing_to_set <= 7) {
 459                         sec_min_space = 0;
 460
 461                         if (min_spacing_to_set < sec_min_space)
 462                                 min_spacing_to_set = sec_min_space;
 463
 464                         mac->min_space_cfg = ((mac->min_space_cfg &
 465                                                0xf8) |
 466                                               min_spacing_to_set);
 467
 468                         *val = min_spacing_to_set;
 469
 470                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 471                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 472                                   mac->min_space_cfg);
 473
 474                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 475                                        mac->min_space_cfg);
 476                 }
 477                 break; }
 478         case HW_VAR_SHORTGI_DENSITY:{
 479                 u8 density_to_set;
 480
 481                 density_to_set = *val;
 482                 mac->min_space_cfg |= (density_to_set << 3);
 483
 484                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 485                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 486                           mac->min_space_cfg);
 487
 488                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 489                                mac->min_space_cfg);
 490                 break;
 491                 }
 492         case HW_VAR_AMPDU_FACTOR:{
 493                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 494                 u8 factor_toset;
 495                 u8 *p_regtoset = NULL;
 496                 u8 index = 0;
 497
 498                 p_regtoset = regtoset_normal;
 499
 500                 factor_toset = *val;
 501                 if (factor_toset <= 3) {
 502                         factor_toset = (1 << (factor_toset + 2));
 503                         if (factor_toset > 0xf)
 504                                 factor_toset = 0xf;
 505
 506                         for (index = 0; index < 4; index++) {
 507                                 if ((p_regtoset[index] & 0xf0) >
 508                                     (factor_toset << 4))
 509                                         p_regtoset[index] =
 510                                             (p_regtoset[index] & 0x0f) |
 511                                             (factor_toset << 4);
 512
 513                                 if ((p_regtoset[index] & 0x0f) >
 514                                     factor_toset)
 515                                         p_regtoset[index] =
 516                                             (p_regtoset[index] & 0xf0) |
 517                                             (factor_toset);
 518
 519                                 rtl_write_byte(rtlpriv,
 520                                                (REG_AGGLEN_LMT + index),
 521                                                p_regtoset[index]);
 522
 523                         }
 524
 525                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 526                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 527                                   factor_toset);
 528                 }
 529                 break; }
 530         case HW_VAR_AC_PARAM:{
 531                 u8 e_aci = *val;
 532                 rtl88e_dm_init_edca_turbo(hw);
 533
 534                 if (rtlpci->acm_method != EACMWAY2_SW)
 535                         rtlpriv->cfg->ops->set_hw_reg(hw,
 536                                                       HW_VAR_ACM_CTRL,
 537                                                       &e_aci);
 538                 break; }
 539         case HW_VAR_ACM_CTRL:{
 540                 u8 e_aci = *val;
 541                 union aci_aifsn *p_aci_aifsn =
 542                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 543                 u8 acm = p_aci_aifsn->f.acm;
 544                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 545
 546                 acm_ctrl = acm_ctrl |
 547                            ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 548
 549                 if (acm) {
 550                         switch (e_aci) {
 551                         case AC0_BE:
 552                                 acm_ctrl |= ACMHW_BEQEN;
 553                                 break;
 554                         case AC2_VI:
 555                                 acm_ctrl |= ACMHW_VIQEN;
 556                                 break;
 557                         case AC3_VO:
 558                                 acm_ctrl |= ACMHW_VOQEN;
 559                                 break;
 560                         default:
 561                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 562                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 563                                          acm);
 564                                 break;
 565                         }
 566                 } else {
 567                         switch (e_aci) {
 568                         case AC0_BE:
 569                                 acm_ctrl &= (~ACMHW_BEQEN);
 570                                 break;
 571                         case AC2_VI:
 572                                 acm_ctrl &= (~ACMHW_VIQEN);
 573                                 break;
 574                         case AC3_VO:
 575                                 acm_ctrl &= (~ACMHW_VOQEN);
 576                                 break;
 577                         default:
 578                                 pr_err("switch case %#x not processed\n",
 579                                        e_aci);
 580                                 break;
 581                         }
 582                 }
 583
 584                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 585                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 586                          acm_ctrl);
 587                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 588                 break; }
 589         case HW_VAR_RCR:
 590                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 591                 rtlpci->receive_config = ((u32 *)(val))[0];
 592                 break;
 593         case HW_VAR_RETRY_LIMIT:{
 594                 u8 retry_limit = *val;
 595
 596                 rtl_write_word(rtlpriv, REG_RL,
 597                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 598                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 599                 break; }
 600         case HW_VAR_DUAL_TSF_RST:
 601                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 602                 break;
 603         case HW_VAR_EFUSE_BYTES:
 604                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 605                 break;
 606         case HW_VAR_EFUSE_USAGE:
 607                 rtlefuse->efuse_usedpercentage = *val;
 608                 break;
 609         case HW_VAR_IO_CMD:
 610                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 611                 break;
 612         case HW_VAR_SET_RPWM:{
 613                 u8 rpwm_val;
 614
 615                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 616                 udelay(1);
 617
 618                 if (rpwm_val & BIT(7)) {
 619                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 620                 } else {
 621                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 622                 }
 623                 break; }
 624         case HW_VAR_H2C_FW_PWRMODE:
 625                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 626                 break;
 627         case HW_VAR_FW_PSMODE_STATUS:
 628                 ppsc->fw_current_inpsmode = *((bool *)val);
 629                 break;
 630         case HW_VAR_RESUME_CLK_ON:
 631                 _rtl88ee_set_fw_ps_rf_on(hw);
 632                 break;
 633         case HW_VAR_FW_LPS_ACTION:{
 634                 bool enter_fwlps = *((bool *)val);
 635
 636                 if (enter_fwlps)
 637                         _rtl88ee_fwlps_enter(hw);
 638                  else
 639                         _rtl88ee_fwlps_leave(hw);
 640
 641                  break; }
 642         case HW_VAR_H2C_FW_JOINBSSRPT:{
 643                 u8 mstatus = *val;
 644                 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 645                 u8 count = 0, dlbcn_count = 0;
 646                 bool b_recover = false;
 647
 648                 if (mstatus == RT_MEDIA_CONNECT) {
 649                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 650                                                       NULL);
 651
 652                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 653                         rtl_write_byte(rtlpriv, REG_CR + 1,
 654                                        (tmp_regcr | BIT(0)));
 655
 656                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 657                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 658
 659                         tmp_reg422 =
 660                             rtl_read_byte(rtlpriv,
 661                                           REG_FWHW_TXQ_CTRL + 2);
 662                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 663                                        tmp_reg422 & (~BIT(6)));
 664                         if (tmp_reg422 & BIT(6))
 665                                 b_recover = true;
 666
 667                         do {
 668                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 669                                                              REG_TDECTRL+2);
 670                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 671                                                (bcnvalid_reg | BIT(0)));
 672                                 _rtl88ee_return_beacon_queue_skb(hw);
 673
 674                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 675                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 676                                                              REG_TDECTRL+2);
 677                                 count = 0;
 678                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 679                                         count++;
 680                                         udelay(10);
 681                                         bcnvalid_reg =
 682                                           rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 683                                 }
 684                                 dlbcn_count++;
 685                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 686
 687                         if (bcnvalid_reg & BIT(0))
 688                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 689
 690                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 691                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 692
 693                         if (b_recover) {
 694                                 rtl_write_byte(rtlpriv,
 695                                                REG_FWHW_TXQ_CTRL + 2,
 696                                                tmp_reg422);
 697                         }
 698
 699                         rtl_write_byte(rtlpriv, REG_CR + 1,
 700                                        (tmp_regcr & ~(BIT(0))));
 701                 }
 702                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 703                 break; }
 704         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 705                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 706                 break;
 707         case HW_VAR_AID:{
 708                 u16 u2btmp;
 709
 710                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 711                 u2btmp &= 0xC000;
 712                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 713                                mac->assoc_id));
 714                 break; }
 715         case HW_VAR_CORRECT_TSF:{
 716                 u8 btype_ibss = *val;
 717
 718                 if (btype_ibss)
 719                         _rtl88ee_stop_tx_beacon(hw);
 720
 721                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 722
 723                 rtl_write_dword(rtlpriv, REG_TSFTR,
 724                                 (u32)(mac->tsf & 0xffffffff));
 725                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 726                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 727
 728                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 729
 730                 if (btype_ibss)
 731                         _rtl88ee_resume_tx_beacon(hw);
 732                 break; }
 733         case HW_VAR_KEEP_ALIVE: {
 734                 u8 array[2];
 735
 736                 array[0] = 0xff;
 737                 array[1] = *((u8 *)val);
 738                 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
 739                                     2, array);
 740                 break; }
 741         default:
 742                 pr_err("switch case %#x not processed\n", variable);
 743                 break;
 744         }
 745 }
 746
 747 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 748 {
 749         struct rtl_priv *rtlpriv = rtl_priv(hw);
 750         bool status = true;
 751         long count = 0;
 752         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 753                     _LLT_OP(_LLT_WRITE_ACCESS);
 754
 755         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 756
 757         do {
 758                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 759                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 760                         break;
 761
 762                 if (count > POLLING_LLT_THRESHOLD) {
 763                         pr_err("Failed to polling write LLT done at address %d!\n",
 764                                address);
 765                         status = false;
 766                         break;
 767                 }
 768         } while (++count);
 769
 770         return status;
 771 }
 772
 773 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 774 {
 775         struct rtl_priv *rtlpriv = rtl_priv(hw);
 776         unsigned short i;
 777         u8 txpktbuf_bndy;
 778         u8 maxpage;
 779         bool status;
 780
 781         maxpage = 0xAF;
 782         txpktbuf_bndy = 0xAB;
 783
 784         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 785         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 786
 787         /*0x2600   MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
 788         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 789         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 790
 791         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 792         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 793
 794         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 795         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 796         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 797
 798         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 799                 status = _rtl88ee_llt_write(hw, i, i + 1);
 800                 if (true != status)
 801                         return status;
 802         }
 803
 804         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 805         if (true != status)
 806                 return status;
 807
 808         for (i = txpktbuf_bndy; i < maxpage; i++) {
 809                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 810                 if (true != status)
 811                         return status;
 812         }
 813
 814         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 815         if (true != status)
 816                 return status;
 817
 818         return true;
 819 }
 820
 821 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 822 {
 823         struct rtl_priv *rtlpriv = rtl_priv(hw);
 824         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 825         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 826
 827         if (rtlpriv->rtlhal.up_first_time)
 828                 return;
 829
 830         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 831                 rtl88ee_sw_led_on(hw, pled0);
 832         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 833                 rtl88ee_sw_led_on(hw, pled0);
 834         else
 835                 rtl88ee_sw_led_off(hw, pled0);
 836 }
 837
 838 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 839 {
 840         struct rtl_priv *rtlpriv = rtl_priv(hw);
 841         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 842         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 843
 844         u8 bytetmp;
 845         u16 wordtmp;
 846
 847         /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
 848         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 849         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 850         /*Auto Power Down to CHIP-off State*/
 851         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 852         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 853
 854         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 855         /* HW Power on sequence */
 856         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 857                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 858                                       RTL8188EE_NIC_ENABLE_FLOW)) {
 859                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 860                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 861                 return false;
 862         }
 863
 864         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 865         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 866
 867         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 868         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 869
 870         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 871         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 872
 873         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 874         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 875
 876         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 877         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 878         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 879         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 880
 881         /*Add for wake up online*/
 882         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 883
 884         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 885         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 886         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 887         rtl_write_byte(rtlpriv, 0x367, 0x80);
 888
 889         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 890         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 891         rtl_write_byte(rtlpriv, MSR, 0x00);
 892
 893         if (!rtlhal->mac_func_enable) {
 894                 if (_rtl88ee_llt_table_init(hw) == false) {
 895                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 896                                  "LLT table init fail\n");
 897                         return false;
 898                 }
 899         }
 900         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 901         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 902
 903         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 904         wordtmp &= 0xf;
 905         wordtmp |= 0xE771;
 906         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 907
 908         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 909         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 910         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 911
 912         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 913                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 914                         DMA_BIT_MASK(32));
 915         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 916                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 917                         DMA_BIT_MASK(32));
 918         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 919                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 920         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 921                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 922         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 923                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 924         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 925                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 926         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 927                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 928                         DMA_BIT_MASK(32));
 929         rtl_write_dword(rtlpriv, REG_RX_DESA,
 930                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 931                         DMA_BIT_MASK(32));
 932
 933         /* if we want to support 64 bit DMA, we should set it here,
 934          * but now we do not support 64 bit DMA
 935          */
 936         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 937
 938         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 939         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 940
 941         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 942                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 943                 bytetmp |= 0x1f;
 944                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 945                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 946         }
 947         _rtl88ee_gen_refresh_led_state(hw);
 948         return true;
 949 }
 950
 951 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 952 {
 953         struct rtl_priv *rtlpriv = rtl_priv(hw);
 954         u8 reg_bw_opmode;
 955         u32 reg_ratr, reg_prsr;
 956
 957         reg_bw_opmode = BW_OPMODE_20MHZ;
 958         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 959             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 960         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 961
 962         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 963         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 964 }
 965
 966 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 967 {
 968         struct rtl_priv *rtlpriv = rtl_priv(hw);
 969         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 970         u8 tmp1byte = 0;
 971         u32 tmp4byte = 0, count = 0;
 972
 973         rtl_write_word(rtlpriv, 0x354, 0x8104);
 974         rtl_write_word(rtlpriv, 0x358, 0x24);
 975
 976         rtl_write_word(rtlpriv, 0x350, 0x70c);
 977         rtl_write_byte(rtlpriv, 0x352, 0x2);
 978         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 979         count = 0;
 980         while (tmp1byte && count < 20) {
 981                 udelay(10);
 982                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 983                 count++;
 984         }
 985         if (0 == tmp1byte) {
 986                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
 987                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
 988                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 989                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 990         }
 991
 992         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 993         count = 0;
 994         while (tmp1byte && count < 20) {
 995                 udelay(10);
 996                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 997                 count++;
 998         }
 999
1000         rtl_write_word(rtlpriv, 0x350, 0x718);
1001         rtl_write_byte(rtlpriv, 0x352, 0x2);
1002         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1003         count = 0;
1004         while (tmp1byte && count < 20) {
1005                 udelay(10);
1006                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1007                 count++;
1008         }
1009
1010         if (ppsc->support_backdoor || (0 == tmp1byte)) {
1011                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1012                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1013                 rtl_write_word(rtlpriv, 0x350, 0xf718);
1014                 rtl_write_byte(rtlpriv, 0x352, 0x1);
1015         }
1016
1017         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1018         count = 0;
1019         while (tmp1byte && count < 20) {
1020                 udelay(10);
1021                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1022                 count++;
1023         }
1024 }
1025
1026 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1027 {
1028         struct rtl_priv *rtlpriv = rtl_priv(hw);
1029         u8 sec_reg_value;
1030
1031         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1032                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1033                   rtlpriv->sec.pairwise_enc_algorithm,
1034                   rtlpriv->sec.group_enc_algorithm);
1035
1036         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1037                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1038                          "not open hw encryption\n");
1039                 return;
1040         }
1041
1042         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1043
1044         if (rtlpriv->sec.use_defaultkey) {
1045                 sec_reg_value |= SCR_TXUSEDK;
1046                 sec_reg_value |= SCR_RXUSEDK;
1047         }
1048
1049         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1050
1051         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1052
1053         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1054                  "The SECR-value %x\n", sec_reg_value);
1055
1056         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1057 }
1058
1059 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1060 {
1061         struct rtl_priv *rtlpriv = rtl_priv(hw);
1062         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1063         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1064         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1065         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1066         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1067         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1068         bool rtstatus = true;
1069         int err = 0;
1070         u8 tmp_u1b, u1byte;
1071         unsigned long flags;
1072
1073         rtlpriv->rtlhal.being_init_adapter = true;
1074         /* As this function can take a very long time (up to 350 ms)
1075          * and can be called with irqs disabled, reenable the irqs
1076          * to let the other devices continue being serviced.
1077          *
1078          * It is safe doing so since our own interrupts will only be enabled
1079          * in a subsequent step.
1080          */
1081         local_save_flags(flags);
1082         local_irq_enable();
1083         rtlhal->fw_ready = false;
1084
1085         rtlpriv->intf_ops->disable_aspm(hw);
1086
1087         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1088         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1089         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1090                 rtlhal->mac_func_enable = true;
1091         } else {
1092                 rtlhal->mac_func_enable = false;
1093                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1094         }
1095
1096         rtstatus = _rtl88ee_init_mac(hw);
1097         if (rtstatus != true) {
1098                 pr_info("Init MAC failed\n");
1099                 err = 1;
1100                 goto exit;
1101         }
1102
1103         err = rtl88e_download_fw(hw, false);
1104         if (err) {
1105                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1106                          "Failed to download FW. Init HW without FW now..\n");
1107                 err = 1;
1108                 goto exit;
1109         }
1110         rtlhal->fw_ready = true;
1111         /*fw related variable initialize */
1112         rtlhal->last_hmeboxnum = 0;
1113         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1114         rtlhal->fw_clk_change_in_progress = false;
1115         rtlhal->allow_sw_to_change_hwclc = false;
1116         ppsc->fw_current_inpsmode = false;
1117
1118         rtl88e_phy_mac_config(hw);
1119         /* because last function modify RCR, so we update
1120          * rcr var here, or TP will unstable for receive_config
1121          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1122          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1123          */
1124         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1125         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1126
1127         rtl88e_phy_bb_config(hw);
1128         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1129         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1130
1131         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1132         rtl88e_phy_rf_config(hw);
1133
1134         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1135                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1136         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1137
1138         _rtl88ee_hw_configure(hw);
1139         rtl_cam_reset_all_entry(hw);
1140         rtl88ee_enable_hw_security_config(hw);
1141
1142         rtlhal->mac_func_enable = true;
1143         ppsc->rfpwr_state = ERFON;
1144
1145         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1146         _rtl88ee_enable_aspm_back_door(hw);
1147         rtlpriv->intf_ops->enable_aspm(hw);
1148
1149         if (ppsc->rfpwr_state == ERFON) {
1150                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1151                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1152                      (rtlhal->oem_id == RT_CID_819X_HP))) {
1153                         rtl88e_phy_set_rfpath_switch(hw, true);
1154                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1155                 } else {
1156                         rtl88e_phy_set_rfpath_switch(hw, false);
1157                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1158                 }
1159                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1160                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1161                          ("MAIN_ANT") : ("AUX_ANT"));
1162
1163                 if (rtlphy->iqk_initialized) {
1164                         rtl88e_phy_iq_calibrate(hw, true);
1165                 } else {
1166                         rtl88e_phy_iq_calibrate(hw, false);
1167                         rtlphy->iqk_initialized = true;
1168                 }
1169
1170                 rtl88e_dm_check_txpower_tracking(hw);
1171                 rtl88e_phy_lc_calibrate(hw);
1172         }
1173
1174         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1175         if (!(tmp_u1b & BIT(0))) {
1176                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1177                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1178         }
1179
1180         if (!(tmp_u1b & BIT(4))) {
1181                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1182                 tmp_u1b &= 0x0F;
1183                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1184                 udelay(10);
1185                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1186                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1187         }
1188         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1189         rtl88e_dm_init(hw);
1190 exit:
1191         local_irq_restore(flags);
1192         rtlpriv->rtlhal.being_init_adapter = false;
1193         return err;
1194 }
1195
1196 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1197 {
1198         struct rtl_priv *rtlpriv = rtl_priv(hw);
1199         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1200         enum version_8188e version = VERSION_UNKNOWN;
1201         u32 value32;
1202
1203         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1204         if (value32 & TRP_VAUX_EN) {
1205                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1206         } else {
1207                 version = NORMAL_CHIP;
1208                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1209                 version = version | ((value32 & VENDOR_ID) ?
1210                           CHIP_VENDOR_UMC : 0);
1211         }
1212
1213         rtlphy->rf_type = RF_1T1R;
1214         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1215                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1216                  "RF_2T2R" : "RF_1T1R");
1217
1218         return version;
1219 }
1220
1221 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1222                                      enum nl80211_iftype type)
1223 {
1224         struct rtl_priv *rtlpriv = rtl_priv(hw);
1225         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1226         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1227         u8 mode = MSR_NOLINK;
1228
1229         switch (type) {
1230         case NL80211_IFTYPE_UNSPECIFIED:
1231                 mode = MSR_NOLINK;
1232                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1233                          "Set Network type to NO LINK!\n");
1234                 break;
1235         case NL80211_IFTYPE_ADHOC:
1236         case NL80211_IFTYPE_MESH_POINT:
1237                 mode = MSR_ADHOC;
1238                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1239                          "Set Network type to Ad Hoc!\n");
1240                 break;
1241         case NL80211_IFTYPE_STATION:
1242                 mode = MSR_INFRA;
1243                 ledaction = LED_CTL_LINK;
1244                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1245                          "Set Network type to STA!\n");
1246                 break;
1247         case NL80211_IFTYPE_AP:
1248                 mode = MSR_AP;
1249                 ledaction = LED_CTL_LINK;
1250                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1251                          "Set Network type to AP!\n");
1252                 break;
1253         default:
1254                 pr_err("Network type %d not support!\n", type);
1255                 return 1;
1256                 break;
1257         }
1258
1259         /* MSR_INFRA == Link in infrastructure network;
1260          * MSR_ADHOC == Link in ad hoc network;
1261          * Therefore, check link state is necessary.
1262          *
1263          * MSR_AP == AP mode; link state is not cared here.
1264          */
1265         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1266                 mode = MSR_NOLINK;
1267                 ledaction = LED_CTL_NO_LINK;
1268         }
1269
1270         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1271                 _rtl88ee_stop_tx_beacon(hw);
1272                 _rtl88ee_enable_bcn_sub_func(hw);
1273         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1274                 _rtl88ee_resume_tx_beacon(hw);
1275                 _rtl88ee_disable_bcn_sub_func(hw);
1276         } else {
1277                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1278                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1279                          mode);
1280         }
1281
1282         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1283         rtlpriv->cfg->ops->led_control(hw, ledaction);
1284         if (mode == MSR_AP)
1285                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1286         else
1287                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1288         return 0;
1289 }
1290
1291 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1292 {
1293         struct rtl_priv *rtlpriv = rtl_priv(hw);
1294         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1295         u32 reg_rcr = rtlpci->receive_config;
1296
1297         if (rtlpriv->psc.rfpwr_state != ERFON)
1298                 return;
1299
1300         if (check_bssid == true) {
1301                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1302                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1303                                               (u8 *)(&reg_rcr));
1304                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1305         } else if (check_bssid == false) {
1306                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1307                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1308                 rtlpriv->cfg->ops->set_hw_reg(hw,
1309                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1310         }
1311
1312 }
1313
1314 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1315                              enum nl80211_iftype type)
1316 {
1317         struct rtl_priv *rtlpriv = rtl_priv(hw);
1318
1319         if (_rtl88ee_set_media_status(hw, type))
1320                 return -EOPNOTSUPP;
1321
1322         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1323                 if (type != NL80211_IFTYPE_AP &&
1324                     type != NL80211_IFTYPE_MESH_POINT)
1325                         rtl88ee_set_check_bssid(hw, true);
1326         } else {
1327                 rtl88ee_set_check_bssid(hw, false);
1328         }
1329
1330         return 0;
1331 }
1332
1333 /* don't set REG_EDCA_BE_PARAM here
1334  * because mac80211 will send pkt when scan
1335  */
1336 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1337 {
1338         struct rtl_priv *rtlpriv = rtl_priv(hw);
1339         rtl88e_dm_init_edca_turbo(hw);
1340         switch (aci) {
1341         case AC1_BK:
1342                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1343                 break;
1344         case AC0_BE:
1345                 break;
1346         case AC2_VI:
1347                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1348                 break;
1349         case AC3_VO:
1350                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1351                 break;
1352         default:
1353                 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);
1354                 break;
1355         }
1356 }
1357
1358 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1359 {
1360         struct rtl_priv *rtlpriv = rtl_priv(hw);
1361         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1362
1363         rtl_write_dword(rtlpriv, REG_HIMR,
1364                         rtlpci->irq_mask[0] & 0xFFFFFFFF);
1365         rtl_write_dword(rtlpriv, REG_HIMRE,
1366                         rtlpci->irq_mask[1] & 0xFFFFFFFF);
1367         rtlpci->irq_enabled = true;
1368         /* there are some C2H CMDs have been sent
1369          * before system interrupt is enabled, e.g., C2H, CPWM.
1370          * So we need to clear all C2H events that FW has notified,
1371          * otherwise FW won't schedule any commands anymore.
1372          */
1373         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1374         /*enable system interrupt*/
1375         rtl_write_dword(rtlpriv, REG_HSIMR,
1376                         rtlpci->sys_irq_mask & 0xFFFFFFFF);
1377 }
1378
1379 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1380 {
1381         struct rtl_priv *rtlpriv = rtl_priv(hw);
1382         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1383
1384         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1385         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1386         rtlpci->irq_enabled = false;
1387         /*synchronize_irq(rtlpci->pdev->irq);*/
1388 }
1389
1390 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1391 {
1392         struct rtl_priv *rtlpriv = rtl_priv(hw);
1393         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1394         u8 u1b_tmp;
1395         u32 count = 0;
1396         rtlhal->mac_func_enable = false;
1397         rtlpriv->intf_ops->enable_aspm(hw);
1398
1399         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1400         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1401         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1402
1403         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1404         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1405                 udelay(10);
1406                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1407                 count++;
1408         }
1409         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1410
1411         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1412                                  PWR_INTF_PCI_MSK,
1413                                  RTL8188EE_NIC_LPS_ENTER_FLOW);
1414
1415         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1416
1417         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1418                 rtl88e_firmware_selfreset(hw);
1419
1420         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1421         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1422         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1423
1424         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1425         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1426
1427         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1428                                  PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1429
1430         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1431         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1432         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1433         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1434
1435         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1436
1437         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1438         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1439         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1440
1441         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1442         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1443         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1444         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1445
1446         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1447 }
1448
1449 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1450 {
1451         struct rtl_priv *rtlpriv = rtl_priv(hw);
1452         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1453         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1454         enum nl80211_iftype opmode;
1455
1456         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1457
1458         mac->link_state = MAC80211_NOLINK;
1459         opmode = NL80211_IFTYPE_UNSPECIFIED;
1460
1461         _rtl88ee_set_media_status(hw, opmode);
1462
1463         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1464             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1465                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1466
1467         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1468         _rtl88ee_poweroff_adapter(hw);
1469
1470         /* after power off we should do iqk again */
1471         rtlpriv->phy.iqk_initialized = false;
1472 }
1473
1474 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1475                                   struct rtl_int *intvec)
1476 {
1477         struct rtl_priv *rtlpriv = rtl_priv(hw);
1478         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1479
1480         intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1481         rtl_write_dword(rtlpriv, ISR, intvec->inta);
1482
1483         intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1484         rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1485
1486 }
1487
1488 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1489 {
1490         struct rtl_priv *rtlpriv = rtl_priv(hw);
1491         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1492         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1493         u16 bcn_interval, atim_window;
1494
1495         bcn_interval = mac->beacon_interval;
1496         atim_window = 2;        /*FIX MERGE */
1497         rtl88ee_disable_interrupt(hw);
1498         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1499         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1500         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1501         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1502         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1503         rtl_write_byte(rtlpriv, 0x606, 0x30);
1504         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1505         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1506         /*rtl88ee_enable_interrupt(hw);*/
1507 }
1508
1509 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1510 {
1511         struct rtl_priv *rtlpriv = rtl_priv(hw);
1512         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1513         u16 bcn_interval = mac->beacon_interval;
1514
1515         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1516                  "beacon_interval:%d\n", bcn_interval);
1517         /*rtl88ee_disable_interrupt(hw);*/
1518         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1519         /*rtl88ee_enable_interrupt(hw);*/
1520 }
1521
1522 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1523                                    u32 add_msr, u32 rm_msr)
1524 {
1525         struct rtl_priv *rtlpriv = rtl_priv(hw);
1526         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1527
1528         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1529                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1530
1531         if (add_msr)
1532                 rtlpci->irq_mask[0] |= add_msr;
1533         if (rm_msr)
1534                 rtlpci->irq_mask[0] &= (~rm_msr);
1535         rtl88ee_disable_interrupt(hw);
1536         rtl88ee_enable_interrupt(hw);
1537 }
1538
1539 static u8 _rtl88e_get_chnl_group(u8 chnl)
1540 {
1541         u8 group = 0;
1542
1543         if (chnl < 3)
1544                 group = 0;
1545         else if (chnl < 6)
1546                 group = 1;
1547         else if (chnl < 9)
1548                 group = 2;
1549         else if (chnl < 12)
1550                 group = 3;
1551         else if (chnl < 14)
1552                 group = 4;
1553         else if (chnl == 14)
1554                 group = 5;
1555
1556         return group;
1557 }
1558
1559 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1560 {
1561         int group, txcnt;
1562
1563         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1564                 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1565                 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1566         }
1567         for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1568                 if (txcnt == 0) {
1569                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1570                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1571                 } else {
1572                         pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1573                         pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1574                         pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1575                         pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1576                 }
1577         }
1578 }
1579
1580 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1581                                       struct txpower_info_2g *pwrinfo24g,
1582                                       struct txpower_info_5g *pwrinfo5g,
1583                                       bool autoload_fail, u8 *hwinfo)
1584 {
1585         struct rtl_priv *rtlpriv = rtl_priv(hw);
1586         u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1587
1588         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1589                  "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1590                  (eeaddr+1), hwinfo[eeaddr+1]);
1591         if (0xFF == hwinfo[eeaddr+1])  /*YJ,add,120316*/
1592                 autoload_fail = true;
1593
1594         if (autoload_fail) {
1595                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1596                          "auto load fail : Use Default value!\n");
1597                 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1598                         /* 2.4G default value */
1599                         set_24g_base(pwrinfo24g, rfpath);
1600                 }
1601                 return;
1602         }
1603
1604         for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1605                 /*2.4G default value*/
1606                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1607                         pwrinfo24g->index_cck_base[rfpath][group] =
1608                           hwinfo[eeaddr++];
1609                         if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1610                                 pwrinfo24g->index_cck_base[rfpath][group] =
1611                                   0x2D;
1612                 }
1613                 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1614                         pwrinfo24g->index_bw40_base[rfpath][group] =
1615                                 hwinfo[eeaddr++];
1616                         if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1617                                 pwrinfo24g->index_bw40_base[rfpath][group] =
1618                                         0x2D;
1619                 }
1620                 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1621                 if (hwinfo[eeaddr] == 0xFF) {
1622                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1623                 } else {
1624                         pwrinfo24g->bw20_diff[rfpath][0] =
1625                                 (hwinfo[eeaddr]&0xf0)>>4;
1626                         /*bit sign number to 8 bit sign number*/
1627                         if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1628                                 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1629                 }
1630
1631                 if (hwinfo[eeaddr] == 0xFF) {
1632                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1633                 } else {
1634                         pwrinfo24g->ofdm_diff[rfpath][0] =
1635                                 (hwinfo[eeaddr]&0x0f);
1636                                 /*bit sign number to 8 bit sign number*/
1637                         if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1638                                 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1639                 }
1640                 pwrinfo24g->cck_diff[rfpath][0] = 0;
1641                 eeaddr++;
1642                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1643                         if (hwinfo[eeaddr] == 0xFF) {
1644                                 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1645                         } else {
1646                                 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1647                                   (hwinfo[eeaddr]&0xf0)>>4;
1648                                 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1649                                     BIT(3))
1650                                         pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1651                                           0xF0;
1652                         }
1653
1654                         if (hwinfo[eeaddr] == 0xFF) {
1655                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1656                                         0xFE;
1657                         } else {
1658                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1659                                   (hwinfo[eeaddr]&0x0f);
1660                                 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1661                                     BIT(3))
1662                                         pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1663                                           0xF0;
1664                         }
1665                         eeaddr++;
1666
1667                         if (hwinfo[eeaddr] == 0xFF) {
1668                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1669                         } else {
1670                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1671                                   (hwinfo[eeaddr]&0xf0)>>4;
1672                                 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1673                                     BIT(3))
1674                                         pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1675                                           0xF0;
1676                         }
1677
1678                         if (hwinfo[eeaddr] == 0xFF) {
1679                                 pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1680                         } else {
1681                                 pwrinfo24g->cck_diff[rfpath][txcnt] =
1682                                   (hwinfo[eeaddr]&0x0f);
1683                                 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1684                                     BIT(3))
1685                                         pwrinfo24g->cck_diff[rfpath][txcnt] |=
1686                                           0xF0;
1687                         }
1688                         eeaddr++;
1689                 }
1690
1691                 /*5G default value*/
1692                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1693                         pwrinfo5g->index_bw40_base[rfpath][group] =
1694                                 hwinfo[eeaddr++];
1695                         if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1696                                 pwrinfo5g->index_bw40_base[rfpath][group] =
1697                                   0xFE;
1698                 }
1699
1700                 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1701
1702                 if (hwinfo[eeaddr] == 0xFF) {
1703                         pwrinfo5g->bw20_diff[rfpath][0] = 0;
1704                 } else {
1705                         pwrinfo5g->bw20_diff[rfpath][0] =
1706                           (hwinfo[eeaddr]&0xf0)>>4;
1707                         if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1708                                 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1709                 }
1710
1711                 if (hwinfo[eeaddr] == 0xFF) {
1712                         pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1713                 } else {
1714                         pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1715                         if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1716                                 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1717                 }
1718                 eeaddr++;
1719                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1720                         if (hwinfo[eeaddr] == 0xFF) {
1721                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =   0xFE;
1722                         } else {
1723                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1724                                   (hwinfo[eeaddr]&0xf0)>>4;
1725                                 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1726                                     BIT(3))
1727                                         pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1728                                           0xF0;
1729                         }
1730
1731                         if (hwinfo[eeaddr] == 0xFF) {
1732                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =   0xFE;
1733                         } else {
1734                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1735                                   (hwinfo[eeaddr]&0x0f);
1736                                 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1737                                     BIT(3))
1738                                         pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1739                                           0xF0;
1740                         }
1741                         eeaddr++;
1742                 }
1743
1744                 if (hwinfo[eeaddr] == 0xFF) {
1745                         pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1746                         pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1747                 } else {
1748                         pwrinfo5g->ofdm_diff[rfpath][1] =
1749                                         (hwinfo[eeaddr]&0xf0)>>4;
1750                         pwrinfo5g->ofdm_diff[rfpath][2] =
1751                                         (hwinfo[eeaddr]&0x0f);
1752                 }
1753                 eeaddr++;
1754
1755                 if (hwinfo[eeaddr] == 0xFF)
1756                         pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1757                 else
1758                         pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1759                 eeaddr++;
1760
1761                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1762                         if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1763                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] =   0xFE;
1764                         else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1765                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1766                 }
1767         }
1768 }
1769
1770 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1771                                                  bool autoload_fail,
1772                                                  u8 *hwinfo)
1773 {
1774         struct rtl_priv *rtlpriv = rtl_priv(hw);
1775         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1776         struct txpower_info_2g pwrinfo24g;
1777         struct txpower_info_5g pwrinfo5g;
1778         u8 rf_path, index;
1779         u8 i;
1780
1781         read_power_value_fromprom(hw, &pwrinfo24g,
1782                                   &pwrinfo5g, autoload_fail, hwinfo);
1783
1784         for (rf_path = 0; rf_path < 2; rf_path++) {
1785                 for (i = 0; i < 14; i++) {
1786                         index = _rtl88e_get_chnl_group(i+1);
1787
1788                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1789                                 pwrinfo24g.index_cck_base[rf_path][index];
1790                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1791                                 pwrinfo24g.index_bw40_base[rf_path][index];
1792                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1793                                 pwrinfo24g.bw20_diff[rf_path][0];
1794                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1795                                 pwrinfo24g.ofdm_diff[rf_path][0];
1796                 }
1797
1798                 for (i = 0; i < 14; i++) {
1799                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1800                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1801                                 rf_path, i,
1802                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1803                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1804                 }
1805         }
1806
1807         if (!autoload_fail)
1808                 rtlefuse->eeprom_thermalmeter =
1809                         hwinfo[EEPROM_THERMAL_METER_88E];
1810         else
1811                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1812
1813         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1814                 rtlefuse->apk_thermalmeterignore = true;
1815                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1816         }
1817
1818         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1819         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1820                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1821
1822         if (!autoload_fail) {
1823                 rtlefuse->eeprom_regulatory =
1824                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1825                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1826                         rtlefuse->eeprom_regulatory = 0;
1827         } else {
1828                 rtlefuse->eeprom_regulatory = 0;
1829         }
1830         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1831                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1832 }
1833
1834 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1835 {
1836         struct rtl_priv *rtlpriv = rtl_priv(hw);
1837         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1838         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1839         int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1840                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1841                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1842                         COUNTRY_CODE_WORLD_WIDE_13};
1843         u8 *hwinfo;
1844
1845         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1846         if (!hwinfo)
1847                 return;
1848
1849         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1850                 goto exit;
1851
1852         if (rtlefuse->eeprom_oemid == 0xFF)
1853                 rtlefuse->eeprom_oemid = 0;
1854
1855         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1856                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1857         /* set channel plan from efuse */
1858         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1859         /*tx power*/
1860         _rtl88ee_read_txpower_info_from_hwpg(hw,
1861                                              rtlefuse->autoload_failflag,
1862                                              hwinfo);
1863         rtlefuse->txpwr_fromeprom = true;
1864
1865         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1866                                                  rtlefuse->autoload_failflag,
1867                                                  hwinfo);
1868
1869         /*board type*/
1870         rtlefuse->board_type =
1871                 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1872         rtlhal->board_type = rtlefuse->board_type;
1873         /*Wake on wlan*/
1874         rtlefuse->wowlan_enable =
1875                 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1876         /*parse xtal*/
1877         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1878         if (hwinfo[EEPROM_XTAL_88E])
1879                 rtlefuse->crystalcap = 0x20;
1880         /*antenna diversity*/
1881         rtlefuse->antenna_div_cfg =
1882                 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1883         if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1884                 rtlefuse->antenna_div_cfg = 0;
1885         if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1886             rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1887                 rtlefuse->antenna_div_cfg = 0;
1888
1889         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1890         if (rtlefuse->antenna_div_type == 0xFF)
1891                 rtlefuse->antenna_div_type = 0x01;
1892         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1893                 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1894                 rtlefuse->antenna_div_cfg = 1;
1895
1896         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1897                 switch (rtlefuse->eeprom_oemid) {
1898                 case EEPROM_CID_DEFAULT:
1899                         if (rtlefuse->eeprom_did == 0x8179) {
1900                                 if (rtlefuse->eeprom_svid == 0x1025) {
1901                                         rtlhal->oem_id = RT_CID_819X_ACER;
1902                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1903                                      rtlefuse->eeprom_smid == 0x0179) ||
1904                                      (rtlefuse->eeprom_svid == 0x17AA &&
1905                                      rtlefuse->eeprom_smid == 0x0179)) {
1906                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1907                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1908                                            rtlefuse->eeprom_smid == 0x197d) {
1909                                         rtlhal->oem_id = RT_CID_819X_HP;
1910                                 } else {
1911                                         rtlhal->oem_id = RT_CID_DEFAULT;
1912                                 }
1913                         } else {
1914                                 rtlhal->oem_id = RT_CID_DEFAULT;
1915                         }
1916                         break;
1917                 case EEPROM_CID_TOSHIBA:
1918                         rtlhal->oem_id = RT_CID_TOSHIBA;
1919                         break;
1920                 case EEPROM_CID_QMI:
1921                         rtlhal->oem_id = RT_CID_819X_QMI;
1922                         break;
1923                 case EEPROM_CID_WHQL:
1924                 default:
1925                         rtlhal->oem_id = RT_CID_DEFAULT;
1926                         break;
1927
1928                 }
1929         }
1930 exit:
1931         kfree(hwinfo);
1932 }
1933
1934 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1935 {
1936         struct rtl_priv *rtlpriv = rtl_priv(hw);
1937         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1938
1939         rtlpriv->ledctl.led_opendrain = true;
1940
1941         switch (rtlhal->oem_id) {
1942         case RT_CID_819X_HP:
1943                 rtlpriv->ledctl.led_opendrain = true;
1944                 break;
1945         case RT_CID_819X_LENOVO:
1946         case RT_CID_DEFAULT:
1947         case RT_CID_TOSHIBA:
1948         case RT_CID_CCX:
1949         case RT_CID_819X_ACER:
1950         case RT_CID_WHQL:
1951         default:
1952                 break;
1953         }
1954         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1955                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1956 }
1957
1958 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1959 {
1960         struct rtl_priv *rtlpriv = rtl_priv(hw);
1961         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1962         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1963         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1964         u8 tmp_u1b;
1965
1966         rtlhal->version = _rtl88ee_read_chip_version(hw);
1967         if (get_rf_type(rtlphy) == RF_1T1R)
1968                 rtlpriv->dm.rfpath_rxenable[0] = true;
1969         else
1970                 rtlpriv->dm.rfpath_rxenable[0] =
1971                     rtlpriv->dm.rfpath_rxenable[1] = true;
1972         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1973                                                 rtlhal->version);
1974         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1975         if (tmp_u1b & BIT(4)) {
1976                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1977                 rtlefuse->epromtype = EEPROM_93C46;
1978         } else {
1979                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1980                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1981         }
1982         if (tmp_u1b & BIT(5)) {
1983                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1984                 rtlefuse->autoload_failflag = false;
1985                 _rtl88ee_read_adapter_info(hw);
1986         } else {
1987                 pr_err("Autoload ERR!!\n");
1988         }
1989         _rtl88ee_hal_customized_behavior(hw);
1990 }
1991
1992 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1993                 struct ieee80211_sta *sta)
1994 {
1995         struct rtl_priv *rtlpriv = rtl_priv(hw);
1996         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1997         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1998         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1999         u32 ratr_value;
2000         u8 ratr_index = 0;
2001         u8 b_nmode = mac->ht_enable;
2002         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2003         u16 shortgi_rate;
2004         u32 tmp_ratr_value;
2005         u8 curtxbw_40mhz = mac->bw_40;
2006         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2007                                 1 : 0;
2008         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2009                                 1 : 0;
2010         enum wireless_mode wirelessmode = mac->mode;
2011         u32 ratr_mask;
2012
2013         if (rtlhal->current_bandtype == BAND_ON_5G)
2014                 ratr_value = sta->supp_rates[1] << 4;
2015         else
2016                 ratr_value = sta->supp_rates[0];
2017         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2018                 ratr_value = 0xfff;
2019         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2020                        sta->ht_cap.mcs.rx_mask[0] << 12);
2021         switch (wirelessmode) {
2022         case WIRELESS_MODE_B:
2023                 if (ratr_value & 0x0000000c)
2024                         ratr_value &= 0x0000000d;
2025                 else
2026                         ratr_value &= 0x0000000f;
2027                 break;
2028         case WIRELESS_MODE_G:
2029                 ratr_value &= 0x00000FF5;
2030                 break;
2031         case WIRELESS_MODE_N_24G:
2032         case WIRELESS_MODE_N_5G:
2033                 b_nmode = 1;
2034                 if (get_rf_type(rtlphy) == RF_1T2R ||
2035                     get_rf_type(rtlphy) == RF_1T1R)
2036                         ratr_mask = 0x000ff005;
2037                 else
2038                         ratr_mask = 0x0f0ff005;
2039
2040                 ratr_value &= ratr_mask;
2041                 break;
2042         default:
2043                 if (rtlphy->rf_type == RF_1T2R)
2044                         ratr_value &= 0x000ff0ff;
2045                 else
2046                         ratr_value &= 0x0f0ff0ff;
2047
2048                 break;
2049         }
2050
2051         if ((rtlpriv->btcoexist.bt_coexistence) &&
2052             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2053             (rtlpriv->btcoexist.bt_cur_state) &&
2054             (rtlpriv->btcoexist.bt_ant_isolation) &&
2055             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2056              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2057                 ratr_value &= 0x0fffcfc0;
2058         else
2059                 ratr_value &= 0x0FFFFFFF;
2060
2061         if (b_nmode &&
2062             ((curtxbw_40mhz && curshortgi_40mhz) ||
2063              (!curtxbw_40mhz && curshortgi_20mhz))) {
2064                 ratr_value |= 0x10000000;
2065                 tmp_ratr_value = (ratr_value >> 12);
2066
2067                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2068                         if ((1 << shortgi_rate) & tmp_ratr_value)
2069                                 break;
2070                 }
2071
2072                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2073                     (shortgi_rate << 4) | (shortgi_rate);
2074         }
2075
2076         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2077
2078         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2079                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2080 }
2081
2082 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2083                 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2084 {
2085         struct rtl_priv *rtlpriv = rtl_priv(hw);
2086         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2087         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2088         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2089         struct rtl_sta_info *sta_entry = NULL;
2090         u32 ratr_bitmap;
2091         u8 ratr_index;
2092         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2093                                 ? 1 : 0;
2094         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2095                                 1 : 0;
2096         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2097                                 1 : 0;
2098         enum wireless_mode wirelessmode = 0;
2099         bool b_shortgi = false;
2100         u8 rate_mask[5];
2101         u8 macid = 0;
2102         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2103
2104         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2105         wirelessmode = sta_entry->wireless_mode;
2106         if (mac->opmode == NL80211_IFTYPE_STATION ||
2107                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2108                 curtxbw_40mhz = mac->bw_40;
2109         else if (mac->opmode == NL80211_IFTYPE_AP ||
2110                 mac->opmode == NL80211_IFTYPE_ADHOC)
2111                 macid = sta->aid + 1;
2112
2113         if (rtlhal->current_bandtype == BAND_ON_5G)
2114                 ratr_bitmap = sta->supp_rates[1] << 4;
2115         else
2116                 ratr_bitmap = sta->supp_rates[0];
2117         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2118                 ratr_bitmap = 0xfff;
2119         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2120                         sta->ht_cap.mcs.rx_mask[0] << 12);
2121         switch (wirelessmode) {
2122         case WIRELESS_MODE_B:
2123                 ratr_index = RATR_INX_WIRELESS_B;
2124                 if (ratr_bitmap & 0x0000000c)
2125                         ratr_bitmap &= 0x0000000d;
2126                 else
2127                         ratr_bitmap &= 0x0000000f;
2128                 break;
2129         case WIRELESS_MODE_G:
2130                 ratr_index = RATR_INX_WIRELESS_GB;
2131
2132                 if (rssi_level == 1)
2133                         ratr_bitmap &= 0x00000f00;
2134                 else if (rssi_level == 2)
2135                         ratr_bitmap &= 0x00000ff0;
2136                 else
2137                         ratr_bitmap &= 0x00000ff5;
2138                 break;
2139         case WIRELESS_MODE_N_24G:
2140         case WIRELESS_MODE_N_5G:
2141                 ratr_index = RATR_INX_WIRELESS_NGB;
2142                 if (rtlphy->rf_type == RF_1T2R ||
2143                     rtlphy->rf_type == RF_1T1R) {
2144                         if (curtxbw_40mhz) {
2145                                 if (rssi_level == 1)
2146                                         ratr_bitmap &= 0x000f0000;
2147                                 else if (rssi_level == 2)
2148                                         ratr_bitmap &= 0x000ff000;
2149                                 else
2150                                         ratr_bitmap &= 0x000ff015;
2151                         } else {
2152                                 if (rssi_level == 1)
2153                                         ratr_bitmap &= 0x000f0000;
2154                                 else if (rssi_level == 2)
2155                                         ratr_bitmap &= 0x000ff000;
2156                                 else
2157                                         ratr_bitmap &= 0x000ff005;
2158                         }
2159                 } else {
2160                         if (curtxbw_40mhz) {
2161                                 if (rssi_level == 1)
2162                                         ratr_bitmap &= 0x0f8f0000;
2163                                 else if (rssi_level == 2)
2164                                         ratr_bitmap &= 0x0f8ff000;
2165                                 else
2166                                         ratr_bitmap &= 0x0f8ff015;
2167                         } else {
2168                                 if (rssi_level == 1)
2169                                         ratr_bitmap &= 0x0f8f0000;
2170                                 else if (rssi_level == 2)
2171                                         ratr_bitmap &= 0x0f8ff000;
2172                                 else
2173                                         ratr_bitmap &= 0x0f8ff005;
2174                         }
2175                 }
2176                 /*}*/
2177
2178                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2179                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2180
2181                         if (macid == 0)
2182                                 b_shortgi = true;
2183                         else if (macid == 1)
2184                                 b_shortgi = false;
2185                 }
2186                 break;
2187         default:
2188                 ratr_index = RATR_INX_WIRELESS_NGB;
2189
2190                 if (rtlphy->rf_type == RF_1T2R)
2191                         ratr_bitmap &= 0x000ff0ff;
2192                 else
2193                         ratr_bitmap &= 0x0f0ff0ff;
2194                 break;
2195         }
2196         sta_entry->ratr_index = ratr_index;
2197
2198         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2199                  "ratr_bitmap :%x\n", ratr_bitmap);
2200         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2201                              (ratr_index << 28);
2202         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2203         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2204                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2205                  ratr_index, ratr_bitmap,
2206                  rate_mask[0], rate_mask[1],
2207                  rate_mask[2], rate_mask[3],
2208                  rate_mask[4]);
2209         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2210         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2211 }
2212
2213 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2214                 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2215 {
2216         struct rtl_priv *rtlpriv = rtl_priv(hw);
2217
2218         if (rtlpriv->dm.useramask)
2219                 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2220         else
2221                 rtl88ee_update_hal_rate_table(hw, sta);
2222 }
2223
2224 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2225 {
2226         struct rtl_priv *rtlpriv = rtl_priv(hw);
2227         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2228         u16 sifs_timer;
2229
2230         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2231         if (!mac->ht_enable)
2232                 sifs_timer = 0x0a0a;
2233         else
2234                 sifs_timer = 0x0e0e;
2235         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2236 }
2237
2238 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2239 {
2240         struct rtl_priv *rtlpriv = rtl_priv(hw);
2241         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2242         enum rf_pwrstate e_rfpowerstate_toset;
2243         u32 u4tmp;
2244         bool b_actuallyset = false;
2245
2246         if (rtlpriv->rtlhal.being_init_adapter)
2247                 return false;
2248
2249         if (ppsc->swrf_processing)
2250                 return false;
2251
2252         spin_lock(&rtlpriv->locks.rf_ps_lock);
2253         if (ppsc->rfchange_inprogress) {
2254                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2255                 return false;
2256         } else {
2257                 ppsc->rfchange_inprogress = true;
2258                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2259         }
2260
2261         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2262         e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2263
2264         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2265                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2266                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2267
2268                 e_rfpowerstate_toset = ERFON;
2269                 ppsc->hwradiooff = false;
2270                 b_actuallyset = true;
2271         } else if ((!ppsc->hwradiooff) &&
2272                    (e_rfpowerstate_toset == ERFOFF)) {
2273                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2274                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2275
2276                 e_rfpowerstate_toset = ERFOFF;
2277                 ppsc->hwradiooff = true;
2278                 b_actuallyset = true;
2279         }
2280
2281         if (b_actuallyset) {
2282                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2283                 ppsc->rfchange_inprogress = false;
2284                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2285         } else {
2286                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2287                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2288
2289                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2290                 ppsc->rfchange_inprogress = false;
2291                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2292         }
2293
2294         *valid = 1;
2295         return !ppsc->hwradiooff;
2296
2297 }
2298
2299 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2300                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2301                      bool is_wepkey, bool clear_all)
2302 {
2303         struct rtl_priv *rtlpriv = rtl_priv(hw);
2304         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2305         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2306         u8 *macaddr = p_macaddr;
2307         u32 entry_id = 0;
2308         bool is_pairwise = false;
2309         static u8 cam_const_addr[4][6] = {
2310                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2311                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2312                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2313                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2314         };
2315         static u8 cam_const_broad[] = {
2316                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2317         };
2318
2319         if (clear_all) {
2320                 u8 idx = 0;
2321                 u8 cam_offset = 0;
2322                 u8 clear_number = 5;
2323
2324                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2325
2326                 for (idx = 0; idx < clear_number; idx++) {
2327                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2328                         rtl_cam_empty_entry(hw, cam_offset + idx);
2329
2330                         if (idx < 5) {
2331                                 memset(rtlpriv->sec.key_buf[idx], 0,
2332                                        MAX_KEY_LEN);
2333                                 rtlpriv->sec.key_len[idx] = 0;
2334                         }
2335                 }
2336
2337         } else {
2338                 switch (enc_algo) {
2339                 case WEP40_ENCRYPTION:
2340                         enc_algo = CAM_WEP40;
2341                         break;
2342                 case WEP104_ENCRYPTION:
2343                         enc_algo = CAM_WEP104;
2344                         break;
2345                 case TKIP_ENCRYPTION:
2346                         enc_algo = CAM_TKIP;
2347                         break;
2348                 case AESCCMP_ENCRYPTION:
2349                         enc_algo = CAM_AES;
2350                         break;
2351                 default:
2352                         pr_err("switch case %#x not processed\n",
2353                                enc_algo);
2354                         enc_algo = CAM_TKIP;
2355                         break;
2356                 }
2357
2358                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2359                         macaddr = cam_const_addr[key_index];
2360                         entry_id = key_index;
2361                 } else {
2362                         if (is_group) {
2363                                 macaddr = cam_const_broad;
2364                                 entry_id = key_index;
2365                         } else {
2366                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2367                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2368                                         entry_id =
2369                                           rtl_cam_get_free_entry(hw, p_macaddr);
2370                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2371                                                 pr_err("Can not find free hw security cam entry\n");
2372                                                 return;
2373                                         }
2374                                 } else {
2375                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2376                                 }
2377                                 key_index = PAIRWISE_KEYIDX;
2378                                 is_pairwise = true;
2379                         }
2380                 }
2381
2382                 if (rtlpriv->sec.key_len[key_index] == 0) {
2383                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2384                                  "delete one entry, entry_id is %d\n",
2385                                  entry_id);
2386                         if (mac->opmode == NL80211_IFTYPE_AP ||
2387                                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2388                                 rtl_cam_del_entry(hw, p_macaddr);
2389                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2390                 } else {
2391                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2392                                  "add one entry\n");
2393                         if (is_pairwise) {
2394                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2395                                          "set Pairwise key\n");
2396
2397                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2398                                                       entry_id, enc_algo,
2399                                                       CAM_CONFIG_NO_USEDK,
2400                                                       rtlpriv->sec.key_buf[key_index]);
2401                         } else {
2402                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2403                                          "set group key\n");
2404
2405                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2406                                         rtl_cam_add_one_entry(hw,
2407                                                         rtlefuse->dev_addr,
2408                                                         PAIRWISE_KEYIDX,
2409                                                         CAM_PAIRWISE_KEY_POSITION,
2410                                                         enc_algo,
2411                                                         CAM_CONFIG_NO_USEDK,
2412                                                         rtlpriv->sec.key_buf
2413                                                         [entry_id]);
2414                                 }
2415
2416                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2417                                                       entry_id, enc_algo,
2418                                                       CAM_CONFIG_NO_USEDK,
2419                                                       rtlpriv->sec.key_buf[entry_id]);
2420                         }
2421
2422                 }
2423         }
2424 }
2425
2426 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2427 {
2428         struct rtl_priv *rtlpriv = rtl_priv(hw);
2429
2430         rtlpriv->btcoexist.bt_coexistence =
2431                 rtlpriv->btcoexist.eeprom_bt_coexist;
2432         rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2433         rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2434
2435         if (rtlpriv->btcoexist.reg_bt_iso == 2)
2436                 rtlpriv->btcoexist.bt_ant_isolation =
2437                                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2438         else
2439                 rtlpriv->btcoexist.bt_ant_isolation =
2440                                 rtlpriv->btcoexist.reg_bt_iso;
2441
2442         rtlpriv->btcoexist.bt_radio_shared_type =
2443                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2444
2445         if (rtlpriv->btcoexist.bt_coexistence) {
2446                 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2447                         rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2448                 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2449                         rtlpriv->btcoexist.bt_service = BT_SCO;
2450                 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2451                         rtlpriv->btcoexist.bt_service = BT_BUSY;
2452                 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2453                         rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2454                 else
2455                         rtlpriv->btcoexist.bt_service = BT_IDLE;
2456
2457                 rtlpriv->btcoexist.bt_edca_ul = 0;
2458                 rtlpriv->btcoexist.bt_edca_dl = 0;
2459                 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2460         }
2461 }
2462
2463 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2464                                               bool auto_load_fail, u8 *hwinfo)
2465 {
2466         struct rtl_priv *rtlpriv = rtl_priv(hw);
2467         u8 value;
2468
2469         if (!auto_load_fail) {
2470                 rtlpriv->btcoexist.eeprom_bt_coexist =
2471                         ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2472                 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2473                         rtlpriv->btcoexist.eeprom_bt_coexist  = 0;
2474                 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2475                 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2476                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2477                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2478                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2479                                  ((value & 0x20) >> 5);
2480         } else {
2481                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2482                 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2483                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2484                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2485                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2486         }
2487
2488         rtl8188ee_bt_var_init(hw);
2489 }
2490
2491 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2492 {
2493         struct rtl_priv *rtlpriv = rtl_priv(hw);
2494
2495         /* 0:Low, 1:High, 2:From Efuse. */
2496         rtlpriv->btcoexist.reg_bt_iso = 2;
2497         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2498         rtlpriv->btcoexist.reg_bt_sco = 3;
2499         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2500         rtlpriv->btcoexist.reg_bt_sco = 0;
2501 }
2502
2503 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2504 {
2505         struct rtl_priv *rtlpriv = rtl_priv(hw);
2506         struct rtl_phy *rtlphy = &rtlpriv->phy;
2507         u8 u1_tmp;
2508
2509         if (rtlpriv->btcoexist.bt_coexistence &&
2510             ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2511               rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2512                 if (rtlpriv->btcoexist.bt_ant_isolation)
2513                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2514
2515                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2516                          BIT_OFFSET_LEN_MASK_32(0, 1);
2517                 u1_tmp = u1_tmp |
2518                          ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2519                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2520                          ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2521                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2522                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2523
2524                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2525                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2526                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2527
2528                 /* Config to 1T1R. */
2529                 if (rtlphy->rf_type == RF_1T1R) {
2530                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2531                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2532                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2533
2534                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2535                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2536                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2537                 }
2538         }
2539 }
2540
2541 void rtl88ee_suspend(struct ieee80211_hw *hw)
2542 {
2543 }
2544
2545 void rtl88ee_resume(struct ieee80211_hw *hw)
2546 {
2547 }