drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../core.h"
  28 #include "../pci.h"
  29 #include "../base.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "dm.h"
  34 #include "../rtl8192c/dm_common.h"
  35 #include "../rtl8192c/fw_common.h"
  36 #include "../rtl8192c/phy_common.h"
  37 #include "hw.h"
  38 #include "rf.h"
  39 #include "sw.h"
  40 #include "trx.h"
  41 #include "led.h"
  42
  43 #include <linux/module.h>
  44
  45 static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
  46 {
  47         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  48
  49         /*close ASPM for AMD defaultly */
  50         rtlpci->const_amdpci_aspm = 0;
  51
  52         /*
  53          * ASPM PS mode.
  54          * 0 - Disable ASPM,
  55          * 1 - Enable ASPM without Clock Req,
  56          * 2 - Enable ASPM with Clock Req,
  57          * 3 - Alwyas Enable ASPM with Clock Req,
  58          * 4 - Always Enable ASPM without Clock Req.
  59          * set defult to RTL8192CE:3 RTL8192E:2
  60          * */
  61         rtlpci->const_pci_aspm = 3;
  62
  63         /*Setting for PCI-E device */
  64         rtlpci->const_devicepci_aspm_setting = 0x03;
  65
  66         /*Setting for PCI-E bridge */
  67         rtlpci->const_hostpci_aspm_setting = 0x02;
  68
  69         /*
  70          * In Hw/Sw Radio Off situation.
  71          * 0 - Default,
  72          * 1 - From ASPM setting without low Mac Pwr,
  73          * 2 - From ASPM setting with low Mac Pwr,
  74          * 3 - Bus D3
  75          * set default to RTL8192CE:0 RTL8192SE:2
  76          */
  77         rtlpci->const_hwsw_rfoff_d3 = 0;
  78
  79         /*
  80          * This setting works for those device with
  81          * backdoor ASPM setting such as EPHY setting.
  82          * 0 - Not support ASPM,
  83          * 1 - Support ASPM,
  84          * 2 - According to chipset.
  85          */
  86         rtlpci->const_support_pciaspm = 1;
  87 }
  88
  89 int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
  90 {
  91         int err;
  92         struct rtl_priv *rtlpriv = rtl_priv(hw);
  93         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  94         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  95         char *fw_name;
  96
  97         rtl8192ce_bt_reg_init(hw);
  98
  99         rtlpriv->dm.dm_initialgain_enable = true;
 100         rtlpriv->dm.dm_flag = 0;
 101         rtlpriv->dm.disable_framebursting = false;
 102         rtlpriv->dm.thermalvalue = 0;
 103         rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
 104
 105         /* compatible 5G band 88ce just 2.4G band & smsp */
 106         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 107         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 108         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 109
 110         rtlpci->receive_config = (RCR_APPFCS |
 111                                   RCR_AMF |
 112                                   RCR_ADF |
 113                                   RCR_APP_MIC |
 114                                   RCR_APP_ICV |
 115                                   RCR_AICV |
 116                                   RCR_ACRC32 |
 117                                   RCR_AB |
 118                                   RCR_AM |
 119                                   RCR_APM |
 120                                   RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
 121
 122         rtlpci->irq_mask[0] =
 123             (u32) (IMR_ROK |
 124                    IMR_VODOK |
 125                    IMR_VIDOK |
 126                    IMR_BEDOK |
 127                    IMR_BKDOK |
 128                    IMR_MGNTDOK |
 129                    IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
 130
 131         rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
 132
 133         /* for LPS & IPS */
 134         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 135         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 136         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 137         rtlpriv->cfg->mod_params->sw_crypto =
 138                 rtlpriv->cfg->mod_params->sw_crypto;
 139         if (!rtlpriv->psc.inactiveps)
 140                 pr_info("rtl8192ce: Power Save off (module option)\n");
 141         if (!rtlpriv->psc.fwctrl_lps)
 142                 pr_info("rtl8192ce: FW Power Save off (module option)\n");
 143         rtlpriv->psc.reg_fwctrl_lps = 3;
 144         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 145         /* for ASPM, you can close aspm through
 146          * set const_support_pciaspm = 0 */
 147         rtl92c_init_aspm_vars(hw);
 148
 149         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 150                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 151         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 152                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 153         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 154                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 155
 156         /* for firmware buf */
 157         rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
 158         if (!rtlpriv->rtlhal.pfirmware) {
 159                 pr_err("Can't alloc buffer for fw\n");
 160                 return 1;
 161         }
 162
 163         /* request fw */
 164         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
 165             !IS_92C_SERIAL(rtlhal->version))
 166                 fw_name = "/*(DEBLOBBED)*/";
 167         else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
 168                 fw_name = "/*(DEBLOBBED)*/";
 169         else
 170                 fw_name = "/*(DEBLOBBED)*/";
 171
 172         rtlpriv->max_fw_size = 0x4000;
 173         pr_info("Using firmware %s\n", fw_name);
 174         err = reject_firmware_nowait(THIS_MODULE, 1, fw_name,
 175                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 176                                       rtl_fw_cb);
 177         if (err) {
 178                 pr_err("Failed to request firmware!\n");
 179                 vfree(rtlpriv->rtlhal.pfirmware);
 180                 rtlpriv->rtlhal.pfirmware = NULL;
 181                 return 1;
 182         }
 183
 184         return 0;
 185 }
 186
 187 void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190
 191         if (rtlpriv->rtlhal.pfirmware) {
 192                 vfree(rtlpriv->rtlhal.pfirmware);
 193                 rtlpriv->rtlhal.pfirmware = NULL;
 194         }
 195 }
 196
 197 static struct rtl_hal_ops rtl8192ce_hal_ops = {
 198         .init_sw_vars = rtl92c_init_sw_vars,
 199         .deinit_sw_vars = rtl92c_deinit_sw_vars,
 200         .read_eeprom_info = rtl92ce_read_eeprom_info,
 201         .interrupt_recognized = rtl92ce_interrupt_recognized,
 202         .hw_init = rtl92ce_hw_init,
 203         .hw_disable = rtl92ce_card_disable,
 204         .hw_suspend = rtl92ce_suspend,
 205         .hw_resume = rtl92ce_resume,
 206         .enable_interrupt = rtl92ce_enable_interrupt,
 207         .disable_interrupt = rtl92ce_disable_interrupt,
 208         .set_network_type = rtl92ce_set_network_type,
 209         .set_chk_bssid = rtl92ce_set_check_bssid,
 210         .set_qos = rtl92ce_set_qos,
 211         .set_bcn_reg = rtl92ce_set_beacon_related_registers,
 212         .set_bcn_intv = rtl92ce_set_beacon_interval,
 213         .update_interrupt_mask = rtl92ce_update_interrupt_mask,
 214         .get_hw_reg = rtl92ce_get_hw_reg,
 215         .set_hw_reg = rtl92ce_set_hw_reg,
 216         .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
 217         .fill_tx_desc = rtl92ce_tx_fill_desc,
 218         .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
 219         .query_rx_desc = rtl92ce_rx_query_desc,
 220         .set_channel_access = rtl92ce_update_channel_access_setting,
 221         .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
 222         .set_bw_mode = rtl92c_phy_set_bw_mode,
 223         .switch_channel = rtl92c_phy_sw_chnl,
 224         .dm_watchdog = rtl92c_dm_watchdog,
 225         .scan_operation_backup = rtl_phy_scan_operation_backup,
 226         .set_rf_power_state = rtl92c_phy_set_rf_power_state,
 227         .led_control = rtl92ce_led_control,
 228         .set_desc = rtl92ce_set_desc,
 229         .get_desc = rtl92ce_get_desc,
 230         .is_tx_desc_closed = rtl92ce_is_tx_desc_closed,
 231         .tx_polling = rtl92ce_tx_polling,
 232         .enable_hw_sec = rtl92ce_enable_hw_security_config,
 233         .set_key = rtl92ce_set_key,
 234         .init_sw_leds = rtl92ce_init_sw_leds,
 235         .get_bbreg = rtl92c_phy_query_bb_reg,
 236         .set_bbreg = rtl92c_phy_set_bb_reg,
 237         .set_rfreg = rtl92ce_phy_set_rf_reg,
 238         .get_rfreg = rtl92c_phy_query_rf_reg,
 239         .phy_rf6052_config = rtl92ce_phy_rf6052_config,
 240         .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
 241         .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
 242         .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
 243         .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
 244         .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
 245         .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
 246         .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
 247         .get_btc_status = rtl_btc_status_false,
 248 };
 249
 250 static struct rtl_mod_params rtl92ce_mod_params = {
 251         .sw_crypto = false,
 252         .inactiveps = true,
 253         .swctrl_lps = false,
 254         .fwctrl_lps = true,
 255         .debug_level = 0,
 256         .debug_mask = 0,
 257 };
 258
 259 static const struct rtl_hal_cfg rtl92ce_hal_cfg = {
 260         .bar_id = 2,
 261         .write_readback = true,
 262         .name = "rtl92c_pci",
 263         .ops = &rtl8192ce_hal_ops,
 264         .mod_params = &rtl92ce_mod_params,
 265
 266         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 267         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 268         .maps[SYS_CLK] = REG_SYS_CLKR,
 269         .maps[MAC_RCR_AM] = AM,
 270         .maps[MAC_RCR_AB] = AB,
 271         .maps[MAC_RCR_ACRC32] = ACRC32,
 272         .maps[MAC_RCR_ACF] = ACF,
 273         .maps[MAC_RCR_AAP] = AAP,
 274         .maps[MAC_HIMR] = REG_HIMR,
 275         .maps[MAC_HIMRE] = REG_HIMRE,
 276
 277         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 278         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 279         .maps[EFUSE_CLK] = 0,
 280         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 281         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 282         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 283         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 284         .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
 285         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 286         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 287         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 288         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 289
 290         .maps[RWCAM] = REG_CAMCMD,
 291         .maps[WCAMI] = REG_CAMWRITE,
 292         .maps[RCAMO] = REG_CAMREAD,
 293         .maps[CAMDBG] = REG_CAMDBG,
 294         .maps[SECR] = REG_SECCFG,
 295         .maps[SEC_CAM_NONE] = CAM_NONE,
 296         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 297         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 298         .maps[SEC_CAM_AES] = CAM_AES,
 299         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 300
 301         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 302         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 303         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 304         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 305         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 306         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 307         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 308         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 309         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 310         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 311         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 312         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 313         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 314         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 315         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 316         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 317
 318         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 319         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 320         .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
 321         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 322         .maps[RTL_IMR_RDU] = IMR_RDU,
 323         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 324         .maps[RTL_IMR_BDOK] = IMR_BDOK,
 325         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 326         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 327         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 328         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 329         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 330         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 331         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 332         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 333         .maps[RTL_IMR_ROK] = IMR_ROK,
 334         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
 335
 336         .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
 337         .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
 338         .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
 339         .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
 340         .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
 341         .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
 342         .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
 343         .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
 344         .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
 345         .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
 346         .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
 347         .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
 348
 349         .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
 350         .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
 351 };
 352
 353 static const struct pci_device_id rtl92ce_pci_ids[] = {
 354         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
 355         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
 356         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
 357         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
 358         {},
 359 };
 360
 361 MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
 362
 363 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 364 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 365 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 366 MODULE_LICENSE("GPL");
 367 MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
 368 /*(DEBLOBBED)*/
 369
 370 module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
 371 module_param_named(debug_level, rtl92ce_mod_params.debug_level, int, 0644);
 372 module_param_named(debug_mask, rtl92ce_mod_params.debug_mask, ullong, 0644);
 373 module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
 374 module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
 375 module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
 376 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 377 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 378 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 379 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 380 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 381 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 382
 383 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 384
 385 static struct pci_driver rtl92ce_driver = {
 386         .name = KBUILD_MODNAME,
 387         .id_table = rtl92ce_pci_ids,
 388         .probe = rtl_pci_probe,
 389         .remove = rtl_pci_disconnect,
 390         .driver.pm = &rtlwifi_pm_ops,
 391 };
 392
 393 module_pci_driver(rtl92ce_driver);