drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../cam.h"
  34 #include "../ps.h"
  35 #include "../usb.h"
  36 #include "reg.h"
  37 #include "def.h"
  38 #include "phy.h"
  39 #include "../rtl8192c/phy_common.h"
  40 #include "mac.h"
  41 #include "dm.h"
  42 #include "../rtl8192c/dm_common.h"
  43 #include "../rtl8192c/fw_common.h"
  44 #include "hw.h"
  45 #include "../rtl8192ce/hw.h"
  46 #include "trx.h"
  47 #include "led.h"
  48 #include "table.h"
  49
  50 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  51 {
  52         struct rtl_priv *rtlpriv = rtl_priv(hw);
  53         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  54         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  55
  56         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  57         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  58         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  59                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  60                         RTL8192CUPHY_REG_Array_PG_HPLength;
  61                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  62                         RTL8192CUPHY_REG_Array_PG_HP;
  63         } else {
  64                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  65                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  66                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  67                         RTL8192CUPHY_REG_ARRAY_PG;
  68         }
  69         /* 2T */
  70         rtlphy->hwparam_tables[PHY_REG_2T].length =
  71                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  72         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  73                         RTL8192CUPHY_REG_2TARRAY;
  74         rtlphy->hwparam_tables[RADIOA_2T].length =
  75                         RTL8192CURADIOA_2TARRAYLENGTH;
  76         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  77                         RTL8192CURADIOA_2TARRAY;
  78         rtlphy->hwparam_tables[RADIOB_2T].length =
  79                         RTL8192CURADIOB_2TARRAYLENGTH;
  80         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  81                         RTL8192CU_RADIOB_2TARRAY;
  82         rtlphy->hwparam_tables[AGCTAB_2T].length =
  83                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  84         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  85                         RTL8192CUAGCTAB_2TARRAY;
  86         /* 1T */
  87         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  88                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  89                         RTL8192CUPHY_REG_1T_HPArrayLength;
  90                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  91                         RTL8192CUPHY_REG_1T_HPArray;
  92                 rtlphy->hwparam_tables[RADIOA_1T].length =
  93                         RTL8192CURadioA_1T_HPArrayLength;
  94                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  95                         RTL8192CURadioA_1T_HPArray;
  96                 rtlphy->hwparam_tables[RADIOB_1T].length =
  97                         RTL8192CURADIOB_1TARRAYLENGTH;
  98                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  99                         RTL8192CU_RADIOB_1TARRAY;
 100                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 101                         RTL8192CUAGCTAB_1T_HPArrayLength;
 102                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 103                         Rtl8192CUAGCTAB_1T_HPArray;
 104         } else {
 105                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 106                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 107                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 108                         RTL8192CUPHY_REG_1TARRAY;
 109                 rtlphy->hwparam_tables[RADIOA_1T].length =
 110                         RTL8192CURADIOA_1TARRAYLENGTH;
 111                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 112                         RTL8192CU_RADIOA_1TARRAY;
 113                 rtlphy->hwparam_tables[RADIOB_1T].length =
 114                         RTL8192CURADIOB_1TARRAYLENGTH;
 115                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 116                         RTL8192CU_RADIOB_1TARRAY;
 117                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 118                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 119                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 120                         RTL8192CUAGCTAB_1TARRAY;
 121         }
 122 }
 123
 124 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 125                                                  bool autoload_fail,
 126                                                  u8 *hwinfo)
 127 {
 128         struct rtl_priv *rtlpriv = rtl_priv(hw);
 129         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 130         u8 rf_path, index, tempval;
 131         u16 i;
 132
 133         for (rf_path = 0; rf_path < 2; rf_path++) {
 134                 for (i = 0; i < 3; i++) {
 135                         if (!autoload_fail) {
 136                                 rtlefuse->
 137                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 138                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 139                                 rtlefuse->
 140                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 141                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 142                                            i];
 143                         } else {
 144                                 rtlefuse->
 145                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 146                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 147                                 rtlefuse->
 148                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 149                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 150                         }
 151                 }
 152         }
 153         for (i = 0; i < 3; i++) {
 154                 if (!autoload_fail)
 155                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 156                 else
 157                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 158                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
 159                     (tempval & 0xf);
 160                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
 161                     ((tempval & 0xf0) >> 4);
 162         }
 163         for (rf_path = 0; rf_path < 2; rf_path++)
 164                 for (i = 0; i < 3; i++)
 165                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 166                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
 167                                 rf_path, i,
 168                                 rtlefuse->
 169                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
 170         for (rf_path = 0; rf_path < 2; rf_path++)
 171                 for (i = 0; i < 3; i++)
 172                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 173                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 174                                 rf_path, i,
 175                                 rtlefuse->
 176                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
 177         for (rf_path = 0; rf_path < 2; rf_path++)
 178                 for (i = 0; i < 3; i++)
 179                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 180                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 181                                 rf_path, i,
 182                                 rtlefuse->
 183                                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
 184         for (rf_path = 0; rf_path < 2; rf_path++) {
 185                 for (i = 0; i < 14; i++) {
 186                         index = rtl92c_get_chnl_group((u8)i);
 187                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 188                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 189                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 190                             rtlefuse->
 191                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 192                         if ((rtlefuse->
 193                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 194                              rtlefuse->
 195                              eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
 196                             > 0) {
 197                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 198                                     rtlefuse->
 199                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 200                                     [index] - rtlefuse->
 201                                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
 202                                     [index];
 203                         } else {
 204                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 205                         }
 206                 }
 207                 for (i = 0; i < 14; i++) {
 208                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 209                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
 210                                 rtlefuse->txpwrlevel_cck[rf_path][i],
 211                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 212                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
 213                 }
 214         }
 215         for (i = 0; i < 3; i++) {
 216                 if (!autoload_fail) {
 217                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 218                             hwinfo[EEPROM_TXPWR_GROUP + i];
 219                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 220                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 221                 } else {
 222                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 223                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 224                 }
 225         }
 226         for (rf_path = 0; rf_path < 2; rf_path++) {
 227                 for (i = 0; i < 14; i++) {
 228                         index = rtl92c_get_chnl_group((u8)i);
 229                         if (rf_path == RF90_PATH_A) {
 230                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 231                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 232                                      & 0xf);
 233                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 234                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 235                                      & 0xf);
 236                         } else if (rf_path == RF90_PATH_B) {
 237                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 238                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 239                                       & 0xf0) >> 4);
 240                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 241                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 242                                       & 0xf0) >> 4);
 243                         }
 244                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 245                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 246                                 rf_path, i,
 247                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
 248                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 249                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 250                                 rf_path, i,
 251                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
 252                 }
 253         }
 254         for (i = 0; i < 14; i++) {
 255                 index = rtl92c_get_chnl_group((u8)i);
 256                 if (!autoload_fail)
 257                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 258                 else
 259                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 260                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 261                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 262                     ((tempval >> 4) & 0xF);
 263                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 264                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 265                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 266                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 267                 index = rtl92c_get_chnl_group((u8)i);
 268                 if (!autoload_fail)
 269                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 270                 else
 271                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 272                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 273                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 274                     ((tempval >> 4) & 0xF);
 275         }
 276         rtlefuse->legacy_ht_txpowerdiff =
 277             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 278         for (i = 0; i < 14; i++)
 279                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 280                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
 281                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
 282         for (i = 0; i < 14; i++)
 283                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 284                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
 285                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
 286         for (i = 0; i < 14; i++)
 287                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 288                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
 289                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
 290         for (i = 0; i < 14; i++)
 291                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 292                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
 293                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
 294         if (!autoload_fail)
 295                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 296         else
 297                 rtlefuse->eeprom_regulatory = 0;
 298         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 299                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
 300         if (!autoload_fail) {
 301                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 302                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 303         } else {
 304                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 305                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 306         }
 307         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 308                 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 309                 rtlefuse->eeprom_tssi[RF90_PATH_A],
 310                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
 311         if (!autoload_fail)
 312                 tempval = hwinfo[EEPROM_THERMAL_METER];
 313         else
 314                 tempval = EEPROM_DEFAULT_THERMALMETER;
 315         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 316         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 317             rtlefuse->eeprom_thermalmeter > 0x1c)
 318                 rtlefuse->eeprom_thermalmeter = 0x12;
 319         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 320                 rtlefuse->apk_thermalmeterignore = true;
 321         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 322         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 323                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
 324 }
 325
 326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 327 {
 328         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 329         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 330         u8 boardType;
 331
 332         if (IS_NORMAL_CHIP(rtlhal->version)) {
 333                 boardType = ((contents[EEPROM_RF_OPT1]) &
 334                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 335         } else {
 336                 boardType = contents[EEPROM_RF_OPT4];
 337                 boardType &= BOARD_TYPE_TEST_MASK;
 338         }
 339         rtlefuse->board_type = boardType;
 340         if (IS_HIGHT_PA(rtlefuse->board_type))
 341                 rtlefuse->external_pa = 1;
 342         pr_info("Board Type %x\n", rtlefuse->board_type);
 343 }
 344
 345 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 346 {
 347         struct rtl_priv *rtlpriv = rtl_priv(hw);
 348         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 349         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 350         int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
 351                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
 352                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
 353                         0};
 354         u8 *hwinfo;
 355
 356         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
 357         if (!hwinfo)
 358                 return;
 359
 360         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
 361                 goto exit;
 362
 363         _rtl92cu_read_txpower_info_from_hwpg(hw,
 364                                            rtlefuse->autoload_failflag, hwinfo);
 365         _rtl92cu_read_board_type(hw, hwinfo);
 366
 367         rtlefuse->txpwr_fromeprom = true;
 368         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 369                 switch (rtlefuse->eeprom_oemid) {
 370                 case EEPROM_CID_DEFAULT:
 371                         if (rtlefuse->eeprom_did == 0x8176) {
 372                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 373                                      rtlefuse->eeprom_smid == 0x1629))
 374                                         rtlhal->oem_id = RT_CID_819X_HP;
 375                                 else
 376                                         rtlhal->oem_id = RT_CID_DEFAULT;
 377                         } else {
 378                                 rtlhal->oem_id = RT_CID_DEFAULT;
 379                         }
 380                         break;
 381                 case EEPROM_CID_TOSHIBA:
 382                         rtlhal->oem_id = RT_CID_TOSHIBA;
 383                         break;
 384                 case EEPROM_CID_QMI:
 385                         rtlhal->oem_id = RT_CID_819X_QMI;
 386                         break;
 387                 case EEPROM_CID_WHQL:
 388                 default:
 389                         rtlhal->oem_id = RT_CID_DEFAULT;
 390                         break;
 391                 }
 392         }
 393 exit:
 394         kfree(hwinfo);
 395 }
 396
 397 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 398 {
 399         struct rtl_priv *rtlpriv = rtl_priv(hw);
 400         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 401         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 402
 403         switch (rtlhal->oem_id) {
 404         case RT_CID_819X_HP:
 405                 usb_priv->ledctl.led_opendrain = true;
 406                 break;
 407         case RT_CID_819X_LENOVO:
 408         case RT_CID_DEFAULT:
 409         case RT_CID_TOSHIBA:
 410         case RT_CID_CCX:
 411         case RT_CID_819X_ACER:
 412         case RT_CID_WHQL:
 413         default:
 414                 break;
 415         }
 416         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
 417                  rtlhal->oem_id);
 418 }
 419
 420 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 421 {
 422
 423         struct rtl_priv *rtlpriv = rtl_priv(hw);
 424         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 425         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 426         u8 tmp_u1b;
 427
 428         if (!IS_NORMAL_CHIP(rtlhal->version))
 429                 return;
 430         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 431         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 432                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 433         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
 434                  tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
 435         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 436         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
 437                  tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
 438         _rtl92cu_read_adapter_info(hw);
 439         _rtl92cu_hal_customized_behavior(hw);
 440         return;
 441 }
 442
 443 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 444 {
 445         struct rtl_priv *rtlpriv = rtl_priv(hw);
 446         int             status = 0;
 447         u16             value16;
 448         u8              value8;
 449         /*  polling autoload done. */
 450         u32     pollingCount = 0;
 451
 452         do {
 453                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 454                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 455                                  "Autoload Done!\n");
 456                         break;
 457                 }
 458                 if (pollingCount++ > 100) {
 459                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 460                                  "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
 461                         return -ENODEV;
 462                 }
 463         } while (true);
 464         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 465         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 466         /* Power on when re-enter from IPS/Radio off/card disable */
 467         /* enable SPS into PWM mode */
 468         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 469         udelay(100);
 470         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 471         if (0 == (value8 & LDV12_EN)) {
 472                 value8 |= LDV12_EN;
 473                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 474                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 475                          " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
 476                          value8);
 477                 udelay(100);
 478                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 479                 value8 &= ~ISO_MD2PP;
 480                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 481         }
 482         /*  auto enable WLAN */
 483         pollingCount = 0;
 484         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 485         value16 |= APFM_ONMAC;
 486         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 487         do {
 488                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 489                         pr_info("MAC auto ON okay!\n");
 490                         break;
 491                 }
 492                 if (pollingCount++ > 1000) {
 493                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 494                                  "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
 495                         return -ENODEV;
 496                 }
 497         } while (true);
 498         /* Enable Radio ,GPIO ,and LED function */
 499         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 500         /* release RF digital isolation */
 501         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 502         value16 &= ~ISO_DIOR;
 503         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 504         /* Reconsider when to do this operation after asking HWSD. */
 505         pollingCount = 0;
 506         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 507                                                 REG_APSD_CTRL) & ~BIT(6)));
 508         do {
 509                 pollingCount++;
 510         } while ((pollingCount < 200) &&
 511                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 512         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 513         value16 = rtl_read_word(rtlpriv,  REG_CR);
 514         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 515                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 516         rtl_write_word(rtlpriv, REG_CR, value16);
 517         return status;
 518 }
 519
 520 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 521                                               bool wmm_enable,
 522                                               u8 out_ep_num,
 523                                               u8 queue_sel)
 524 {
 525         struct rtl_priv *rtlpriv = rtl_priv(hw);
 526         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 527         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 528         u32 outEPNum = (u32)out_ep_num;
 529         u32 numHQ = 0;
 530         u32 numLQ = 0;
 531         u32 numNQ = 0;
 532         u32 numPubQ;
 533         u32 value32;
 534         u8 value8;
 535         u32 txQPageNum, txQPageUnit, txQRemainPage;
 536
 537         if (!wmm_enable) {
 538                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 539                           CHIP_A_PAGE_NUM_PUBQ;
 540                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 541
 542                 txQPageUnit = txQPageNum/outEPNum;
 543                 txQRemainPage = txQPageNum % outEPNum;
 544                 if (queue_sel & TX_SELE_HQ)
 545                         numHQ = txQPageUnit;
 546                 if (queue_sel & TX_SELE_LQ)
 547                         numLQ = txQPageUnit;
 548                 /* HIGH priority queue always present in the configuration of
 549                  * 2 out-ep. Remainder pages have assigned to High queue */
 550                 if ((outEPNum > 1) && (txQRemainPage))
 551                         numHQ += txQRemainPage;
 552                 /* NOTE: This step done before writting REG_RQPN. */
 553                 if (isChipN) {
 554                         if (queue_sel & TX_SELE_NQ)
 555                                 numNQ = txQPageUnit;
 556                         value8 = (u8)_NPQ(numNQ);
 557                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 558                 }
 559         } else {
 560                 /* for WMM ,number of out-ep must more than or equal to 2! */
 561                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 562                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 563                 if (queue_sel & TX_SELE_HQ) {
 564                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 565                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 566                 }
 567                 if (queue_sel & TX_SELE_LQ) {
 568                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 569                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 570                 }
 571                 /* NOTE: This step done before writting REG_RQPN. */
 572                 if (isChipN) {
 573                         if (queue_sel & TX_SELE_NQ)
 574                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 575                         value8 = (u8)_NPQ(numNQ);
 576                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 577                 }
 578         }
 579         /* TX DMA */
 580         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 581         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 582 }
 583
 584 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 585 {
 586         struct rtl_priv *rtlpriv = rtl_priv(hw);
 587         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 588         u8      txpktbuf_bndy;
 589         u8      value8;
 590
 591         if (!wmm_enable)
 592                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 593         else /* for WMM */
 594                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 595                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 596                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 597         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 598         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 599         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 600         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 601         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 602         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 603         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 604         rtl_write_byte(rtlpriv, REG_PBP, value8);
 605 }
 606
 607 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 608                                             u16 bkQ, u16 viQ, u16 voQ,
 609                                             u16 mgtQ, u16 hiQ)
 610 {
 611         struct rtl_priv *rtlpriv = rtl_priv(hw);
 612         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 613
 614         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 615                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 616                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 617         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 618 }
 619
 620 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 621                                                     bool wmm_enable,
 622                                                     u8 queue_sel)
 623 {
 624         u16 uninitialized_var(value);
 625
 626         switch (queue_sel) {
 627         case TX_SELE_HQ:
 628                 value = QUEUE_HIGH;
 629                 break;
 630         case TX_SELE_LQ:
 631                 value = QUEUE_LOW;
 632                 break;
 633         case TX_SELE_NQ:
 634                 value = QUEUE_NORMAL;
 635                 break;
 636         default:
 637                 WARN_ON(1); /* Shall not reach here! */
 638                 break;
 639         }
 640         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 641                                         value, value);
 642         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 643 }
 644
 645 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 646                                                                 bool wmm_enable,
 647                                                                 u8 queue_sel)
 648 {
 649         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 650         u16 uninitialized_var(valueHi);
 651         u16 uninitialized_var(valueLow);
 652
 653         switch (queue_sel) {
 654         case (TX_SELE_HQ | TX_SELE_LQ):
 655                 valueHi = QUEUE_HIGH;
 656                 valueLow = QUEUE_LOW;
 657                 break;
 658         case (TX_SELE_NQ | TX_SELE_LQ):
 659                 valueHi = QUEUE_NORMAL;
 660                 valueLow = QUEUE_LOW;
 661                 break;
 662         case (TX_SELE_HQ | TX_SELE_NQ):
 663                 valueHi = QUEUE_HIGH;
 664                 valueLow = QUEUE_NORMAL;
 665                 break;
 666         default:
 667                 WARN_ON(1);
 668                 break;
 669         }
 670         if (!wmm_enable) {
 671                 beQ = valueLow;
 672                 bkQ = valueLow;
 673                 viQ = valueHi;
 674                 voQ = valueHi;
 675                 mgtQ = valueHi;
 676                 hiQ = valueHi;
 677         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 678                 beQ = valueHi;
 679                 bkQ = valueLow;
 680                 viQ = valueLow;
 681                 voQ = valueHi;
 682                 mgtQ = valueHi;
 683                 hiQ = valueHi;
 684         }
 685         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 686         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 687 }
 688
 689 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 690                                                       bool wmm_enable,
 691                                                       u8 queue_sel)
 692 {
 693         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 694         struct rtl_priv *rtlpriv = rtl_priv(hw);
 695
 696         if (!wmm_enable) { /* typical setting */
 697                 beQ     = QUEUE_LOW;
 698                 bkQ     = QUEUE_LOW;
 699                 viQ     = QUEUE_NORMAL;
 700                 voQ     = QUEUE_HIGH;
 701                 mgtQ    = QUEUE_HIGH;
 702                 hiQ     = QUEUE_HIGH;
 703         } else { /* for WMM */
 704                 beQ     = QUEUE_LOW;
 705                 bkQ     = QUEUE_NORMAL;
 706                 viQ     = QUEUE_NORMAL;
 707                 voQ     = QUEUE_HIGH;
 708                 mgtQ    = QUEUE_HIGH;
 709                 hiQ     = QUEUE_HIGH;
 710         }
 711         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 712         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 713                  queue_sel);
 714 }
 715
 716 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 717                                                bool wmm_enable,
 718                                                u8 out_ep_num,
 719                                                u8 queue_sel)
 720 {
 721         switch (out_ep_num) {
 722         case 1:
 723                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 724                                                         queue_sel);
 725                 break;
 726         case 2:
 727                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 728                                                         queue_sel);
 729                 break;
 730         case 3:
 731                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 732                                                           queue_sel);
 733                 break;
 734         default:
 735                 WARN_ON(1); /* Shall not reach here! */
 736                 break;
 737         }
 738 }
 739
 740 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 741                                                bool wmm_enable,
 742                                                u8 out_ep_num,
 743                                                u8 queue_sel)
 744 {
 745         u8 hq_sele = 0;
 746         struct rtl_priv *rtlpriv = rtl_priv(hw);
 747
 748         switch (out_ep_num) {
 749         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 750                 if (!wmm_enable) /* typical setting */
 751                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 752                                    HQSEL_HIQ;
 753                 else    /* for WMM */
 754                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 755                                   HQSEL_HIQ;
 756                 break;
 757         case 1:
 758                 if (TX_SELE_LQ == queue_sel) {
 759                         /* map all endpoint to Low queue */
 760                         hq_sele = 0;
 761                 } else if (TX_SELE_HQ == queue_sel) {
 762                         /* map all endpoint to High queue */
 763                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 764                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 765                 }
 766                 break;
 767         default:
 768                 WARN_ON(1); /* Shall not reach here! */
 769                 break;
 770         }
 771         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 772         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 773                  hq_sele);
 774 }
 775
 776 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 777                                                 bool wmm_enable,
 778                                                 u8 out_ep_num,
 779                                                 u8 queue_sel)
 780 {
 781         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 782         if (IS_NORMAL_CHIP(rtlhal->version))
 783                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 784                                                    queue_sel);
 785         else
 786                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 787                                                    queue_sel);
 788 }
 789
 790 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 791 {
 792 }
 793
 794 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 795 {
 796         u16 value16;
 797         u32 value32;
 798         struct rtl_priv *rtlpriv = rtl_priv(hw);
 799
 800         value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 801                    RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 802                    RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 803         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));
 804         /* Accept all multicast address */
 805         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 806         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 807         /* Accept all management frames */
 808         value16 = 0xFFFF;
 809         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
 810                                       (u8 *)(&value16));
 811         /* Reject all control frame - default value is 0 */
 812         value16 = 0x0;
 813         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
 814                                       (u8 *)(&value16));
 815         /* Accept all data frames */
 816         value16 = 0xFFFF;
 817         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,
 818                                       (u8 *)(&value16));
 819 }
 820
 821 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)
 822 {
 823         struct rtl_priv *rtlpriv = rtl_priv(hw);
 824         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 825
 826         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
 827
 828         /* TODO: Remove these magic number */
 829         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
 830         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
 831         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
 832         /* Change beacon AIFS to the largest number
 833          * beacause test chip does not contension before sending beacon.
 834          */
 835         if (IS_NORMAL_CHIP(rtlhal->version))
 836                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
 837         else
 838                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
 839 }
 840
 841 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 842 {
 843         struct rtl_priv *rtlpriv = rtl_priv(hw);
 844         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 845         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 846         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 847         int err = 0;
 848         u32     boundary = 0;
 849         u8 wmm_enable = false; /* TODO */
 850         u8 out_ep_nums = rtlusb->out_ep_nums;
 851         u8 queue_sel = rtlusb->out_queue_sel;
 852         err = _rtl92cu_init_power_on(hw);
 853
 854         if (err) {
 855                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 856                          "Failed to init power on!\n");
 857                 return err;
 858         }
 859         if (!wmm_enable) {
 860                 boundary = TX_PAGE_BOUNDARY;
 861         } else { /* for WMM */
 862                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
 863                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 864                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 865         }
 866         if (false == rtl92c_init_llt_table(hw, boundary)) {
 867                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 868                          "Failed to init LLT Table!\n");
 869                 return -EINVAL;
 870         }
 871         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
 872                                           queue_sel);
 873         _rtl92c_init_trx_buffer(hw, wmm_enable);
 874         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
 875                                      queue_sel);
 876         /* Get Rx PHY status in order to report RSSI and others. */
 877         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
 878         rtl92c_init_interrupt(hw);
 879         rtl92c_init_network_type(hw);
 880         _rtl92cu_init_wmac_setting(hw);
 881         rtl92c_init_adaptive_ctrl(hw);
 882         rtl92c_init_edca(hw);
 883         rtl92c_init_rate_fallback(hw);
 884         rtl92c_init_retry_function(hw);
 885         _rtl92cu_init_usb_aggregation(hw);
 886         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
 887         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
 888         _rtl92cu_init_beacon_parameters(hw);
 889         rtl92c_init_ampdu_aggregation(hw);
 890         rtl92c_init_beacon_max_error(hw);
 891         return err;
 892 }
 893
 894 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
 895 {
 896         struct rtl_priv *rtlpriv = rtl_priv(hw);
 897         u8 sec_reg_value = 0x0;
 898         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 899
 900         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 901                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 902                  rtlpriv->sec.pairwise_enc_algorithm,
 903                  rtlpriv->sec.group_enc_algorithm);
 904         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 905                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 906                          "not open sw encryption\n");
 907                 return;
 908         }
 909         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 910         if (rtlpriv->sec.use_defaultkey) {
 911                 sec_reg_value |= SCR_TxUseDK;
 912                 sec_reg_value |= SCR_RxUseDK;
 913         }
 914         if (IS_NORMAL_CHIP(rtlhal->version))
 915                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 916         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 917         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 918                  sec_reg_value);
 919         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 920 }
 921
 922 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
 923 {
 924         struct rtl_priv *rtlpriv = rtl_priv(hw);
 925         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
 926
 927         /* To Fix MAC loopback mode fail. */
 928         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
 929         rtl_write_byte(rtlpriv, 0x15, 0xe9);
 930         /* HW SEQ CTRL */
 931         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 932         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 933         /* fixed USB interface interference issue */
 934         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
 935         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
 936         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
 937         rtlusb->reg_bcn_ctrl_val = 0x18;
 938         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
 939 }
 940
 941 static void _InitPABias(struct ieee80211_hw *hw)
 942 {
 943         struct rtl_priv *rtlpriv = rtl_priv(hw);
 944         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 945         u8 pa_setting;
 946
 947         /* FIXED PA current issue */
 948         pa_setting = efuse_read_1byte(hw, 0x1FA);
 949         if (!(pa_setting & BIT(0))) {
 950                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 951                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 952                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 953                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 954         }
 955         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
 956             IS_92C_SERIAL(rtlhal->version)) {
 957                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 958                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 959                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 960                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 961         }
 962         if (!(pa_setting & BIT(4))) {
 963                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
 964                 pa_setting &= 0x0F;
 965                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
 966         }
 967 }
 968
 969 int rtl92cu_hw_init(struct ieee80211_hw *hw)
 970 {
 971         struct rtl_priv *rtlpriv = rtl_priv(hw);
 972         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 973         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 974         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 975         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 976         int err = 0;
 977         unsigned long flags;
 978
 979         /* As this function can take a very long time (up to 350 ms)
 980          * and can be called with irqs disabled, reenable the irqs
 981          * to let the other devices continue being serviced.
 982          *
 983          * It is safe doing so since our own interrupts will only be enabled
 984          * in a subsequent step.
 985          */
 986         local_save_flags(flags);
 987         local_irq_enable();
 988
 989         rtlhal->fw_ready = false;
 990         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
 991         err = _rtl92cu_init_mac(hw);
 992         if (err) {
 993                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
 994                 goto exit;
 995         }
 996         err = rtl92c_download_fw(hw);
 997         if (err) {
 998                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 999                          "Failed to download FW. Init HW without FW now..\n");
1000                 err = 1;
1001                 goto exit;
1002         }
1003
1004         rtlhal->fw_ready = true;
1005         rtlhal->last_hmeboxnum = 0; /* h2c */
1006         _rtl92cu_phy_param_tab_init(hw);
1007         rtl92cu_phy_mac_config(hw);
1008         rtl92cu_phy_bb_config(hw);
1009         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1010         rtl92c_phy_rf_config(hw);
1011         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1012             !IS_92C_SERIAL(rtlhal->version)) {
1013                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1014                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1015         }
1016         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1017                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1018         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1019                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1020         rtl92cu_bb_block_on(hw);
1021         rtl_cam_reset_all_entry(hw);
1022         rtl92cu_enable_hw_security_config(hw);
1023         ppsc->rfpwr_state = ERFON;
1024         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1025         if (ppsc->rfpwr_state == ERFON) {
1026                 rtl92c_phy_set_rfpath_switch(hw, 1);
1027                 if (rtlphy->iqk_initialized) {
1028                         rtl92c_phy_iq_calibrate(hw, true);
1029                 } else {
1030                         rtl92c_phy_iq_calibrate(hw, false);
1031                         rtlphy->iqk_initialized = true;
1032                 }
1033                 rtl92c_dm_check_txpower_tracking(hw);
1034                 rtl92c_phy_lc_calibrate(hw);
1035         }
1036         _rtl92cu_hw_configure(hw);
1037         _InitPABias(hw);
1038         rtl92c_dm_init(hw);
1039 exit:
1040         local_irq_disable();
1041         local_irq_restore(flags);
1042         return err;
1043 }
1044
1045 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1046 {
1047         struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 /**************************************
1049 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1050 b.      RF path 0 offset 0x00 = 0x00    disable RF
1051 c.      APSD_CTRL 0x600[7:0] = 0x40
1052 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1053 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1054 ***************************************/
1055         u8 eRFPath = 0, value8 = 0;
1056         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1057         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1058
1059         value8 |= APSDOFF;
1060         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1061         value8 = 0;
1062         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1063         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1064         value8 &= (~FEN_BB_GLB_RSTn);
1065         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1066 }
1067
1068 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1069 {
1070         struct rtl_priv *rtlpriv = rtl_priv(hw);
1071         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1072
1073         if (rtlhal->fw_version <=  0x20) {
1074                 /*****************************
1075                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1076                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1077                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1078                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1079                 ******************************/
1080                 u16 valu16 = 0;
1081
1082                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1083                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1084                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1085                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1086                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1087                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1088                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1089                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1090                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1091                                FEN_CPUEN)); /* enable MCU ,8051 */
1092         } else {
1093                 u8 retry_cnts = 0;
1094
1095                 /* IF fw in RAM code, do reset */
1096                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1097                         /* reset MCU ready status */
1098                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1099                         /* 8051 reset by self */
1100                         rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1101                         while ((retry_cnts++ < 100) &&
1102                                (FEN_CPUEN & rtl_read_word(rtlpriv,
1103                                REG_SYS_FUNC_EN))) {
1104                                 udelay(50);
1105                         }
1106                         if (retry_cnts >= 100) {
1107                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1108                                          "#####=> 8051 reset failed!.........................\n");
1109                                 /* if 8051 reset fail, reset MAC. */
1110                                 rtl_write_byte(rtlpriv,
1111                                                REG_SYS_FUNC_EN + 1,
1112                                                0x50);
1113                                 udelay(100);
1114                         }
1115                 }
1116                 /* Reset MAC and Enable 8051 */
1117                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1118                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1119         }
1120         if (bWithoutHWSM) {
1121                 /*****************************
1122                   Without HW auto state machine
1123                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1124                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1125                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1126                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1127                 ******************************/
1128                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1129                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1130                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1131                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1132         }
1133 }
1134
1135 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1136 {
1137         struct rtl_priv *rtlpriv = rtl_priv(hw);
1138 /*****************************
1139 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1140 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1141 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1142 ******************************/
1143         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1144         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1145 }
1146
1147 static void _DisableGPIO(struct ieee80211_hw *hw)
1148 {
1149         struct rtl_priv *rtlpriv = rtl_priv(hw);
1150 /***************************************
1151 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1152 k. Value = GPIO_PIN_CTRL[7:0]
1153 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1154 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1155 n. LEDCFG 0x4C[15:0] = 0x8080
1156 ***************************************/
1157         u8      value8;
1158         u16     value16;
1159         u32     value32;
1160
1161         /* 1. Disable GPIO[7:0] */
1162         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1163         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1164         value8 = (u8)(value32&0x000000FF);
1165         value32 |= ((value8<<8) | 0x00FF0000);
1166         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1167         /* 2. Disable GPIO[10:8] */
1168         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1169         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1170         value8 = (u8)(value16&0x000F);
1171         value16 |= ((value8<<4) | 0x0780);
1172         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1173         /* 3. Disable LED0 & 1 */
1174         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1175 }
1176
1177 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1178 {
1179         struct rtl_priv *rtlpriv = rtl_priv(hw);
1180         u16 value16 = 0;
1181         u8 value8 = 0;
1182
1183         if (bWithoutHWSM) {
1184                 /*****************************
1185                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1186                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1187                 r. When driver call disable, the ASIC will turn off remaining
1188                    clock automatically
1189                 ******************************/
1190                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1191                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1192                 value8 &= (~LDV12_EN);
1193                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1194         }
1195
1196 /*****************************
1197 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1198 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1199 ******************************/
1200         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1201         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1202         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1203         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1204 }
1205
1206 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1207 {
1208         /* ==== RF Off Sequence ==== */
1209         _DisableRFAFEAndResetBB(hw);
1210         /* ==== Reset digital sequence   ====== */
1211         _ResetDigitalProcedure1(hw, false);
1212         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1213         _DisableGPIO(hw);
1214         /* ==== Disable analog sequence === */
1215         _DisableAnalog(hw, false);
1216 }
1217
1218 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1219 {
1220         /*==== RF Off Sequence ==== */
1221         _DisableRFAFEAndResetBB(hw);
1222         /*  ==== Reset digital sequence   ====== */
1223         _ResetDigitalProcedure1(hw, true);
1224         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1225         _DisableGPIO(hw);
1226         /*  ==== Reset digital sequence   ====== */
1227         _ResetDigitalProcedure2(hw);
1228         /*  ==== Disable analog sequence === */
1229         _DisableAnalog(hw, true);
1230 }
1231
1232 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1233                                       u8 set_bits, u8 clear_bits)
1234 {
1235         struct rtl_priv *rtlpriv = rtl_priv(hw);
1236         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1237
1238         rtlusb->reg_bcn_ctrl_val |= set_bits;
1239         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1240         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1241 }
1242
1243 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1244 {
1245         struct rtl_priv *rtlpriv = rtl_priv(hw);
1246         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1247         u8 tmp1byte = 0;
1248         if (IS_NORMAL_CHIP(rtlhal->version)) {
1249                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1250                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1251                                tmp1byte & (~BIT(6)));
1252                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1253                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1254                 tmp1byte &= ~(BIT(0));
1255                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1256         } else {
1257                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1258                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1259         }
1260 }
1261
1262 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1263 {
1264         struct rtl_priv *rtlpriv = rtl_priv(hw);
1265         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1266         u8 tmp1byte = 0;
1267
1268         if (IS_NORMAL_CHIP(rtlhal->version)) {
1269                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1270                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1271                                tmp1byte | BIT(6));
1272                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1273                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1274                 tmp1byte |= BIT(0);
1275                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1276         } else {
1277                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1278                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1279         }
1280 }
1281
1282 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1283 {
1284         struct rtl_priv *rtlpriv = rtl_priv(hw);
1285         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1286
1287         if (IS_NORMAL_CHIP(rtlhal->version))
1288                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1289         else
1290                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1291 }
1292
1293 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1294 {
1295         struct rtl_priv *rtlpriv = rtl_priv(hw);
1296         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1297
1298         if (IS_NORMAL_CHIP(rtlhal->version))
1299                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1300         else
1301                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1302 }
1303
1304 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1305                                      enum nl80211_iftype type)
1306 {
1307         struct rtl_priv *rtlpriv = rtl_priv(hw);
1308         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1309         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1310
1311         bt_msr &= 0xfc;
1312         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1313             NL80211_IFTYPE_STATION) {
1314                 _rtl92cu_stop_tx_beacon(hw);
1315                 _rtl92cu_enable_bcn_sub_func(hw);
1316         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1317                 _rtl92cu_resume_tx_beacon(hw);
1318                 _rtl92cu_disable_bcn_sub_func(hw);
1319         } else {
1320                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1321                          "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1322                          type);
1323         }
1324         switch (type) {
1325         case NL80211_IFTYPE_UNSPECIFIED:
1326                 bt_msr |= MSR_NOLINK;
1327                 ledaction = LED_CTL_LINK;
1328                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1329                          "Set Network type to NO LINK!\n");
1330                 break;
1331         case NL80211_IFTYPE_ADHOC:
1332                 bt_msr |= MSR_ADHOC;
1333                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1334                          "Set Network type to Ad Hoc!\n");
1335                 break;
1336         case NL80211_IFTYPE_STATION:
1337                 bt_msr |= MSR_INFRA;
1338                 ledaction = LED_CTL_LINK;
1339                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1340                          "Set Network type to STA!\n");
1341                 break;
1342         case NL80211_IFTYPE_AP:
1343                 bt_msr |= MSR_AP;
1344                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1345                          "Set Network type to AP!\n");
1346                 break;
1347         default:
1348                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1349                          "Network type %d not supported!\n", type);
1350                 goto error_out;
1351         }
1352         rtl_write_byte(rtlpriv, MSR, bt_msr);
1353         rtlpriv->cfg->ops->led_control(hw, ledaction);
1354         if ((bt_msr & MSR_MASK) == MSR_AP)
1355                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1356         else
1357                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1358         return 0;
1359 error_out:
1360         return 1;
1361 }
1362
1363 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1364 {
1365         struct rtl_priv *rtlpriv = rtl_priv(hw);
1366         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1367         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1368         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1369         enum nl80211_iftype opmode;
1370
1371         mac->link_state = MAC80211_NOLINK;
1372         opmode = NL80211_IFTYPE_UNSPECIFIED;
1373         _rtl92cu_set_media_status(hw, opmode);
1374         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1375         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1376         if (rtlusb->disableHWSM)
1377                 _CardDisableHWSM(hw);
1378         else
1379                 _CardDisableWithoutHWSM(hw);
1380
1381         /* after power off we should do iqk again */
1382         rtlpriv->phy.iqk_initialized = false;
1383 }
1384
1385 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1386 {
1387         struct rtl_priv *rtlpriv = rtl_priv(hw);
1388         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1389         u32 reg_rcr;
1390
1391         if (rtlpriv->psc.rfpwr_state != ERFON)
1392                 return;
1393
1394         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1395
1396         if (check_bssid) {
1397                 u8 tmp;
1398                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1399                         reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1400                         tmp = BIT(4);
1401                 } else {
1402                         reg_rcr |= RCR_CBSSID;
1403                         tmp = BIT(4) | BIT(5);
1404                 }
1405                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1406                                               (u8 *) (&reg_rcr));
1407                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1408         } else {
1409                 u8 tmp;
1410                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1411                         reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1412                         tmp = BIT(4);
1413                 } else {
1414                         reg_rcr &= ~RCR_CBSSID;
1415                         tmp = BIT(4) | BIT(5);
1416                 }
1417                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1418                 rtlpriv->cfg->ops->set_hw_reg(hw,
1419                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1420                 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1421         }
1422 }
1423
1424 /*========================================================================== */
1425
1426 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1427 {
1428         struct rtl_priv *rtlpriv = rtl_priv(hw);
1429
1430         if (_rtl92cu_set_media_status(hw, type))
1431                 return -EOPNOTSUPP;
1432
1433         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1434                 if (type != NL80211_IFTYPE_AP)
1435                         rtl92cu_set_check_bssid(hw, true);
1436         } else {
1437                 rtl92cu_set_check_bssid(hw, false);
1438         }
1439
1440         return 0;
1441 }
1442
1443 static void _beacon_function_enable(struct ieee80211_hw *hw)
1444 {
1445         struct rtl_priv *rtlpriv = rtl_priv(hw);
1446
1447         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1448         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1449 }
1450
1451 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1452 {
1453
1454         struct rtl_priv *rtlpriv = rtl_priv(hw);
1455         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1456         u16 bcn_interval, atim_window;
1457         u32 value32;
1458
1459         bcn_interval = mac->beacon_interval;
1460         atim_window = 2;        /*FIX MERGE */
1461         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1462         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1463         _rtl92cu_init_beacon_parameters(hw);
1464         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1465         /*
1466          * Force beacon frame transmission even after receiving beacon frame
1467          * from other ad hoc STA
1468          *
1469          *
1470          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1471          */
1472         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1473         value32 &= ~TSFRST;
1474         rtl_write_dword(rtlpriv, REG_TCR, value32);
1475         value32 |= TSFRST;
1476         rtl_write_dword(rtlpriv, REG_TCR, value32);
1477         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1478                  "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1479                  value32);
1480         /* TODO: Modify later (Find the right parameters)
1481          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1482         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1483             (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1484             (mac->opmode == NL80211_IFTYPE_AP)) {
1485                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1486                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1487         }
1488         _beacon_function_enable(hw);
1489 }
1490
1491 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1492 {
1493         struct rtl_priv *rtlpriv = rtl_priv(hw);
1494         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1495         u16 bcn_interval = mac->beacon_interval;
1496
1497         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1498                  bcn_interval);
1499         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1500 }
1501
1502 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1503                                    u32 add_msr, u32 rm_msr)
1504 {
1505 }
1506
1507 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1508 {
1509         struct rtl_priv *rtlpriv = rtl_priv(hw);
1510         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1511         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1512
1513         switch (variable) {
1514         case HW_VAR_RCR:
1515                 *((u32 *)(val)) = mac->rx_conf;
1516                 break;
1517         case HW_VAR_RF_STATE:
1518                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1519                 break;
1520         case HW_VAR_FWLPS_RF_ON:{
1521                         enum rf_pwrstate rfState;
1522                         u32 val_rcr;
1523
1524                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1525                                                       (u8 *)(&rfState));
1526                         if (rfState == ERFOFF) {
1527                                 *((bool *) (val)) = true;
1528                         } else {
1529                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1530                                 val_rcr &= 0x00070000;
1531                                 if (val_rcr)
1532                                         *((bool *) (val)) = false;
1533                                 else
1534                                         *((bool *) (val)) = true;
1535                         }
1536                         break;
1537                 }
1538         case HW_VAR_FW_PSMODE_STATUS:
1539                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1540                 break;
1541         case HW_VAR_CORRECT_TSF:{
1542                         u64 tsf;
1543                         u32 *ptsf_low = (u32 *)&tsf;
1544                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1545
1546                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1547                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1548                         *((u64 *)(val)) = tsf;
1549                         break;
1550                 }
1551         case HW_VAR_MGT_FILTER:
1552                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1553                 break;
1554         case HW_VAR_CTRL_FILTER:
1555                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1556                 break;
1557         case HW_VAR_DATA_FILTER:
1558                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1559                 break;
1560         case HAL_DEF_WOWLAN:
1561                 break;
1562         default:
1563                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1564                          "switch case %#x not processed\n", variable);
1565                 break;
1566         }
1567 }
1568
1569 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1570 {
1571   /* Currently nothing happens here.
1572    * Traffic stops after some seconds in WPA2 802.11n mode.
1573    * Maybe because rtl8192cu chip should be set from here?
1574    * If I understand correctly, the realtek vendor driver sends some urbs
1575    * if its "here".
1576    *
1577    * This is maybe necessary:
1578    * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb);
1579    */
1580         dev_kfree_skb(skb);
1581
1582         return true;
1583 }
1584
1585 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1586 {
1587         struct rtl_priv *rtlpriv = rtl_priv(hw);
1588         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1589         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1590         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1591         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1592         enum wireless_mode wirelessmode = mac->mode;
1593         u8 idx = 0;
1594
1595         switch (variable) {
1596         case HW_VAR_ETHER_ADDR:{
1597                         for (idx = 0; idx < ETH_ALEN; idx++) {
1598                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1599                                                val[idx]);
1600                         }
1601                         break;
1602                 }
1603         case HW_VAR_BASIC_RATE:{
1604                         u16 rate_cfg = ((u16 *) val)[0];
1605                         u8 rate_index = 0;
1606
1607                         rate_cfg &= 0x15f;
1608                         /* TODO */
1609                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1610                          *     && ((rate_cfg & 0x150) == 0)) {
1611                          *        rate_cfg |= 0x010;
1612                          * } */
1613                         rate_cfg |= 0x01;
1614                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1615                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1616                                        (rate_cfg >> 8) & 0xff);
1617                         while (rate_cfg > 0x1) {
1618                                 rate_cfg >>= 1;
1619                                 rate_index++;
1620                         }
1621                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1622                                        rate_index);
1623                         break;
1624                 }
1625         case HW_VAR_BSSID:{
1626                         for (idx = 0; idx < ETH_ALEN; idx++) {
1627                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1628                                                val[idx]);
1629                         }
1630                         break;
1631                 }
1632         case HW_VAR_SIFS:{
1633                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1634                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1635                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1636                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1637                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1638                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1639                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1640                         break;
1641                 }
1642         case HW_VAR_SLOT_TIME:{
1643                         u8 e_aci;
1644                         u8 QOS_MODE = 1;
1645
1646                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1647                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1648                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
1649                         if (QOS_MODE) {
1650                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1651                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1652                                                                 HW_VAR_AC_PARAM,
1653                                                                 &e_aci);
1654                         } else {
1655                                 u8 sifstime = 0;
1656                                 u8      u1bAIFS;
1657
1658                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1659                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1660                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1661                                         sifstime = 16;
1662                                 else
1663                                         sifstime = 10;
1664                                 u1bAIFS = sifstime + (2 *  val[0]);
1665                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1666                                                u1bAIFS);
1667                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1668                                                u1bAIFS);
1669                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1670                                                u1bAIFS);
1671                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1672                                                u1bAIFS);
1673                         }
1674                         break;
1675                 }
1676         case HW_VAR_ACK_PREAMBLE:{
1677                         u8 reg_tmp;
1678                         u8 short_preamble = (bool)*val;
1679                         reg_tmp = 0;
1680                         if (short_preamble)
1681                                 reg_tmp |= 0x80;
1682                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1683                         break;
1684                 }
1685         case HW_VAR_AMPDU_MIN_SPACE:{
1686                         u8 min_spacing_to_set;
1687                         u8 sec_min_space;
1688
1689                         min_spacing_to_set = *val;
1690                         if (min_spacing_to_set <= 7) {
1691                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1692                                 case NO_ENCRYPTION:
1693                                 case AESCCMP_ENCRYPTION:
1694                                         sec_min_space = 0;
1695                                         break;
1696                                 case WEP40_ENCRYPTION:
1697                                 case WEP104_ENCRYPTION:
1698                                 case TKIP_ENCRYPTION:
1699                                         sec_min_space = 6;
1700                                         break;
1701                                 default:
1702                                         sec_min_space = 7;
1703                                         break;
1704                                 }
1705                                 if (min_spacing_to_set < sec_min_space)
1706                                         min_spacing_to_set = sec_min_space;
1707                                 mac->min_space_cfg = ((mac->min_space_cfg &
1708                                                      0xf8) |
1709                                                      min_spacing_to_set);
1710                                 *val = min_spacing_to_set;
1711                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1712                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1713                                          mac->min_space_cfg);
1714                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1715                                                mac->min_space_cfg);
1716                         }
1717                         break;
1718                 }
1719         case HW_VAR_SHORTGI_DENSITY:{
1720                         u8 density_to_set;
1721
1722                         density_to_set = *val;
1723                         density_to_set &= 0x1f;
1724                         mac->min_space_cfg &= 0x07;
1725                         mac->min_space_cfg |= (density_to_set << 3);
1726                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1727                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1728                                  mac->min_space_cfg);
1729                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1730                                        mac->min_space_cfg);
1731                         break;
1732                 }
1733         case HW_VAR_AMPDU_FACTOR:{
1734                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1735                         u8 factor_toset;
1736                         u8 *p_regtoset = NULL;
1737                         u8 index = 0;
1738
1739                         p_regtoset = regtoset_normal;
1740                         factor_toset = *val;
1741                         if (factor_toset <= 3) {
1742                                 factor_toset = (1 << (factor_toset + 2));
1743                                 if (factor_toset > 0xf)
1744                                         factor_toset = 0xf;
1745                                 for (index = 0; index < 4; index++) {
1746                                         if ((p_regtoset[index] & 0xf0) >
1747                                             (factor_toset << 4))
1748                                                 p_regtoset[index] =
1749                                                      (p_regtoset[index] & 0x0f)
1750                                                      | (factor_toset << 4);
1751                                         if ((p_regtoset[index] & 0x0f) >
1752                                              factor_toset)
1753                                                 p_regtoset[index] =
1754                                                      (p_regtoset[index] & 0xf0)
1755                                                      | (factor_toset);
1756                                         rtl_write_byte(rtlpriv,
1757                                                        (REG_AGGLEN_LMT + index),
1758                                                        p_regtoset[index]);
1759                                 }
1760                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1761                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1762                                          factor_toset);
1763                         }
1764                         break;
1765                 }
1766         case HW_VAR_AC_PARAM:{
1767                         u8 e_aci = *val;
1768                         u32 u4b_ac_param;
1769                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1770                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1771                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1772
1773                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1774                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1775                                          AC_PARAM_ECW_MIN_OFFSET);
1776                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1777                                          AC_PARAM_ECW_MAX_OFFSET);
1778                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1779                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1780                                  "queue:%x, ac_param:%x\n",
1781                                  e_aci, u4b_ac_param);
1782                         switch (e_aci) {
1783                         case AC1_BK:
1784                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1785                                                 u4b_ac_param);
1786                                 break;
1787                         case AC0_BE:
1788                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1789                                                 u4b_ac_param);
1790                                 break;
1791                         case AC2_VI:
1792                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1793                                                 u4b_ac_param);
1794                                 break;
1795                         case AC3_VO:
1796                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1797                                                 u4b_ac_param);
1798                                 break;
1799                         default:
1800                                 RT_ASSERT(false, "invalid aci: %d !\n",
1801                                           e_aci);
1802                                 break;
1803                         }
1804                         break;
1805                 }
1806         case HW_VAR_RCR:{
1807                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1808                         mac->rx_conf = ((u32 *) (val))[0];
1809                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1810                                  "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1811                         break;
1812                 }
1813         case HW_VAR_RETRY_LIMIT:{
1814                         u8 retry_limit = val[0];
1815
1816                         rtl_write_word(rtlpriv, REG_RL,
1817                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1818                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
1819                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1820                                  "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1821                                  retry_limit);
1822                         break;
1823                 }
1824         case HW_VAR_DUAL_TSF_RST:
1825                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1826                 break;
1827         case HW_VAR_EFUSE_BYTES:
1828                 rtlefuse->efuse_usedbytes = *((u16 *) val);
1829                 break;
1830         case HW_VAR_EFUSE_USAGE:
1831                 rtlefuse->efuse_usedpercentage = *val;
1832                 break;
1833         case HW_VAR_IO_CMD:
1834                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1835                 break;
1836         case HW_VAR_WPA_CONFIG:
1837                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1838                 break;
1839         case HW_VAR_SET_RPWM:{
1840                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1841
1842                         if (rpwm_val & BIT(7))
1843                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1844                         else
1845                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1846                                                *val | BIT(7));
1847                         break;
1848                 }
1849         case HW_VAR_H2C_FW_PWRMODE:{
1850                         u8 psmode = *val;
1851
1852                         if ((psmode != FW_PS_ACTIVE_MODE) &&
1853                            (!IS_92C_SERIAL(rtlhal->version)))
1854                                 rtl92c_dm_rf_saving(hw, true);
1855                         rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1856                         break;
1857                 }
1858         case HW_VAR_FW_PSMODE_STATUS:
1859                 ppsc->fw_current_inpsmode = *((bool *) val);
1860                 break;
1861         case HW_VAR_H2C_FW_JOINBSSRPT:{
1862                         u8 mstatus = *val;
1863                         u8 tmp_reg422;
1864                         bool recover = false;
1865
1866                         if (mstatus == RT_MEDIA_CONNECT) {
1867                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1868                                                          HW_VAR_AID, NULL);
1869                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1870                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1871                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1872                                 tmp_reg422 = rtl_read_byte(rtlpriv,
1873                                                         REG_FWHW_TXQ_CTRL + 2);
1874                                 if (tmp_reg422 & BIT(6))
1875                                         recover = true;
1876                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1877                                                tmp_reg422 & (~BIT(6)));
1878                                 rtl92c_set_fw_rsvdpagepkt(hw,
1879                                                           &usb_cmd_send_packet);
1880                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1881                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1882                                 if (recover)
1883                                         rtl_write_byte(rtlpriv,
1884                                                  REG_FWHW_TXQ_CTRL + 2,
1885                                                 tmp_reg422 | BIT(6));
1886                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1887                         }
1888                         rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1889                         break;
1890                 }
1891         case HW_VAR_AID:{
1892                         u16 u2btmp;
1893
1894                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1895                         u2btmp &= 0xC000;
1896                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1897                                        (u2btmp | mac->assoc_id));
1898                         break;
1899                 }
1900         case HW_VAR_CORRECT_TSF:{
1901                         u8 btype_ibss = val[0];
1902
1903                         if (btype_ibss)
1904                                 _rtl92cu_stop_tx_beacon(hw);
1905                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1906                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1907                                         0xffffffff));
1908                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1909                                         (u32)((mac->tsf >> 32) & 0xffffffff));
1910                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1911                         if (btype_ibss)
1912                                 _rtl92cu_resume_tx_beacon(hw);
1913                         break;
1914                 }
1915         case HW_VAR_MGT_FILTER:
1916                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1917                 mac->rx_mgt_filter = *(u16 *)val;
1918                 break;
1919         case HW_VAR_CTRL_FILTER:
1920                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1921                 mac->rx_ctrl_filter = *(u16 *)val;
1922                 break;
1923         case HW_VAR_DATA_FILTER:
1924                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1925                 mac->rx_data_filter = *(u16 *)val;
1926                 break;
1927         case HW_VAR_KEEP_ALIVE:{
1928                         u8 array[2];
1929                         array[0] = 0xff;
1930                         array[1] = *((u8 *)val);
1931                         rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,
1932                                             array);
1933                         break;
1934                 }
1935         default:
1936                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1937                          "switch case %#x not processed\n", variable);
1938                 break;
1939         }
1940 }
1941
1942 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1943                                           struct ieee80211_sta *sta)
1944 {
1945         struct rtl_priv *rtlpriv = rtl_priv(hw);
1946         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1947         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1948         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1949         u32 ratr_value;
1950         u8 ratr_index = 0;
1951         u8 nmode = mac->ht_enable;
1952         u8 mimo_ps = IEEE80211_SMPS_OFF;
1953         u16 shortgi_rate;
1954         u32 tmp_ratr_value;
1955         u8 curtxbw_40mhz = mac->bw_40;
1956         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1957                                1 : 0;
1958         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1959                                1 : 0;
1960         enum wireless_mode wirelessmode = mac->mode;
1961
1962         if (rtlhal->current_bandtype == BAND_ON_5G)
1963                 ratr_value = sta->supp_rates[1] << 4;
1964         else
1965                 ratr_value = sta->supp_rates[0];
1966         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1967                 ratr_value = 0xfff;
1968
1969         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1970                         sta->ht_cap.mcs.rx_mask[0] << 12);
1971         switch (wirelessmode) {
1972         case WIRELESS_MODE_B:
1973                 if (ratr_value & 0x0000000c)
1974                         ratr_value &= 0x0000000d;
1975                 else
1976                         ratr_value &= 0x0000000f;
1977                 break;
1978         case WIRELESS_MODE_G:
1979                 ratr_value &= 0x00000FF5;
1980                 break;
1981         case WIRELESS_MODE_N_24G:
1982         case WIRELESS_MODE_N_5G:
1983                 nmode = 1;
1984                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1985                         ratr_value &= 0x0007F005;
1986                 } else {
1987                         u32 ratr_mask;
1988
1989                         if (get_rf_type(rtlphy) == RF_1T2R ||
1990                             get_rf_type(rtlphy) == RF_1T1R)
1991                                 ratr_mask = 0x000ff005;
1992                         else
1993                                 ratr_mask = 0x0f0ff005;
1994
1995                         ratr_value &= ratr_mask;
1996                 }
1997                 break;
1998         default:
1999                 if (rtlphy->rf_type == RF_1T2R)
2000                         ratr_value &= 0x000ff0ff;
2001                 else
2002                         ratr_value &= 0x0f0ff0ff;
2003
2004                 break;
2005         }
2006
2007         ratr_value &= 0x0FFFFFFF;
2008
2009         if (nmode && ((curtxbw_40mhz &&
2010                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2011                                                curshortgi_20mhz))) {
2012
2013                 ratr_value |= 0x10000000;
2014                 tmp_ratr_value = (ratr_value >> 12);
2015
2016                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2017                         if ((1 << shortgi_rate) & tmp_ratr_value)
2018                                 break;
2019                 }
2020
2021                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2022                     (shortgi_rate << 4) | (shortgi_rate);
2023         }
2024
2025         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2026
2027         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2028                  rtl_read_dword(rtlpriv, REG_ARFR0));
2029 }
2030
2031 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2032                                          struct ieee80211_sta *sta,
2033                                          u8 rssi_level)
2034 {
2035         struct rtl_priv *rtlpriv = rtl_priv(hw);
2036         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2037         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2038         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2039         struct rtl_sta_info *sta_entry = NULL;
2040         u32 ratr_bitmap;
2041         u8 ratr_index;
2042         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2043         u8 curshortgi_40mhz = curtxbw_40mhz &&
2044                               (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2045                                 1 : 0;
2046         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2047                                 1 : 0;
2048         enum wireless_mode wirelessmode = 0;
2049         bool shortgi = false;
2050         u8 rate_mask[5];
2051         u8 macid = 0;
2052         u8 mimo_ps = IEEE80211_SMPS_OFF;
2053
2054         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2055         wirelessmode = sta_entry->wireless_mode;
2056         if (mac->opmode == NL80211_IFTYPE_STATION ||
2057             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2058                 curtxbw_40mhz = mac->bw_40;
2059         else if (mac->opmode == NL80211_IFTYPE_AP ||
2060                 mac->opmode == NL80211_IFTYPE_ADHOC)
2061                 macid = sta->aid + 1;
2062
2063         if (rtlhal->current_bandtype == BAND_ON_5G)
2064                 ratr_bitmap = sta->supp_rates[1] << 4;
2065         else
2066                 ratr_bitmap = sta->supp_rates[0];
2067         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2068                 ratr_bitmap = 0xfff;
2069         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2070                         sta->ht_cap.mcs.rx_mask[0] << 12);
2071         switch (wirelessmode) {
2072         case WIRELESS_MODE_B:
2073                 ratr_index = RATR_INX_WIRELESS_B;
2074                 if (ratr_bitmap & 0x0000000c)
2075                         ratr_bitmap &= 0x0000000d;
2076                 else
2077                         ratr_bitmap &= 0x0000000f;
2078                 break;
2079         case WIRELESS_MODE_G:
2080                 ratr_index = RATR_INX_WIRELESS_GB;
2081
2082                 if (rssi_level == 1)
2083                         ratr_bitmap &= 0x00000f00;
2084                 else if (rssi_level == 2)
2085                         ratr_bitmap &= 0x00000ff0;
2086                 else
2087                         ratr_bitmap &= 0x00000ff5;
2088                 break;
2089         case WIRELESS_MODE_A:
2090                 ratr_index = RATR_INX_WIRELESS_A;
2091                 ratr_bitmap &= 0x00000ff0;
2092                 break;
2093         case WIRELESS_MODE_N_24G:
2094         case WIRELESS_MODE_N_5G:
2095                 ratr_index = RATR_INX_WIRELESS_NGB;
2096
2097                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2098                         if (rssi_level == 1)
2099                                 ratr_bitmap &= 0x00070000;
2100                         else if (rssi_level == 2)
2101                                 ratr_bitmap &= 0x0007f000;
2102                         else
2103                                 ratr_bitmap &= 0x0007f005;
2104                 } else {
2105                         if (rtlphy->rf_type == RF_1T2R ||
2106                             rtlphy->rf_type == RF_1T1R) {
2107                                 if (curtxbw_40mhz) {
2108                                         if (rssi_level == 1)
2109                                                 ratr_bitmap &= 0x000f0000;
2110                                         else if (rssi_level == 2)
2111                                                 ratr_bitmap &= 0x000ff000;
2112                                         else
2113                                                 ratr_bitmap &= 0x000ff015;
2114                                 } else {
2115                                         if (rssi_level == 1)
2116                                                 ratr_bitmap &= 0x000f0000;
2117                                         else if (rssi_level == 2)
2118                                                 ratr_bitmap &= 0x000ff000;
2119                                         else
2120                                                 ratr_bitmap &= 0x000ff005;
2121                                 }
2122                         } else {
2123                                 if (curtxbw_40mhz) {
2124                                         if (rssi_level == 1)
2125                                                 ratr_bitmap &= 0x0f0f0000;
2126                                         else if (rssi_level == 2)
2127                                                 ratr_bitmap &= 0x0f0ff000;
2128                                         else
2129                                                 ratr_bitmap &= 0x0f0ff015;
2130                                 } else {
2131                                         if (rssi_level == 1)
2132                                                 ratr_bitmap &= 0x0f0f0000;
2133                                         else if (rssi_level == 2)
2134                                                 ratr_bitmap &= 0x0f0ff000;
2135                                         else
2136                                                 ratr_bitmap &= 0x0f0ff005;
2137                                 }
2138                         }
2139                 }
2140
2141                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2142                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2143
2144                         if (macid == 0)
2145                                 shortgi = true;
2146                         else if (macid == 1)
2147                                 shortgi = false;
2148                 }
2149                 break;
2150         default:
2151                 ratr_index = RATR_INX_WIRELESS_NGB;
2152
2153                 if (rtlphy->rf_type == RF_1T2R)
2154                         ratr_bitmap &= 0x000ff0ff;
2155                 else
2156                         ratr_bitmap &= 0x0f0ff0ff;
2157                 break;
2158         }
2159         sta_entry->ratr_index = ratr_index;
2160
2161         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2162                  "ratr_bitmap :%x\n", ratr_bitmap);
2163         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2164                                      (ratr_index << 28);
2165         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2166         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2167                  "Rate_index:%x, ratr_val:%x, %5phC\n",
2168                  ratr_index, ratr_bitmap, rate_mask);
2169         memcpy(rtlpriv->rate_mask, rate_mask, 5);
2170         /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2171          * "scheduled while atomic" if called directly */
2172         schedule_work(&rtlpriv->works.fill_h2c_cmd);
2173
2174         if (macid != 0)
2175                 sta_entry->ratr_index = ratr_index;
2176 }
2177
2178 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2179                                  struct ieee80211_sta *sta,
2180                                  u8 rssi_level)
2181 {
2182         struct rtl_priv *rtlpriv = rtl_priv(hw);
2183
2184         if (rtlpriv->dm.useramask)
2185                 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2186         else
2187                 rtl92cu_update_hal_rate_table(hw, sta);
2188 }
2189
2190 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2191 {
2192         struct rtl_priv *rtlpriv = rtl_priv(hw);
2193         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2194         u16 sifs_timer;
2195
2196         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2197                                       &mac->slot_time);
2198         if (!mac->ht_enable)
2199                 sifs_timer = 0x0a0a;
2200         else
2201                 sifs_timer = 0x0e0e;
2202         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2203 }
2204
2205 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2206 {
2207         struct rtl_priv *rtlpriv = rtl_priv(hw);
2208         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2209         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2210         u8 u1tmp = 0;
2211         bool actuallyset = false;
2212         unsigned long flag = 0;
2213         /* to do - usb autosuspend */
2214         u8 usb_autosuspend = 0;
2215
2216         if (ppsc->swrf_processing)
2217                 return false;
2218         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2219         if (ppsc->rfchange_inprogress) {
2220                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2221                 return false;
2222         } else {
2223                 ppsc->rfchange_inprogress = true;
2224                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2225         }
2226         cur_rfstate = ppsc->rfpwr_state;
2227         if (usb_autosuspend) {
2228                 /* to do................... */
2229         } else {
2230                 if (ppsc->pwrdown_mode) {
2231                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2232                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2233                                                ERFOFF : ERFON;
2234                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2235                                  "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2236                 } else {
2237                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2238                                        rtl_read_byte(rtlpriv,
2239                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2240                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2241                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2242                                                  ERFON : ERFOFF;
2243                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2244                                  "GPIO_IN=%02x\n", u1tmp);
2245                 }
2246                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2247                          e_rfpowerstate_toset);
2248         }
2249         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2250                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2251                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2252                 ppsc->hwradiooff = false;
2253                 actuallyset = true;
2254         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2255                     ERFOFF)) {
2256                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2257                          "GPIOChangeRF  - HW Radio OFF\n");
2258                 ppsc->hwradiooff = true;
2259                 actuallyset = true;
2260         } else {
2261                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2262                          "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2263                          ppsc->hwradiooff, e_rfpowerstate_toset);
2264         }
2265         if (actuallyset) {
2266                 ppsc->hwradiooff = true;
2267                 if (e_rfpowerstate_toset == ERFON) {
2268                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2269                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2270                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2271                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2272                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2273                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2274                 }
2275                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2276                 ppsc->rfchange_inprogress = false;
2277                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2278                 /* For power down module, we need to enable register block
2279                  * contrl reg at 0x1c. Then enable power down control bit
2280                  * of register 0x04 BIT4 and BIT15 as 1.
2281                  */
2282                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2283                         /* Enable register area 0x0-0xc. */
2284                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2285                         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2286                 }
2287                 if (e_rfpowerstate_toset == ERFOFF) {
2288                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2289                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2290                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2291                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2292                 }
2293         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2294                 /* Enter D3 or ASPM after GPIO had been done. */
2295                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2296                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2297                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2298                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2299                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2300                 ppsc->rfchange_inprogress = false;
2301                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2302         } else {
2303                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2304                 ppsc->rfchange_inprogress = false;
2305                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2306         }
2307         *valid = 1;
2308         return !ppsc->hwradiooff;
2309 }