drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "../core.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "../rtl8192c/phy_common.h"
  38 #include "rf.h"
  39 #include "dm.h"
  40 #include "../rtl8192c/dm_common.h"
  41 #include "../rtl8192c/fw_common.h"
  42 #include "table.h"
  43
  44 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
  45                              enum radio_path rfpath, u32 regaddr, u32 bitmask)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         u32 original_value, readback_value, bitshift;
  49         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  50
  51         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  52                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
  53                  regaddr, rfpath, bitmask);
  54         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  55                 original_value = _rtl92c_phy_rf_serial_read(hw,
  56                                                             rfpath, regaddr);
  57         } else {
  58                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  59                                                                rfpath, regaddr);
  60         }
  61         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  62         readback_value = (original_value & bitmask) >> bitshift;
  63         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  64                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
  65                  regaddr, rfpath, bitmask, original_value);
  66         return readback_value;
  67 }
  68
  69 void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
  70                             enum radio_path rfpath,
  71                             u32 regaddr, u32 bitmask, u32 data)
  72 {
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  75         u32 original_value, bitshift;
  76
  77         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  78                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  79                  regaddr, bitmask, data, rfpath);
  80         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  81                 if (bitmask != RFREG_OFFSET_MASK) {
  82                         original_value = _rtl92c_phy_rf_serial_read(hw,
  83                                                                     rfpath,
  84                                                                     regaddr);
  85                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  86                         data =
  87                             ((original_value & (~bitmask)) |
  88                              (data << bitshift));
  89                 }
  90                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
  91         } else {
  92                 if (bitmask != RFREG_OFFSET_MASK) {
  93                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  94                                                                        rfpath,
  95                                                                        regaddr);
  96                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  97                         data =
  98                             ((original_value & (~bitmask)) |
  99                              (data << bitshift));
 100                 }
 101                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 102         }
 103         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 104                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 105                  regaddr, bitmask, data, rfpath);
 106 }
 107
 108 bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
 109 {
 110         bool rtstatus;
 111
 112         rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
 113         return rtstatus;
 114 }
 115
 116 bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
 117 {
 118         bool rtstatus = true;
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         u16 regval;
 121         u32 regval32;
 122         u8 b_reg_hwparafile = 1;
 123
 124         _rtl92c_phy_init_bb_rf_register_definition(hw);
 125         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 126         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
 127                        BIT(0) | BIT(1));
 128         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 129         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 130         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 131         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
 132                        FEN_BB_GLB_RSTn | FEN_BBRSTB);
 133         regval32 = rtl_read_dword(rtlpriv, 0x87c);
 134         rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
 135         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
 136         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 137         if (b_reg_hwparafile == 1)
 138                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 139         return rtstatus;
 140 }
 141
 142 bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 143 {
 144         struct rtl_priv *rtlpriv = rtl_priv(hw);
 145         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 146         u32 i;
 147         u32 arraylength;
 148         u32 *ptrarray;
 149
 150         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 151         arraylength =  rtlphy->hwparam_tables[MAC_REG].length ;
 152         ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
 153         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CUMAC_2T_ARRAY\n");
 154         for (i = 0; i < arraylength; i = i + 2)
 155                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 156         return true;
 157 }
 158
 159 bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 160                                             u8 configtype)
 161 {
 162         int i;
 163         u32 *phy_regarray_table;
 164         u32 *agctab_array_table;
 165         u16 phy_reg_arraylen, agctab_arraylen;
 166         struct rtl_priv *rtlpriv = rtl_priv(hw);
 167         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 168         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 169
 170         if (IS_92C_SERIAL(rtlhal->version)) {
 171                 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
 172                 agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_2T].pdata;
 173                 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
 174                 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
 175         } else {
 176                 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
 177                 agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_1T].pdata;
 178                 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
 179                 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
 180         }
 181         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 182                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 183                         rtl_addr_delay(phy_regarray_table[i]);
 184                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 185                                       phy_regarray_table[i + 1]);
 186                         udelay(1);
 187                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 188                                  "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 189                                  phy_regarray_table[i],
 190                                  phy_regarray_table[i + 1]);
 191                 }
 192         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 193                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 194                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 195                                       agctab_array_table[i + 1]);
 196                         udelay(1);
 197                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 198                                  "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 199                                  agctab_array_table[i],
 200                                  agctab_array_table[i + 1]);
 201                 }
 202         }
 203         return true;
 204 }
 205
 206 bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 207                                               u8 configtype)
 208 {
 209         struct rtl_priv *rtlpriv = rtl_priv(hw);
 210         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 211         int i;
 212         u32 *phy_regarray_table_pg;
 213         u16 phy_regarray_pg_len;
 214
 215         rtlphy->pwrgroup_cnt = 0;
 216         phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
 217         phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
 218         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 219                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 220                         rtl_addr_delay(phy_regarray_table_pg[i]);
 221                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 222                                                   phy_regarray_table_pg[i],
 223                                                   phy_regarray_table_pg[i + 1],
 224                                                   phy_regarray_table_pg[i + 2]);
 225                 }
 226         } else {
 227                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 228                          "configtype != BaseBand_Config_PHY_REG\n");
 229         }
 230         return true;
 231 }
 232
 233 bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 234                                           enum radio_path rfpath)
 235 {
 236         int i;
 237         u32 *radioa_array_table;
 238         u32 *radiob_array_table;
 239         u16 radioa_arraylen, radiob_arraylen;
 240         struct rtl_priv *rtlpriv = rtl_priv(hw);
 241         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 242         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 243
 244         if (IS_92C_SERIAL(rtlhal->version)) {
 245                 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
 246                 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
 247                 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
 248                 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
 249                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 250                          "Radio_A:RTL8192CURADIOA_2TARRAY\n");
 251                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 252                          "Radio_B:RTL8192CU_RADIOB_2TARRAY\n");
 253         } else {
 254                 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
 255                 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
 256                 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
 257                 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
 258                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 259                          "Radio_A:RTL8192CU_RADIOA_1TARRAY\n");
 260                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 261                          "Radio_B:RTL8192CU_RADIOB_1TARRAY\n");
 262         }
 263         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 264         switch (rfpath) {
 265         case RF90_PATH_A:
 266                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 267                         rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 268                                         RFREG_OFFSET_MASK,
 269                                         radioa_array_table[i + 1]);
 270                 }
 271                 break;
 272         case RF90_PATH_B:
 273                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 274                         rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 275                                         RFREG_OFFSET_MASK,
 276                                         radiob_array_table[i + 1]);
 277                 }
 278                 break;
 279         case RF90_PATH_C:
 280         case RF90_PATH_D:
 281                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 282                          "switch case %#x not processed\n", rfpath);
 283                 break;
 284         default:
 285                 break;
 286         }
 287         return true;
 288 }
 289
 290 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 291 {
 292         struct rtl_priv *rtlpriv = rtl_priv(hw);
 293         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 294         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 295         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 296         u8 reg_bw_opmode;
 297         u8 reg_prsr_rsc;
 298
 299         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 300                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 301                  "20MHz" : "40MHz");
 302         if (is_hal_stop(rtlhal)) {
 303                 rtlphy->set_bwmode_inprogress = false;
 304                 return;
 305         }
 306         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 307         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 308         switch (rtlphy->current_chan_bw) {
 309         case HT_CHANNEL_WIDTH_20:
 310                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 311                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 312                 break;
 313         case HT_CHANNEL_WIDTH_20_40:
 314                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 315                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 316                 reg_prsr_rsc =
 317                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 318                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 319                 break;
 320         default:
 321                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 322                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 323                 break;
 324         }
 325         switch (rtlphy->current_chan_bw) {
 326         case HT_CHANNEL_WIDTH_20:
 327                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 328                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 329                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 330                 break;
 331         case HT_CHANNEL_WIDTH_20_40:
 332                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 333                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 334                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 335                               (mac->cur_40_prime_sc >> 1));
 336                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 337                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 338                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 339                               (mac->cur_40_prime_sc ==
 340                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 341                 break;
 342         default:
 343                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 344                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 345                 break;
 346         }
 347         rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 348         rtlphy->set_bwmode_inprogress = false;
 349         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 350 }
 351
 352 void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
 353 {
 354         struct rtl_priv *rtlpriv = rtl_priv(hw);
 355
 356         mutex_lock(&rtlpriv->io.bb_mutex);
 357         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 358         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 359         mutex_unlock(&rtlpriv->io.bb_mutex);
 360 }
 361
 362 void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 363 {
 364         u8 tmpreg;
 365         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 366         struct rtl_priv *rtlpriv = rtl_priv(hw);
 367
 368         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 369
 370         if ((tmpreg & 0x70) != 0)
 371                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 372         else
 373                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 374
 375         if ((tmpreg & 0x70) != 0) {
 376                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 377                 if (is2t)
 378                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 379                                                   MASK12BITS);
 380                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 381                               (rf_a_mode & 0x8FFFF) | 0x10000);
 382                 if (is2t)
 383                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 384                                       (rf_b_mode & 0x8FFFF) | 0x10000);
 385         }
 386         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 387         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 388         mdelay(100);
 389         if ((tmpreg & 0x70) != 0) {
 390                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 391                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 392                 if (is2t)
 393                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 394                                       rf_b_mode);
 395         } else {
 396                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 397         }
 398 }
 399
 400 static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 401                                             enum rf_pwrstate rfpwr_state)
 402 {
 403         struct rtl_priv *rtlpriv = rtl_priv(hw);
 404         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 405         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 406         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 407         bool bresult = true;
 408         u8 i, queue_id;
 409         struct rtl8192_tx_ring *ring = NULL;
 410
 411         switch (rfpwr_state) {
 412         case ERFON:
 413                 if ((ppsc->rfpwr_state == ERFOFF) &&
 414                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 415                         bool rtstatus;
 416                         u32 InitializeCount = 0;
 417
 418                         do {
 419                                 InitializeCount++;
 420                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 421                                          "IPS Set eRf nic enable\n");
 422                                 rtstatus = rtl_ps_enable_nic(hw);
 423                         } while (!rtstatus && (InitializeCount < 10));
 424                         RT_CLEAR_PS_LEVEL(ppsc,
 425                                           RT_RF_OFF_LEVL_HALT_NIC);
 426                 } else {
 427                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 428                                  "Set ERFON sleeped:%d ms\n",
 429                                  jiffies_to_msecs(jiffies -
 430                                                   ppsc->last_sleep_jiffies));
 431                         ppsc->last_awake_jiffies = jiffies;
 432                         rtl92ce_phy_set_rf_on(hw);
 433                 }
 434                 if (mac->link_state == MAC80211_LINKED) {
 435                         rtlpriv->cfg->ops->led_control(hw,
 436                                                        LED_CTL_LINK);
 437                 } else {
 438                         rtlpriv->cfg->ops->led_control(hw,
 439                                                        LED_CTL_NO_LINK);
 440                 }
 441                 break;
 442         case ERFOFF:
 443                 for (queue_id = 0, i = 0;
 444                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 445                         ring = &pcipriv->dev.tx_ring[queue_id];
 446                         if (skb_queue_len(&ring->queue) == 0 ||
 447                                 queue_id == BEACON_QUEUE) {
 448                                 queue_id++;
 449                                 continue;
 450                         } else {
 451                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 452                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 453                                          i + 1,
 454                                          queue_id,
 455                                          skb_queue_len(&ring->queue));
 456                                 udelay(10);
 457                                 i++;
 458                         }
 459                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 460                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 461                                          "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 462                                          MAX_DOZE_WAITING_TIMES_9x,
 463                                          queue_id,
 464                                          skb_queue_len(&ring->queue));
 465                                 break;
 466                         }
 467                 }
 468                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 469                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 470                                  "IPS Set eRf nic disable\n");
 471                         rtl_ps_disable_nic(hw);
 472                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 473                 } else {
 474                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 475                                 rtlpriv->cfg->ops->led_control(hw,
 476                                                          LED_CTL_NO_LINK);
 477                         } else {
 478                                 rtlpriv->cfg->ops->led_control(hw,
 479                                                          LED_CTL_POWER_OFF);
 480                         }
 481                 }
 482                 break;
 483         case ERFSLEEP:
 484                 if (ppsc->rfpwr_state == ERFOFF)
 485                         return false;
 486                 for (queue_id = 0, i = 0;
 487                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 488                         ring = &pcipriv->dev.tx_ring[queue_id];
 489                         if (skb_queue_len(&ring->queue) == 0) {
 490                                 queue_id++;
 491                                 continue;
 492                         } else {
 493                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 494                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 495                                          i + 1, queue_id,
 496                                          skb_queue_len(&ring->queue));
 497                                 udelay(10);
 498                                 i++;
 499                         }
 500                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 501                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 502                                          "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
 503                                          MAX_DOZE_WAITING_TIMES_9x,
 504                                          queue_id,
 505                                          skb_queue_len(&ring->queue));
 506                                 break;
 507                         }
 508                 }
 509                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 510                          "Set ERFSLEEP awaked:%d ms\n",
 511                          jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
 512                 ppsc->last_sleep_jiffies = jiffies;
 513                 _rtl92c_phy_set_rf_sleep(hw);
 514                 break;
 515         default:
 516                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 517                          "switch case %#x not processed\n", rfpwr_state);
 518                 bresult = false;
 519                 break;
 520         }
 521         if (bresult)
 522                 ppsc->rfpwr_state = rfpwr_state;
 523         return bresult;
 524 }
 525
 526 bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 527                                     enum rf_pwrstate rfpwr_state)
 528 {
 529         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 530         bool bresult = false;
 531
 532         if (rfpwr_state == ppsc->rfpwr_state)
 533                 return bresult;
 534         bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
 535         return bresult;
 536 }