drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "../core.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "rf.h"
  38 #include "dm.h"
  39 #include "fw.h"
  40 #include "hw.h"
  41 #include "table.h"
  42
  43 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
  44 {
  45         u32 i;
  46
  47         for (i = 0; i <= 31; i++) {
  48                 if (((bitmask >> i) & 0x1) == 1)
  49                         break;
  50         }
  51
  52         return i;
  53 }
  54
  55 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  56 {
  57         struct rtl_priv *rtlpriv = rtl_priv(hw);
  58         u32 returnvalue = 0, originalvalue, bitshift;
  59
  60         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  61                  regaddr, bitmask);
  62
  63         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  64         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  65         returnvalue = (originalvalue & bitmask) >> bitshift;
  66
  67         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  68                  bitmask, regaddr, originalvalue);
  69
  70         return returnvalue;
  71
  72 }
  73
  74 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
  75                            u32 data)
  76 {
  77         struct rtl_priv *rtlpriv = rtl_priv(hw);
  78         u32 originalvalue, bitshift;
  79
  80         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  81                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  82                  regaddr, bitmask, data);
  83
  84         if (bitmask != MASKDWORD) {
  85                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  86                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  87                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  88         }
  89
  90         rtl_write_dword(rtlpriv, regaddr, data);
  91
  92         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  93                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  94                  regaddr, bitmask, data);
  95
  96 }
  97
  98 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
  99                                       enum radio_path rfpath, u32 offset)
 100 {
 101
 102         struct rtl_priv *rtlpriv = rtl_priv(hw);
 103         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 104         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 105         u32 newoffset;
 106         u32 tmplong, tmplong2;
 107         u8 rfpi_enable = 0;
 108         u32 retvalue = 0;
 109
 110         offset &= 0x3f;
 111         newoffset = offset;
 112
 113         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 114
 115         if (rfpath == RF90_PATH_A)
 116                 tmplong2 = tmplong;
 117         else
 118                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 119
 120         tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
 121                         BLSSI_READEDGE;
 122
 123         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 124                       tmplong & (~BLSSI_READEDGE));
 125
 126         mdelay(1);
 127
 128         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 129         mdelay(1);
 130
 131         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
 132                       BLSSI_READEDGE);
 133         mdelay(1);
 134
 135         if (rfpath == RF90_PATH_A)
 136                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 137                                                 BIT(8));
 138         else if (rfpath == RF90_PATH_B)
 139                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 140                                                 BIT(8));
 141
 142         if (rfpi_enable)
 143                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 144                                          BLSSI_READBACK_DATA);
 145         else
 146                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 147                                          BLSSI_READBACK_DATA);
 148
 149         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 150                                  BLSSI_READBACK_DATA);
 151
 152         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 153                  rfpath, pphyreg->rf_rb, retvalue);
 154
 155         return retvalue;
 156
 157 }
 158
 159 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
 160                                         enum radio_path rfpath, u32 offset,
 161                                         u32 data)
 162 {
 163         struct rtl_priv *rtlpriv = rtl_priv(hw);
 164         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 165         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 166         u32 data_and_addr = 0;
 167         u32 newoffset;
 168
 169         offset &= 0x3f;
 170         newoffset = offset;
 171
 172         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 173         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 174
 175         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 176                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 177 }
 178
 179
 180 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 181                             u32 regaddr, u32 bitmask)
 182 {
 183         struct rtl_priv *rtlpriv = rtl_priv(hw);
 184         u32 original_value, readback_value, bitshift;
 185
 186         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 187                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 188                  regaddr, rfpath, bitmask);
 189
 190         spin_lock(&rtlpriv->locks.rf_lock);
 191
 192         original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
 193
 194         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 195         readback_value = (original_value & bitmask) >> bitshift;
 196
 197         spin_unlock(&rtlpriv->locks.rf_lock);
 198
 199         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 200                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 201                  regaddr, rfpath, bitmask, original_value);
 202
 203         return readback_value;
 204 }
 205
 206 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 207                            u32 regaddr, u32 bitmask, u32 data)
 208 {
 209         struct rtl_priv *rtlpriv = rtl_priv(hw);
 210         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 211         u32 original_value, bitshift;
 212
 213         if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
 214                 return;
 215
 216         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 217                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 218                  regaddr, bitmask, data, rfpath);
 219
 220         spin_lock(&rtlpriv->locks.rf_lock);
 221
 222         if (bitmask != RFREG_OFFSET_MASK) {
 223                 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
 224                                                             regaddr);
 225                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 226                 data = ((original_value & (~bitmask)) | (data << bitshift));
 227         }
 228
 229         _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
 230
 231         spin_unlock(&rtlpriv->locks.rf_lock);
 232
 233         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 234                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 235                  regaddr, bitmask, data, rfpath);
 236
 237 }
 238
 239 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
 240                                       u8 operation)
 241 {
 242         struct rtl_priv *rtlpriv = rtl_priv(hw);
 243         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 244
 245         if (!is_hal_stop(rtlhal)) {
 246                 switch (operation) {
 247                 case SCAN_OPT_BACKUP:
 248                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
 249                         break;
 250                 case SCAN_OPT_RESTORE:
 251                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
 252                         break;
 253                 default:
 254                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 255                                  "Unknown operation\n");
 256                         break;
 257                 }
 258         }
 259 }
 260
 261 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
 262                             enum nl80211_channel_type ch_type)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 267         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 268         u8 reg_bw_opmode;
 269
 270         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 271                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 272                  "20MHz" : "40MHz");
 273
 274         if (rtlphy->set_bwmode_inprogress)
 275                 return;
 276         if (is_hal_stop(rtlhal))
 277                 return;
 278
 279         rtlphy->set_bwmode_inprogress = true;
 280
 281         reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
 282         /* dummy read */
 283         rtl_read_byte(rtlpriv, RRSR + 2);
 284
 285         switch (rtlphy->current_chan_bw) {
 286         case HT_CHANNEL_WIDTH_20:
 287                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 288                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 289                 break;
 290         case HT_CHANNEL_WIDTH_20_40:
 291                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 292                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 293                 break;
 294         default:
 295                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 296                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 297                 break;
 298         }
 299
 300         switch (rtlphy->current_chan_bw) {
 301         case HT_CHANNEL_WIDTH_20:
 302                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 303                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 304
 305                 if (rtlhal->version >= VERSION_8192S_BCUT)
 306                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
 307                 break;
 308         case HT_CHANNEL_WIDTH_20_40:
 309                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 310                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 311
 312                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 313                                 (mac->cur_40_prime_sc >> 1));
 314                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 315
 316                 if (rtlhal->version >= VERSION_8192S_BCUT)
 317                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
 318                 break;
 319         default:
 320                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 321                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 322                 break;
 323         }
 324
 325         rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 326         rtlphy->set_bwmode_inprogress = false;
 327         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 328 }
 329
 330 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 331                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
 332                 u32 para1, u32 para2, u32 msdelay)
 333 {
 334         struct swchnlcmd *pcmd;
 335
 336         if (cmdtable == NULL) {
 337                 RT_ASSERT(false, "cmdtable cannot be NULL\n");
 338                 return false;
 339         }
 340
 341         if (cmdtableidx >= cmdtablesz)
 342                 return false;
 343
 344         pcmd = cmdtable + cmdtableidx;
 345         pcmd->cmdid = cmdid;
 346         pcmd->para1 = para1;
 347         pcmd->para2 = para2;
 348         pcmd->msdelay = msdelay;
 349
 350         return true;
 351 }
 352
 353 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 354              u8 channel, u8 *stage, u8 *step, u32 *delay)
 355 {
 356         struct rtl_priv *rtlpriv = rtl_priv(hw);
 357         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 358         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 359         u32 precommoncmdcnt;
 360         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 361         u32 postcommoncmdcnt;
 362         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 363         u32 rfdependcmdcnt;
 364         struct swchnlcmd *currentcmd = NULL;
 365         u8 rfpath;
 366         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 367
 368         precommoncmdcnt = 0;
 369         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 370                         MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 371         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 372                         MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 373
 374         postcommoncmdcnt = 0;
 375
 376         _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 377                         MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 378
 379         rfdependcmdcnt = 0;
 380
 381         RT_ASSERT((channel >= 1 && channel <= 14),
 382                   "invalid channel for Zebra: %d\n", channel);
 383
 384         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 385                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 386                                          RF_CHNLBW, channel, 10);
 387
 388         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 389                         MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
 390
 391         do {
 392                 switch (*stage) {
 393                 case 0:
 394                         currentcmd = &precommoncmd[*step];
 395                         break;
 396                 case 1:
 397                         currentcmd = &rfdependcmd[*step];
 398                         break;
 399                 case 2:
 400                         currentcmd = &postcommoncmd[*step];
 401                         break;
 402                 default:
 403                         return true;
 404                 }
 405
 406                 if (currentcmd->cmdid == CMDID_END) {
 407                         if ((*stage) == 2) {
 408                                 return true;
 409                         } else {
 410                                 (*stage)++;
 411                                 (*step) = 0;
 412                                 continue;
 413                         }
 414                 }
 415
 416                 switch (currentcmd->cmdid) {
 417                 case CMDID_SET_TXPOWEROWER_LEVEL:
 418                         rtl92s_phy_set_txpower(hw, channel);
 419                         break;
 420                 case CMDID_WRITEPORT_ULONG:
 421                         rtl_write_dword(rtlpriv, currentcmd->para1,
 422                                         currentcmd->para2);
 423                         break;
 424                 case CMDID_WRITEPORT_USHORT:
 425                         rtl_write_word(rtlpriv, currentcmd->para1,
 426                                        (u16)currentcmd->para2);
 427                         break;
 428                 case CMDID_WRITEPORT_UCHAR:
 429                         rtl_write_byte(rtlpriv, currentcmd->para1,
 430                                        (u8)currentcmd->para2);
 431                         break;
 432                 case CMDID_RF_WRITEREG:
 433                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 434                                 rtlphy->rfreg_chnlval[rfpath] =
 435                                          ((rtlphy->rfreg_chnlval[rfpath] &
 436                                          0xfffffc00) | currentcmd->para2);
 437                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 438                                               currentcmd->para1,
 439                                               RFREG_OFFSET_MASK,
 440                                               rtlphy->rfreg_chnlval[rfpath]);
 441                         }
 442                         break;
 443                 default:
 444                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 445                                  "switch case %#x not processed\n",
 446                                  currentcmd->cmdid);
 447                         break;
 448                 }
 449
 450                 break;
 451         } while (true);
 452
 453         (*delay) = currentcmd->msdelay;
 454         (*step)++;
 455         return false;
 456 }
 457
 458 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
 459 {
 460         struct rtl_priv *rtlpriv = rtl_priv(hw);
 461         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 462         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 463         u32 delay;
 464         bool ret;
 465
 466         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
 467                  rtlphy->current_channel);
 468
 469         if (rtlphy->sw_chnl_inprogress)
 470                 return 0;
 471
 472         if (rtlphy->set_bwmode_inprogress)
 473                 return 0;
 474
 475         if (is_hal_stop(rtlhal))
 476                 return 0;
 477
 478         rtlphy->sw_chnl_inprogress = true;
 479         rtlphy->sw_chnl_stage = 0;
 480         rtlphy->sw_chnl_step = 0;
 481
 482         do {
 483                 if (!rtlphy->sw_chnl_inprogress)
 484                         break;
 485
 486                 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
 487                                  rtlphy->current_channel,
 488                                  &rtlphy->sw_chnl_stage,
 489                                  &rtlphy->sw_chnl_step, &delay);
 490                 if (!ret) {
 491                         if (delay > 0)
 492                                 mdelay(delay);
 493                         else
 494                                 continue;
 495                 } else {
 496                         rtlphy->sw_chnl_inprogress = false;
 497                 }
 498                 break;
 499         } while (true);
 500
 501         rtlphy->sw_chnl_inprogress = false;
 502
 503         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 504
 505         return 1;
 506 }
 507
 508 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
 509 {
 510         struct rtl_priv *rtlpriv = rtl_priv(hw);
 511         u8 u1btmp;
 512
 513         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
 514         u1btmp |= BIT(0);
 515
 516         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
 517         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
 518         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
 519         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 520         udelay(100);
 521
 522         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 523         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
 524         udelay(10);
 525
 526         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 527         udelay(10);
 528
 529         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 530         udelay(10);
 531
 532         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 533
 534         /* we should chnge GPIO to input mode
 535          * this will drop away current about 25mA*/
 536         rtl8192se_gpiobit3_cfg_inputmode(hw);
 537 }
 538
 539 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
 540                                    enum rf_pwrstate rfpwr_state)
 541 {
 542         struct rtl_priv *rtlpriv = rtl_priv(hw);
 543         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 544         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 545         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 546         bool bresult = true;
 547         u8 i, queue_id;
 548         struct rtl8192_tx_ring *ring = NULL;
 549
 550         if (rfpwr_state == ppsc->rfpwr_state)
 551                 return false;
 552
 553         switch (rfpwr_state) {
 554         case ERFON:{
 555                         if ((ppsc->rfpwr_state == ERFOFF) &&
 556                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 557
 558                                 bool rtstatus;
 559                                 u32 InitializeCount = 0;
 560                                 do {
 561                                         InitializeCount++;
 562                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 563                                                  "IPS Set eRf nic enable\n");
 564                                         rtstatus = rtl_ps_enable_nic(hw);
 565                                 } while (!rtstatus && (InitializeCount < 10));
 566
 567                                 RT_CLEAR_PS_LEVEL(ppsc,
 568                                                   RT_RF_OFF_LEVL_HALT_NIC);
 569                         } else {
 570                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 571                                          "awake, sleeped:%d ms state_inap:%x\n",
 572                                          jiffies_to_msecs(jiffies -
 573                                                           ppsc->
 574                                                           last_sleep_jiffies),
 575                                          rtlpriv->psc.state_inap);
 576                                 ppsc->last_awake_jiffies = jiffies;
 577                                 rtl_write_word(rtlpriv, CMDR, 0x37FC);
 578                                 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
 579                                 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
 580                         }
 581
 582                         if (mac->link_state == MAC80211_LINKED)
 583                                 rtlpriv->cfg->ops->led_control(hw,
 584                                                          LED_CTL_LINK);
 585                         else
 586                                 rtlpriv->cfg->ops->led_control(hw,
 587                                                          LED_CTL_NO_LINK);
 588                         break;
 589                 }
 590         case ERFOFF:{
 591                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 592                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 593                                          "IPS Set eRf nic disable\n");
 594                                 rtl_ps_disable_nic(hw);
 595                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 596                         } else {
 597                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 598                                         rtlpriv->cfg->ops->led_control(hw,
 599                                                          LED_CTL_NO_LINK);
 600                                 else
 601                                         rtlpriv->cfg->ops->led_control(hw,
 602                                                          LED_CTL_POWER_OFF);
 603                         }
 604                         break;
 605                 }
 606         case ERFSLEEP:
 607                         if (ppsc->rfpwr_state == ERFOFF)
 608                                 return false;
 609
 610                         for (queue_id = 0, i = 0;
 611                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 612                                 ring = &pcipriv->dev.tx_ring[queue_id];
 613                                 if (skb_queue_len(&ring->queue) == 0 ||
 614                                         queue_id == BEACON_QUEUE) {
 615                                         queue_id++;
 616                                         continue;
 617                                 } else {
 618                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 619                                                  "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
 620                                                  i + 1, queue_id,
 621                                                  skb_queue_len(&ring->queue));
 622
 623                                         udelay(10);
 624                                         i++;
 625                                 }
 626
 627                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 628                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 629                                                  "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 630                                                  MAX_DOZE_WAITING_TIMES_9x,
 631                                                  queue_id,
 632                                                  skb_queue_len(&ring->queue));
 633                                         break;
 634                                 }
 635                         }
 636
 637                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 638                                  "Set ERFSLEEP awaked:%d ms\n",
 639                                  jiffies_to_msecs(jiffies -
 640                                                   ppsc->last_awake_jiffies));
 641
 642                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 643                                  "sleep awaked:%d ms state_inap:%x\n",
 644                                  jiffies_to_msecs(jiffies -
 645                                                   ppsc->last_awake_jiffies),
 646                                  rtlpriv->psc.state_inap);
 647                         ppsc->last_sleep_jiffies = jiffies;
 648                         _rtl92se_phy_set_rf_sleep(hw);
 649                         break;
 650         default:
 651                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 652                          "switch case %#x not processed\n", rfpwr_state);
 653                 bresult = false;
 654                 break;
 655         }
 656
 657         if (bresult)
 658                 ppsc->rfpwr_state = rfpwr_state;
 659
 660         return bresult;
 661 }
 662
 663 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
 664                                                  enum radio_path rfpath)
 665 {
 666         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 667         bool rtstatus = true;
 668         u32 tmpval = 0;
 669
 670         /* If inferiority IC, we have to increase the PA bias current */
 671         if (rtlhal->ic_class != IC_INFERIORITY_A) {
 672                 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
 673                 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
 674         }
 675
 676         return rtstatus;
 677 }
 678
 679 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 680                 u32 reg_addr, u32 bitmask, u32 data)
 681 {
 682         struct rtl_priv *rtlpriv = rtl_priv(hw);
 683         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 684         int index;
 685
 686         if (reg_addr == RTXAGC_RATE18_06)
 687                 index = 0;
 688         else if (reg_addr == RTXAGC_RATE54_24)
 689                 index = 1;
 690         else if (reg_addr == RTXAGC_CCK_MCS32)
 691                 index = 6;
 692         else if (reg_addr == RTXAGC_MCS03_MCS00)
 693                 index = 2;
 694         else if (reg_addr == RTXAGC_MCS07_MCS04)
 695                 index = 3;
 696         else if (reg_addr == RTXAGC_MCS11_MCS08)
 697                 index = 4;
 698         else if (reg_addr == RTXAGC_MCS15_MCS12)
 699                 index = 5;
 700         else
 701                 return;
 702
 703         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 704         if (index == 5)
 705                 rtlphy->pwrgroup_cnt++;
 706 }
 707
 708 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
 709 {
 710         struct rtl_priv *rtlpriv = rtl_priv(hw);
 711         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 712
 713         /*RF Interface Sowrtware Control */
 714         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 715         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 716         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 717         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 718
 719         /* RF Interface Readback Value */
 720         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 721         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 722         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 723         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 724
 725         /* RF Interface Output (and Enable) */
 726         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 727         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 728         rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
 729         rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
 730
 731         /* RF Interface (Output and)  Enable */
 732         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 733         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 734         rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
 735         rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
 736
 737         /* Addr of LSSI. Wirte RF register by driver */
 738         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 739                                                  RFPGA0_XA_LSSIPARAMETER;
 740         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 741                                                  RFPGA0_XB_LSSIPARAMETER;
 742         rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
 743                                                  RFPGA0_XC_LSSIPARAMETER;
 744         rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
 745                                                  RFPGA0_XD_LSSIPARAMETER;
 746
 747         /* RF parameter */
 748         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 749         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 750         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 751         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 752
 753         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 754         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 755         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 756         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 757         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 758
 759         /* Tranceiver A~D HSSI Parameter-1 */
 760         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 761         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 762         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
 763         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
 764
 765         /* Tranceiver A~D HSSI Parameter-2 */
 766         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 767         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 768         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
 769         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
 770
 771         /* RF switch Control */
 772         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 773         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 774         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 775         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 776
 777         /* AGC control 1  */
 778         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 779         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 780         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 781         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 782
 783         /* AGC control 2  */
 784         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 785         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 786         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 787         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 788
 789         /* RX AFE control 1  */
 790         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 791         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 792         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 793         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 794
 795         /* RX AFE control 1   */
 796         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 797         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 798         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 799         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 800
 801         /* Tx AFE control 1  */
 802         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 803         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 804         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 805         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 806
 807         /* Tx AFE control 2  */
 808         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 809         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 810         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 811         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 812
 813         /* Tranceiver LSSI Readback */
 814         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 815         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 816         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 817         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 818
 819         /* Tranceiver LSSI Readback PI mode  */
 820         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 821         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 822 }
 823
 824
 825 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
 826 {
 827         int i;
 828         u32 *phy_reg_table;
 829         u32 *agc_table;
 830         u16 phy_reg_len, agc_len;
 831
 832         agc_len = AGCTAB_ARRAYLENGTH;
 833         agc_table = rtl8192seagctab_array;
 834         /* Default RF_type: 2T2R */
 835         phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
 836         phy_reg_table = rtl8192sephy_reg_2t2rarray;
 837
 838         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 839                 for (i = 0; i < phy_reg_len; i = i + 2) {
 840                         rtl_addr_delay(phy_reg_table[i]);
 841
 842                         /* Add delay for ECS T20 & LG malow platform, */
 843                         udelay(1);
 844
 845                         rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
 846                                         phy_reg_table[i + 1]);
 847                 }
 848         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 849                 for (i = 0; i < agc_len; i = i + 2) {
 850                         rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
 851                                         agc_table[i + 1]);
 852
 853                         /* Add delay for ECS T20 & LG malow platform */
 854                         udelay(1);
 855                 }
 856         }
 857
 858         return true;
 859 }
 860
 861 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
 862                                           u8 configtype)
 863 {
 864         struct rtl_priv *rtlpriv = rtl_priv(hw);
 865         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 866         u32 *phy_regarray2xtxr_table;
 867         u16 phy_regarray2xtxr_len;
 868         int i;
 869
 870         if (rtlphy->rf_type == RF_1T1R) {
 871                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
 872                 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
 873         } else if (rtlphy->rf_type == RF_1T2R) {
 874                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
 875                 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
 876         } else {
 877                 return false;
 878         }
 879
 880         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 881                 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
 882                         rtl_addr_delay(phy_regarray2xtxr_table[i]);
 883
 884                         rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
 885                                 phy_regarray2xtxr_table[i + 1],
 886                                 phy_regarray2xtxr_table[i + 2]);
 887                 }
 888         }
 889
 890         return true;
 891 }
 892
 893 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
 894                                           u8 configtype)
 895 {
 896         int i;
 897         u32 *phy_table_pg;
 898         u16 phy_pg_len;
 899
 900         phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
 901         phy_table_pg = rtl8192sephy_reg_array_pg;
 902
 903         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 904                 for (i = 0; i < phy_pg_len; i = i + 3) {
 905                         rtl_addr_delay(phy_table_pg[i]);
 906
 907                         _rtl92s_store_pwrindex_diffrate_offset(hw,
 908                                         phy_table_pg[i],
 909                                         phy_table_pg[i + 1],
 910                                         phy_table_pg[i + 2]);
 911                         rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
 912                                         phy_table_pg[i + 1],
 913                                         phy_table_pg[i + 2]);
 914                 }
 915         }
 916
 917         return true;
 918 }
 919
 920 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
 921 {
 922         struct rtl_priv *rtlpriv = rtl_priv(hw);
 923         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 924         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 925         bool rtstatus = true;
 926
 927         /* 1. Read PHY_REG.TXT BB INIT!! */
 928         /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
 929         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
 930             rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
 931                 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
 932
 933                 if (rtlphy->rf_type != RF_2T2R &&
 934                     rtlphy->rf_type != RF_2T2R_GREEN)
 935                         /* so we should reconfig BB reg with the right
 936                          * PHY parameters. */
 937                         rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
 938                                                 BASEBAND_CONFIG_PHY_REG);
 939         } else {
 940                 rtstatus = false;
 941         }
 942
 943         if (!rtstatus) {
 944                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 945                          "Write BB Reg Fail!!\n");
 946                 goto phy_BB8190_Config_ParaFile_Fail;
 947         }
 948
 949         /* 2. If EEPROM or EFUSE autoload OK, We must config by
 950          *    PHY_REG_PG.txt */
 951         if (rtlefuse->autoload_failflag == false) {
 952                 rtlphy->pwrgroup_cnt = 0;
 953
 954                 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
 955                                                  BASEBAND_CONFIG_PHY_REG);
 956         }
 957         if (!rtstatus) {
 958                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 959                          "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
 960                 goto phy_BB8190_Config_ParaFile_Fail;
 961         }
 962
 963         /* 3. BB AGC table Initialization */
 964         rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
 965
 966         if (!rtstatus) {
 967                 pr_err("%s(): AGC Table Fail\n", __func__);
 968                 goto phy_BB8190_Config_ParaFile_Fail;
 969         }
 970
 971         /* Check if the CCK HighPower is turned ON. */
 972         /* This is used to calculate PWDB. */
 973         rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
 974                         RFPGA0_XA_HSSIPARAMETER2, 0x200));
 975
 976 phy_BB8190_Config_ParaFile_Fail:
 977         return rtstatus;
 978 }
 979
 980 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
 981 {
 982         struct rtl_priv *rtlpriv = rtl_priv(hw);
 983         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 984         int i;
 985         bool rtstatus = true;
 986         u32 *radio_a_table;
 987         u32 *radio_b_table;
 988         u16 radio_a_tblen, radio_b_tblen;
 989
 990         radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
 991         radio_a_table = rtl8192seradioa_1t_array;
 992
 993         /* Using Green mode array table for RF_2T2R_GREEN */
 994         if (rtlphy->rf_type == RF_2T2R_GREEN) {
 995                 radio_b_table = rtl8192seradiob_gm_array;
 996                 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
 997         } else {
 998                 radio_b_table = rtl8192seradiob_array;
 999                 radio_b_tblen = RADIOB_ARRAYLENGTH;
1000         }
1001
1002         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1003         rtstatus = true;
1004
1005         switch (rfpath) {
1006         case RF90_PATH_A:
1007                 for (i = 0; i < radio_a_tblen; i = i + 2) {
1008                         rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
1009                                         MASK20BITS, radio_a_table[i + 1]);
1010
1011                 }
1012
1013                 /* PA Bias current for inferiority IC */
1014                 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1015                 break;
1016         case RF90_PATH_B:
1017                 for (i = 0; i < radio_b_tblen; i = i + 2) {
1018                         rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
1019                                         MASK20BITS, radio_b_table[i + 1]);
1020                 }
1021                 break;
1022         case RF90_PATH_C:
1023                 ;
1024                 break;
1025         case RF90_PATH_D:
1026                 ;
1027                 break;
1028         default:
1029                 break;
1030         }
1031
1032         return rtstatus;
1033 }
1034
1035
1036 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1037 {
1038         struct rtl_priv *rtlpriv = rtl_priv(hw);
1039         u32 i;
1040         u32 arraylength;
1041         u32 *ptraArray;
1042
1043         arraylength = MAC_2T_ARRAYLENGTH;
1044         ptraArray = rtl8192semac_2t_array;
1045
1046         for (i = 0; i < arraylength; i = i + 2)
1047                 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1048
1049         return true;
1050 }
1051
1052
1053 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1054 {
1055         struct rtl_priv *rtlpriv = rtl_priv(hw);
1056         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1057         bool rtstatus = true;
1058         u8 pathmap, index, rf_num = 0;
1059         u8 path1, path2;
1060
1061         _rtl92s_phy_init_register_definition(hw);
1062
1063         /* Config BB and AGC */
1064         rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1065
1066
1067         /* Check BB/RF confiuration setting. */
1068         /* We only need to configure RF which is turned on. */
1069         path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1070         mdelay(10);
1071         path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1072         pathmap = path1 | path2;
1073
1074         rtlphy->rf_pathmap = pathmap;
1075         for (index = 0; index < 4; index++) {
1076                 if ((pathmap >> index) & 0x1)
1077                         rf_num++;
1078         }
1079
1080         if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1081             (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1082             (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1083             (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1084                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1085                          "RF_Type(%x) does not match RF_Num(%x)!!\n",
1086                          rtlphy->rf_type, rf_num);
1087                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1088                          "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1089                          path1, path2, pathmap);
1090         }
1091
1092         return rtstatus;
1093 }
1094
1095 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1096 {
1097         struct rtl_priv *rtlpriv = rtl_priv(hw);
1098         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1099
1100         /* Initialize general global value */
1101         if (rtlphy->rf_type == RF_1T1R)
1102                 rtlphy->num_total_rfpath = 1;
1103         else
1104                 rtlphy->num_total_rfpath = 2;
1105
1106         /* Config BB and RF */
1107         return rtl92s_phy_rf6052_config(hw);
1108 }
1109
1110 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1111 {
1112         struct rtl_priv *rtlpriv = rtl_priv(hw);
1113         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1114
1115         /* read rx initial gain */
1116         rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1117                         ROFDM0_XAAGCCORE1, MASKBYTE0);
1118         rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1119                         ROFDM0_XBAGCCORE1, MASKBYTE0);
1120         rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1121                         ROFDM0_XCAGCCORE1, MASKBYTE0);
1122         rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1123                         ROFDM0_XDAGCCORE1, MASKBYTE0);
1124         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1125                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1126                  rtlphy->default_initialgain[0],
1127                  rtlphy->default_initialgain[1],
1128                  rtlphy->default_initialgain[2],
1129                  rtlphy->default_initialgain[3]);
1130
1131         /* read framesync */
1132         rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1133         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1134                                               MASKDWORD);
1135         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1136                  "Default framesync (0x%x) = 0x%x\n",
1137                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
1138
1139 }
1140
1141 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1142                                           u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1143 {
1144         struct rtl_priv *rtlpriv = rtl_priv(hw);
1145         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1146         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1147         u8 index = (channel - 1);
1148
1149         /* 1. CCK */
1150         /* RF-A */
1151         cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1152         /* RF-B */
1153         cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1154
1155         /* 2. OFDM for 1T or 2T */
1156         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1157                 /* Read HT 40 OFDM TX power */
1158                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1159                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1160         } else if (rtlphy->rf_type == RF_2T2R) {
1161                 /* Read HT 40 OFDM TX power */
1162                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1163                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1164         } else {
1165                 ofdmpowerLevel[0] = 0;
1166                 ofdmpowerLevel[1] = 0;
1167         }
1168 }
1169
1170 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1171                 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1172 {
1173         struct rtl_priv *rtlpriv = rtl_priv(hw);
1174         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1175
1176         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1177         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1178 }
1179
1180 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1181 {
1182         struct rtl_priv *rtlpriv = rtl_priv(hw);
1183         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1184         /* [0]:RF-A, [1]:RF-B */
1185         u8 cckpowerlevel[2], ofdmpowerLevel[2];
1186
1187         if (!rtlefuse->txpwr_fromeprom)
1188                 return;
1189
1190         /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1191          * but the RF-B Tx Power must be calculated by the antenna diff.
1192          * So we have to rewrite Antenna gain offset register here.
1193          * Please refer to BB register 0x80c
1194          * 1. For CCK.
1195          * 2. For OFDM 1T or 2T */
1196         _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1197                         &ofdmpowerLevel[0]);
1198
1199         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1200                  "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1201                  channel, cckpowerlevel[0], cckpowerlevel[1],
1202                  ofdmpowerLevel[0], ofdmpowerLevel[1]);
1203
1204         _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1205                         &ofdmpowerLevel[0]);
1206
1207         rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1208         rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1209
1210 }
1211
1212 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1213 {
1214         struct rtl_priv *rtlpriv = rtl_priv(hw);
1215         u16 pollingcnt = 10000;
1216         u32 tmpvalue;
1217
1218         /* Make sure that CMD IO has be accepted by FW. */
1219         do {
1220                 udelay(10);
1221
1222                 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1223                 if (tmpvalue == 0)
1224                         break;
1225         } while (--pollingcnt);
1226
1227         if (pollingcnt == 0)
1228                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1229 }
1230
1231
1232 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1233 {
1234         struct rtl_priv *rtlpriv = rtl_priv(hw);
1235         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1236         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1237         u32 input, current_aid = 0;
1238
1239         if (is_hal_stop(rtlhal))
1240                 return;
1241
1242         if (hal_get_firmwareversion(rtlpriv) < 0x34)
1243                 goto skip;
1244         /* We re-map RA related CMD IO to combinational ones */
1245         /* if FW version is v.52 or later. */
1246         switch (rtlhal->current_fwcmd_io) {
1247         case FW_CMD_RA_REFRESH_N:
1248                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1249                 break;
1250         case FW_CMD_RA_REFRESH_BG:
1251                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1252                 break;
1253         default:
1254                 break;
1255         }
1256
1257 skip:
1258         switch (rtlhal->current_fwcmd_io) {
1259         case FW_CMD_RA_RESET:
1260                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1261                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1262                 rtl92s_phy_chk_fwcmd_iodone(hw);
1263                 break;
1264         case FW_CMD_RA_ACTIVE:
1265                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1266                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1267                 rtl92s_phy_chk_fwcmd_iodone(hw);
1268                 break;
1269         case FW_CMD_RA_REFRESH_N:
1270                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1271                 input = FW_RA_REFRESH;
1272                 rtl_write_dword(rtlpriv, WFM5, input);
1273                 rtl92s_phy_chk_fwcmd_iodone(hw);
1274                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1275                 rtl92s_phy_chk_fwcmd_iodone(hw);
1276                 break;
1277         case FW_CMD_RA_REFRESH_BG:
1278                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1279                          "FW_CMD_RA_REFRESH_BG\n");
1280                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1281                 rtl92s_phy_chk_fwcmd_iodone(hw);
1282                 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1283                 rtl92s_phy_chk_fwcmd_iodone(hw);
1284                 break;
1285         case FW_CMD_RA_REFRESH_N_COMB:
1286                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1287                          "FW_CMD_RA_REFRESH_N_COMB\n");
1288                 input = FW_RA_IOT_N_COMB;
1289                 rtl_write_dword(rtlpriv, WFM5, input);
1290                 rtl92s_phy_chk_fwcmd_iodone(hw);
1291                 break;
1292         case FW_CMD_RA_REFRESH_BG_COMB:
1293                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1294                          "FW_CMD_RA_REFRESH_BG_COMB\n");
1295                 input = FW_RA_IOT_BG_COMB;
1296                 rtl_write_dword(rtlpriv, WFM5, input);
1297                 rtl92s_phy_chk_fwcmd_iodone(hw);
1298                 break;
1299         case FW_CMD_IQK_ENABLE:
1300                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1301                 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1302                 rtl92s_phy_chk_fwcmd_iodone(hw);
1303                 break;
1304         case FW_CMD_PAUSE_DM_BY_SCAN:
1305                 /* Lower initial gain */
1306                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1307                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1308                 /* CCA threshold */
1309                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1310                 break;
1311         case FW_CMD_RESUME_DM_BY_SCAN:
1312                 /* CCA threshold */
1313                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1314                 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1315                 break;
1316         case FW_CMD_HIGH_PWR_DISABLE:
1317                 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1318                         break;
1319
1320                 /* Lower initial gain */
1321                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1322                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1323                 /* CCA threshold */
1324                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1325                 break;
1326         case FW_CMD_HIGH_PWR_ENABLE:
1327                 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1328                         rtlpriv->dm.dynamic_txpower_enable)
1329                         break;
1330
1331                 /* CCA threshold */
1332                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1333                 break;
1334         case FW_CMD_LPS_ENTER:
1335                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1336                 current_aid = rtlpriv->mac80211.assoc_id;
1337                 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1338                                 ((current_aid | 0xc000) << 8)));
1339                 rtl92s_phy_chk_fwcmd_iodone(hw);
1340                 /* FW set TXOP disable here, so disable EDCA
1341                  * turbo mode until driver leave LPS */
1342                 break;
1343         case FW_CMD_LPS_LEAVE:
1344                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1345                 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1346                 rtl92s_phy_chk_fwcmd_iodone(hw);
1347                 break;
1348         case FW_CMD_ADD_A2_ENTRY:
1349                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1350                 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1351                 rtl92s_phy_chk_fwcmd_iodone(hw);
1352                 break;
1353         case FW_CMD_CTRL_DM_BY_DRIVER:
1354                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1355                          "FW_CMD_CTRL_DM_BY_DRIVER\n");
1356                 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1357                 rtl92s_phy_chk_fwcmd_iodone(hw);
1358                 break;
1359
1360         default:
1361                 break;
1362         }
1363
1364         rtl92s_phy_chk_fwcmd_iodone(hw);
1365
1366         /* Clear FW CMD operation flag. */
1367         rtlhal->set_fwcmd_inprogress = false;
1368 }
1369
1370 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1371 {
1372         struct rtl_priv *rtlpriv = rtl_priv(hw);
1373         struct dig_t *digtable = &rtlpriv->dm_digtable;
1374         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1375         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1376         u32     fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1377         u16     fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1378         bool postprocessing = false;
1379
1380         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1381                  "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1382                  fw_cmdio, rtlhal->set_fwcmd_inprogress);
1383
1384         do {
1385                 /* We re-map to combined FW CMD ones if firmware version */
1386                 /* is v.53 or later. */
1387                 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1388                         switch (fw_cmdio) {
1389                         case FW_CMD_RA_REFRESH_N:
1390                                 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1391                                 break;
1392                         case FW_CMD_RA_REFRESH_BG:
1393                                 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1394                                 break;
1395                         default:
1396                                 break;
1397                         }
1398                 } else {
1399                         if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1400                             (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1401                             (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1402                                 postprocessing = true;
1403                                 break;
1404                         }
1405                 }
1406
1407                 /* If firmware version is v.62 or later,
1408                  * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1409                 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1410                         if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1411                                 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1412                 }
1413
1414
1415                 /* We shall revise all FW Cmd IO into Reg0x364
1416                  * DM map table in the future. */
1417                 switch (fw_cmdio) {
1418                 case FW_CMD_RA_INIT:
1419                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1420                         fw_cmdmap |= FW_RA_INIT_CTL;
1421                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1422                         /* Clear control flag to sync with FW. */
1423                         FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1424                         break;
1425                 case FW_CMD_DIG_DISABLE:
1426                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1427                                  "Set DIG disable!!\n");
1428                         fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1429                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1430                         break;
1431                 case FW_CMD_DIG_ENABLE:
1432                 case FW_CMD_DIG_RESUME:
1433                         if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1434                                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1435                                          "Set DIG enable or resume!!\n");
1436                                 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1437                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1438                         }
1439                         break;
1440                 case FW_CMD_DIG_HALT:
1441                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1442                                  "Set DIG halt!!\n");
1443                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1444                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1445                         break;
1446                 case FW_CMD_TXPWR_TRACK_THERMAL: {
1447                         u8      thermalval = 0;
1448                         fw_cmdmap |= FW_PWR_TRK_CTL;
1449
1450                         /* Clear FW parameter in terms of thermal parts. */
1451                         fw_param &= FW_PWR_TRK_PARAM_CLR;
1452
1453                         thermalval = rtlpriv->dm.thermalvalue;
1454                         fw_param |= ((thermalval << 24) |
1455                                      (rtlefuse->thermalmeter[0] << 16));
1456
1457                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1458                                  "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1459                                  fw_cmdmap, fw_param);
1460
1461                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1462                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1463
1464                         /* Clear control flag to sync with FW. */
1465                         FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1466                         }
1467                         break;
1468                 /* The following FW CMDs are only compatible to
1469                  * v.53 or later. */
1470                 case FW_CMD_RA_REFRESH_N_COMB:
1471                         fw_cmdmap |= FW_RA_N_CTL;
1472
1473                         /* Clear RA BG mode control. */
1474                         fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1475
1476                         /* Clear FW parameter in terms of RA parts. */
1477                         fw_param &= FW_RA_PARAM_CLR;
1478
1479                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1480                                  "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1481                                  fw_cmdmap, fw_param);
1482
1483                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1484                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1485
1486                         /* Clear control flag to sync with FW. */
1487                         FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1488                         break;
1489                 case FW_CMD_RA_REFRESH_BG_COMB:
1490                         fw_cmdmap |= FW_RA_BG_CTL;
1491
1492                         /* Clear RA n-mode control. */
1493                         fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1494                         /* Clear FW parameter in terms of RA parts. */
1495                         fw_param &= FW_RA_PARAM_CLR;
1496
1497                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1498                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1499
1500                         /* Clear control flag to sync with FW. */
1501                         FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1502                         break;
1503                 case FW_CMD_IQK_ENABLE:
1504                         fw_cmdmap |= FW_IQK_CTL;
1505                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1506                         /* Clear control flag to sync with FW. */
1507                         FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1508                         break;
1509                 /* The following FW CMD is compatible to v.62 or later.  */
1510                 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1511                         fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1512                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1513                         break;
1514                 /*  The followed FW Cmds needs post-processing later. */
1515                 case FW_CMD_RESUME_DM_BY_SCAN:
1516                         fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1517                                       FW_HIGH_PWR_ENABLE_CTL |
1518                                       FW_SS_CTL);
1519
1520                         if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1521                                 !digtable->dig_enable_flag)
1522                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1523
1524                         if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1525                             rtlpriv->dm.dynamic_txpower_enable)
1526                                 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1527
1528                         if ((digtable->dig_ext_port_stage ==
1529                             DIG_EXT_PORT_STAGE_0) ||
1530                             (digtable->dig_ext_port_stage ==
1531                             DIG_EXT_PORT_STAGE_1))
1532                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1533
1534                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1535                         postprocessing = true;
1536                         break;
1537                 case FW_CMD_PAUSE_DM_BY_SCAN:
1538                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1539                                        FW_HIGH_PWR_ENABLE_CTL |
1540                                        FW_SS_CTL);
1541                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1542                         postprocessing = true;
1543                         break;
1544                 case FW_CMD_HIGH_PWR_DISABLE:
1545                         fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1546                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1547                         postprocessing = true;
1548                         break;
1549                 case FW_CMD_HIGH_PWR_ENABLE:
1550                         if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1551                             !rtlpriv->dm.dynamic_txpower_enable) {
1552                                 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1553                                               FW_SS_CTL);
1554                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1555                                 postprocessing = true;
1556                         }
1557                         break;
1558                 case FW_CMD_DIG_MODE_FA:
1559                         fw_cmdmap |= FW_FA_CTL;
1560                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1561                         break;
1562                 case FW_CMD_DIG_MODE_SS:
1563                         fw_cmdmap &= ~FW_FA_CTL;
1564                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1565                         break;
1566                 case FW_CMD_PAPE_CONTROL:
1567                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1568                                  "[FW CMD] Set PAPE Control\n");
1569                         fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1570
1571                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1572                         break;
1573                 default:
1574                         /* Pass to original FW CMD processing callback
1575                          * routine. */
1576                         postprocessing = true;
1577                         break;
1578                 }
1579         } while (false);
1580
1581         /* We shall post processing these FW CMD if
1582          * variable postprocessing is set.
1583          */
1584         if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1585                 rtlhal->set_fwcmd_inprogress = true;
1586                 /* Update current FW Cmd for callback use. */
1587                 rtlhal->current_fwcmd_io = fw_cmdio;
1588         } else {
1589                 return false;
1590         }
1591
1592         _rtl92s_phy_set_fwcmd_io(hw);
1593         return true;
1594 }
1595
1596 static  void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1597 {
1598         struct rtl_priv *rtlpriv = rtl_priv(hw);
1599         u32     delay = 100;
1600         u8      regu1;
1601
1602         regu1 = rtl_read_byte(rtlpriv, 0x554);
1603         while ((regu1 & BIT(5)) && (delay > 0)) {
1604                 regu1 = rtl_read_byte(rtlpriv, 0x554);
1605                 delay--;
1606                 /* We delay only 50us to prevent
1607                  * being scheduled out. */
1608                 udelay(50);
1609         }
1610 }
1611
1612 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1613 {
1614         struct rtl_priv *rtlpriv = rtl_priv(hw);
1615         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1616
1617         /* The way to be capable to switch clock request
1618          * when the PG setting does not support clock request.
1619          * This is the backdoor solution to switch clock
1620          * request before ASPM or D3. */
1621         rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1622         rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1623
1624         /* Switch EPHY parameter!!!! */
1625         rtl_write_word(rtlpriv, 0x550, 0x1000);
1626         rtl_write_byte(rtlpriv, 0x554, 0x20);
1627         _rtl92s_phy_check_ephy_switchready(hw);
1628
1629         rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1630         rtl_write_byte(rtlpriv, 0x554, 0x3e);
1631         _rtl92s_phy_check_ephy_switchready(hw);
1632
1633         rtl_write_word(rtlpriv, 0x550, 0xff80);
1634         rtl_write_byte(rtlpriv, 0x554, 0x39);
1635         _rtl92s_phy_check_ephy_switchready(hw);
1636
1637         /* Delay L1 enter time */
1638         if (ppsc->support_aspm && !ppsc->support_backdoor)
1639                 rtl_write_byte(rtlpriv, 0x560, 0x40);
1640         else
1641                 rtl_write_byte(rtlpriv, 0x560, 0x00);
1642
1643 }
1644
1645 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1646 {
1647         struct rtl_priv *rtlpriv = rtl_priv(hw);
1648         u32 new_bcn_num = 0;
1649
1650         if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1651                 /* Fw v.51 and later. */
1652                 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1653                                 (beaconinterval << 8));
1654         } else {
1655                 new_bcn_num = beaconinterval * 32 - 64;
1656                 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1657                 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1658         }
1659 }