drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../pci.h"
  28 #include "../ps.h"
  29 #include "../core.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "rf.h"
  34 #include "dm.h"
  35 #include "fw.h"
  36 #include "hw.h"
  37 #include "table.h"
  38
  39 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
  40 {
  41         u32 i;
  42
  43         for (i = 0; i <= 31; i++) {
  44                 if (((bitmask >> i) & 0x1) == 1)
  45                         break;
  46         }
  47
  48         return i;
  49 }
  50
  51 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  52 {
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54         u32 returnvalue = 0, originalvalue, bitshift;
  55
  56         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  57                  regaddr, bitmask);
  58
  59         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  60         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  61         returnvalue = (originalvalue & bitmask) >> bitshift;
  62
  63         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  64                  bitmask, regaddr, originalvalue);
  65
  66         return returnvalue;
  67
  68 }
  69
  70 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
  71                            u32 data)
  72 {
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74         u32 originalvalue, bitshift;
  75
  76         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  77                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  78                  regaddr, bitmask, data);
  79
  80         if (bitmask != MASKDWORD) {
  81                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  82                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  83                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  84         }
  85
  86         rtl_write_dword(rtlpriv, regaddr, data);
  87
  88         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  89                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  90                  regaddr, bitmask, data);
  91
  92 }
  93
  94 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
  95                                       enum radio_path rfpath, u32 offset)
  96 {
  97
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 100         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 101         u32 newoffset;
 102         u32 tmplong, tmplong2;
 103         u8 rfpi_enable = 0;
 104         u32 retvalue = 0;
 105
 106         offset &= 0x3f;
 107         newoffset = offset;
 108
 109         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 110
 111         if (rfpath == RF90_PATH_A)
 112                 tmplong2 = tmplong;
 113         else
 114                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 115
 116         tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
 117                         BLSSI_READEDGE;
 118
 119         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 120                       tmplong & (~BLSSI_READEDGE));
 121
 122         mdelay(1);
 123
 124         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 125         mdelay(1);
 126
 127         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
 128                       BLSSI_READEDGE);
 129         mdelay(1);
 130
 131         if (rfpath == RF90_PATH_A)
 132                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 133                                                 BIT(8));
 134         else if (rfpath == RF90_PATH_B)
 135                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 136                                                 BIT(8));
 137
 138         if (rfpi_enable)
 139                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 140                                          BLSSI_READBACK_DATA);
 141         else
 142                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 143                                          BLSSI_READBACK_DATA);
 144
 145         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 146                                  BLSSI_READBACK_DATA);
 147
 148         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 149                  rfpath, pphyreg->rf_rb, retvalue);
 150
 151         return retvalue;
 152
 153 }
 154
 155 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
 156                                         enum radio_path rfpath, u32 offset,
 157                                         u32 data)
 158 {
 159         struct rtl_priv *rtlpriv = rtl_priv(hw);
 160         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 161         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 162         u32 data_and_addr = 0;
 163         u32 newoffset;
 164
 165         offset &= 0x3f;
 166         newoffset = offset;
 167
 168         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 169         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 170
 171         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 172                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 173 }
 174
 175
 176 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 177                             u32 regaddr, u32 bitmask)
 178 {
 179         struct rtl_priv *rtlpriv = rtl_priv(hw);
 180         u32 original_value, readback_value, bitshift;
 181
 182         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 183                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 184                  regaddr, rfpath, bitmask);
 185
 186         spin_lock(&rtlpriv->locks.rf_lock);
 187
 188         original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
 189
 190         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 191         readback_value = (original_value & bitmask) >> bitshift;
 192
 193         spin_unlock(&rtlpriv->locks.rf_lock);
 194
 195         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 196                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 197                  regaddr, rfpath, bitmask, original_value);
 198
 199         return readback_value;
 200 }
 201
 202 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 203                            u32 regaddr, u32 bitmask, u32 data)
 204 {
 205         struct rtl_priv *rtlpriv = rtl_priv(hw);
 206         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 207         u32 original_value, bitshift;
 208
 209         if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
 210                 return;
 211
 212         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 213                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 214                  regaddr, bitmask, data, rfpath);
 215
 216         spin_lock(&rtlpriv->locks.rf_lock);
 217
 218         if (bitmask != RFREG_OFFSET_MASK) {
 219                 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
 220                                                             regaddr);
 221                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 222                 data = ((original_value & (~bitmask)) | (data << bitshift));
 223         }
 224
 225         _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
 226
 227         spin_unlock(&rtlpriv->locks.rf_lock);
 228
 229         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 230                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 231                  regaddr, bitmask, data, rfpath);
 232
 233 }
 234
 235 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
 236                                       u8 operation)
 237 {
 238         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 239
 240         if (!is_hal_stop(rtlhal)) {
 241                 switch (operation) {
 242                 case SCAN_OPT_BACKUP:
 243                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
 244                         break;
 245                 case SCAN_OPT_RESTORE:
 246                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
 247                         break;
 248                 default:
 249                         pr_err("Unknown operation\n");
 250                         break;
 251                 }
 252         }
 253 }
 254
 255 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
 256                             enum nl80211_channel_type ch_type)
 257 {
 258         struct rtl_priv *rtlpriv = rtl_priv(hw);
 259         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 260         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 261         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 262         u8 reg_bw_opmode;
 263
 264         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 265                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 266                  "20MHz" : "40MHz");
 267
 268         if (rtlphy->set_bwmode_inprogress)
 269                 return;
 270         if (is_hal_stop(rtlhal))
 271                 return;
 272
 273         rtlphy->set_bwmode_inprogress = true;
 274
 275         reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
 276         /* dummy read */
 277         rtl_read_byte(rtlpriv, RRSR + 2);
 278
 279         switch (rtlphy->current_chan_bw) {
 280         case HT_CHANNEL_WIDTH_20:
 281                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 282                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 283                 break;
 284         case HT_CHANNEL_WIDTH_20_40:
 285                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 286                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 287                 break;
 288         default:
 289                 pr_err("unknown bandwidth: %#X\n",
 290                        rtlphy->current_chan_bw);
 291                 break;
 292         }
 293
 294         switch (rtlphy->current_chan_bw) {
 295         case HT_CHANNEL_WIDTH_20:
 296                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 297                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 298
 299                 if (rtlhal->version >= VERSION_8192S_BCUT)
 300                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
 301                 break;
 302         case HT_CHANNEL_WIDTH_20_40:
 303                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 304                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 305
 306                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 307                                 (mac->cur_40_prime_sc >> 1));
 308                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 309
 310                 if (rtlhal->version >= VERSION_8192S_BCUT)
 311                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
 312                 break;
 313         default:
 314                 pr_err("unknown bandwidth: %#X\n",
 315                        rtlphy->current_chan_bw);
 316                 break;
 317         }
 318
 319         rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 320         rtlphy->set_bwmode_inprogress = false;
 321         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 322 }
 323
 324 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 325                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
 326                 u32 para1, u32 para2, u32 msdelay)
 327 {
 328         struct swchnlcmd *pcmd;
 329
 330         if (cmdtable == NULL) {
 331                 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n");
 332                 return false;
 333         }
 334
 335         if (cmdtableidx >= cmdtablesz)
 336                 return false;
 337
 338         pcmd = cmdtable + cmdtableidx;
 339         pcmd->cmdid = cmdid;
 340         pcmd->para1 = para1;
 341         pcmd->para2 = para2;
 342         pcmd->msdelay = msdelay;
 343
 344         return true;
 345 }
 346
 347 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 348              u8 channel, u8 *stage, u8 *step, u32 *delay)
 349 {
 350         struct rtl_priv *rtlpriv = rtl_priv(hw);
 351         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 352         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 353         u32 precommoncmdcnt;
 354         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 355         u32 postcommoncmdcnt;
 356         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 357         u32 rfdependcmdcnt;
 358         struct swchnlcmd *currentcmd = NULL;
 359         u8 rfpath;
 360         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 361
 362         precommoncmdcnt = 0;
 363         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 364                         MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 365         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 366                         MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 367
 368         postcommoncmdcnt = 0;
 369
 370         _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 371                         MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 372
 373         rfdependcmdcnt = 0;
 374
 375         WARN_ONCE((channel < 1 || channel > 14),
 376                   "rtl8192se: invalid channel for Zebra: %d\n", channel);
 377
 378         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 379                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 380                                          RF_CHNLBW, channel, 10);
 381
 382         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 383                         MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
 384
 385         do {
 386                 switch (*stage) {
 387                 case 0:
 388                         currentcmd = &precommoncmd[*step];
 389                         break;
 390                 case 1:
 391                         currentcmd = &rfdependcmd[*step];
 392                         break;
 393                 case 2:
 394                         currentcmd = &postcommoncmd[*step];
 395                         break;
 396                 default:
 397                         return true;
 398                 }
 399
 400                 if (currentcmd->cmdid == CMDID_END) {
 401                         if ((*stage) == 2) {
 402                                 return true;
 403                         } else {
 404                                 (*stage)++;
 405                                 (*step) = 0;
 406                                 continue;
 407                         }
 408                 }
 409
 410                 switch (currentcmd->cmdid) {
 411                 case CMDID_SET_TXPOWEROWER_LEVEL:
 412                         rtl92s_phy_set_txpower(hw, channel);
 413                         break;
 414                 case CMDID_WRITEPORT_ULONG:
 415                         rtl_write_dword(rtlpriv, currentcmd->para1,
 416                                         currentcmd->para2);
 417                         break;
 418                 case CMDID_WRITEPORT_USHORT:
 419                         rtl_write_word(rtlpriv, currentcmd->para1,
 420                                        (u16)currentcmd->para2);
 421                         break;
 422                 case CMDID_WRITEPORT_UCHAR:
 423                         rtl_write_byte(rtlpriv, currentcmd->para1,
 424                                        (u8)currentcmd->para2);
 425                         break;
 426                 case CMDID_RF_WRITEREG:
 427                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 428                                 rtlphy->rfreg_chnlval[rfpath] =
 429                                          ((rtlphy->rfreg_chnlval[rfpath] &
 430                                          0xfffffc00) | currentcmd->para2);
 431                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 432                                               currentcmd->para1,
 433                                               RFREG_OFFSET_MASK,
 434                                               rtlphy->rfreg_chnlval[rfpath]);
 435                         }
 436                         break;
 437                 default:
 438                         pr_err("switch case %#x not processed\n",
 439                                currentcmd->cmdid);
 440                         break;
 441                 }
 442
 443                 break;
 444         } while (true);
 445
 446         (*delay) = currentcmd->msdelay;
 447         (*step)++;
 448         return false;
 449 }
 450
 451 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
 452 {
 453         struct rtl_priv *rtlpriv = rtl_priv(hw);
 454         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 455         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 456         u32 delay;
 457         bool ret;
 458
 459         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
 460                  rtlphy->current_channel);
 461
 462         if (rtlphy->sw_chnl_inprogress)
 463                 return 0;
 464
 465         if (rtlphy->set_bwmode_inprogress)
 466                 return 0;
 467
 468         if (is_hal_stop(rtlhal))
 469                 return 0;
 470
 471         rtlphy->sw_chnl_inprogress = true;
 472         rtlphy->sw_chnl_stage = 0;
 473         rtlphy->sw_chnl_step = 0;
 474
 475         do {
 476                 if (!rtlphy->sw_chnl_inprogress)
 477                         break;
 478
 479                 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
 480                                  rtlphy->current_channel,
 481                                  &rtlphy->sw_chnl_stage,
 482                                  &rtlphy->sw_chnl_step, &delay);
 483                 if (!ret) {
 484                         if (delay > 0)
 485                                 mdelay(delay);
 486                         else
 487                                 continue;
 488                 } else {
 489                         rtlphy->sw_chnl_inprogress = false;
 490                 }
 491                 break;
 492         } while (true);
 493
 494         rtlphy->sw_chnl_inprogress = false;
 495
 496         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 497
 498         return 1;
 499 }
 500
 501 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
 502 {
 503         struct rtl_priv *rtlpriv = rtl_priv(hw);
 504         u8 u1btmp;
 505
 506         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
 507         u1btmp |= BIT(0);
 508
 509         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
 510         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
 511         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
 512         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 513         udelay(100);
 514
 515         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 516         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
 517         udelay(10);
 518
 519         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 520         udelay(10);
 521
 522         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 523         udelay(10);
 524
 525         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 526
 527         /* we should chnge GPIO to input mode
 528          * this will drop away current about 25mA*/
 529         rtl8192se_gpiobit3_cfg_inputmode(hw);
 530 }
 531
 532 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
 533                                    enum rf_pwrstate rfpwr_state)
 534 {
 535         struct rtl_priv *rtlpriv = rtl_priv(hw);
 536         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 537         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 538         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 539         bool bresult = true;
 540         u8 i, queue_id;
 541         struct rtl8192_tx_ring *ring = NULL;
 542
 543         if (rfpwr_state == ppsc->rfpwr_state)
 544                 return false;
 545
 546         switch (rfpwr_state) {
 547         case ERFON:{
 548                         if ((ppsc->rfpwr_state == ERFOFF) &&
 549                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 550
 551                                 bool rtstatus;
 552                                 u32 InitializeCount = 0;
 553                                 do {
 554                                         InitializeCount++;
 555                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 556                                                  "IPS Set eRf nic enable\n");
 557                                         rtstatus = rtl_ps_enable_nic(hw);
 558                                 } while (!rtstatus && (InitializeCount < 10));
 559
 560                                 RT_CLEAR_PS_LEVEL(ppsc,
 561                                                   RT_RF_OFF_LEVL_HALT_NIC);
 562                         } else {
 563                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 564                                          "awake, sleeped:%d ms state_inap:%x\n",
 565                                          jiffies_to_msecs(jiffies -
 566                                                           ppsc->
 567                                                           last_sleep_jiffies),
 568                                          rtlpriv->psc.state_inap);
 569                                 ppsc->last_awake_jiffies = jiffies;
 570                                 rtl_write_word(rtlpriv, CMDR, 0x37FC);
 571                                 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
 572                                 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
 573                         }
 574
 575                         if (mac->link_state == MAC80211_LINKED)
 576                                 rtlpriv->cfg->ops->led_control(hw,
 577                                                          LED_CTL_LINK);
 578                         else
 579                                 rtlpriv->cfg->ops->led_control(hw,
 580                                                          LED_CTL_NO_LINK);
 581                         break;
 582                 }
 583         case ERFOFF:{
 584                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 585                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 586                                          "IPS Set eRf nic disable\n");
 587                                 rtl_ps_disable_nic(hw);
 588                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 589                         } else {
 590                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 591                                         rtlpriv->cfg->ops->led_control(hw,
 592                                                          LED_CTL_NO_LINK);
 593                                 else
 594                                         rtlpriv->cfg->ops->led_control(hw,
 595                                                          LED_CTL_POWER_OFF);
 596                         }
 597                         break;
 598                 }
 599         case ERFSLEEP:
 600                         if (ppsc->rfpwr_state == ERFOFF)
 601                                 return false;
 602
 603                         for (queue_id = 0, i = 0;
 604                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 605                                 ring = &pcipriv->dev.tx_ring[queue_id];
 606                                 if (skb_queue_len(&ring->queue) == 0 ||
 607                                         queue_id == BEACON_QUEUE) {
 608                                         queue_id++;
 609                                         continue;
 610                                 } else {
 611                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 612                                                  "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
 613                                                  i + 1, queue_id,
 614                                                  skb_queue_len(&ring->queue));
 615
 616                                         udelay(10);
 617                                         i++;
 618                                 }
 619
 620                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 621                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 622                                                  "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 623                                                  MAX_DOZE_WAITING_TIMES_9x,
 624                                                  queue_id,
 625                                                  skb_queue_len(&ring->queue));
 626                                         break;
 627                                 }
 628                         }
 629
 630                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 631                                  "Set ERFSLEEP awaked:%d ms\n",
 632                                  jiffies_to_msecs(jiffies -
 633                                                   ppsc->last_awake_jiffies));
 634
 635                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 636                                  "sleep awaked:%d ms state_inap:%x\n",
 637                                  jiffies_to_msecs(jiffies -
 638                                                   ppsc->last_awake_jiffies),
 639                                  rtlpriv->psc.state_inap);
 640                         ppsc->last_sleep_jiffies = jiffies;
 641                         _rtl92se_phy_set_rf_sleep(hw);
 642                         break;
 643         default:
 644                 pr_err("switch case %#x not processed\n",
 645                        rfpwr_state);
 646                 bresult = false;
 647                 break;
 648         }
 649
 650         if (bresult)
 651                 ppsc->rfpwr_state = rfpwr_state;
 652
 653         return bresult;
 654 }
 655
 656 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
 657                                                  enum radio_path rfpath)
 658 {
 659         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 660         bool rtstatus = true;
 661         u32 tmpval = 0;
 662
 663         /* If inferiority IC, we have to increase the PA bias current */
 664         if (rtlhal->ic_class != IC_INFERIORITY_A) {
 665                 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
 666                 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
 667         }
 668
 669         return rtstatus;
 670 }
 671
 672 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 673                 u32 reg_addr, u32 bitmask, u32 data)
 674 {
 675         struct rtl_priv *rtlpriv = rtl_priv(hw);
 676         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 677         int index;
 678
 679         if (reg_addr == RTXAGC_RATE18_06)
 680                 index = 0;
 681         else if (reg_addr == RTXAGC_RATE54_24)
 682                 index = 1;
 683         else if (reg_addr == RTXAGC_CCK_MCS32)
 684                 index = 6;
 685         else if (reg_addr == RTXAGC_MCS03_MCS00)
 686                 index = 2;
 687         else if (reg_addr == RTXAGC_MCS07_MCS04)
 688                 index = 3;
 689         else if (reg_addr == RTXAGC_MCS11_MCS08)
 690                 index = 4;
 691         else if (reg_addr == RTXAGC_MCS15_MCS12)
 692                 index = 5;
 693         else
 694                 return;
 695
 696         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 697         if (index == 5)
 698                 rtlphy->pwrgroup_cnt++;
 699 }
 700
 701 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
 702 {
 703         struct rtl_priv *rtlpriv = rtl_priv(hw);
 704         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 705
 706         /*RF Interface Sowrtware Control */
 707         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 708         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 709         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 710         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 711
 712         /* RF Interface Readback Value */
 713         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 714         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 715         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 716         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 717
 718         /* RF Interface Output (and Enable) */
 719         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 720         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 721         rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
 722         rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
 723
 724         /* RF Interface (Output and)  Enable */
 725         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 726         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 727         rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
 728         rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
 729
 730         /* Addr of LSSI. Wirte RF register by driver */
 731         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 732                                                  RFPGA0_XA_LSSIPARAMETER;
 733         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 734                                                  RFPGA0_XB_LSSIPARAMETER;
 735         rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
 736                                                  RFPGA0_XC_LSSIPARAMETER;
 737         rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
 738                                                  RFPGA0_XD_LSSIPARAMETER;
 739
 740         /* RF parameter */
 741         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 742         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 743         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 744         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 745
 746         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 747         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 748         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 749         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 750         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 751
 752         /* Tranceiver A~D HSSI Parameter-1 */
 753         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 754         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 755         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
 756         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
 757
 758         /* Tranceiver A~D HSSI Parameter-2 */
 759         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 760         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 761         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
 762         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
 763
 764         /* RF switch Control */
 765         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 766         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 767         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 768         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 769
 770         /* AGC control 1  */
 771         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 772         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 773         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 774         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 775
 776         /* AGC control 2  */
 777         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 778         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 779         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 780         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 781
 782         /* RX AFE control 1  */
 783         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 784         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 785         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 786         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 787
 788         /* RX AFE control 1   */
 789         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 790         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 791         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 792         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 793
 794         /* Tx AFE control 1  */
 795         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 796         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 797         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 798         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 799
 800         /* Tx AFE control 2  */
 801         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 802         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 803         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 804         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 805
 806         /* Tranceiver LSSI Readback */
 807         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 808         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 809         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 810         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 811
 812         /* Tranceiver LSSI Readback PI mode  */
 813         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 814         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 815 }
 816
 817
 818 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
 819 {
 820         int i;
 821         u32 *phy_reg_table;
 822         u32 *agc_table;
 823         u16 phy_reg_len, agc_len;
 824
 825         agc_len = AGCTAB_ARRAYLENGTH;
 826         agc_table = rtl8192seagctab_array;
 827         /* Default RF_type: 2T2R */
 828         phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
 829         phy_reg_table = rtl8192sephy_reg_2t2rarray;
 830
 831         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 832                 for (i = 0; i < phy_reg_len; i = i + 2) {
 833                         rtl_addr_delay(phy_reg_table[i]);
 834
 835                         /* Add delay for ECS T20 & LG malow platform, */
 836                         udelay(1);
 837
 838                         rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
 839                                         phy_reg_table[i + 1]);
 840                 }
 841         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 842                 for (i = 0; i < agc_len; i = i + 2) {
 843                         rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
 844                                         agc_table[i + 1]);
 845
 846                         /* Add delay for ECS T20 & LG malow platform */
 847                         udelay(1);
 848                 }
 849         }
 850
 851         return true;
 852 }
 853
 854 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
 855                                           u8 configtype)
 856 {
 857         struct rtl_priv *rtlpriv = rtl_priv(hw);
 858         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 859         u32 *phy_regarray2xtxr_table;
 860         u16 phy_regarray2xtxr_len;
 861         int i;
 862
 863         if (rtlphy->rf_type == RF_1T1R) {
 864                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
 865                 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
 866         } else if (rtlphy->rf_type == RF_1T2R) {
 867                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
 868                 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
 869         } else {
 870                 return false;
 871         }
 872
 873         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 874                 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
 875                         rtl_addr_delay(phy_regarray2xtxr_table[i]);
 876
 877                         rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
 878                                 phy_regarray2xtxr_table[i + 1],
 879                                 phy_regarray2xtxr_table[i + 2]);
 880                 }
 881         }
 882
 883         return true;
 884 }
 885
 886 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
 887                                           u8 configtype)
 888 {
 889         int i;
 890         u32 *phy_table_pg;
 891         u16 phy_pg_len;
 892
 893         phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
 894         phy_table_pg = rtl8192sephy_reg_array_pg;
 895
 896         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 897                 for (i = 0; i < phy_pg_len; i = i + 3) {
 898                         rtl_addr_delay(phy_table_pg[i]);
 899
 900                         _rtl92s_store_pwrindex_diffrate_offset(hw,
 901                                         phy_table_pg[i],
 902                                         phy_table_pg[i + 1],
 903                                         phy_table_pg[i + 2]);
 904                         rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
 905                                         phy_table_pg[i + 1],
 906                                         phy_table_pg[i + 2]);
 907                 }
 908         }
 909
 910         return true;
 911 }
 912
 913 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
 914 {
 915         struct rtl_priv *rtlpriv = rtl_priv(hw);
 916         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 917         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 918         bool rtstatus = true;
 919
 920         /* 1. Read PHY_REG.TXT BB INIT!! */
 921         /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
 922         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
 923             rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
 924                 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
 925
 926                 if (rtlphy->rf_type != RF_2T2R &&
 927                     rtlphy->rf_type != RF_2T2R_GREEN)
 928                         /* so we should reconfig BB reg with the right
 929                          * PHY parameters. */
 930                         rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
 931                                                 BASEBAND_CONFIG_PHY_REG);
 932         } else {
 933                 rtstatus = false;
 934         }
 935
 936         if (!rtstatus) {
 937                 pr_err("Write BB Reg Fail!!\n");
 938                 goto phy_BB8190_Config_ParaFile_Fail;
 939         }
 940
 941         /* 2. If EEPROM or EFUSE autoload OK, We must config by
 942          *    PHY_REG_PG.txt */
 943         if (rtlefuse->autoload_failflag == false) {
 944                 rtlphy->pwrgroup_cnt = 0;
 945
 946                 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
 947                                                  BASEBAND_CONFIG_PHY_REG);
 948         }
 949         if (!rtstatus) {
 950                 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
 951                 goto phy_BB8190_Config_ParaFile_Fail;
 952         }
 953
 954         /* 3. BB AGC table Initialization */
 955         rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
 956
 957         if (!rtstatus) {
 958                 pr_err("%s(): AGC Table Fail\n", __func__);
 959                 goto phy_BB8190_Config_ParaFile_Fail;
 960         }
 961
 962         /* Check if the CCK HighPower is turned ON. */
 963         /* This is used to calculate PWDB. */
 964         rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
 965                         RFPGA0_XA_HSSIPARAMETER2, 0x200));
 966
 967 phy_BB8190_Config_ParaFile_Fail:
 968         return rtstatus;
 969 }
 970
 971 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
 972 {
 973         struct rtl_priv *rtlpriv = rtl_priv(hw);
 974         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 975         int i;
 976         bool rtstatus = true;
 977         u32 *radio_a_table;
 978         u32 *radio_b_table;
 979         u16 radio_a_tblen, radio_b_tblen;
 980
 981         radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
 982         radio_a_table = rtl8192seradioa_1t_array;
 983
 984         /* Using Green mode array table for RF_2T2R_GREEN */
 985         if (rtlphy->rf_type == RF_2T2R_GREEN) {
 986                 radio_b_table = rtl8192seradiob_gm_array;
 987                 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
 988         } else {
 989                 radio_b_table = rtl8192seradiob_array;
 990                 radio_b_tblen = RADIOB_ARRAYLENGTH;
 991         }
 992
 993         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
 994         rtstatus = true;
 995
 996         switch (rfpath) {
 997         case RF90_PATH_A:
 998                 for (i = 0; i < radio_a_tblen; i = i + 2) {
 999                         rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
1000                                         MASK20BITS, radio_a_table[i + 1]);
1001
1002                 }
1003
1004                 /* PA Bias current for inferiority IC */
1005                 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1006                 break;
1007         case RF90_PATH_B:
1008                 for (i = 0; i < radio_b_tblen; i = i + 2) {
1009                         rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
1010                                         MASK20BITS, radio_b_table[i + 1]);
1011                 }
1012                 break;
1013         case RF90_PATH_C:
1014                 ;
1015                 break;
1016         case RF90_PATH_D:
1017                 ;
1018                 break;
1019         default:
1020                 break;
1021         }
1022
1023         return rtstatus;
1024 }
1025
1026
1027 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1028 {
1029         struct rtl_priv *rtlpriv = rtl_priv(hw);
1030         u32 i;
1031         u32 arraylength;
1032         u32 *ptraArray;
1033
1034         arraylength = MAC_2T_ARRAYLENGTH;
1035         ptraArray = rtl8192semac_2t_array;
1036
1037         for (i = 0; i < arraylength; i = i + 2)
1038                 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1039
1040         return true;
1041 }
1042
1043
1044 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1045 {
1046         struct rtl_priv *rtlpriv = rtl_priv(hw);
1047         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1048         bool rtstatus = true;
1049         u8 pathmap, index, rf_num = 0;
1050         u8 path1, path2;
1051
1052         _rtl92s_phy_init_register_definition(hw);
1053
1054         /* Config BB and AGC */
1055         rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1056
1057
1058         /* Check BB/RF confiuration setting. */
1059         /* We only need to configure RF which is turned on. */
1060         path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1061         mdelay(10);
1062         path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1063         pathmap = path1 | path2;
1064
1065         rtlphy->rf_pathmap = pathmap;
1066         for (index = 0; index < 4; index++) {
1067                 if ((pathmap >> index) & 0x1)
1068                         rf_num++;
1069         }
1070
1071         if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1072             (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1073             (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1074             (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1075                 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n",
1076                        rtlphy->rf_type, rf_num);
1077                 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1078                        path1, path2, pathmap);
1079         }
1080
1081         return rtstatus;
1082 }
1083
1084 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1085 {
1086         struct rtl_priv *rtlpriv = rtl_priv(hw);
1087         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1088
1089         /* Initialize general global value */
1090         if (rtlphy->rf_type == RF_1T1R)
1091                 rtlphy->num_total_rfpath = 1;
1092         else
1093                 rtlphy->num_total_rfpath = 2;
1094
1095         /* Config BB and RF */
1096         return rtl92s_phy_rf6052_config(hw);
1097 }
1098
1099 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1100 {
1101         struct rtl_priv *rtlpriv = rtl_priv(hw);
1102         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1103
1104         /* read rx initial gain */
1105         rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1106                         ROFDM0_XAAGCCORE1, MASKBYTE0);
1107         rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1108                         ROFDM0_XBAGCCORE1, MASKBYTE0);
1109         rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1110                         ROFDM0_XCAGCCORE1, MASKBYTE0);
1111         rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1112                         ROFDM0_XDAGCCORE1, MASKBYTE0);
1113         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1114                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1115                  rtlphy->default_initialgain[0],
1116                  rtlphy->default_initialgain[1],
1117                  rtlphy->default_initialgain[2],
1118                  rtlphy->default_initialgain[3]);
1119
1120         /* read framesync */
1121         rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1122         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1123                                               MASKDWORD);
1124         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1125                  "Default framesync (0x%x) = 0x%x\n",
1126                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
1127
1128 }
1129
1130 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1131                                           u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1132 {
1133         struct rtl_priv *rtlpriv = rtl_priv(hw);
1134         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1135         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1136         u8 index = (channel - 1);
1137
1138         /* 1. CCK */
1139         /* RF-A */
1140         cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1141         /* RF-B */
1142         cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1143
1144         /* 2. OFDM for 1T or 2T */
1145         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1146                 /* Read HT 40 OFDM TX power */
1147                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1148                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1149         } else if (rtlphy->rf_type == RF_2T2R) {
1150                 /* Read HT 40 OFDM TX power */
1151                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1152                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1153         } else {
1154                 ofdmpowerLevel[0] = 0;
1155                 ofdmpowerLevel[1] = 0;
1156         }
1157 }
1158
1159 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1160                 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1161 {
1162         struct rtl_priv *rtlpriv = rtl_priv(hw);
1163         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1164
1165         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1166         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1167 }
1168
1169 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1170 {
1171         struct rtl_priv *rtlpriv = rtl_priv(hw);
1172         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1173         /* [0]:RF-A, [1]:RF-B */
1174         u8 cckpowerlevel[2], ofdmpowerLevel[2];
1175
1176         if (!rtlefuse->txpwr_fromeprom)
1177                 return;
1178
1179         /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1180          * but the RF-B Tx Power must be calculated by the antenna diff.
1181          * So we have to rewrite Antenna gain offset register here.
1182          * Please refer to BB register 0x80c
1183          * 1. For CCK.
1184          * 2. For OFDM 1T or 2T */
1185         _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1186                         &ofdmpowerLevel[0]);
1187
1188         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1189                  "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1190                  channel, cckpowerlevel[0], cckpowerlevel[1],
1191                  ofdmpowerLevel[0], ofdmpowerLevel[1]);
1192
1193         _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1194                         &ofdmpowerLevel[0]);
1195
1196         rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1197         rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1198
1199 }
1200
1201 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1202 {
1203         struct rtl_priv *rtlpriv = rtl_priv(hw);
1204         u16 pollingcnt = 10000;
1205         u32 tmpvalue;
1206
1207         /* Make sure that CMD IO has be accepted by FW. */
1208         do {
1209                 udelay(10);
1210
1211                 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1212                 if (tmpvalue == 0)
1213                         break;
1214         } while (--pollingcnt);
1215
1216         if (pollingcnt == 0)
1217                 pr_err("Set FW Cmd fail!!\n");
1218 }
1219
1220
1221 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1222 {
1223         struct rtl_priv *rtlpriv = rtl_priv(hw);
1224         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1225         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1226         u32 input, current_aid = 0;
1227
1228         if (is_hal_stop(rtlhal))
1229                 return;
1230
1231         if (hal_get_firmwareversion(rtlpriv) < 0x34)
1232                 goto skip;
1233         /* We re-map RA related CMD IO to combinational ones */
1234         /* if FW version is v.52 or later. */
1235         switch (rtlhal->current_fwcmd_io) {
1236         case FW_CMD_RA_REFRESH_N:
1237                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1238                 break;
1239         case FW_CMD_RA_REFRESH_BG:
1240                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1241                 break;
1242         default:
1243                 break;
1244         }
1245
1246 skip:
1247         switch (rtlhal->current_fwcmd_io) {
1248         case FW_CMD_RA_RESET:
1249                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1250                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1251                 rtl92s_phy_chk_fwcmd_iodone(hw);
1252                 break;
1253         case FW_CMD_RA_ACTIVE:
1254                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1255                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1256                 rtl92s_phy_chk_fwcmd_iodone(hw);
1257                 break;
1258         case FW_CMD_RA_REFRESH_N:
1259                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1260                 input = FW_RA_REFRESH;
1261                 rtl_write_dword(rtlpriv, WFM5, input);
1262                 rtl92s_phy_chk_fwcmd_iodone(hw);
1263                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1264                 rtl92s_phy_chk_fwcmd_iodone(hw);
1265                 break;
1266         case FW_CMD_RA_REFRESH_BG:
1267                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1268                          "FW_CMD_RA_REFRESH_BG\n");
1269                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1270                 rtl92s_phy_chk_fwcmd_iodone(hw);
1271                 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1272                 rtl92s_phy_chk_fwcmd_iodone(hw);
1273                 break;
1274         case FW_CMD_RA_REFRESH_N_COMB:
1275                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1276                          "FW_CMD_RA_REFRESH_N_COMB\n");
1277                 input = FW_RA_IOT_N_COMB;
1278                 rtl_write_dword(rtlpriv, WFM5, input);
1279                 rtl92s_phy_chk_fwcmd_iodone(hw);
1280                 break;
1281         case FW_CMD_RA_REFRESH_BG_COMB:
1282                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1283                          "FW_CMD_RA_REFRESH_BG_COMB\n");
1284                 input = FW_RA_IOT_BG_COMB;
1285                 rtl_write_dword(rtlpriv, WFM5, input);
1286                 rtl92s_phy_chk_fwcmd_iodone(hw);
1287                 break;
1288         case FW_CMD_IQK_ENABLE:
1289                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1290                 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1291                 rtl92s_phy_chk_fwcmd_iodone(hw);
1292                 break;
1293         case FW_CMD_PAUSE_DM_BY_SCAN:
1294                 /* Lower initial gain */
1295                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1296                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1297                 /* CCA threshold */
1298                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1299                 break;
1300         case FW_CMD_RESUME_DM_BY_SCAN:
1301                 /* CCA threshold */
1302                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1303                 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1304                 break;
1305         case FW_CMD_HIGH_PWR_DISABLE:
1306                 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1307                         break;
1308
1309                 /* Lower initial gain */
1310                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1311                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1312                 /* CCA threshold */
1313                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1314                 break;
1315         case FW_CMD_HIGH_PWR_ENABLE:
1316                 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1317                         rtlpriv->dm.dynamic_txpower_enable)
1318                         break;
1319
1320                 /* CCA threshold */
1321                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1322                 break;
1323         case FW_CMD_LPS_ENTER:
1324                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1325                 current_aid = rtlpriv->mac80211.assoc_id;
1326                 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1327                                 ((current_aid | 0xc000) << 8)));
1328                 rtl92s_phy_chk_fwcmd_iodone(hw);
1329                 /* FW set TXOP disable here, so disable EDCA
1330                  * turbo mode until driver leave LPS */
1331                 break;
1332         case FW_CMD_LPS_LEAVE:
1333                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1334                 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1335                 rtl92s_phy_chk_fwcmd_iodone(hw);
1336                 break;
1337         case FW_CMD_ADD_A2_ENTRY:
1338                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1339                 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1340                 rtl92s_phy_chk_fwcmd_iodone(hw);
1341                 break;
1342         case FW_CMD_CTRL_DM_BY_DRIVER:
1343                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1344                          "FW_CMD_CTRL_DM_BY_DRIVER\n");
1345                 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1346                 rtl92s_phy_chk_fwcmd_iodone(hw);
1347                 break;
1348
1349         default:
1350                 break;
1351         }
1352
1353         rtl92s_phy_chk_fwcmd_iodone(hw);
1354
1355         /* Clear FW CMD operation flag. */
1356         rtlhal->set_fwcmd_inprogress = false;
1357 }
1358
1359 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1360 {
1361         struct rtl_priv *rtlpriv = rtl_priv(hw);
1362         struct dig_t *digtable = &rtlpriv->dm_digtable;
1363         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1364         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1365         u32     fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1366         u16     fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1367         bool postprocessing = false;
1368
1369         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1370                  "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1371                  fw_cmdio, rtlhal->set_fwcmd_inprogress);
1372
1373         do {
1374                 /* We re-map to combined FW CMD ones if firmware version */
1375                 /* is v.53 or later. */
1376                 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1377                         switch (fw_cmdio) {
1378                         case FW_CMD_RA_REFRESH_N:
1379                                 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1380                                 break;
1381                         case FW_CMD_RA_REFRESH_BG:
1382                                 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1383                                 break;
1384                         default:
1385                                 break;
1386                         }
1387                 } else {
1388                         if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1389                             (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1390                             (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1391                                 postprocessing = true;
1392                                 break;
1393                         }
1394                 }
1395
1396                 /* If firmware version is v.62 or later,
1397                  * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1398                 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1399                         if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1400                                 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1401                 }
1402
1403
1404                 /* We shall revise all FW Cmd IO into Reg0x364
1405                  * DM map table in the future. */
1406                 switch (fw_cmdio) {
1407                 case FW_CMD_RA_INIT:
1408                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1409                         fw_cmdmap |= FW_RA_INIT_CTL;
1410                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1411                         /* Clear control flag to sync with FW. */
1412                         FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1413                         break;
1414                 case FW_CMD_DIG_DISABLE:
1415                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1416                                  "Set DIG disable!!\n");
1417                         fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1418                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1419                         break;
1420                 case FW_CMD_DIG_ENABLE:
1421                 case FW_CMD_DIG_RESUME:
1422                         if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1423                                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1424                                          "Set DIG enable or resume!!\n");
1425                                 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1426                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1427                         }
1428                         break;
1429                 case FW_CMD_DIG_HALT:
1430                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1431                                  "Set DIG halt!!\n");
1432                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1433                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1434                         break;
1435                 case FW_CMD_TXPWR_TRACK_THERMAL: {
1436                         u8      thermalval = 0;
1437                         fw_cmdmap |= FW_PWR_TRK_CTL;
1438
1439                         /* Clear FW parameter in terms of thermal parts. */
1440                         fw_param &= FW_PWR_TRK_PARAM_CLR;
1441
1442                         thermalval = rtlpriv->dm.thermalvalue;
1443                         fw_param |= ((thermalval << 24) |
1444                                      (rtlefuse->thermalmeter[0] << 16));
1445
1446                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1447                                  "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1448                                  fw_cmdmap, fw_param);
1449
1450                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1451                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1452
1453                         /* Clear control flag to sync with FW. */
1454                         FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1455                         }
1456                         break;
1457                 /* The following FW CMDs are only compatible to
1458                  * v.53 or later. */
1459                 case FW_CMD_RA_REFRESH_N_COMB:
1460                         fw_cmdmap |= FW_RA_N_CTL;
1461
1462                         /* Clear RA BG mode control. */
1463                         fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1464
1465                         /* Clear FW parameter in terms of RA parts. */
1466                         fw_param &= FW_RA_PARAM_CLR;
1467
1468                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1469                                  "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1470                                  fw_cmdmap, fw_param);
1471
1472                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1473                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1474
1475                         /* Clear control flag to sync with FW. */
1476                         FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1477                         break;
1478                 case FW_CMD_RA_REFRESH_BG_COMB:
1479                         fw_cmdmap |= FW_RA_BG_CTL;
1480
1481                         /* Clear RA n-mode control. */
1482                         fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1483                         /* Clear FW parameter in terms of RA parts. */
1484                         fw_param &= FW_RA_PARAM_CLR;
1485
1486                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1487                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1488
1489                         /* Clear control flag to sync with FW. */
1490                         FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1491                         break;
1492                 case FW_CMD_IQK_ENABLE:
1493                         fw_cmdmap |= FW_IQK_CTL;
1494                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1495                         /* Clear control flag to sync with FW. */
1496                         FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1497                         break;
1498                 /* The following FW CMD is compatible to v.62 or later.  */
1499                 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1500                         fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1501                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1502                         break;
1503                 /*  The followed FW Cmds needs post-processing later. */
1504                 case FW_CMD_RESUME_DM_BY_SCAN:
1505                         fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1506                                       FW_HIGH_PWR_ENABLE_CTL |
1507                                       FW_SS_CTL);
1508
1509                         if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1510                                 !digtable->dig_enable_flag)
1511                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1512
1513                         if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1514                             rtlpriv->dm.dynamic_txpower_enable)
1515                                 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1516
1517                         if ((digtable->dig_ext_port_stage ==
1518                             DIG_EXT_PORT_STAGE_0) ||
1519                             (digtable->dig_ext_port_stage ==
1520                             DIG_EXT_PORT_STAGE_1))
1521                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1522
1523                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1524                         postprocessing = true;
1525                         break;
1526                 case FW_CMD_PAUSE_DM_BY_SCAN:
1527                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1528                                        FW_HIGH_PWR_ENABLE_CTL |
1529                                        FW_SS_CTL);
1530                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1531                         postprocessing = true;
1532                         break;
1533                 case FW_CMD_HIGH_PWR_DISABLE:
1534                         fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1535                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1536                         postprocessing = true;
1537                         break;
1538                 case FW_CMD_HIGH_PWR_ENABLE:
1539                         if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1540                             !rtlpriv->dm.dynamic_txpower_enable) {
1541                                 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1542                                               FW_SS_CTL);
1543                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1544                                 postprocessing = true;
1545                         }
1546                         break;
1547                 case FW_CMD_DIG_MODE_FA:
1548                         fw_cmdmap |= FW_FA_CTL;
1549                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1550                         break;
1551                 case FW_CMD_DIG_MODE_SS:
1552                         fw_cmdmap &= ~FW_FA_CTL;
1553                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1554                         break;
1555                 case FW_CMD_PAPE_CONTROL:
1556                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1557                                  "[FW CMD] Set PAPE Control\n");
1558                         fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1559
1560                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1561                         break;
1562                 default:
1563                         /* Pass to original FW CMD processing callback
1564                          * routine. */
1565                         postprocessing = true;
1566                         break;
1567                 }
1568         } while (false);
1569
1570         /* We shall post processing these FW CMD if
1571          * variable postprocessing is set.
1572          */
1573         if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1574                 rtlhal->set_fwcmd_inprogress = true;
1575                 /* Update current FW Cmd for callback use. */
1576                 rtlhal->current_fwcmd_io = fw_cmdio;
1577         } else {
1578                 return false;
1579         }
1580
1581         _rtl92s_phy_set_fwcmd_io(hw);
1582         return true;
1583 }
1584
1585 static  void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1586 {
1587         struct rtl_priv *rtlpriv = rtl_priv(hw);
1588         u32     delay = 100;
1589         u8      regu1;
1590
1591         regu1 = rtl_read_byte(rtlpriv, 0x554);
1592         while ((regu1 & BIT(5)) && (delay > 0)) {
1593                 regu1 = rtl_read_byte(rtlpriv, 0x554);
1594                 delay--;
1595                 /* We delay only 50us to prevent
1596                  * being scheduled out. */
1597                 udelay(50);
1598         }
1599 }
1600
1601 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1602 {
1603         struct rtl_priv *rtlpriv = rtl_priv(hw);
1604         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1605
1606         /* The way to be capable to switch clock request
1607          * when the PG setting does not support clock request.
1608          * This is the backdoor solution to switch clock
1609          * request before ASPM or D3. */
1610         rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1611         rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1612
1613         /* Switch EPHY parameter!!!! */
1614         rtl_write_word(rtlpriv, 0x550, 0x1000);
1615         rtl_write_byte(rtlpriv, 0x554, 0x20);
1616         _rtl92s_phy_check_ephy_switchready(hw);
1617
1618         rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1619         rtl_write_byte(rtlpriv, 0x554, 0x3e);
1620         _rtl92s_phy_check_ephy_switchready(hw);
1621
1622         rtl_write_word(rtlpriv, 0x550, 0xff80);
1623         rtl_write_byte(rtlpriv, 0x554, 0x39);
1624         _rtl92s_phy_check_ephy_switchready(hw);
1625
1626         /* Delay L1 enter time */
1627         if (ppsc->support_aspm && !ppsc->support_backdoor)
1628                 rtl_write_byte(rtlpriv, 0x560, 0x40);
1629         else
1630                 rtl_write_byte(rtlpriv, 0x560, 0x00);
1631
1632 }
1633
1634 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1635 {
1636         struct rtl_priv *rtlpriv = rtl_priv(hw);
1637         u32 new_bcn_num = 0;
1638
1639         if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1640                 /* Fw v.51 and later. */
1641                 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1642                                 (beaconinterval << 8));
1643         } else {
1644                 new_bcn_num = beaconinterval * 32 - 64;
1645                 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1646                 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1647         }
1648 }