drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "../rtl8723com/phy_common.h"
  37 #include "dm.h"
  38 #include "../rtl8723com/dm_common.h"
  39 #include "fw.h"
  40 #include "../rtl8723com/fw_common.h"
  41 #include "led.h"
  42 #include "hw.h"
  43 #include "../pwrseqcmd.h"
  44 #include "pwrseq.h"
  45 #include "../btcoexist/rtl_btc.h"
  46
  47 #define LLT_CONFIG      5
  48
  49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  54         unsigned long flags;
  55
  56         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  57         while (skb_queue_len(&ring->queue)) {
  58                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  59                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  60
  61                 pci_unmap_single(rtlpci->pdev,
  62                                  rtlpriv->cfg->ops->get_desc(
  63                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  64                                  skb->len, PCI_DMA_TODEVICE);
  65                 kfree_skb(skb);
  66                 ring->idx = (ring->idx + 1) % ring->entries;
  67         }
  68         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  69 }
  70
  71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  72                                         u8 set_bits, u8 clear_bits)
  73 {
  74         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76
  77         rtlpci->reg_bcn_ctrl_val |= set_bits;
  78         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  79
  80         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  81 }
  82
  83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u8 tmp1byte;
  87
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  89         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  91         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  92         tmp1byte &= ~(BIT(0));
  93         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  94 }
  95
  96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
  97 {
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         u8 tmp1byte;
 100
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 102         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 104         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 105         tmp1byte |= BIT(1);
 106         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 107 }
 108
 109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
 112 }
 113
 114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
 115 {
 116         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
 117 }
 118
 119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
 120                                        bool b_need_turn_off_ckk)
 121 {
 122         struct rtl_priv *rtlpriv = rtl_priv(hw);
 123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 124         bool b_support_remote_wake_up;
 125         u32 count = 0, isr_regaddr, content;
 126         bool b_schedule_timer = b_need_turn_off_ckk;
 127         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 128                                       (u8 *)(&b_support_remote_wake_up));
 129
 130         if (!rtlhal->fw_ready)
 131                 return;
 132         if (!rtlpriv->psc.fw_current_inpsmode)
 133                 return;
 134
 135         while (1) {
 136                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 137                 if (rtlhal->fw_clk_change_in_progress) {
 138                         while (rtlhal->fw_clk_change_in_progress) {
 139                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 140                                 count++;
 141                                 udelay(100);
 142                                 if (count > 1000)
 143                                         return;
 144                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         }
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                 } else {
 148                         rtlhal->fw_clk_change_in_progress = false;
 149                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 150                         break;
 151                 }
 152         }
 153
 154         if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
 155                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 156                                               (u8 *)(&rpwm_val));
 157                 if (FW_PS_IS_ACK(rpwm_val)) {
 158                         isr_regaddr = REG_HISR;
 159                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         while (!(content & IMR_CPWM) && (count < 500)) {
 161                                 udelay(50);
 162                                 count++;
 163                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 164                         }
 165
 166                         if (content & IMR_CPWM) {
 167                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 168                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
 169                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 170                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 171                                          rtlhal->fw_ps_state);
 172                         }
 173                 }
 174
 175                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 rtlhal->fw_clk_change_in_progress = false;
 177                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 178                 if (b_schedule_timer)
 179                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 180                                   jiffies + MSECS(10));
 181         } else  {
 182                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 183                 rtlhal->fw_clk_change_in_progress = false;
 184                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 185         }
 186 }
 187
 188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 189 {
 190         struct rtl_priv *rtlpriv = rtl_priv(hw);
 191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 192         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 193         struct rtl8192_tx_ring *ring;
 194         enum rf_pwrstate rtstate;
 195         bool b_schedule_timer = false;
 196         u8 queue;
 197
 198         if (!rtlhal->fw_ready)
 199                 return;
 200         if (!rtlpriv->psc.fw_current_inpsmode)
 201                 return;
 202         if (!rtlhal->allow_sw_to_change_hwclc)
 203                 return;
 204         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 205         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 206                 return;
 207
 208         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 209                 ring = &rtlpci->tx_ring[queue];
 210                 if (skb_queue_len(&ring->queue)) {
 211                         b_schedule_timer = true;
 212                         break;
 213                 }
 214         }
 215
 216         if (b_schedule_timer) {
 217                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 218                           jiffies + MSECS(10));
 219                 return;
 220         }
 221
 222         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240
 241 }
 242
 243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 244 {
 245         u8 rpwm_val = 0;
 246         rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
 247         _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
 260                 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                               (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                               (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON;  /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                               (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                               (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                               (u8 *)(&fw_current_inps));
 274         }
 275
 276 }
 277
 278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
 279 {
 280         struct rtl_priv *rtlpriv = rtl_priv(hw);
 281         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 282         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 283         bool fw_current_inps = true;
 284         u8 rpwm_val;
 285
 286         if (ppsc->low_power_enable) {
 287                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 288                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 289                                               (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 291                                               (u8 *)(&ppsc->fwctrl_psmode));
 292                 rtlhal->allow_sw_to_change_hwclc = true;
 293                 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
 294         } else {
 295                 rpwm_val = FW_PS_STATE_RF_OFF;  /* RF off */
 296                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 297                                               (u8 *)(&fw_current_inps));
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 299                                               (u8 *)(&ppsc->fwctrl_psmode));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 301                                               (u8 *)(&rpwm_val));
 302         }
 303
 304 }
 305
 306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 307 {
 308         struct rtl_priv *rtlpriv = rtl_priv(hw);
 309         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 310         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 311
 312         switch (variable) {
 313         case HW_VAR_RCR:
 314                 *((u32 *)(val)) = rtlpci->receive_config;
 315                 break;
 316         case HW_VAR_RF_STATE:
 317                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 318                 break;
 319         case HW_VAR_FWLPS_RF_ON:{
 320                 enum rf_pwrstate rfState;
 321                 u32 val_rcr;
 322
 323                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 324                                               (u8 *)(&rfState));
 325                 if (rfState == ERFOFF) {
 326                         *((bool *)(val)) = true;
 327                 } else {
 328                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 329                         val_rcr &= 0x00070000;
 330                         if (val_rcr)
 331                                 *((bool *)(val)) = false;
 332                         else
 333                                 *((bool *)(val)) = true;
 334                 }
 335                 }
 336                 break;
 337         case HW_VAR_FW_PSMODE_STATUS:
 338                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 339                 break;
 340         case HW_VAR_CORRECT_TSF:{
 341                 u64 tsf;
 342                 u32 *ptsf_low = (u32 *)&tsf;
 343                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 344
 345                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 346                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 347
 348                 *((u64 *)(val)) = tsf;
 349                 }
 350                 break;
 351         case HAL_DEF_WOWLAN:
 352                 break;
 353         default:
 354                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 355                          "switch case %#x not processed\n", variable);
 356                 break;
 357         }
 358 }
 359
 360 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
 361 {
 362         struct rtl_priv *rtlpriv = rtl_priv(hw);
 363         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 364         u8 count = 0, dlbcn_count = 0;
 365         bool b_recover = false;
 366
 367         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 368         rtl_write_byte(rtlpriv, REG_CR + 1,
 369                        (tmp_regcr | BIT(0)));
 370
 371         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 372         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
 373
 374         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 375         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 376         if (tmp_reg422 & BIT(6))
 377                 b_recover = true;
 378
 379         do {
 380                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 381                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 382                                (bcnvalid_reg | BIT(0)));
 383                 _rtl8723be_return_beacon_queue_skb(hw);
 384
 385                 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
 386                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 387                 count = 0;
 388                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 389                         count++;
 390                         udelay(10);
 391                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 392                                                      REG_TDECTRL + 2);
 393                 }
 394                 dlbcn_count++;
 395         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 396
 397         if (bcnvalid_reg & BIT(0))
 398                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 399
 400         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 401         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
 402
 403         if (b_recover)
 404                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 405
 406         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 407         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 408 }
 409
 410 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 411 {
 412         struct rtl_priv *rtlpriv = rtl_priv(hw);
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 416         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 417         u8 idx;
 418
 419         switch (variable) {
 420         case HW_VAR_ETHER_ADDR:
 421                 for (idx = 0; idx < ETH_ALEN; idx++)
 422                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 423                 break;
 424         case HW_VAR_BASIC_RATE:{
 425                 u16 b_rate_cfg = ((u16 *)val)[0];
 426                 u8 rate_index = 0;
 427                 b_rate_cfg = b_rate_cfg & 0x15f;
 428                 b_rate_cfg |= 0x01;
 429                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 430                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 431                 while (b_rate_cfg > 0x1) {
 432                         b_rate_cfg = (b_rate_cfg >> 1);
 433                         rate_index++;
 434                 }
 435                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 436                 }
 437                 break;
 438         case HW_VAR_BSSID:
 439                 for (idx = 0; idx < ETH_ALEN; idx++)
 440                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 441
 442                 break;
 443         case HW_VAR_SIFS:
 444                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 445                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 446
 447                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 448                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 449
 450                 if (!mac->ht_enable)
 451                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 452                 else
 453                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 454                                        *((u16 *)val));
 455                 break;
 456         case HW_VAR_SLOT_TIME:{
 457                 u8 e_aci;
 458
 459                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 460                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 461
 462                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 463
 464                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 465                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 466                                                       (u8 *)(&e_aci));
 467                 }
 468                 }
 469                 break;
 470         case HW_VAR_ACK_PREAMBLE:{
 471                 u8 reg_tmp;
 472                 u8 short_preamble = (bool)(*(u8 *)val);
 473                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
 474                 if (short_preamble) {
 475                         reg_tmp |= 0x02;
 476                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 477                 } else {
 478                         reg_tmp &= 0xFD;
 479                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 480                 }
 481                 }
 482                 break;
 483         case HW_VAR_WPA_CONFIG:
 484                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 485                 break;
 486         case HW_VAR_AMPDU_MIN_SPACE:{
 487                 u8 min_spacing_to_set;
 488                 u8 sec_min_space;
 489
 490                 min_spacing_to_set = *((u8 *)val);
 491                 if (min_spacing_to_set <= 7) {
 492                         sec_min_space = 0;
 493
 494                         if (min_spacing_to_set < sec_min_space)
 495                                 min_spacing_to_set = sec_min_space;
 496
 497                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 498                                               min_spacing_to_set);
 499
 500                         *val = min_spacing_to_set;
 501
 502                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 503                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 504                                   mac->min_space_cfg);
 505
 506                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 507                                        mac->min_space_cfg);
 508                 }
 509                 }
 510                 break;
 511         case HW_VAR_SHORTGI_DENSITY:{
 512                 u8 density_to_set;
 513
 514                 density_to_set = *((u8 *)val);
 515                 mac->min_space_cfg |= (density_to_set << 3);
 516
 517                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 518                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 519                           mac->min_space_cfg);
 520
 521                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 522                                mac->min_space_cfg);
 523                 }
 524                 break;
 525         case HW_VAR_AMPDU_FACTOR:{
 526                 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 527                 u8 factor_toset;
 528                 u8 *p_regtoset = NULL;
 529                 u8 index = 0;
 530
 531                 p_regtoset = regtoset_normal;
 532
 533                 factor_toset = *((u8 *)val);
 534                 if (factor_toset <= 3) {
 535                         factor_toset = (1 << (factor_toset + 2));
 536                         if (factor_toset > 0xf)
 537                                 factor_toset = 0xf;
 538
 539                         for (index = 0; index < 4; index++) {
 540                                 if ((p_regtoset[index] & 0xf0) >
 541                                     (factor_toset << 4))
 542                                         p_regtoset[index] =
 543                                                 (p_regtoset[index] & 0x0f) |
 544                                                 (factor_toset << 4);
 545
 546                                 if ((p_regtoset[index] & 0x0f) > factor_toset)
 547                                         p_regtoset[index] =
 548                                                 (p_regtoset[index] & 0xf0) |
 549                                                 (factor_toset);
 550
 551                                 rtl_write_byte(rtlpriv,
 552                                                (REG_AGGLEN_LMT + index),
 553                                                p_regtoset[index]);
 554
 555                         }
 556
 557                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 558                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 559                                   factor_toset);
 560                 }
 561                 }
 562                 break;
 563         case HW_VAR_AC_PARAM:{
 564                 u8 e_aci = *((u8 *)val);
 565                 rtl8723_dm_init_edca_turbo(hw);
 566
 567                 if (rtlpci->acm_method != EACMWAY2_SW)
 568                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 569                                                       (u8 *)(&e_aci));
 570                 }
 571                 break;
 572         case HW_VAR_ACM_CTRL:{
 573                 u8 e_aci = *((u8 *)val);
 574                 union aci_aifsn *p_aci_aifsn =
 575                                 (union aci_aifsn *)(&(mac->ac[0].aifs));
 576                 u8 acm = p_aci_aifsn->f.acm;
 577                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 578
 579                 acm_ctrl =
 580                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 581
 582                 if (acm) {
 583                         switch (e_aci) {
 584                         case AC0_BE:
 585                                 acm_ctrl |= ACMHW_BEQEN;
 586                                 break;
 587                         case AC2_VI:
 588                                 acm_ctrl |= ACMHW_VIQEN;
 589                                 break;
 590                         case AC3_VO:
 591                                 acm_ctrl |= ACMHW_VOQEN;
 592                                 break;
 593                         default:
 594                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 595                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 596                                          acm);
 597                                 break;
 598                         }
 599                 } else {
 600                         switch (e_aci) {
 601                         case AC0_BE:
 602                                 acm_ctrl &= (~ACMHW_BEQEN);
 603                                 break;
 604                         case AC2_VI:
 605                                 acm_ctrl &= (~ACMHW_VIQEN);
 606                                 break;
 607                         case AC3_VO:
 608                                 acm_ctrl &= (~ACMHW_VOQEN);
 609                                 break;
 610                         default:
 611                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 612                                          "switch case %#x not processed\n",
 613                                          e_aci);
 614                                 break;
 615                         }
 616                 }
 617
 618                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 619                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 620                          acm_ctrl);
 621                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 622                 }
 623                 break;
 624         case HW_VAR_RCR:
 625                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 626                 rtlpci->receive_config = ((u32 *)(val))[0];
 627                 break;
 628         case HW_VAR_RETRY_LIMIT:{
 629                 u8 retry_limit = ((u8 *)(val))[0];
 630
 631                 rtl_write_word(rtlpriv, REG_RL,
 632                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 633                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 634                 }
 635                 break;
 636         case HW_VAR_DUAL_TSF_RST:
 637                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 638                 break;
 639         case HW_VAR_EFUSE_BYTES:
 640                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 641                 break;
 642         case HW_VAR_EFUSE_USAGE:
 643                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 644                 break;
 645         case HW_VAR_IO_CMD:
 646                 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
 647                 break;
 648         case HW_VAR_SET_RPWM:{
 649                 u8 rpwm_val;
 650
 651                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 652                 udelay(1);
 653
 654                 if (rpwm_val & BIT(7)) {
 655                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 656                 } else {
 657                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 658                                        ((*(u8 *)val) | BIT(7)));
 659                 }
 660                 }
 661                 break;
 662         case HW_VAR_H2C_FW_PWRMODE:
 663                 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 664                 break;
 665         case HW_VAR_FW_PSMODE_STATUS:
 666                 ppsc->fw_current_inpsmode = *((bool *)val);
 667                 break;
 668         case HW_VAR_RESUME_CLK_ON:
 669                 _rtl8723be_set_fw_ps_rf_on(hw);
 670                 break;
 671         case HW_VAR_FW_LPS_ACTION:{
 672                 bool b_enter_fwlps = *((bool *)val);
 673
 674                 if (b_enter_fwlps)
 675                         _rtl8723be_fwlps_enter(hw);
 676                 else
 677                         _rtl8723be_fwlps_leave(hw);
 678                 }
 679                 break;
 680         case HW_VAR_H2C_FW_JOINBSSRPT:{
 681                 u8 mstatus = (*(u8 *)val);
 682
 683                 if (mstatus == RT_MEDIA_CONNECT) {
 684                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 685                         _rtl8723be_download_rsvd_page(hw);
 686                 }
 687                 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
 688                 }
 689                 break;
 690         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 691                 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 692                 break;
 693         case HW_VAR_AID:{
 694                 u16 u2btmp;
 695                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 696                 u2btmp &= 0xC000;
 697                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 698                                (u2btmp | mac->assoc_id));
 699                 }
 700                 break;
 701         case HW_VAR_CORRECT_TSF:{
 702                 u8 btype_ibss = ((u8 *)(val))[0];
 703
 704                 if (btype_ibss)
 705                         _rtl8723be_stop_tx_beacon(hw);
 706
 707                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 708
 709                 rtl_write_dword(rtlpriv, REG_TSFTR,
 710                                 (u32) (mac->tsf & 0xffffffff));
 711                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 712                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 713
 714                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 715
 716                 if (btype_ibss)
 717                         _rtl8723be_resume_tx_beacon(hw);
 718                 }
 719                 break;
 720         case HW_VAR_KEEP_ALIVE:{
 721                 u8 array[2];
 722                 array[0] = 0xff;
 723                 array[1] = *((u8 *)val);
 724                 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
 725                 }
 726                 break;
 727         default:
 728                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 729                          "switch case %#x not processed\n", variable);
 730                 break;
 731         }
 732 }
 733
 734 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 735 {
 736         struct rtl_priv *rtlpriv = rtl_priv(hw);
 737         bool status = true;
 738         long count = 0;
 739         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 740                     _LLT_OP(_LLT_WRITE_ACCESS);
 741
 742         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 743
 744         do {
 745                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 746                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 747                         break;
 748
 749                 if (count > POLLING_LLT_THRESHOLD) {
 750                         pr_err("Failed to polling write LLT done at address %d!\n",
 751                                address);
 752                         status = false;
 753                         break;
 754                 }
 755         } while (++count);
 756
 757         return status;
 758 }
 759
 760 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
 761 {
 762         struct rtl_priv *rtlpriv = rtl_priv(hw);
 763         unsigned short i;
 764         u8 txpktbuf_bndy;
 765         u8 maxPage;
 766         bool status;
 767
 768         maxPage = 255;
 769         txpktbuf_bndy = 245;
 770
 771         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 772                         (0x27FF0000 | txpktbuf_bndy));
 773         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 774
 775         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 776         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 777
 778         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 779         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 780         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 781
 782         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 783                 status = _rtl8723be_llt_write(hw, i, i + 1);
 784                 if (!status)
 785                         return status;
 786         }
 787
 788         status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 789
 790         if (!status)
 791                 return status;
 792
 793         for (i = txpktbuf_bndy; i < maxPage; i++) {
 794                 status = _rtl8723be_llt_write(hw, i, (i + 1));
 795                 if (!status)
 796                         return status;
 797         }
 798
 799         status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
 800         if (!status)
 801                 return status;
 802
 803         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
 804         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 805
 806         return true;
 807 }
 808
 809 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 813         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 814
 815         if (rtlpriv->rtlhal.up_first_time)
 816                 return;
 817
 818         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 819                 rtl8723be_sw_led_on(hw, pled0);
 820         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 821                 rtl8723be_sw_led_on(hw, pled0);
 822         else
 823                 rtl8723be_sw_led_off(hw, pled0);
 824 }
 825
 826 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
 827 {
 828         struct rtl_priv *rtlpriv = rtl_priv(hw);
 829         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 830         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 831         unsigned char bytetmp;
 832         unsigned short wordtmp;
 833
 834         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 835
 836         /*Auto Power Down to CHIP-off State*/
 837         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 838         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 839
 840         /* HW Power on sequence */
 841         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 842                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 843                                       RTL8723_NIC_ENABLE_FLOW)) {
 844                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 845                          "init MAC Fail as power on failure\n");
 846                 return false;
 847         }
 848
 849         if (rtlpriv->cfg->ops->get_btc_status())
 850                 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
 851
 852         bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
 853         rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
 854
 855         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 856         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 857
 858         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 859         bytetmp = 0xff;
 860         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 861         mdelay(2);
 862
 863         bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
 864         bytetmp |= 0x7f;
 865         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 866         mdelay(2);
 867
 868         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 869         if (bytetmp & BIT(0)) {
 870                 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 871                 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
 872         }
 873
 874         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 875         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 876         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 877         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 878
 879         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 880
 881         if (!rtlhal->mac_func_enable) {
 882                 if (_rtl8723be_llt_table_init(hw) == false)
 883                         return false;
 884         }
 885
 886         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 887         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 888
 889         /* Enable FW Beamformer Interrupt */
 890         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 891         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 892
 893         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 894         wordtmp &= 0xf;
 895         wordtmp |= 0xF5B1;
 896         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 897
 898         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 899         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 900         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 901         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 902
 903         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 904                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 905                         DMA_BIT_MASK(32));
 906         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 907                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 908                         DMA_BIT_MASK(32));
 909         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 910                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 911         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 912                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 913         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 914                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 915         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 916                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 917         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 918                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 919                         DMA_BIT_MASK(32));
 920         rtl_write_dword(rtlpriv, REG_RX_DESA,
 921                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 922                         DMA_BIT_MASK(32));
 923
 924         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 925         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
 926
 927         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 928
 929         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 930
 931         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 932
 933         /* <20130114, Kordan> The following setting is
 934          * only for DPDT and Fixed board type.
 935          * TODO:  A better solution is configure it
 936          * according EFUSE during the run-time.
 937          */
 938         rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
 939         rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
 940         rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
 941         rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
 942         rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
 943         rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
 944         rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
 945         rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
 946
 947         bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
 948         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
 949
 950         _rtl8723be_gen_refresh_led_state(hw);
 951         return true;
 952 }
 953
 954 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
 955 {
 956         struct rtl_priv *rtlpriv = rtl_priv(hw);
 957         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 958         u32 reg_rrsr;
 959
 960         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 961         /* Init value for RRSR. */
 962         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 963
 964         /* ARFB table 9 for 11ac 5G 2SS */
 965         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
 966
 967         /* ARFB table 10 for 11ac 5G 1SS */
 968         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
 969
 970         /* CF-End setting. */
 971         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
 972
 973         /* 0x456 = 0x70, sugguested by Zhilin */
 974         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
 975
 976         /* Set retry limit */
 977         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 978
 979         /* Set Data / Response auto rate fallack retry count */
 980         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 981         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 982         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 983         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 984
 985         rtlpci->reg_bcn_ctrl_val = 0x1d;
 986         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 987
 988         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 989         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 990
 991         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 992
 993         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 994         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 995
 996         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
 997
 998         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
 999
1000         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
1001 }
1002
1003 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1004 {
1005         u16 read_addr = addr & 0xfffc;
1006         u8 ret = 0, tmp = 0, count = 0;
1007
1008         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1009         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1010         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1011         count = 0;
1012         while (tmp && count < 20) {
1013                 udelay(10);
1014                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1015                 count++;
1016         }
1017         if (0 == tmp) {
1018                 read_addr = REG_DBI_RDATA + addr % 4;
1019                 ret = rtl_read_byte(rtlpriv, read_addr);
1020         }
1021
1022         return ret;
1023 }
1024
1025 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1026 {
1027         u8 tmp = 0, count = 0;
1028         u16 write_addr = 0, remainder = addr % 4;
1029
1030         /* Write DBI 1Byte Data */
1031         write_addr = REG_DBI_WDATA + remainder;
1032         rtl_write_byte(rtlpriv, write_addr, data);
1033
1034         /* Write DBI 2Byte Address & Write Enable */
1035         write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1036         rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1037
1038         /* Write DBI Write Flag */
1039         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1040
1041         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1042         count = 0;
1043         while (tmp && count < 20) {
1044                 udelay(10);
1045                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1046                 count++;
1047         }
1048 }
1049
1050 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1051 {
1052         u16 ret = 0;
1053         u8 tmp = 0, count = 0;
1054
1055         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1056         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1057         count = 0;
1058         while (tmp && count < 20) {
1059                 udelay(10);
1060                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1061                 count++;
1062         }
1063
1064         if (0 == tmp)
1065                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1066
1067         return ret;
1068 }
1069
1070 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1071 {
1072         u8 tmp = 0, count = 0;
1073
1074         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1075         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1076         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1077         count = 0;
1078         while (tmp && count < 20) {
1079                 udelay(10);
1080                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1081                 count++;
1082         }
1083 }
1084
1085 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1086 {
1087         struct rtl_priv *rtlpriv = rtl_priv(hw);
1088         u8 tmp8 = 0;
1089         u16 tmp16 = 0;
1090
1091         /* <Roger_Notes> Overwrite following ePHY parameter for
1092          * some platform compatibility issue,
1093          * especially when CLKReq is enabled, 2012.11.09.
1094          */
1095         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1096         if (tmp16 != 0x0663)
1097                 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1098
1099         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1100         if (tmp16 != 0x7544)
1101                 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1102
1103         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1104         if (tmp16 != 0xB880)
1105                 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1106
1107         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1108         if (tmp16 != 0x4000)
1109                 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1110
1111         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1112         if (tmp16 != 0x9003)
1113                 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1114
1115         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1116         if (tmp16 != 0x0D03)
1117                 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1118
1119         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1120         if (tmp16 != 0x4037)
1121                 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1122
1123         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1124         if (tmp16 != 0x0070)
1125                 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1126
1127         /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1128         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1129         _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1130                              ASPM_L1_LATENCY << 3);
1131
1132         /* Configuration Space offset 0x719 Bit3 is for L1
1133          * BIT4 is for clock request
1134          */
1135         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1136         _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1137 }
1138
1139 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1140 {
1141         struct rtl_priv *rtlpriv = rtl_priv(hw);
1142         u8 sec_reg_value;
1143
1144         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1145                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1146                   rtlpriv->sec.pairwise_enc_algorithm,
1147                   rtlpriv->sec.group_enc_algorithm);
1148
1149         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1150                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1151                          "not open hw encryption\n");
1152                 return;
1153         }
1154
1155         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1156
1157         if (rtlpriv->sec.use_defaultkey) {
1158                 sec_reg_value |= SCR_TXUSEDK;
1159                 sec_reg_value |= SCR_RXUSEDK;
1160         }
1161
1162         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1163
1164         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1165
1166         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1167                  "The SECR-value %x\n", sec_reg_value);
1168
1169         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1170 }
1171
1172 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1173 {
1174         struct rtl_priv *rtlpriv = rtl_priv(hw);
1175         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1176         u8 u1b_tmp;
1177
1178         rtlhal->mac_func_enable = false;
1179         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1180         /* 1. Run LPS WL RFOFF flow */
1181         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1182                                  PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1183
1184         /* 2. 0x1F[7:0] = 0 */
1185         /* turn off RF */
1186         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1187         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1188             rtlhal->fw_ready) {
1189                 rtl8723be_firmware_selfreset(hw);
1190         }
1191
1192         /* Reset MCU. Suggested by Filen. */
1193         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1194         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1195
1196         /* g.   MCUFWDL 0x80[1:0]=0      */
1197         /* reset MCU ready status */
1198         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1199
1200         /* HW card disable configuration. */
1201         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1202                                  PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1203
1204         /* Reset MCU IO Wrapper */
1205         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1206         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1207         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1208         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1209
1210         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1211         /* lock ISO/CLK/Power control register */
1212         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1213 }
1214
1215 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1216 {
1217         u8 tmp;
1218
1219         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1220         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1221         if (!(tmp & BIT(2))) {
1222                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1223                 mdelay(100); /* Suggested by DD Justin_tsai. */
1224         }
1225
1226         /* read reg 0x350 Bit[25] if 1 : RX hang
1227          * read reg 0x350 Bit[24] if 1 : TX hang
1228          */
1229         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1230         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1231                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1232                          "CheckPcieDMAHang8723BE(): true!!\n");
1233                 return true;
1234         }
1235         return false;
1236 }
1237
1238 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1239                                                 bool mac_power_on)
1240 {
1241         u8 tmp;
1242         bool release_mac_rx_pause;
1243         u8 backup_pcie_dma_pause;
1244
1245         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1246                  "ResetPcieInterfaceDMA8723BE()\n");
1247
1248         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1249          * released by SD1 Alan.
1250          * 2013.05.07, by tynli.
1251          */
1252
1253         /* 1. disable register write lock
1254          *      write 0x1C bit[1:0] = 2'h0
1255          *      write 0xCC bit[2] = 1'b1
1256          */
1257         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1258         tmp &= ~(BIT(1) | BIT(0));
1259         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1260         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1261         tmp |= BIT(2);
1262         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1263
1264         /* 2. Check and pause TRX DMA
1265          *      write 0x284 bit[18] = 1'b1
1266          *      write 0x301 = 0xFF
1267          */
1268         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1269         if (tmp & BIT(2)) {
1270                 /* Already pause before the function for another purpose. */
1271                 release_mac_rx_pause = false;
1272         } else {
1273                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1274                 release_mac_rx_pause = true;
1275         }
1276
1277         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1278         if (backup_pcie_dma_pause != 0xFF)
1279                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1280
1281         if (mac_power_on) {
1282                 /* 3. reset TRX function
1283                  *      write 0x100 = 0x00
1284                  */
1285                 rtl_write_byte(rtlpriv, REG_CR, 0);
1286         }
1287
1288         /* 4. Reset PCIe DMA
1289          *      write 0x003 bit[0] = 0
1290          */
1291         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1292         tmp &= ~(BIT(0));
1293         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1294
1295         /* 5. Enable PCIe DMA
1296          *      write 0x003 bit[0] = 1
1297          */
1298         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1299         tmp |= BIT(0);
1300         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1301
1302         if (mac_power_on) {
1303                 /* 6. enable TRX function
1304                  *      write 0x100 = 0xFF
1305                  */
1306                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1307
1308                 /* We should init LLT & RQPN and
1309                  * prepare Tx/Rx descrptor address later
1310                  * because MAC function is reset.
1311                  */
1312         }
1313
1314         /* 7. Restore PCIe autoload down bit
1315          *      write 0xF8 bit[17] = 1'b1
1316          */
1317         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1318         tmp |= BIT(1);
1319         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1320
1321         /* In MAC power on state, BB and RF maybe in ON state,
1322          * if we release TRx DMA here
1323          * it will cause packets to be started to Tx/Rx,
1324          * so we release Tx/Rx DMA later.
1325          */
1326         if (!mac_power_on) {
1327                 /* 8. release TRX DMA
1328                  *      write 0x284 bit[18] = 1'b0
1329                  *      write 0x301 = 0x00
1330                  */
1331                 if (release_mac_rx_pause) {
1332                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1333                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1334                                        (tmp & (~BIT(2))));
1335                 }
1336                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1337                                backup_pcie_dma_pause);
1338         }
1339
1340         /* 9. lock system register
1341          *      write 0xCC bit[2] = 1'b0
1342          */
1343         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1344         tmp &= ~(BIT(2));
1345         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1346 }
1347
1348 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1349 {
1350         struct rtl_priv *rtlpriv = rtl_priv(hw);
1351         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1352         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1353         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1354         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1355         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1356         bool rtstatus = true;
1357         int err;
1358         u8 tmp_u1b;
1359         unsigned long flags;
1360
1361         /* reenable interrupts to not interfere with other devices */
1362         local_save_flags(flags);
1363         local_irq_enable();
1364
1365         rtlhal->fw_ready = false;
1366         rtlpriv->rtlhal.being_init_adapter = true;
1367         rtlpriv->intf_ops->disable_aspm(hw);
1368
1369         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1370         if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1371                 rtlhal->mac_func_enable = true;
1372         } else {
1373                 rtlhal->mac_func_enable = false;
1374                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1375         }
1376
1377         if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1378                 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1379                                                     rtlhal->mac_func_enable);
1380                 rtlhal->mac_func_enable = false;
1381         }
1382         if (rtlhal->mac_func_enable) {
1383                 _rtl8723be_poweroff_adapter(hw);
1384                 rtlhal->mac_func_enable = false;
1385         }
1386         rtstatus = _rtl8723be_init_mac(hw);
1387         if (!rtstatus) {
1388                 pr_err("Init MAC failed\n");
1389                 err = 1;
1390                 goto exit;
1391         }
1392
1393         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1394         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1395
1396         err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1397         if (err) {
1398                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1399                          "Failed to download FW. Init HW without FW now..\n");
1400                 err = 1;
1401                 goto exit;
1402         }
1403         rtlhal->fw_ready = true;
1404
1405         rtlhal->last_hmeboxnum = 0;
1406         rtl8723be_phy_mac_config(hw);
1407         /* because last function modify RCR, so we update
1408          * rcr var here, or TP will unstable for receive_config
1409          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1410          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1411          */
1412         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1413         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1414         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1415
1416         rtl8723be_phy_bb_config(hw);
1417         rtl8723be_phy_rf_config(hw);
1418
1419         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1420                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1421         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1422                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1423         rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1424         rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1425
1426         _rtl8723be_hw_configure(hw);
1427         rtlhal->mac_func_enable = true;
1428         rtl_cam_reset_all_entry(hw);
1429         rtl8723be_enable_hw_security_config(hw);
1430
1431         ppsc->rfpwr_state = ERFON;
1432
1433         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1434         _rtl8723be_enable_aspm_back_door(hw);
1435         rtlpriv->intf_ops->enable_aspm(hw);
1436
1437         rtl8723be_bt_hw_init(hw);
1438
1439         if (ppsc->rfpwr_state == ERFON) {
1440                 rtl8723be_phy_set_rfpath_switch(hw, 1);
1441                 /* when use 1ant NIC, iqk will disturb BT music
1442                  * root cause is not clear now, is something
1443                  * related with 'mdelay' and Reg[0x948]
1444                  */
1445                 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1446                     !rtlpriv->cfg->ops->get_btc_status()) {
1447                         rtl8723be_phy_iq_calibrate(hw,
1448                                                    (rtlphy->iqk_initialized ?
1449                                                     true : false));
1450                         rtlphy->iqk_initialized = true;
1451                 }
1452                 rtl8723be_dm_check_txpower_tracking(hw);
1453                 rtl8723be_phy_lc_calibrate(hw);
1454         }
1455         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1456
1457         /* Release Rx DMA. */
1458         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1459         if (tmp_u1b & BIT(2)) {
1460                 /* Release Rx DMA if needed */
1461                 tmp_u1b &= (~BIT(2));
1462                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1463         }
1464         /* Release Tx/Rx PCIE DMA. */
1465         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1466
1467         rtl8723be_dm_init(hw);
1468 exit:
1469         local_irq_restore(flags);
1470         rtlpriv->rtlhal.being_init_adapter = false;
1471         return err;
1472 }
1473
1474 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1475 {
1476         struct rtl_priv *rtlpriv = rtl_priv(hw);
1477         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1478         enum version_8723e version = VERSION_UNKNOWN;
1479         u32 value32;
1480
1481         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1482         if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1483                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1484         else
1485                 version = (enum version_8723e)CHIP_8723B;
1486
1487         rtlphy->rf_type = RF_1T1R;
1488
1489         /* treat rtl8723be chip as  MP version in default */
1490         version = (enum version_8723e)(version | NORMAL_CHIP);
1491
1492         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1493         /* cut version */
1494         version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1495         /* Manufacture */
1496         if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1497                 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1498
1499         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1500                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1501                   "RF_2T2R" : "RF_1T1R");
1502
1503         return version;
1504 }
1505
1506 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1507                                        enum nl80211_iftype type)
1508 {
1509         struct rtl_priv *rtlpriv = rtl_priv(hw);
1510         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1511         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1512         u8 mode = MSR_NOLINK;
1513
1514         switch (type) {
1515         case NL80211_IFTYPE_UNSPECIFIED:
1516                 mode = MSR_NOLINK;
1517                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518                          "Set Network type to NO LINK!\n");
1519                 break;
1520         case NL80211_IFTYPE_ADHOC:
1521         case NL80211_IFTYPE_MESH_POINT:
1522                 mode = MSR_ADHOC;
1523                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1524                          "Set Network type to Ad Hoc!\n");
1525                 break;
1526         case NL80211_IFTYPE_STATION:
1527                 mode = MSR_INFRA;
1528                 ledaction = LED_CTL_LINK;
1529                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1530                          "Set Network type to STA!\n");
1531                 break;
1532         case NL80211_IFTYPE_AP:
1533                 mode = MSR_AP;
1534                 ledaction = LED_CTL_LINK;
1535                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1536                          "Set Network type to AP!\n");
1537                 break;
1538         default:
1539                 pr_err("Network type %d not support!\n", type);
1540                 return 1;
1541         }
1542
1543         /* MSR_INFRA == Link in infrastructure network;
1544          * MSR_ADHOC == Link in ad hoc network;
1545          * Therefore, check link state is necessary.
1546          *
1547          * MSR_AP == AP mode; link state is not cared here.
1548          */
1549         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1550                 mode = MSR_NOLINK;
1551                 ledaction = LED_CTL_NO_LINK;
1552         }
1553
1554         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1555                 _rtl8723be_stop_tx_beacon(hw);
1556                 _rtl8723be_enable_bcn_sub_func(hw);
1557         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1558                 _rtl8723be_resume_tx_beacon(hw);
1559                 _rtl8723be_disable_bcn_sub_func(hw);
1560         } else {
1561                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1562                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1563                          mode);
1564         }
1565
1566         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1567         rtlpriv->cfg->ops->led_control(hw, ledaction);
1568         if (mode == MSR_AP)
1569                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1570         else
1571                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1572         return 0;
1573 }
1574
1575 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1576 {
1577         struct rtl_priv *rtlpriv = rtl_priv(hw);
1578         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1579         u32 reg_rcr = rtlpci->receive_config;
1580
1581         if (rtlpriv->psc.rfpwr_state != ERFON)
1582                 return;
1583
1584         if (check_bssid) {
1585                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1586                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1587                                               (u8 *)(&reg_rcr));
1588                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1589         } else if (!check_bssid) {
1590                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1591                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1592                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1593                                               (u8 *)(&reg_rcr));
1594         }
1595
1596 }
1597
1598 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1599                                enum nl80211_iftype type)
1600 {
1601         struct rtl_priv *rtlpriv = rtl_priv(hw);
1602
1603         if (_rtl8723be_set_media_status(hw, type))
1604                 return -EOPNOTSUPP;
1605
1606         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1607                 if (type != NL80211_IFTYPE_AP)
1608                         rtl8723be_set_check_bssid(hw, true);
1609         } else {
1610                 rtl8723be_set_check_bssid(hw, false);
1611         }
1612
1613         return 0;
1614 }
1615
1616 /* don't set REG_EDCA_BE_PARAM here
1617  * because mac80211 will send pkt when scan
1618  */
1619 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1620 {
1621         struct rtl_priv *rtlpriv = rtl_priv(hw);
1622
1623         rtl8723_dm_init_edca_turbo(hw);
1624         switch (aci) {
1625         case AC1_BK:
1626                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1627                 break;
1628         case AC0_BE:
1629                 break;
1630         case AC2_VI:
1631                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1632                 break;
1633         case AC3_VO:
1634                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1635                 break;
1636         default:
1637                 WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci);
1638                 break;
1639         }
1640 }
1641
1642 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1643 {
1644         struct rtl_priv *rtlpriv = rtl_priv(hw);
1645         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1646
1647         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1648         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1649         rtlpci->irq_enabled = true;
1650
1651         /*enable system interrupt*/
1652         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1653 }
1654
1655 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1656 {
1657         struct rtl_priv *rtlpriv = rtl_priv(hw);
1658         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1659
1660         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1661         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1662         rtlpci->irq_enabled = false;
1663         /*synchronize_irq(rtlpci->pdev->irq);*/
1664 }
1665
1666 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1667 {
1668         struct rtl_priv *rtlpriv = rtl_priv(hw);
1669         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1670         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1671         enum nl80211_iftype opmode;
1672
1673         mac->link_state = MAC80211_NOLINK;
1674         opmode = NL80211_IFTYPE_UNSPECIFIED;
1675         _rtl8723be_set_media_status(hw, opmode);
1676         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1677             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1678                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1679         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1680         _rtl8723be_poweroff_adapter(hw);
1681
1682         /* after power off we should do iqk again */
1683         if (!rtlpriv->cfg->ops->get_btc_status())
1684                 rtlpriv->phy.iqk_initialized = false;
1685 }
1686
1687 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1688                                     u32 *p_inta, u32 *p_intb)
1689 {
1690         struct rtl_priv *rtlpriv = rtl_priv(hw);
1691         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1692
1693         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1694         rtl_write_dword(rtlpriv, ISR, *p_inta);
1695
1696         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1697                                         rtlpci->irq_mask[1];
1698         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1699 }
1700
1701 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1702 {
1703         struct rtl_priv *rtlpriv = rtl_priv(hw);
1704         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1705         u16 bcn_interval, atim_window;
1706
1707         bcn_interval = mac->beacon_interval;
1708         atim_window = 2;        /*FIX MERGE */
1709         rtl8723be_disable_interrupt(hw);
1710         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1711         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1712         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1713         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1714         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1715         rtl_write_byte(rtlpriv, 0x606, 0x30);
1716         rtl8723be_enable_interrupt(hw);
1717 }
1718
1719 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1720 {
1721         struct rtl_priv *rtlpriv = rtl_priv(hw);
1722         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1723         u16 bcn_interval = mac->beacon_interval;
1724
1725         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1726                  "beacon_interval:%d\n", bcn_interval);
1727         rtl8723be_disable_interrupt(hw);
1728         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1729         rtl8723be_enable_interrupt(hw);
1730 }
1731
1732 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1733                                    u32 add_msr, u32 rm_msr)
1734 {
1735         struct rtl_priv *rtlpriv = rtl_priv(hw);
1736         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1737
1738         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1739                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1740
1741         if (add_msr)
1742                 rtlpci->irq_mask[0] |= add_msr;
1743         if (rm_msr)
1744                 rtlpci->irq_mask[0] &= (~rm_msr);
1745         rtl8723be_disable_interrupt(hw);
1746         rtl8723be_enable_interrupt(hw);
1747 }
1748
1749 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1750 {
1751         u8 group;
1752
1753         if (chnl < 3)
1754                 group = 0;
1755         else if (chnl < 9)
1756                 group = 1;
1757         else
1758                 group = 2;
1759         return group;
1760 }
1761
1762 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1763                                         struct txpower_info_2g *pw2g,
1764                                         struct txpower_info_5g *pw5g,
1765                                         bool autoload_fail, u8 *hwinfo)
1766 {
1767         struct rtl_priv *rtlpriv = rtl_priv(hw);
1768         u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1769
1770         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1771                  "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1772                  (addr + 1), hwinfo[addr + 1]);
1773         if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
1774                 autoload_fail = true;
1775
1776         if (autoload_fail) {
1777                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1778                          "auto load fail : Use Default value!\n");
1779                 for (path = 0; path < MAX_RF_PATH; path++) {
1780                         /* 2.4G default value */
1781                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1782                                 pw2g->index_cck_base[path][group] = 0x2D;
1783                                 pw2g->index_bw40_base[path][group] = 0x2D;
1784                         }
1785                         for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1786                                 if (cnt == 0) {
1787                                         pw2g->bw20_diff[path][0] = 0x02;
1788                                         pw2g->ofdm_diff[path][0] = 0x04;
1789                                 } else {
1790                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1791                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1792                                         pw2g->cck_diff[path][cnt] = 0xFE;
1793                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1794                                 }
1795                         }
1796                 }
1797                 return;
1798         }
1799
1800         for (path = 0; path < MAX_RF_PATH; path++) {
1801                 /*2.4G default value*/
1802                 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1803                         pw2g->index_cck_base[path][group] = hwinfo[addr++];
1804                         if (pw2g->index_cck_base[path][group] == 0xFF)
1805                                 pw2g->index_cck_base[path][group] = 0x2D;
1806
1807                 }
1808                 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1809                         pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1810                         if (pw2g->index_bw40_base[path][group] == 0xFF)
1811                                 pw2g->index_bw40_base[path][group] = 0x2D;
1812                 }
1813                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1814                         if (cnt == 0) {
1815                                 pw2g->bw40_diff[path][cnt] = 0;
1816                                 if (hwinfo[addr] == 0xFF) {
1817                                         pw2g->bw20_diff[path][cnt] = 0x02;
1818                                 } else {
1819                                         pw2g->bw20_diff[path][cnt] =
1820                                                 (hwinfo[addr] & 0xf0) >> 4;
1821                                         /*bit sign number to 8 bit sign number*/
1822                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1823                                                 pw2g->bw20_diff[path][cnt] |=
1824                                                                           0xF0;
1825                                 }
1826
1827                                 if (hwinfo[addr] == 0xFF) {
1828                                         pw2g->ofdm_diff[path][cnt] = 0x04;
1829                                 } else {
1830                                         pw2g->ofdm_diff[path][cnt] =
1831                                                         (hwinfo[addr] & 0x0f);
1832                                         /*bit sign number to 8 bit sign number*/
1833                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1834                                                 pw2g->ofdm_diff[path][cnt] |=
1835                                                                           0xF0;
1836                                 }
1837                                 pw2g->cck_diff[path][cnt] = 0;
1838                                 addr++;
1839                         } else {
1840                                 if (hwinfo[addr] == 0xFF) {
1841                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1842                                 } else {
1843                                         pw2g->bw40_diff[path][cnt] =
1844                                                 (hwinfo[addr] & 0xf0) >> 4;
1845                                         if (pw2g->bw40_diff[path][cnt] & BIT(3))
1846                                                 pw2g->bw40_diff[path][cnt] |=
1847                                                                           0xF0;
1848                                 }
1849
1850                                 if (hwinfo[addr] == 0xFF) {
1851                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1852                                 } else {
1853                                         pw2g->bw20_diff[path][cnt] =
1854                                                         (hwinfo[addr] & 0x0f);
1855                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1856                                                 pw2g->bw20_diff[path][cnt] |=
1857                                                                           0xF0;
1858                                 }
1859                                 addr++;
1860
1861                                 if (hwinfo[addr] == 0xFF) {
1862                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1863                                 } else {
1864                                         pw2g->ofdm_diff[path][cnt] =
1865                                                 (hwinfo[addr] & 0xf0) >> 4;
1866                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1867                                                 pw2g->ofdm_diff[path][cnt] |=
1868                                                                           0xF0;
1869                                 }
1870
1871                                 if (hwinfo[addr] == 0xFF)
1872                                         pw2g->cck_diff[path][cnt] = 0xFE;
1873                                 else {
1874                                         pw2g->cck_diff[path][cnt] =
1875                                                         (hwinfo[addr] & 0x0f);
1876                                         if (pw2g->cck_diff[path][cnt] & BIT(3))
1877                                                 pw2g->cck_diff[path][cnt] |=
1878                                                                          0xF0;
1879                                 }
1880                                 addr++;
1881                         }
1882                 }
1883
1884                 /*5G default value*/
1885                 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1886                         pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1887                         if (pw5g->index_bw40_base[path][group] == 0xFF)
1888                                 pw5g->index_bw40_base[path][group] = 0xFE;
1889                 }
1890
1891                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1892                         if (cnt == 0) {
1893                                 pw5g->bw40_diff[path][cnt] = 0;
1894
1895                                 if (hwinfo[addr] == 0xFF) {
1896                                         pw5g->bw20_diff[path][cnt] = 0;
1897                                 } else {
1898                                         pw5g->bw20_diff[path][0] =
1899                                                 (hwinfo[addr] & 0xf0) >> 4;
1900                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1901                                                 pw5g->bw20_diff[path][cnt] |=
1902                                                                           0xF0;
1903                                 }
1904
1905                                 if (hwinfo[addr] == 0xFF)
1906                                         pw5g->ofdm_diff[path][cnt] = 0x04;
1907                                 else {
1908                                         pw5g->ofdm_diff[path][0] =
1909                                                         (hwinfo[addr] & 0x0f);
1910                                         if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1911                                                 pw5g->ofdm_diff[path][cnt] |=
1912                                                                           0xF0;
1913                                 }
1914                                 addr++;
1915                         } else {
1916                                 if (hwinfo[addr] == 0xFF) {
1917                                         pw5g->bw40_diff[path][cnt] = 0xFE;
1918                                 } else {
1919                                         pw5g->bw40_diff[path][cnt] =
1920                                                 (hwinfo[addr] & 0xf0) >> 4;
1921                                         if (pw5g->bw40_diff[path][cnt] & BIT(3))
1922                                                 pw5g->bw40_diff[path][cnt] |= 0xF0;
1923                                 }
1924
1925                                 if (hwinfo[addr] == 0xFF) {
1926                                         pw5g->bw20_diff[path][cnt] = 0xFE;
1927                                 } else {
1928                                         pw5g->bw20_diff[path][cnt] =
1929                                                         (hwinfo[addr] & 0x0f);
1930                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1931                                                 pw5g->bw20_diff[path][cnt] |= 0xF0;
1932                                 }
1933                                 addr++;
1934                         }
1935                 }
1936
1937                 if (hwinfo[addr] == 0xFF) {
1938                         pw5g->ofdm_diff[path][1] = 0xFE;
1939                         pw5g->ofdm_diff[path][2] = 0xFE;
1940                 } else {
1941                         pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1942                         pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1943                 }
1944                 addr++;
1945
1946                 if (hwinfo[addr] == 0xFF)
1947                         pw5g->ofdm_diff[path][3] = 0xFE;
1948                 else
1949                         pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1950                 addr++;
1951
1952                 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1953                         if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1954                                 pw5g->ofdm_diff[path][cnt] = 0xFE;
1955                         else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1956                                 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1957                 }
1958         }
1959 }
1960
1961 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1962                                                    bool autoload_fail,
1963                                                    u8 *hwinfo)
1964 {
1965         struct rtl_priv *rtlpriv = rtl_priv(hw);
1966         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1967         struct txpower_info_2g pw2g;
1968         struct txpower_info_5g pw5g;
1969         u8 rf_path, index;
1970         u8 i;
1971
1972         _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1973                                              hwinfo);
1974
1975         for (rf_path = 0; rf_path < 2; rf_path++) {
1976                 for (i = 0; i < 14; i++) {
1977                         index = _rtl8723be_get_chnl_group(i+1);
1978
1979                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1980                                         pw2g.index_cck_base[rf_path][index];
1981                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1982                                         pw2g.index_bw40_base[rf_path][index];
1983                 }
1984                 for (i = 0; i < MAX_TX_COUNT; i++) {
1985                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1986                                                 pw2g.bw20_diff[rf_path][i];
1987                         rtlefuse->txpwr_ht40diff[rf_path][i] =
1988                                                 pw2g.bw40_diff[rf_path][i];
1989                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1990                                                 pw2g.ofdm_diff[rf_path][i];
1991                 }
1992
1993                 for (i = 0; i < 14; i++) {
1994                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1995                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1996                                 rf_path, i,
1997                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1998                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1999                 }
2000         }
2001
2002         if (!autoload_fail)
2003                 rtlefuse->eeprom_thermalmeter =
2004                                         hwinfo[EEPROM_THERMAL_METER_88E];
2005         else
2006                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2007
2008         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
2009                 rtlefuse->apk_thermalmeterignore = true;
2010                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2011         }
2012
2013         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2014         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2015                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
2016
2017         if (!autoload_fail) {
2018                 rtlefuse->eeprom_regulatory =
2019                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2020                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2021                         rtlefuse->eeprom_regulatory = 0;
2022         } else {
2023                 rtlefuse->eeprom_regulatory = 0;
2024         }
2025         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2026                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2027 }
2028
2029 static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw)
2030 {
2031         u8 package_type;
2032         u8 value;
2033
2034         efuse_power_switch(hw, false, true);
2035         if (!efuse_one_byte_read(hw, 0x1FB, &value))
2036                 value = 0;
2037         efuse_power_switch(hw, false, false);
2038
2039         switch (value & 0x7) {
2040         case 0x4:
2041                 package_type = PACKAGE_TFBGA79;
2042                 break;
2043         case 0x5:
2044                 package_type = PACKAGE_TFBGA90;
2045                 break;
2046         case 0x6:
2047                 package_type = PACKAGE_QFN68;
2048                 break;
2049         case 0x7:
2050                 package_type = PACKAGE_TFBGA80;
2051                 break;
2052         default:
2053                 package_type = PACKAGE_DEFAULT;
2054                 break;
2055         }
2056
2057         return package_type;
2058 }
2059
2060 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2061                                          bool pseudo_test)
2062 {
2063         struct rtl_priv *rtlpriv = rtl_priv(hw);
2064         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2065         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2066         int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2067                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2068                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2069                         COUNTRY_CODE_WORLD_WIDE_13};
2070         u8 *hwinfo;
2071         int i;
2072         bool is_toshiba_smid1 = false;
2073         bool is_toshiba_smid2 = false;
2074         bool is_samsung_smid = false;
2075         bool is_lenovo_smid = false;
2076         u16 toshiba_smid1[] = {
2077                 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2078                 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2079                 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2080                 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2081         };
2082         u16 toshiba_smid2[] = {
2083                 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2084                 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2085         };
2086         u16 samsung_smid[] = {
2087                 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2088                 0x8193, 0x9191, 0x9192, 0x9193
2089         };
2090         u16 lenovo_smid[] = {
2091                 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2092         };
2093
2094         if (pseudo_test) {
2095                 /* needs to be added */
2096                 return;
2097         }
2098
2099         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2100         if (!hwinfo)
2101                 return;
2102
2103         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2104                 goto exit;
2105
2106         /*parse xtal*/
2107         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2108         if (rtlefuse->crystalcap == 0xFF)
2109                 rtlefuse->crystalcap = 0x20;
2110
2111         _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2112                                                hwinfo);
2113
2114         rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2115                                                  rtlefuse->autoload_failflag,
2116                                                  hwinfo);
2117
2118         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
2119                 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
2120
2121         rtlhal->board_type = rtlefuse->board_type;
2122         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2123                  "board_type = 0x%x\n", rtlefuse->board_type);
2124
2125         rtlhal->package_type = _rtl8723be_read_package_type(hw);
2126
2127         /* set channel plan from efuse */
2128         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2129
2130         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2131                 /* Does this one have a Toshiba SMID from group 1? */
2132                 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
2133                         if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2134                                 is_toshiba_smid1 = true;
2135                                 break;
2136                         }
2137                 }
2138                 /* Does this one have a Toshiba SMID from group 2? */
2139                 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
2140                         if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2141                                 is_toshiba_smid2 = true;
2142                                 break;
2143                         }
2144                 }
2145                 /* Does this one have a Samsung SMID? */
2146                 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
2147                         if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2148                                 is_samsung_smid = true;
2149                                 break;
2150                         }
2151                 }
2152                 /* Does this one have a Lenovo SMID? */
2153                 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
2154                         if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2155                                 is_lenovo_smid = true;
2156                                 break;
2157                         }
2158                 }
2159                 switch (rtlefuse->eeprom_oemid) {
2160                 case EEPROM_CID_DEFAULT:
2161                         if (rtlefuse->eeprom_did == 0x8176) {
2162                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2163                                     is_toshiba_smid1) {
2164                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2165                                 } else if (rtlefuse->eeprom_svid == 0x1025) {
2166                                         rtlhal->oem_id = RT_CID_819X_ACER;
2167                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2168                                            is_samsung_smid) {
2169                                         rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2170                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2171                                            is_lenovo_smid) {
2172                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2173                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2174                                             rtlefuse->eeprom_smid == 0x8197) ||
2175                                            (rtlefuse->eeprom_svid == 0x10EC &&
2176                                             rtlefuse->eeprom_smid == 0x9196)) {
2177                                         rtlhal->oem_id = RT_CID_819X_CLEVO;
2178                                 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2179                                             rtlefuse->eeprom_smid == 0x8194) ||
2180                                            (rtlefuse->eeprom_svid == 0x1028 &&
2181                                             rtlefuse->eeprom_smid == 0x8198) ||
2182                                            (rtlefuse->eeprom_svid == 0x1028 &&
2183                                             rtlefuse->eeprom_smid == 0x9197) ||
2184                                            (rtlefuse->eeprom_svid == 0x1028 &&
2185                                             rtlefuse->eeprom_smid == 0x9198)) {
2186                                         rtlhal->oem_id = RT_CID_819X_DELL;
2187                                 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2188                                             rtlefuse->eeprom_smid == 0x1629)) {
2189                                         rtlhal->oem_id = RT_CID_819X_HP;
2190                                 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2191                                            rtlefuse->eeprom_smid == 0x2315)) {
2192                                         rtlhal->oem_id = RT_CID_819X_QMI;
2193                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2194                                            rtlefuse->eeprom_smid == 0x8203)) {
2195                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2196                                 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2197                                            rtlefuse->eeprom_smid == 0x84B5)) {
2198                                         rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2199                                 } else {
2200                                         rtlhal->oem_id = RT_CID_DEFAULT;
2201                                 }
2202                         } else if (rtlefuse->eeprom_did == 0x8178) {
2203                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2204                                     is_toshiba_smid2)
2205                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2206                                 else if (rtlefuse->eeprom_svid == 0x1025)
2207                                         rtlhal->oem_id = RT_CID_819X_ACER;
2208                                 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2209                                           rtlefuse->eeprom_smid == 0x8186))
2210                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2211                                 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2212                                           rtlefuse->eeprom_smid == 0x84B6))
2213                                         rtlhal->oem_id =
2214                                                         RT_CID_819X_EDIMAX_ASUS;
2215                                 else
2216                                         rtlhal->oem_id = RT_CID_DEFAULT;
2217                         } else {
2218                                         rtlhal->oem_id = RT_CID_DEFAULT;
2219                         }
2220                         break;
2221                 case EEPROM_CID_TOSHIBA:
2222                         rtlhal->oem_id = RT_CID_TOSHIBA;
2223                         break;
2224                 case EEPROM_CID_CCX:
2225                         rtlhal->oem_id = RT_CID_CCX;
2226                         break;
2227                 case EEPROM_CID_QMI:
2228                         rtlhal->oem_id = RT_CID_819X_QMI;
2229                         break;
2230                 case EEPROM_CID_WHQL:
2231                         break;
2232                 default:
2233                         rtlhal->oem_id = RT_CID_DEFAULT;
2234                         break;
2235                 }
2236         }
2237 exit:
2238         kfree(hwinfo);
2239 }
2240
2241 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2242 {
2243         struct rtl_priv *rtlpriv = rtl_priv(hw);
2244         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2245
2246         rtlpriv->ledctl.led_opendrain = true;
2247         switch (rtlhal->oem_id) {
2248         case RT_CID_819X_HP:
2249                 rtlpriv->ledctl.led_opendrain = true;
2250                 break;
2251         case RT_CID_819X_LENOVO:
2252         case RT_CID_DEFAULT:
2253         case RT_CID_TOSHIBA:
2254         case RT_CID_CCX:
2255         case RT_CID_819X_ACER:
2256         case RT_CID_WHQL:
2257         default:
2258                 break;
2259         }
2260         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2261                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2262 }
2263
2264 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2265 {
2266         struct rtl_priv *rtlpriv = rtl_priv(hw);
2267         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2268         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2269         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2270         u8 tmp_u1b;
2271
2272         rtlhal->version = _rtl8723be_read_chip_version(hw);
2273         if (get_rf_type(rtlphy) == RF_1T1R)
2274                 rtlpriv->dm.rfpath_rxenable[0] = true;
2275         else
2276                 rtlpriv->dm.rfpath_rxenable[0] =
2277                     rtlpriv->dm.rfpath_rxenable[1] = true;
2278         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2279                  rtlhal->version);
2280         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2281         if (tmp_u1b & BIT(4)) {
2282                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2283                 rtlefuse->epromtype = EEPROM_93C46;
2284         } else {
2285                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2286                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2287         }
2288         if (tmp_u1b & BIT(5)) {
2289                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2290                 rtlefuse->autoload_failflag = false;
2291                 _rtl8723be_read_adapter_info(hw, false);
2292         } else {
2293                 pr_err("Autoload ERR!!\n");
2294         }
2295         _rtl8723be_hal_customized_behavior(hw);
2296 }
2297
2298 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2299                                           u8 rate_index)
2300 {
2301         u8 ret = 0;
2302         switch (rate_index) {
2303         case RATR_INX_WIRELESS_NGB:
2304                 ret = 1;
2305                 break;
2306         case RATR_INX_WIRELESS_N:
2307         case RATR_INX_WIRELESS_NG:
2308                 ret = 5;
2309                 break;
2310         case RATR_INX_WIRELESS_NB:
2311                 ret = 3;
2312                 break;
2313         case RATR_INX_WIRELESS_GB:
2314                 ret = 6;
2315                 break;
2316         case RATR_INX_WIRELESS_G:
2317                 ret = 7;
2318                 break;
2319         case RATR_INX_WIRELESS_B:
2320                 ret = 8;
2321                 break;
2322         default:
2323                 ret = 0;
2324                 break;
2325         }
2326         return ret;
2327 }
2328
2329 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2330                                            struct ieee80211_sta *sta,
2331                                            u8 rssi_level)
2332 {
2333         struct rtl_priv *rtlpriv = rtl_priv(hw);
2334         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2335         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2336         struct rtl_sta_info *sta_entry = NULL;
2337         u32 ratr_bitmap;
2338         u8 ratr_index;
2339         u8 curtxbw_40mhz = (sta->ht_cap.cap &
2340                               IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2341         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2342                                 1 : 0;
2343         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2344                                 1 : 0;
2345         enum wireless_mode wirelessmode = 0;
2346         bool shortgi = false;
2347         u8 rate_mask[7];
2348         u8 macid = 0;
2349
2350         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2351         wirelessmode = sta_entry->wireless_mode;
2352         if (mac->opmode == NL80211_IFTYPE_STATION ||
2353             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2354                 curtxbw_40mhz = mac->bw_40;
2355         else if (mac->opmode == NL80211_IFTYPE_AP ||
2356                  mac->opmode == NL80211_IFTYPE_ADHOC)
2357                 macid = sta->aid + 1;
2358
2359         ratr_bitmap = sta->supp_rates[0];
2360
2361         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2362                 ratr_bitmap = 0xfff;
2363
2364         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2365                         sta->ht_cap.mcs.rx_mask[0] << 12);
2366         switch (wirelessmode) {
2367         case WIRELESS_MODE_B:
2368                 ratr_index = RATR_INX_WIRELESS_B;
2369                 if (ratr_bitmap & 0x0000000c)
2370                         ratr_bitmap &= 0x0000000d;
2371                 else
2372                         ratr_bitmap &= 0x0000000f;
2373                 break;
2374         case WIRELESS_MODE_G:
2375                 ratr_index = RATR_INX_WIRELESS_GB;
2376
2377                 if (rssi_level == 1)
2378                         ratr_bitmap &= 0x00000f00;
2379                 else if (rssi_level == 2)
2380                         ratr_bitmap &= 0x00000ff0;
2381                 else
2382                         ratr_bitmap &= 0x00000ff5;
2383                 break;
2384         case WIRELESS_MODE_N_24G:
2385         case WIRELESS_MODE_N_5G:
2386                 ratr_index = RATR_INX_WIRELESS_NGB;
2387                 if (rtlphy->rf_type == RF_1T1R) {
2388                         if (curtxbw_40mhz) {
2389                                 if (rssi_level == 1)
2390                                         ratr_bitmap &= 0x000f0000;
2391                                 else if (rssi_level == 2)
2392                                         ratr_bitmap &= 0x000ff000;
2393                                 else
2394                                         ratr_bitmap &= 0x000ff015;
2395                         } else {
2396                                 if (rssi_level == 1)
2397                                         ratr_bitmap &= 0x000f0000;
2398                                 else if (rssi_level == 2)
2399                                         ratr_bitmap &= 0x000ff000;
2400                                 else
2401                                         ratr_bitmap &= 0x000ff005;
2402                         }
2403                 } else {
2404                         if (curtxbw_40mhz) {
2405                                 if (rssi_level == 1)
2406                                         ratr_bitmap &= 0x0f8f0000;
2407                                 else if (rssi_level == 2)
2408                                         ratr_bitmap &= 0x0f8ff000;
2409                                 else
2410                                         ratr_bitmap &= 0x0f8ff015;
2411                         } else {
2412                                 if (rssi_level == 1)
2413                                         ratr_bitmap &= 0x0f8f0000;
2414                                 else if (rssi_level == 2)
2415                                         ratr_bitmap &= 0x0f8ff000;
2416                                 else
2417                                         ratr_bitmap &= 0x0f8ff005;
2418                         }
2419                 }
2420                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2421                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2422                         if (macid == 0)
2423                                 shortgi = true;
2424                         else if (macid == 1)
2425                                 shortgi = false;
2426                 }
2427                 break;
2428         default:
2429                 ratr_index = RATR_INX_WIRELESS_NGB;
2430
2431                 if (rtlphy->rf_type == RF_1T2R)
2432                         ratr_bitmap &= 0x000ff0ff;
2433                 else
2434                         ratr_bitmap &= 0x0f0ff0ff;
2435                 break;
2436         }
2437
2438         sta_entry->ratr_index = ratr_index;
2439
2440         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2441                  "ratr_bitmap :%x\n", ratr_bitmap);
2442         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2443                                        (ratr_index << 28);
2444         rate_mask[0] = macid;
2445         rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2446                                                       (shortgi ? 0x80 : 0x00);
2447         rate_mask[2] = curtxbw_40mhz;
2448
2449         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2450         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2451         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2452         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2453
2454         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2455                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2456                  ratr_index, ratr_bitmap,
2457                  rate_mask[0], rate_mask[1],
2458                  rate_mask[2], rate_mask[3],
2459                  rate_mask[4], rate_mask[5],
2460                  rate_mask[6]);
2461         rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2462         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2463 }
2464
2465 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2466                                    struct ieee80211_sta *sta,
2467                                    u8 rssi_level)
2468 {
2469         struct rtl_priv *rtlpriv = rtl_priv(hw);
2470         if (rtlpriv->dm.useramask)
2471                 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2472 }
2473
2474 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2475 {
2476         struct rtl_priv *rtlpriv = rtl_priv(hw);
2477         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2478         u16 sifs_timer;
2479
2480         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2481         if (!mac->ht_enable)
2482                 sifs_timer = 0x0a0a;
2483         else
2484                 sifs_timer = 0x0e0e;
2485         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2486 }
2487
2488 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2489 {
2490         struct rtl_priv *rtlpriv = rtl_priv(hw);
2491         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2492         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2493         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2494         u8 u1tmp;
2495         bool b_actuallyset = false;
2496
2497         if (rtlpriv->rtlhal.being_init_adapter)
2498                 return false;
2499
2500         if (ppsc->swrf_processing)
2501                 return false;
2502
2503         spin_lock(&rtlpriv->locks.rf_ps_lock);
2504         if (ppsc->rfchange_inprogress) {
2505                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2506                 return false;
2507         } else {
2508                 ppsc->rfchange_inprogress = true;
2509                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2510         }
2511
2512         cur_rfstate = ppsc->rfpwr_state;
2513
2514         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2515                        rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2516
2517         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2518
2519         if (rtlphy->polarity_ctl)
2520                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2521         else
2522                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2523
2524         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2525                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2526                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2527
2528                 e_rfpowerstate_toset = ERFON;
2529                 ppsc->hwradiooff = false;
2530                 b_actuallyset = true;
2531         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2532                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2533                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2534
2535                 e_rfpowerstate_toset = ERFOFF;
2536                 ppsc->hwradiooff = true;
2537                 b_actuallyset = true;
2538         }
2539
2540         if (b_actuallyset) {
2541                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2542                 ppsc->rfchange_inprogress = false;
2543                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2544         } else {
2545                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2546                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2547
2548                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2549                 ppsc->rfchange_inprogress = false;
2550                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2551         }
2552
2553         *valid = 1;
2554         return !ppsc->hwradiooff;
2555
2556 }
2557
2558 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2559                        u8 *p_macaddr, bool is_group, u8 enc_algo,
2560                        bool is_wepkey, bool clear_all)
2561 {
2562         struct rtl_priv *rtlpriv = rtl_priv(hw);
2563         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2564         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2565         u8 *macaddr = p_macaddr;
2566         u32 entry_id = 0;
2567         bool is_pairwise = false;
2568
2569         static u8 cam_const_addr[4][6] = {
2570                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2571                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2572                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2573                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2574         };
2575         static u8 cam_const_broad[] = {
2576                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2577         };
2578
2579         if (clear_all) {
2580                 u8 idx = 0;
2581                 u8 cam_offset = 0;
2582                 u8 clear_number = 5;
2583
2584                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2585
2586                 for (idx = 0; idx < clear_number; idx++) {
2587                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2588                         rtl_cam_empty_entry(hw, cam_offset + idx);
2589
2590                         if (idx < 5) {
2591                                 memset(rtlpriv->sec.key_buf[idx], 0,
2592                                        MAX_KEY_LEN);
2593                                 rtlpriv->sec.key_len[idx] = 0;
2594                         }
2595                 }
2596
2597         } else {
2598                 switch (enc_algo) {
2599                 case WEP40_ENCRYPTION:
2600                         enc_algo = CAM_WEP40;
2601                         break;
2602                 case WEP104_ENCRYPTION:
2603                         enc_algo = CAM_WEP104;
2604                         break;
2605                 case TKIP_ENCRYPTION:
2606                         enc_algo = CAM_TKIP;
2607                         break;
2608                 case AESCCMP_ENCRYPTION:
2609                         enc_algo = CAM_AES;
2610                         break;
2611                 default:
2612                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2613                                  "switch case %#x not processed\n", enc_algo);
2614                         enc_algo = CAM_TKIP;
2615                         break;
2616                 }
2617
2618                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2619                         macaddr = cam_const_addr[key_index];
2620                         entry_id = key_index;
2621                 } else {
2622                         if (is_group) {
2623                                 macaddr = cam_const_broad;
2624                                 entry_id = key_index;
2625                         } else {
2626                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2627                                         entry_id = rtl_cam_get_free_entry(hw,
2628                                                                 p_macaddr);
2629                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2630                                                 pr_err("Can not find free hw security cam entry\n");
2631                                                 return;
2632                                         }
2633                                 } else {
2634                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2635                                 }
2636
2637                                 key_index = PAIRWISE_KEYIDX;
2638                                 is_pairwise = true;
2639                         }
2640                 }
2641
2642                 if (rtlpriv->sec.key_len[key_index] == 0) {
2643                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2644                                  "delete one entry, entry_id is %d\n",
2645                                   entry_id);
2646                         if (mac->opmode == NL80211_IFTYPE_AP)
2647                                 rtl_cam_del_entry(hw, p_macaddr);
2648                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2649                 } else {
2650                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2651                                  "add one entry\n");
2652                         if (is_pairwise) {
2653                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2654                                          "set Pairwise key\n");
2655
2656                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2657                                                entry_id, enc_algo,
2658                                                CAM_CONFIG_NO_USEDK,
2659                                                rtlpriv->sec.key_buf[key_index]);
2660                         } else {
2661                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2662                                          "set group key\n");
2663
2664                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2665                                         rtl_cam_add_one_entry(hw,
2666                                                 rtlefuse->dev_addr,
2667                                                 PAIRWISE_KEYIDX,
2668                                                 CAM_PAIRWISE_KEY_POSITION,
2669                                                 enc_algo,
2670                                                 CAM_CONFIG_NO_USEDK,
2671                                                 rtlpriv->sec.key_buf
2672                                                 [entry_id]);
2673                                 }
2674
2675                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2676                                                 entry_id, enc_algo,
2677                                                 CAM_CONFIG_NO_USEDK,
2678                                                 rtlpriv->sec.key_buf[entry_id]);
2679                         }
2680                 }
2681         }
2682 }
2683
2684 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2685                                               bool auto_load_fail, u8 *hwinfo)
2686 {
2687         struct rtl_priv *rtlpriv = rtl_priv(hw);
2688         struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2689         u8 value;
2690         u32 tmpu_32;
2691
2692         if (!auto_load_fail) {
2693                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2694                 if (tmpu_32 & BIT(18))
2695                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2696                 else
2697                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2698                 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2699                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2700                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2701                 rtlpriv->btcoexist.btc_info.single_ant_path =
2702                          (value & 0x40 ? ANT_AUX : ANT_MAIN);   /*0xc3[6]*/
2703         } else {
2704                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2705                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2706                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2707                 rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN;
2708         }
2709
2710         /* override ant_num / ant_path */
2711         if (mod_params->ant_sel) {
2712                 rtlpriv->btcoexist.btc_info.ant_num =
2713                         (mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2);
2714
2715                 rtlpriv->btcoexist.btc_info.single_ant_path =
2716                         (mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN);
2717         }
2718 }
2719
2720 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2721 {
2722         struct rtl_priv *rtlpriv = rtl_priv(hw);
2723
2724         /* 0:Low, 1:High, 2:From Efuse. */
2725         rtlpriv->btcoexist.reg_bt_iso = 2;
2726         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2727         rtlpriv->btcoexist.reg_bt_sco = 3;
2728         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2729         rtlpriv->btcoexist.reg_bt_sco = 0;
2730 }
2731
2732 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2733 {
2734         struct rtl_priv *rtlpriv = rtl_priv(hw);
2735
2736         if (rtlpriv->cfg->ops->get_btc_status())
2737                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2738
2739 }
2740
2741 void rtl8723be_suspend(struct ieee80211_hw *hw)
2742 {
2743 }
2744
2745 void rtl8723be_resume(struct ieee80211_hw *hw)
2746 {
2747 }