drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61                                  skb->len, PCI_DMA_TODEVICE);
  62                 kfree_skb(skb);
  63                 ring->idx = (ring->idx + 1) % ring->entries;
  64         }
  65         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66 }
  67
  68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                         u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76
  77         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  78 }
  79
  80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  81 {
  82         struct rtl_priv *rtlpriv = rtl_priv(hw);
  83         u8 tmp1byte;
  84
  85         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  86         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 102         tmp1byte |= BIT(0);
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 104 }
 105
 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 107 {
 108         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 109 }
 110
 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                         (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         goto change_done;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         goto change_done;
 149                 }
 150         }
 151 change_done:
 152         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                         (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer)
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                         u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 247         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 260                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                 (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                 (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                 (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                 (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                 (u8 *)(&fw_current_inps));
 274         }
 275 }
 276
 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 278 {
 279         struct rtl_priv *rtlpriv = rtl_priv(hw);
 280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 282         bool fw_current_inps = true;
 283         u8 rpwm_val;
 284
 285         if (ppsc->low_power_enable) {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw,
 288                                 HW_VAR_FW_PSMODE_STATUS,
 289                                 (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_H2C_FW_PWRMODE,
 292                                 (u8 *)(&ppsc->fwctrl_psmode));
 293                 rtlhal->allow_sw_to_change_hwclc = true;
 294                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 295         } else {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw,
 298                                 HW_VAR_FW_PSMODE_STATUS,
 299                                 (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw,
 301                                 HW_VAR_H2C_FW_PWRMODE,
 302                                 (u8 *)(&ppsc->fwctrl_psmode));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_SET_RPWM,
 305                                 (u8 *)(&rpwm_val));
 306         }
 307 }
 308
 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 310                                           bool dl_whole_packets)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 314         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 315         u8 count = 0, dlbcn_count = 0;
 316         bool send_beacon = false;
 317
 318         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 319         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 320
 321         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 323
 324         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 325         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 326                        tmp_reg422 & (~BIT(6)));
 327         if (tmp_reg422 & BIT(6))
 328                 send_beacon = true;
 329
 330         do {
 331                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 332                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 333                                (bcnvalid_reg | BIT(0)));
 334                 _rtl8821ae_return_beacon_queue_skb(hw);
 335
 336                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 337                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 338                                                      dl_whole_packets);
 339                 else
 340                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 341                                                      dl_whole_packets);
 342
 343                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 344                 count = 0;
 345                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 346                         count++;
 347                         udelay(10);
 348                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 349                 }
 350                 dlbcn_count++;
 351         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 352
 353         if (!(bcnvalid_reg & BIT(0)))
 354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 355                          "Download RSVD page failed!\n");
 356         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 357                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 358                 _rtl8821ae_return_beacon_queue_skb(hw);
 359                 if (send_beacon) {
 360                         dlbcn_count = 0;
 361                         do {
 362                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 363                                                bcnvalid_reg | BIT(0));
 364
 365                                 _rtl8821ae_return_beacon_queue_skb(hw);
 366
 367                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 368                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 369                                                                      false);
 370                                 else
 371                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 372                                                                      false);
 373
 374                                 /* check rsvd page download OK. */
 375                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 376                                                              REG_TDECTRL + 2);
 377                                 count = 0;
 378                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 379                                         count++;
 380                                         udelay(10);
 381                                         bcnvalid_reg =
 382                                           rtl_read_byte(rtlpriv,
 383                                                         REG_TDECTRL + 2);
 384                                 }
 385                                 dlbcn_count++;
 386                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 387
 388                         if (!(bcnvalid_reg & BIT(0)))
 389                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 390                                          "2 Download RSVD page failed!\n");
 391                 }
 392         }
 393
 394         if (bcnvalid_reg & BIT(0))
 395                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 396
 397         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 399
 400         if (send_beacon)
 401                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 402
 403         if (!rtlhal->enter_pnp_sleep) {
 404                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406         }
 407 }
 408
 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 410 {
 411         struct rtl_priv *rtlpriv = rtl_priv(hw);
 412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415
 416         switch (variable) {
 417         case HW_VAR_ETHER_ADDR:
 418                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 419                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 420                 break;
 421         case HW_VAR_BSSID:
 422                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 423                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 424                 break;
 425         case HW_VAR_MEDIA_STATUS:
 426                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 427                 break;
 428         case HW_VAR_SLOT_TIME:
 429                 *((u8 *)(val)) = mac->slot_time;
 430                 break;
 431         case HW_VAR_BEACON_INTERVAL:
 432                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 433                 break;
 434         case HW_VAR_ATIM_WINDOW:
 435                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 436                 break;
 437         case HW_VAR_RCR:
 438                 *((u32 *)(val)) = rtlpci->receive_config;
 439                 break;
 440         case HW_VAR_RF_STATE:
 441                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 442                 break;
 443         case HW_VAR_FWLPS_RF_ON:{
 444                 enum rf_pwrstate rfstate;
 445                 u32 val_rcr;
 446
 447                 rtlpriv->cfg->ops->get_hw_reg(hw,
 448                                               HW_VAR_RF_STATE,
 449                                               (u8 *)(&rfstate));
 450                 if (rfstate == ERFOFF) {
 451                         *((bool *)(val)) = true;
 452                 } else {
 453                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 454                         val_rcr &= 0x00070000;
 455                         if (val_rcr)
 456                                 *((bool *)(val)) = false;
 457                         else
 458                                 *((bool *)(val)) = true;
 459                 }
 460                 break; }
 461         case HW_VAR_FW_PSMODE_STATUS:
 462                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 463                 break;
 464         case HW_VAR_CORRECT_TSF:{
 465                 u64 tsf;
 466                 u32 *ptsf_low = (u32 *)&tsf;
 467                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 468
 469                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 470                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 471
 472                 *((u64 *)(val)) = tsf;
 473
 474                 break; }
 475         case HAL_DEF_WOWLAN:
 476                 if (ppsc->wo_wlan_mode)
 477                         *((bool *)(val)) = true;
 478                 else
 479                         *((bool *)(val)) = false;
 480                 break;
 481         default:
 482                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 483                          "switch case %#x not processed\n", variable);
 484                 break;
 485         }
 486 }
 487
 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 494         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 495         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 496         u8 idx;
 497
 498         switch (variable) {
 499         case HW_VAR_ETHER_ADDR:{
 500                         for (idx = 0; idx < ETH_ALEN; idx++) {
 501                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 502                                                val[idx]);
 503                         }
 504                         break;
 505                 }
 506         case HW_VAR_BASIC_RATE:{
 507                         u16 b_rate_cfg = ((u16 *)val)[0];
 508                         b_rate_cfg = b_rate_cfg & 0x15f;
 509                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 510                         break;
 511                 }
 512         case HW_VAR_BSSID:{
 513                         for (idx = 0; idx < ETH_ALEN; idx++) {
 514                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 515                                                val[idx]);
 516                         }
 517                         break;
 518                 }
 519         case HW_VAR_SIFS:
 520                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 521                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 522
 523                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 524                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 525
 526                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 528                 break;
 529         case HW_VAR_R2T_SIFS:
 530                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 531                 break;
 532         case HW_VAR_SLOT_TIME:{
 533                 u8 e_aci;
 534
 535                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 536                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 537
 538                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 539
 540                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 541                         rtlpriv->cfg->ops->set_hw_reg(hw,
 542                                                       HW_VAR_AC_PARAM,
 543                                                       (u8 *)(&e_aci));
 544                 }
 545                 break; }
 546         case HW_VAR_ACK_PREAMBLE:{
 547                 u8 reg_tmp;
 548                 u8 short_preamble = (bool)(*(u8 *)val);
 549
 550                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 551                 if (short_preamble) {
 552                         reg_tmp |= BIT(1);
 553                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 554                                        reg_tmp);
 555                 } else {
 556                         reg_tmp &= (~BIT(1));
 557                         rtl_write_byte(rtlpriv,
 558                                 REG_TRXPTCL_CTL + 2,
 559                                 reg_tmp);
 560                 }
 561                 break; }
 562         case HW_VAR_WPA_CONFIG:
 563                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 564                 break;
 565         case HW_VAR_AMPDU_MIN_SPACE:{
 566                 u8 min_spacing_to_set;
 567                 u8 sec_min_space;
 568
 569                 min_spacing_to_set = *((u8 *)val);
 570                 if (min_spacing_to_set <= 7) {
 571                         sec_min_space = 0;
 572
 573                         if (min_spacing_to_set < sec_min_space)
 574                                 min_spacing_to_set = sec_min_space;
 575
 576                         mac->min_space_cfg = ((mac->min_space_cfg &
 577                                                0xf8) |
 578                                               min_spacing_to_set);
 579
 580                         *val = min_spacing_to_set;
 581
 582                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 583                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 584                                   mac->min_space_cfg);
 585
 586                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 587                                        mac->min_space_cfg);
 588                 }
 589                 break; }
 590         case HW_VAR_SHORTGI_DENSITY:{
 591                 u8 density_to_set;
 592
 593                 density_to_set = *((u8 *)val);
 594                 mac->min_space_cfg |= (density_to_set << 3);
 595
 596                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 597                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 598                           mac->min_space_cfg);
 599
 600                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 601                                mac->min_space_cfg);
 602
 603                 break; }
 604         case HW_VAR_AMPDU_FACTOR:{
 605                 u32     ampdu_len =  (*((u8 *)val));
 606
 607                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 608                         if (ampdu_len < VHT_AGG_SIZE_128K)
 609                                 ampdu_len =
 610                                         (0x2000 << (*((u8 *)val))) - 1;
 611                         else
 612                                 ampdu_len = 0x1ffff;
 613                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 614                         if (ampdu_len < HT_AGG_SIZE_64K)
 615                                 ampdu_len =
 616                                         (0x2000 << (*((u8 *)val))) - 1;
 617                         else
 618                                 ampdu_len = 0xffff;
 619                 }
 620                 ampdu_len |= BIT(31);
 621
 622                 rtl_write_dword(rtlpriv,
 623                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 624                 break; }
 625         case HW_VAR_AC_PARAM:{
 626                 u8 e_aci = *((u8 *)val);
 627
 628                 rtl8821ae_dm_init_edca_turbo(hw);
 629                 if (rtlpci->acm_method != EACMWAY2_SW)
 630                         rtlpriv->cfg->ops->set_hw_reg(hw,
 631                                                       HW_VAR_ACM_CTRL,
 632                                                       (u8 *)(&e_aci));
 633                 break; }
 634         case HW_VAR_ACM_CTRL:{
 635                 u8 e_aci = *((u8 *)val);
 636                 union aci_aifsn *p_aci_aifsn =
 637                     (union aci_aifsn *)(&mac->ac[0].aifs);
 638                 u8 acm = p_aci_aifsn->f.acm;
 639                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 640
 641                 acm_ctrl =
 642                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 643
 644                 if (acm) {
 645                         switch (e_aci) {
 646                         case AC0_BE:
 647                                 acm_ctrl |= ACMHW_BEQEN;
 648                                 break;
 649                         case AC2_VI:
 650                                 acm_ctrl |= ACMHW_VIQEN;
 651                                 break;
 652                         case AC3_VO:
 653                                 acm_ctrl |= ACMHW_VOQEN;
 654                                 break;
 655                         default:
 656                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 657                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 658                                          acm);
 659                                 break;
 660                         }
 661                 } else {
 662                         switch (e_aci) {
 663                         case AC0_BE:
 664                                 acm_ctrl &= (~ACMHW_BEQEN);
 665                                 break;
 666                         case AC2_VI:
 667                                 acm_ctrl &= (~ACMHW_VIQEN);
 668                                 break;
 669                         case AC3_VO:
 670                                 acm_ctrl &= (~ACMHW_VOQEN);
 671                                 break;
 672                         default:
 673                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 674                                          "switch case %#x not processed\n",
 675                                          e_aci);
 676                                 break;
 677                         }
 678                 }
 679
 680                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 681                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 682                          acm_ctrl);
 683                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 684                 break; }
 685         case HW_VAR_RCR:
 686                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 687                 rtlpci->receive_config = ((u32 *)(val))[0];
 688                 break;
 689         case HW_VAR_RETRY_LIMIT:{
 690                 u8 retry_limit = ((u8 *)(val))[0];
 691
 692                 rtl_write_word(rtlpriv, REG_RL,
 693                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 694                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 695                 break; }
 696         case HW_VAR_DUAL_TSF_RST:
 697                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 698                 break;
 699         case HW_VAR_EFUSE_BYTES:
 700                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 701                 break;
 702         case HW_VAR_EFUSE_USAGE:
 703                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 704                 break;
 705         case HW_VAR_IO_CMD:
 706                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 707                 break;
 708         case HW_VAR_SET_RPWM:{
 709                 u8 rpwm_val;
 710
 711                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 712                 udelay(1);
 713
 714                 if (rpwm_val & BIT(7)) {
 715                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 716                                        (*(u8 *)val));
 717                 } else {
 718                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 719                                        ((*(u8 *)val) | BIT(7)));
 720                 }
 721
 722                 break; }
 723         case HW_VAR_H2C_FW_PWRMODE:
 724                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 725                 break;
 726         case HW_VAR_FW_PSMODE_STATUS:
 727                 ppsc->fw_current_inpsmode = *((bool *)val);
 728                 break;
 729         case HW_VAR_INIT_RTS_RATE:
 730                 break;
 731         case HW_VAR_RESUME_CLK_ON:
 732                 _rtl8821ae_set_fw_ps_rf_on(hw);
 733                 break;
 734         case HW_VAR_FW_LPS_ACTION:{
 735                 bool b_enter_fwlps = *((bool *)val);
 736
 737                 if (b_enter_fwlps)
 738                         _rtl8821ae_fwlps_enter(hw);
 739                  else
 740                         _rtl8821ae_fwlps_leave(hw);
 741                  break; }
 742         case HW_VAR_H2C_FW_JOINBSSRPT:{
 743                 u8 mstatus = (*(u8 *)val);
 744
 745                 if (mstatus == RT_MEDIA_CONNECT) {
 746                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 747                                                       NULL);
 748                         _rtl8821ae_download_rsvd_page(hw, false);
 749                 }
 750                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 751
 752                 break; }
 753         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 754                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 755                 break;
 756         case HW_VAR_AID:{
 757                 u16 u2btmp;
 758                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 759                 u2btmp &= 0xC000;
 760                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 761                                mac->assoc_id));
 762                 break; }
 763         case HW_VAR_CORRECT_TSF:{
 764                 u8 btype_ibss = ((u8 *)(val))[0];
 765
 766                 if (btype_ibss)
 767                         _rtl8821ae_stop_tx_beacon(hw);
 768
 769                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 770
 771                 rtl_write_dword(rtlpriv, REG_TSFTR,
 772                                 (u32)(mac->tsf & 0xffffffff));
 773                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 774                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 775
 776                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 777
 778                 if (btype_ibss)
 779                         _rtl8821ae_resume_tx_beacon(hw);
 780                 break; }
 781         case HW_VAR_NAV_UPPER: {
 782                 u32     us_nav_upper = ((u32)*val);
 783
 784                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 785                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 786                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 787                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 788                         break;
 789                 }
 790                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 791                                ((u8)((us_nav_upper +
 792                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 793                                 HAL_92C_NAV_UPPER_UNIT)));
 794                 break; }
 795         case HW_VAR_KEEP_ALIVE: {
 796                 u8 array[2];
 797                 array[0] = 0xff;
 798                 array[1] = *((u8 *)val);
 799                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 800                                        array);
 801                 break; }
 802         default:
 803                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 804                          "switch case %#x not processed\n", variable);
 805                 break;
 806         }
 807 }
 808
 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         bool status = true;
 813         long count = 0;
 814         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 815                     _LLT_OP(_LLT_WRITE_ACCESS);
 816
 817         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 818
 819         do {
 820                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 821                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 822                         break;
 823
 824                 if (count > POLLING_LLT_THRESHOLD) {
 825                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 826                                  "Failed to polling write LLT done at address %d!\n",
 827                                  address);
 828                         status = false;
 829                         break;
 830                 }
 831         } while (++count);
 832
 833         return status;
 834 }
 835
 836 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 837 {
 838         struct rtl_priv *rtlpriv = rtl_priv(hw);
 839         unsigned short i;
 840         u8 txpktbuf_bndy;
 841         u32 rqpn;
 842         u8 maxpage;
 843         bool status;
 844
 845         maxpage = 255;
 846         txpktbuf_bndy = 0xF8;
 847         rqpn = 0x80e70808;
 848         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
 849                 txpktbuf_bndy = 0xFA;
 850                 rqpn = 0x80e90808;
 851         }
 852
 853         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 854         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 855
 856         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 857
 858         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 859         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 860
 861         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 862         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 863
 864         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 865                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 866                 if (!status)
 867                         return status;
 868         }
 869
 870         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 871         if (!status)
 872                 return status;
 873
 874         for (i = txpktbuf_bndy; i < maxpage; i++) {
 875                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 876                 if (!status)
 877                         return status;
 878         }
 879
 880         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 881         if (!status)
 882                 return status;
 883
 884         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 885
 886         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 887
 888         return true;
 889 }
 890
 891 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 892 {
 893         struct rtl_priv *rtlpriv = rtl_priv(hw);
 894         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 895         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 896         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 897         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 898
 899         if (rtlpriv->rtlhal.up_first_time)
 900                 return;
 901
 902         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 903                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 904                         rtl8812ae_sw_led_on(hw, pled0);
 905                 else
 906                         rtl8821ae_sw_led_on(hw, pled0);
 907         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 908                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 909                         rtl8812ae_sw_led_on(hw, pled0);
 910                 else
 911                         rtl8821ae_sw_led_on(hw, pled0);
 912         else
 913                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 914                         rtl8812ae_sw_led_off(hw, pled0);
 915                 else
 916                         rtl8821ae_sw_led_off(hw, pled0);
 917 }
 918
 919 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 920 {
 921         struct rtl_priv *rtlpriv = rtl_priv(hw);
 922         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 923         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 924
 925         u8 bytetmp = 0;
 926         u16 wordtmp = 0;
 927         bool mac_func_enable = rtlhal->mac_func_enable;
 928
 929         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 930
 931         /*Auto Power Down to CHIP-off State*/
 932         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 933         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 934
 935         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 936                 /* HW Power on sequence*/
 937                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 938                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 939                                               RTL8812_NIC_ENABLE_FLOW)) {
 940                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 941                                          "init 8812 MAC Fail as power on failure\n");
 942                                 return false;
 943                 }
 944         } else {
 945                 /* HW Power on sequence */
 946                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 947                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 948                                               RTL8821A_NIC_ENABLE_FLOW)){
 949                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 950                                 "init 8821 MAC Fail as power on failure\n");
 951                         return false;
 952                 }
 953         }
 954
 955         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 956         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 957
 958         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 959         bytetmp = 0xff;
 960         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 961         mdelay(2);
 962
 963         bytetmp = 0xff;
 964         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 965         mdelay(2);
 966
 967         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 968                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 969                 if (bytetmp & BIT(0)) {
 970                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 971                         bytetmp |= BIT(6);
 972                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 973                 }
 974         }
 975
 976         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 977         bytetmp &= ~BIT(4);
 978         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 979
 980         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 981
 982         if (!mac_func_enable) {
 983                 if (!_rtl8821ae_llt_table_init(hw))
 984                         return false;
 985         }
 986
 987         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 988         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 989
 990         /* Enable FW Beamformer Interrupt */
 991         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 992         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 993
 994         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 995         wordtmp &= 0xf;
 996         wordtmp |= 0xF5B1;
 997         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 998
 999         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
1000         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1001         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1002         /*low address*/
1003         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1004                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1005         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1006                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1007         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1008                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1009         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1010                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1011         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1012                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1013         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1014                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1015         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1016                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1017         rtl_write_dword(rtlpriv, REG_RX_DESA,
1018                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1019
1020         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1021
1022         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1023
1024         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1025
1026         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1027         _rtl8821ae_gen_refresh_led_state(hw);
1028
1029         return true;
1030 }
1031
1032 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1033 {
1034         struct rtl_priv *rtlpriv = rtl_priv(hw);
1035         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1036         u32 reg_rrsr;
1037
1038         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1039
1040         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1041         /* ARFB table 9 for 11ac 5G 2SS */
1042         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1043         /* ARFB table 10 for 11ac 5G 1SS */
1044         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1045         /* ARFB table 11 for 11ac 24G 1SS */
1046         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1047         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1048         /* ARFB table 12 for 11ac 24G 1SS */
1049         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1050         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1051         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1052         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1053         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1054
1055         /*Set retry limit*/
1056         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1057
1058         /* Set Data / Response auto rate fallack retry count*/
1059         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1060         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1061         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1062         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1063
1064         rtlpci->reg_bcn_ctrl_val = 0x1d;
1065         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1066
1067         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1068         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1069
1070         /* AGGR_BK_TIME Reg51A 0x16 */
1071         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1072
1073         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1074         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1075
1076         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1077         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1078         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1079 }
1080
1081 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1082 {
1083         u16 ret = 0;
1084         u8 tmp = 0, count = 0;
1085
1086         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1087         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1088         count = 0;
1089         while (tmp && count < 20) {
1090                 udelay(10);
1091                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1092                 count++;
1093         }
1094         if (0 == tmp)
1095                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1096
1097         return ret;
1098 }
1099
1100 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1101 {
1102         u8 tmp = 0, count = 0;
1103
1104         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1105         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1106         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1107         count = 0;
1108         while (tmp && count < 20) {
1109                 udelay(10);
1110                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1111                 count++;
1112         }
1113 }
1114
1115 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1116 {
1117         u16 read_addr = addr & 0xfffc;
1118         u8 tmp = 0, count = 0, ret = 0;
1119
1120         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1121         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1122         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123         count = 0;
1124         while (tmp && count < 20) {
1125                 udelay(10);
1126                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1127                 count++;
1128         }
1129         if (0 == tmp) {
1130                 read_addr = REG_DBI_RDATA + addr % 4;
1131                 ret = rtl_read_word(rtlpriv, read_addr);
1132         }
1133         return ret;
1134 }
1135
1136 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1137 {
1138         u8 tmp = 0, count = 0;
1139         u16 wrtie_addr, remainder = addr % 4;
1140
1141         wrtie_addr = REG_DBI_WDATA + remainder;
1142         rtl_write_byte(rtlpriv, wrtie_addr, data);
1143
1144         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1145         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1146
1147         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1148
1149         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1150         count = 0;
1151         while (tmp && count < 20) {
1152                 udelay(10);
1153                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1154                 count++;
1155         }
1156 }
1157
1158 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1159 {
1160         struct rtl_priv *rtlpriv = rtl_priv(hw);
1161         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1162         u8 tmp;
1163
1164         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1165                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1166                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1167
1168                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1169                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1170         }
1171
1172         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1173         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1174
1175         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1176         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1177
1178         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1179                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1180                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1181         }
1182 }
1183
1184 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1185 {
1186         struct rtl_priv *rtlpriv = rtl_priv(hw);
1187         u8 sec_reg_value;
1188         u8 tmp;
1189
1190         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1191                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1192                   rtlpriv->sec.pairwise_enc_algorithm,
1193                   rtlpriv->sec.group_enc_algorithm);
1194
1195         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1196                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1197                          "not open hw encryption\n");
1198                 return;
1199         }
1200
1201         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1202
1203         if (rtlpriv->sec.use_defaultkey) {
1204                 sec_reg_value |= SCR_TXUSEDK;
1205                 sec_reg_value |= SCR_RXUSEDK;
1206         }
1207
1208         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1209
1210         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1211         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1212
1213         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1214                  "The SECR-value %x\n", sec_reg_value);
1215
1216         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1217 }
1218
1219 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1220 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1221 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1223 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1224 /* ----------------------------------------------------------- */
1225
1226 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1227 {
1228         struct rtl_priv *rtlpriv = rtl_priv(hw);
1229         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1230                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1231                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1232
1233         rtlpriv->cfg->ops->set_hw_reg(hw,
1234                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1235
1236         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1237                  "Initialize MacId media status: from %d to %d\n",
1238                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1239                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1240 }
1241
1242 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1243 {
1244         struct rtl_priv *rtlpriv = rtl_priv(hw);
1245         u8 tmp;
1246
1247         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1248         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1249         if (!(tmp & BIT(2))) {
1250                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1251                 mdelay(100);
1252         }
1253
1254         /* read reg 0x350 Bit[25] if 1 : RX hang */
1255         /* read reg 0x350 Bit[24] if 1 : TX hang */
1256         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1257         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1258                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1259                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1260                 return true;
1261         } else {
1262                 return false;
1263         }
1264 }
1265
1266 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1267                                          bool mac_power_on,
1268                                          bool in_watchdog)
1269 {
1270         struct rtl_priv *rtlpriv = rtl_priv(hw);
1271         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1272         u8 tmp;
1273         bool release_mac_rx_pause;
1274         u8 backup_pcie_dma_pause;
1275
1276         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1277
1278         /* 1. Disable register write lock. 0x1c[1] = 0 */
1279         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1280         tmp &= ~(BIT(1));
1281         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1282         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1283                 /* write 0xCC bit[2] = 1'b1 */
1284                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1285                 tmp |= BIT(2);
1286                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1287         }
1288
1289         /* 2. Check and pause TRX DMA */
1290         /* write 0x284 bit[18] = 1'b1 */
1291         /* write 0x301 = 0xFF */
1292         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1293         if (tmp & BIT(2)) {
1294                 /* Already pause before the function for another purpose. */
1295                 release_mac_rx_pause = false;
1296         } else {
1297                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1298                 release_mac_rx_pause = true;
1299         }
1300         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1301         if (backup_pcie_dma_pause != 0xFF)
1302                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1303
1304         if (mac_power_on) {
1305                 /* 3. reset TRX function */
1306                 /* write 0x100 = 0x00 */
1307                 rtl_write_byte(rtlpriv, REG_CR, 0);
1308         }
1309
1310         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1311         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1312         tmp &= ~(BIT(0));
1313         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1314
1315         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1316         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1317         tmp |= BIT(0);
1318         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1319
1320         if (mac_power_on) {
1321                 /* 6. enable TRX function */
1322                 /* write 0x100 = 0xFF */
1323                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1324
1325                 /* We should init LLT & RQPN and
1326                  * prepare Tx/Rx descrptor address later
1327                  * because MAC function is reset.*/
1328         }
1329
1330         /* 7. Restore PCIe autoload down bit */
1331         /* 8812AE does not has the defination. */
1332         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1333                 /* write 0xF8 bit[17] = 1'b1 */
1334                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1335                 tmp |= BIT(1);
1336                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1337         }
1338
1339         /* In MAC power on state, BB and RF maybe in ON state,
1340          * if we release TRx DMA here.
1341          * it will cause packets to be started to Tx/Rx,
1342          * so we release Tx/Rx DMA later.*/
1343         if (!mac_power_on/* || in_watchdog*/) {
1344                 /* 8. release TRX DMA */
1345                 /* write 0x284 bit[18] = 1'b0 */
1346                 /* write 0x301 = 0x00 */
1347                 if (release_mac_rx_pause) {
1348                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1349                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1350                                        tmp & (~BIT(2)));
1351                 }
1352                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1353                                backup_pcie_dma_pause);
1354         }
1355
1356         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1357                 /* 9. lock system register */
1358                 /* write 0xCC bit[2] = 1'b0 */
1359                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1360                 tmp &= ~(BIT(2));
1361                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1362         }
1363         return true;
1364 }
1365
1366 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1367 {
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1370         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1371         u8 fw_reason = 0;
1372         struct timeval ts;
1373
1374         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1375
1376         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1377                  fw_reason);
1378
1379         ppsc->wakeup_reason = 0;
1380
1381         rtlhal->last_suspend_sec = ts.tv_sec;
1382
1383         switch (fw_reason) {
1384         case FW_WOW_V2_PTK_UPDATE_EVENT:
1385                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1386                 do_gettimeofday(&ts);
1387                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1388                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1389                          "It's a WOL PTK Key update event!\n");
1390                 break;
1391         case FW_WOW_V2_GTK_UPDATE_EVENT:
1392                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1393                 do_gettimeofday(&ts);
1394                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1395                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1396                          "It's a WOL GTK Key update event!\n");
1397                 break;
1398         case FW_WOW_V2_DISASSOC_EVENT:
1399                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1400                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1401                          "It's a disassociation event!\n");
1402                 break;
1403         case FW_WOW_V2_DEAUTH_EVENT:
1404                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1405                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1406                          "It's a deauth event!\n");
1407                 break;
1408         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1409                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1410                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1411                          "It's a Fw disconnect decision (AP lost) event!\n");
1412         break;
1413         case FW_WOW_V2_MAGIC_PKT_EVENT:
1414                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1415                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1416                          "It's a magic packet event!\n");
1417                 break;
1418         case FW_WOW_V2_UNICAST_PKT_EVENT:
1419                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1420                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1421                          "It's an unicast packet event!\n");
1422                 break;
1423         case FW_WOW_V2_PATTERN_PKT_EVENT:
1424                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1425                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1426                          "It's a pattern match event!\n");
1427                 break;
1428         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1429                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1430                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1431                          "It's an RTD3 Ssid match event!\n");
1432                 break;
1433         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1434                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1435                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1436                          "It's an RealWoW wake packet event!\n");
1437                 break;
1438         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1439                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1440                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1441                          "It's an RealWoW ack lost event!\n");
1442                 break;
1443         default:
1444                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1445                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1446                           fw_reason);
1447                 break;
1448         }
1449 }
1450
1451 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1452 {
1453         struct rtl_priv *rtlpriv = rtl_priv(hw);
1454         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1455
1456         /*low address*/
1457         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1458                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1459         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1460                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1461         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1462                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1463         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1464                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1465         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1466                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1467         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1468                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1469         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1470                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1471         rtl_write_dword(rtlpriv, REG_RX_DESA,
1472                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1473 }
1474
1475 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1476 {
1477         bool status = true;
1478         u32 i;
1479         u32 txpktbuf_bndy = boundary;
1480         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1481
1482         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1483                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1484                 if (!status)
1485                         return status;
1486         }
1487
1488         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1489         if (!status)
1490                 return status;
1491
1492         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1493                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1494                 if (!status)
1495                         return status;
1496         }
1497
1498         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1499                                       txpktbuf_bndy);
1500         if (!status)
1501                 return status;
1502
1503         return status;
1504 }
1505
1506 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1507                              u16 npq_rqpn_value, u32 rqpn_val)
1508 {
1509         struct rtl_priv *rtlpriv = rtl_priv(hw);
1510         u8 tmp;
1511         bool ret = true;
1512         u16 count = 0, tmp16;
1513         bool support_remote_wakeup;
1514
1515         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1516                                       (u8 *)(&support_remote_wakeup));
1517
1518         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1519                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1520                   boundary, npq_rqpn_value, rqpn_val);
1521
1522         /* stop PCIe DMA
1523          * 1. 0x301[7:0] = 0xFE */
1524         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1525
1526         /* wait TXFF empty
1527          * 2. polling till 0x41A[15:0]=0x07FF */
1528         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1529         while ((tmp16 & 0x07FF) != 0x07FF) {
1530                 udelay(100);
1531                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1532                 count++;
1533                 if ((count % 200) == 0) {
1534                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1535                                  "Tx queue is not empty for 20ms!\n");
1536                 }
1537                 if (count >= 1000) {
1538                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1539                                  "Wait for Tx FIFO empty timeout!\n");
1540                         break;
1541                 }
1542         }
1543
1544         /* TX pause
1545          * 3. reg 0x522=0xFF */
1546         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1547
1548         /* Wait TX State Machine OK
1549          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1550         count = 0;
1551         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1552                 udelay(100);
1553                 count++;
1554                 if (count >= 500) {
1555                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1556                                  "Wait for TX State Machine ready timeout !!\n");
1557                         break;
1558                 }
1559         }
1560
1561         /* stop RX DMA path
1562          * 5.   0x284[18] = 1
1563          * 6.   wait till 0x284[17] == 1
1564          * wait RX DMA idle */
1565         count = 0;
1566         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1567         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1568         do {
1569                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1570                 udelay(10);
1571                 count++;
1572         } while (!(tmp & BIT(1)) && count < 100);
1573
1574         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1575                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1576                   count, tmp);
1577
1578         /* reset BB
1579          * 7.   0x02 [0] = 0 */
1580         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1581         tmp &= ~(BIT(0));
1582         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1583
1584         /* Reset TRX MAC
1585          * 8.    0x100 = 0x00
1586          * Delay (1ms) */
1587         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1588         udelay(1000);
1589
1590         /* Disable MAC Security Engine
1591          * 9.   0x100 bit[9]=0 */
1592         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1593         tmp &= ~(BIT(1));
1594         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1595
1596         /* To avoid DD-Tim Circuit hang
1597          * 10.  0x553 bit[5]=1 */
1598         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1599         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1600
1601         /* Enable MAC Security Engine
1602          * 11.  0x100 bit[9]=1 */
1603         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1604         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1605
1606         /* Enable TRX MAC
1607          * 12.   0x100 = 0xFF
1608          *      Delay (1ms) */
1609         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1610         udelay(1000);
1611
1612         /* Enable BB
1613          * 13.  0x02 [0] = 1 */
1614         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1615         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1616
1617         /* beacon setting
1618          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1619         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1620         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1621         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1622
1623         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1624          * WMAC_LBK_BF_HD */
1625         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1626                        (u8)boundary);
1627
1628         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1629
1630         /* init LLT
1631          * 17. init LLT */
1632         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1633                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1634                          "Failed to init LLT table!\n");
1635                 return false;
1636         }
1637
1638         /* reallocate RQPN
1639          * 18. reallocate RQPN and init LLT */
1640         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1641         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1642
1643         /* release Tx pause
1644          * 19. 0x522=0x00 */
1645         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1646
1647         /* enable PCIE DMA
1648          * 20. 0x301[7:0] = 0x00
1649          * 21. 0x284[18] = 0 */
1650         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1651         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1652         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1653
1654         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1655         return ret;
1656 }
1657
1658 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1659 {
1660         struct rtl_priv *rtlpriv = rtl_priv(hw);
1661         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1662         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1663
1664 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1665         /* Re-download normal Fw. */
1666         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1667 #endif
1668
1669         /* Re-Initialize LLT table. */
1670         if (rtlhal->re_init_llt_table) {
1671                 u32 rqpn = 0x80e70808;
1672                 u8 rqpn_npq = 0, boundary = 0xF8;
1673                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1674                         rqpn = 0x80e90808;
1675                         boundary = 0xFA;
1676                 }
1677                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1678                         rtlhal->re_init_llt_table = false;
1679         }
1680
1681         ppsc->rfpwr_state = ERFON;
1682 }
1683
1684 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1685 {
1686         u8 tmp  = 0;
1687         struct rtl_priv *rtlpriv = rtl_priv(hw);
1688
1689         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1690
1691         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1692         if (!(tmp & (BIT(2) | BIT(3)))) {
1693                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1694                          "0x160(%#x)return!!\n", tmp);
1695                 return;
1696         }
1697
1698         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1699         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1700
1701         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1702         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1703
1704         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1705 }
1706
1707 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1708 {
1709         u8 tmp  = 0;
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711
1712         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1713
1714         /* Check 0x98[10] */
1715         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1716         if (!(tmp & BIT(2))) {
1717                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1718                          "<---0x99(%#x) return!!\n", tmp);
1719                 return;
1720         }
1721
1722         /* LTR idle latency, 0x90 for 144us */
1723         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1724
1725         /* LTR active latency, 0x3c for 60us */
1726         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1727
1728         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1729         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1730
1731         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1732         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1733         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1734
1735         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1736 }
1737
1738 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1739 {
1740         struct rtl_priv *rtlpriv = rtl_priv(hw);
1741         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1742         bool init_finished = true;
1743         u8 tmp = 0;
1744
1745         /* Get Fw wake up reason. */
1746         _rtl8821ae_get_wakeup_reason(hw);
1747
1748         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1749          * The root cause has not be found. */
1750         if (_rtl8821ae_check_pcie_dma_hang(hw))
1751                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1752
1753         /* Prepare Tx/Rx Desc Hw address. */
1754         _rtl8821ae_init_trx_desc_hw_address(hw);
1755
1756         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1757         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1758         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1759
1760         /* Check wake up event.
1761          * We should check wake packet bit before disable wowlan by H2C or
1762          * Fw will clear the bit. */
1763         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1764         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1765                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1766
1767         /* Set the WoWLAN related function control disable. */
1768         rtl8821ae_set_fw_wowlan_mode(hw, false);
1769         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1770
1771         if (rtlhal->hw_rof_enable) {
1772                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1773                 if (tmp & BIT(1)) {
1774                         /* Clear GPIO9 ISR */
1775                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1776                         init_finished = false;
1777                 } else {
1778                         init_finished = true;
1779                 }
1780         }
1781
1782         if (init_finished) {
1783                 _rtl8821ae_simple_initialize_adapter(hw);
1784
1785                 /* Release Pcie Interface Tx DMA. */
1786                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1787                 /* Release Pcie RX DMA */
1788                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1789
1790                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1791                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1792
1793                 _rtl8821ae_enable_l1off(hw);
1794                 _rtl8821ae_enable_ltr(hw);
1795         }
1796
1797         return init_finished;
1798 }
1799
1800 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1801 {
1802         /* BB OFDM RX Path_A */
1803         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1804         /* BB OFDM TX Path_A */
1805         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1806         /* BB CCK R/Rx Path_A */
1807         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1808         /* MCS support */
1809         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1810         /* RF Path_B HSSI OFF */
1811         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1812         /* RF Path_B Power Down */
1813         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1814         /* ADDA Path_B OFF */
1815         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1816         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1817 }
1818
1819 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1820 {
1821         struct rtl_priv *rtlpriv = rtl_priv(hw);
1822         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1823         u8 u1b_tmp;
1824
1825         rtlhal->mac_func_enable = false;
1826
1827         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1828                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1829                 /* 1. Run LPS WL RFOFF flow */
1830                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1831                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1832                 */
1833                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1834                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1835                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1836         }
1837         /* 2. 0x1F[7:0] = 0 */
1838         /* turn off RF */
1839         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1840         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1841                 rtlhal->fw_ready) {
1842                 rtl8821ae_firmware_selfreset(hw);
1843         }
1844
1845         /* Reset MCU. Suggested by Filen. */
1846         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1847         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1848
1849         /* g.   MCUFWDL 0x80[1:0]=0      */
1850         /* reset MCU ready status */
1851         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1852
1853         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1854                 /* HW card disable configuration. */
1855                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1856                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1857         } else {
1858                 /* HW card disable configuration. */
1859                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1860                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1861         }
1862
1863         /* Reset MCU IO Wrapper */
1864         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1865         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1866         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1867         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1868
1869         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1870         /* lock ISO/CLK/Power control register */
1871         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1872 }
1873
1874 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1875 {
1876         struct rtl_priv *rtlpriv = rtl_priv(hw);
1877         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1878         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1879         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1880         bool rtstatus = true;
1881         int err;
1882         u8 tmp_u1b;
1883         bool support_remote_wakeup;
1884         u32 nav_upper = WIFI_NAV_UPPER_US;
1885
1886         rtlhal->being_init_adapter = true;
1887         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1888                                       (u8 *)(&support_remote_wakeup));
1889         rtlpriv->intf_ops->disable_aspm(hw);
1890
1891         /*YP wowlan not considered*/
1892
1893         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1894         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1895                 rtlhal->mac_func_enable = true;
1896                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1897                          "MAC has already power on.\n");
1898         } else {
1899                 rtlhal->mac_func_enable = false;
1900                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1901         }
1902
1903         if (support_remote_wakeup &&
1904                 rtlhal->wake_from_pnp_sleep &&
1905                 rtlhal->mac_func_enable) {
1906                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1907                         rtlhal->being_init_adapter = false;
1908                         return 0;
1909                 }
1910         }
1911
1912         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1913                 _rtl8821ae_reset_pcie_interface_dma(hw,
1914                                                     rtlhal->mac_func_enable,
1915                                                     false);
1916                 rtlhal->mac_func_enable = false;
1917         }
1918
1919         /* Reset MAC/BB/RF status if it is not powered off
1920          * before calling initialize Hw flow to prevent
1921          * from interface and MAC status mismatch.
1922          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1923         if (rtlhal->mac_func_enable) {
1924                 _rtl8821ae_poweroff_adapter(hw);
1925                 rtlhal->mac_func_enable = false;
1926         }
1927
1928         rtstatus = _rtl8821ae_init_mac(hw);
1929         if (rtstatus != true) {
1930                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1931                 err = 1;
1932                 return err;
1933         }
1934
1935         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1936         tmp_u1b &= 0x7F;
1937         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1938
1939         err = rtl8821ae_download_fw(hw, false);
1940         if (err) {
1941                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1942                          "Failed to download FW. Init HW without FW now\n");
1943                 err = 1;
1944                 rtlhal->fw_ready = false;
1945                 return err;
1946         } else {
1947                 rtlhal->fw_ready = true;
1948         }
1949         ppsc->fw_current_inpsmode = false;
1950         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1951         rtlhal->fw_clk_change_in_progress = false;
1952         rtlhal->allow_sw_to_change_hwclc = false;
1953         rtlhal->last_hmeboxnum = 0;
1954
1955         /*SIC_Init(Adapter);
1956         if(rtlhal->AMPDUBurstMode)
1957                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1958
1959         rtl8821ae_phy_mac_config(hw);
1960         /* because last function modify RCR, so we update
1961          * rcr var here, or TP will unstable for receive_config
1962          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1963          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1964         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1965         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1966         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1967         rtl8821ae_phy_bb_config(hw);
1968
1969         rtl8821ae_phy_rf_config(hw);
1970
1971         if (rtlpriv->phy.rf_type == RF_1T1R &&
1972                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1973                 _rtl8812ae_bb8812_config_1t(hw);
1974
1975         _rtl8821ae_hw_configure(hw);
1976
1977         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1978
1979         /*set wireless mode*/
1980
1981         rtlhal->mac_func_enable = true;
1982
1983         rtl_cam_reset_all_entry(hw);
1984
1985         rtl8821ae_enable_hw_security_config(hw);
1986
1987         ppsc->rfpwr_state = ERFON;
1988
1989         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1990         _rtl8821ae_enable_aspm_back_door(hw);
1991         rtlpriv->intf_ops->enable_aspm(hw);
1992
1993         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1994             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1995                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1996
1997         rtl8821ae_bt_hw_init(hw);
1998         rtlpriv->rtlhal.being_init_adapter = false;
1999
2000         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2001
2002         /* rtl8821ae_dm_check_txpower_tracking(hw); */
2003         /* rtl8821ae_phy_lc_calibrate(hw); */
2004         if (support_remote_wakeup)
2005                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2006
2007         /* Release Rx DMA*/
2008         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2009         if (tmp_u1b & BIT(2)) {
2010                 /* Release Rx DMA if needed*/
2011                 tmp_u1b &= ~BIT(2);
2012                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2013         }
2014
2015         /* Release Tx/Rx PCIE DMA if*/
2016         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2017
2018         rtl8821ae_dm_init(hw);
2019         rtl8821ae_macid_initialize_mediastatus(hw);
2020
2021         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2022         return err;
2023 }
2024
2025 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2026 {
2027         struct rtl_priv *rtlpriv = rtl_priv(hw);
2028         struct rtl_phy *rtlphy = &rtlpriv->phy;
2029         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2030         enum version_8821ae version = VERSION_UNKNOWN;
2031         u32 value32;
2032
2033         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2034         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2035                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2036
2037         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2038                 rtlphy->rf_type = RF_2T2R;
2039         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2040                 rtlphy->rf_type = RF_1T1R;
2041
2042         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2043                  "RF_Type is %x!!\n", rtlphy->rf_type);
2044
2045         if (value32 & TRP_VAUX_EN) {
2046                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2047                         if (rtlphy->rf_type == RF_2T2R)
2048                                 version = VERSION_TEST_CHIP_2T2R_8812;
2049                         else
2050                                 version = VERSION_TEST_CHIP_1T1R_8812;
2051                 } else
2052                         version = VERSION_TEST_CHIP_8821;
2053         } else {
2054                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2055                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2056
2057                         if (rtlphy->rf_type == RF_2T2R)
2058                                 version =
2059                                         (enum version_8821ae)(CHIP_8812
2060                                         | NORMAL_CHIP |
2061                                         RF_TYPE_2T2R);
2062                         else
2063                                 version = (enum version_8821ae)(CHIP_8812
2064                                         | NORMAL_CHIP);
2065
2066                         version = (enum version_8821ae)(version | (rtl_id << 12));
2067                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2068                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2069
2070                         version = (enum version_8821ae)(CHIP_8821
2071                                 | NORMAL_CHIP | rtl_id);
2072                 }
2073         }
2074
2075         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2076                 /*WL_HWROF_EN.*/
2077                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2078                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2079         }
2080
2081         switch (version) {
2082         case VERSION_TEST_CHIP_1T1R_8812:
2083                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2084                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2085                 break;
2086         case VERSION_TEST_CHIP_2T2R_8812:
2087                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2088                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2089                 break;
2090         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2091                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2092                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2093                 break;
2094         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2095                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2096                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2097                 break;
2098         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2099                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2100                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2101                 break;
2102         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2103                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2104                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2105                 break;
2106         case VERSION_TEST_CHIP_8821:
2107                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2108                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2109                 break;
2110         case VERSION_NORMAL_TSMC_CHIP_8821:
2111                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2112                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2113                 break;
2114         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2115                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2116                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2117                 break;
2118         default:
2119                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2120                          "Chip Version ID: Unknow (0x%X)\n", version);
2121                 break;
2122         }
2123
2124         return version;
2125 }
2126
2127 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2128                                      enum nl80211_iftype type)
2129 {
2130         struct rtl_priv *rtlpriv = rtl_priv(hw);
2131         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2132         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2133         bt_msr &= 0xfc;
2134
2135         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2136         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2137                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2138
2139         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2140             type == NL80211_IFTYPE_STATION) {
2141                 _rtl8821ae_stop_tx_beacon(hw);
2142                 _rtl8821ae_enable_bcn_sub_func(hw);
2143         } else if (type == NL80211_IFTYPE_ADHOC ||
2144                 type == NL80211_IFTYPE_AP) {
2145                 _rtl8821ae_resume_tx_beacon(hw);
2146                 _rtl8821ae_disable_bcn_sub_func(hw);
2147         } else {
2148                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2149                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2150                          type);
2151         }
2152
2153         switch (type) {
2154         case NL80211_IFTYPE_UNSPECIFIED:
2155                 bt_msr |= MSR_NOLINK;
2156                 ledaction = LED_CTL_LINK;
2157                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2158                          "Set Network type to NO LINK!\n");
2159                 break;
2160         case NL80211_IFTYPE_ADHOC:
2161                 bt_msr |= MSR_ADHOC;
2162                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2163                          "Set Network type to Ad Hoc!\n");
2164                 break;
2165         case NL80211_IFTYPE_STATION:
2166                 bt_msr |= MSR_INFRA;
2167                 ledaction = LED_CTL_LINK;
2168                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2169                          "Set Network type to STA!\n");
2170                 break;
2171         case NL80211_IFTYPE_AP:
2172                 bt_msr |= MSR_AP;
2173                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2174                          "Set Network type to AP!\n");
2175                 break;
2176         default:
2177                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2178                          "Network type %d not support!\n", type);
2179                 return 1;
2180         }
2181
2182         rtl_write_byte(rtlpriv, MSR, bt_msr);
2183         rtlpriv->cfg->ops->led_control(hw, ledaction);
2184         if ((bt_msr & MSR_MASK) == MSR_AP)
2185                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2186         else
2187                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2188
2189         return 0;
2190 }
2191
2192 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2193 {
2194         struct rtl_priv *rtlpriv = rtl_priv(hw);
2195         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2196         u32 reg_rcr = rtlpci->receive_config;
2197
2198         if (rtlpriv->psc.rfpwr_state != ERFON)
2199                 return;
2200
2201         if (check_bssid) {
2202                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2203                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2204                                               (u8 *)(&reg_rcr));
2205                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2206         } else if (!check_bssid) {
2207                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2208                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2209                 rtlpriv->cfg->ops->set_hw_reg(hw,
2210                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2211         }
2212 }
2213
2214 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2215 {
2216         struct rtl_priv *rtlpriv = rtl_priv(hw);
2217
2218         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2219
2220         if (_rtl8821ae_set_media_status(hw, type))
2221                 return -EOPNOTSUPP;
2222
2223         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2224                 if (type != NL80211_IFTYPE_AP)
2225                         rtl8821ae_set_check_bssid(hw, true);
2226         } else {
2227                 rtl8821ae_set_check_bssid(hw, false);
2228         }
2229
2230         return 0;
2231 }
2232
2233 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2234 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2235 {
2236         struct rtl_priv *rtlpriv = rtl_priv(hw);
2237         rtl8821ae_dm_init_edca_turbo(hw);
2238         switch (aci) {
2239         case AC1_BK:
2240                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2241                 break;
2242         case AC0_BE:
2243                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2244                 break;
2245         case AC2_VI:
2246                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2247                 break;
2248         case AC3_VO:
2249                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2250                 break;
2251         default:
2252                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2253                 break;
2254         }
2255 }
2256
2257 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2258 {
2259         struct rtl_priv *rtlpriv = rtl_priv(hw);
2260         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2261
2262         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2263
2264         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2265         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2266
2267         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2268         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2269 }
2270
2271 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2272 {
2273         struct rtl_priv *rtlpriv = rtl_priv(hw);
2274         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2275
2276         if (rtlpci->int_clear)
2277                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2278
2279         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2280         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2281         rtlpci->irq_enabled = true;
2282         /* there are some C2H CMDs have been sent before
2283         system interrupt is enabled, e.g., C2H, CPWM.
2284         *So we need to clear all C2H events that FW has
2285         notified, otherwise FW won't schedule any commands anymore.
2286         */
2287         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2288         /*enable system interrupt*/
2289         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2290 }
2291
2292 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2293 {
2294         struct rtl_priv *rtlpriv = rtl_priv(hw);
2295         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2296
2297         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2298         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2299         rtlpci->irq_enabled = false;
2300         /*synchronize_irq(rtlpci->pdev->irq);*/
2301 }
2302
2303 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2304 {
2305         struct rtl_priv *rtlpriv = rtl_priv(hw);
2306         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2307         u16 cap_hdr;
2308         u8 cap_pointer;
2309         u8 cap_id = 0xff;
2310         u8 pmcs_reg;
2311         u8 cnt = 0;
2312
2313         /* Get the Capability pointer first,
2314          * the Capability Pointer is located at
2315          * offset 0x34 from the Function Header */
2316
2317         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2318         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2319                  "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2320
2321         do {
2322                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2323                 cap_id = cap_hdr & 0xFF;
2324
2325                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2326                          "in pci configuration, cap_pointer%x = %x\n",
2327                           cap_pointer, cap_id);
2328
2329                 if (cap_id == 0x01) {
2330                         break;
2331                 } else {
2332                         /* point to next Capability */
2333                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2334                         /* 0: end of pci capability, 0xff: invalid value */
2335                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2336                                 cap_id = 0xff;
2337                                 break;
2338                         }
2339                 }
2340         } while (cnt++ < 200);
2341
2342         if (cap_id == 0x01) {
2343                 /* Get the PM CSR (Control/Status Register),
2344                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2345                  */
2346                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2347
2348                 if (pmcs_reg & BIT(7)) {
2349                         /* PME event occured, clear the PM_Status by write 1 */
2350                         pmcs_reg = pmcs_reg | BIT(7);
2351
2352                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2353                                               pmcs_reg);
2354                         /* Read it back to check */
2355                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2356                                              &pmcs_reg);
2357                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2358                                  "Clear PME status 0x%2x to 0x%2x\n",
2359                                   cap_pointer + 5, pmcs_reg);
2360                 } else {
2361                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2362                                  "PME status(0x%2x) = 0x%2x\n",
2363                                   cap_pointer + 5, pmcs_reg);
2364                 }
2365         } else {
2366                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2367                          "Cannot find PME Capability\n");
2368         }
2369 }
2370
2371 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2372 {
2373         struct rtl_priv *rtlpriv = rtl_priv(hw);
2374         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2375         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2376         struct rtl_mac *mac = rtl_mac(rtlpriv);
2377         enum nl80211_iftype opmode;
2378         bool support_remote_wakeup;
2379         u8 tmp;
2380         u32 count = 0;
2381
2382         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2383                                       (u8 *)(&support_remote_wakeup));
2384
2385         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2386
2387         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2388             || !rtlhal->enter_pnp_sleep) {
2389                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2390                 mac->link_state = MAC80211_NOLINK;
2391                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2392                 _rtl8821ae_set_media_status(hw, opmode);
2393                 _rtl8821ae_poweroff_adapter(hw);
2394         } else {
2395                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2396                 /* 3 <1> Prepare for configuring wowlan related infomations */
2397                 /* Clear Fw WoWLAN event. */
2398                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2399
2400 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2401                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2402 #endif
2403                 /* Dynamically adjust Tx packet boundary
2404                  * for download reserved page packet.
2405                  * reserve 30 pages for rsvd page */
2406                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2407                         rtlhal->re_init_llt_table = true;
2408
2409                 /* 3 <2> Set Fw releted H2C cmd. */
2410
2411                 /* Set WoWLAN related security information. */
2412                 rtl8821ae_set_fw_global_info_cmd(hw);
2413
2414                 _rtl8821ae_download_rsvd_page(hw, true);
2415
2416                 /* Just enable AOAC related functions when we connect to AP. */
2417                 printk("mac->link_state = %d\n", mac->link_state);
2418                 if (mac->link_state >= MAC80211_LINKED &&
2419                     mac->opmode == NL80211_IFTYPE_STATION) {
2420                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2421                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2422                                                               RT_MEDIA_CONNECT);
2423
2424                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2425                         /* Enable Fw Keep alive mechanism. */
2426                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2427
2428                         /* Enable disconnect decision control. */
2429                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2430                 }
2431
2432                 /* 3 <3> Hw Configutations */
2433
2434                 /* Wait untill Rx DMA Finished before host sleep.
2435                  * FW Pause Rx DMA may happens when received packet doing dma.
2436                  */
2437                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2438
2439                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2440                 count = 0;
2441                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2442                         udelay(10);
2443                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2444                 }
2445                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2446                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2447                           count);
2448
2449                 /* reset trx ring */
2450                 rtlpriv->intf_ops->reset_trx_ring(hw);
2451
2452                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2453
2454                 _rtl8821ae_clear_pci_pme_status(hw);
2455                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2456                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2457                 /* prevent 8051 to be reset by PERST */
2458                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2459                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2460         }
2461
2462         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2463             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2464                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2465         /* For wowlan+LPS+32k. */
2466         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2467                 /* Set the WoWLAN related function control enable.
2468                  * It should be the last H2C cmd in the WoWLAN flow. */
2469                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2470
2471                 /* Stop Pcie Interface Tx DMA. */
2472                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2473                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2474
2475                 /* Wait for TxDMA idle. */
2476                 count = 0;
2477                 do {
2478                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2479                         udelay(10);
2480                         count++;
2481                 } while ((tmp != 0) && (count < 100));
2482                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2483                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2484                           count);
2485
2486                 if (rtlhal->hw_rof_enable) {
2487                         printk("hw_rof_enable\n");
2488                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2489                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2490                 }
2491         }
2492         /* after power off we should do iqk again */
2493         rtlpriv->phy.iqk_initialized = false;
2494 }
2495
2496 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2497                                   u32 *p_inta, u32 *p_intb)
2498 {
2499         struct rtl_priv *rtlpriv = rtl_priv(hw);
2500         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2501
2502         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2503         rtl_write_dword(rtlpriv, ISR, *p_inta);
2504
2505         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2506         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2507 }
2508
2509 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2510 {
2511         struct rtl_priv *rtlpriv = rtl_priv(hw);
2512         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2513         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2514         u16 bcn_interval, atim_window;
2515
2516         bcn_interval = mac->beacon_interval;
2517         atim_window = 2;        /*FIX MERGE */
2518         rtl8821ae_disable_interrupt(hw);
2519         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2520         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2521         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2522         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2523         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2524         rtl_write_byte(rtlpriv, 0x606, 0x30);
2525         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2526         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2527         rtl8821ae_enable_interrupt(hw);
2528 }
2529
2530 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2531 {
2532         struct rtl_priv *rtlpriv = rtl_priv(hw);
2533         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2534         u16 bcn_interval = mac->beacon_interval;
2535
2536         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2537                  "beacon_interval:%d\n", bcn_interval);
2538         rtl8821ae_disable_interrupt(hw);
2539         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2540         rtl8821ae_enable_interrupt(hw);
2541 }
2542
2543 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2544                                    u32 add_msr, u32 rm_msr)
2545 {
2546         struct rtl_priv *rtlpriv = rtl_priv(hw);
2547         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2548
2549         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2550                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2551
2552         if (add_msr)
2553                 rtlpci->irq_mask[0] |= add_msr;
2554         if (rm_msr)
2555                 rtlpci->irq_mask[0] &= (~rm_msr);
2556         rtl8821ae_disable_interrupt(hw);
2557         rtl8821ae_enable_interrupt(hw);
2558 }
2559
2560 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2561 {
2562         u8 group = 0;
2563
2564         if (chnl <= 14) {
2565                 if (1 <= chnl && chnl <= 2)
2566                         group = 0;
2567         else if (3 <= chnl && chnl <= 5)
2568                         group = 1;
2569         else if (6 <= chnl && chnl <= 8)
2570                         group = 2;
2571         else if (9 <= chnl && chnl <= 11)
2572                         group = 3;
2573         else /*if (12 <= chnl && chnl <= 14)*/
2574                         group = 4;
2575         } else {
2576                 if (36 <= chnl && chnl <= 42)
2577                         group = 0;
2578         else if (44 <= chnl && chnl <= 48)
2579                         group = 1;
2580         else if (50 <= chnl && chnl <= 58)
2581                         group = 2;
2582         else if (60 <= chnl && chnl <= 64)
2583                         group = 3;
2584         else if (100 <= chnl && chnl <= 106)
2585                         group = 4;
2586         else if (108 <= chnl && chnl <= 114)
2587                         group = 5;
2588         else if (116 <= chnl && chnl <= 122)
2589                         group = 6;
2590         else if (124 <= chnl && chnl <= 130)
2591                         group = 7;
2592         else if (132 <= chnl && chnl <= 138)
2593                         group = 8;
2594         else if (140 <= chnl && chnl <= 144)
2595                         group = 9;
2596         else if (149 <= chnl && chnl <= 155)
2597                         group = 10;
2598         else if (157 <= chnl && chnl <= 161)
2599                         group = 11;
2600         else if (165 <= chnl && chnl <= 171)
2601                         group = 12;
2602         else if (173 <= chnl && chnl <= 177)
2603                         group = 13;
2604                 else
2605                         /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2606                                 "5G, Channel %d in Group not found\n",chnl);*/
2607                         RT_ASSERT(!COMP_EFUSE,
2608                                 "5G, Channel %d in Group not found\n", chnl);
2609         }
2610         return group;
2611 }
2612
2613 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2614         struct txpower_info_2g *pwrinfo24g,
2615         struct txpower_info_5g *pwrinfo5g,
2616         bool autoload_fail,
2617         u8 *hwinfo)
2618 {
2619         struct rtl_priv *rtlpriv = rtl_priv(hw);
2620         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2621
2622         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2623                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2624                  (eeAddr+1), hwinfo[eeAddr+1]);
2625         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2626                 autoload_fail = true;
2627
2628         if (autoload_fail) {
2629                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2630                          "auto load fail : Use Default value!\n");
2631                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2632                         /*2.4G default value*/
2633                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2634                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2635                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2636                         }
2637                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2638                                 if (TxCount == 0) {
2639                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2640                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2641                                 } else {
2642                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2643                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2644                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2645                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2646                                 }
2647                         }
2648                         /*5G default value*/
2649                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2650                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2651
2652                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2653                                 if (TxCount == 0) {
2654                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2655                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2656                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2657                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2658                                 } else {
2659                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2660                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2661                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2662                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2663                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2664                                 }
2665                         }
2666                 }
2667                 return;
2668         }
2669
2670         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2671
2672         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2673                 /*2.4G default value*/
2674                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2675                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2676                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2677                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2678                 }
2679                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2680                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2681                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2682                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2683                 }
2684                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2685                         if (TxCount == 0) {
2686                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2687                                 /*bit sign number to 8 bit sign number*/
2688                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2689                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2690                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2691                                 /*bit sign number to 8 bit sign number*/
2692                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2693                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2694                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2695
2696                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2697                                 eeAddr++;
2698                         } else {
2699                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2700                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2701                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2702
2703                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2704                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2705                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2706
2707                                 eeAddr++;
2708
2709                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2710                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2711                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2712
2713                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2714                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2715                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2716
2717                                 eeAddr++;
2718                         }
2719                 }
2720
2721                 /*5G default value*/
2722                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2723                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2724                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2725                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2726                 }
2727
2728                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2729                         if (TxCount == 0) {
2730                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2731
2732                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2733                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2734                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2735
2736                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2737                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2738                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2739
2740                                 eeAddr++;
2741                         } else {
2742                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2743                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2744                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2745
2746                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2747                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2748                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2749
2750                                 eeAddr++;
2751                         }
2752                 }
2753
2754                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2755                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2756
2757                 eeAddr++;
2758
2759                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2760
2761                 eeAddr++;
2762
2763                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2764                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2765                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2766                 }
2767                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2768                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2769                         /* 4bit sign number to 8 bit sign number */
2770                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2771                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2772                         /* 4bit sign number to 8 bit sign number */
2773                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2774                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2775                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2776
2777                         eeAddr++;
2778                 }
2779         }
2780 }
2781 #if 0
2782 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2783                                                  bool autoload_fail,
2784                                                  u8 *hwinfo)
2785 {
2786         struct rtl_priv *rtlpriv = rtl_priv(hw);
2787         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2788         struct txpower_info_2g pwrinfo24g;
2789         struct txpower_info_5g pwrinfo5g;
2790         u8 rf_path, index;
2791         u8 i;
2792
2793         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2794                                         &pwrinfo5g, autoload_fail, hwinfo);
2795
2796         for (rf_path = 0; rf_path < 2; rf_path++) {
2797                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2798                         index = _rtl8821ae_get_chnl_group(i + 1);
2799
2800                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2801                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2802                                         pwrinfo24g.index_cck_base[rf_path][5];
2803                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2804                                         pwrinfo24g.index_bw40_base[rf_path][index];
2805                         } else {
2806                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2807                                         pwrinfo24g.index_cck_base[rf_path][index];
2808                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2809                                         pwrinfo24g.index_bw40_base[rf_path][index];
2810                         }
2811                 }
2812
2813                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2814                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2815                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2816                                         pwrinfo5g.index_bw40_base[rf_path][index];
2817                 }
2818                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2819                         u8 upper, lower;
2820                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2821                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2822                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2823
2824                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2825                 }
2826                 for (i = 0; i < MAX_TX_COUNT; i++) {
2827                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2828                                 pwrinfo24g.cck_diff[rf_path][i];
2829                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2830                                 pwrinfo24g.ofdm_diff[rf_path][i];
2831                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2832                                 pwrinfo24g.bw20_diff[rf_path][i];
2833                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2834                                 pwrinfo24g.bw40_diff[rf_path][i];
2835
2836                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2837                                 pwrinfo5g.ofdm_diff[rf_path][i];
2838                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2839                                 pwrinfo5g.bw20_diff[rf_path][i];
2840                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2841                                 pwrinfo5g.bw40_diff[rf_path][i];
2842                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2843                                 pwrinfo5g.bw80_diff[rf_path][i];
2844                 }
2845         }
2846
2847         if (!autoload_fail) {
2848                 rtlefuse->eeprom_regulatory =
2849                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2850                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2851                         rtlefuse->eeprom_regulatory = 0;
2852         } else {
2853                 rtlefuse->eeprom_regulatory = 0;
2854         }
2855
2856         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2857         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2858 }
2859 #endif
2860 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2861                                                  bool autoload_fail,
2862                                                  u8 *hwinfo)
2863 {
2864         struct rtl_priv *rtlpriv = rtl_priv(hw);
2865         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2866         struct txpower_info_2g pwrinfo24g;
2867         struct txpower_info_5g pwrinfo5g;
2868         u8 rf_path, index;
2869         u8 i;
2870
2871         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2872                 &pwrinfo5g, autoload_fail, hwinfo);
2873
2874         for (rf_path = 0; rf_path < 2; rf_path++) {
2875                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2876                         index = _rtl8821ae_get_chnl_group(i + 1);
2877
2878                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2879                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2880                                         pwrinfo24g.index_cck_base[rf_path][5];
2881                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2882                                         pwrinfo24g.index_bw40_base[rf_path][index];
2883                         } else {
2884                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2885                                         pwrinfo24g.index_cck_base[rf_path][index];
2886                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2887                                         pwrinfo24g.index_bw40_base[rf_path][index];
2888                         }
2889                 }
2890
2891                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2892                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2893                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2894                                 pwrinfo5g.index_bw40_base[rf_path][index];
2895                 }
2896                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2897                         u8 upper, lower;
2898                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2899                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2900                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2901
2902                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2903                 }
2904                 for (i = 0; i < MAX_TX_COUNT; i++) {
2905                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2906                                 pwrinfo24g.cck_diff[rf_path][i];
2907                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2908                                 pwrinfo24g.ofdm_diff[rf_path][i];
2909                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2910                                 pwrinfo24g.bw20_diff[rf_path][i];
2911                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2912                                 pwrinfo24g.bw40_diff[rf_path][i];
2913
2914                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2915                                 pwrinfo5g.ofdm_diff[rf_path][i];
2916                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2917                                 pwrinfo5g.bw20_diff[rf_path][i];
2918                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2919                                 pwrinfo5g.bw40_diff[rf_path][i];
2920                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2921                                 pwrinfo5g.bw80_diff[rf_path][i];
2922                 }
2923         }
2924         /*bit0~2*/
2925         if (!autoload_fail) {
2926                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2927                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2928                         rtlefuse->eeprom_regulatory = 0;
2929         } else {
2930                 rtlefuse->eeprom_regulatory = 0;
2931         }
2932
2933         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2934         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2935 }
2936
2937 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2938                                     bool autoload_fail)
2939 {
2940         struct rtl_priv *rtlpriv = rtl_priv(hw);
2941         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2942
2943         if (!autoload_fail) {
2944                 rtlhal->pa_type_2g = hwinfo[0xBC];
2945                 rtlhal->lna_type_2g = hwinfo[0xBD];
2946                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2947                         rtlhal->pa_type_2g = 0;
2948                         rtlhal->lna_type_2g = 0;
2949                 }
2950                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2951                                           (rtlhal->pa_type_2g & BIT(4))) ?
2952                                          1 : 0;
2953                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2954                                            (rtlhal->lna_type_2g & BIT(3))) ?
2955                                           1 : 0;
2956
2957                 rtlhal->pa_type_5g = hwinfo[0xBC];
2958                 rtlhal->lna_type_5g = hwinfo[0xBF];
2959                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2960                         rtlhal->pa_type_5g = 0;
2961                         rtlhal->lna_type_5g = 0;
2962                 }
2963                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2964                                           (rtlhal->pa_type_5g & BIT(0))) ?
2965                                          1 : 0;
2966                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2967                                            (rtlhal->lna_type_5g & BIT(3))) ?
2968                                           1 : 0;
2969         } else {
2970                 rtlhal->external_pa_2g  = 0;
2971                 rtlhal->external_lna_2g = 0;
2972                 rtlhal->external_pa_5g  = 0;
2973                 rtlhal->external_lna_5g = 0;
2974         }
2975 }
2976
2977 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2978                                     bool autoload_fail)
2979 {
2980         struct rtl_priv *rtlpriv = rtl_priv(hw);
2981         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2982
2983         if (!autoload_fail) {
2984                 rtlhal->pa_type_2g = hwinfo[0xBC];
2985                 rtlhal->lna_type_2g = hwinfo[0xBD];
2986                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2987                         rtlhal->pa_type_2g = 0;
2988                         rtlhal->lna_type_2g = 0;
2989                 }
2990                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2991                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2992
2993                 rtlhal->pa_type_5g = hwinfo[0xBC];
2994                 rtlhal->lna_type_5g = hwinfo[0xBF];
2995                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2996                         rtlhal->pa_type_5g = 0;
2997                         rtlhal->lna_type_5g = 0;
2998                 }
2999                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3000                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3001         } else {
3002                 rtlhal->external_pa_2g  = 0;
3003                 rtlhal->external_lna_2g = 0;
3004                 rtlhal->external_pa_5g  = 0;
3005                 rtlhal->external_lna_5g = 0;
3006         }
3007 }
3008
3009 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3010                               bool autoload_fail)
3011 {
3012         struct rtl_priv *rtlpriv = rtl_priv(hw);
3013         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3014
3015         if (!autoload_fail) {
3016                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3017                         if (rtlhal->external_lna_5g) {
3018                                 if (rtlhal->external_pa_5g) {
3019                                         if (rtlhal->external_lna_2g &&
3020                                             rtlhal->external_pa_2g)
3021                                                 rtlhal->rfe_type = 3;
3022                                         else
3023                                                 rtlhal->rfe_type = 0;
3024                                 } else {
3025                                         rtlhal->rfe_type = 2;
3026                                 }
3027                         } else {
3028                                 rtlhal->rfe_type = 4;
3029                         }
3030                 } else {
3031                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3032
3033                         if (rtlhal->rfe_type == 4 &&
3034                             (rtlhal->external_pa_5g ||
3035                              rtlhal->external_pa_2g ||
3036                              rtlhal->external_lna_5g ||
3037                              rtlhal->external_lna_2g)) {
3038                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3039                                         rtlhal->rfe_type = 2;
3040                         }
3041                 }
3042         } else {
3043                 rtlhal->rfe_type = 0x04;
3044         }
3045
3046         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3047                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3048 }
3049
3050 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3051                                               bool auto_load_fail, u8 *hwinfo)
3052 {
3053         struct rtl_priv *rtlpriv = rtl_priv(hw);
3054         u8 value;
3055
3056         if (!auto_load_fail) {
3057                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3058                 if (((value & 0xe0) >> 5) == 0x1)
3059                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3060                 else
3061                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3062                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3063
3064                 value = hwinfo[EEPROM_RF_BT_SETTING];
3065                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3066         } else {
3067                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3068                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3069                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3070         }
3071         /*move BT_InitHalVars() to init_sw_vars*/
3072 }
3073
3074 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3075                                               bool auto_load_fail, u8 *hwinfo)
3076 {
3077         struct rtl_priv *rtlpriv = rtl_priv(hw);
3078         u8 value;
3079         u32 tmpu_32;
3080
3081         if (!auto_load_fail) {
3082                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3083                 if (tmpu_32 & BIT(18))
3084                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3085                 else
3086                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3087                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3088
3089                 value = hwinfo[EEPROM_RF_BT_SETTING];
3090                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3091         } else {
3092                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3093                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3094                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3095         }
3096         /*move BT_InitHalVars() to init_sw_vars*/
3097 }
3098
3099 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3100 {
3101         struct rtl_priv *rtlpriv = rtl_priv(hw);
3102         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3103         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3104         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3105         int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3106                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3107                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3108                         COUNTRY_CODE_WORLD_WIDE_13};
3109         u8 *hwinfo;
3110
3111         if (b_pseudo_test) {
3112                 ;/* need add */
3113         }
3114
3115         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3116         if (!hwinfo)
3117                 return;
3118
3119         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3120                 goto exit;
3121
3122         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3123                                                hwinfo);
3124
3125         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3126                 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3127                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3128                                 rtlefuse->autoload_failflag, hwinfo);
3129         } else {
3130                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3131                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3132                                 rtlefuse->autoload_failflag, hwinfo);
3133         }
3134
3135         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3136         /*board type*/
3137         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3138         if (rtlhal->external_lna_2g != 0)
3139                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3140         if (rtlhal->external_lna_5g != 0)
3141                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3142         if (rtlhal->external_pa_2g != 0)
3143                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3144         if (rtlhal->external_pa_5g != 0)
3145                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3146
3147         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3148                 rtlefuse->board_type |= ODM_BOARD_BT;
3149
3150         rtlhal->board_type = rtlefuse->board_type;
3151         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3152                  "board_type = 0x%x\n", rtlefuse->board_type);
3153
3154         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3155         if (rtlefuse->eeprom_channelplan == 0xff)
3156                 rtlefuse->eeprom_channelplan = 0x7F;
3157
3158         /* set channel plan from efuse */
3159         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3160
3161         /*parse xtal*/
3162         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3163         if (rtlefuse->crystalcap == 0xFF)
3164                 rtlefuse->crystalcap = 0x20;
3165
3166         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3167         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3168             rtlefuse->autoload_failflag) {
3169                 rtlefuse->apk_thermalmeterignore = true;
3170                 rtlefuse->eeprom_thermalmeter = 0xff;
3171         }
3172
3173         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3174         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3175                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3176
3177         if (!rtlefuse->autoload_failflag) {
3178                 rtlefuse->antenna_div_cfg =
3179                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3180                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3181                         rtlefuse->antenna_div_cfg = 0;
3182
3183                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3184                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3185                         rtlefuse->antenna_div_cfg = 0;
3186
3187                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3188                 if (rtlefuse->antenna_div_type == 0xff)
3189                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3190         } else {
3191                 rtlefuse->antenna_div_cfg = 0;
3192                 rtlefuse->antenna_div_type = 0;
3193         }
3194
3195         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3196                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3197                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3198
3199         pcipriv->ledctl.led_opendrain = true;
3200
3201         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3202                 switch (rtlefuse->eeprom_oemid) {
3203                 case RT_CID_DEFAULT:
3204                         break;
3205                 case EEPROM_CID_TOSHIBA:
3206                         rtlhal->oem_id = RT_CID_TOSHIBA;
3207                         break;
3208                 case EEPROM_CID_CCX:
3209                         rtlhal->oem_id = RT_CID_CCX;
3210                         break;
3211                 case EEPROM_CID_QMI:
3212                         rtlhal->oem_id = RT_CID_819X_QMI;
3213                         break;
3214                 case EEPROM_CID_WHQL:
3215                         break;
3216                 default:
3217                         break;
3218                 }
3219         }
3220 exit:
3221         kfree(hwinfo);
3222 }
3223
3224 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3225 {
3226         struct rtl_priv *rtlpriv = rtl_priv(hw);
3227         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3228         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3229
3230         pcipriv->ledctl.led_opendrain = true;
3231         switch (rtlhal->oem_id) {
3232         case RT_CID_819X_HP:
3233                 pcipriv->ledctl.led_opendrain = true;
3234                 break;
3235         case RT_CID_819X_LENOVO:
3236         case RT_CID_DEFAULT:
3237         case RT_CID_TOSHIBA:
3238         case RT_CID_CCX:
3239         case RT_CID_819X_ACER:
3240         case RT_CID_WHQL:
3241         default:
3242                 break;
3243         }
3244         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3245                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3246 }*/
3247
3248 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3249 {
3250         struct rtl_priv *rtlpriv = rtl_priv(hw);
3251         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3252         struct rtl_phy *rtlphy = &rtlpriv->phy;
3253         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3254         u8 tmp_u1b;
3255
3256         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3257         if (get_rf_type(rtlphy) == RF_1T1R)
3258                 rtlpriv->dm.rfpath_rxenable[0] = true;
3259         else
3260                 rtlpriv->dm.rfpath_rxenable[0] =
3261                     rtlpriv->dm.rfpath_rxenable[1] = true;
3262         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3263                                                 rtlhal->version);
3264
3265         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3266         if (tmp_u1b & BIT(4)) {
3267                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3268                 rtlefuse->epromtype = EEPROM_93C46;
3269         } else {
3270                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3271                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3272         }
3273
3274         if (tmp_u1b & BIT(5)) {
3275                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3276                 rtlefuse->autoload_failflag = false;
3277                 _rtl8821ae_read_adapter_info(hw, false);
3278         } else {
3279                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3280         }
3281         /*hal_ReadRFType_8812A()*/
3282         /* _rtl8821ae_hal_customized_behavior(hw); */
3283 }
3284
3285 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3286                 struct ieee80211_sta *sta)
3287 {
3288         struct rtl_priv *rtlpriv = rtl_priv(hw);
3289         struct rtl_phy *rtlphy = &rtlpriv->phy;
3290         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3291         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3292         u32 ratr_value;
3293         u8 ratr_index = 0;
3294         u8 b_nmode = mac->ht_enable;
3295         u8 mimo_ps = IEEE80211_SMPS_OFF;
3296         u16 shortgi_rate;
3297         u32 tmp_ratr_value;
3298         u8 curtxbw_40mhz = mac->bw_40;
3299         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3300                                 1 : 0;
3301         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3302                                 1 : 0;
3303         enum wireless_mode wirelessmode = mac->mode;
3304
3305         if (rtlhal->current_bandtype == BAND_ON_5G)
3306                 ratr_value = sta->supp_rates[1] << 4;
3307         else
3308                 ratr_value = sta->supp_rates[0];
3309         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3310                 ratr_value = 0xfff;
3311         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3312                         sta->ht_cap.mcs.rx_mask[0] << 12);
3313         switch (wirelessmode) {
3314         case WIRELESS_MODE_B:
3315                 if (ratr_value & 0x0000000c)
3316                         ratr_value &= 0x0000000d;
3317                 else
3318                         ratr_value &= 0x0000000f;
3319                 break;
3320         case WIRELESS_MODE_G:
3321                 ratr_value &= 0x00000FF5;
3322                 break;
3323         case WIRELESS_MODE_N_24G:
3324         case WIRELESS_MODE_N_5G:
3325                 b_nmode = 1;
3326                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3327                         ratr_value &= 0x0007F005;
3328                 } else {
3329                         u32 ratr_mask;
3330
3331                         if (get_rf_type(rtlphy) == RF_1T2R ||
3332                             get_rf_type(rtlphy) == RF_1T1R)
3333                                 ratr_mask = 0x000ff005;
3334                         else
3335                                 ratr_mask = 0x0f0ff005;
3336
3337                         ratr_value &= ratr_mask;
3338                 }
3339                 break;
3340         default:
3341                 if (rtlphy->rf_type == RF_1T2R)
3342                         ratr_value &= 0x000ff0ff;
3343                 else
3344                         ratr_value &= 0x0f0ff0ff;
3345
3346                 break;
3347         }
3348
3349         if ((rtlpriv->btcoexist.bt_coexistence) &&
3350              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3351              (rtlpriv->btcoexist.bt_cur_state) &&
3352              (rtlpriv->btcoexist.bt_ant_isolation) &&
3353              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3354              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3355                 ratr_value &= 0x0fffcfc0;
3356         else
3357                 ratr_value &= 0x0FFFFFFF;
3358
3359         if (b_nmode && ((curtxbw_40mhz &&
3360                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3361                                                  b_curshortgi_20mhz))) {
3362                 ratr_value |= 0x10000000;
3363                 tmp_ratr_value = (ratr_value >> 12);
3364
3365                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3366                         if ((1 << shortgi_rate) & tmp_ratr_value)
3367                                 break;
3368                 }
3369
3370                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3371                     (shortgi_rate << 4) | (shortgi_rate);
3372         }
3373
3374         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3375
3376         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3377                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3378 }
3379
3380 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3381         struct ieee80211_hw *hw, u8 rate_index,
3382         enum wireless_mode wirelessmode)
3383 {
3384         struct rtl_priv *rtlpriv = rtl_priv(hw);
3385         struct rtl_phy *rtlphy = &rtlpriv->phy;
3386         u8 ret = 0;
3387         switch (rate_index) {
3388         case RATR_INX_WIRELESS_NGB:
3389                 if (rtlphy->rf_type == RF_1T1R)
3390                         ret = 1;
3391                 else
3392                         ret = 0;
3393                 ; break;
3394         case RATR_INX_WIRELESS_N:
3395         case RATR_INX_WIRELESS_NG:
3396                 if (rtlphy->rf_type == RF_1T1R)
3397                         ret = 5;
3398                 else
3399                         ret = 4;
3400                 ; break;
3401         case RATR_INX_WIRELESS_NB:
3402                 if (rtlphy->rf_type == RF_1T1R)
3403                         ret = 3;
3404                 else
3405                         ret = 2;
3406                 ; break;
3407         case RATR_INX_WIRELESS_GB:
3408                 ret = 6;
3409                 break;
3410         case RATR_INX_WIRELESS_G:
3411                 ret = 7;
3412                 break;
3413         case RATR_INX_WIRELESS_B:
3414                 ret = 8;
3415                 break;
3416         case RATR_INX_WIRELESS_MC:
3417                 if ((wirelessmode == WIRELESS_MODE_B)
3418                         || (wirelessmode == WIRELESS_MODE_G)
3419                         || (wirelessmode == WIRELESS_MODE_N_24G)
3420                         || (wirelessmode == WIRELESS_MODE_AC_24G))
3421                         ret = 6;
3422                 else
3423                         ret = 7;
3424         case RATR_INX_WIRELESS_AC_5N:
3425                 if (rtlphy->rf_type == RF_1T1R)
3426                         ret = 10;
3427                 else
3428                         ret = 9;
3429                 break;
3430         case RATR_INX_WIRELESS_AC_24N:
3431                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3432                         if (rtlphy->rf_type == RF_1T1R)
3433                                 ret = 10;
3434                         else
3435                                 ret = 9;
3436                 } else {
3437                         if (rtlphy->rf_type == RF_1T1R)
3438                                 ret = 11;
3439                         else
3440                                 ret = 12;
3441                 }
3442                 break;
3443         default:
3444                 ret = 0; break;
3445         }
3446         return ret;
3447 }
3448
3449 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3450 {
3451         u8 i, j, tmp_rate;
3452         u32 rate_bitmap = 0;
3453
3454         for (i = j = 0; i < 4; i += 2, j += 10) {
3455                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3456
3457                 switch (tmp_rate) {
3458                 case 2:
3459                         rate_bitmap = rate_bitmap | (0x03ff << j);
3460                         break;
3461                 case 1:
3462                         rate_bitmap = rate_bitmap | (0x01ff << j);
3463                         break;
3464                 case 0:
3465                         rate_bitmap = rate_bitmap | (0x00ff << j);
3466                         break;
3467                 default:
3468                         break;
3469                 }
3470         }
3471
3472         return rate_bitmap;
3473 }
3474
3475 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3476                                              enum wireless_mode wirelessmode,
3477                                              u32 ratr_bitmap)
3478 {
3479         struct rtl_priv *rtlpriv = rtl_priv(hw);
3480         struct rtl_phy *rtlphy = &rtlpriv->phy;
3481         u32 ret_bitmap = ratr_bitmap;
3482
3483         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3484                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3485                 ret_bitmap = ratr_bitmap;
3486         else if (wirelessmode == WIRELESS_MODE_AC_5G
3487                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3488                 if (rtlphy->rf_type == RF_1T1R)
3489                         ret_bitmap = ratr_bitmap & (~BIT21);
3490                 else
3491                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3492         }
3493
3494         return ret_bitmap;
3495 }
3496
3497 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3498                         u32 ratr_bitmap)
3499 {
3500         u8 ret = 0;
3501         if (wirelessmode < WIRELESS_MODE_N_24G)
3502                 ret =  0;
3503         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3504                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3505                         ret = 3;
3506                 else                                    /* Mix, 1SS */
3507                         ret = 2;
3508         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3509                         ret = 1;
3510         } /* VHT */
3511
3512         return ret << 4;
3513 }
3514
3515 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3516                              u8 mac_id, struct rtl_sta_info *sta_entry,
3517                              enum wireless_mode wirelessmode)
3518 {
3519         u8 b_ldpc = 0;
3520         /*not support ldpc, do not open*/
3521         return b_ldpc << 2;
3522 }
3523
3524 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3525                           enum wireless_mode wirelessmode,
3526                           u32 ratr_bitmap)
3527 {
3528         struct rtl_priv *rtlpriv = rtl_priv(hw);
3529         struct rtl_phy *rtlphy = &rtlpriv->phy;
3530         u8 rf_type = RF_1T1R;
3531
3532         if (rtlphy->rf_type == RF_1T1R)
3533                 rf_type = RF_1T1R;
3534         else if (wirelessmode == WIRELESS_MODE_AC_5G
3535                 || wirelessmode == WIRELESS_MODE_AC_24G
3536                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3537                 if (ratr_bitmap & 0xffc00000)
3538                         rf_type = RF_2T2R;
3539         } else if (wirelessmode == WIRELESS_MODE_N_5G
3540                 || wirelessmode == WIRELESS_MODE_N_24G) {
3541                 if (ratr_bitmap & 0xfff00000)
3542                         rf_type = RF_2T2R;
3543         }
3544
3545         return rf_type;
3546 }
3547
3548 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3549                               u8 mac_id)
3550 {
3551         bool b_short_gi = false;
3552         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3553                                 1 : 0;
3554         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3555                                 1 : 0;
3556         u8 b_curshortgi_80mhz = 0;
3557         b_curshortgi_80mhz = (sta->vht_cap.cap &
3558                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3559
3560         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3561                         b_short_gi = false;
3562
3563         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3564                 || b_curshortgi_20mhz)
3565                 b_short_gi = true;
3566
3567         return b_short_gi;
3568 }
3569
3570 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3571                 struct ieee80211_sta *sta, u8 rssi_level)
3572 {
3573         struct rtl_priv *rtlpriv = rtl_priv(hw);
3574         struct rtl_phy *rtlphy = &rtlpriv->phy;
3575         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3576         struct rtl_sta_info *sta_entry = NULL;
3577         u32 ratr_bitmap;
3578         u8 ratr_index;
3579         enum wireless_mode wirelessmode = 0;
3580         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3581                                 ? 1 : 0;
3582         bool b_shortgi = false;
3583         u8 rate_mask[7];
3584         u8 macid = 0;
3585         u8 mimo_ps = IEEE80211_SMPS_OFF;
3586         u8 rf_type;
3587
3588         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3589         wirelessmode = sta_entry->wireless_mode;
3590
3591         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3592                  "wireless mode = 0x%x\n", wirelessmode);
3593         if (mac->opmode == NL80211_IFTYPE_STATION ||
3594                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3595                 curtxbw_40mhz = mac->bw_40;
3596         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3597                 mac->opmode == NL80211_IFTYPE_ADHOC)
3598                 macid = sta->aid + 1;
3599         if (wirelessmode == WIRELESS_MODE_N_5G ||
3600             wirelessmode == WIRELESS_MODE_AC_5G ||
3601             wirelessmode == WIRELESS_MODE_A)
3602                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3603         else
3604                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3605
3606         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3607                 ratr_bitmap = 0xfff;
3608
3609         if (wirelessmode == WIRELESS_MODE_N_24G
3610                 || wirelessmode == WIRELESS_MODE_N_5G)
3611                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3612                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3613         else if (wirelessmode == WIRELESS_MODE_AC_24G
3614                 || wirelessmode == WIRELESS_MODE_AC_5G
3615                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3616                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3617                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3618
3619         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3620         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3621
3622 /*mac id owner*/
3623         switch (wirelessmode) {
3624         case WIRELESS_MODE_B:
3625                 ratr_index = RATR_INX_WIRELESS_B;
3626                 if (ratr_bitmap & 0x0000000c)
3627                         ratr_bitmap &= 0x0000000d;
3628                 else
3629                         ratr_bitmap &= 0x0000000f;
3630                 break;
3631         case WIRELESS_MODE_G:
3632                 ratr_index = RATR_INX_WIRELESS_GB;
3633
3634                 if (rssi_level == 1)
3635                         ratr_bitmap &= 0x00000f00;
3636                 else if (rssi_level == 2)
3637                         ratr_bitmap &= 0x00000ff0;
3638                 else
3639                         ratr_bitmap &= 0x00000ff5;
3640                 break;
3641         case WIRELESS_MODE_A:
3642                 ratr_index = RATR_INX_WIRELESS_G;
3643                 ratr_bitmap &= 0x00000ff0;
3644                 break;
3645         case WIRELESS_MODE_N_24G:
3646         case WIRELESS_MODE_N_5G:
3647                 if (wirelessmode == WIRELESS_MODE_N_24G)
3648                         ratr_index = RATR_INX_WIRELESS_NGB;
3649                 else
3650                         ratr_index = RATR_INX_WIRELESS_NG;
3651
3652                 if (mimo_ps == IEEE80211_SMPS_STATIC
3653                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3654                         if (rssi_level == 1)
3655                                 ratr_bitmap &= 0x000f0000;
3656                         else if (rssi_level == 2)
3657                                 ratr_bitmap &= 0x000ff000;
3658                         else
3659                                 ratr_bitmap &= 0x000ff005;
3660                 } else {
3661                         if (rf_type == RF_1T1R) {
3662                                 if (curtxbw_40mhz) {
3663                                         if (rssi_level == 1)
3664                                                 ratr_bitmap &= 0x000f0000;
3665                                         else if (rssi_level == 2)
3666                                                 ratr_bitmap &= 0x000ff000;
3667                                         else
3668                                                 ratr_bitmap &= 0x000ff015;
3669                                 } else {
3670                                         if (rssi_level == 1)
3671                                                 ratr_bitmap &= 0x000f0000;
3672                                         else if (rssi_level == 2)
3673                                                 ratr_bitmap &= 0x000ff000;
3674                                         else
3675                                                 ratr_bitmap &= 0x000ff005;
3676                                 }
3677                         } else {
3678                                 if (curtxbw_40mhz) {
3679                                         if (rssi_level == 1)
3680                                                 ratr_bitmap &= 0x0fff0000;
3681                                         else if (rssi_level == 2)
3682                                                 ratr_bitmap &= 0x0ffff000;
3683                                         else
3684                                                 ratr_bitmap &= 0x0ffff015;
3685                                 } else {
3686                                         if (rssi_level == 1)
3687                                                 ratr_bitmap &= 0x0fff0000;
3688                                         else if (rssi_level == 2)
3689                                                 ratr_bitmap &= 0x0ffff000;
3690                                         else
3691                                                 ratr_bitmap &= 0x0ffff005;
3692                                 }
3693                         }
3694                 }
3695                 break;
3696
3697         case WIRELESS_MODE_AC_24G:
3698                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3699                 if (rssi_level == 1)
3700                         ratr_bitmap &= 0xfc3f0000;
3701                 else if (rssi_level == 2)
3702                         ratr_bitmap &= 0xfffff000;
3703                 else
3704                         ratr_bitmap &= 0xffffffff;
3705                 break;
3706
3707         case WIRELESS_MODE_AC_5G:
3708                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3709
3710                 if (rf_type == RF_1T1R) {
3711                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3712                                 ratr_bitmap &= 0x003f8000;
3713                         else if (rssi_level == 2)
3714                                 ratr_bitmap &= 0x003ff000;
3715                         else
3716                                 ratr_bitmap &= 0x003ff010;
3717                 } else {
3718                         if (rssi_level == 1)
3719                                 ratr_bitmap &= 0xfe3f8000;
3720                         else if (rssi_level == 2)
3721                                 ratr_bitmap &= 0xfffff000;
3722                         else
3723                                 ratr_bitmap &= 0xfffff010;
3724                 }
3725                 break;
3726
3727         default:
3728                 ratr_index = RATR_INX_WIRELESS_NGB;
3729
3730                 if (rf_type == RF_1T2R)
3731                         ratr_bitmap &= 0x000ff0ff;
3732                 else
3733                         ratr_bitmap &= 0x0f8ff0ff;
3734                 break;
3735         }
3736
3737         ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3738         sta_entry->ratr_index = ratr_index;
3739         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3740                                                         ratr_bitmap);
3741
3742         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3743                  "ratr_bitmap :%x\n", ratr_bitmap);
3744
3745         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3746                                        (ratr_index << 28)); */
3747
3748         rate_mask[0] = macid;
3749         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3750         rate_mask[2] = rtlphy->current_chan_bw
3751                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3752                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3753
3754         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3755         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3756         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3757         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3758
3759         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3760                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3761                  ratr_index, ratr_bitmap,
3762                  rate_mask[0], rate_mask[1],
3763                  rate_mask[2], rate_mask[3],
3764                  rate_mask[4], rate_mask[5],
3765                  rate_mask[6]);
3766         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3767         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3768 }
3769
3770 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3771                 struct ieee80211_sta *sta, u8 rssi_level)
3772 {
3773         struct rtl_priv *rtlpriv = rtl_priv(hw);
3774         if (rtlpriv->dm.useramask)
3775                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3776         else
3777                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3778                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3779                 rtl8821ae_update_hal_rate_table(hw, sta);
3780 }
3781
3782 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3783 {
3784         struct rtl_priv *rtlpriv = rtl_priv(hw);
3785         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3786         u16 wireless_mode = mac->mode;
3787         u8 sifs_timer, r2t_sifs;
3788
3789         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3790                                       (u8 *)&mac->slot_time);
3791         if (wireless_mode == WIRELESS_MODE_G)
3792                 sifs_timer = 0x0a;
3793         else
3794                 sifs_timer = 0x0e;
3795         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3796
3797         r2t_sifs = 0xa;
3798
3799         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3800             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3801             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3802                 if (mac->vendor == PEER_ATH)
3803                         r2t_sifs = 0x8;
3804                 else
3805                         r2t_sifs = 0xa;
3806         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3807                 r2t_sifs = 0xa;
3808         }
3809
3810         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3811 }
3812
3813 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3814 {
3815         struct rtl_priv *rtlpriv = rtl_priv(hw);
3816         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3817         struct rtl_phy *rtlphy = &rtlpriv->phy;
3818         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3819         u8 u1tmp = 0;
3820         bool b_actuallyset = false;
3821
3822         if (rtlpriv->rtlhal.being_init_adapter)
3823                 return false;
3824
3825         if (ppsc->swrf_processing)
3826                 return false;
3827
3828         spin_lock(&rtlpriv->locks.rf_ps_lock);
3829         if (ppsc->rfchange_inprogress) {
3830                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3831                 return false;
3832         } else {
3833                 ppsc->rfchange_inprogress = true;
3834                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3835         }
3836
3837         cur_rfstate = ppsc->rfpwr_state;
3838
3839         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3840                         rtl_read_byte(rtlpriv,
3841                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3842
3843         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3844
3845         if (rtlphy->polarity_ctl)
3846                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3847         else
3848                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3849
3850         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3851                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3852                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3853
3854                 e_rfpowerstate_toset = ERFON;
3855                 ppsc->hwradiooff = false;
3856                 b_actuallyset = true;
3857         } else if ((!ppsc->hwradiooff)
3858                    && (e_rfpowerstate_toset == ERFOFF)) {
3859                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3860                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3861
3862                 e_rfpowerstate_toset = ERFOFF;
3863                 ppsc->hwradiooff = true;
3864                 b_actuallyset = true;
3865         }
3866
3867         if (b_actuallyset) {
3868                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3869                 ppsc->rfchange_inprogress = false;
3870                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3871         } else {
3872                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3873                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3874
3875                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3876                 ppsc->rfchange_inprogress = false;
3877                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3878         }
3879
3880         *valid = 1;
3881         return !ppsc->hwradiooff;
3882 }
3883
3884 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3885                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3886                      bool is_wepkey, bool clear_all)
3887 {
3888         struct rtl_priv *rtlpriv = rtl_priv(hw);
3889         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3890         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3891         u8 *macaddr = p_macaddr;
3892         u32 entry_id = 0;
3893         bool is_pairwise = false;
3894
3895         static u8 cam_const_addr[4][6] = {
3896                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3897                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3898                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3899                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3900         };
3901         static u8 cam_const_broad[] = {
3902                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3903         };
3904
3905         if (clear_all) {
3906                 u8 idx = 0;
3907                 u8 cam_offset = 0;
3908                 u8 clear_number = 5;
3909
3910                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3911
3912                 for (idx = 0; idx < clear_number; idx++) {
3913                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3914                         rtl_cam_empty_entry(hw, cam_offset + idx);
3915
3916                         if (idx < 5) {
3917                                 memset(rtlpriv->sec.key_buf[idx], 0,
3918                                        MAX_KEY_LEN);
3919                                 rtlpriv->sec.key_len[idx] = 0;
3920                         }
3921                 }
3922         } else {
3923                 switch (enc_algo) {
3924                 case WEP40_ENCRYPTION:
3925                         enc_algo = CAM_WEP40;
3926                         break;
3927                 case WEP104_ENCRYPTION:
3928                         enc_algo = CAM_WEP104;
3929                         break;
3930                 case TKIP_ENCRYPTION:
3931                         enc_algo = CAM_TKIP;
3932                         break;
3933                 case AESCCMP_ENCRYPTION:
3934                         enc_algo = CAM_AES;
3935                         break;
3936                 default:
3937                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3938                                  "switch case %#x not processed\n", enc_algo);
3939                         enc_algo = CAM_TKIP;
3940                         break;
3941                 }
3942
3943                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3944                         macaddr = cam_const_addr[key_index];
3945                         entry_id = key_index;
3946                 } else {
3947                         if (is_group) {
3948                                 macaddr = cam_const_broad;
3949                                 entry_id = key_index;
3950                         } else {
3951                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3952                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3953                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3954                                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
3955                                                          "Can not find free hwsecurity cam entry\n");
3956                                                 return;
3957                                         }
3958                                 } else {
3959                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3960                                 }
3961
3962                                 key_index = PAIRWISE_KEYIDX;
3963                                 is_pairwise = true;
3964                         }
3965                 }
3966
3967                 if (rtlpriv->sec.key_len[key_index] == 0) {
3968                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3969                                  "delete one entry, entry_id is %d\n",
3970                                  entry_id);
3971                         if (mac->opmode == NL80211_IFTYPE_AP)
3972                                 rtl_cam_del_entry(hw, p_macaddr);
3973                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3974                 } else {
3975                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3976                                  "add one entry\n");
3977                         if (is_pairwise) {
3978                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3979                                          "set Pairwise key\n");
3980
3981                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3982                                                       entry_id, enc_algo,
3983                                                       CAM_CONFIG_NO_USEDK,
3984                                                       rtlpriv->sec.key_buf[key_index]);
3985                         } else {
3986                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3987                                          "set group key\n");
3988
3989                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3990                                         rtl_cam_add_one_entry(hw,
3991                                                         rtlefuse->dev_addr,
3992                                                         PAIRWISE_KEYIDX,
3993                                                         CAM_PAIRWISE_KEY_POSITION,
3994                                                         enc_algo,
3995                                                         CAM_CONFIG_NO_USEDK,
3996                                                         rtlpriv->sec.key_buf
3997                                                         [entry_id]);
3998                                 }
3999
4000                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4001                                                 entry_id, enc_algo,
4002                                                 CAM_CONFIG_NO_USEDK,
4003                                                 rtlpriv->sec.key_buf[entry_id]);
4004                         }
4005                 }
4006         }
4007 }
4008
4009 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4010 {
4011         struct rtl_priv *rtlpriv = rtl_priv(hw);
4012
4013         /* 0:Low, 1:High, 2:From Efuse. */
4014         rtlpriv->btcoexist.reg_bt_iso = 2;
4015         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4016         rtlpriv->btcoexist.reg_bt_sco = 3;
4017         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4018         rtlpriv->btcoexist.reg_bt_sco = 0;
4019 }
4020
4021 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4022 {
4023         struct rtl_priv *rtlpriv = rtl_priv(hw);
4024
4025         if (rtlpriv->cfg->ops->get_btc_status())
4026                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4027 }
4028
4029 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4030 {
4031 }
4032
4033 void rtl8821ae_resume(struct ieee80211_hw *hw)
4034 {
4035 }
4036
4037 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4038 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4039         bool allow_all_da, bool write_into_reg)
4040 {
4041         struct rtl_priv *rtlpriv = rtl_priv(hw);
4042         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4043
4044         if (allow_all_da) /* Set BIT0 */
4045                 rtlpci->receive_config |= RCR_AAP;
4046         else /* Clear BIT0 */
4047                 rtlpci->receive_config &= ~RCR_AAP;
4048
4049         if (write_into_reg)
4050                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4051
4052         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4053                 "receive_config=0x%08X, write_into_reg=%d\n",
4054                 rtlpci->receive_config, write_into_reg);
4055 }
4056
4057 /* WKFMCAMAddAllEntry8812 */
4058 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4059                                   struct rtl_wow_pattern *rtl_pattern,
4060                                   u8 index)
4061 {
4062         struct rtl_priv *rtlpriv = rtl_priv(hw);
4063         u32 cam = 0;
4064         u8 addr = 0;
4065         u16 rxbuf_addr;
4066         u8 tmp, count = 0;
4067         u16 cam_start;
4068         u16 offset;
4069
4070         /* Count the WFCAM entry start offset. */
4071
4072         /* RX page size = 128 byte */
4073         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4074         /* We should start from the boundry */
4075         cam_start = offset * 128;
4076
4077         /* Enable Rx packet buffer access. */
4078         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4079         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4080                 /* Set Rx packet buffer offset.
4081                  * RxBufer pointer increases 1,
4082                  * we can access 8 bytes in Rx packet buffer.
4083                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4084                  * RxBufer addr = (CAM start offset +
4085                  *                 per entry offset of a WKFM CAM)/8
4086                  *      * index: The index of the wake up frame mask
4087                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4088                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4089                  */
4090                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4091                 /* Set R/W start offset */
4092                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4093
4094                 if (addr == 0) {
4095                         cam = BIT(31) | rtl_pattern->crc;
4096
4097                         if (rtl_pattern->type == UNICAST_PATTERN)
4098                                 cam |= BIT(24);
4099                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4100                                 cam |= BIT(25);
4101                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4102                                 cam |= BIT(26);
4103
4104                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4105                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4106                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4107                                   REG_PKTBUF_DBG_DATA_L, cam);
4108
4109                         /* Write to Rx packet buffer. */
4110                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4111                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4112                         cam = rtl_pattern->mask[addr - 2];
4113
4114                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4115                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4116                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4117                                   REG_PKTBUF_DBG_DATA_L, cam);
4118
4119                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4120                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4121                         cam = rtl_pattern->mask[addr - 2];
4122
4123                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4124                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4125                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4126                                   REG_PKTBUF_DBG_DATA_H, cam);
4127
4128                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4129                 }
4130
4131                 count = 0;
4132                 do {
4133                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4134                         udelay(2);
4135                         count++;
4136                 } while (tmp && count < 100);
4137
4138                 RT_ASSERT((count < 100),
4139                           "Write wake up frame mask FAIL %d value!\n", tmp);
4140         }
4141         /* Disable Rx packet buffer access. */
4142         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4143                        DISABLE_TRXPKT_BUF_ACCESS);
4144 }