drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61                                  skb->len, PCI_DMA_TODEVICE);
  62                 kfree_skb(skb);
  63                 ring->idx = (ring->idx + 1) % ring->entries;
  64         }
  65         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66 }
  67
  68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                         u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76
  77         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  78 }
  79
  80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  81 {
  82         struct rtl_priv *rtlpriv = rtl_priv(hw);
  83         u8 tmp1byte;
  84
  85         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  86         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 102         tmp1byte |= BIT(0);
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 104 }
 105
 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 107 {
 108         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 109 }
 110
 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                         (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         goto change_done;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         goto change_done;
 149                 }
 150         }
 151 change_done:
 152         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                         (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer)
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                         u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 247         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 260                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                 (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                 (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                 (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                 (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                 (u8 *)(&fw_current_inps));
 274         }
 275 }
 276
 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 278 {
 279         struct rtl_priv *rtlpriv = rtl_priv(hw);
 280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 282         bool fw_current_inps = true;
 283         u8 rpwm_val;
 284
 285         if (ppsc->low_power_enable) {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw,
 288                                 HW_VAR_FW_PSMODE_STATUS,
 289                                 (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_H2C_FW_PWRMODE,
 292                                 (u8 *)(&ppsc->fwctrl_psmode));
 293                 rtlhal->allow_sw_to_change_hwclc = true;
 294                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 295         } else {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw,
 298                                 HW_VAR_FW_PSMODE_STATUS,
 299                                 (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw,
 301                                 HW_VAR_H2C_FW_PWRMODE,
 302                                 (u8 *)(&ppsc->fwctrl_psmode));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_SET_RPWM,
 305                                 (u8 *)(&rpwm_val));
 306         }
 307 }
 308
 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 310                                           bool dl_whole_packets)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 314         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 315         u8 count = 0, dlbcn_count = 0;
 316         bool send_beacon = false;
 317
 318         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 319         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 320
 321         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 323
 324         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 325         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 326                        tmp_reg422 & (~BIT(6)));
 327         if (tmp_reg422 & BIT(6))
 328                 send_beacon = true;
 329
 330         do {
 331                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 332                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 333                                (bcnvalid_reg | BIT(0)));
 334                 _rtl8821ae_return_beacon_queue_skb(hw);
 335
 336                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 337                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 338                                                      dl_whole_packets);
 339                 else
 340                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 341                                                      dl_whole_packets);
 342
 343                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 344                 count = 0;
 345                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 346                         count++;
 347                         udelay(10);
 348                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 349                 }
 350                 dlbcn_count++;
 351         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 352
 353         if (!(bcnvalid_reg & BIT(0)))
 354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 355                          "Download RSVD page failed!\n");
 356         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 357                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 358                 _rtl8821ae_return_beacon_queue_skb(hw);
 359                 if (send_beacon) {
 360                         dlbcn_count = 0;
 361                         do {
 362                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 363                                                bcnvalid_reg | BIT(0));
 364
 365                                 _rtl8821ae_return_beacon_queue_skb(hw);
 366
 367                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 368                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 369                                                                      false);
 370                                 else
 371                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 372                                                                      false);
 373
 374                                 /* check rsvd page download OK. */
 375                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 376                                                              REG_TDECTRL + 2);
 377                                 count = 0;
 378                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 379                                         count++;
 380                                         udelay(10);
 381                                         bcnvalid_reg =
 382                                           rtl_read_byte(rtlpriv,
 383                                                         REG_TDECTRL + 2);
 384                                 }
 385                                 dlbcn_count++;
 386                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 387
 388                         if (!(bcnvalid_reg & BIT(0)))
 389                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 390                                          "2 Download RSVD page failed!\n");
 391                 }
 392         }
 393
 394         if (bcnvalid_reg & BIT(0))
 395                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 396
 397         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 399
 400         if (send_beacon)
 401                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 402
 403         if (!rtlhal->enter_pnp_sleep) {
 404                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406         }
 407 }
 408
 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 410 {
 411         struct rtl_priv *rtlpriv = rtl_priv(hw);
 412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415
 416         switch (variable) {
 417         case HW_VAR_ETHER_ADDR:
 418                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 419                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 420                 break;
 421         case HW_VAR_BSSID:
 422                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 423                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 424                 break;
 425         case HW_VAR_MEDIA_STATUS:
 426                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 427                 break;
 428         case HW_VAR_SLOT_TIME:
 429                 *((u8 *)(val)) = mac->slot_time;
 430                 break;
 431         case HW_VAR_BEACON_INTERVAL:
 432                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 433                 break;
 434         case HW_VAR_ATIM_WINDOW:
 435                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 436                 break;
 437         case HW_VAR_RCR:
 438                 *((u32 *)(val)) = rtlpci->receive_config;
 439                 break;
 440         case HW_VAR_RF_STATE:
 441                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 442                 break;
 443         case HW_VAR_FWLPS_RF_ON:{
 444                 enum rf_pwrstate rfstate;
 445                 u32 val_rcr;
 446
 447                 rtlpriv->cfg->ops->get_hw_reg(hw,
 448                                               HW_VAR_RF_STATE,
 449                                               (u8 *)(&rfstate));
 450                 if (rfstate == ERFOFF) {
 451                         *((bool *)(val)) = true;
 452                 } else {
 453                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 454                         val_rcr &= 0x00070000;
 455                         if (val_rcr)
 456                                 *((bool *)(val)) = false;
 457                         else
 458                                 *((bool *)(val)) = true;
 459                 }
 460                 break; }
 461         case HW_VAR_FW_PSMODE_STATUS:
 462                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 463                 break;
 464         case HW_VAR_CORRECT_TSF:{
 465                 u64 tsf;
 466                 u32 *ptsf_low = (u32 *)&tsf;
 467                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 468
 469                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 470                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 471
 472                 *((u64 *)(val)) = tsf;
 473
 474                 break; }
 475         case HAL_DEF_WOWLAN:
 476                 if (ppsc->wo_wlan_mode)
 477                         *((bool *)(val)) = true;
 478                 else
 479                         *((bool *)(val)) = false;
 480                 break;
 481         default:
 482                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 483                          "switch case %#x not processed\n", variable);
 484                 break;
 485         }
 486 }
 487
 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 494         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 495         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 496         u8 idx;
 497
 498         switch (variable) {
 499         case HW_VAR_ETHER_ADDR:{
 500                         for (idx = 0; idx < ETH_ALEN; idx++) {
 501                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 502                                                val[idx]);
 503                         }
 504                         break;
 505                 }
 506         case HW_VAR_BASIC_RATE:{
 507                         u16 b_rate_cfg = ((u16 *)val)[0];
 508                         b_rate_cfg = b_rate_cfg & 0x15f;
 509                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 510                         break;
 511                 }
 512         case HW_VAR_BSSID:{
 513                         for (idx = 0; idx < ETH_ALEN; idx++) {
 514                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 515                                                val[idx]);
 516                         }
 517                         break;
 518                 }
 519         case HW_VAR_SIFS:
 520                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 521                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 522
 523                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 524                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 525
 526                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 528                 break;
 529         case HW_VAR_R2T_SIFS:
 530                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 531                 break;
 532         case HW_VAR_SLOT_TIME:{
 533                 u8 e_aci;
 534
 535                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 536                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 537
 538                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 539
 540                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 541                         rtlpriv->cfg->ops->set_hw_reg(hw,
 542                                                       HW_VAR_AC_PARAM,
 543                                                       (u8 *)(&e_aci));
 544                 }
 545                 break; }
 546         case HW_VAR_ACK_PREAMBLE:{
 547                 u8 reg_tmp;
 548                 u8 short_preamble = (bool)(*(u8 *)val);
 549
 550                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 551                 if (short_preamble) {
 552                         reg_tmp |= BIT(1);
 553                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 554                                        reg_tmp);
 555                 } else {
 556                         reg_tmp &= (~BIT(1));
 557                         rtl_write_byte(rtlpriv,
 558                                 REG_TRXPTCL_CTL + 2,
 559                                 reg_tmp);
 560                 }
 561                 break; }
 562         case HW_VAR_WPA_CONFIG:
 563                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 564                 break;
 565         case HW_VAR_AMPDU_MIN_SPACE:{
 566                 u8 min_spacing_to_set;
 567                 u8 sec_min_space;
 568
 569                 min_spacing_to_set = *((u8 *)val);
 570                 if (min_spacing_to_set <= 7) {
 571                         sec_min_space = 0;
 572
 573                         if (min_spacing_to_set < sec_min_space)
 574                                 min_spacing_to_set = sec_min_space;
 575
 576                         mac->min_space_cfg = ((mac->min_space_cfg &
 577                                                0xf8) |
 578                                               min_spacing_to_set);
 579
 580                         *val = min_spacing_to_set;
 581
 582                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 583                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 584                                   mac->min_space_cfg);
 585
 586                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 587                                        mac->min_space_cfg);
 588                 }
 589                 break; }
 590         case HW_VAR_SHORTGI_DENSITY:{
 591                 u8 density_to_set;
 592
 593                 density_to_set = *((u8 *)val);
 594                 mac->min_space_cfg |= (density_to_set << 3);
 595
 596                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 597                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 598                           mac->min_space_cfg);
 599
 600                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 601                                mac->min_space_cfg);
 602
 603                 break; }
 604         case HW_VAR_AMPDU_FACTOR:{
 605                 u32     ampdu_len =  (*((u8 *)val));
 606
 607                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 608                         if (ampdu_len < VHT_AGG_SIZE_128K)
 609                                 ampdu_len =
 610                                         (0x2000 << (*((u8 *)val))) - 1;
 611                         else
 612                                 ampdu_len = 0x1ffff;
 613                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 614                         if (ampdu_len < HT_AGG_SIZE_64K)
 615                                 ampdu_len =
 616                                         (0x2000 << (*((u8 *)val))) - 1;
 617                         else
 618                                 ampdu_len = 0xffff;
 619                 }
 620                 ampdu_len |= BIT(31);
 621
 622                 rtl_write_dword(rtlpriv,
 623                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 624                 break; }
 625         case HW_VAR_AC_PARAM:{
 626                 u8 e_aci = *((u8 *)val);
 627
 628                 rtl8821ae_dm_init_edca_turbo(hw);
 629                 if (rtlpci->acm_method != EACMWAY2_SW)
 630                         rtlpriv->cfg->ops->set_hw_reg(hw,
 631                                                       HW_VAR_ACM_CTRL,
 632                                                       (u8 *)(&e_aci));
 633                 break; }
 634         case HW_VAR_ACM_CTRL:{
 635                 u8 e_aci = *((u8 *)val);
 636                 union aci_aifsn *p_aci_aifsn =
 637                     (union aci_aifsn *)(&mac->ac[0].aifs);
 638                 u8 acm = p_aci_aifsn->f.acm;
 639                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 640
 641                 acm_ctrl =
 642                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 643
 644                 if (acm) {
 645                         switch (e_aci) {
 646                         case AC0_BE:
 647                                 acm_ctrl |= ACMHW_BEQEN;
 648                                 break;
 649                         case AC2_VI:
 650                                 acm_ctrl |= ACMHW_VIQEN;
 651                                 break;
 652                         case AC3_VO:
 653                                 acm_ctrl |= ACMHW_VOQEN;
 654                                 break;
 655                         default:
 656                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 657                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 658                                          acm);
 659                                 break;
 660                         }
 661                 } else {
 662                         switch (e_aci) {
 663                         case AC0_BE:
 664                                 acm_ctrl &= (~ACMHW_BEQEN);
 665                                 break;
 666                         case AC2_VI:
 667                                 acm_ctrl &= (~ACMHW_VIQEN);
 668                                 break;
 669                         case AC3_VO:
 670                                 acm_ctrl &= (~ACMHW_VOQEN);
 671                                 break;
 672                         default:
 673                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 674                                          "switch case %#x not processed\n",
 675                                          e_aci);
 676                                 break;
 677                         }
 678                 }
 679
 680                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 681                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 682                          acm_ctrl);
 683                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 684                 break; }
 685         case HW_VAR_RCR:
 686                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 687                 rtlpci->receive_config = ((u32 *)(val))[0];
 688                 break;
 689         case HW_VAR_RETRY_LIMIT:{
 690                 u8 retry_limit = ((u8 *)(val))[0];
 691
 692                 rtl_write_word(rtlpriv, REG_RL,
 693                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 694                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 695                 break; }
 696         case HW_VAR_DUAL_TSF_RST:
 697                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 698                 break;
 699         case HW_VAR_EFUSE_BYTES:
 700                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 701                 break;
 702         case HW_VAR_EFUSE_USAGE:
 703                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 704                 break;
 705         case HW_VAR_IO_CMD:
 706                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 707                 break;
 708         case HW_VAR_SET_RPWM:{
 709                 u8 rpwm_val;
 710
 711                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 712                 udelay(1);
 713
 714                 if (rpwm_val & BIT(7)) {
 715                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 716                                        (*(u8 *)val));
 717                 } else {
 718                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 719                                        ((*(u8 *)val) | BIT(7)));
 720                 }
 721
 722                 break; }
 723         case HW_VAR_H2C_FW_PWRMODE:
 724                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 725                 break;
 726         case HW_VAR_FW_PSMODE_STATUS:
 727                 ppsc->fw_current_inpsmode = *((bool *)val);
 728                 break;
 729         case HW_VAR_INIT_RTS_RATE:
 730                 break;
 731         case HW_VAR_RESUME_CLK_ON:
 732                 _rtl8821ae_set_fw_ps_rf_on(hw);
 733                 break;
 734         case HW_VAR_FW_LPS_ACTION:{
 735                 bool b_enter_fwlps = *((bool *)val);
 736
 737                 if (b_enter_fwlps)
 738                         _rtl8821ae_fwlps_enter(hw);
 739                  else
 740                         _rtl8821ae_fwlps_leave(hw);
 741                  break; }
 742         case HW_VAR_H2C_FW_JOINBSSRPT:{
 743                 u8 mstatus = (*(u8 *)val);
 744
 745                 if (mstatus == RT_MEDIA_CONNECT) {
 746                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 747                                                       NULL);
 748                         _rtl8821ae_download_rsvd_page(hw, false);
 749                 }
 750                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 751
 752                 break; }
 753         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 754                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 755                 break;
 756         case HW_VAR_AID:{
 757                 u16 u2btmp;
 758                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 759                 u2btmp &= 0xC000;
 760                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 761                                mac->assoc_id));
 762                 break; }
 763         case HW_VAR_CORRECT_TSF:{
 764                 u8 btype_ibss = ((u8 *)(val))[0];
 765
 766                 if (btype_ibss)
 767                         _rtl8821ae_stop_tx_beacon(hw);
 768
 769                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 770
 771                 rtl_write_dword(rtlpriv, REG_TSFTR,
 772                                 (u32)(mac->tsf & 0xffffffff));
 773                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 774                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 775
 776                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 777
 778                 if (btype_ibss)
 779                         _rtl8821ae_resume_tx_beacon(hw);
 780                 break; }
 781         case HW_VAR_NAV_UPPER: {
 782                 u32     us_nav_upper = *(u32 *)val;
 783
 784                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 785                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 786                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 787                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 788                         break;
 789                 }
 790                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 791                                ((u8)((us_nav_upper +
 792                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 793                                 HAL_92C_NAV_UPPER_UNIT)));
 794                 break; }
 795         case HW_VAR_KEEP_ALIVE: {
 796                 u8 array[2];
 797                 array[0] = 0xff;
 798                 array[1] = *((u8 *)val);
 799                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 800                                        array);
 801                 break; }
 802         default:
 803                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 804                          "switch case %#x not processed\n", variable);
 805                 break;
 806         }
 807 }
 808
 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         bool status = true;
 813         long count = 0;
 814         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 815                     _LLT_OP(_LLT_WRITE_ACCESS);
 816
 817         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 818
 819         do {
 820                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 821                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 822                         break;
 823
 824                 if (count > POLLING_LLT_THRESHOLD) {
 825                         pr_err("Failed to polling write LLT done at address %d!\n",
 826                                address);
 827                         status = false;
 828                         break;
 829                 }
 830         } while (++count);
 831
 832         return status;
 833 }
 834
 835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 836 {
 837         struct rtl_priv *rtlpriv = rtl_priv(hw);
 838         unsigned short i;
 839         u8 txpktbuf_bndy;
 840         u32 rqpn;
 841         u8 maxpage;
 842         bool status;
 843
 844         maxpage = 255;
 845         txpktbuf_bndy = 0xF7;
 846         rqpn = 0x80e60808;
 847
 848         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 849         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 850
 851         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 852
 853         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 854         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 855
 856         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 857         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 858
 859         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 860                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 861                 if (!status)
 862                         return status;
 863         }
 864
 865         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 866         if (!status)
 867                 return status;
 868
 869         for (i = txpktbuf_bndy; i < maxpage; i++) {
 870                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 871                 if (!status)
 872                         return status;
 873         }
 874
 875         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 876         if (!status)
 877                 return status;
 878
 879         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 880
 881         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 882
 883         return true;
 884 }
 885
 886 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 887 {
 888         struct rtl_priv *rtlpriv = rtl_priv(hw);
 889         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 890         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 891         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 892
 893         if (rtlpriv->rtlhal.up_first_time)
 894                 return;
 895
 896         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 897                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 898                         rtl8812ae_sw_led_on(hw, pled0);
 899                 else
 900                         rtl8821ae_sw_led_on(hw, pled0);
 901         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 902                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 903                         rtl8812ae_sw_led_on(hw, pled0);
 904                 else
 905                         rtl8821ae_sw_led_on(hw, pled0);
 906         else
 907                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 908                         rtl8812ae_sw_led_off(hw, pled0);
 909                 else
 910                         rtl8821ae_sw_led_off(hw, pled0);
 911 }
 912
 913 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 914 {
 915         struct rtl_priv *rtlpriv = rtl_priv(hw);
 916         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 917         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 918
 919         u8 bytetmp = 0;
 920         u16 wordtmp = 0;
 921         bool mac_func_enable = rtlhal->mac_func_enable;
 922
 923         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 924
 925         /*Auto Power Down to CHIP-off State*/
 926         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 927         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 928
 929         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 930                 /* HW Power on sequence*/
 931                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 932                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 933                                               RTL8812_NIC_ENABLE_FLOW)) {
 934                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 935                                          "init 8812 MAC Fail as power on failure\n");
 936                                 return false;
 937                 }
 938         } else {
 939                 /* HW Power on sequence */
 940                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 941                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 942                                               RTL8821A_NIC_ENABLE_FLOW)){
 943                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 944                                 "init 8821 MAC Fail as power on failure\n");
 945                         return false;
 946                 }
 947         }
 948
 949         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 950         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 951
 952         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 953         bytetmp = 0xff;
 954         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 955         mdelay(2);
 956
 957         bytetmp = 0xff;
 958         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 959         mdelay(2);
 960
 961         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 962                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 963                 if (bytetmp & BIT(0)) {
 964                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 965                         bytetmp |= BIT(6);
 966                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 967                 }
 968         }
 969
 970         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 971         bytetmp &= ~BIT(4);
 972         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 973
 974         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 975
 976         if (!mac_func_enable) {
 977                 if (!_rtl8821ae_llt_table_init(hw))
 978                         return false;
 979         }
 980
 981         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 982         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 983
 984         /* Enable FW Beamformer Interrupt */
 985         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 986         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 987
 988         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 989         wordtmp &= 0xf;
 990         wordtmp |= 0xF5B1;
 991         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 992
 993         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 994         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 995         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 996         /*low address*/
 997         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 998                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
 999         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1000                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1001         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1002                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1003         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1004                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1005         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1006                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1007         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1008                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1009         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1010                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1011         rtl_write_dword(rtlpriv, REG_RX_DESA,
1012                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1013
1014         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1015
1016         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1017
1018         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1019
1020         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1021         _rtl8821ae_gen_refresh_led_state(hw);
1022
1023         return true;
1024 }
1025
1026 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1027 {
1028         struct rtl_priv *rtlpriv = rtl_priv(hw);
1029         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1030         u32 reg_rrsr;
1031
1032         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1033
1034         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1035         /* ARFB table 9 for 11ac 5G 2SS */
1036         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1037         /* ARFB table 10 for 11ac 5G 1SS */
1038         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1039         /* ARFB table 11 for 11ac 24G 1SS */
1040         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1041         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1042         /* ARFB table 12 for 11ac 24G 1SS */
1043         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1044         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1045         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1046         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1047         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1048
1049         /*Set retry limit*/
1050         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1051
1052         /* Set Data / Response auto rate fallack retry count*/
1053         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1054         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1055         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1056         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1057
1058         rtlpci->reg_bcn_ctrl_val = 0x1d;
1059         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1060
1061         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1062         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1063
1064         /* AGGR_BK_TIME Reg51A 0x16 */
1065         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1066
1067         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1068         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1069
1070         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1071         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1072         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1073 }
1074
1075 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1076 {
1077         u16 ret = 0;
1078         u8 tmp = 0, count = 0;
1079
1080         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1081         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1082         count = 0;
1083         while (tmp && count < 20) {
1084                 udelay(10);
1085                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1086                 count++;
1087         }
1088         if (0 == tmp)
1089                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1090
1091         return ret;
1092 }
1093
1094 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1095 {
1096         u8 tmp = 0, count = 0;
1097
1098         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1099         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1100         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1101         count = 0;
1102         while (tmp && count < 20) {
1103                 udelay(10);
1104                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1105                 count++;
1106         }
1107 }
1108
1109 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1110 {
1111         u16 read_addr = addr & 0xfffc;
1112         u8 tmp = 0, count = 0, ret = 0;
1113
1114         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1115         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1116         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1117         count = 0;
1118         while (tmp && count < 20) {
1119                 udelay(10);
1120                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1121                 count++;
1122         }
1123         if (0 == tmp) {
1124                 read_addr = REG_DBI_RDATA + addr % 4;
1125                 ret = rtl_read_byte(rtlpriv, read_addr);
1126         }
1127         return ret;
1128 }
1129
1130 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1131 {
1132         u8 tmp = 0, count = 0;
1133         u16 wrtie_addr, remainder = addr % 4;
1134
1135         wrtie_addr = REG_DBI_WDATA + remainder;
1136         rtl_write_byte(rtlpriv, wrtie_addr, data);
1137
1138         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1139         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1140
1141         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1142
1143         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1144         count = 0;
1145         while (tmp && count < 20) {
1146                 udelay(10);
1147                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1148                 count++;
1149         }
1150 }
1151
1152 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1153 {
1154         struct rtl_priv *rtlpriv = rtl_priv(hw);
1155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1156         u8 tmp;
1157
1158         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1159                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1160                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1161
1162                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1163                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1164         }
1165
1166         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1167         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1168                              ASPM_L1_LATENCY << 3);
1169
1170         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1171         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1172
1173         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1174                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1175                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1176         }
1177 }
1178
1179 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1180 {
1181         struct rtl_priv *rtlpriv = rtl_priv(hw);
1182         u8 sec_reg_value;
1183         u8 tmp;
1184
1185         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1186                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1187                   rtlpriv->sec.pairwise_enc_algorithm,
1188                   rtlpriv->sec.group_enc_algorithm);
1189
1190         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1191                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1192                          "not open hw encryption\n");
1193                 return;
1194         }
1195
1196         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1197
1198         if (rtlpriv->sec.use_defaultkey) {
1199                 sec_reg_value |= SCR_TXUSEDK;
1200                 sec_reg_value |= SCR_RXUSEDK;
1201         }
1202
1203         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1204
1205         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1206         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1207
1208         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1209                  "The SECR-value %x\n", sec_reg_value);
1210
1211         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1212 }
1213
1214 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1215 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1216 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1217 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1218 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1219 /* ----------------------------------------------------------- */
1220
1221 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1222 {
1223         struct rtl_priv *rtlpriv = rtl_priv(hw);
1224         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1225                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1226                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1227
1228         rtlpriv->cfg->ops->set_hw_reg(hw,
1229                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1230
1231         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1232                  "Initialize MacId media status: from %d to %d\n",
1233                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1234                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1235 }
1236
1237 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1238 {
1239         struct rtl_priv *rtlpriv = rtl_priv(hw);
1240         u8 tmp;
1241
1242         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1243         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1244         if (!(tmp & BIT(2))) {
1245                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1246                 mdelay(100);
1247         }
1248
1249         /* read reg 0x350 Bit[25] if 1 : RX hang */
1250         /* read reg 0x350 Bit[24] if 1 : TX hang */
1251         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1252         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1253                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1254                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1255                 return true;
1256         } else {
1257                 return false;
1258         }
1259 }
1260
1261 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1262                                          bool mac_power_on,
1263                                          bool in_watchdog)
1264 {
1265         struct rtl_priv *rtlpriv = rtl_priv(hw);
1266         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1267         u8 tmp;
1268         bool release_mac_rx_pause;
1269         u8 backup_pcie_dma_pause;
1270
1271         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1272
1273         /* 1. Disable register write lock. 0x1c[1] = 0 */
1274         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1275         tmp &= ~(BIT(1));
1276         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1277         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1278                 /* write 0xCC bit[2] = 1'b1 */
1279                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1280                 tmp |= BIT(2);
1281                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1282         }
1283
1284         /* 2. Check and pause TRX DMA */
1285         /* write 0x284 bit[18] = 1'b1 */
1286         /* write 0x301 = 0xFF */
1287         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1288         if (tmp & BIT(2)) {
1289                 /* Already pause before the function for another purpose. */
1290                 release_mac_rx_pause = false;
1291         } else {
1292                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1293                 release_mac_rx_pause = true;
1294         }
1295         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1296         if (backup_pcie_dma_pause != 0xFF)
1297                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1298
1299         if (mac_power_on) {
1300                 /* 3. reset TRX function */
1301                 /* write 0x100 = 0x00 */
1302                 rtl_write_byte(rtlpriv, REG_CR, 0);
1303         }
1304
1305         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1306         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1307         tmp &= ~(BIT(0));
1308         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1309
1310         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1311         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1312         tmp |= BIT(0);
1313         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1314
1315         if (mac_power_on) {
1316                 /* 6. enable TRX function */
1317                 /* write 0x100 = 0xFF */
1318                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1319
1320                 /* We should init LLT & RQPN and
1321                  * prepare Tx/Rx descrptor address later
1322                  * because MAC function is reset.*/
1323         }
1324
1325         /* 7. Restore PCIe autoload down bit */
1326         /* 8812AE does not has the defination. */
1327         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1328                 /* write 0xF8 bit[17] = 1'b1 */
1329                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1330                 tmp |= BIT(1);
1331                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1332         }
1333
1334         /* In MAC power on state, BB and RF maybe in ON state,
1335          * if we release TRx DMA here.
1336          * it will cause packets to be started to Tx/Rx,
1337          * so we release Tx/Rx DMA later.*/
1338         if (!mac_power_on/* || in_watchdog*/) {
1339                 /* 8. release TRX DMA */
1340                 /* write 0x284 bit[18] = 1'b0 */
1341                 /* write 0x301 = 0x00 */
1342                 if (release_mac_rx_pause) {
1343                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1344                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1345                                        tmp & (~BIT(2)));
1346                 }
1347                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1348                                backup_pcie_dma_pause);
1349         }
1350
1351         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1352                 /* 9. lock system register */
1353                 /* write 0xCC bit[2] = 1'b0 */
1354                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1355                 tmp &= ~(BIT(2));
1356                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1357         }
1358         return true;
1359 }
1360
1361 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1362 {
1363         struct rtl_priv *rtlpriv = rtl_priv(hw);
1364         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1365         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1366         u8 fw_reason = 0;
1367         struct timeval ts;
1368
1369         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1370
1371         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1372                  fw_reason);
1373
1374         ppsc->wakeup_reason = 0;
1375
1376         do_gettimeofday(&ts);
1377         rtlhal->last_suspend_sec = ts.tv_sec;
1378
1379         switch (fw_reason) {
1380         case FW_WOW_V2_PTK_UPDATE_EVENT:
1381                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1382                 do_gettimeofday(&ts);
1383                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1384                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1385                          "It's a WOL PTK Key update event!\n");
1386                 break;
1387         case FW_WOW_V2_GTK_UPDATE_EVENT:
1388                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1389                 do_gettimeofday(&ts);
1390                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1391                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1392                          "It's a WOL GTK Key update event!\n");
1393                 break;
1394         case FW_WOW_V2_DISASSOC_EVENT:
1395                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1396                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1397                          "It's a disassociation event!\n");
1398                 break;
1399         case FW_WOW_V2_DEAUTH_EVENT:
1400                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1401                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1402                          "It's a deauth event!\n");
1403                 break;
1404         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1405                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1406                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1407                          "It's a Fw disconnect decision (AP lost) event!\n");
1408         break;
1409         case FW_WOW_V2_MAGIC_PKT_EVENT:
1410                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1411                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1412                          "It's a magic packet event!\n");
1413                 break;
1414         case FW_WOW_V2_UNICAST_PKT_EVENT:
1415                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1416                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1417                          "It's an unicast packet event!\n");
1418                 break;
1419         case FW_WOW_V2_PATTERN_PKT_EVENT:
1420                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1421                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1422                          "It's a pattern match event!\n");
1423                 break;
1424         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1425                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1426                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1427                          "It's an RTD3 Ssid match event!\n");
1428                 break;
1429         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1430                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1431                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1432                          "It's an RealWoW wake packet event!\n");
1433                 break;
1434         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1435                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1436                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1437                          "It's an RealWoW ack lost event!\n");
1438                 break;
1439         default:
1440                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1441                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1442                           fw_reason);
1443                 break;
1444         }
1445 }
1446
1447 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1448 {
1449         struct rtl_priv *rtlpriv = rtl_priv(hw);
1450         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1451
1452         /*low address*/
1453         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1454                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1455         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1456                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1457         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1458                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1459         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1460                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1461         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1462                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1463         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1464                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1465         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1466                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1467         rtl_write_dword(rtlpriv, REG_RX_DESA,
1468                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1469 }
1470
1471 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1472 {
1473         bool status = true;
1474         u32 i;
1475         u32 txpktbuf_bndy = boundary;
1476         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1477
1478         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1479                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1480                 if (!status)
1481                         return status;
1482         }
1483
1484         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1485         if (!status)
1486                 return status;
1487
1488         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1489                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1490                 if (!status)
1491                         return status;
1492         }
1493
1494         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1495                                       txpktbuf_bndy);
1496         if (!status)
1497                 return status;
1498
1499         return status;
1500 }
1501
1502 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1503                              u16 npq_rqpn_value, u32 rqpn_val)
1504 {
1505         struct rtl_priv *rtlpriv = rtl_priv(hw);
1506         u8 tmp;
1507         bool ret = true;
1508         u16 count = 0, tmp16;
1509         bool support_remote_wakeup;
1510
1511         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1512                                       (u8 *)(&support_remote_wakeup));
1513
1514         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1515                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1516                   boundary, npq_rqpn_value, rqpn_val);
1517
1518         /* stop PCIe DMA
1519          * 1. 0x301[7:0] = 0xFE */
1520         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1521
1522         /* wait TXFF empty
1523          * 2. polling till 0x41A[15:0]=0x07FF */
1524         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1525         while ((tmp16 & 0x07FF) != 0x07FF) {
1526                 udelay(100);
1527                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1528                 count++;
1529                 if ((count % 200) == 0) {
1530                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1531                                  "Tx queue is not empty for 20ms!\n");
1532                 }
1533                 if (count >= 1000) {
1534                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1535                                  "Wait for Tx FIFO empty timeout!\n");
1536                         break;
1537                 }
1538         }
1539
1540         /* TX pause
1541          * 3. reg 0x522=0xFF */
1542         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1543
1544         /* Wait TX State Machine OK
1545          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1546         count = 0;
1547         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1548                 udelay(100);
1549                 count++;
1550                 if (count >= 500) {
1551                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1552                                  "Wait for TX State Machine ready timeout !!\n");
1553                         break;
1554                 }
1555         }
1556
1557         /* stop RX DMA path
1558          * 5.   0x284[18] = 1
1559          * 6.   wait till 0x284[17] == 1
1560          * wait RX DMA idle */
1561         count = 0;
1562         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1563         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1564         do {
1565                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1566                 udelay(10);
1567                 count++;
1568         } while (!(tmp & BIT(1)) && count < 100);
1569
1570         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1571                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1572                   count, tmp);
1573
1574         /* reset BB
1575          * 7.   0x02 [0] = 0 */
1576         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1577         tmp &= ~(BIT(0));
1578         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1579
1580         /* Reset TRX MAC
1581          * 8.    0x100 = 0x00
1582          * Delay (1ms) */
1583         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1584         udelay(1000);
1585
1586         /* Disable MAC Security Engine
1587          * 9.   0x100 bit[9]=0 */
1588         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1589         tmp &= ~(BIT(1));
1590         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1591
1592         /* To avoid DD-Tim Circuit hang
1593          * 10.  0x553 bit[5]=1 */
1594         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1595         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1596
1597         /* Enable MAC Security Engine
1598          * 11.  0x100 bit[9]=1 */
1599         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1600         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1601
1602         /* Enable TRX MAC
1603          * 12.   0x100 = 0xFF
1604          *      Delay (1ms) */
1605         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1606         udelay(1000);
1607
1608         /* Enable BB
1609          * 13.  0x02 [0] = 1 */
1610         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1611         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1612
1613         /* beacon setting
1614          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1615         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1616         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1617         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1618
1619         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1620          * WMAC_LBK_BF_HD */
1621         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1622                        (u8)boundary);
1623
1624         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1625
1626         /* init LLT
1627          * 17. init LLT */
1628         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1629                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1630                          "Failed to init LLT table!\n");
1631                 return false;
1632         }
1633
1634         /* reallocate RQPN
1635          * 18. reallocate RQPN and init LLT */
1636         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1637         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1638
1639         /* release Tx pause
1640          * 19. 0x522=0x00 */
1641         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1642
1643         /* enable PCIE DMA
1644          * 20. 0x301[7:0] = 0x00
1645          * 21. 0x284[18] = 0 */
1646         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1647         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1648         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1649
1650         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1651         return ret;
1652 }
1653
1654 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1655 {
1656         struct rtl_priv *rtlpriv = rtl_priv(hw);
1657         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1658         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1659
1660 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1661         /* Re-download normal Fw. */
1662         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1663 #endif
1664
1665         /* Re-Initialize LLT table. */
1666         if (rtlhal->re_init_llt_table) {
1667                 u32 rqpn = 0x80e70808;
1668                 u8 rqpn_npq = 0, boundary = 0xF8;
1669                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1670                         rqpn = 0x80e90808;
1671                         boundary = 0xFA;
1672                 }
1673                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1674                         rtlhal->re_init_llt_table = false;
1675         }
1676
1677         ppsc->rfpwr_state = ERFON;
1678 }
1679
1680 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1681 {
1682         u8 tmp  = 0;
1683         struct rtl_priv *rtlpriv = rtl_priv(hw);
1684
1685         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1686
1687         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1688         if (!(tmp & (BIT(2) | BIT(3)))) {
1689                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1690                          "0x160(%#x)return!!\n", tmp);
1691                 return;
1692         }
1693
1694         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1695         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1696
1697         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1698         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1699
1700         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1701 }
1702
1703 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1704 {
1705         u8 tmp  = 0;
1706         struct rtl_priv *rtlpriv = rtl_priv(hw);
1707
1708         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1709
1710         /* Check 0x98[10] */
1711         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1712         if (!(tmp & BIT(2))) {
1713                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1714                          "<---0x99(%#x) return!!\n", tmp);
1715                 return;
1716         }
1717
1718         /* LTR idle latency, 0x90 for 144us */
1719         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1720
1721         /* LTR active latency, 0x3c for 60us */
1722         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1723
1724         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1725         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1726
1727         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1728         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1729         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1730
1731         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1732 }
1733
1734 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1735 {
1736         struct rtl_priv *rtlpriv = rtl_priv(hw);
1737         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1738         bool init_finished = true;
1739         u8 tmp = 0;
1740
1741         /* Get Fw wake up reason. */
1742         _rtl8821ae_get_wakeup_reason(hw);
1743
1744         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1745          * The root cause has not be found. */
1746         if (_rtl8821ae_check_pcie_dma_hang(hw))
1747                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1748
1749         /* Prepare Tx/Rx Desc Hw address. */
1750         _rtl8821ae_init_trx_desc_hw_address(hw);
1751
1752         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1753         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1754         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1755
1756         /* Check wake up event.
1757          * We should check wake packet bit before disable wowlan by H2C or
1758          * Fw will clear the bit. */
1759         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1760         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1761                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1762
1763         /* Set the WoWLAN related function control disable. */
1764         rtl8821ae_set_fw_wowlan_mode(hw, false);
1765         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1766
1767         if (rtlhal->hw_rof_enable) {
1768                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1769                 if (tmp & BIT(1)) {
1770                         /* Clear GPIO9 ISR */
1771                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1772                         init_finished = false;
1773                 } else {
1774                         init_finished = true;
1775                 }
1776         }
1777
1778         if (init_finished) {
1779                 _rtl8821ae_simple_initialize_adapter(hw);
1780
1781                 /* Release Pcie Interface Tx DMA. */
1782                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1783                 /* Release Pcie RX DMA */
1784                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1785
1786                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1787                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1788
1789                 _rtl8821ae_enable_l1off(hw);
1790                 _rtl8821ae_enable_ltr(hw);
1791         }
1792
1793         return init_finished;
1794 }
1795
1796 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1797 {
1798         /* BB OFDM RX Path_A */
1799         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1800         /* BB OFDM TX Path_A */
1801         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1802         /* BB CCK R/Rx Path_A */
1803         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1804         /* MCS support */
1805         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1806         /* RF Path_B HSSI OFF */
1807         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1808         /* RF Path_B Power Down */
1809         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1810         /* ADDA Path_B OFF */
1811         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1812         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1813 }
1814
1815 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1816 {
1817         struct rtl_priv *rtlpriv = rtl_priv(hw);
1818         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1819         u8 u1b_tmp;
1820
1821         rtlhal->mac_func_enable = false;
1822
1823         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1824                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1825                 /* 1. Run LPS WL RFOFF flow */
1826                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1827                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1828                 */
1829                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1830                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1831                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1832         }
1833         /* 2. 0x1F[7:0] = 0 */
1834         /* turn off RF */
1835         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1836         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1837                 rtlhal->fw_ready) {
1838                 rtl8821ae_firmware_selfreset(hw);
1839         }
1840
1841         /* Reset MCU. Suggested by Filen. */
1842         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1843         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1844
1845         /* g.   MCUFWDL 0x80[1:0]=0      */
1846         /* reset MCU ready status */
1847         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1848
1849         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1850                 /* HW card disable configuration. */
1851                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1852                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1853         } else {
1854                 /* HW card disable configuration. */
1855                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1856                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1857         }
1858
1859         /* Reset MCU IO Wrapper */
1860         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1861         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1862         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1863         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1864
1865         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1866         /* lock ISO/CLK/Power control register */
1867         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1868 }
1869
1870 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1871 {
1872         struct rtl_priv *rtlpriv = rtl_priv(hw);
1873         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1874         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1875         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1876         bool rtstatus = true;
1877         int err;
1878         u8 tmp_u1b;
1879         bool support_remote_wakeup;
1880         u32 nav_upper = WIFI_NAV_UPPER_US;
1881
1882         rtlhal->being_init_adapter = true;
1883         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1884                                       (u8 *)(&support_remote_wakeup));
1885         rtlpriv->intf_ops->disable_aspm(hw);
1886
1887         /*YP wowlan not considered*/
1888
1889         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1890         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1891                 rtlhal->mac_func_enable = true;
1892                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1893                          "MAC has already power on.\n");
1894         } else {
1895                 rtlhal->mac_func_enable = false;
1896                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1897         }
1898
1899         if (support_remote_wakeup &&
1900                 rtlhal->wake_from_pnp_sleep &&
1901                 rtlhal->mac_func_enable) {
1902                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1903                         rtlhal->being_init_adapter = false;
1904                         return 0;
1905                 }
1906         }
1907
1908         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1909                 _rtl8821ae_reset_pcie_interface_dma(hw,
1910                                                     rtlhal->mac_func_enable,
1911                                                     false);
1912                 rtlhal->mac_func_enable = false;
1913         }
1914
1915         /* Reset MAC/BB/RF status if it is not powered off
1916          * before calling initialize Hw flow to prevent
1917          * from interface and MAC status mismatch.
1918          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1919         if (rtlhal->mac_func_enable) {
1920                 _rtl8821ae_poweroff_adapter(hw);
1921                 rtlhal->mac_func_enable = false;
1922         }
1923
1924         rtstatus = _rtl8821ae_init_mac(hw);
1925         if (rtstatus != true) {
1926                 pr_err("Init MAC failed\n");
1927                 err = 1;
1928                 return err;
1929         }
1930
1931         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1932         tmp_u1b &= 0x7F;
1933         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1934
1935         err = rtl8821ae_download_fw(hw, false);
1936         if (err) {
1937                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1938                          "Failed to download FW. Init HW without FW now\n");
1939                 err = 1;
1940                 rtlhal->fw_ready = false;
1941                 return err;
1942         } else {
1943                 rtlhal->fw_ready = true;
1944         }
1945         ppsc->fw_current_inpsmode = false;
1946         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1947         rtlhal->fw_clk_change_in_progress = false;
1948         rtlhal->allow_sw_to_change_hwclc = false;
1949         rtlhal->last_hmeboxnum = 0;
1950
1951         /*SIC_Init(Adapter);
1952         if(rtlhal->AMPDUBurstMode)
1953                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1954
1955         rtl8821ae_phy_mac_config(hw);
1956         /* because last function modify RCR, so we update
1957          * rcr var here, or TP will unstable for receive_config
1958          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1959          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1960         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1961         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1962         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1963         rtl8821ae_phy_bb_config(hw);
1964
1965         rtl8821ae_phy_rf_config(hw);
1966
1967         if (rtlpriv->phy.rf_type == RF_1T1R &&
1968                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1969                 _rtl8812ae_bb8812_config_1t(hw);
1970
1971         _rtl8821ae_hw_configure(hw);
1972
1973         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1974
1975         /*set wireless mode*/
1976
1977         rtlhal->mac_func_enable = true;
1978
1979         rtl_cam_reset_all_entry(hw);
1980
1981         rtl8821ae_enable_hw_security_config(hw);
1982
1983         ppsc->rfpwr_state = ERFON;
1984
1985         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1986         _rtl8821ae_enable_aspm_back_door(hw);
1987         rtlpriv->intf_ops->enable_aspm(hw);
1988
1989         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1990             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1991                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1992
1993         rtl8821ae_bt_hw_init(hw);
1994         rtlpriv->rtlhal.being_init_adapter = false;
1995
1996         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1997
1998         /* rtl8821ae_dm_check_txpower_tracking(hw); */
1999         /* rtl8821ae_phy_lc_calibrate(hw); */
2000         if (support_remote_wakeup)
2001                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2002
2003         /* Release Rx DMA*/
2004         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2005         if (tmp_u1b & BIT(2)) {
2006                 /* Release Rx DMA if needed*/
2007                 tmp_u1b &= ~BIT(2);
2008                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2009         }
2010
2011         /* Release Tx/Rx PCIE DMA if*/
2012         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2013
2014         rtl8821ae_dm_init(hw);
2015         rtl8821ae_macid_initialize_mediastatus(hw);
2016
2017         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2018         return err;
2019 }
2020
2021 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2022 {
2023         struct rtl_priv *rtlpriv = rtl_priv(hw);
2024         struct rtl_phy *rtlphy = &rtlpriv->phy;
2025         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2026         enum version_8821ae version = VERSION_UNKNOWN;
2027         u32 value32;
2028
2029         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2030         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2031                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2032
2033         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2034                 rtlphy->rf_type = RF_2T2R;
2035         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2036                 rtlphy->rf_type = RF_1T1R;
2037
2038         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2039                  "RF_Type is %x!!\n", rtlphy->rf_type);
2040
2041         if (value32 & TRP_VAUX_EN) {
2042                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2043                         if (rtlphy->rf_type == RF_2T2R)
2044                                 version = VERSION_TEST_CHIP_2T2R_8812;
2045                         else
2046                                 version = VERSION_TEST_CHIP_1T1R_8812;
2047                 } else
2048                         version = VERSION_TEST_CHIP_8821;
2049         } else {
2050                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2051                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2052
2053                         if (rtlphy->rf_type == RF_2T2R)
2054                                 version =
2055                                         (enum version_8821ae)(CHIP_8812
2056                                         | NORMAL_CHIP |
2057                                         RF_TYPE_2T2R);
2058                         else
2059                                 version = (enum version_8821ae)(CHIP_8812
2060                                         | NORMAL_CHIP);
2061
2062                         version = (enum version_8821ae)(version | (rtl_id << 12));
2063                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2064                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2065
2066                         version = (enum version_8821ae)(CHIP_8821
2067                                 | NORMAL_CHIP | rtl_id);
2068                 }
2069         }
2070
2071         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2072                 /*WL_HWROF_EN.*/
2073                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2074                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2075         }
2076
2077         switch (version) {
2078         case VERSION_TEST_CHIP_1T1R_8812:
2079                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2080                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2081                 break;
2082         case VERSION_TEST_CHIP_2T2R_8812:
2083                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2084                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2085                 break;
2086         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2087                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2088                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2089                 break;
2090         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2091                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2092                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2093                 break;
2094         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2095                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2096                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2097                 break;
2098         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2099                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2100                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2101                 break;
2102         case VERSION_TEST_CHIP_8821:
2103                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2104                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2105                 break;
2106         case VERSION_NORMAL_TSMC_CHIP_8821:
2107                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2108                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2109                 break;
2110         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2111                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2112                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2113                 break;
2114         default:
2115                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2116                          "Chip Version ID: Unknown (0x%X)\n", version);
2117                 break;
2118         }
2119
2120         return version;
2121 }
2122
2123 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2124                                      enum nl80211_iftype type)
2125 {
2126         struct rtl_priv *rtlpriv = rtl_priv(hw);
2127         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2128         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2129         bt_msr &= 0xfc;
2130
2131         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2132         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2133                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2134
2135         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2136             type == NL80211_IFTYPE_STATION) {
2137                 _rtl8821ae_stop_tx_beacon(hw);
2138                 _rtl8821ae_enable_bcn_sub_func(hw);
2139         } else if (type == NL80211_IFTYPE_ADHOC ||
2140                 type == NL80211_IFTYPE_AP) {
2141                 _rtl8821ae_resume_tx_beacon(hw);
2142                 _rtl8821ae_disable_bcn_sub_func(hw);
2143         } else {
2144                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2145                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2146                          type);
2147         }
2148
2149         switch (type) {
2150         case NL80211_IFTYPE_UNSPECIFIED:
2151                 bt_msr |= MSR_NOLINK;
2152                 ledaction = LED_CTL_LINK;
2153                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2154                          "Set Network type to NO LINK!\n");
2155                 break;
2156         case NL80211_IFTYPE_ADHOC:
2157                 bt_msr |= MSR_ADHOC;
2158                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2159                          "Set Network type to Ad Hoc!\n");
2160                 break;
2161         case NL80211_IFTYPE_STATION:
2162                 bt_msr |= MSR_INFRA;
2163                 ledaction = LED_CTL_LINK;
2164                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165                          "Set Network type to STA!\n");
2166                 break;
2167         case NL80211_IFTYPE_AP:
2168                 bt_msr |= MSR_AP;
2169                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2170                          "Set Network type to AP!\n");
2171                 break;
2172         default:
2173                 pr_err("Network type %d not support!\n", type);
2174                 return 1;
2175         }
2176
2177         rtl_write_byte(rtlpriv, MSR, bt_msr);
2178         rtlpriv->cfg->ops->led_control(hw, ledaction);
2179         if ((bt_msr & MSR_MASK) == MSR_AP)
2180                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2181         else
2182                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2183
2184         return 0;
2185 }
2186
2187 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2188 {
2189         struct rtl_priv *rtlpriv = rtl_priv(hw);
2190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2191         u32 reg_rcr = rtlpci->receive_config;
2192
2193         if (rtlpriv->psc.rfpwr_state != ERFON)
2194                 return;
2195
2196         if (check_bssid) {
2197                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2198                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2199                                               (u8 *)(&reg_rcr));
2200                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2201         } else if (!check_bssid) {
2202                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2203                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2204                 rtlpriv->cfg->ops->set_hw_reg(hw,
2205                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2206         }
2207 }
2208
2209 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2210 {
2211         struct rtl_priv *rtlpriv = rtl_priv(hw);
2212
2213         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2214
2215         if (_rtl8821ae_set_media_status(hw, type))
2216                 return -EOPNOTSUPP;
2217
2218         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2219                 if (type != NL80211_IFTYPE_AP)
2220                         rtl8821ae_set_check_bssid(hw, true);
2221         } else {
2222                 rtl8821ae_set_check_bssid(hw, false);
2223         }
2224
2225         return 0;
2226 }
2227
2228 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2229 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2230 {
2231         struct rtl_priv *rtlpriv = rtl_priv(hw);
2232         rtl8821ae_dm_init_edca_turbo(hw);
2233         switch (aci) {
2234         case AC1_BK:
2235                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2236                 break;
2237         case AC0_BE:
2238                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2239                 break;
2240         case AC2_VI:
2241                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2242                 break;
2243         case AC3_VO:
2244                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2245                 break;
2246         default:
2247                 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2248                 break;
2249         }
2250 }
2251
2252 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2253 {
2254         struct rtl_priv *rtlpriv = rtl_priv(hw);
2255         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2256
2257         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2258
2259         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2260         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2261
2262         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2263         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2264 }
2265
2266 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2267 {
2268         struct rtl_priv *rtlpriv = rtl_priv(hw);
2269         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2270
2271         if (rtlpci->int_clear)
2272                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2273
2274         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2275         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2276         rtlpci->irq_enabled = true;
2277         /* there are some C2H CMDs have been sent before
2278         system interrupt is enabled, e.g., C2H, CPWM.
2279         *So we need to clear all C2H events that FW has
2280         notified, otherwise FW won't schedule any commands anymore.
2281         */
2282         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2283         /*enable system interrupt*/
2284         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2285 }
2286
2287 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2288 {
2289         struct rtl_priv *rtlpriv = rtl_priv(hw);
2290         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2291
2292         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2293         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2294         rtlpci->irq_enabled = false;
2295         /*synchronize_irq(rtlpci->pdev->irq);*/
2296 }
2297
2298 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2299 {
2300         struct rtl_priv *rtlpriv = rtl_priv(hw);
2301         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2302         u16 cap_hdr;
2303         u8 cap_pointer;
2304         u8 cap_id = 0xff;
2305         u8 pmcs_reg;
2306         u8 cnt = 0;
2307
2308         /* Get the Capability pointer first,
2309          * the Capability Pointer is located at
2310          * offset 0x34 from the Function Header */
2311
2312         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2313         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2314                  "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2315
2316         do {
2317                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2318                 cap_id = cap_hdr & 0xFF;
2319
2320                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2321                          "in pci configuration, cap_pointer%x = %x\n",
2322                           cap_pointer, cap_id);
2323
2324                 if (cap_id == 0x01) {
2325                         break;
2326                 } else {
2327                         /* point to next Capability */
2328                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2329                         /* 0: end of pci capability, 0xff: invalid value */
2330                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2331                                 cap_id = 0xff;
2332                                 break;
2333                         }
2334                 }
2335         } while (cnt++ < 200);
2336
2337         if (cap_id == 0x01) {
2338                 /* Get the PM CSR (Control/Status Register),
2339                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2340                  */
2341                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2342
2343                 if (pmcs_reg & BIT(7)) {
2344                         /* PME event occured, clear the PM_Status by write 1 */
2345                         pmcs_reg = pmcs_reg | BIT(7);
2346
2347                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2348                                               pmcs_reg);
2349                         /* Read it back to check */
2350                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2351                                              &pmcs_reg);
2352                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2353                                  "Clear PME status 0x%2x to 0x%2x\n",
2354                                   cap_pointer + 5, pmcs_reg);
2355                 } else {
2356                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2357                                  "PME status(0x%2x) = 0x%2x\n",
2358                                   cap_pointer + 5, pmcs_reg);
2359                 }
2360         } else {
2361                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2362                          "Cannot find PME Capability\n");
2363         }
2364 }
2365
2366 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2367 {
2368         struct rtl_priv *rtlpriv = rtl_priv(hw);
2369         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2370         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2371         struct rtl_mac *mac = rtl_mac(rtlpriv);
2372         enum nl80211_iftype opmode;
2373         bool support_remote_wakeup;
2374         u8 tmp;
2375         u32 count = 0;
2376
2377         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2378                                       (u8 *)(&support_remote_wakeup));
2379
2380         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2381
2382         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2383             || !rtlhal->enter_pnp_sleep) {
2384                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2385                 mac->link_state = MAC80211_NOLINK;
2386                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2387                 _rtl8821ae_set_media_status(hw, opmode);
2388                 _rtl8821ae_poweroff_adapter(hw);
2389         } else {
2390                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2391                 /* 3 <1> Prepare for configuring wowlan related infomations */
2392                 /* Clear Fw WoWLAN event. */
2393                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2394
2395 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2396                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2397 #endif
2398                 /* Dynamically adjust Tx packet boundary
2399                  * for download reserved page packet.
2400                  * reserve 30 pages for rsvd page */
2401                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2402                         rtlhal->re_init_llt_table = true;
2403
2404                 /* 3 <2> Set Fw releted H2C cmd. */
2405
2406                 /* Set WoWLAN related security information. */
2407                 rtl8821ae_set_fw_global_info_cmd(hw);
2408
2409                 _rtl8821ae_download_rsvd_page(hw, true);
2410
2411                 /* Just enable AOAC related functions when we connect to AP. */
2412                 printk("mac->link_state = %d\n", mac->link_state);
2413                 if (mac->link_state >= MAC80211_LINKED &&
2414                     mac->opmode == NL80211_IFTYPE_STATION) {
2415                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2416                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2417                                                               RT_MEDIA_CONNECT);
2418
2419                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2420                         /* Enable Fw Keep alive mechanism. */
2421                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2422
2423                         /* Enable disconnect decision control. */
2424                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2425                 }
2426
2427                 /* 3 <3> Hw Configutations */
2428
2429                 /* Wait untill Rx DMA Finished before host sleep.
2430                  * FW Pause Rx DMA may happens when received packet doing dma.
2431                  */
2432                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2433
2434                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2435                 count = 0;
2436                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2437                         udelay(10);
2438                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2439                 }
2440                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2441                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2442                           count);
2443
2444                 /* reset trx ring */
2445                 rtlpriv->intf_ops->reset_trx_ring(hw);
2446
2447                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2448
2449                 _rtl8821ae_clear_pci_pme_status(hw);
2450                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2451                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2452                 /* prevent 8051 to be reset by PERST */
2453                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2454                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2455         }
2456
2457         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2458             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2459                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2460         /* For wowlan+LPS+32k. */
2461         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2462                 /* Set the WoWLAN related function control enable.
2463                  * It should be the last H2C cmd in the WoWLAN flow. */
2464                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2465
2466                 /* Stop Pcie Interface Tx DMA. */
2467                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2468                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2469
2470                 /* Wait for TxDMA idle. */
2471                 count = 0;
2472                 do {
2473                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2474                         udelay(10);
2475                         count++;
2476                 } while ((tmp != 0) && (count < 100));
2477                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2478                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2479                           count);
2480
2481                 if (rtlhal->hw_rof_enable) {
2482                         printk("hw_rof_enable\n");
2483                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2484                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2485                 }
2486         }
2487         /* after power off we should do iqk again */
2488         rtlpriv->phy.iqk_initialized = false;
2489 }
2490
2491 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2492                                   u32 *p_inta, u32 *p_intb)
2493 {
2494         struct rtl_priv *rtlpriv = rtl_priv(hw);
2495         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2496
2497         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2498         rtl_write_dword(rtlpriv, ISR, *p_inta);
2499
2500         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2501         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2502 }
2503
2504 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2505 {
2506         struct rtl_priv *rtlpriv = rtl_priv(hw);
2507         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2508         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2509         u16 bcn_interval, atim_window;
2510
2511         bcn_interval = mac->beacon_interval;
2512         atim_window = 2;        /*FIX MERGE */
2513         rtl8821ae_disable_interrupt(hw);
2514         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2515         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2516         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2517         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2518         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2519         rtl_write_byte(rtlpriv, 0x606, 0x30);
2520         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2521         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2522         rtl8821ae_enable_interrupt(hw);
2523 }
2524
2525 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2526 {
2527         struct rtl_priv *rtlpriv = rtl_priv(hw);
2528         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2529         u16 bcn_interval = mac->beacon_interval;
2530
2531         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2532                  "beacon_interval:%d\n", bcn_interval);
2533         rtl8821ae_disable_interrupt(hw);
2534         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2535         rtl8821ae_enable_interrupt(hw);
2536 }
2537
2538 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2539                                    u32 add_msr, u32 rm_msr)
2540 {
2541         struct rtl_priv *rtlpriv = rtl_priv(hw);
2542         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2543
2544         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2545                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2546
2547         if (add_msr)
2548                 rtlpci->irq_mask[0] |= add_msr;
2549         if (rm_msr)
2550                 rtlpci->irq_mask[0] &= (~rm_msr);
2551         rtl8821ae_disable_interrupt(hw);
2552         rtl8821ae_enable_interrupt(hw);
2553 }
2554
2555 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2556 {
2557         u8 group = 0;
2558
2559         if (chnl <= 14) {
2560                 if (1 <= chnl && chnl <= 2)
2561                         group = 0;
2562         else if (3 <= chnl && chnl <= 5)
2563                         group = 1;
2564         else if (6 <= chnl && chnl <= 8)
2565                         group = 2;
2566         else if (9 <= chnl && chnl <= 11)
2567                         group = 3;
2568         else /*if (12 <= chnl && chnl <= 14)*/
2569                         group = 4;
2570         } else {
2571                 if (36 <= chnl && chnl <= 42)
2572                         group = 0;
2573         else if (44 <= chnl && chnl <= 48)
2574                         group = 1;
2575         else if (50 <= chnl && chnl <= 58)
2576                         group = 2;
2577         else if (60 <= chnl && chnl <= 64)
2578                         group = 3;
2579         else if (100 <= chnl && chnl <= 106)
2580                         group = 4;
2581         else if (108 <= chnl && chnl <= 114)
2582                         group = 5;
2583         else if (116 <= chnl && chnl <= 122)
2584                         group = 6;
2585         else if (124 <= chnl && chnl <= 130)
2586                         group = 7;
2587         else if (132 <= chnl && chnl <= 138)
2588                         group = 8;
2589         else if (140 <= chnl && chnl <= 144)
2590                         group = 9;
2591         else if (149 <= chnl && chnl <= 155)
2592                         group = 10;
2593         else if (157 <= chnl && chnl <= 161)
2594                         group = 11;
2595         else if (165 <= chnl && chnl <= 171)
2596                         group = 12;
2597         else if (173 <= chnl && chnl <= 177)
2598                         group = 13;
2599         else
2600                 WARN_ONCE(true,
2601                           "rtl8821ae: 5G, Channel %d in Group not found\n",
2602                           chnl);
2603         }
2604         return group;
2605 }
2606
2607 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2608         struct txpower_info_2g *pwrinfo24g,
2609         struct txpower_info_5g *pwrinfo5g,
2610         bool autoload_fail,
2611         u8 *hwinfo)
2612 {
2613         struct rtl_priv *rtlpriv = rtl_priv(hw);
2614         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2615
2616         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2617                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2618                  (eeAddr+1), hwinfo[eeAddr+1]);
2619         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2620                 autoload_fail = true;
2621
2622         if (autoload_fail) {
2623                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2624                          "auto load fail : Use Default value!\n");
2625                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2626                         /*2.4G default value*/
2627                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2628                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2629                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2630                         }
2631                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2632                                 if (TxCount == 0) {
2633                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2634                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2635                                 } else {
2636                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2637                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2638                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2639                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2640                                 }
2641                         }
2642                         /*5G default value*/
2643                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2644                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2645
2646                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2647                                 if (TxCount == 0) {
2648                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2649                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2650                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2651                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2652                                 } else {
2653                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2654                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2655                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2656                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2657                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2658                                 }
2659                         }
2660                 }
2661                 return;
2662         }
2663
2664         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2665
2666         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2667                 /*2.4G default value*/
2668                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2669                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2670                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2671                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2672                 }
2673                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2674                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2675                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2676                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2677                 }
2678                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2679                         if (TxCount == 0) {
2680                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2681                                 /*bit sign number to 8 bit sign number*/
2682                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2683                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2684                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2685                                 /*bit sign number to 8 bit sign number*/
2686                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2687                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2688                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2689
2690                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2691                                 eeAddr++;
2692                         } else {
2693                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2694                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2695                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2696
2697                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2698                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2699                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2700
2701                                 eeAddr++;
2702
2703                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2704                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2705                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2706
2707                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2708                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2709                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2710
2711                                 eeAddr++;
2712                         }
2713                 }
2714
2715                 /*5G default value*/
2716                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2717                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2718                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2719                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2720                 }
2721
2722                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2723                         if (TxCount == 0) {
2724                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2725
2726                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2727                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2728                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2729
2730                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2731                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2732                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2733
2734                                 eeAddr++;
2735                         } else {
2736                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2737                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2738                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2739
2740                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2741                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2742                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2743
2744                                 eeAddr++;
2745                         }
2746                 }
2747
2748                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2749                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2750
2751                 eeAddr++;
2752
2753                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2754
2755                 eeAddr++;
2756
2757                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2758                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2759                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2760                 }
2761                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2762                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2763                         /* 4bit sign number to 8 bit sign number */
2764                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2765                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2766                         /* 4bit sign number to 8 bit sign number */
2767                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2768                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2769                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2770
2771                         eeAddr++;
2772                 }
2773         }
2774 }
2775 #if 0
2776 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2777                                                  bool autoload_fail,
2778                                                  u8 *hwinfo)
2779 {
2780         struct rtl_priv *rtlpriv = rtl_priv(hw);
2781         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2782         struct txpower_info_2g pwrinfo24g;
2783         struct txpower_info_5g pwrinfo5g;
2784         u8 rf_path, index;
2785         u8 i;
2786
2787         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2788                                         &pwrinfo5g, autoload_fail, hwinfo);
2789
2790         for (rf_path = 0; rf_path < 2; rf_path++) {
2791                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2792                         index = _rtl8821ae_get_chnl_group(i + 1);
2793
2794                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2795                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2796                                         pwrinfo24g.index_cck_base[rf_path][5];
2797                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2798                                         pwrinfo24g.index_bw40_base[rf_path][index];
2799                         } else {
2800                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2801                                         pwrinfo24g.index_cck_base[rf_path][index];
2802                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2803                                         pwrinfo24g.index_bw40_base[rf_path][index];
2804                         }
2805                 }
2806
2807                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2808                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2809                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2810                                         pwrinfo5g.index_bw40_base[rf_path][index];
2811                 }
2812                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2813                         u8 upper, lower;
2814                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2815                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2816                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2817
2818                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2819                 }
2820                 for (i = 0; i < MAX_TX_COUNT; i++) {
2821                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2822                                 pwrinfo24g.cck_diff[rf_path][i];
2823                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2824                                 pwrinfo24g.ofdm_diff[rf_path][i];
2825                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2826                                 pwrinfo24g.bw20_diff[rf_path][i];
2827                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2828                                 pwrinfo24g.bw40_diff[rf_path][i];
2829
2830                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2831                                 pwrinfo5g.ofdm_diff[rf_path][i];
2832                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2833                                 pwrinfo5g.bw20_diff[rf_path][i];
2834                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2835                                 pwrinfo5g.bw40_diff[rf_path][i];
2836                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2837                                 pwrinfo5g.bw80_diff[rf_path][i];
2838                 }
2839         }
2840
2841         if (!autoload_fail) {
2842                 rtlefuse->eeprom_regulatory =
2843                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2844                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2845                         rtlefuse->eeprom_regulatory = 0;
2846         } else {
2847                 rtlefuse->eeprom_regulatory = 0;
2848         }
2849
2850         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2851         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2852 }
2853 #endif
2854 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2855                                                  bool autoload_fail,
2856                                                  u8 *hwinfo)
2857 {
2858         struct rtl_priv *rtlpriv = rtl_priv(hw);
2859         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2860         struct txpower_info_2g pwrinfo24g;
2861         struct txpower_info_5g pwrinfo5g;
2862         u8 rf_path, index;
2863         u8 i;
2864
2865         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2866                 &pwrinfo5g, autoload_fail, hwinfo);
2867
2868         for (rf_path = 0; rf_path < 2; rf_path++) {
2869                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2870                         index = _rtl8821ae_get_chnl_group(i + 1);
2871
2872                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2873                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2874                                         pwrinfo24g.index_cck_base[rf_path][5];
2875                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2876                                         pwrinfo24g.index_bw40_base[rf_path][index];
2877                         } else {
2878                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2879                                         pwrinfo24g.index_cck_base[rf_path][index];
2880                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2881                                         pwrinfo24g.index_bw40_base[rf_path][index];
2882                         }
2883                 }
2884
2885                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2886                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2887                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2888                                 pwrinfo5g.index_bw40_base[rf_path][index];
2889                 }
2890                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2891                         u8 upper, lower;
2892                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2893                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2894                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2895
2896                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2897                 }
2898                 for (i = 0; i < MAX_TX_COUNT; i++) {
2899                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2900                                 pwrinfo24g.cck_diff[rf_path][i];
2901                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2902                                 pwrinfo24g.ofdm_diff[rf_path][i];
2903                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2904                                 pwrinfo24g.bw20_diff[rf_path][i];
2905                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2906                                 pwrinfo24g.bw40_diff[rf_path][i];
2907
2908                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2909                                 pwrinfo5g.ofdm_diff[rf_path][i];
2910                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2911                                 pwrinfo5g.bw20_diff[rf_path][i];
2912                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2913                                 pwrinfo5g.bw40_diff[rf_path][i];
2914                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2915                                 pwrinfo5g.bw80_diff[rf_path][i];
2916                 }
2917         }
2918         /*bit0~2*/
2919         if (!autoload_fail) {
2920                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2921                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2922                         rtlefuse->eeprom_regulatory = 0;
2923         } else {
2924                 rtlefuse->eeprom_regulatory = 0;
2925         }
2926
2927         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2928         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2929 }
2930
2931 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2932                                     bool autoload_fail)
2933 {
2934         struct rtl_priv *rtlpriv = rtl_priv(hw);
2935         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2936
2937         if (!autoload_fail) {
2938                 rtlhal->pa_type_2g = hwinfo[0xBC];
2939                 rtlhal->lna_type_2g = hwinfo[0xBD];
2940                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2941                         rtlhal->pa_type_2g = 0;
2942                         rtlhal->lna_type_2g = 0;
2943                 }
2944                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2945                                           (rtlhal->pa_type_2g & BIT(4))) ?
2946                                          1 : 0;
2947                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2948                                            (rtlhal->lna_type_2g & BIT(3))) ?
2949                                           1 : 0;
2950
2951                 rtlhal->pa_type_5g = hwinfo[0xBC];
2952                 rtlhal->lna_type_5g = hwinfo[0xBF];
2953                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2954                         rtlhal->pa_type_5g = 0;
2955                         rtlhal->lna_type_5g = 0;
2956                 }
2957                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2958                                           (rtlhal->pa_type_5g & BIT(0))) ?
2959                                          1 : 0;
2960                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2961                                            (rtlhal->lna_type_5g & BIT(3))) ?
2962                                           1 : 0;
2963         } else {
2964                 rtlhal->external_pa_2g  = 0;
2965                 rtlhal->external_lna_2g = 0;
2966                 rtlhal->external_pa_5g  = 0;
2967                 rtlhal->external_lna_5g = 0;
2968         }
2969 }
2970
2971 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
2972                                            bool autoload_fail)
2973 {
2974         struct rtl_priv *rtlpriv = rtl_priv(hw);
2975         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2976
2977         u8 ext_type_pa_2g_a  = (hwinfo[0xBD] & BIT(2))      >> 2; /* 0xBD[2] */
2978         u8 ext_type_pa_2g_b  = (hwinfo[0xBD] & BIT(6))      >> 6; /* 0xBD[6] */
2979         u8 ext_type_pa_5g_a  = (hwinfo[0xBF] & BIT(2))      >> 2; /* 0xBF[2] */
2980         u8 ext_type_pa_5g_b  = (hwinfo[0xBF] & BIT(6))      >> 6; /* 0xBF[6] */
2981         /* 0xBD[1:0] */
2982         u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0;
2983         /* 0xBD[5:4] */
2984         u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4;
2985         /* 0xBF[1:0] */
2986         u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0;
2987         /* 0xBF[5:4] */
2988         u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4;
2989
2990         _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
2991
2992         /* [2.4G] Path A and B are both extPA */
2993         if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
2994                 rtlhal->type_gpa  = ext_type_pa_2g_b  << 2 | ext_type_pa_2g_a;
2995
2996         /* [5G] Path A and B are both extPA */
2997         if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
2998                 rtlhal->type_apa  = ext_type_pa_5g_b  << 2 | ext_type_pa_5g_a;
2999
3000         /* [2.4G] Path A and B are both extLNA */
3001         if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
3002                 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
3003
3004         /* [5G] Path A and B are both extLNA */
3005         if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
3006                 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
3007 }
3008
3009 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
3010                                     bool autoload_fail)
3011 {
3012         struct rtl_priv *rtlpriv = rtl_priv(hw);
3013         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3014
3015         if (!autoload_fail) {
3016                 rtlhal->pa_type_2g = hwinfo[0xBC];
3017                 rtlhal->lna_type_2g = hwinfo[0xBD];
3018                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3019                         rtlhal->pa_type_2g = 0;
3020                         rtlhal->lna_type_2g = 0;
3021                 }
3022                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3023                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3024
3025                 rtlhal->pa_type_5g = hwinfo[0xBC];
3026                 rtlhal->lna_type_5g = hwinfo[0xBF];
3027                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3028                         rtlhal->pa_type_5g = 0;
3029                         rtlhal->lna_type_5g = 0;
3030                 }
3031                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3032                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3033         } else {
3034                 rtlhal->external_pa_2g  = 0;
3035                 rtlhal->external_lna_2g = 0;
3036                 rtlhal->external_pa_5g  = 0;
3037                 rtlhal->external_lna_5g = 0;
3038         }
3039 }
3040
3041 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3042                               bool autoload_fail)
3043 {
3044         struct rtl_priv *rtlpriv = rtl_priv(hw);
3045         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3046
3047         if (!autoload_fail) {
3048                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3049                         if (rtlhal->external_lna_5g) {
3050                                 if (rtlhal->external_pa_5g) {
3051                                         if (rtlhal->external_lna_2g &&
3052                                             rtlhal->external_pa_2g)
3053                                                 rtlhal->rfe_type = 3;
3054                                         else
3055                                                 rtlhal->rfe_type = 0;
3056                                 } else {
3057                                         rtlhal->rfe_type = 2;
3058                                 }
3059                         } else {
3060                                 rtlhal->rfe_type = 4;
3061                         }
3062                 } else {
3063                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3064
3065                         if (rtlhal->rfe_type == 4 &&
3066                             (rtlhal->external_pa_5g ||
3067                              rtlhal->external_pa_2g ||
3068                              rtlhal->external_lna_5g ||
3069                              rtlhal->external_lna_2g)) {
3070                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3071                                         rtlhal->rfe_type = 2;
3072                         }
3073                 }
3074         } else {
3075                 rtlhal->rfe_type = 0x04;
3076         }
3077
3078         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3079                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3080 }
3081
3082 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3083                                               bool auto_load_fail, u8 *hwinfo)
3084 {
3085         struct rtl_priv *rtlpriv = rtl_priv(hw);
3086         u8 value;
3087
3088         if (!auto_load_fail) {
3089                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3090                 if (((value & 0xe0) >> 5) == 0x1)
3091                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3092                 else
3093                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3094                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3095
3096                 value = hwinfo[EEPROM_RF_BT_SETTING];
3097                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3098         } else {
3099                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3100                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3101                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3102         }
3103         /*move BT_InitHalVars() to init_sw_vars*/
3104 }
3105
3106 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3107                                               bool auto_load_fail, u8 *hwinfo)
3108 {
3109         struct rtl_priv *rtlpriv = rtl_priv(hw);
3110         u8 value;
3111         u32 tmpu_32;
3112
3113         if (!auto_load_fail) {
3114                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3115                 if (tmpu_32 & BIT(18))
3116                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3117                 else
3118                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3119                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3120
3121                 value = hwinfo[EEPROM_RF_BT_SETTING];
3122                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3123         } else {
3124                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3125                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3126                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3127         }
3128         /*move BT_InitHalVars() to init_sw_vars*/
3129 }
3130
3131 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3132 {
3133         struct rtl_priv *rtlpriv = rtl_priv(hw);
3134         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3135         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3136         int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3137                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3138                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3139                         COUNTRY_CODE_WORLD_WIDE_13};
3140         u8 *hwinfo;
3141
3142         if (b_pseudo_test) {
3143                 ;/* need add */
3144         }
3145
3146         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3147         if (!hwinfo)
3148                 return;
3149
3150         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3151                 goto exit;
3152
3153         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3154                                                hwinfo);
3155
3156         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3157                 _rtl8812ae_read_amplifier_type(hw, hwinfo,
3158                                                rtlefuse->autoload_failflag);
3159                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3160                                 rtlefuse->autoload_failflag, hwinfo);
3161         } else {
3162                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3163                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3164                                 rtlefuse->autoload_failflag, hwinfo);
3165         }
3166
3167         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3168         /*board type*/
3169         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3170         if (rtlhal->external_lna_2g != 0)
3171                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3172         if (rtlhal->external_lna_5g != 0)
3173                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3174         if (rtlhal->external_pa_2g != 0)
3175                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3176         if (rtlhal->external_pa_5g != 0)
3177                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3178
3179         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3180                 rtlefuse->board_type |= ODM_BOARD_BT;
3181
3182         rtlhal->board_type = rtlefuse->board_type;
3183         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3184                  "board_type = 0x%x\n", rtlefuse->board_type);
3185
3186         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3187         if (rtlefuse->eeprom_channelplan == 0xff)
3188                 rtlefuse->eeprom_channelplan = 0x7F;
3189
3190         /* set channel plan from efuse */
3191         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3192
3193         /*parse xtal*/
3194         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3195         if (rtlefuse->crystalcap == 0xFF)
3196                 rtlefuse->crystalcap = 0x20;
3197
3198         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3199         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3200             rtlefuse->autoload_failflag) {
3201                 rtlefuse->apk_thermalmeterignore = true;
3202                 rtlefuse->eeprom_thermalmeter = 0xff;
3203         }
3204
3205         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3206         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3207                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3208
3209         if (!rtlefuse->autoload_failflag) {
3210                 rtlefuse->antenna_div_cfg =
3211                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3212                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3213                         rtlefuse->antenna_div_cfg = 0;
3214
3215                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3216                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3217                         rtlefuse->antenna_div_cfg = 0;
3218
3219                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3220                 if (rtlefuse->antenna_div_type == 0xff)
3221                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3222         } else {
3223                 rtlefuse->antenna_div_cfg = 0;
3224                 rtlefuse->antenna_div_type = 0;
3225         }
3226
3227         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3228                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3229                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3230
3231         rtlpriv->ledctl.led_opendrain = true;
3232
3233         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3234                 switch (rtlefuse->eeprom_oemid) {
3235                 case RT_CID_DEFAULT:
3236                         break;
3237                 case EEPROM_CID_TOSHIBA:
3238                         rtlhal->oem_id = RT_CID_TOSHIBA;
3239                         break;
3240                 case EEPROM_CID_CCX:
3241                         rtlhal->oem_id = RT_CID_CCX;
3242                         break;
3243                 case EEPROM_CID_QMI:
3244                         rtlhal->oem_id = RT_CID_819X_QMI;
3245                         break;
3246                 case EEPROM_CID_WHQL:
3247                         break;
3248                 default:
3249                         break;
3250                 }
3251         }
3252 exit:
3253         kfree(hwinfo);
3254 }
3255
3256 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3257 {
3258         struct rtl_priv *rtlpriv = rtl_priv(hw);
3259         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3260         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3261
3262         rtlpriv->ledctl.led_opendrain = true;
3263         switch (rtlhal->oem_id) {
3264         case RT_CID_819X_HP:
3265                 rtlpriv->ledctl.led_opendrain = true;
3266                 break;
3267         case RT_CID_819X_LENOVO:
3268         case RT_CID_DEFAULT:
3269         case RT_CID_TOSHIBA:
3270         case RT_CID_CCX:
3271         case RT_CID_819X_ACER:
3272         case RT_CID_WHQL:
3273         default:
3274                 break;
3275         }
3276         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3277                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3278 }*/
3279
3280 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3281 {
3282         struct rtl_priv *rtlpriv = rtl_priv(hw);
3283         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3284         struct rtl_phy *rtlphy = &rtlpriv->phy;
3285         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3286         u8 tmp_u1b;
3287
3288         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3289         if (get_rf_type(rtlphy) == RF_1T1R)
3290                 rtlpriv->dm.rfpath_rxenable[0] = true;
3291         else
3292                 rtlpriv->dm.rfpath_rxenable[0] =
3293                     rtlpriv->dm.rfpath_rxenable[1] = true;
3294         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3295                                                 rtlhal->version);
3296
3297         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3298         if (tmp_u1b & BIT(4)) {
3299                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3300                 rtlefuse->epromtype = EEPROM_93C46;
3301         } else {
3302                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3303                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3304         }
3305
3306         if (tmp_u1b & BIT(5)) {
3307                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3308                 rtlefuse->autoload_failflag = false;
3309                 _rtl8821ae_read_adapter_info(hw, false);
3310         } else {
3311                 pr_err("Autoload ERR!!\n");
3312         }
3313         /*hal_ReadRFType_8812A()*/
3314         /* _rtl8821ae_hal_customized_behavior(hw); */
3315 }
3316
3317 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3318                 struct ieee80211_sta *sta)
3319 {
3320         struct rtl_priv *rtlpriv = rtl_priv(hw);
3321         struct rtl_phy *rtlphy = &rtlpriv->phy;
3322         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3323         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3324         u32 ratr_value;
3325         u8 ratr_index = 0;
3326         u8 b_nmode = mac->ht_enable;
3327         u8 mimo_ps = IEEE80211_SMPS_OFF;
3328         u16 shortgi_rate;
3329         u32 tmp_ratr_value;
3330         u8 curtxbw_40mhz = mac->bw_40;
3331         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3332                                 1 : 0;
3333         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3334                                 1 : 0;
3335         enum wireless_mode wirelessmode = mac->mode;
3336
3337         if (rtlhal->current_bandtype == BAND_ON_5G)
3338                 ratr_value = sta->supp_rates[1] << 4;
3339         else
3340                 ratr_value = sta->supp_rates[0];
3341         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3342                 ratr_value = 0xfff;
3343         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3344                         sta->ht_cap.mcs.rx_mask[0] << 12);
3345         switch (wirelessmode) {
3346         case WIRELESS_MODE_B:
3347                 if (ratr_value & 0x0000000c)
3348                         ratr_value &= 0x0000000d;
3349                 else
3350                         ratr_value &= 0x0000000f;
3351                 break;
3352         case WIRELESS_MODE_G:
3353                 ratr_value &= 0x00000FF5;
3354                 break;
3355         case WIRELESS_MODE_N_24G:
3356         case WIRELESS_MODE_N_5G:
3357                 b_nmode = 1;
3358                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3359                         ratr_value &= 0x0007F005;
3360                 } else {
3361                         u32 ratr_mask;
3362
3363                         if (get_rf_type(rtlphy) == RF_1T2R ||
3364                             get_rf_type(rtlphy) == RF_1T1R)
3365                                 ratr_mask = 0x000ff005;
3366                         else
3367                                 ratr_mask = 0x0f0ff005;
3368
3369                         ratr_value &= ratr_mask;
3370                 }
3371                 break;
3372         default:
3373                 if (rtlphy->rf_type == RF_1T2R)
3374                         ratr_value &= 0x000ff0ff;
3375                 else
3376                         ratr_value &= 0x0f0ff0ff;
3377
3378                 break;
3379         }
3380
3381         if ((rtlpriv->btcoexist.bt_coexistence) &&
3382              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3383              (rtlpriv->btcoexist.bt_cur_state) &&
3384              (rtlpriv->btcoexist.bt_ant_isolation) &&
3385              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3386              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3387                 ratr_value &= 0x0fffcfc0;
3388         else
3389                 ratr_value &= 0x0FFFFFFF;
3390
3391         if (b_nmode && ((curtxbw_40mhz &&
3392                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3393                                                  b_curshortgi_20mhz))) {
3394                 ratr_value |= 0x10000000;
3395                 tmp_ratr_value = (ratr_value >> 12);
3396
3397                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3398                         if ((1 << shortgi_rate) & tmp_ratr_value)
3399                                 break;
3400                 }
3401
3402                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3403                     (shortgi_rate << 4) | (shortgi_rate);
3404         }
3405
3406         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3407
3408         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3409                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3410 }
3411
3412 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3413         struct ieee80211_hw *hw, u8 rate_index,
3414         enum wireless_mode wirelessmode)
3415 {
3416         struct rtl_priv *rtlpriv = rtl_priv(hw);
3417         struct rtl_phy *rtlphy = &rtlpriv->phy;
3418         u8 ret = 0;
3419         switch (rate_index) {
3420         case RATR_INX_WIRELESS_NGB:
3421                 if (rtlphy->rf_type == RF_1T1R)
3422                         ret = 1;
3423                 else
3424                         ret = 0;
3425                 ; break;
3426         case RATR_INX_WIRELESS_N:
3427         case RATR_INX_WIRELESS_NG:
3428                 if (rtlphy->rf_type == RF_1T1R)
3429                         ret = 5;
3430                 else
3431                         ret = 4;
3432                 ; break;
3433         case RATR_INX_WIRELESS_NB:
3434                 if (rtlphy->rf_type == RF_1T1R)
3435                         ret = 3;
3436                 else
3437                         ret = 2;
3438                 ; break;
3439         case RATR_INX_WIRELESS_GB:
3440                 ret = 6;
3441                 break;
3442         case RATR_INX_WIRELESS_G:
3443                 ret = 7;
3444                 break;
3445         case RATR_INX_WIRELESS_B:
3446                 ret = 8;
3447                 break;
3448         case RATR_INX_WIRELESS_MC:
3449                 if ((wirelessmode == WIRELESS_MODE_B)
3450                         || (wirelessmode == WIRELESS_MODE_G)
3451                         || (wirelessmode == WIRELESS_MODE_N_24G)
3452                         || (wirelessmode == WIRELESS_MODE_AC_24G))
3453                         ret = 6;
3454                 else
3455                         ret = 7;
3456         case RATR_INX_WIRELESS_AC_5N:
3457                 if (rtlphy->rf_type == RF_1T1R)
3458                         ret = 10;
3459                 else
3460                         ret = 9;
3461                 break;
3462         case RATR_INX_WIRELESS_AC_24N:
3463                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3464                         if (rtlphy->rf_type == RF_1T1R)
3465                                 ret = 10;
3466                         else
3467                                 ret = 9;
3468                 } else {
3469                         if (rtlphy->rf_type == RF_1T1R)
3470                                 ret = 11;
3471                         else
3472                                 ret = 12;
3473                 }
3474                 break;
3475         default:
3476                 ret = 0; break;
3477         }
3478         return ret;
3479 }
3480
3481 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3482 {
3483         u8 i, j, tmp_rate;
3484         u32 rate_bitmap = 0;
3485
3486         for (i = j = 0; i < 4; i += 2, j += 10) {
3487                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3488
3489                 switch (tmp_rate) {
3490                 case 2:
3491                         rate_bitmap = rate_bitmap | (0x03ff << j);
3492                         break;
3493                 case 1:
3494                         rate_bitmap = rate_bitmap | (0x01ff << j);
3495                         break;
3496                 case 0:
3497                         rate_bitmap = rate_bitmap | (0x00ff << j);
3498                         break;
3499                 default:
3500                         break;
3501                 }
3502         }
3503
3504         return rate_bitmap;
3505 }
3506
3507 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3508                                              enum wireless_mode wirelessmode,
3509                                              u32 ratr_bitmap)
3510 {
3511         struct rtl_priv *rtlpriv = rtl_priv(hw);
3512         struct rtl_phy *rtlphy = &rtlpriv->phy;
3513         u32 ret_bitmap = ratr_bitmap;
3514
3515         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3516                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3517                 ret_bitmap = ratr_bitmap;
3518         else if (wirelessmode == WIRELESS_MODE_AC_5G
3519                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3520                 if (rtlphy->rf_type == RF_1T1R)
3521                         ret_bitmap = ratr_bitmap & (~BIT21);
3522                 else
3523                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3524         }
3525
3526         return ret_bitmap;
3527 }
3528
3529 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3530                         u32 ratr_bitmap)
3531 {
3532         u8 ret = 0;
3533         if (wirelessmode < WIRELESS_MODE_N_24G)
3534                 ret =  0;
3535         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3536                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3537                         ret = 3;
3538                 else                                    /* Mix, 1SS */
3539                         ret = 2;
3540         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3541                         ret = 1;
3542         } /* VHT */
3543
3544         return ret << 4;
3545 }
3546
3547 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3548                              u8 mac_id, struct rtl_sta_info *sta_entry,
3549                              enum wireless_mode wirelessmode)
3550 {
3551         u8 b_ldpc = 0;
3552         /*not support ldpc, do not open*/
3553         return b_ldpc << 2;
3554 }
3555
3556 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3557                           enum wireless_mode wirelessmode,
3558                           u32 ratr_bitmap)
3559 {
3560         struct rtl_priv *rtlpriv = rtl_priv(hw);
3561         struct rtl_phy *rtlphy = &rtlpriv->phy;
3562         u8 rf_type = RF_1T1R;
3563
3564         if (rtlphy->rf_type == RF_1T1R)
3565                 rf_type = RF_1T1R;
3566         else if (wirelessmode == WIRELESS_MODE_AC_5G
3567                 || wirelessmode == WIRELESS_MODE_AC_24G
3568                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3569                 if (ratr_bitmap & 0xffc00000)
3570                         rf_type = RF_2T2R;
3571         } else if (wirelessmode == WIRELESS_MODE_N_5G
3572                 || wirelessmode == WIRELESS_MODE_N_24G) {
3573                 if (ratr_bitmap & 0xfff00000)
3574                         rf_type = RF_2T2R;
3575         }
3576
3577         return rf_type;
3578 }
3579
3580 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3581                               u8 mac_id)
3582 {
3583         bool b_short_gi = false;
3584         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3585                                 1 : 0;
3586         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3587                                 1 : 0;
3588         u8 b_curshortgi_80mhz = 0;
3589         b_curshortgi_80mhz = (sta->vht_cap.cap &
3590                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3591
3592         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3593                         b_short_gi = false;
3594
3595         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3596                 || b_curshortgi_20mhz)
3597                 b_short_gi = true;
3598
3599         return b_short_gi;
3600 }
3601
3602 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3603                 struct ieee80211_sta *sta, u8 rssi_level)
3604 {
3605         struct rtl_priv *rtlpriv = rtl_priv(hw);
3606         struct rtl_phy *rtlphy = &rtlpriv->phy;
3607         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3608         struct rtl_sta_info *sta_entry = NULL;
3609         u32 ratr_bitmap;
3610         u8 ratr_index;
3611         enum wireless_mode wirelessmode = 0;
3612         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3613                                 ? 1 : 0;
3614         bool b_shortgi = false;
3615         u8 rate_mask[7];
3616         u8 macid = 0;
3617         u8 mimo_ps = IEEE80211_SMPS_OFF;
3618         u8 rf_type;
3619
3620         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3621         wirelessmode = sta_entry->wireless_mode;
3622
3623         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3624                  "wireless mode = 0x%x\n", wirelessmode);
3625         if (mac->opmode == NL80211_IFTYPE_STATION ||
3626                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3627                 curtxbw_40mhz = mac->bw_40;
3628         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3629                 mac->opmode == NL80211_IFTYPE_ADHOC)
3630                 macid = sta->aid + 1;
3631         if (wirelessmode == WIRELESS_MODE_N_5G ||
3632             wirelessmode == WIRELESS_MODE_AC_5G ||
3633             wirelessmode == WIRELESS_MODE_A)
3634                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3635         else
3636                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3637
3638         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3639                 ratr_bitmap = 0xfff;
3640
3641         if (wirelessmode == WIRELESS_MODE_N_24G
3642                 || wirelessmode == WIRELESS_MODE_N_5G)
3643                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3644                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3645         else if (wirelessmode == WIRELESS_MODE_AC_24G
3646                 || wirelessmode == WIRELESS_MODE_AC_5G
3647                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3648                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3649                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3650
3651         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3652         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3653
3654 /*mac id owner*/
3655         switch (wirelessmode) {
3656         case WIRELESS_MODE_B:
3657                 ratr_index = RATR_INX_WIRELESS_B;
3658                 if (ratr_bitmap & 0x0000000c)
3659                         ratr_bitmap &= 0x0000000d;
3660                 else
3661                         ratr_bitmap &= 0x0000000f;
3662                 break;
3663         case WIRELESS_MODE_G:
3664                 ratr_index = RATR_INX_WIRELESS_GB;
3665
3666                 if (rssi_level == 1)
3667                         ratr_bitmap &= 0x00000f00;
3668                 else if (rssi_level == 2)
3669                         ratr_bitmap &= 0x00000ff0;
3670                 else
3671                         ratr_bitmap &= 0x00000ff5;
3672                 break;
3673         case WIRELESS_MODE_A:
3674                 ratr_index = RATR_INX_WIRELESS_G;
3675                 ratr_bitmap &= 0x00000ff0;
3676                 break;
3677         case WIRELESS_MODE_N_24G:
3678         case WIRELESS_MODE_N_5G:
3679                 if (wirelessmode == WIRELESS_MODE_N_24G)
3680                         ratr_index = RATR_INX_WIRELESS_NGB;
3681                 else
3682                         ratr_index = RATR_INX_WIRELESS_NG;
3683
3684                 if (mimo_ps == IEEE80211_SMPS_STATIC
3685                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3686                         if (rssi_level == 1)
3687                                 ratr_bitmap &= 0x000f0000;
3688                         else if (rssi_level == 2)
3689                                 ratr_bitmap &= 0x000ff000;
3690                         else
3691                                 ratr_bitmap &= 0x000ff005;
3692                 } else {
3693                         if (rf_type == RF_1T1R) {
3694                                 if (curtxbw_40mhz) {
3695                                         if (rssi_level == 1)
3696                                                 ratr_bitmap &= 0x000f0000;
3697                                         else if (rssi_level == 2)
3698                                                 ratr_bitmap &= 0x000ff000;
3699                                         else
3700                                                 ratr_bitmap &= 0x000ff015;
3701                                 } else {
3702                                         if (rssi_level == 1)
3703                                                 ratr_bitmap &= 0x000f0000;
3704                                         else if (rssi_level == 2)
3705                                                 ratr_bitmap &= 0x000ff000;
3706                                         else
3707                                                 ratr_bitmap &= 0x000ff005;
3708                                 }
3709                         } else {
3710                                 if (curtxbw_40mhz) {
3711                                         if (rssi_level == 1)
3712                                                 ratr_bitmap &= 0x0fff0000;
3713                                         else if (rssi_level == 2)
3714                                                 ratr_bitmap &= 0x0ffff000;
3715                                         else
3716                                                 ratr_bitmap &= 0x0ffff015;
3717                                 } else {
3718                                         if (rssi_level == 1)
3719                                                 ratr_bitmap &= 0x0fff0000;
3720                                         else if (rssi_level == 2)
3721                                                 ratr_bitmap &= 0x0ffff000;
3722                                         else
3723                                                 ratr_bitmap &= 0x0ffff005;
3724                                 }
3725                         }
3726                 }
3727                 break;
3728
3729         case WIRELESS_MODE_AC_24G:
3730                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3731                 if (rssi_level == 1)
3732                         ratr_bitmap &= 0xfc3f0000;
3733                 else if (rssi_level == 2)
3734                         ratr_bitmap &= 0xfffff000;
3735                 else
3736                         ratr_bitmap &= 0xffffffff;
3737                 break;
3738
3739         case WIRELESS_MODE_AC_5G:
3740                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3741
3742                 if (rf_type == RF_1T1R) {
3743                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3744                                 ratr_bitmap &= 0x003f8000;
3745                         else if (rssi_level == 2)
3746                                 ratr_bitmap &= 0x003ff000;
3747                         else
3748                                 ratr_bitmap &= 0x003ff010;
3749                 } else {
3750                         if (rssi_level == 1)
3751                                 ratr_bitmap &= 0xfe3f8000;
3752                         else if (rssi_level == 2)
3753                                 ratr_bitmap &= 0xfffff000;
3754                         else
3755                                 ratr_bitmap &= 0xfffff010;
3756                 }
3757                 break;
3758
3759         default:
3760                 ratr_index = RATR_INX_WIRELESS_NGB;
3761
3762                 if (rf_type == RF_1T2R)
3763                         ratr_bitmap &= 0x000ff0ff;
3764                 else
3765                         ratr_bitmap &= 0x0f8ff0ff;
3766                 break;
3767         }
3768
3769         ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3770         sta_entry->ratr_index = ratr_index;
3771         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3772                                                         ratr_bitmap);
3773
3774         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3775                  "ratr_bitmap :%x\n", ratr_bitmap);
3776
3777         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3778                                        (ratr_index << 28)); */
3779
3780         rate_mask[0] = macid;
3781         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3782         rate_mask[2] = rtlphy->current_chan_bw
3783                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3784                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3785
3786         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3787         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3788         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3789         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3790
3791         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3792                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3793                  ratr_index, ratr_bitmap,
3794                  rate_mask[0], rate_mask[1],
3795                  rate_mask[2], rate_mask[3],
3796                  rate_mask[4], rate_mask[5],
3797                  rate_mask[6]);
3798         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3799         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3800 }
3801
3802 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3803                 struct ieee80211_sta *sta, u8 rssi_level)
3804 {
3805         struct rtl_priv *rtlpriv = rtl_priv(hw);
3806         if (rtlpriv->dm.useramask)
3807                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3808         else
3809                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3810                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3811                 rtl8821ae_update_hal_rate_table(hw, sta);
3812 }
3813
3814 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3815 {
3816         struct rtl_priv *rtlpriv = rtl_priv(hw);
3817         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3818         u16 wireless_mode = mac->mode;
3819         u8 sifs_timer, r2t_sifs;
3820
3821         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3822                                       (u8 *)&mac->slot_time);
3823         if (wireless_mode == WIRELESS_MODE_G)
3824                 sifs_timer = 0x0a;
3825         else
3826                 sifs_timer = 0x0e;
3827         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3828
3829         r2t_sifs = 0xa;
3830
3831         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3832             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3833             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3834                 if (mac->vendor == PEER_ATH)
3835                         r2t_sifs = 0x8;
3836                 else
3837                         r2t_sifs = 0xa;
3838         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3839                 r2t_sifs = 0xa;
3840         }
3841
3842         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3843 }
3844
3845 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3846 {
3847         struct rtl_priv *rtlpriv = rtl_priv(hw);
3848         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3849         struct rtl_phy *rtlphy = &rtlpriv->phy;
3850         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3851         u8 u1tmp = 0;
3852         bool b_actuallyset = false;
3853
3854         if (rtlpriv->rtlhal.being_init_adapter)
3855                 return false;
3856
3857         if (ppsc->swrf_processing)
3858                 return false;
3859
3860         spin_lock(&rtlpriv->locks.rf_ps_lock);
3861         if (ppsc->rfchange_inprogress) {
3862                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3863                 return false;
3864         } else {
3865                 ppsc->rfchange_inprogress = true;
3866                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3867         }
3868
3869         cur_rfstate = ppsc->rfpwr_state;
3870
3871         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3872                         rtl_read_byte(rtlpriv,
3873                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3874
3875         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3876
3877         if (rtlphy->polarity_ctl)
3878                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3879         else
3880                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3881
3882         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3883                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3884                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3885
3886                 e_rfpowerstate_toset = ERFON;
3887                 ppsc->hwradiooff = false;
3888                 b_actuallyset = true;
3889         } else if ((!ppsc->hwradiooff)
3890                    && (e_rfpowerstate_toset == ERFOFF)) {
3891                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3892                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3893
3894                 e_rfpowerstate_toset = ERFOFF;
3895                 ppsc->hwradiooff = true;
3896                 b_actuallyset = true;
3897         }
3898
3899         if (b_actuallyset) {
3900                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3901                 ppsc->rfchange_inprogress = false;
3902                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3903         } else {
3904                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3905                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3906
3907                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3908                 ppsc->rfchange_inprogress = false;
3909                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3910         }
3911
3912         *valid = 1;
3913         return !ppsc->hwradiooff;
3914 }
3915
3916 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3917                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3918                      bool is_wepkey, bool clear_all)
3919 {
3920         struct rtl_priv *rtlpriv = rtl_priv(hw);
3921         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3922         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3923         u8 *macaddr = p_macaddr;
3924         u32 entry_id = 0;
3925         bool is_pairwise = false;
3926
3927         static u8 cam_const_addr[4][6] = {
3928                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3929                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3930                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3931                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3932         };
3933         static u8 cam_const_broad[] = {
3934                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3935         };
3936
3937         if (clear_all) {
3938                 u8 idx = 0;
3939                 u8 cam_offset = 0;
3940                 u8 clear_number = 5;
3941
3942                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3943
3944                 for (idx = 0; idx < clear_number; idx++) {
3945                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3946                         rtl_cam_empty_entry(hw, cam_offset + idx);
3947
3948                         if (idx < 5) {
3949                                 memset(rtlpriv->sec.key_buf[idx], 0,
3950                                        MAX_KEY_LEN);
3951                                 rtlpriv->sec.key_len[idx] = 0;
3952                         }
3953                 }
3954         } else {
3955                 switch (enc_algo) {
3956                 case WEP40_ENCRYPTION:
3957                         enc_algo = CAM_WEP40;
3958                         break;
3959                 case WEP104_ENCRYPTION:
3960                         enc_algo = CAM_WEP104;
3961                         break;
3962                 case TKIP_ENCRYPTION:
3963                         enc_algo = CAM_TKIP;
3964                         break;
3965                 case AESCCMP_ENCRYPTION:
3966                         enc_algo = CAM_AES;
3967                         break;
3968                 default:
3969                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3970                                  "switch case %#x not processed\n", enc_algo);
3971                         enc_algo = CAM_TKIP;
3972                         break;
3973                 }
3974
3975                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3976                         macaddr = cam_const_addr[key_index];
3977                         entry_id = key_index;
3978                 } else {
3979                         if (is_group) {
3980                                 macaddr = cam_const_broad;
3981                                 entry_id = key_index;
3982                         } else {
3983                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3984                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3985                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3986                                                 pr_err("an not find free hwsecurity cam entry\n");
3987                                                 return;
3988                                         }
3989                                 } else {
3990                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3991                                 }
3992
3993                                 key_index = PAIRWISE_KEYIDX;
3994                                 is_pairwise = true;
3995                         }
3996                 }
3997
3998                 if (rtlpriv->sec.key_len[key_index] == 0) {
3999                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4000                                  "delete one entry, entry_id is %d\n",
4001                                  entry_id);
4002                         if (mac->opmode == NL80211_IFTYPE_AP)
4003                                 rtl_cam_del_entry(hw, p_macaddr);
4004                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4005                 } else {
4006                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4007                                  "add one entry\n");
4008                         if (is_pairwise) {
4009                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4010                                          "set Pairwise key\n");
4011
4012                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4013                                                       entry_id, enc_algo,
4014                                                       CAM_CONFIG_NO_USEDK,
4015                                                       rtlpriv->sec.key_buf[key_index]);
4016                         } else {
4017                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4018                                          "set group key\n");
4019
4020                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4021                                         rtl_cam_add_one_entry(hw,
4022                                                         rtlefuse->dev_addr,
4023                                                         PAIRWISE_KEYIDX,
4024                                                         CAM_PAIRWISE_KEY_POSITION,
4025                                                         enc_algo,
4026                                                         CAM_CONFIG_NO_USEDK,
4027                                                         rtlpriv->sec.key_buf
4028                                                         [entry_id]);
4029                                 }
4030
4031                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4032                                                 entry_id, enc_algo,
4033                                                 CAM_CONFIG_NO_USEDK,
4034                                                 rtlpriv->sec.key_buf[entry_id]);
4035                         }
4036                 }
4037         }
4038 }
4039
4040 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4041 {
4042         struct rtl_priv *rtlpriv = rtl_priv(hw);
4043
4044         /* 0:Low, 1:High, 2:From Efuse. */
4045         rtlpriv->btcoexist.reg_bt_iso = 2;
4046         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4047         rtlpriv->btcoexist.reg_bt_sco = 3;
4048         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4049         rtlpriv->btcoexist.reg_bt_sco = 0;
4050 }
4051
4052 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4053 {
4054         struct rtl_priv *rtlpriv = rtl_priv(hw);
4055
4056         if (rtlpriv->cfg->ops->get_btc_status())
4057                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4058 }
4059
4060 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4061 {
4062 }
4063
4064 void rtl8821ae_resume(struct ieee80211_hw *hw)
4065 {
4066 }
4067
4068 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4069 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4070         bool allow_all_da, bool write_into_reg)
4071 {
4072         struct rtl_priv *rtlpriv = rtl_priv(hw);
4073         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4074
4075         if (allow_all_da) /* Set BIT0 */
4076                 rtlpci->receive_config |= RCR_AAP;
4077         else /* Clear BIT0 */
4078                 rtlpci->receive_config &= ~RCR_AAP;
4079
4080         if (write_into_reg)
4081                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4082
4083         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4084                 "receive_config=0x%08X, write_into_reg=%d\n",
4085                 rtlpci->receive_config, write_into_reg);
4086 }
4087
4088 /* WKFMCAMAddAllEntry8812 */
4089 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4090                                   struct rtl_wow_pattern *rtl_pattern,
4091                                   u8 index)
4092 {
4093         struct rtl_priv *rtlpriv = rtl_priv(hw);
4094         u32 cam = 0;
4095         u8 addr = 0;
4096         u16 rxbuf_addr;
4097         u8 tmp, count = 0;
4098         u16 cam_start;
4099         u16 offset;
4100
4101         /* Count the WFCAM entry start offset. */
4102
4103         /* RX page size = 128 byte */
4104         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4105         /* We should start from the boundry */
4106         cam_start = offset * 128;
4107
4108         /* Enable Rx packet buffer access. */
4109         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4110         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4111                 /* Set Rx packet buffer offset.
4112                  * RxBufer pointer increases 1,
4113                  * we can access 8 bytes in Rx packet buffer.
4114                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4115                  * RxBufer addr = (CAM start offset +
4116                  *                 per entry offset of a WKFM CAM)/8
4117                  *      * index: The index of the wake up frame mask
4118                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4119                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4120                  */
4121                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4122                 /* Set R/W start offset */
4123                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4124
4125                 if (addr == 0) {
4126                         cam = BIT(31) | rtl_pattern->crc;
4127
4128                         if (rtl_pattern->type == UNICAST_PATTERN)
4129                                 cam |= BIT(24);
4130                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4131                                 cam |= BIT(25);
4132                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4133                                 cam |= BIT(26);
4134
4135                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4136                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4137                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4138                                   REG_PKTBUF_DBG_DATA_L, cam);
4139
4140                         /* Write to Rx packet buffer. */
4141                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4142                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4143                         cam = rtl_pattern->mask[addr - 2];
4144
4145                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4146                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4147                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4148                                   REG_PKTBUF_DBG_DATA_L, cam);
4149
4150                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4151                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4152                         cam = rtl_pattern->mask[addr - 2];
4153
4154                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4155                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4156                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4157                                   REG_PKTBUF_DBG_DATA_H, cam);
4158
4159                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4160                 }
4161
4162                 count = 0;
4163                 do {
4164                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4165                         udelay(2);
4166                         count++;
4167                 } while (tmp && count < 100);
4168
4169                 WARN_ONCE((count >= 100),
4170                           "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4171                           tmp);
4172         }
4173         /* Disable Rx packet buffer access. */
4174         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4175                        DISABLE_TRXPKT_BUF_ACCESS);
4176 }