drivers/net/wireless/ti/wl12xx/main.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <linux/err.h>
  26
  27 #include "../wlcore/wlcore.h"
  28 #include "../wlcore/debug.h"
  29 #include "../wlcore/io.h"
  30 #include "../wlcore/acx.h"
  31 #include "../wlcore/tx.h"
  32 #include "../wlcore/rx.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "wl12xx.h"
  36 #include "reg.h"
  37 #include "cmd.h"
  38 #include "acx.h"
  39 #include "scan.h"
  40 #include "event.h"
  41 #include "debugfs.h"
  42 #include "conf.h"
  43
  44 static char *fref_param;
  45 static char *tcxo_param;
  46
  47 static struct wlcore_conf wl12xx_conf = {
  48         .sg = {
  49                 .params = {
  50                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  51                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  52                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  53                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  54                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  55                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  56                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  57                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  58                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  59                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  60                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  61                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  62                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  63                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  64                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  65                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  66                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  67                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  68                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  69                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  70                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  71                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  72                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  73                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  74                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  75                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  76                         /* active scan params */
  77                         [WL12XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  78                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  79                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  80                         /* passive scan params */
  81                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_BR] = 800,
  82                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_EDR] = 200,
  83                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_HV3] = 200,
  84                         /* passive scan in dual antenna params */
  85                         [WL12XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  86                         [WL12XX_CONF_SG_BCN_HV3_COLL_THR_IN_PASSIVE_SCAN] = 0,
  87                         [WL12XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
  88                         /* general params */
  89                         [WL12XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  90                         [WL12XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
  91                         [WL12XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
  92                         [WL12XX_CONF_SG_DHCP_TIME] = 5000,
  93                         [WL12XX_CONF_SG_RXT] = 1200,
  94                         [WL12XX_CONF_SG_TXT] = 1000,
  95                         [WL12XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  96                         [WL12XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  97                         [WL12XX_CONF_SG_HV3_MAX_SERVED] = 6,
  98                         [WL12XX_CONF_SG_PS_POLL_TIMEOUT] = 10,
  99                         [WL12XX_CONF_SG_UPSD_TIMEOUT] = 10,
 100                         [WL12XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 101                         [WL12XX_CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 102                         [WL12XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 103                         /* AP params */
 104                         [WL12XX_CONF_AP_BEACON_MISS_TX] = 3,
 105                         [WL12XX_CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 106                         [WL12XX_CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 107                         [WL12XX_CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 108                         [WL12XX_CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 109                         [WL12XX_CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 110                         /* CTS Diluting params */
 111                         [WL12XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 112                         [WL12XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 113                 },
 114                 .state = CONF_SG_PROTECTIVE,
 115         },
 116         .rx = {
 117                 .rx_msdu_life_time           = 512000,
 118                 .packet_detection_threshold  = 0,
 119                 .ps_poll_timeout             = 15,
 120                 .upsd_timeout                = 15,
 121                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 122                 .rx_cca_threshold            = 0,
 123                 .irq_blk_threshold           = 0xFFFF,
 124                 .irq_pkt_threshold           = 0,
 125                 .irq_timeout                 = 600,
 126                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 127         },
 128         .tx = {
 129                 .tx_energy_detection         = 0,
 130                 .sta_rc_conf                 = {
 131                         .enabled_rates       = 0,
 132                         .short_retry_limit   = 10,
 133                         .long_retry_limit    = 10,
 134                         .aflags              = 0,
 135                 },
 136                 .ac_conf_count               = 4,
 137                 .ac_conf                     = {
 138                         [CONF_TX_AC_BE] = {
 139                                 .ac          = CONF_TX_AC_BE,
 140                                 .cw_min      = 15,
 141                                 .cw_max      = 63,
 142                                 .aifsn       = 3,
 143                                 .tx_op_limit = 0,
 144                         },
 145                         [CONF_TX_AC_BK] = {
 146                                 .ac          = CONF_TX_AC_BK,
 147                                 .cw_min      = 15,
 148                                 .cw_max      = 63,
 149                                 .aifsn       = 7,
 150                                 .tx_op_limit = 0,
 151                         },
 152                         [CONF_TX_AC_VI] = {
 153                                 .ac          = CONF_TX_AC_VI,
 154                                 .cw_min      = 15,
 155                                 .cw_max      = 63,
 156                                 .aifsn       = CONF_TX_AIFS_PIFS,
 157                                 .tx_op_limit = 3008,
 158                         },
 159                         [CONF_TX_AC_VO] = {
 160                                 .ac          = CONF_TX_AC_VO,
 161                                 .cw_min      = 15,
 162                                 .cw_max      = 63,
 163                                 .aifsn       = CONF_TX_AIFS_PIFS,
 164                                 .tx_op_limit = 1504,
 165                         },
 166                 },
 167                 .max_tx_retries = 100,
 168                 .ap_aging_period = 300,
 169                 .tid_conf_count = 4,
 170                 .tid_conf = {
 171                         [CONF_TX_AC_BE] = {
 172                                 .queue_id    = CONF_TX_AC_BE,
 173                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 174                                 .tsid        = CONF_TX_AC_BE,
 175                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 176                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 177                                 .apsd_conf   = {0, 0},
 178                         },
 179                         [CONF_TX_AC_BK] = {
 180                                 .queue_id    = CONF_TX_AC_BK,
 181                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 182                                 .tsid        = CONF_TX_AC_BK,
 183                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 184                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 185                                 .apsd_conf   = {0, 0},
 186                         },
 187                         [CONF_TX_AC_VI] = {
 188                                 .queue_id    = CONF_TX_AC_VI,
 189                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 190                                 .tsid        = CONF_TX_AC_VI,
 191                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 192                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 193                                 .apsd_conf   = {0, 0},
 194                         },
 195                         [CONF_TX_AC_VO] = {
 196                                 .queue_id    = CONF_TX_AC_VO,
 197                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 198                                 .tsid        = CONF_TX_AC_VO,
 199                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 200                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 201                                 .apsd_conf   = {0, 0},
 202                         },
 203                 },
 204                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 205                 .tx_compl_timeout            = 700,
 206                 .tx_compl_threshold          = 4,
 207                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 208                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 209                 .tmpl_short_retry_limit      = 10,
 210                 .tmpl_long_retry_limit       = 10,
 211                 .tx_watchdog_timeout         = 5000,
 212                 .slow_link_thold             = 3,
 213                 .fast_link_thold             = 10,
 214         },
 215         .conn = {
 216                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 217                 .listen_interval             = 1,
 218                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 219                 .suspend_listen_interval     = 3,
 220                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 221                 .bcn_filt_ie_count           = 3,
 222                 .bcn_filt_ie = {
 223                         [0] = {
 224                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 225                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 226                         },
 227                         [1] = {
 228                                 .ie          = WLAN_EID_HT_OPERATION,
 229                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 230                         },
 231                         [2] = {
 232                                 .ie          = WLAN_EID_ERP_INFO,
 233                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 234                         },
 235                 },
 236                 .synch_fail_thold            = 12,
 237                 .bss_lose_timeout            = 400,
 238                 .beacon_rx_timeout           = 10000,
 239                 .broadcast_timeout           = 20000,
 240                 .rx_broadcast_in_ps          = 1,
 241                 .ps_poll_threshold           = 10,
 242                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 243                 .bet_max_consecutive         = 50,
 244                 .psm_entry_retries           = 8,
 245                 .psm_exit_retries            = 16,
 246                 .psm_entry_nullfunc_retries  = 3,
 247                 .dynamic_ps_timeout          = 1500,
 248                 .forced_ps                   = false,
 249                 .keep_alive_interval         = 55000,
 250                 .max_listen_interval         = 20,
 251                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 252                 .suspend_rx_ba_activity      = 0,
 253         },
 254         .itrim = {
 255                 .enable = false,
 256                 .timeout = 50000,
 257         },
 258         .pm_config = {
 259                 .host_clk_settling_time = 5000,
 260                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 261         },
 262         .roam_trigger = {
 263                 .trigger_pacing               = 1,
 264                 .avg_weight_rssi_beacon       = 20,
 265                 .avg_weight_rssi_data         = 10,
 266                 .avg_weight_snr_beacon        = 20,
 267                 .avg_weight_snr_data          = 10,
 268         },
 269         .scan = {
 270                 .min_dwell_time_active        = 7500,
 271                 .max_dwell_time_active        = 30000,
 272                 .min_dwell_time_active_long   = 25000,
 273                 .max_dwell_time_active_long   = 50000,
 274                 .dwell_time_passive           = 100000,
 275                 .dwell_time_dfs               = 150000,
 276                 .num_probe_reqs               = 2,
 277                 .split_scan_timeout           = 50000,
 278         },
 279         .sched_scan = {
 280                 /*
 281                  * Values are in TU/1000 but since sched scan FW command
 282                  * params are in TUs rounding up may occur.
 283                  */
 284                 .base_dwell_time                = 7500,
 285                 .max_dwell_time_delta           = 22500,
 286                 /* based on 250bits per probe @1Mbps */
 287                 .dwell_time_delta_per_probe     = 2000,
 288                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 289                 .dwell_time_delta_per_probe_5   = 350,
 290                 .dwell_time_passive             = 100000,
 291                 .dwell_time_dfs                 = 150000,
 292                 .num_probe_reqs                 = 2,
 293                 .rssi_threshold                 = -90,
 294                 .snr_threshold                  = 0,
 295         },
 296         .ht = {
 297                 .rx_ba_win_size = 8,
 298                 .tx_ba_win_size = 64,
 299                 .inactivity_timeout = 10000,
 300                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 301         },
 302         /*
 303          * Memory config for wl127x chips is given in the
 304          * wl12xx_default_priv_conf struct. The below configuration is
 305          * for wl128x chips.
 306          */
 307         .mem = {
 308                 .num_stations                 = 1,
 309                 .ssid_profiles                = 1,
 310                 .rx_block_num                 = 40,
 311                 .tx_min_block_num             = 40,
 312                 .dynamic_memory               = 1,
 313                 .min_req_tx_blocks            = 45,
 314                 .min_req_rx_blocks            = 22,
 315                 .tx_min                       = 27,
 316         },
 317         .fm_coex = {
 318                 .enable                       = true,
 319                 .swallow_period               = 5,
 320                 .n_divider_fref_set_1         = 0xff,       /* default */
 321                 .n_divider_fref_set_2         = 12,
 322                 .m_divider_fref_set_1         = 0xffff,
 323                 .m_divider_fref_set_2         = 148,        /* default */
 324                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 325                 .ldo_stabilization_time       = 0xffff,     /* default */
 326                 .fm_disturbed_band_margin     = 0xff,       /* default */
 327                 .swallow_clk_diff             = 0xff,       /* default */
 328         },
 329         .rx_streaming = {
 330                 .duration                      = 150,
 331                 .queues                        = 0x1,
 332                 .interval                      = 20,
 333                 .always                        = 0,
 334         },
 335         .fwlog = {
 336                 .mode                         = WL12XX_FWLOG_CONTINUOUS,
 337                 .mem_blocks                   = 2,
 338                 .severity                     = 0,
 339                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 340                 .output                       = WL12XX_FWLOG_OUTPUT_DBG_PINS,
 341                 .threshold                    = 0,
 342         },
 343         .rate = {
 344                 .rate_retry_score = 32000,
 345                 .per_add = 8192,
 346                 .per_th1 = 2048,
 347                 .per_th2 = 4096,
 348                 .max_per = 8100,
 349                 .inverse_curiosity_factor = 5,
 350                 .tx_fail_low_th = 4,
 351                 .tx_fail_high_th = 10,
 352                 .per_alpha_shift = 4,
 353                 .per_add_shift = 13,
 354                 .per_beta1_shift = 10,
 355                 .per_beta2_shift = 8,
 356                 .rate_check_up = 2,
 357                 .rate_check_down = 12,
 358                 .rate_retry_policy = {
 359                         0x00, 0x00, 0x00, 0x00, 0x00,
 360                         0x00, 0x00, 0x00, 0x00, 0x00,
 361                         0x00, 0x00, 0x00,
 362                 },
 363         },
 364         .hangover = {
 365                 .recover_time               = 0,
 366                 .hangover_period            = 20,
 367                 .dynamic_mode               = 1,
 368                 .early_termination_mode     = 1,
 369                 .max_period                 = 20,
 370                 .min_period                 = 1,
 371                 .increase_delta             = 1,
 372                 .decrease_delta             = 2,
 373                 .quiet_time                 = 4,
 374                 .increase_time              = 1,
 375                 .window_size                = 16,
 376         },
 377         .recovery = {
 378                 .bug_on_recovery            = 0,
 379                 .no_recovery                = 0,
 380         },
 381 };
 382
 383 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 384         .rf = {
 385                 .tx_per_channel_power_compensation_2 = {
 386                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 387                 },
 388                 .tx_per_channel_power_compensation_5 = {
 389                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 390                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 391                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 392                 },
 393         },
 394         .mem_wl127x = {
 395                 .num_stations                 = 1,
 396                 .ssid_profiles                = 1,
 397                 .rx_block_num                 = 70,
 398                 .tx_min_block_num             = 40,
 399                 .dynamic_memory               = 1,
 400                 .min_req_tx_blocks            = 100,
 401                 .min_req_rx_blocks            = 22,
 402                 .tx_min                       = 27,
 403         },
 404
 405 };
 406
 407 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 408 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 409 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 410
 411 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 412         /* MCS rates are used only with 11n */
 413         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 414         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 415         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 416         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 417         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 418         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 419         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 420         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 421         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 422
 423         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 424         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 425         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 426         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 427
 428         /* TI-specific rate */
 429         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 430
 431         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 432         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 433         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 434         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 435         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 436         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 437         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 438         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 439 };
 440
 441 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 442         /* MCS rates are used only with 11n */
 443         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 444         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 445         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 446         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 447         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 448         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 449         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 450         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 451         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 452
 453         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 454         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 455         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 456         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 457
 458         /* TI-specific rate */
 459         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 460
 461         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 462         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 463         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 464         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 465         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 466         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 467         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 468         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 469 };
 470
 471 static const u8 *wl12xx_band_rate_to_idx[] = {
 472         [NL80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 473         [NL80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 474 };
 475
 476 enum wl12xx_hw_rates {
 477         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 478         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 479         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 480         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 481         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 482         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 483         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 484         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 485         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 486         WL12XX_CONF_HW_RXTX_RATE_54,
 487         WL12XX_CONF_HW_RXTX_RATE_48,
 488         WL12XX_CONF_HW_RXTX_RATE_36,
 489         WL12XX_CONF_HW_RXTX_RATE_24,
 490         WL12XX_CONF_HW_RXTX_RATE_22,
 491         WL12XX_CONF_HW_RXTX_RATE_18,
 492         WL12XX_CONF_HW_RXTX_RATE_12,
 493         WL12XX_CONF_HW_RXTX_RATE_11,
 494         WL12XX_CONF_HW_RXTX_RATE_9,
 495         WL12XX_CONF_HW_RXTX_RATE_6,
 496         WL12XX_CONF_HW_RXTX_RATE_5_5,
 497         WL12XX_CONF_HW_RXTX_RATE_2,
 498         WL12XX_CONF_HW_RXTX_RATE_1,
 499         WL12XX_CONF_HW_RXTX_RATE_MAX,
 500 };
 501
 502 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 503         [PART_DOWN] = {
 504                 .mem = {
 505                         .start = 0x00000000,
 506                         .size  = 0x000177c0
 507                 },
 508                 .reg = {
 509                         .start = REGISTERS_BASE,
 510                         .size  = 0x00008800
 511                 },
 512                 .mem2 = {
 513                         .start = 0x00000000,
 514                         .size  = 0x00000000
 515                 },
 516                 .mem3 = {
 517                         .start = 0x00000000,
 518                         .size  = 0x00000000
 519                 },
 520         },
 521
 522         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 523                          * partition here */
 524                 .mem = {
 525                         .start = 0x00040000,
 526                         .size  = 0x00014fc0
 527                 },
 528                 .reg = {
 529                         .start = REGISTERS_BASE,
 530                         .size  = 0x00008800
 531                 },
 532                 .mem2 = {
 533                         .start = 0x00000000,
 534                         .size  = 0x00000000
 535                 },
 536                 .mem3 = {
 537                         .start = 0x00000000,
 538                         .size  = 0x00000000
 539                 },
 540         },
 541
 542         [PART_WORK] = {
 543                 .mem = {
 544                         .start = 0x00040000,
 545                         .size  = 0x00014fc0
 546                 },
 547                 .reg = {
 548                         .start = REGISTERS_BASE,
 549                         .size  = 0x0000a000
 550                 },
 551                 .mem2 = {
 552                         .start = 0x003004f8,
 553                         .size  = 0x00000004
 554                 },
 555                 .mem3 = {
 556                         .start = 0x00000000,
 557                         .size  = 0x00040404
 558                 },
 559         },
 560
 561         [PART_DRPW] = {
 562                 .mem = {
 563                         .start = 0x00040000,
 564                         .size  = 0x00014fc0
 565                 },
 566                 .reg = {
 567                         .start = DRPW_BASE,
 568                         .size  = 0x00006000
 569                 },
 570                 .mem2 = {
 571                         .start = 0x00000000,
 572                         .size  = 0x00000000
 573                 },
 574                 .mem3 = {
 575                         .start = 0x00000000,
 576                         .size  = 0x00000000
 577                 }
 578         }
 579 };
 580
 581 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 582         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 583         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 584         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 585         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 586         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 587         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 588         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 589         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 590         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 591         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 592
 593         /* data access memory addresses, used with partition translation */
 594         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 595         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 596
 597         /* raw data access memory addresses */
 598         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 599 };
 600
 601 /* TODO: maybe move to a new header file? */
 602 #define WL127X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 603 #define WL127X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 604 #define WL127X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 605
 606 #define WL128X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 607 #define WL128X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 608 #define WL128X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 609
 610 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 611 {
 612         int ret;
 613
 614         if (wl->chip.id != CHIP_ID_128X_PG20) {
 615                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 616                 struct wl12xx_priv *priv = wl->priv;
 617
 618                 /*
 619                  * Choose the block we want to read
 620                  * For aggregated packets, only the first memory block
 621                  * should be retrieved. The FW takes care of the rest.
 622                  */
 623                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 624
 625                 priv->rx_mem_addr->addr = (mem_block << 8) +
 626                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 627
 628                 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
 629
 630                 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
 631                                    sizeof(*priv->rx_mem_addr), false);
 632                 if (ret < 0)
 633                         return ret;
 634         }
 635
 636         return 0;
 637 }
 638
 639 static int wl12xx_identify_chip(struct wl1271 *wl)
 640 {
 641         int ret = 0;
 642
 643         switch (wl->chip.id) {
 644         case CHIP_ID_127X_PG10:
 645                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 646                                wl->chip.id);
 647
 648                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 649                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 650                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 651                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 652                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 653                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 654                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 655                        sizeof(wl->conf.mem));
 656
 657                 /* read data preparation is only needed by wl127x */
 658                 wl->ops->prepare_read = wl127x_prepare_read;
 659
 660                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 661                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 662                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 663                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 664                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 665                 break;
 666
 667         case CHIP_ID_127X_PG20:
 668                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 669                              wl->chip.id);
 670
 671                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 672                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 673                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 674                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 675                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 676                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 677                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 678                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 679                        sizeof(wl->conf.mem));
 680
 681                 /* read data preparation is only needed by wl127x */
 682                 wl->ops->prepare_read = wl127x_prepare_read;
 683
 684                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 685                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 686                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 687                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 688                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 689                 break;
 690
 691         case CHIP_ID_128X_PG20:
 692                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 693                              wl->chip.id);
 694                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 695                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 696                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 697
 698                 /* wl128x requires TX blocksize alignment */
 699                 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 700                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 701                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 702                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 703
 704                 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
 705                               WL128X_IFTYPE_SR_VER,  WL128X_MAJOR_SR_VER,
 706                               WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
 707                               WL128X_IFTYPE_MR_VER,  WL128X_MAJOR_MR_VER,
 708                               WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
 709                 break;
 710         case CHIP_ID_128X_PG10:
 711         default:
 712                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 713                 ret = -ENODEV;
 714                 goto out;
 715         }
 716
 717         wl->fw_mem_block_size = 256;
 718         wl->fwlog_end = 0x2000000;
 719
 720         /* common settings */
 721         wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
 722         wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
 723         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 724         wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 725         wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
 726         wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
 727 out:
 728         return ret;
 729 }
 730
 731 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
 732                                              u16 val)
 733 {
 734         int ret;
 735
 736         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 737         addr = (addr >> 1) + 0x30000;
 738         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 739         if (ret < 0)
 740                 goto out;
 741
 742         /* write value to OCP_POR_WDATA */
 743         ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 744         if (ret < 0)
 745                 goto out;
 746
 747         /* write 1 to OCP_CMD */
 748         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 749         if (ret < 0)
 750                 goto out;
 751
 752 out:
 753         return ret;
 754 }
 755
 756 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
 757                                             u16 *out)
 758 {
 759         u32 val;
 760         int timeout = OCP_CMD_LOOP;
 761         int ret;
 762
 763         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 764         addr = (addr >> 1) + 0x30000;
 765         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 766         if (ret < 0)
 767                 return ret;
 768
 769         /* write 2 to OCP_CMD */
 770         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 771         if (ret < 0)
 772                 return ret;
 773
 774         /* poll for data ready */
 775         do {
 776                 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
 777                 if (ret < 0)
 778                         return ret;
 779         } while (!(val & OCP_READY_MASK) && --timeout);
 780
 781         if (!timeout) {
 782                 wl1271_warning("Top register access timed out.");
 783                 return -ETIMEDOUT;
 784         }
 785
 786         /* check data status and return if OK */
 787         if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
 788                 wl1271_warning("Top register access returned error.");
 789                 return -EIO;
 790         }
 791
 792         if (out)
 793                 *out = val & 0xffff;
 794
 795         return 0;
 796 }
 797
 798 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 799 {
 800         u16 spare_reg;
 801         int ret;
 802
 803         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 804         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 805         if (ret < 0)
 806                 return ret;
 807
 808         if (spare_reg == 0xFFFF)
 809                 return -EFAULT;
 810         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 811         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 812         if (ret < 0)
 813                 return ret;
 814
 815         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 816         ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 817                                    WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 818         if (ret < 0)
 819                 return ret;
 820
 821         /* Delay execution for 15msec, to let the HW settle */
 822         mdelay(15);
 823
 824         return 0;
 825 }
 826
 827 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 828 {
 829         u16 tcxo_detection;
 830         int ret;
 831
 832         ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
 833         if (ret < 0)
 834                 return false;
 835
 836         if (tcxo_detection & TCXO_DET_FAILED)
 837                 return false;
 838
 839         return true;
 840 }
 841
 842 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 843 {
 844         u16 fref_detection;
 845         int ret;
 846
 847         ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
 848         if (ret < 0)
 849                 return false;
 850
 851         if (fref_detection & FREF_CLK_DETECT_FAIL)
 852                 return false;
 853
 854         return true;
 855 }
 856
 857 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 858 {
 859         int ret;
 860
 861         ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 862         if (ret < 0)
 863                 goto out;
 864
 865         ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 866         if (ret < 0)
 867                 goto out;
 868
 869         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 870                                    MCS_PLL_CONFIG_REG_VAL);
 871
 872 out:
 873         return ret;
 874 }
 875
 876 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 877 {
 878         u16 spare_reg;
 879         u16 pll_config;
 880         u8 input_freq;
 881         struct wl12xx_priv *priv = wl->priv;
 882         int ret;
 883
 884         /* Mask bits [3:1] in the sys_clk_cfg register */
 885         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 886         if (ret < 0)
 887                 return ret;
 888
 889         if (spare_reg == 0xFFFF)
 890                 return -EFAULT;
 891         spare_reg |= BIT(2);
 892         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 893         if (ret < 0)
 894                 return ret;
 895
 896         /* Handle special cases of the TCXO clock */
 897         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 898             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 899                 return wl128x_manually_configure_mcs_pll(wl);
 900
 901         /* Set the input frequency according to the selected clock source */
 902         input_freq = (clk & 1) + 1;
 903
 904         ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
 905         if (ret < 0)
 906                 return ret;
 907
 908         if (pll_config == 0xFFFF)
 909                 return -EFAULT;
 910         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 911         pll_config |= MCS_PLL_ENABLE_HP;
 912         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 913
 914         return ret;
 915 }
 916
 917 /*
 918  * WL128x has two clocks input - TCXO and FREF.
 919  * TCXO is the main clock of the device, while FREF is used to sync
 920  * between the GPS and the cellular modem.
 921  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 922  * as the WLAN/BT main clock.
 923  */
 924 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 925 {
 926         struct wl12xx_priv *priv = wl->priv;
 927         u16 sys_clk_cfg;
 928         int ret;
 929
 930         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 931         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 932             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 933                 if (!wl128x_switch_tcxo_to_fref(wl))
 934                         return -EINVAL;
 935                 goto fref_clk;
 936         }
 937
 938         /* Query the HW, to determine which clock source we should use */
 939         ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
 940         if (ret < 0)
 941                 return ret;
 942
 943         if (sys_clk_cfg == 0xFFFF)
 944                 return -EINVAL;
 945         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 946                 goto fref_clk;
 947
 948         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 949         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 950             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 951                 if (!wl128x_switch_tcxo_to_fref(wl))
 952                         return -EINVAL;
 953                 goto fref_clk;
 954         }
 955
 956         /* TCXO clock is selected */
 957         if (!wl128x_is_tcxo_valid(wl))
 958                 return -EINVAL;
 959         *selected_clock = priv->tcxo_clock;
 960         goto config_mcs_pll;
 961
 962 fref_clk:
 963         /* FREF clock is selected */
 964         if (!wl128x_is_fref_valid(wl))
 965                 return -EINVAL;
 966         *selected_clock = priv->ref_clock;
 967
 968 config_mcs_pll:
 969         return wl128x_configure_mcs_pll(wl, *selected_clock);
 970 }
 971
 972 static int wl127x_boot_clk(struct wl1271 *wl)
 973 {
 974         struct wl12xx_priv *priv = wl->priv;
 975         u32 pause;
 976         u32 clk;
 977         int ret;
 978
 979         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 980                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 981
 982         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 983             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 984             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 985                 /* ref clk: 19.2/38.4/38.4-XTAL */
 986                 clk = 0x3;
 987         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 988                  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
 989                  priv->ref_clock == CONF_REF_CLK_52_E)
 990                 /* ref clk: 26/52 */
 991                 clk = 0x5;
 992         else
 993                 return -EINVAL;
 994
 995         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 996                 u16 val;
 997                 /* Set clock type (open drain) */
 998                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
 999                 if (ret < 0)
1000                         goto out;
1001
1002                 val &= FREF_CLK_TYPE_BITS;
1003                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
1004                 if (ret < 0)
1005                         goto out;
1006
1007                 /* Set clock pull mode (no pull) */
1008                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1009                 if (ret < 0)
1010                         goto out;
1011
1012                 val |= NO_PULL;
1013                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1014                 if (ret < 0)
1015                         goto out;
1016         } else {
1017                 u16 val;
1018                 /* Set clock polarity */
1019                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1020                 if (ret < 0)
1021                         goto out;
1022
1023                 val &= FREF_CLK_POLARITY_BITS;
1024                 val |= CLK_REQ_OUTN_SEL;
1025                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1026                 if (ret < 0)
1027                         goto out;
1028         }
1029
1030         ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1031         if (ret < 0)
1032                 goto out;
1033
1034         ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1035         if (ret < 0)
1036                 goto out;
1037
1038         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1039
1040         pause &= ~(WU_COUNTER_PAUSE_VAL);
1041         pause |= WU_COUNTER_PAUSE_VAL;
1042         ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1043
1044 out:
1045         return ret;
1046 }
1047
1048 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1049 {
1050         unsigned long timeout;
1051         u32 boot_data;
1052         int ret = 0;
1053
1054         /* perform soft reset */
1055         ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1056         if (ret < 0)
1057                 goto out;
1058
1059         /* SOFT_RESET is self clearing */
1060         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1061         while (1) {
1062                 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1063                 if (ret < 0)
1064                         goto out;
1065
1066                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1067                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1068                         break;
1069
1070                 if (time_after(jiffies, timeout)) {
1071                         /* 1.2 check pWhalBus->uSelfClearTime if the
1072                          * timeout was reached */
1073                         wl1271_error("soft reset timeout");
1074                         return -1;
1075                 }
1076
1077                 udelay(SOFT_RESET_STALL_TIME);
1078         }
1079
1080         /* disable Rx/Tx */
1081         ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1082         if (ret < 0)
1083                 goto out;
1084
1085         /* disable auto calibration on start*/
1086         ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1087
1088 out:
1089         return ret;
1090 }
1091
1092 static int wl12xx_pre_boot(struct wl1271 *wl)
1093 {
1094         struct wl12xx_priv *priv = wl->priv;
1095         int ret = 0;
1096         u32 clk;
1097         int selected_clock = -1;
1098
1099         if (wl->chip.id == CHIP_ID_128X_PG20) {
1100                 ret = wl128x_boot_clk(wl, &selected_clock);
1101                 if (ret < 0)
1102                         goto out;
1103         } else {
1104                 ret = wl127x_boot_clk(wl);
1105                 if (ret < 0)
1106                         goto out;
1107         }
1108
1109         /* Continue the ELP wake up sequence */
1110         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1111         if (ret < 0)
1112                 goto out;
1113
1114         udelay(500);
1115
1116         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1117         if (ret < 0)
1118                 goto out;
1119
1120         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1121            to be used by DRPw FW. The RTRIM value will be added by the FW
1122            before taking DRPw out of reset */
1123
1124         ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1125         if (ret < 0)
1126                 goto out;
1127
1128         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1129
1130         if (wl->chip.id == CHIP_ID_128X_PG20)
1131                 clk |= ((selected_clock & 0x3) << 1) << 4;
1132         else
1133                 clk |= (priv->ref_clock << 1) << 4;
1134
1135         ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1136         if (ret < 0)
1137                 goto out;
1138
1139         ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1140         if (ret < 0)
1141                 goto out;
1142
1143         /* Disable interrupts */
1144         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1145         if (ret < 0)
1146                 goto out;
1147
1148         ret = wl1271_boot_soft_reset(wl);
1149         if (ret < 0)
1150                 goto out;
1151
1152 out:
1153         return ret;
1154 }
1155
1156 static int wl12xx_pre_upload(struct wl1271 *wl)
1157 {
1158         u32 tmp;
1159         u16 polarity;
1160         int ret;
1161
1162         /* write firmware's last address (ie. it's length) to
1163          * ACX_EEPROMLESS_IND_REG */
1164         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1165
1166         ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1167         if (ret < 0)
1168                 goto out;
1169
1170         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1171         if (ret < 0)
1172                 goto out;
1173
1174         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1175
1176         /* 6. read the EEPROM parameters */
1177         ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1178         if (ret < 0)
1179                 goto out;
1180
1181         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1182          * to upload_fw) */
1183
1184         if (wl->chip.id == CHIP_ID_128X_PG20) {
1185                 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1186                 if (ret < 0)
1187                         goto out;
1188         }
1189
1190         /* polarity must be set before the firmware is loaded */
1191         ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1192         if (ret < 0)
1193                 goto out;
1194
1195         /* We use HIGH polarity, so unset the LOW bit */
1196         polarity &= ~POLARITY_LOW;
1197         ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1198
1199 out:
1200         return ret;
1201 }
1202
1203 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1204 {
1205         int ret;
1206
1207         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1208                                WL12XX_ACX_ALL_EVENTS_VECTOR);
1209         if (ret < 0)
1210                 goto out;
1211
1212         wlcore_enable_interrupts(wl);
1213         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1214                                WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1215         if (ret < 0)
1216                 goto disable_interrupts;
1217
1218         ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1219         if (ret < 0)
1220                 goto disable_interrupts;
1221
1222         return ret;
1223
1224 disable_interrupts:
1225         wlcore_disable_interrupts(wl);
1226
1227 out:
1228         return ret;
1229 }
1230
1231 static int wl12xx_boot(struct wl1271 *wl)
1232 {
1233         int ret;
1234
1235         ret = wl12xx_pre_boot(wl);
1236         if (ret < 0)
1237                 goto out;
1238
1239         ret = wlcore_boot_upload_nvs(wl);
1240         if (ret < 0)
1241                 goto out;
1242
1243         ret = wl12xx_pre_upload(wl);
1244         if (ret < 0)
1245                 goto out;
1246
1247         ret = wlcore_boot_upload_firmware(wl);
1248         if (ret < 0)
1249                 goto out;
1250
1251         wl->event_mask = BSS_LOSE_EVENT_ID |
1252                 REGAINED_BSS_EVENT_ID |
1253                 SCAN_COMPLETE_EVENT_ID |
1254                 ROLE_STOP_COMPLETE_EVENT_ID |
1255                 RSSI_SNR_TRIGGER_0_EVENT_ID |
1256                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1257                 SOFT_GEMINI_SENSE_EVENT_ID |
1258                 PERIODIC_SCAN_REPORT_EVENT_ID |
1259                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1260                 DUMMY_PACKET_EVENT_ID |
1261                 PEER_REMOVE_COMPLETE_EVENT_ID |
1262                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1263                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1264                 INACTIVE_STA_EVENT_ID |
1265                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1266
1267         wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1268
1269         ret = wlcore_boot_run_firmware(wl);
1270         if (ret < 0)
1271                 goto out;
1272
1273         ret = wl12xx_enable_interrupts(wl);
1274
1275 out:
1276         return ret;
1277 }
1278
1279 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1280                                void *buf, size_t len)
1281 {
1282         int ret;
1283
1284         ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1285         if (ret < 0)
1286                 return ret;
1287
1288         ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1289
1290         return ret;
1291 }
1292
1293 static int wl12xx_ack_event(struct wl1271 *wl)
1294 {
1295         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1296                                 WL12XX_INTR_TRIG_EVENT_ACK);
1297 }
1298
1299 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1300 {
1301         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1302         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1303
1304         return (align_len + blk_size - 1) / blk_size + spare_blks;
1305 }
1306
1307 static void
1308 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1309                           u32 blks, u32 spare_blks)
1310 {
1311         if (wl->chip.id == CHIP_ID_128X_PG20) {
1312                 desc->wl128x_mem.total_mem_blocks = blks;
1313         } else {
1314                 desc->wl127x_mem.extra_blocks = spare_blks;
1315                 desc->wl127x_mem.total_mem_blocks = blks;
1316         }
1317 }
1318
1319 static void
1320 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1321                             struct sk_buff *skb)
1322 {
1323         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1324
1325         if (wl->chip.id == CHIP_ID_128X_PG20) {
1326                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1327                 desc->length = cpu_to_le16(aligned_len >> 2);
1328
1329                 wl1271_debug(DEBUG_TX,
1330                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1331                              desc->hlid,
1332                              le16_to_cpu(desc->length),
1333                              le16_to_cpu(desc->life_time),
1334                              desc->wl128x_mem.total_mem_blocks,
1335                              desc->wl128x_mem.extra_bytes);
1336         } else {
1337                 /* calculate number of padding bytes */
1338                 int pad = aligned_len - skb->len;
1339                 desc->tx_attr |=
1340                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1341
1342                 /* Store the aligned length in terms of words */
1343                 desc->length = cpu_to_le16(aligned_len >> 2);
1344
1345                 wl1271_debug(DEBUG_TX,
1346                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1347                              pad, desc->hlid,
1348                              le16_to_cpu(desc->length),
1349                              le16_to_cpu(desc->life_time),
1350                              desc->wl127x_mem.total_mem_blocks);
1351         }
1352 }
1353
1354 static enum wl_rx_buf_align
1355 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1356 {
1357         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1358                 return WLCORE_RX_BUF_UNALIGNED;
1359
1360         return WLCORE_RX_BUF_ALIGNED;
1361 }
1362
1363 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1364                                     u32 data_len)
1365 {
1366         struct wl1271_rx_descriptor *desc = rx_data;
1367
1368         /* invalid packet */
1369         if (data_len < sizeof(*desc) ||
1370             data_len < sizeof(*desc) + desc->pad_len)
1371                 return 0;
1372
1373         return data_len - sizeof(*desc) - desc->pad_len;
1374 }
1375
1376 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1377 {
1378         if (wl->fw_status->tx_results_counter ==
1379             (wl->tx_results_count & 0xff))
1380                 return 0;
1381
1382         return wlcore_tx_complete(wl);
1383 }
1384
1385 static int wl12xx_hw_init(struct wl1271 *wl)
1386 {
1387         int ret;
1388
1389         if (wl->chip.id == CHIP_ID_128X_PG20) {
1390                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1391
1392                 ret = wl128x_cmd_general_parms(wl);
1393                 if (ret < 0)
1394                         goto out;
1395
1396                 /*
1397                  * If we are in calibrator based auto detect then we got the FEM nr
1398                  * in wl->fem_manuf. No need to continue further
1399                  */
1400                 if (wl->plt_mode == PLT_FEM_DETECT)
1401                         goto out;
1402
1403                 ret = wl128x_cmd_radio_parms(wl);
1404                 if (ret < 0)
1405                         goto out;
1406
1407                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1408                         /* Enable SDIO padding */
1409                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1410
1411                 /* Must be before wl1271_acx_init_mem_config() */
1412                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1413                 if (ret < 0)
1414                         goto out;
1415         } else {
1416                 ret = wl1271_cmd_general_parms(wl);
1417                 if (ret < 0)
1418                         goto out;
1419
1420                 /*
1421                  * If we are in calibrator based auto detect then we got the FEM nr
1422                  * in wl->fem_manuf. No need to continue further
1423                  */
1424                 if (wl->plt_mode == PLT_FEM_DETECT)
1425                         goto out;
1426
1427                 ret = wl1271_cmd_radio_parms(wl);
1428                 if (ret < 0)
1429                         goto out;
1430                 ret = wl1271_cmd_ext_radio_parms(wl);
1431                 if (ret < 0)
1432                         goto out;
1433         }
1434 out:
1435         return ret;
1436 }
1437
1438 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1439                                      struct wl_fw_status *fw_status)
1440 {
1441         struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1442
1443         fw_status->intr = le32_to_cpu(int_fw_status->intr);
1444         fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1445         fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1446         fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1447         fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1448
1449         fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1450         fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1451         fw_status->link_fast_bitmap =
1452                         le32_to_cpu(int_fw_status->link_fast_bitmap);
1453         fw_status->total_released_blks =
1454                         le32_to_cpu(int_fw_status->total_released_blks);
1455         fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1456
1457         fw_status->counters.tx_released_pkts =
1458                         int_fw_status->counters.tx_released_pkts;
1459         fw_status->counters.tx_lnk_free_pkts =
1460                         int_fw_status->counters.tx_lnk_free_pkts;
1461         fw_status->counters.tx_voice_released_blks =
1462                         int_fw_status->counters.tx_voice_released_blks;
1463         fw_status->counters.tx_last_rate =
1464                         int_fw_status->counters.tx_last_rate;
1465
1466         fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1467 }
1468
1469 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1470                                        struct wl12xx_vif *wlvif)
1471 {
1472         return wlvif->rate_set;
1473 }
1474
1475 static void wl12xx_conf_init(struct wl1271 *wl)
1476 {
1477         struct wl12xx_priv *priv = wl->priv;
1478
1479         /* apply driver default configuration */
1480         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1481
1482         /* apply default private configuration */
1483         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1484 }
1485
1486 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1487 {
1488         bool supported = false;
1489         u8 major, minor;
1490
1491         if (wl->chip.id == CHIP_ID_128X_PG20) {
1492                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1493                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1494
1495                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1496                 if (major > 2 || (major == 2 && minor >= 1))
1497                         supported = true;
1498         } else {
1499                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1500                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1501
1502                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1503                 if (major == 3 && minor >= 1)
1504                         supported = true;
1505         }
1506
1507         wl1271_debug(DEBUG_PROBE,
1508                      "PG Ver major = %d minor = %d, MAC %s present",
1509                      major, minor, supported ? "is" : "is not");
1510
1511         return supported;
1512 }
1513
1514 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1515 {
1516         u32 mac1, mac2;
1517         int ret;
1518
1519         /* Device may be in ELP from the bootloader or kexec */
1520         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1521         if (ret < 0)
1522                 goto out;
1523
1524         usleep_range(500000, 700000);
1525
1526         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1527         if (ret < 0)
1528                 goto out;
1529
1530         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1531         if (ret < 0)
1532                 goto out;
1533
1534         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1535         if (ret < 0)
1536                 goto out;
1537
1538         /* these are the two parts of the BD_ADDR */
1539         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1540                 ((mac1 & 0xff000000) >> 24);
1541         wl->fuse_nic_addr = mac1 & 0xffffff;
1542
1543         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1544
1545 out:
1546         return ret;
1547 }
1548
1549 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1550 {
1551         u16 die_info;
1552         int ret;
1553
1554         if (wl->chip.id == CHIP_ID_128X_PG20)
1555                 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1556                                           &die_info);
1557         else
1558                 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1559                                           &die_info);
1560
1561         if (ret >= 0 && ver)
1562                 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1563
1564         return ret;
1565 }
1566
1567 static int wl12xx_get_mac(struct wl1271 *wl)
1568 {
1569         if (wl12xx_mac_in_fuse(wl))
1570                 return wl12xx_get_fuse_mac(wl);
1571
1572         return 0;
1573 }
1574
1575 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1576                                     struct wl1271_tx_hw_descr *desc,
1577                                     struct sk_buff *skb)
1578 {
1579         desc->wl12xx_reserved = 0;
1580 }
1581
1582 static int wl12xx_plt_init(struct wl1271 *wl)
1583 {
1584         int ret;
1585
1586         ret = wl->ops->boot(wl);
1587         if (ret < 0)
1588                 goto out;
1589
1590         ret = wl->ops->hw_init(wl);
1591         if (ret < 0)
1592                 goto out_irq_disable;
1593
1594         /*
1595          * If we are in calibrator based auto detect then we got the FEM nr
1596          * in wl->fem_manuf. No need to continue further
1597          */
1598         if (wl->plt_mode == PLT_FEM_DETECT)
1599                 goto out;
1600
1601         ret = wl1271_acx_init_mem_config(wl);
1602         if (ret < 0)
1603                 goto out_irq_disable;
1604
1605         ret = wl12xx_acx_mem_cfg(wl);
1606         if (ret < 0)
1607                 goto out_free_memmap;
1608
1609         /* Enable data path */
1610         ret = wl1271_cmd_data_path(wl, 1);
1611         if (ret < 0)
1612                 goto out_free_memmap;
1613
1614         /* Configure for CAM power saving (ie. always active) */
1615         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1616         if (ret < 0)
1617                 goto out_free_memmap;
1618
1619         /* configure PM */
1620         ret = wl1271_acx_pm_config(wl);
1621         if (ret < 0)
1622                 goto out_free_memmap;
1623
1624         goto out;
1625
1626 out_free_memmap:
1627         kfree(wl->target_mem_map);
1628         wl->target_mem_map = NULL;
1629
1630 out_irq_disable:
1631         mutex_unlock(&wl->mutex);
1632         /* Unlocking the mutex in the middle of handling is
1633            inherently unsafe. In this case we deem it safe to do,
1634            because we need to let any possibly pending IRQ out of
1635            the system (and while we are WL1271_STATE_OFF the IRQ
1636            work function will not do anything.) Also, any other
1637            possible concurrent operations will fail due to the
1638            current state, hence the wl1271 struct should be safe. */
1639         wlcore_disable_interrupts(wl);
1640         mutex_lock(&wl->mutex);
1641 out:
1642         return ret;
1643 }
1644
1645 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1646 {
1647         if (is_gem)
1648                 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1649
1650         return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1651 }
1652
1653 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1654                           struct ieee80211_vif *vif,
1655                           struct ieee80211_sta *sta,
1656                           struct ieee80211_key_conf *key_conf)
1657 {
1658         return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1659 }
1660
1661 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1662                                struct ieee80211_sta_ht_cap *ht_cap,
1663                                bool allow_ht_operation,
1664                                u32 rate_set, u8 hlid)
1665 {
1666         return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1667                                               hlid);
1668 }
1669
1670 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1671                                  struct wl1271_link *lnk)
1672 {
1673         u8 thold;
1674
1675         if (test_bit(hlid, &wl->fw_fast_lnk_map))
1676                 thold = wl->conf.tx.fast_link_thold;
1677         else
1678                 thold = wl->conf.tx.slow_link_thold;
1679
1680         return lnk->allocated_pkts < thold;
1681 }
1682
1683 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1684                                 struct wl1271_link *lnk)
1685 {
1686         /* any link is good for low priority */
1687         return true;
1688 }
1689
1690 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1691 {
1692         return hwaddr << 5;
1693 }
1694
1695 static int wl12xx_setup(struct wl1271 *wl);
1696
1697 static struct wlcore_ops wl12xx_ops = {
1698         .setup                  = wl12xx_setup,
1699         .identify_chip          = wl12xx_identify_chip,
1700         .boot                   = wl12xx_boot,
1701         .plt_init               = wl12xx_plt_init,
1702         .trigger_cmd            = wl12xx_trigger_cmd,
1703         .ack_event              = wl12xx_ack_event,
1704         .wait_for_event         = wl12xx_wait_for_event,
1705         .process_mailbox_events = wl12xx_process_mailbox_events,
1706         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1707         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1708         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1709         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1710         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1711         .tx_immediate_compl     = NULL,
1712         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1713         .hw_init                = wl12xx_hw_init,
1714         .init_vif               = NULL,
1715         .convert_fw_status      = wl12xx_convert_fw_status,
1716         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1717         .get_pg_ver             = wl12xx_get_pg_ver,
1718         .get_mac                = wl12xx_get_mac,
1719         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1720         .set_rx_csum            = NULL,
1721         .ap_get_mimo_wide_rate_mask = NULL,
1722         .debugfs_init           = wl12xx_debugfs_add_files,
1723         .scan_start             = wl12xx_scan_start,
1724         .scan_stop              = wl12xx_scan_stop,
1725         .sched_scan_start       = wl12xx_sched_scan_start,
1726         .sched_scan_stop        = wl12xx_scan_sched_scan_stop,
1727         .get_spare_blocks       = wl12xx_get_spare_blocks,
1728         .set_key                = wl12xx_set_key,
1729         .channel_switch         = wl12xx_cmd_channel_switch,
1730         .pre_pkt_send           = NULL,
1731         .set_peer_cap           = wl12xx_set_peer_cap,
1732         .convert_hwaddr         = wl12xx_convert_hwaddr,
1733         .lnk_high_prio          = wl12xx_lnk_high_prio,
1734         .lnk_low_prio           = wl12xx_lnk_low_prio,
1735         .interrupt_notify       = NULL,
1736         .rx_ba_filter           = NULL,
1737         .ap_sleep               = NULL,
1738 };
1739
1740 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1741         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1742                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1743         .ht_supported = true,
1744         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1745         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1746         .mcs = {
1747                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1748                 .rx_highest = cpu_to_le16(72),
1749                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1750                 },
1751 };
1752
1753 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1754         {
1755                 .max = 3,
1756                 .types = BIT(NL80211_IFTYPE_STATION),
1757         },
1758         {
1759                 .max = 1,
1760                 .types = BIT(NL80211_IFTYPE_AP) |
1761                          BIT(NL80211_IFTYPE_P2P_GO) |
1762                          BIT(NL80211_IFTYPE_P2P_CLIENT),
1763         },
1764 };
1765
1766 static const struct ieee80211_iface_combination
1767 wl12xx_iface_combinations[] = {
1768         {
1769                 .max_interfaces = 3,
1770                 .limits = wl12xx_iface_limits,
1771                 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1772                 .num_different_channels = 1,
1773         },
1774 };
1775
1776 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1777         { 19200000,     false,  WL12XX_REFCLOCK_19      },
1778         { 26000000,     false,  WL12XX_REFCLOCK_26      },
1779         { 26000000,     true,   WL12XX_REFCLOCK_26_XTAL },
1780         { 38400000,     false,  WL12XX_REFCLOCK_38      },
1781         { 38400000,     true,   WL12XX_REFCLOCK_38_XTAL },
1782         { 52000000,     false,  WL12XX_REFCLOCK_52      },
1783         { 0,            false,  0 }
1784 };
1785
1786 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1787         { 16368000,     true,   WL12XX_TCXOCLOCK_16_368 },
1788         { 16800000,     true,   WL12XX_TCXOCLOCK_16_8   },
1789         { 19200000,     true,   WL12XX_TCXOCLOCK_19_2   },
1790         { 26000000,     true,   WL12XX_TCXOCLOCK_26     },
1791         { 32736000,     true,   WL12XX_TCXOCLOCK_32_736 },
1792         { 33600000,     true,   WL12XX_TCXOCLOCK_33_6   },
1793         { 38400000,     true,   WL12XX_TCXOCLOCK_38_4   },
1794         { 52000000,     true,   WL12XX_TCXOCLOCK_52     },
1795         { 0,            false,  0 }
1796 };
1797
1798 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1799                                 u32 freq, bool xtal)
1800 {
1801         int i;
1802
1803         for (i = 0; table[i].freq != 0; i++)
1804                 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1805                         return table[i].hw_idx;
1806
1807         return -EINVAL;
1808 }
1809
1810 static int wl12xx_setup(struct wl1271 *wl)
1811 {
1812         struct wl12xx_priv *priv = wl->priv;
1813         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1814
1815         BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1816         BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1817         BUILD_BUG_ON(WL12XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1818
1819         wl->rtable = wl12xx_rtable;
1820         wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1821         wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1822         wl->num_links = WL12XX_MAX_LINKS;
1823         wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1824         wl->iface_combinations = wl12xx_iface_combinations;
1825         wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1826         wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1827         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1828         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1829         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1830         wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1831         wl->fw_status_priv_len = 0;
1832         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1833         wl->ofdm_only_ap = true;
1834         wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, &wl12xx_ht_cap);
1835         wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, &wl12xx_ht_cap);
1836         wl12xx_conf_init(wl);
1837
1838         if (!fref_param) {
1839                 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1840                                                 pdev_data->ref_clock_freq,
1841                                                 pdev_data->ref_clock_xtal);
1842                 if (priv->ref_clock < 0) {
1843                         wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1844                                      pdev_data->ref_clock_freq,
1845                                      pdev_data->ref_clock_xtal ?
1846                                      "XTAL" : "not XTAL");
1847
1848                         return priv->ref_clock;
1849                 }
1850         } else {
1851                 if (!strcmp(fref_param, "19.2"))
1852                         priv->ref_clock = WL12XX_REFCLOCK_19;
1853                 else if (!strcmp(fref_param, "26"))
1854                         priv->ref_clock = WL12XX_REFCLOCK_26;
1855                 else if (!strcmp(fref_param, "26x"))
1856                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1857                 else if (!strcmp(fref_param, "38.4"))
1858                         priv->ref_clock = WL12XX_REFCLOCK_38;
1859                 else if (!strcmp(fref_param, "38.4x"))
1860                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1861                 else if (!strcmp(fref_param, "52"))
1862                         priv->ref_clock = WL12XX_REFCLOCK_52;
1863                 else
1864                         wl1271_error("Invalid fref parameter %s", fref_param);
1865         }
1866
1867         if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1868                 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1869                                                 pdev_data->tcxo_clock_freq,
1870                                                 true);
1871                 if (priv->tcxo_clock < 0) {
1872                         wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1873                                      pdev_data->tcxo_clock_freq);
1874
1875                         return priv->tcxo_clock;
1876                 }
1877         } else if (tcxo_param) {
1878                 if (!strcmp(tcxo_param, "19.2"))
1879                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1880                 else if (!strcmp(tcxo_param, "26"))
1881                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1882                 else if (!strcmp(tcxo_param, "38.4"))
1883                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1884                 else if (!strcmp(tcxo_param, "52"))
1885                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1886                 else if (!strcmp(tcxo_param, "16.368"))
1887                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1888                 else if (!strcmp(tcxo_param, "32.736"))
1889                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1890                 else if (!strcmp(tcxo_param, "16.8"))
1891                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1892                 else if (!strcmp(tcxo_param, "33.6"))
1893                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1894                 else
1895                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1896         }
1897
1898         priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1899         if (!priv->rx_mem_addr)
1900                 return -ENOMEM;
1901
1902         return 0;
1903 }
1904
1905 static int wl12xx_probe(struct platform_device *pdev)
1906 {
1907         struct wl1271 *wl;
1908         struct ieee80211_hw *hw;
1909         int ret;
1910
1911         hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1912                              WL12XX_AGGR_BUFFER_SIZE,
1913                              sizeof(struct wl12xx_event_mailbox));
1914         if (IS_ERR(hw)) {
1915                 wl1271_error("can't allocate hw");
1916                 ret = PTR_ERR(hw);
1917                 goto out;
1918         }
1919
1920         wl = hw->priv;
1921         wl->ops = &wl12xx_ops;
1922         wl->ptable = wl12xx_ptable;
1923         ret = wlcore_probe(wl, pdev);
1924         if (ret)
1925                 goto out_free;
1926
1927         return ret;
1928
1929 out_free:
1930         wlcore_free_hw(wl);
1931 out:
1932         return ret;
1933 }
1934
1935 static int wl12xx_remove(struct platform_device *pdev)
1936 {
1937         struct wl1271 *wl = platform_get_drvdata(pdev);
1938         struct wl12xx_priv *priv;
1939
1940         if (!wl)
1941                 goto out;
1942         priv = wl->priv;
1943
1944         kfree(priv->rx_mem_addr);
1945
1946 out:
1947         return wlcore_remove(pdev);
1948 }
1949
1950 static const struct platform_device_id wl12xx_id_table[] = {
1951         { "wl12xx", 0 },
1952         {  } /* Terminating Entry */
1953 };
1954 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1955
1956 static struct platform_driver wl12xx_driver = {
1957         .probe          = wl12xx_probe,
1958         .remove         = wl12xx_remove,
1959         .id_table       = wl12xx_id_table,
1960         .driver = {
1961                 .name   = "wl12xx_driver",
1962         }
1963 };
1964
1965 module_platform_driver(wl12xx_driver);
1966
1967 module_param_named(fref, fref_param, charp, 0);
1968 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1969
1970 module_param_named(tcxo, tcxo_param, charp, 0);
1971 MODULE_PARM_DESC(tcxo,
1972                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1973
1974 MODULE_LICENSE("GPL v2");
1975 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1976 /*(DEBLOBBED)*/