drivers/net/wireless/ti/wl12xx/main.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/platform_device.h>
  25
  26 #include <linux/err.h>
  27
  28 #include "../wlcore/wlcore.h"
  29 #include "../wlcore/debug.h"
  30 #include "../wlcore/io.h"
  31 #include "../wlcore/acx.h"
  32 #include "../wlcore/tx.h"
  33 #include "../wlcore/rx.h"
  34 #include "../wlcore/boot.h"
  35
  36 #include "wl12xx.h"
  37 #include "reg.h"
  38 #include "cmd.h"
  39 #include "acx.h"
  40 #include "scan.h"
  41 #include "event.h"
  42 #include "debugfs.h"
  43 #include "conf.h"
  44
  45 static char *fref_param;
  46 static char *tcxo_param;
  47
  48 static struct wlcore_conf wl12xx_conf = {
  49         .sg = {
  50                 .params = {
  51                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  52                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  53                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  54                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  55                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  56                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  57                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  58                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  59                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  60                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  61                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  62                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  63                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  64                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  65                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  66                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  67                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  68                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  69                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  70                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  71                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  72                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  73                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  74                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  75                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  76                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  77                         /* active scan params */
  78                         [WL12XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  79                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  80                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  81                         /* passive scan params */
  82                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_BR] = 800,
  83                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_EDR] = 200,
  84                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_HV3] = 200,
  85                         /* passive scan in dual antenna params */
  86                         [WL12XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  87                         [WL12XX_CONF_SG_BCN_HV3_COLL_THR_IN_PASSIVE_SCAN] = 0,
  88                         [WL12XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
  89                         /* general params */
  90                         [WL12XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  91                         [WL12XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
  92                         [WL12XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
  93                         [WL12XX_CONF_SG_DHCP_TIME] = 5000,
  94                         [WL12XX_CONF_SG_RXT] = 1200,
  95                         [WL12XX_CONF_SG_TXT] = 1000,
  96                         [WL12XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  97                         [WL12XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  98                         [WL12XX_CONF_SG_HV3_MAX_SERVED] = 6,
  99                         [WL12XX_CONF_SG_PS_POLL_TIMEOUT] = 10,
 100                         [WL12XX_CONF_SG_UPSD_TIMEOUT] = 10,
 101                         [WL12XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 102                         [WL12XX_CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 103                         [WL12XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 104                         /* AP params */
 105                         [WL12XX_CONF_AP_BEACON_MISS_TX] = 3,
 106                         [WL12XX_CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 107                         [WL12XX_CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 108                         [WL12XX_CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 109                         [WL12XX_CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 110                         [WL12XX_CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 111                         /* CTS Diluting params */
 112                         [WL12XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 113                         [WL12XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 114                 },
 115                 .state = CONF_SG_PROTECTIVE,
 116         },
 117         .rx = {
 118                 .rx_msdu_life_time           = 512000,
 119                 .packet_detection_threshold  = 0,
 120                 .ps_poll_timeout             = 15,
 121                 .upsd_timeout                = 15,
 122                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 123                 .rx_cca_threshold            = 0,
 124                 .irq_blk_threshold           = 0xFFFF,
 125                 .irq_pkt_threshold           = 0,
 126                 .irq_timeout                 = 600,
 127                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 128         },
 129         .tx = {
 130                 .tx_energy_detection         = 0,
 131                 .sta_rc_conf                 = {
 132                         .enabled_rates       = 0,
 133                         .short_retry_limit   = 10,
 134                         .long_retry_limit    = 10,
 135                         .aflags              = 0,
 136                 },
 137                 .ac_conf_count               = 4,
 138                 .ac_conf                     = {
 139                         [CONF_TX_AC_BE] = {
 140                                 .ac          = CONF_TX_AC_BE,
 141                                 .cw_min      = 15,
 142                                 .cw_max      = 63,
 143                                 .aifsn       = 3,
 144                                 .tx_op_limit = 0,
 145                         },
 146                         [CONF_TX_AC_BK] = {
 147                                 .ac          = CONF_TX_AC_BK,
 148                                 .cw_min      = 15,
 149                                 .cw_max      = 63,
 150                                 .aifsn       = 7,
 151                                 .tx_op_limit = 0,
 152                         },
 153                         [CONF_TX_AC_VI] = {
 154                                 .ac          = CONF_TX_AC_VI,
 155                                 .cw_min      = 15,
 156                                 .cw_max      = 63,
 157                                 .aifsn       = CONF_TX_AIFS_PIFS,
 158                                 .tx_op_limit = 3008,
 159                         },
 160                         [CONF_TX_AC_VO] = {
 161                                 .ac          = CONF_TX_AC_VO,
 162                                 .cw_min      = 15,
 163                                 .cw_max      = 63,
 164                                 .aifsn       = CONF_TX_AIFS_PIFS,
 165                                 .tx_op_limit = 1504,
 166                         },
 167                 },
 168                 .max_tx_retries = 100,
 169                 .ap_aging_period = 300,
 170                 .tid_conf_count = 4,
 171                 .tid_conf = {
 172                         [CONF_TX_AC_BE] = {
 173                                 .queue_id    = CONF_TX_AC_BE,
 174                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 175                                 .tsid        = CONF_TX_AC_BE,
 176                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 177                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 178                                 .apsd_conf   = {0, 0},
 179                         },
 180                         [CONF_TX_AC_BK] = {
 181                                 .queue_id    = CONF_TX_AC_BK,
 182                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 183                                 .tsid        = CONF_TX_AC_BK,
 184                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 185                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 186                                 .apsd_conf   = {0, 0},
 187                         },
 188                         [CONF_TX_AC_VI] = {
 189                                 .queue_id    = CONF_TX_AC_VI,
 190                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 191                                 .tsid        = CONF_TX_AC_VI,
 192                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 193                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 194                                 .apsd_conf   = {0, 0},
 195                         },
 196                         [CONF_TX_AC_VO] = {
 197                                 .queue_id    = CONF_TX_AC_VO,
 198                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 199                                 .tsid        = CONF_TX_AC_VO,
 200                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 201                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 202                                 .apsd_conf   = {0, 0},
 203                         },
 204                 },
 205                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 206                 .tx_compl_timeout            = 700,
 207                 .tx_compl_threshold          = 4,
 208                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 209                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 210                 .tmpl_short_retry_limit      = 10,
 211                 .tmpl_long_retry_limit       = 10,
 212                 .tx_watchdog_timeout         = 5000,
 213                 .slow_link_thold             = 3,
 214                 .fast_link_thold             = 10,
 215         },
 216         .conn = {
 217                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 218                 .listen_interval             = 1,
 219                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 220                 .suspend_listen_interval     = 3,
 221                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 222                 .bcn_filt_ie_count           = 3,
 223                 .bcn_filt_ie = {
 224                         [0] = {
 225                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 226                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 227                         },
 228                         [1] = {
 229                                 .ie          = WLAN_EID_HT_OPERATION,
 230                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 231                         },
 232                         [2] = {
 233                                 .ie          = WLAN_EID_ERP_INFO,
 234                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 235                         },
 236                 },
 237                 .synch_fail_thold            = 12,
 238                 .bss_lose_timeout            = 400,
 239                 .beacon_rx_timeout           = 10000,
 240                 .broadcast_timeout           = 20000,
 241                 .rx_broadcast_in_ps          = 1,
 242                 .ps_poll_threshold           = 10,
 243                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 244                 .bet_max_consecutive         = 50,
 245                 .psm_entry_retries           = 8,
 246                 .psm_exit_retries            = 16,
 247                 .psm_entry_nullfunc_retries  = 3,
 248                 .dynamic_ps_timeout          = 1500,
 249                 .forced_ps                   = false,
 250                 .keep_alive_interval         = 55000,
 251                 .max_listen_interval         = 20,
 252                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 253                 .suspend_rx_ba_activity      = 0,
 254         },
 255         .itrim = {
 256                 .enable = false,
 257                 .timeout = 50000,
 258         },
 259         .pm_config = {
 260                 .host_clk_settling_time = 5000,
 261                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 262         },
 263         .roam_trigger = {
 264                 .trigger_pacing               = 1,
 265                 .avg_weight_rssi_beacon       = 20,
 266                 .avg_weight_rssi_data         = 10,
 267                 .avg_weight_snr_beacon        = 20,
 268                 .avg_weight_snr_data          = 10,
 269         },
 270         .scan = {
 271                 .min_dwell_time_active        = 7500,
 272                 .max_dwell_time_active        = 30000,
 273                 .min_dwell_time_active_long   = 25000,
 274                 .max_dwell_time_active_long   = 50000,
 275                 .dwell_time_passive           = 100000,
 276                 .dwell_time_dfs               = 150000,
 277                 .num_probe_reqs               = 2,
 278                 .split_scan_timeout           = 50000,
 279         },
 280         .sched_scan = {
 281                 /*
 282                  * Values are in TU/1000 but since sched scan FW command
 283                  * params are in TUs rounding up may occur.
 284                  */
 285                 .base_dwell_time                = 7500,
 286                 .max_dwell_time_delta           = 22500,
 287                 /* based on 250bits per probe @1Mbps */
 288                 .dwell_time_delta_per_probe     = 2000,
 289                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 290                 .dwell_time_delta_per_probe_5   = 350,
 291                 .dwell_time_passive             = 100000,
 292                 .dwell_time_dfs                 = 150000,
 293                 .num_probe_reqs                 = 2,
 294                 .rssi_threshold                 = -90,
 295                 .snr_threshold                  = 0,
 296         },
 297         .ht = {
 298                 .rx_ba_win_size = 8,
 299                 .tx_ba_win_size = 64,
 300                 .inactivity_timeout = 10000,
 301                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 302         },
 303         /*
 304          * Memory config for wl127x chips is given in the
 305          * wl12xx_default_priv_conf struct. The below configuration is
 306          * for wl128x chips.
 307          */
 308         .mem = {
 309                 .num_stations                 = 1,
 310                 .ssid_profiles                = 1,
 311                 .rx_block_num                 = 40,
 312                 .tx_min_block_num             = 40,
 313                 .dynamic_memory               = 1,
 314                 .min_req_tx_blocks            = 45,
 315                 .min_req_rx_blocks            = 22,
 316                 .tx_min                       = 27,
 317         },
 318         .fm_coex = {
 319                 .enable                       = true,
 320                 .swallow_period               = 5,
 321                 .n_divider_fref_set_1         = 0xff,       /* default */
 322                 .n_divider_fref_set_2         = 12,
 323                 .m_divider_fref_set_1         = 0xffff,
 324                 .m_divider_fref_set_2         = 148,        /* default */
 325                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 326                 .ldo_stabilization_time       = 0xffff,     /* default */
 327                 .fm_disturbed_band_margin     = 0xff,       /* default */
 328                 .swallow_clk_diff             = 0xff,       /* default */
 329         },
 330         .rx_streaming = {
 331                 .duration                      = 150,
 332                 .queues                        = 0x1,
 333                 .interval                      = 20,
 334                 .always                        = 0,
 335         },
 336         .fwlog = {
 337                 .mode                         = WL12XX_FWLOG_CONTINUOUS,
 338                 .mem_blocks                   = 2,
 339                 .severity                     = 0,
 340                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 341                 .output                       = WL12XX_FWLOG_OUTPUT_DBG_PINS,
 342                 .threshold                    = 0,
 343         },
 344         .rate = {
 345                 .rate_retry_score = 32000,
 346                 .per_add = 8192,
 347                 .per_th1 = 2048,
 348                 .per_th2 = 4096,
 349                 .max_per = 8100,
 350                 .inverse_curiosity_factor = 5,
 351                 .tx_fail_low_th = 4,
 352                 .tx_fail_high_th = 10,
 353                 .per_alpha_shift = 4,
 354                 .per_add_shift = 13,
 355                 .per_beta1_shift = 10,
 356                 .per_beta2_shift = 8,
 357                 .rate_check_up = 2,
 358                 .rate_check_down = 12,
 359                 .rate_retry_policy = {
 360                         0x00, 0x00, 0x00, 0x00, 0x00,
 361                         0x00, 0x00, 0x00, 0x00, 0x00,
 362                         0x00, 0x00, 0x00,
 363                 },
 364         },
 365         .hangover = {
 366                 .recover_time               = 0,
 367                 .hangover_period            = 20,
 368                 .dynamic_mode               = 1,
 369                 .early_termination_mode     = 1,
 370                 .max_period                 = 20,
 371                 .min_period                 = 1,
 372                 .increase_delta             = 1,
 373                 .decrease_delta             = 2,
 374                 .quiet_time                 = 4,
 375                 .increase_time              = 1,
 376                 .window_size                = 16,
 377         },
 378         .recovery = {
 379                 .bug_on_recovery            = 0,
 380                 .no_recovery                = 0,
 381         },
 382 };
 383
 384 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 385         .rf = {
 386                 .tx_per_channel_power_compensation_2 = {
 387                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 388                 },
 389                 .tx_per_channel_power_compensation_5 = {
 390                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 391                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 392                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 393                 },
 394         },
 395         .mem_wl127x = {
 396                 .num_stations                 = 1,
 397                 .ssid_profiles                = 1,
 398                 .rx_block_num                 = 70,
 399                 .tx_min_block_num             = 40,
 400                 .dynamic_memory               = 1,
 401                 .min_req_tx_blocks            = 100,
 402                 .min_req_rx_blocks            = 22,
 403                 .tx_min                       = 27,
 404         },
 405
 406 };
 407
 408 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 409 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 410 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 411
 412 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 413         /* MCS rates are used only with 11n */
 414         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 415         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 416         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 417         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 418         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 419         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 420         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 421         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 422         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 423
 424         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 425         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 426         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 427         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 428
 429         /* TI-specific rate */
 430         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 431
 432         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 433         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 434         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 435         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 436         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 437         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 438         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 439         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 440 };
 441
 442 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 443         /* MCS rates are used only with 11n */
 444         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 445         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 446         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 447         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 448         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 449         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 450         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 451         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 452         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 453
 454         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 455         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 456         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 457         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 458
 459         /* TI-specific rate */
 460         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 461
 462         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 463         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 464         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 465         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 466         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 467         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 468         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 469         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 470 };
 471
 472 static const u8 *wl12xx_band_rate_to_idx[] = {
 473         [NL80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 474         [NL80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 475 };
 476
 477 enum wl12xx_hw_rates {
 478         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 479         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 480         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 481         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 482         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 483         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 484         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 485         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 486         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 487         WL12XX_CONF_HW_RXTX_RATE_54,
 488         WL12XX_CONF_HW_RXTX_RATE_48,
 489         WL12XX_CONF_HW_RXTX_RATE_36,
 490         WL12XX_CONF_HW_RXTX_RATE_24,
 491         WL12XX_CONF_HW_RXTX_RATE_22,
 492         WL12XX_CONF_HW_RXTX_RATE_18,
 493         WL12XX_CONF_HW_RXTX_RATE_12,
 494         WL12XX_CONF_HW_RXTX_RATE_11,
 495         WL12XX_CONF_HW_RXTX_RATE_9,
 496         WL12XX_CONF_HW_RXTX_RATE_6,
 497         WL12XX_CONF_HW_RXTX_RATE_5_5,
 498         WL12XX_CONF_HW_RXTX_RATE_2,
 499         WL12XX_CONF_HW_RXTX_RATE_1,
 500         WL12XX_CONF_HW_RXTX_RATE_MAX,
 501 };
 502
 503 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 504         [PART_DOWN] = {
 505                 .mem = {
 506                         .start = 0x00000000,
 507                         .size  = 0x000177c0
 508                 },
 509                 .reg = {
 510                         .start = REGISTERS_BASE,
 511                         .size  = 0x00008800
 512                 },
 513                 .mem2 = {
 514                         .start = 0x00000000,
 515                         .size  = 0x00000000
 516                 },
 517                 .mem3 = {
 518                         .start = 0x00000000,
 519                         .size  = 0x00000000
 520                 },
 521         },
 522
 523         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 524                          * partition here */
 525                 .mem = {
 526                         .start = 0x00040000,
 527                         .size  = 0x00014fc0
 528                 },
 529                 .reg = {
 530                         .start = REGISTERS_BASE,
 531                         .size  = 0x00008800
 532                 },
 533                 .mem2 = {
 534                         .start = 0x00000000,
 535                         .size  = 0x00000000
 536                 },
 537                 .mem3 = {
 538                         .start = 0x00000000,
 539                         .size  = 0x00000000
 540                 },
 541         },
 542
 543         [PART_WORK] = {
 544                 .mem = {
 545                         .start = 0x00040000,
 546                         .size  = 0x00014fc0
 547                 },
 548                 .reg = {
 549                         .start = REGISTERS_BASE,
 550                         .size  = 0x0000a000
 551                 },
 552                 .mem2 = {
 553                         .start = 0x003004f8,
 554                         .size  = 0x00000004
 555                 },
 556                 .mem3 = {
 557                         .start = 0x00000000,
 558                         .size  = 0x00040404
 559                 },
 560         },
 561
 562         [PART_DRPW] = {
 563                 .mem = {
 564                         .start = 0x00040000,
 565                         .size  = 0x00014fc0
 566                 },
 567                 .reg = {
 568                         .start = DRPW_BASE,
 569                         .size  = 0x00006000
 570                 },
 571                 .mem2 = {
 572                         .start = 0x00000000,
 573                         .size  = 0x00000000
 574                 },
 575                 .mem3 = {
 576                         .start = 0x00000000,
 577                         .size  = 0x00000000
 578                 }
 579         }
 580 };
 581
 582 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 583         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 584         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 585         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 586         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 587         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 588         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 589         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 590         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 591         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 592         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 593
 594         /* data access memory addresses, used with partition translation */
 595         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 596         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 597
 598         /* raw data access memory addresses */
 599         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 600 };
 601
 602 /* TODO: maybe move to a new header file? */
 603 #define WL127X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 604 #define WL127X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 605 #define WL127X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 606
 607 #define WL128X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 608 #define WL128X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 609 #define WL128X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 610
 611 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 612 {
 613         int ret;
 614
 615         if (wl->chip.id != CHIP_ID_128X_PG20) {
 616                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 617                 struct wl12xx_priv *priv = wl->priv;
 618
 619                 /*
 620                  * Choose the block we want to read
 621                  * For aggregated packets, only the first memory block
 622                  * should be retrieved. The FW takes care of the rest.
 623                  */
 624                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 625
 626                 priv->rx_mem_addr->addr = (mem_block << 8) +
 627                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 628
 629                 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
 630
 631                 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
 632                                    sizeof(*priv->rx_mem_addr), false);
 633                 if (ret < 0)
 634                         return ret;
 635         }
 636
 637         return 0;
 638 }
 639
 640 static int wl12xx_identify_chip(struct wl1271 *wl)
 641 {
 642         int ret = 0;
 643
 644         switch (wl->chip.id) {
 645         case CHIP_ID_127X_PG10:
 646                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 647                                wl->chip.id);
 648
 649                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 650                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 651                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 652                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 653                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 654                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 655                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 656                        sizeof(wl->conf.mem));
 657
 658                 /* read data preparation is only needed by wl127x */
 659                 wl->ops->prepare_read = wl127x_prepare_read;
 660
 661                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 662                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 663                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 664                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 665                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 666                 break;
 667
 668         case CHIP_ID_127X_PG20:
 669                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 670                              wl->chip.id);
 671
 672                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 673                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 674                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 675                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 676                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 677                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 678                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 679                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 680                        sizeof(wl->conf.mem));
 681
 682                 /* read data preparation is only needed by wl127x */
 683                 wl->ops->prepare_read = wl127x_prepare_read;
 684
 685                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 686                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 687                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 688                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 689                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 690                 break;
 691
 692         case CHIP_ID_128X_PG20:
 693                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 694                              wl->chip.id);
 695                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 696                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 697                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 698
 699                 /* wl128x requires TX blocksize alignment */
 700                 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 701                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 702                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 703                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 704
 705                 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
 706                               WL128X_IFTYPE_SR_VER,  WL128X_MAJOR_SR_VER,
 707                               WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
 708                               WL128X_IFTYPE_MR_VER,  WL128X_MAJOR_MR_VER,
 709                               WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
 710                 break;
 711         case CHIP_ID_128X_PG10:
 712         default:
 713                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 714                 ret = -ENODEV;
 715                 goto out;
 716         }
 717
 718         wl->fw_mem_block_size = 256;
 719         wl->fwlog_end = 0x2000000;
 720
 721         /* common settings */
 722         wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
 723         wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
 724         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 725         wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 726         wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
 727         wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
 728 out:
 729         return ret;
 730 }
 731
 732 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
 733                                              u16 val)
 734 {
 735         int ret;
 736
 737         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 738         addr = (addr >> 1) + 0x30000;
 739         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 740         if (ret < 0)
 741                 goto out;
 742
 743         /* write value to OCP_POR_WDATA */
 744         ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 745         if (ret < 0)
 746                 goto out;
 747
 748         /* write 1 to OCP_CMD */
 749         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 750         if (ret < 0)
 751                 goto out;
 752
 753 out:
 754         return ret;
 755 }
 756
 757 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
 758                                             u16 *out)
 759 {
 760         u32 val;
 761         int timeout = OCP_CMD_LOOP;
 762         int ret;
 763
 764         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 765         addr = (addr >> 1) + 0x30000;
 766         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 767         if (ret < 0)
 768                 return ret;
 769
 770         /* write 2 to OCP_CMD */
 771         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 772         if (ret < 0)
 773                 return ret;
 774
 775         /* poll for data ready */
 776         do {
 777                 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
 778                 if (ret < 0)
 779                         return ret;
 780         } while (!(val & OCP_READY_MASK) && --timeout);
 781
 782         if (!timeout) {
 783                 wl1271_warning("Top register access timed out.");
 784                 return -ETIMEDOUT;
 785         }
 786
 787         /* check data status and return if OK */
 788         if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
 789                 wl1271_warning("Top register access returned error.");
 790                 return -EIO;
 791         }
 792
 793         if (out)
 794                 *out = val & 0xffff;
 795
 796         return 0;
 797 }
 798
 799 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 800 {
 801         u16 spare_reg;
 802         int ret;
 803
 804         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 805         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 806         if (ret < 0)
 807                 return ret;
 808
 809         if (spare_reg == 0xFFFF)
 810                 return -EFAULT;
 811         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 812         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 813         if (ret < 0)
 814                 return ret;
 815
 816         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 817         ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 818                                    WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 819         if (ret < 0)
 820                 return ret;
 821
 822         /* Delay execution for 15msec, to let the HW settle */
 823         mdelay(15);
 824
 825         return 0;
 826 }
 827
 828 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 829 {
 830         u16 tcxo_detection;
 831         int ret;
 832
 833         ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
 834         if (ret < 0)
 835                 return false;
 836
 837         if (tcxo_detection & TCXO_DET_FAILED)
 838                 return false;
 839
 840         return true;
 841 }
 842
 843 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 844 {
 845         u16 fref_detection;
 846         int ret;
 847
 848         ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
 849         if (ret < 0)
 850                 return false;
 851
 852         if (fref_detection & FREF_CLK_DETECT_FAIL)
 853                 return false;
 854
 855         return true;
 856 }
 857
 858 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 859 {
 860         int ret;
 861
 862         ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 863         if (ret < 0)
 864                 goto out;
 865
 866         ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 867         if (ret < 0)
 868                 goto out;
 869
 870         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 871                                    MCS_PLL_CONFIG_REG_VAL);
 872
 873 out:
 874         return ret;
 875 }
 876
 877 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 878 {
 879         u16 spare_reg;
 880         u16 pll_config;
 881         u8 input_freq;
 882         struct wl12xx_priv *priv = wl->priv;
 883         int ret;
 884
 885         /* Mask bits [3:1] in the sys_clk_cfg register */
 886         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 887         if (ret < 0)
 888                 return ret;
 889
 890         if (spare_reg == 0xFFFF)
 891                 return -EFAULT;
 892         spare_reg |= BIT(2);
 893         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 894         if (ret < 0)
 895                 return ret;
 896
 897         /* Handle special cases of the TCXO clock */
 898         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 899             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 900                 return wl128x_manually_configure_mcs_pll(wl);
 901
 902         /* Set the input frequency according to the selected clock source */
 903         input_freq = (clk & 1) + 1;
 904
 905         ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
 906         if (ret < 0)
 907                 return ret;
 908
 909         if (pll_config == 0xFFFF)
 910                 return -EFAULT;
 911         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 912         pll_config |= MCS_PLL_ENABLE_HP;
 913         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 914
 915         return ret;
 916 }
 917
 918 /*
 919  * WL128x has two clocks input - TCXO and FREF.
 920  * TCXO is the main clock of the device, while FREF is used to sync
 921  * between the GPS and the cellular modem.
 922  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 923  * as the WLAN/BT main clock.
 924  */
 925 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 926 {
 927         struct wl12xx_priv *priv = wl->priv;
 928         u16 sys_clk_cfg;
 929         int ret;
 930
 931         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 932         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 933             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 934                 if (!wl128x_switch_tcxo_to_fref(wl))
 935                         return -EINVAL;
 936                 goto fref_clk;
 937         }
 938
 939         /* Query the HW, to determine which clock source we should use */
 940         ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
 941         if (ret < 0)
 942                 return ret;
 943
 944         if (sys_clk_cfg == 0xFFFF)
 945                 return -EINVAL;
 946         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 947                 goto fref_clk;
 948
 949         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 950         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 951             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 952                 if (!wl128x_switch_tcxo_to_fref(wl))
 953                         return -EINVAL;
 954                 goto fref_clk;
 955         }
 956
 957         /* TCXO clock is selected */
 958         if (!wl128x_is_tcxo_valid(wl))
 959                 return -EINVAL;
 960         *selected_clock = priv->tcxo_clock;
 961         goto config_mcs_pll;
 962
 963 fref_clk:
 964         /* FREF clock is selected */
 965         if (!wl128x_is_fref_valid(wl))
 966                 return -EINVAL;
 967         *selected_clock = priv->ref_clock;
 968
 969 config_mcs_pll:
 970         return wl128x_configure_mcs_pll(wl, *selected_clock);
 971 }
 972
 973 static int wl127x_boot_clk(struct wl1271 *wl)
 974 {
 975         struct wl12xx_priv *priv = wl->priv;
 976         u32 pause;
 977         u32 clk;
 978         int ret;
 979
 980         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 981                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 982
 983         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 984             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 985             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 986                 /* ref clk: 19.2/38.4/38.4-XTAL */
 987                 clk = 0x3;
 988         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 989                  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
 990                  priv->ref_clock == CONF_REF_CLK_52_E)
 991                 /* ref clk: 26/52 */
 992                 clk = 0x5;
 993         else
 994                 return -EINVAL;
 995
 996         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 997                 u16 val;
 998                 /* Set clock type (open drain) */
 999                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
1000                 if (ret < 0)
1001                         goto out;
1002
1003                 val &= FREF_CLK_TYPE_BITS;
1004                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
1005                 if (ret < 0)
1006                         goto out;
1007
1008                 /* Set clock pull mode (no pull) */
1009                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1010                 if (ret < 0)
1011                         goto out;
1012
1013                 val |= NO_PULL;
1014                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1015                 if (ret < 0)
1016                         goto out;
1017         } else {
1018                 u16 val;
1019                 /* Set clock polarity */
1020                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1021                 if (ret < 0)
1022                         goto out;
1023
1024                 val &= FREF_CLK_POLARITY_BITS;
1025                 val |= CLK_REQ_OUTN_SEL;
1026                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1027                 if (ret < 0)
1028                         goto out;
1029         }
1030
1031         ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1032         if (ret < 0)
1033                 goto out;
1034
1035         ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1036         if (ret < 0)
1037                 goto out;
1038
1039         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1040
1041         pause &= ~(WU_COUNTER_PAUSE_VAL);
1042         pause |= WU_COUNTER_PAUSE_VAL;
1043         ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1044
1045 out:
1046         return ret;
1047 }
1048
1049 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1050 {
1051         unsigned long timeout;
1052         u32 boot_data;
1053         int ret = 0;
1054
1055         /* perform soft reset */
1056         ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1057         if (ret < 0)
1058                 goto out;
1059
1060         /* SOFT_RESET is self clearing */
1061         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1062         while (1) {
1063                 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1064                 if (ret < 0)
1065                         goto out;
1066
1067                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1068                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1069                         break;
1070
1071                 if (time_after(jiffies, timeout)) {
1072                         /* 1.2 check pWhalBus->uSelfClearTime if the
1073                          * timeout was reached */
1074                         wl1271_error("soft reset timeout");
1075                         return -1;
1076                 }
1077
1078                 udelay(SOFT_RESET_STALL_TIME);
1079         }
1080
1081         /* disable Rx/Tx */
1082         ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1083         if (ret < 0)
1084                 goto out;
1085
1086         /* disable auto calibration on start*/
1087         ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1088
1089 out:
1090         return ret;
1091 }
1092
1093 static int wl12xx_pre_boot(struct wl1271 *wl)
1094 {
1095         struct wl12xx_priv *priv = wl->priv;
1096         int ret = 0;
1097         u32 clk;
1098         int selected_clock = -1;
1099
1100         if (wl->chip.id == CHIP_ID_128X_PG20) {
1101                 ret = wl128x_boot_clk(wl, &selected_clock);
1102                 if (ret < 0)
1103                         goto out;
1104         } else {
1105                 ret = wl127x_boot_clk(wl);
1106                 if (ret < 0)
1107                         goto out;
1108         }
1109
1110         /* Continue the ELP wake up sequence */
1111         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1112         if (ret < 0)
1113                 goto out;
1114
1115         udelay(500);
1116
1117         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1118         if (ret < 0)
1119                 goto out;
1120
1121         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1122            to be used by DRPw FW. The RTRIM value will be added by the FW
1123            before taking DRPw out of reset */
1124
1125         ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1126         if (ret < 0)
1127                 goto out;
1128
1129         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1130
1131         if (wl->chip.id == CHIP_ID_128X_PG20)
1132                 clk |= ((selected_clock & 0x3) << 1) << 4;
1133         else
1134                 clk |= (priv->ref_clock << 1) << 4;
1135
1136         ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1137         if (ret < 0)
1138                 goto out;
1139
1140         ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1141         if (ret < 0)
1142                 goto out;
1143
1144         /* Disable interrupts */
1145         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1146         if (ret < 0)
1147                 goto out;
1148
1149         ret = wl1271_boot_soft_reset(wl);
1150         if (ret < 0)
1151                 goto out;
1152
1153 out:
1154         return ret;
1155 }
1156
1157 static int wl12xx_pre_upload(struct wl1271 *wl)
1158 {
1159         u32 tmp;
1160         u16 polarity;
1161         int ret;
1162
1163         /* write firmware's last address (ie. it's length) to
1164          * ACX_EEPROMLESS_IND_REG */
1165         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1166
1167         ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1168         if (ret < 0)
1169                 goto out;
1170
1171         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1172         if (ret < 0)
1173                 goto out;
1174
1175         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1176
1177         /* 6. read the EEPROM parameters */
1178         ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1179         if (ret < 0)
1180                 goto out;
1181
1182         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1183          * to upload_fw) */
1184
1185         if (wl->chip.id == CHIP_ID_128X_PG20) {
1186                 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1187                 if (ret < 0)
1188                         goto out;
1189         }
1190
1191         /* polarity must be set before the firmware is loaded */
1192         ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1193         if (ret < 0)
1194                 goto out;
1195
1196         /* We use HIGH polarity, so unset the LOW bit */
1197         polarity &= ~POLARITY_LOW;
1198         ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1199
1200 out:
1201         return ret;
1202 }
1203
1204 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1205 {
1206         int ret;
1207
1208         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1209                                WL12XX_ACX_ALL_EVENTS_VECTOR);
1210         if (ret < 0)
1211                 goto out;
1212
1213         wlcore_enable_interrupts(wl);
1214         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1215                                WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1216         if (ret < 0)
1217                 goto disable_interrupts;
1218
1219         ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1220         if (ret < 0)
1221                 goto disable_interrupts;
1222
1223         return ret;
1224
1225 disable_interrupts:
1226         wlcore_disable_interrupts(wl);
1227
1228 out:
1229         return ret;
1230 }
1231
1232 static int wl12xx_boot(struct wl1271 *wl)
1233 {
1234         int ret;
1235
1236         ret = wl12xx_pre_boot(wl);
1237         if (ret < 0)
1238                 goto out;
1239
1240         ret = wlcore_boot_upload_nvs(wl);
1241         if (ret < 0)
1242                 goto out;
1243
1244         ret = wl12xx_pre_upload(wl);
1245         if (ret < 0)
1246                 goto out;
1247
1248         ret = wlcore_boot_upload_firmware(wl);
1249         if (ret < 0)
1250                 goto out;
1251
1252         wl->event_mask = BSS_LOSE_EVENT_ID |
1253                 REGAINED_BSS_EVENT_ID |
1254                 SCAN_COMPLETE_EVENT_ID |
1255                 ROLE_STOP_COMPLETE_EVENT_ID |
1256                 RSSI_SNR_TRIGGER_0_EVENT_ID |
1257                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1258                 SOFT_GEMINI_SENSE_EVENT_ID |
1259                 PERIODIC_SCAN_REPORT_EVENT_ID |
1260                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1261                 DUMMY_PACKET_EVENT_ID |
1262                 PEER_REMOVE_COMPLETE_EVENT_ID |
1263                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1264                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1265                 INACTIVE_STA_EVENT_ID |
1266                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1267
1268         wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1269
1270         ret = wlcore_boot_run_firmware(wl);
1271         if (ret < 0)
1272                 goto out;
1273
1274         ret = wl12xx_enable_interrupts(wl);
1275
1276 out:
1277         return ret;
1278 }
1279
1280 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1281                                void *buf, size_t len)
1282 {
1283         int ret;
1284
1285         ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1286         if (ret < 0)
1287                 return ret;
1288
1289         ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1290
1291         return ret;
1292 }
1293
1294 static int wl12xx_ack_event(struct wl1271 *wl)
1295 {
1296         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1297                                 WL12XX_INTR_TRIG_EVENT_ACK);
1298 }
1299
1300 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1301 {
1302         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1303         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1304
1305         return (align_len + blk_size - 1) / blk_size + spare_blks;
1306 }
1307
1308 static void
1309 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1310                           u32 blks, u32 spare_blks)
1311 {
1312         if (wl->chip.id == CHIP_ID_128X_PG20) {
1313                 desc->wl128x_mem.total_mem_blocks = blks;
1314         } else {
1315                 desc->wl127x_mem.extra_blocks = spare_blks;
1316                 desc->wl127x_mem.total_mem_blocks = blks;
1317         }
1318 }
1319
1320 static void
1321 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1322                             struct sk_buff *skb)
1323 {
1324         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1325
1326         if (wl->chip.id == CHIP_ID_128X_PG20) {
1327                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1328                 desc->length = cpu_to_le16(aligned_len >> 2);
1329
1330                 wl1271_debug(DEBUG_TX,
1331                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1332                              desc->hlid,
1333                              le16_to_cpu(desc->length),
1334                              le16_to_cpu(desc->life_time),
1335                              desc->wl128x_mem.total_mem_blocks,
1336                              desc->wl128x_mem.extra_bytes);
1337         } else {
1338                 /* calculate number of padding bytes */
1339                 int pad = aligned_len - skb->len;
1340                 desc->tx_attr |=
1341                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1342
1343                 /* Store the aligned length in terms of words */
1344                 desc->length = cpu_to_le16(aligned_len >> 2);
1345
1346                 wl1271_debug(DEBUG_TX,
1347                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1348                              pad, desc->hlid,
1349                              le16_to_cpu(desc->length),
1350                              le16_to_cpu(desc->life_time),
1351                              desc->wl127x_mem.total_mem_blocks);
1352         }
1353 }
1354
1355 static enum wl_rx_buf_align
1356 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1357 {
1358         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1359                 return WLCORE_RX_BUF_UNALIGNED;
1360
1361         return WLCORE_RX_BUF_ALIGNED;
1362 }
1363
1364 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1365                                     u32 data_len)
1366 {
1367         struct wl1271_rx_descriptor *desc = rx_data;
1368
1369         /* invalid packet */
1370         if (data_len < sizeof(*desc) ||
1371             data_len < sizeof(*desc) + desc->pad_len)
1372                 return 0;
1373
1374         return data_len - sizeof(*desc) - desc->pad_len;
1375 }
1376
1377 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1378 {
1379         if (wl->fw_status->tx_results_counter ==
1380             (wl->tx_results_count & 0xff))
1381                 return 0;
1382
1383         return wlcore_tx_complete(wl);
1384 }
1385
1386 static int wl12xx_hw_init(struct wl1271 *wl)
1387 {
1388         int ret;
1389
1390         if (wl->chip.id == CHIP_ID_128X_PG20) {
1391                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1392
1393                 ret = wl128x_cmd_general_parms(wl);
1394                 if (ret < 0)
1395                         goto out;
1396
1397                 /*
1398                  * If we are in calibrator based auto detect then we got the FEM nr
1399                  * in wl->fem_manuf. No need to continue further
1400                  */
1401                 if (wl->plt_mode == PLT_FEM_DETECT)
1402                         goto out;
1403
1404                 ret = wl128x_cmd_radio_parms(wl);
1405                 if (ret < 0)
1406                         goto out;
1407
1408                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1409                         /* Enable SDIO padding */
1410                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1411
1412                 /* Must be before wl1271_acx_init_mem_config() */
1413                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1414                 if (ret < 0)
1415                         goto out;
1416         } else {
1417                 ret = wl1271_cmd_general_parms(wl);
1418                 if (ret < 0)
1419                         goto out;
1420
1421                 /*
1422                  * If we are in calibrator based auto detect then we got the FEM nr
1423                  * in wl->fem_manuf. No need to continue further
1424                  */
1425                 if (wl->plt_mode == PLT_FEM_DETECT)
1426                         goto out;
1427
1428                 ret = wl1271_cmd_radio_parms(wl);
1429                 if (ret < 0)
1430                         goto out;
1431                 ret = wl1271_cmd_ext_radio_parms(wl);
1432                 if (ret < 0)
1433                         goto out;
1434         }
1435 out:
1436         return ret;
1437 }
1438
1439 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1440                                      struct wl_fw_status *fw_status)
1441 {
1442         struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1443
1444         fw_status->intr = le32_to_cpu(int_fw_status->intr);
1445         fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1446         fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1447         fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1448         fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1449
1450         fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1451         fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1452         fw_status->link_fast_bitmap =
1453                         le32_to_cpu(int_fw_status->link_fast_bitmap);
1454         fw_status->total_released_blks =
1455                         le32_to_cpu(int_fw_status->total_released_blks);
1456         fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1457
1458         fw_status->counters.tx_released_pkts =
1459                         int_fw_status->counters.tx_released_pkts;
1460         fw_status->counters.tx_lnk_free_pkts =
1461                         int_fw_status->counters.tx_lnk_free_pkts;
1462         fw_status->counters.tx_voice_released_blks =
1463                         int_fw_status->counters.tx_voice_released_blks;
1464         fw_status->counters.tx_last_rate =
1465                         int_fw_status->counters.tx_last_rate;
1466
1467         fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1468 }
1469
1470 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1471                                        struct wl12xx_vif *wlvif)
1472 {
1473         return wlvif->rate_set;
1474 }
1475
1476 static void wl12xx_conf_init(struct wl1271 *wl)
1477 {
1478         struct wl12xx_priv *priv = wl->priv;
1479
1480         /* apply driver default configuration */
1481         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1482
1483         /* apply default private configuration */
1484         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1485 }
1486
1487 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1488 {
1489         bool supported = false;
1490         u8 major, minor;
1491
1492         if (wl->chip.id == CHIP_ID_128X_PG20) {
1493                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1494                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1495
1496                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1497                 if (major > 2 || (major == 2 && minor >= 1))
1498                         supported = true;
1499         } else {
1500                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1501                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1502
1503                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1504                 if (major == 3 && minor >= 1)
1505                         supported = true;
1506         }
1507
1508         wl1271_debug(DEBUG_PROBE,
1509                      "PG Ver major = %d minor = %d, MAC %s present",
1510                      major, minor, supported ? "is" : "is not");
1511
1512         return supported;
1513 }
1514
1515 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1516 {
1517         u32 mac1, mac2;
1518         int ret;
1519
1520         /* Device may be in ELP from the bootloader or kexec */
1521         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1522         if (ret < 0)
1523                 goto out;
1524
1525         usleep_range(500000, 700000);
1526
1527         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1528         if (ret < 0)
1529                 goto out;
1530
1531         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1532         if (ret < 0)
1533                 goto out;
1534
1535         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1536         if (ret < 0)
1537                 goto out;
1538
1539         /* these are the two parts of the BD_ADDR */
1540         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1541                 ((mac1 & 0xff000000) >> 24);
1542         wl->fuse_nic_addr = mac1 & 0xffffff;
1543
1544         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1545
1546 out:
1547         return ret;
1548 }
1549
1550 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1551 {
1552         u16 die_info;
1553         int ret;
1554
1555         if (wl->chip.id == CHIP_ID_128X_PG20)
1556                 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1557                                           &die_info);
1558         else
1559                 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1560                                           &die_info);
1561
1562         if (ret >= 0 && ver)
1563                 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1564
1565         return ret;
1566 }
1567
1568 static int wl12xx_get_mac(struct wl1271 *wl)
1569 {
1570         if (wl12xx_mac_in_fuse(wl))
1571                 return wl12xx_get_fuse_mac(wl);
1572
1573         return 0;
1574 }
1575
1576 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1577                                     struct wl1271_tx_hw_descr *desc,
1578                                     struct sk_buff *skb)
1579 {
1580         desc->wl12xx_reserved = 0;
1581 }
1582
1583 static int wl12xx_plt_init(struct wl1271 *wl)
1584 {
1585         int ret;
1586
1587         ret = wl->ops->boot(wl);
1588         if (ret < 0)
1589                 goto out;
1590
1591         ret = wl->ops->hw_init(wl);
1592         if (ret < 0)
1593                 goto out_irq_disable;
1594
1595         /*
1596          * If we are in calibrator based auto detect then we got the FEM nr
1597          * in wl->fem_manuf. No need to continue further
1598          */
1599         if (wl->plt_mode == PLT_FEM_DETECT)
1600                 goto out;
1601
1602         ret = wl1271_acx_init_mem_config(wl);
1603         if (ret < 0)
1604                 goto out_irq_disable;
1605
1606         ret = wl12xx_acx_mem_cfg(wl);
1607         if (ret < 0)
1608                 goto out_free_memmap;
1609
1610         /* Enable data path */
1611         ret = wl1271_cmd_data_path(wl, 1);
1612         if (ret < 0)
1613                 goto out_free_memmap;
1614
1615         /* Configure for CAM power saving (ie. always active) */
1616         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1617         if (ret < 0)
1618                 goto out_free_memmap;
1619
1620         /* configure PM */
1621         ret = wl1271_acx_pm_config(wl);
1622         if (ret < 0)
1623                 goto out_free_memmap;
1624
1625         goto out;
1626
1627 out_free_memmap:
1628         kfree(wl->target_mem_map);
1629         wl->target_mem_map = NULL;
1630
1631 out_irq_disable:
1632         mutex_unlock(&wl->mutex);
1633         /* Unlocking the mutex in the middle of handling is
1634            inherently unsafe. In this case we deem it safe to do,
1635            because we need to let any possibly pending IRQ out of
1636            the system (and while we are WL1271_STATE_OFF the IRQ
1637            work function will not do anything.) Also, any other
1638            possible concurrent operations will fail due to the
1639            current state, hence the wl1271 struct should be safe. */
1640         wlcore_disable_interrupts(wl);
1641         mutex_lock(&wl->mutex);
1642 out:
1643         return ret;
1644 }
1645
1646 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1647 {
1648         if (is_gem)
1649                 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1650
1651         return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1652 }
1653
1654 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1655                           struct ieee80211_vif *vif,
1656                           struct ieee80211_sta *sta,
1657                           struct ieee80211_key_conf *key_conf)
1658 {
1659         return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1660 }
1661
1662 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1663                                struct ieee80211_sta_ht_cap *ht_cap,
1664                                bool allow_ht_operation,
1665                                u32 rate_set, u8 hlid)
1666 {
1667         return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1668                                               hlid);
1669 }
1670
1671 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1672                                  struct wl1271_link *lnk)
1673 {
1674         u8 thold;
1675
1676         if (test_bit(hlid, &wl->fw_fast_lnk_map))
1677                 thold = wl->conf.tx.fast_link_thold;
1678         else
1679                 thold = wl->conf.tx.slow_link_thold;
1680
1681         return lnk->allocated_pkts < thold;
1682 }
1683
1684 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1685                                 struct wl1271_link *lnk)
1686 {
1687         /* any link is good for low priority */
1688         return true;
1689 }
1690
1691 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1692 {
1693         return hwaddr << 5;
1694 }
1695
1696 static int wl12xx_setup(struct wl1271 *wl);
1697
1698 static struct wlcore_ops wl12xx_ops = {
1699         .setup                  = wl12xx_setup,
1700         .identify_chip          = wl12xx_identify_chip,
1701         .boot                   = wl12xx_boot,
1702         .plt_init               = wl12xx_plt_init,
1703         .trigger_cmd            = wl12xx_trigger_cmd,
1704         .ack_event              = wl12xx_ack_event,
1705         .wait_for_event         = wl12xx_wait_for_event,
1706         .process_mailbox_events = wl12xx_process_mailbox_events,
1707         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1708         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1709         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1710         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1711         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1712         .tx_immediate_compl     = NULL,
1713         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1714         .hw_init                = wl12xx_hw_init,
1715         .init_vif               = NULL,
1716         .convert_fw_status      = wl12xx_convert_fw_status,
1717         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1718         .get_pg_ver             = wl12xx_get_pg_ver,
1719         .get_mac                = wl12xx_get_mac,
1720         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1721         .set_rx_csum            = NULL,
1722         .ap_get_mimo_wide_rate_mask = NULL,
1723         .debugfs_init           = wl12xx_debugfs_add_files,
1724         .scan_start             = wl12xx_scan_start,
1725         .scan_stop              = wl12xx_scan_stop,
1726         .sched_scan_start       = wl12xx_sched_scan_start,
1727         .sched_scan_stop        = wl12xx_scan_sched_scan_stop,
1728         .get_spare_blocks       = wl12xx_get_spare_blocks,
1729         .set_key                = wl12xx_set_key,
1730         .channel_switch         = wl12xx_cmd_channel_switch,
1731         .pre_pkt_send           = NULL,
1732         .set_peer_cap           = wl12xx_set_peer_cap,
1733         .convert_hwaddr         = wl12xx_convert_hwaddr,
1734         .lnk_high_prio          = wl12xx_lnk_high_prio,
1735         .lnk_low_prio           = wl12xx_lnk_low_prio,
1736         .interrupt_notify       = NULL,
1737         .rx_ba_filter           = NULL,
1738         .ap_sleep               = NULL,
1739 };
1740
1741 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1742         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1743                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1744         .ht_supported = true,
1745         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1746         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1747         .mcs = {
1748                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1749                 .rx_highest = cpu_to_le16(72),
1750                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1751                 },
1752 };
1753
1754 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1755         {
1756                 .max = 3,
1757                 .types = BIT(NL80211_IFTYPE_STATION),
1758         },
1759         {
1760                 .max = 1,
1761                 .types = BIT(NL80211_IFTYPE_AP) |
1762                          BIT(NL80211_IFTYPE_P2P_GO) |
1763                          BIT(NL80211_IFTYPE_P2P_CLIENT),
1764         },
1765 };
1766
1767 static const struct ieee80211_iface_combination
1768 wl12xx_iface_combinations[] = {
1769         {
1770                 .max_interfaces = 3,
1771                 .limits = wl12xx_iface_limits,
1772                 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1773                 .num_different_channels = 1,
1774         },
1775 };
1776
1777 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1778         { 19200000,     false,  WL12XX_REFCLOCK_19      },
1779         { 26000000,     false,  WL12XX_REFCLOCK_26      },
1780         { 26000000,     true,   WL12XX_REFCLOCK_26_XTAL },
1781         { 38400000,     false,  WL12XX_REFCLOCK_38      },
1782         { 38400000,     true,   WL12XX_REFCLOCK_38_XTAL },
1783         { 52000000,     false,  WL12XX_REFCLOCK_52      },
1784         { 0,            false,  0 }
1785 };
1786
1787 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1788         { 16368000,     true,   WL12XX_TCXOCLOCK_16_368 },
1789         { 16800000,     true,   WL12XX_TCXOCLOCK_16_8   },
1790         { 19200000,     true,   WL12XX_TCXOCLOCK_19_2   },
1791         { 26000000,     true,   WL12XX_TCXOCLOCK_26     },
1792         { 32736000,     true,   WL12XX_TCXOCLOCK_32_736 },
1793         { 33600000,     true,   WL12XX_TCXOCLOCK_33_6   },
1794         { 38400000,     true,   WL12XX_TCXOCLOCK_38_4   },
1795         { 52000000,     true,   WL12XX_TCXOCLOCK_52     },
1796         { 0,            false,  0 }
1797 };
1798
1799 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1800                                 u32 freq, bool xtal)
1801 {
1802         int i;
1803
1804         for (i = 0; table[i].freq != 0; i++)
1805                 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1806                         return table[i].hw_idx;
1807
1808         return -EINVAL;
1809 }
1810
1811 static int wl12xx_setup(struct wl1271 *wl)
1812 {
1813         struct wl12xx_priv *priv = wl->priv;
1814         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1815
1816         BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1817         BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1818         BUILD_BUG_ON(WL12XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1819
1820         wl->rtable = wl12xx_rtable;
1821         wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1822         wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1823         wl->num_links = WL12XX_MAX_LINKS;
1824         wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1825         wl->iface_combinations = wl12xx_iface_combinations;
1826         wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1827         wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1828         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1829         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1830         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1831         wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1832         wl->fw_status_priv_len = 0;
1833         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1834         wl->ofdm_only_ap = true;
1835         wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, &wl12xx_ht_cap);
1836         wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, &wl12xx_ht_cap);
1837         wl12xx_conf_init(wl);
1838
1839         if (!fref_param) {
1840                 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1841                                                 pdev_data->ref_clock_freq,
1842                                                 pdev_data->ref_clock_xtal);
1843                 if (priv->ref_clock < 0) {
1844                         wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1845                                      pdev_data->ref_clock_freq,
1846                                      pdev_data->ref_clock_xtal ?
1847                                      "XTAL" : "not XTAL");
1848
1849                         return priv->ref_clock;
1850                 }
1851         } else {
1852                 if (!strcmp(fref_param, "19.2"))
1853                         priv->ref_clock = WL12XX_REFCLOCK_19;
1854                 else if (!strcmp(fref_param, "26"))
1855                         priv->ref_clock = WL12XX_REFCLOCK_26;
1856                 else if (!strcmp(fref_param, "26x"))
1857                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1858                 else if (!strcmp(fref_param, "38.4"))
1859                         priv->ref_clock = WL12XX_REFCLOCK_38;
1860                 else if (!strcmp(fref_param, "38.4x"))
1861                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1862                 else if (!strcmp(fref_param, "52"))
1863                         priv->ref_clock = WL12XX_REFCLOCK_52;
1864                 else
1865                         wl1271_error("Invalid fref parameter %s", fref_param);
1866         }
1867
1868         if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1869                 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1870                                                 pdev_data->tcxo_clock_freq,
1871                                                 true);
1872                 if (priv->tcxo_clock < 0) {
1873                         wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1874                                      pdev_data->tcxo_clock_freq);
1875
1876                         return priv->tcxo_clock;
1877                 }
1878         } else if (tcxo_param) {
1879                 if (!strcmp(tcxo_param, "19.2"))
1880                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1881                 else if (!strcmp(tcxo_param, "26"))
1882                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1883                 else if (!strcmp(tcxo_param, "38.4"))
1884                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1885                 else if (!strcmp(tcxo_param, "52"))
1886                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1887                 else if (!strcmp(tcxo_param, "16.368"))
1888                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1889                 else if (!strcmp(tcxo_param, "32.736"))
1890                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1891                 else if (!strcmp(tcxo_param, "16.8"))
1892                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1893                 else if (!strcmp(tcxo_param, "33.6"))
1894                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1895                 else
1896                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1897         }
1898
1899         priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1900         if (!priv->rx_mem_addr)
1901                 return -ENOMEM;
1902
1903         return 0;
1904 }
1905
1906 static int wl12xx_probe(struct platform_device *pdev)
1907 {
1908         struct wl1271 *wl;
1909         struct ieee80211_hw *hw;
1910         int ret;
1911
1912         hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1913                              WL12XX_AGGR_BUFFER_SIZE,
1914                              sizeof(struct wl12xx_event_mailbox));
1915         if (IS_ERR(hw)) {
1916                 wl1271_error("can't allocate hw");
1917                 ret = PTR_ERR(hw);
1918                 goto out;
1919         }
1920
1921         wl = hw->priv;
1922         wl->ops = &wl12xx_ops;
1923         wl->ptable = wl12xx_ptable;
1924         ret = wlcore_probe(wl, pdev);
1925         if (ret)
1926                 goto out_free;
1927
1928         return ret;
1929
1930 out_free:
1931         wlcore_free_hw(wl);
1932 out:
1933         return ret;
1934 }
1935
1936 static int wl12xx_remove(struct platform_device *pdev)
1937 {
1938         struct wl1271 *wl = platform_get_drvdata(pdev);
1939         struct wl12xx_priv *priv;
1940
1941         if (!wl)
1942                 goto out;
1943         priv = wl->priv;
1944
1945         kfree(priv->rx_mem_addr);
1946
1947 out:
1948         return wlcore_remove(pdev);
1949 }
1950
1951 static const struct platform_device_id wl12xx_id_table[] = {
1952         { "wl12xx", 0 },
1953         {  } /* Terminating Entry */
1954 };
1955 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1956
1957 static struct platform_driver wl12xx_driver = {
1958         .probe          = wl12xx_probe,
1959         .remove         = wl12xx_remove,
1960         .id_table       = wl12xx_id_table,
1961         .driver = {
1962                 .name   = "wl12xx_driver",
1963         }
1964 };
1965
1966 module_platform_driver(wl12xx_driver);
1967
1968 module_param_named(fref, fref_param, charp, 0);
1969 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1970
1971 module_param_named(tcxo, tcxo_param, charp, 0);
1972 MODULE_PARM_DESC(tcxo,
1973                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1974
1975 MODULE_LICENSE("GPL v2");
1976 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1977 /*(DEBLOBBED)*/