1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched/signal.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
29 # define pci_lock_config(f) do { (void)(f); } while (0)
30 # define pci_unlock_config(f) do { (void)(f); } while (0)
32 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
33 # define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
36 #define PCI_OP_READ(size, type, len) \
37 int pci_bus_read_config_##size \
38 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
41 unsigned long flags; \
43 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
44 pci_lock_config(flags); \
45 res = bus->ops->read(bus, devfn, pos, len, &data); \
46 *value = (type)data; \
47 pci_unlock_config(flags); \
51 #define PCI_OP_WRITE(size, type, len) \
52 int pci_bus_write_config_##size \
53 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
56 unsigned long flags; \
57 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
58 pci_lock_config(flags); \
59 res = bus->ops->write(bus, devfn, pos, len, value); \
60 pci_unlock_config(flags); \
64 PCI_OP_READ(byte, u8, 1)
65 PCI_OP_READ(word, u16, 2)
66 PCI_OP_READ(dword, u32, 4)
67 PCI_OP_WRITE(byte, u8, 1)
68 PCI_OP_WRITE(word, u16, 2)
69 PCI_OP_WRITE(dword, u32, 4)
71 EXPORT_SYMBOL(pci_bus_read_config_byte);
72 EXPORT_SYMBOL(pci_bus_read_config_word);
73 EXPORT_SYMBOL(pci_bus_read_config_dword);
74 EXPORT_SYMBOL(pci_bus_write_config_byte);
75 EXPORT_SYMBOL(pci_bus_write_config_word);
76 EXPORT_SYMBOL(pci_bus_write_config_dword);
78 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
83 addr = bus->ops->map_bus(bus, devfn, where);
86 return PCIBIOS_DEVICE_NOT_FOUND;
96 return PCIBIOS_SUCCESSFUL;
98 EXPORT_SYMBOL_GPL(pci_generic_config_read);
100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
105 addr = bus->ops->map_bus(bus, devfn, where);
107 return PCIBIOS_DEVICE_NOT_FOUND;
116 return PCIBIOS_SUCCESSFUL;
118 EXPORT_SYMBOL_GPL(pci_generic_config_write);
120 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
128 return PCIBIOS_DEVICE_NOT_FOUND;
134 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
136 return PCIBIOS_SUCCESSFUL;
138 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
140 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 val)
146 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
148 return PCIBIOS_DEVICE_NOT_FOUND;
152 return PCIBIOS_SUCCESSFUL;
156 * In general, hardware that supports only 32-bit writes on PCI is
157 * not spec-compliant. For example, software may perform a 16-bit
158 * write. If the hardware only supports 32-bit accesses, we must
159 * do a 32-bit read, merge in the 16 bits we intend to write,
160 * followed by a 32-bit write. If the 16 bits we *don't* intend to
161 * write happen to have any RW1C (write-one-to-clear) bits set, we
162 * just inadvertently cleared something we shouldn't have.
164 if (!bus->unsafe_warn) {
165 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
166 size, pci_domain_nr(bus), bus->number,
167 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
168 bus->unsafe_warn = 1;
171 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
172 tmp = readl(addr) & mask;
173 tmp |= val << ((where & 0x3) * 8);
176 return PCIBIOS_SUCCESSFUL;
178 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
181 * pci_bus_set_ops - Set raw operations of pci bus
182 * @bus: pci bus struct
183 * @ops: new raw operations
185 * Return previous raw operations
187 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
189 struct pci_ops *old_ops;
192 raw_spin_lock_irqsave(&pci_lock, flags);
195 raw_spin_unlock_irqrestore(&pci_lock, flags);
198 EXPORT_SYMBOL(pci_bus_set_ops);
201 * The following routines are to prevent the user from accessing PCI config
202 * space when it's unsafe to do so. Some devices require this during BIST and
203 * we're required to prevent it during D-state transitions.
205 * We have a bit per device to indicate it's blocked and a global wait queue
206 * for callers to sleep on until devices are unblocked.
208 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
210 static noinline void pci_wait_cfg(struct pci_dev *dev)
211 __must_hold(&pci_lock)
214 raw_spin_unlock_irq(&pci_lock);
215 wait_event(pci_cfg_wait, !dev->block_cfg_access);
216 raw_spin_lock_irq(&pci_lock);
217 } while (dev->block_cfg_access);
220 /* Returns 0 on success, negative values indicate error. */
221 #define PCI_USER_READ_CONFIG(size, type) \
222 int pci_user_read_config_##size \
223 (struct pci_dev *dev, int pos, type *val) \
225 int ret = PCIBIOS_SUCCESSFUL; \
227 if (PCI_##size##_BAD) \
229 raw_spin_lock_irq(&pci_lock); \
230 if (unlikely(dev->block_cfg_access)) \
232 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
233 pos, sizeof(type), &data); \
234 raw_spin_unlock_irq(&pci_lock); \
236 return pcibios_err_to_errno(ret); \
238 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
240 /* Returns 0 on success, negative values indicate error. */
241 #define PCI_USER_WRITE_CONFIG(size, type) \
242 int pci_user_write_config_##size \
243 (struct pci_dev *dev, int pos, type val) \
245 int ret = PCIBIOS_SUCCESSFUL; \
246 if (PCI_##size##_BAD) \
248 raw_spin_lock_irq(&pci_lock); \
249 if (unlikely(dev->block_cfg_access)) \
251 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
252 pos, sizeof(type), val); \
253 raw_spin_unlock_irq(&pci_lock); \
254 return pcibios_err_to_errno(ret); \
256 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
258 PCI_USER_READ_CONFIG(byte, u8)
259 PCI_USER_READ_CONFIG(word, u16)
260 PCI_USER_READ_CONFIG(dword, u32)
261 PCI_USER_WRITE_CONFIG(byte, u8)
262 PCI_USER_WRITE_CONFIG(word, u16)
263 PCI_USER_WRITE_CONFIG(dword, u32)
265 /* VPD access through PCI 2.2+ VPD capability */
268 * pci_read_vpd - Read one entry from Vital Product Data
269 * @dev: pci device struct
270 * @pos: offset in vpd space
271 * @count: number of bytes to read
272 * @buf: pointer to where to store result
274 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
276 if (!dev->vpd || !dev->vpd->ops)
278 return dev->vpd->ops->read(dev, pos, count, buf);
280 EXPORT_SYMBOL(pci_read_vpd);
283 * pci_write_vpd - Write entry to Vital Product Data
284 * @dev: pci device struct
285 * @pos: offset in vpd space
286 * @count: number of bytes to write
287 * @buf: buffer containing write data
289 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
291 if (!dev->vpd || !dev->vpd->ops)
293 return dev->vpd->ops->write(dev, pos, count, buf);
295 EXPORT_SYMBOL(pci_write_vpd);
298 * pci_set_vpd_size - Set size of Vital Product Data space
299 * @dev: pci device struct
300 * @len: size of vpd space
302 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
304 if (!dev->vpd || !dev->vpd->ops)
306 return dev->vpd->ops->set_size(dev, len);
308 EXPORT_SYMBOL(pci_set_vpd_size);
310 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
313 * pci_vpd_size - determine actual size of Vital Product Data
314 * @dev: pci device struct
315 * @old_size: current assumed size, also maximum allowed size
317 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
320 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
322 while (off < old_size &&
323 pci_read_vpd(dev, off, 1, header) == 1) {
326 if (header[0] & PCI_VPD_LRDT) {
327 /* Large Resource Data Type Tag */
328 tag = pci_vpd_lrdt_tag(header);
329 /* Only read length from known tag items */
330 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
331 (tag == PCI_VPD_LTIN_RO_DATA) ||
332 (tag == PCI_VPD_LTIN_RW_DATA)) {
333 if (pci_read_vpd(dev, off+1, 2,
336 "invalid large VPD tag %02x size at offset %zu",
340 off += PCI_VPD_LRDT_TAG_SIZE +
341 pci_vpd_lrdt_size(header);
344 /* Short Resource Data Type Tag */
345 off += PCI_VPD_SRDT_TAG_SIZE +
346 pci_vpd_srdt_size(header);
347 tag = pci_vpd_srdt_tag(header);
350 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
353 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
354 (tag != PCI_VPD_LTIN_RO_DATA) &&
355 (tag != PCI_VPD_LTIN_RW_DATA)) {
357 "invalid %s VPD tag %02x at offset %zu",
358 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
367 * Wait for last operation to complete.
368 * This code has to spin since there is no other notification from the PCI
369 * hardware. Since the VPD is often implemented by serial attachment to an
370 * EEPROM, it may take many milliseconds to complete.
372 * Returns 0 on success, negative values indicate error.
374 static int pci_vpd_wait(struct pci_dev *dev)
376 struct pci_vpd *vpd = dev->vpd;
377 unsigned long timeout = jiffies + msecs_to_jiffies(125);
378 unsigned long max_sleep = 16;
385 while (time_before(jiffies, timeout)) {
386 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
391 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
396 if (fatal_signal_pending(current))
399 usleep_range(10, max_sleep);
400 if (max_sleep < 1024)
404 dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
408 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
411 struct pci_vpd *vpd = dev->vpd;
413 loff_t end = pos + count;
421 vpd->len = pci_vpd_size(dev, vpd->len);
430 if (end > vpd->len) {
435 if (mutex_lock_killable(&vpd->lock))
438 ret = pci_vpd_wait(dev);
444 unsigned int i, skip;
446 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
451 vpd->flag = PCI_VPD_ADDR_F;
452 ret = pci_vpd_wait(dev);
456 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
461 for (i = 0; i < sizeof(u32); i++) {
471 mutex_unlock(&vpd->lock);
472 return ret ? ret : count;
475 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
478 struct pci_vpd *vpd = dev->vpd;
480 loff_t end = pos + count;
483 if (pos < 0 || (pos & 3) || (count & 3))
488 vpd->len = pci_vpd_size(dev, vpd->len);
497 if (mutex_lock_killable(&vpd->lock))
500 ret = pci_vpd_wait(dev);
512 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
515 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
516 pos | PCI_VPD_ADDR_F);
522 ret = pci_vpd_wait(dev);
529 mutex_unlock(&vpd->lock);
530 return ret ? ret : count;
533 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
535 struct pci_vpd *vpd = dev->vpd;
537 if (len == 0 || len > PCI_VPD_MAX_SIZE)
546 static const struct pci_vpd_ops pci_vpd_ops = {
547 .read = pci_vpd_read,
548 .write = pci_vpd_write,
549 .set_size = pci_vpd_set_size,
552 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
555 struct pci_dev *tdev = pci_get_slot(dev->bus,
556 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
562 ret = pci_read_vpd(tdev, pos, count, arg);
567 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
570 struct pci_dev *tdev = pci_get_slot(dev->bus,
571 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
577 ret = pci_write_vpd(tdev, pos, count, arg);
582 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
584 struct pci_dev *tdev = pci_get_slot(dev->bus,
585 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
591 ret = pci_set_vpd_size(tdev, len);
596 static const struct pci_vpd_ops pci_vpd_f0_ops = {
597 .read = pci_vpd_f0_read,
598 .write = pci_vpd_f0_write,
599 .set_size = pci_vpd_f0_set_size,
602 int pci_vpd_init(struct pci_dev *dev)
607 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
611 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
615 vpd->len = PCI_VPD_MAX_SIZE;
616 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
617 vpd->ops = &pci_vpd_f0_ops;
619 vpd->ops = &pci_vpd_ops;
620 mutex_init(&vpd->lock);
628 void pci_vpd_release(struct pci_dev *dev)
634 * pci_cfg_access_lock - Lock PCI config reads/writes
635 * @dev: pci device struct
637 * When access is locked, any userspace reads or writes to config
638 * space and concurrent lock requests will sleep until access is
639 * allowed via pci_cfg_access_unlock() again.
641 void pci_cfg_access_lock(struct pci_dev *dev)
645 raw_spin_lock_irq(&pci_lock);
646 if (dev->block_cfg_access)
648 dev->block_cfg_access = 1;
649 raw_spin_unlock_irq(&pci_lock);
651 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
654 * pci_cfg_access_trylock - try to lock PCI config reads/writes
655 * @dev: pci device struct
657 * Same as pci_cfg_access_lock, but will return 0 if access is
658 * already locked, 1 otherwise. This function can be used from
661 bool pci_cfg_access_trylock(struct pci_dev *dev)
666 raw_spin_lock_irqsave(&pci_lock, flags);
667 if (dev->block_cfg_access)
670 dev->block_cfg_access = 1;
671 raw_spin_unlock_irqrestore(&pci_lock, flags);
675 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
678 * pci_cfg_access_unlock - Unlock PCI config reads/writes
679 * @dev: pci device struct
681 * This function allows PCI config accesses to resume.
683 void pci_cfg_access_unlock(struct pci_dev *dev)
687 raw_spin_lock_irqsave(&pci_lock, flags);
689 /* This indicates a problem in the caller, but we don't need
690 * to kill them, unlike a double-block above. */
691 WARN_ON(!dev->block_cfg_access);
693 dev->block_cfg_access = 0;
694 raw_spin_unlock_irqrestore(&pci_lock, flags);
696 wake_up_all(&pci_cfg_wait);
698 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
700 static inline int pcie_cap_version(const struct pci_dev *dev)
702 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
705 static bool pcie_downstream_port(const struct pci_dev *dev)
707 int type = pci_pcie_type(dev);
709 return type == PCI_EXP_TYPE_ROOT_PORT ||
710 type == PCI_EXP_TYPE_DOWNSTREAM ||
711 type == PCI_EXP_TYPE_PCIE_BRIDGE;
714 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
716 int type = pci_pcie_type(dev);
718 return type == PCI_EXP_TYPE_ENDPOINT ||
719 type == PCI_EXP_TYPE_LEG_END ||
720 type == PCI_EXP_TYPE_ROOT_PORT ||
721 type == PCI_EXP_TYPE_UPSTREAM ||
722 type == PCI_EXP_TYPE_DOWNSTREAM ||
723 type == PCI_EXP_TYPE_PCI_BRIDGE ||
724 type == PCI_EXP_TYPE_PCIE_BRIDGE;
727 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
729 return pcie_downstream_port(dev) &&
730 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
733 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
735 int type = pci_pcie_type(dev);
737 return type == PCI_EXP_TYPE_ROOT_PORT ||
738 type == PCI_EXP_TYPE_RC_EC;
741 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
743 if (!pci_is_pcie(dev))
756 return pcie_cap_has_lnkctl(dev);
760 return pcie_cap_has_sltctl(dev);
764 return pcie_cap_has_rtctl(dev);
765 case PCI_EXP_DEVCAP2:
766 case PCI_EXP_DEVCTL2:
767 case PCI_EXP_LNKCAP2:
768 case PCI_EXP_LNKCTL2:
769 case PCI_EXP_LNKSTA2:
770 return pcie_cap_version(dev) > 1;
777 * Note that these accessor functions are only for the "PCI Express
778 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
779 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
781 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
789 if (pcie_capability_reg_implemented(dev, pos)) {
790 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
792 * Reset *val to 0 if pci_read_config_word() fails, it may
793 * have been written as 0xFFFF if hardware error happens
794 * during pci_read_config_word().
802 * For Functions that do not implement the Slot Capabilities,
803 * Slot Status, and Slot Control registers, these spaces must
804 * be hardwired to 0b, with the exception of the Presence Detect
805 * State bit in the Slot Status register of Downstream Ports,
806 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
808 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
809 pos == PCI_EXP_SLTSTA)
810 *val = PCI_EXP_SLTSTA_PDS;
814 EXPORT_SYMBOL(pcie_capability_read_word);
816 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
824 if (pcie_capability_reg_implemented(dev, pos)) {
825 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
827 * Reset *val to 0 if pci_read_config_dword() fails, it may
828 * have been written as 0xFFFFFFFF if hardware error happens
829 * during pci_read_config_dword().
836 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
837 pos == PCI_EXP_SLTSTA)
838 *val = PCI_EXP_SLTSTA_PDS;
842 EXPORT_SYMBOL(pcie_capability_read_dword);
844 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
849 if (!pcie_capability_reg_implemented(dev, pos))
852 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
854 EXPORT_SYMBOL(pcie_capability_write_word);
856 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
861 if (!pcie_capability_reg_implemented(dev, pos))
864 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
866 EXPORT_SYMBOL(pcie_capability_write_dword);
868 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
874 ret = pcie_capability_read_word(dev, pos, &val);
878 ret = pcie_capability_write_word(dev, pos, val);
883 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
885 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
891 ret = pcie_capability_read_dword(dev, pos, &val);
895 ret = pcie_capability_write_dword(dev, pos, val);
900 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
902 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
904 if (pci_dev_is_disconnected(dev)) {
906 return PCIBIOS_DEVICE_NOT_FOUND;
908 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
910 EXPORT_SYMBOL(pci_read_config_byte);
912 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
914 if (pci_dev_is_disconnected(dev)) {
916 return PCIBIOS_DEVICE_NOT_FOUND;
918 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
920 EXPORT_SYMBOL(pci_read_config_word);
922 int pci_read_config_dword(const struct pci_dev *dev, int where,
925 if (pci_dev_is_disconnected(dev)) {
927 return PCIBIOS_DEVICE_NOT_FOUND;
929 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
931 EXPORT_SYMBOL(pci_read_config_dword);
933 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
935 if (pci_dev_is_disconnected(dev))
936 return PCIBIOS_DEVICE_NOT_FOUND;
937 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
939 EXPORT_SYMBOL(pci_write_config_byte);
941 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
943 if (pci_dev_is_disconnected(dev))
944 return PCIBIOS_DEVICE_NOT_FOUND;
945 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
947 EXPORT_SYMBOL(pci_write_config_word);
949 int pci_write_config_dword(const struct pci_dev *dev, int where,
952 if (pci_dev_is_disconnected(dev))
953 return PCIBIOS_DEVICE_NOT_FOUND;
954 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
956 EXPORT_SYMBOL(pci_write_config_dword);