drivers/pci/dwc/pcie-spear13xx.c

   1 /*
   2  * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
   3  *
   4  * SPEAr13xx PCIe Glue Layer Source Code
   5  *
   6  * Copyright (C) 2010-2014 ST Microelectronics
   7  * Pratyush Anand <pratyush.anand@gmail.com>
   8  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2. This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/pci.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/resource.h>
  24
  25 #include "pcie-designware.h"
  26
  27 struct spear13xx_pcie {
  28         struct dw_pcie          *pci;
  29         void __iomem            *app_base;
  30         struct phy              *phy;
  31         struct clk              *clk;
  32         bool                    is_gen1;
  33 };
  34
  35 struct pcie_app_reg {
  36         u32     app_ctrl_0;             /* cr0 */
  37         u32     app_ctrl_1;             /* cr1 */
  38         u32     app_status_0;           /* cr2 */
  39         u32     app_status_1;           /* cr3 */
  40         u32     msg_status;             /* cr4 */
  41         u32     msg_payload;            /* cr5 */
  42         u32     int_sts;                /* cr6 */
  43         u32     int_clr;                /* cr7 */
  44         u32     int_mask;               /* cr8 */
  45         u32     mst_bmisc;              /* cr9 */
  46         u32     phy_ctrl;               /* cr10 */
  47         u32     phy_status;             /* cr11 */
  48         u32     cxpl_debug_info_0;      /* cr12 */
  49         u32     cxpl_debug_info_1;      /* cr13 */
  50         u32     ven_msg_ctrl_0;         /* cr14 */
  51         u32     ven_msg_ctrl_1;         /* cr15 */
  52         u32     ven_msg_data_0;         /* cr16 */
  53         u32     ven_msg_data_1;         /* cr17 */
  54         u32     ven_msi_0;              /* cr18 */
  55         u32     ven_msi_1;              /* cr19 */
  56         u32     mst_rmisc;              /* cr20 */
  57 };
  58
  59 /* CR0 ID */
  60 #define APP_LTSSM_ENABLE_ID                     3
  61 #define DEVICE_TYPE_RC                          (4 << 25)
  62 #define MISCTRL_EN_ID                           30
  63 #define REG_TRANSLATION_ENABLE                  31
  64
  65 /* CR3 ID */
  66 #define XMLH_LINK_UP                            (1 << 6)
  67
  68 /* CR6 */
  69 #define MSI_CTRL_INT                            (1 << 26)
  70
  71 #define EXP_CAP_ID_OFFSET                       0x70
  72
  73 #define to_spear13xx_pcie(x)    dev_get_drvdata((x)->dev)
  74
  75 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
  76 {
  77         struct dw_pcie *pci = spear13xx_pcie->pci;
  78         struct pcie_port *pp = &pci->pp;
  79         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
  80         u32 val;
  81         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
  82
  83         if (dw_pcie_link_up(pci)) {
  84                 dev_err(pci->dev, "link already up\n");
  85                 return 0;
  86         }
  87
  88         dw_pcie_setup_rc(pp);
  89
  90         /*
  91          * this controller support only 128 bytes read size, however its
  92          * default value in capability register is 512 bytes. So force
  93          * it to 128 here.
  94          */
  95         dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
  96         val &= ~PCI_EXP_DEVCTL_READRQ;
  97         dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
  98
  99         dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
 100         dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
 101
 102         /*
 103          * if is_gen1 is set then handle it, so that some buggy card
 104          * also works
 105          */
 106         if (spear13xx_pcie->is_gen1) {
 107                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
 108                              4, &val);
 109                 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 110                         val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 111                         val |= PCI_EXP_LNKCAP_SLS_2_5GB;
 112                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 113                                       PCI_EXP_LNKCAP, 4, val);
 114                 }
 115
 116                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
 117                              2, &val);
 118                 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 119                         val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 120                         val |= PCI_EXP_LNKCAP_SLS_2_5GB;
 121                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 122                                       PCI_EXP_LNKCTL2, 2, val);
 123                 }
 124         }
 125
 126         /* enable ltssm */
 127         writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
 128                         | (1 << APP_LTSSM_ENABLE_ID)
 129                         | ((u32)1 << REG_TRANSLATION_ENABLE),
 130                         &app_reg->app_ctrl_0);
 131
 132         return dw_pcie_wait_for_link(pci);
 133 }
 134
 135 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
 136 {
 137         struct spear13xx_pcie *spear13xx_pcie = arg;
 138         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 139         struct dw_pcie *pci = spear13xx_pcie->pci;
 140         struct pcie_port *pp = &pci->pp;
 141         unsigned int status;
 142
 143         status = readl(&app_reg->int_sts);
 144
 145         if (status & MSI_CTRL_INT) {
 146                 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
 147                 dw_handle_msi_irq(pp);
 148         }
 149
 150         writel(status, &app_reg->int_clr);
 151
 152         return IRQ_HANDLED;
 153 }
 154
 155 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
 156 {
 157         struct dw_pcie *pci = spear13xx_pcie->pci;
 158         struct pcie_port *pp = &pci->pp;
 159         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 160
 161         /* Enable MSI interrupt */
 162         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 163                 dw_pcie_msi_init(pp);
 164                 writel(readl(&app_reg->int_mask) |
 165                                 MSI_CTRL_INT, &app_reg->int_mask);
 166         }
 167 }
 168
 169 static int spear13xx_pcie_link_up(struct dw_pcie *pci)
 170 {
 171         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
 172         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 173
 174         if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
 175                 return 1;
 176
 177         return 0;
 178 }
 179
 180 static int spear13xx_pcie_host_init(struct pcie_port *pp)
 181 {
 182         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 183         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
 184
 185         spear13xx_pcie_establish_link(spear13xx_pcie);
 186         spear13xx_pcie_enable_interrupts(spear13xx_pcie);
 187
 188         return 0;
 189 }
 190
 191 static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
 192         .host_init = spear13xx_pcie_host_init,
 193 };
 194
 195 static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
 196                                    struct platform_device *pdev)
 197 {
 198         struct dw_pcie *pci = spear13xx_pcie->pci;
 199         struct pcie_port *pp = &pci->pp;
 200         struct device *dev = &pdev->dev;
 201         int ret;
 202
 203         pp->irq = platform_get_irq(pdev, 0);
 204         if (pp->irq < 0) {
 205                 dev_err(dev, "failed to get irq\n");
 206                 return pp->irq;
 207         }
 208         ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
 209                                IRQF_SHARED | IRQF_NO_THREAD,
 210                                "spear1340-pcie", spear13xx_pcie);
 211         if (ret) {
 212                 dev_err(dev, "failed to request irq %d\n", pp->irq);
 213                 return ret;
 214         }
 215
 216         pp->root_bus_nr = -1;
 217         pp->ops = &spear13xx_pcie_host_ops;
 218
 219         ret = dw_pcie_host_init(pp);
 220         if (ret) {
 221                 dev_err(dev, "failed to initialize host\n");
 222                 return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static const struct dw_pcie_ops dw_pcie_ops = {
 229         .link_up = spear13xx_pcie_link_up,
 230 };
 231
 232 static int spear13xx_pcie_probe(struct platform_device *pdev)
 233 {
 234         struct device *dev = &pdev->dev;
 235         struct dw_pcie *pci;
 236         struct spear13xx_pcie *spear13xx_pcie;
 237         struct device_node *np = dev->of_node;
 238         struct resource *dbi_base;
 239         int ret;
 240
 241         spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
 242         if (!spear13xx_pcie)
 243                 return -ENOMEM;
 244
 245         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 246         if (!pci)
 247                 return -ENOMEM;
 248
 249         pci->dev = dev;
 250         pci->ops = &dw_pcie_ops;
 251
 252         spear13xx_pcie->pci = pci;
 253
 254         spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
 255         if (IS_ERR(spear13xx_pcie->phy)) {
 256                 ret = PTR_ERR(spear13xx_pcie->phy);
 257                 if (ret == -EPROBE_DEFER)
 258                         dev_info(dev, "probe deferred\n");
 259                 else
 260                         dev_err(dev, "couldn't get pcie-phy\n");
 261                 return ret;
 262         }
 263
 264         phy_init(spear13xx_pcie->phy);
 265
 266         spear13xx_pcie->clk = devm_clk_get(dev, NULL);
 267         if (IS_ERR(spear13xx_pcie->clk)) {
 268                 dev_err(dev, "couldn't get clk for pcie\n");
 269                 return PTR_ERR(spear13xx_pcie->clk);
 270         }
 271         ret = clk_prepare_enable(spear13xx_pcie->clk);
 272         if (ret) {
 273                 dev_err(dev, "couldn't enable clk for pcie\n");
 274                 return ret;
 275         }
 276
 277         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 278         pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
 279         if (IS_ERR(pci->dbi_base)) {
 280                 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
 281                 ret = PTR_ERR(pci->dbi_base);
 282                 goto fail_clk;
 283         }
 284         spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
 285
 286         if (of_property_read_bool(np, "st,pcie-is-gen1"))
 287                 spear13xx_pcie->is_gen1 = true;
 288
 289         platform_set_drvdata(pdev, spear13xx_pcie);
 290
 291         ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
 292         if (ret < 0)
 293                 goto fail_clk;
 294
 295         return 0;
 296
 297 fail_clk:
 298         clk_disable_unprepare(spear13xx_pcie->clk);
 299
 300         return ret;
 301 }
 302
 303 static const struct of_device_id spear13xx_pcie_of_match[] = {
 304         { .compatible = "st,spear1340-pcie", },
 305         {},
 306 };
 307
 308 static struct platform_driver spear13xx_pcie_driver = {
 309         .probe          = spear13xx_pcie_probe,
 310         .driver = {
 311                 .name   = "spear-pcie",
 312                 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
 313                 .suppress_bind_attrs = true,
 314         },
 315 };
 316
 317 builtin_platform_driver(spear13xx_pcie_driver);