drivers/phy/qualcomm/phy-qcom-qmp.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_address.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/slab.h>
  31
  32 #include <dt-bindings/phy/phy.h>
  33
  34 /* QMP PHY QSERDES COM registers */
  35 #define QSERDES_COM_BG_TIMER                            0x00c
  36 #define QSERDES_COM_SSC_EN_CENTER                       0x010
  37 #define QSERDES_COM_SSC_ADJ_PER1                        0x014
  38 #define QSERDES_COM_SSC_ADJ_PER2                        0x018
  39 #define QSERDES_COM_SSC_PER1                            0x01c
  40 #define QSERDES_COM_SSC_PER2                            0x020
  41 #define QSERDES_COM_SSC_STEP_SIZE1                      0x024
  42 #define QSERDES_COM_SSC_STEP_SIZE2                      0x028
  43 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN                 0x034
  44 #define QSERDES_COM_CLK_ENABLE1                         0x038
  45 #define QSERDES_COM_SYS_CLK_CTRL                        0x03c
  46 #define QSERDES_COM_SYSCLK_BUF_ENABLE                   0x040
  47 #define QSERDES_COM_PLL_IVCO                            0x048
  48 #define QSERDES_COM_LOCK_CMP1_MODE0                     0x04c
  49 #define QSERDES_COM_LOCK_CMP2_MODE0                     0x050
  50 #define QSERDES_COM_LOCK_CMP3_MODE0                     0x054
  51 #define QSERDES_COM_LOCK_CMP1_MODE1                     0x058
  52 #define QSERDES_COM_LOCK_CMP2_MODE1                     0x05c
  53 #define QSERDES_COM_LOCK_CMP3_MODE1                     0x060
  54 #define QSERDES_COM_BG_TRIM                             0x070
  55 #define QSERDES_COM_CLK_EP_DIV                          0x074
  56 #define QSERDES_COM_CP_CTRL_MODE0                       0x078
  57 #define QSERDES_COM_CP_CTRL_MODE1                       0x07c
  58 #define QSERDES_COM_PLL_RCTRL_MODE0                     0x084
  59 #define QSERDES_COM_PLL_RCTRL_MODE1                     0x088
  60 #define QSERDES_COM_PLL_CCTRL_MODE0                     0x090
  61 #define QSERDES_COM_PLL_CCTRL_MODE1                     0x094
  62 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM                 0x0a8
  63 #define QSERDES_COM_SYSCLK_EN_SEL                       0x0ac
  64 #define QSERDES_COM_RESETSM_CNTRL                       0x0b4
  65 #define QSERDES_COM_RESTRIM_CTRL                        0x0bc
  66 #define QSERDES_COM_RESCODE_DIV_NUM                     0x0c4
  67 #define QSERDES_COM_LOCK_CMP_EN                         0x0c8
  68 #define QSERDES_COM_LOCK_CMP_CFG                        0x0cc
  69 #define QSERDES_COM_DEC_START_MODE0                     0x0d0
  70 #define QSERDES_COM_DEC_START_MODE1                     0x0d4
  71 #define QSERDES_COM_DIV_FRAC_START1_MODE0               0x0dc
  72 #define QSERDES_COM_DIV_FRAC_START2_MODE0               0x0e0
  73 #define QSERDES_COM_DIV_FRAC_START3_MODE0               0x0e4
  74 #define QSERDES_COM_DIV_FRAC_START1_MODE1               0x0e8
  75 #define QSERDES_COM_DIV_FRAC_START2_MODE1               0x0ec
  76 #define QSERDES_COM_DIV_FRAC_START3_MODE1               0x0f0
  77 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0               0x108
  78 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0               0x10c
  79 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1               0x110
  80 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1               0x114
  81 #define QSERDES_COM_VCO_TUNE_CTRL                       0x124
  82 #define QSERDES_COM_VCO_TUNE_MAP                        0x128
  83 #define QSERDES_COM_VCO_TUNE1_MODE0                     0x12c
  84 #define QSERDES_COM_VCO_TUNE2_MODE0                     0x130
  85 #define QSERDES_COM_VCO_TUNE1_MODE1                     0x134
  86 #define QSERDES_COM_VCO_TUNE2_MODE1                     0x138
  87 #define QSERDES_COM_VCO_TUNE_TIMER1                     0x144
  88 #define QSERDES_COM_VCO_TUNE_TIMER2                     0x148
  89 #define QSERDES_COM_BG_CTRL                             0x170
  90 #define QSERDES_COM_CLK_SELECT                          0x174
  91 #define QSERDES_COM_HSCLK_SEL                           0x178
  92 #define QSERDES_COM_CORECLK_DIV                         0x184
  93 #define QSERDES_COM_CORE_CLK_EN                         0x18c
  94 #define QSERDES_COM_C_READY_STATUS                      0x190
  95 #define QSERDES_COM_CMN_CONFIG                          0x194
  96 #define QSERDES_COM_SVS_MODE_CLK_SEL                    0x19c
  97 #define QSERDES_COM_DEBUG_BUS0                          0x1a0
  98 #define QSERDES_COM_DEBUG_BUS1                          0x1a4
  99 #define QSERDES_COM_DEBUG_BUS2                          0x1a8
 100 #define QSERDES_COM_DEBUG_BUS3                          0x1ac
 101 #define QSERDES_COM_DEBUG_BUS_SEL                       0x1b0
 102 #define QSERDES_COM_CORECLK_DIV_MODE1                   0x1bc
 103
 104 /* QMP PHY TX registers */
 105 #define QSERDES_TX_EMP_POST1_LVL                        0x018
 106 #define QSERDES_TX_SLEW_CNTL                            0x040
 107 #define QSERDES_TX_RES_CODE_LANE_OFFSET                 0x054
 108 #define QSERDES_TX_DEBUG_BUS_SEL                        0x064
 109 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN     0x068
 110 #define QSERDES_TX_LANE_MODE                            0x094
 111 #define QSERDES_TX_RCV_DETECT_LVL_2                     0x0ac
 112
 113 /* QMP PHY RX registers */
 114 #define QSERDES_RX_UCDR_SO_GAIN_HALF                    0x010
 115 #define QSERDES_RX_UCDR_SO_GAIN                         0x01c
 116 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN                0x040
 117 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE        0x048
 118 #define QSERDES_RX_RX_TERM_BW                           0x090
 119 #define QSERDES_RX_RX_EQ_GAIN1_LSB                      0x0c4
 120 #define QSERDES_RX_RX_EQ_GAIN1_MSB                      0x0c8
 121 #define QSERDES_RX_RX_EQ_GAIN2_LSB                      0x0cc
 122 #define QSERDES_RX_RX_EQ_GAIN2_MSB                      0x0d0
 123 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2                0x0d8
 124 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3                0x0dc
 125 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4                0x0e0
 126 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1          0x108
 127 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2             0x10c
 128 #define QSERDES_RX_SIGDET_ENABLES                       0x110
 129 #define QSERDES_RX_SIGDET_CNTRL                         0x114
 130 #define QSERDES_RX_SIGDET_LVL                           0x118
 131 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL                0x11c
 132 #define QSERDES_RX_RX_BAND                              0x120
 133 #define QSERDES_RX_RX_INTERFACE_MODE                    0x12c
 134
 135 /* QMP PHY PCS registers */
 136 #define QPHY_POWER_DOWN_CONTROL                         0x04
 137 #define QPHY_TXDEEMPH_M6DB_V0                           0x24
 138 #define QPHY_TXDEEMPH_M3P5DB_V0                         0x28
 139 #define QPHY_ENDPOINT_REFCLK_DRIVE                      0x54
 140 #define QPHY_RX_IDLE_DTCT_CNTRL                         0x58
 141 #define QPHY_POWER_STATE_CONFIG1                        0x60
 142 #define QPHY_POWER_STATE_CONFIG2                        0x64
 143 #define QPHY_POWER_STATE_CONFIG4                        0x6c
 144 #define QPHY_LOCK_DETECT_CONFIG1                        0x80
 145 #define QPHY_LOCK_DETECT_CONFIG2                        0x84
 146 #define QPHY_LOCK_DETECT_CONFIG3                        0x88
 147 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK                0xa0
 148 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK                  0xa4
 149 #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB           0x1A8
 150 #define QPHY_OSC_DTCT_ACTIONS                           0x1AC
 151 #define QPHY_RX_SIGDET_LVL                              0x1D8
 152 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB            0x1DC
 153 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB            0x1E0
 154
 155 /* QPHY_SW_RESET bit */
 156 #define SW_RESET                                BIT(0)
 157 /* QPHY_POWER_DOWN_CONTROL */
 158 #define SW_PWRDN                                BIT(0)
 159 #define REFCLK_DRV_DSBL                         BIT(1)
 160 /* QPHY_START_CONTROL bits */
 161 #define SERDES_START                            BIT(0)
 162 #define PCS_START                               BIT(1)
 163 #define PLL_READY_GATE_EN                       BIT(3)
 164 /* QPHY_PCS_STATUS bit */
 165 #define PHYSTATUS                               BIT(6)
 166 /* QPHY_COM_PCS_READY_STATUS bit */
 167 #define PCS_READY                               BIT(0)
 168
 169 #define PHY_INIT_COMPLETE_TIMEOUT               1000
 170 #define POWER_DOWN_DELAY_US_MIN                 10
 171 #define POWER_DOWN_DELAY_US_MAX                 11
 172
 173 #define MAX_PROP_NAME                           32
 174
 175 struct qmp_phy_init_tbl {
 176         unsigned int offset;
 177         unsigned int val;
 178         /*
 179          * register part of layout ?
 180          * if yes, then offset gives index in the reg-layout
 181          */
 182         int in_layout;
 183 };
 184
 185 #define QMP_PHY_INIT_CFG(o, v)          \
 186         {                               \
 187                 .offset = o,            \
 188                 .val = v,               \
 189         }
 190
 191 #define QMP_PHY_INIT_CFG_L(o, v)        \
 192         {                               \
 193                 .offset = o,            \
 194                 .val = v,               \
 195                 .in_layout = 1,         \
 196         }
 197
 198 /* set of registers with offsets different per-PHY */
 199 enum qphy_reg_layout {
 200         /* Common block control registers */
 201         QPHY_COM_SW_RESET,
 202         QPHY_COM_POWER_DOWN_CONTROL,
 203         QPHY_COM_START_CONTROL,
 204         QPHY_COM_PCS_READY_STATUS,
 205         /* PCS registers */
 206         QPHY_PLL_LOCK_CHK_DLY_TIME,
 207         QPHY_FLL_CNTRL1,
 208         QPHY_FLL_CNTRL2,
 209         QPHY_FLL_CNT_VAL_L,
 210         QPHY_FLL_CNT_VAL_H_TOL,
 211         QPHY_FLL_MAN_CODE,
 212         QPHY_SW_RESET,
 213         QPHY_START_CTRL,
 214         QPHY_PCS_READY_STATUS,
 215 };
 216
 217 static const unsigned int pciephy_regs_layout[] = {
 218         [QPHY_COM_SW_RESET]             = 0x400,
 219         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 220         [QPHY_COM_START_CONTROL]        = 0x408,
 221         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 222         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 223         [QPHY_FLL_CNTRL1]               = 0xc4,
 224         [QPHY_FLL_CNTRL2]               = 0xc8,
 225         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 226         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 227         [QPHY_FLL_MAN_CODE]             = 0xd4,
 228         [QPHY_SW_RESET]                 = 0x00,
 229         [QPHY_START_CTRL]               = 0x08,
 230         [QPHY_PCS_READY_STATUS]         = 0x174,
 231 };
 232
 233 static const unsigned int usb3phy_regs_layout[] = {
 234         [QPHY_FLL_CNTRL1]               = 0xc0,
 235         [QPHY_FLL_CNTRL2]               = 0xc4,
 236         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 237         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 238         [QPHY_FLL_MAN_CODE]             = 0xd0,
 239         [QPHY_SW_RESET]                 = 0x00,
 240         [QPHY_START_CTRL]               = 0x08,
 241         [QPHY_PCS_READY_STATUS]         = 0x17c,
 242 };
 243
 244 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 245         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 247         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 248         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 263         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 264         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 272         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 278         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 279         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 280         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 288 };
 289
 290 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 291         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 292         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 293 };
 294
 295 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 296         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 297         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 298         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 299         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 300         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 301         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 302         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 303         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 304         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 305         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 306 };
 307
 308 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 309         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 310         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 311         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 312
 313         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 314
 315         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 316         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 317         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 318         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 319         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 320 };
 321
 322 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 323         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 332         /* PLL and Loop filter settings */
 333         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 338         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 349         /* SSC settings */
 350         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 355         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 357 };
 358
 359 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 360         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 361         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 362         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 363 };
 364
 365 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 366         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 367         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 368         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 369         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 370         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 371         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 372         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 373         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 374         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 375         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 376 };
 377
 378 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 379         /* FLL settings */
 380         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 381         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 382         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 383         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 384         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 385
 386         /* Lock Det settings */
 387         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 388         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 389         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 390         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 391 };
 392
 393 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 394         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 395         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 396         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 397         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 398         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 399         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 400         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 401         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 402         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 403         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 404         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 405         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 406         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 407         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 408         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 409         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 410         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 411         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 412         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 413         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 414         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 415         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 416         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 417         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 418         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 419         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 420         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 421         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 422         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 423         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 424         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 425         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 426         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 427         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 428         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 429         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 430         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 431         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 432         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 433         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 434 };
 435
 436 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 437         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 438         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 439         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 440         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 441         QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 442         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 443 };
 444
 445 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 446         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 447         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 448         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 449         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 450         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 451         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 452         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 453 };
 454
 455 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 456         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 457         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 458         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 459         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 460         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 461         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 462         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 463         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 464         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 465         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 466         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 467         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 468         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 469 };
 470
 471 /* struct qmp_phy_cfg - per-PHY initialization config */
 472 struct qmp_phy_cfg {
 473         /* phy-type - PCIE/UFS/USB */
 474         unsigned int type;
 475         /* number of lanes provided by phy */
 476         int nlanes;
 477
 478         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 479         const struct qmp_phy_init_tbl *serdes_tbl;
 480         int serdes_tbl_num;
 481         const struct qmp_phy_init_tbl *tx_tbl;
 482         int tx_tbl_num;
 483         const struct qmp_phy_init_tbl *rx_tbl;
 484         int rx_tbl_num;
 485         const struct qmp_phy_init_tbl *pcs_tbl;
 486         int pcs_tbl_num;
 487
 488         /* clock ids to be requested */
 489         const char * const *clk_list;
 490         int num_clks;
 491         /* resets to be requested */
 492         const char * const *reset_list;
 493         int num_resets;
 494         /* regulators to be requested */
 495         const char * const *vreg_list;
 496         int num_vregs;
 497
 498         /* array of registers with different offsets */
 499         const unsigned int *regs;
 500
 501         unsigned int start_ctrl;
 502         unsigned int pwrdn_ctrl;
 503         unsigned int mask_pcs_ready;
 504         unsigned int mask_com_pcs_ready;
 505
 506         /* true, if PHY has a separate PHY_COM control block */
 507         bool has_phy_com_ctrl;
 508         /* true, if PHY has a reset for individual lanes */
 509         bool has_lane_rst;
 510         /* true, if PHY needs delay after POWER_DOWN */
 511         bool has_pwrdn_delay;
 512         /* power_down delay in usec */
 513         int pwrdn_delay_min;
 514         int pwrdn_delay_max;
 515 };
 516
 517 /**
 518  * struct qmp_phy - per-lane phy descriptor
 519  *
 520  * @phy: generic phy
 521  * @tx: iomapped memory space for lane's tx
 522  * @rx: iomapped memory space for lane's rx
 523  * @pcs: iomapped memory space for lane's pcs
 524  * @pipe_clk: pipe lock
 525  * @index: lane index
 526  * @qmp: QMP phy to which this lane belongs
 527  * @lane_rst: lane's reset controller
 528  */
 529 struct qmp_phy {
 530         struct phy *phy;
 531         void __iomem *tx;
 532         void __iomem *rx;
 533         void __iomem *pcs;
 534         struct clk *pipe_clk;
 535         unsigned int index;
 536         struct qcom_qmp *qmp;
 537         struct reset_control *lane_rst;
 538 };
 539
 540 /**
 541  * struct qcom_qmp - structure holding QMP phy block attributes
 542  *
 543  * @dev: device
 544  * @serdes: iomapped memory space for phy's serdes
 545  *
 546  * @clks: array of clocks required by phy
 547  * @resets: array of resets required by phy
 548  * @vregs: regulator supplies bulk data
 549  *
 550  * @cfg: phy specific configuration
 551  * @phys: array of per-lane phy descriptors
 552  * @phy_mutex: mutex lock for PHY common block initialization
 553  * @init_count: phy common block initialization count
 554  */
 555 struct qcom_qmp {
 556         struct device *dev;
 557         void __iomem *serdes;
 558
 559         struct clk **clks;
 560         struct reset_control **resets;
 561         struct regulator_bulk_data *vregs;
 562
 563         const struct qmp_phy_cfg *cfg;
 564         struct qmp_phy **phys;
 565
 566         struct mutex phy_mutex;
 567         int init_count;
 568 };
 569
 570 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 571 {
 572         u32 reg;
 573
 574         reg = readl(base + offset);
 575         reg |= val;
 576         writel(reg, base + offset);
 577
 578         /* ensure that above write is through */
 579         readl(base + offset);
 580 }
 581
 582 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 583 {
 584         u32 reg;
 585
 586         reg = readl(base + offset);
 587         reg &= ~val;
 588         writel(reg, base + offset);
 589
 590         /* ensure that above write is through */
 591         readl(base + offset);
 592 }
 593
 594 /* list of clocks required by phy */
 595 static const char * const msm8996_phy_clk_l[] = {
 596         "aux", "cfg_ahb", "ref",
 597 };
 598
 599 /* list of resets */
 600 static const char * const msm8996_pciephy_reset_l[] = {
 601         "phy", "common", "cfg",
 602 };
 603
 604 static const char * const msm8996_usb3phy_reset_l[] = {
 605         "phy", "common",
 606 };
 607
 608 /* list of regulators */
 609 static const char * const msm8996_phy_vreg_l[] = {
 610         "vdda-phy", "vdda-pll",
 611 };
 612
 613 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
 614         .type                   = PHY_TYPE_PCIE,
 615         .nlanes                 = 3,
 616
 617         .serdes_tbl             = msm8996_pcie_serdes_tbl,
 618         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
 619         .tx_tbl                 = msm8996_pcie_tx_tbl,
 620         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
 621         .rx_tbl                 = msm8996_pcie_rx_tbl,
 622         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
 623         .pcs_tbl                = msm8996_pcie_pcs_tbl,
 624         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
 625         .clk_list               = msm8996_phy_clk_l,
 626         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 627         .reset_list             = msm8996_pciephy_reset_l,
 628         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
 629         .vreg_list              = msm8996_phy_vreg_l,
 630         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 631         .regs                   = pciephy_regs_layout,
 632
 633         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
 634         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 635         .mask_com_pcs_ready     = PCS_READY,
 636
 637         .has_phy_com_ctrl       = true,
 638         .has_lane_rst           = true,
 639         .has_pwrdn_delay        = true,
 640         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 641         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 642 };
 643
 644 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 645         .type                   = PHY_TYPE_USB3,
 646         .nlanes                 = 1,
 647
 648         .serdes_tbl             = msm8996_usb3_serdes_tbl,
 649         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
 650         .tx_tbl                 = msm8996_usb3_tx_tbl,
 651         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
 652         .rx_tbl                 = msm8996_usb3_rx_tbl,
 653         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
 654         .pcs_tbl                = msm8996_usb3_pcs_tbl,
 655         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
 656         .clk_list               = msm8996_phy_clk_l,
 657         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 658         .reset_list             = msm8996_usb3phy_reset_l,
 659         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 660         .vreg_list              = msm8996_phy_vreg_l,
 661         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 662         .regs                   = usb3phy_regs_layout,
 663
 664         .start_ctrl             = SERDES_START | PCS_START,
 665         .pwrdn_ctrl             = SW_PWRDN,
 666         .mask_pcs_ready         = PHYSTATUS,
 667 };
 668
 669 static const char * const ipq8074_pciephy_clk_l[] = {
 670         "aux", "cfg_ahb",
 671 };
 672 /* list of resets */
 673 static const char * const ipq8074_pciephy_reset_l[] = {
 674         "phy", "common",
 675 };
 676
 677 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 678         .type                   = PHY_TYPE_PCIE,
 679         .nlanes                 = 1,
 680
 681         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
 682         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
 683         .tx_tbl                 = ipq8074_pcie_tx_tbl,
 684         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
 685         .rx_tbl                 = ipq8074_pcie_rx_tbl,
 686         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
 687         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
 688         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
 689         .clk_list               = ipq8074_pciephy_clk_l,
 690         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
 691         .reset_list             = ipq8074_pciephy_reset_l,
 692         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
 693         .vreg_list              = NULL,
 694         .num_vregs              = 0,
 695         .regs                   = pciephy_regs_layout,
 696
 697         .start_ctrl             = SERDES_START | PCS_START,
 698         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 699         .mask_pcs_ready         = PHYSTATUS,
 700
 701         .has_phy_com_ctrl       = false,
 702         .has_lane_rst           = false,
 703         .has_pwrdn_delay        = true,
 704         .pwrdn_delay_min        = 995,          /* us */
 705         .pwrdn_delay_max        = 1005,         /* us */
 706 };
 707
 708 static void qcom_qmp_phy_configure(void __iomem *base,
 709                                    const unsigned int *regs,
 710                                    const struct qmp_phy_init_tbl tbl[],
 711                                    int num)
 712 {
 713         int i;
 714         const struct qmp_phy_init_tbl *t = tbl;
 715
 716         if (!t)
 717                 return;
 718
 719         for (i = 0; i < num; i++, t++) {
 720                 if (t->in_layout)
 721                         writel(t->val, base + regs[t->offset]);
 722                 else
 723                         writel(t->val, base + t->offset);
 724         }
 725 }
 726
 727 static int qcom_qmp_phy_poweron(struct phy *phy)
 728 {
 729         struct qmp_phy *qphy = phy_get_drvdata(phy);
 730         struct qcom_qmp *qmp = qphy->qmp;
 731         int num = qmp->cfg->num_vregs;
 732         int ret;
 733
 734         dev_vdbg(&phy->dev, "Powering on QMP phy\n");
 735
 736         /* turn on regulator supplies */
 737         ret = regulator_bulk_enable(num, qmp->vregs);
 738         if (ret) {
 739                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
 740                 return ret;
 741         }
 742
 743         ret = clk_prepare_enable(qphy->pipe_clk);
 744         if (ret) {
 745                 dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret);
 746                 regulator_bulk_disable(num, qmp->vregs);
 747                 return ret;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int qcom_qmp_phy_poweroff(struct phy *phy)
 754 {
 755         struct qmp_phy *qphy = phy_get_drvdata(phy);
 756         struct qcom_qmp *qmp = qphy->qmp;
 757
 758         regulator_bulk_disable(qmp->cfg->num_vregs, qmp->vregs);
 759
 760         return 0;
 761 }
 762
 763 static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
 764 {
 765         const struct qmp_phy_cfg *cfg = qmp->cfg;
 766         void __iomem *serdes = qmp->serdes;
 767         int ret, i;
 768
 769         mutex_lock(&qmp->phy_mutex);
 770         if (qmp->init_count++) {
 771                 mutex_unlock(&qmp->phy_mutex);
 772                 return 0;
 773         }
 774
 775         for (i = 0; i < cfg->num_resets; i++) {
 776                 ret = reset_control_deassert(qmp->resets[i]);
 777                 if (ret) {
 778                         dev_err(qmp->dev, "%s reset deassert failed\n",
 779                                 qmp->cfg->reset_list[i]);
 780                         goto err_rst;
 781                 }
 782         }
 783
 784         if (cfg->has_phy_com_ctrl)
 785                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
 786                              SW_PWRDN);
 787
 788         /* Serdes configuration */
 789         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
 790                                cfg->serdes_tbl_num);
 791
 792         if (cfg->has_phy_com_ctrl) {
 793                 void __iomem *status;
 794                 unsigned int mask, val;
 795
 796                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
 797                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
 798                              SERDES_START | PCS_START);
 799
 800                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
 801                 mask = cfg->mask_com_pcs_ready;
 802
 803                 ret = readl_poll_timeout(status, val, (val & mask), 10,
 804                                          PHY_INIT_COMPLETE_TIMEOUT);
 805                 if (ret) {
 806                         dev_err(qmp->dev,
 807                                 "phy common block init timed-out\n");
 808                         goto err_rst;
 809                 }
 810         }
 811
 812         mutex_unlock(&qmp->phy_mutex);
 813
 814         return 0;
 815
 816 err_rst:
 817         while (--i >= 0)
 818                 reset_control_assert(qmp->resets[i]);
 819         mutex_unlock(&qmp->phy_mutex);
 820
 821         return ret;
 822 }
 823
 824 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
 825 {
 826         const struct qmp_phy_cfg *cfg = qmp->cfg;
 827         void __iomem *serdes = qmp->serdes;
 828         int i = cfg->num_resets;
 829
 830         mutex_lock(&qmp->phy_mutex);
 831         if (--qmp->init_count) {
 832                 mutex_unlock(&qmp->phy_mutex);
 833                 return 0;
 834         }
 835
 836         if (cfg->has_phy_com_ctrl) {
 837                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
 838                              SERDES_START | PCS_START);
 839                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
 840                              SW_RESET);
 841                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
 842                              SW_PWRDN);
 843         }
 844
 845         while (--i >= 0)
 846                 reset_control_assert(qmp->resets[i]);
 847
 848         mutex_unlock(&qmp->phy_mutex);
 849
 850         return 0;
 851 }
 852
 853 /* PHY Initialization */
 854 static int qcom_qmp_phy_init(struct phy *phy)
 855 {
 856         struct qmp_phy *qphy = phy_get_drvdata(phy);
 857         struct qcom_qmp *qmp = qphy->qmp;
 858         const struct qmp_phy_cfg *cfg = qmp->cfg;
 859         void __iomem *tx = qphy->tx;
 860         void __iomem *rx = qphy->rx;
 861         void __iomem *pcs = qphy->pcs;
 862         void __iomem *status;
 863         unsigned int mask, val;
 864         int ret, i;
 865
 866         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
 867
 868         for (i = 0; i < qmp->cfg->num_clks; i++) {
 869                 ret = clk_prepare_enable(qmp->clks[i]);
 870                 if (ret) {
 871                         dev_err(qmp->dev, "failed to enable %s clk, err=%d\n",
 872                                 qmp->cfg->clk_list[i], ret);
 873                         goto err_clk;
 874                 }
 875         }
 876
 877         ret = qcom_qmp_phy_com_init(qmp);
 878         if (ret)
 879                 goto err_clk;
 880
 881         if (cfg->has_lane_rst) {
 882                 ret = reset_control_deassert(qphy->lane_rst);
 883                 if (ret) {
 884                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
 885                                 qphy->index);
 886                         goto err_lane_rst;
 887                 }
 888         }
 889
 890         /* Tx, Rx, and PCS configurations */
 891         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
 892         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
 893         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
 894
 895         /*
 896          * Pull out PHY from POWER DOWN state.
 897          * This is active low enable signal to power-down PHY.
 898          */
 899         qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
 900
 901         if (cfg->has_pwrdn_delay)
 902                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
 903
 904         /* start SerDes and Phy-Coding-Sublayer */
 905         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
 906
 907         /* Pull PHY out of reset state */
 908         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 909
 910         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
 911         mask = cfg->mask_pcs_ready;
 912
 913         ret = readl_poll_timeout(status, val, !(val & mask), 1,
 914                                  PHY_INIT_COMPLETE_TIMEOUT);
 915         if (ret) {
 916                 dev_err(qmp->dev, "phy initialization timed-out\n");
 917                 goto err_pcs_ready;
 918         }
 919
 920         return ret;
 921
 922 err_pcs_ready:
 923         if (cfg->has_lane_rst)
 924                 reset_control_assert(qphy->lane_rst);
 925 err_lane_rst:
 926         qcom_qmp_phy_com_exit(qmp);
 927 err_clk:
 928         while (--i >= 0)
 929                 clk_disable_unprepare(qmp->clks[i]);
 930
 931         return ret;
 932 }
 933
 934 static int qcom_qmp_phy_exit(struct phy *phy)
 935 {
 936         struct qmp_phy *qphy = phy_get_drvdata(phy);
 937         struct qcom_qmp *qmp = qphy->qmp;
 938         const struct qmp_phy_cfg *cfg = qmp->cfg;
 939         int i = cfg->num_clks;
 940
 941         clk_disable_unprepare(qphy->pipe_clk);
 942
 943         /* PHY reset */
 944         qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 945
 946         /* stop SerDes and Phy-Coding-Sublayer */
 947         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
 948
 949         /* Put PHY into POWER DOWN state: active low */
 950         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
 951
 952         if (cfg->has_lane_rst)
 953                 reset_control_assert(qphy->lane_rst);
 954
 955         qcom_qmp_phy_com_exit(qmp);
 956
 957         while (--i >= 0)
 958                 clk_disable_unprepare(qmp->clks[i]);
 959
 960         return 0;
 961 }
 962
 963 static int qcom_qmp_phy_vreg_init(struct device *dev)
 964 {
 965         struct qcom_qmp *qmp = dev_get_drvdata(dev);
 966         int num = qmp->cfg->num_vregs;
 967         int i;
 968
 969         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
 970         if (!qmp->vregs)
 971                 return -ENOMEM;
 972
 973         for (i = 0; i < num; i++)
 974                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
 975
 976         return devm_regulator_bulk_get(dev, num, qmp->vregs);
 977 }
 978
 979 static int qcom_qmp_phy_reset_init(struct device *dev)
 980 {
 981         struct qcom_qmp *qmp = dev_get_drvdata(dev);
 982         int i;
 983
 984         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
 985                                    sizeof(*qmp->resets), GFP_KERNEL);
 986         if (!qmp->resets)
 987                 return -ENOMEM;
 988
 989         for (i = 0; i < qmp->cfg->num_resets; i++) {
 990                 struct reset_control *rst;
 991                 const char *name = qmp->cfg->reset_list[i];
 992
 993                 rst = devm_reset_control_get(dev, name);
 994                 if (IS_ERR(rst)) {
 995                         dev_err(dev, "failed to get %s reset\n", name);
 996                         return PTR_ERR(rst);
 997                 }
 998                 qmp->resets[i] = rst;
 999         }
1000
1001         return 0;
1002 }
1003
1004 static int qcom_qmp_phy_clk_init(struct device *dev)
1005 {
1006         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1007         int ret, i;
1008
1009         qmp->clks = devm_kcalloc(dev, qmp->cfg->num_clks,
1010                                  sizeof(*qmp->clks), GFP_KERNEL);
1011         if (!qmp->clks)
1012                 return -ENOMEM;
1013
1014         for (i = 0; i < qmp->cfg->num_clks; i++) {
1015                 struct clk *_clk;
1016                 const char *name = qmp->cfg->clk_list[i];
1017
1018                 _clk = devm_clk_get(dev, name);
1019                 if (IS_ERR(_clk)) {
1020                         ret = PTR_ERR(_clk);
1021                         if (ret != -EPROBE_DEFER)
1022                                 dev_err(dev, "failed to get %s clk, %d\n",
1023                                         name, ret);
1024                         return ret;
1025                 }
1026                 qmp->clks[i] = _clk;
1027         }
1028
1029         return 0;
1030 }
1031
1032 /*
1033  * Register a fixed rate pipe clock.
1034  *
1035  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1036  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1037  * by the PHY driver for its operations.
1038  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1039  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1040  * Below picture shows this relationship.
1041  *
1042  *         +---------------+
1043  *         |   PHY block   |<<---------------------------------------+
1044  *         |               |                                         |
1045  *         |   +-------+   |                   +-----+               |
1046  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1047  *    clk  |   +-------+   |                   +-----+
1048  *         +---------------+
1049  */
1050 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1051 {
1052         struct clk_fixed_rate *fixed;
1053         struct clk_init_data init = { };
1054         int ret;
1055
1056         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1057             (qmp->cfg->type != PHY_TYPE_PCIE)) {
1058                 /* not all phys register pipe clocks, so return success */
1059                 return 0;
1060         }
1061
1062         ret = of_property_read_string(np, "clock-output-names", &init.name);
1063         if (ret) {
1064                 dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
1065                 return ret;
1066         }
1067
1068         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1069         if (!fixed)
1070                 return -ENOMEM;
1071
1072         init.ops = &clk_fixed_rate_ops;
1073
1074         /* controllers using QMP phys use 125MHz pipe clock interface */
1075         fixed->fixed_rate = 125000000;
1076         fixed->hw.init = &init;
1077
1078         return devm_clk_hw_register(qmp->dev, &fixed->hw);
1079 }
1080
1081 static const struct phy_ops qcom_qmp_phy_gen_ops = {
1082         .init           = qcom_qmp_phy_init,
1083         .exit           = qcom_qmp_phy_exit,
1084         .power_on       = qcom_qmp_phy_poweron,
1085         .power_off      = qcom_qmp_phy_poweroff,
1086         .owner          = THIS_MODULE,
1087 };
1088
1089 static
1090 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1091 {
1092         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1093         struct phy *generic_phy;
1094         struct qmp_phy *qphy;
1095         char prop_name[MAX_PROP_NAME];
1096         int ret;
1097
1098         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1099         if (!qphy)
1100                 return -ENOMEM;
1101
1102         /*
1103          * Get memory resources for each phy lane:
1104          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1105          */
1106         qphy->tx = of_iomap(np, 0);
1107         if (!qphy->tx)
1108                 return -ENOMEM;
1109
1110         qphy->rx = of_iomap(np, 1);
1111         if (!qphy->rx)
1112                 return -ENOMEM;
1113
1114         qphy->pcs = of_iomap(np, 2);
1115         if (!qphy->pcs)
1116                 return -ENOMEM;
1117
1118         /*
1119          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1120          * based phys, so they essentially have pipe clock. So,
1121          * we return error in case phy is USB3 or PIPE type.
1122          * Otherwise, we initialize pipe clock to NULL for
1123          * all phys that don't need this.
1124          */
1125         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1126         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1127         if (IS_ERR(qphy->pipe_clk)) {
1128                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1129                     qmp->cfg->type == PHY_TYPE_USB3) {
1130                         ret = PTR_ERR(qphy->pipe_clk);
1131                         if (ret != -EPROBE_DEFER)
1132                                 dev_err(dev,
1133                                         "failed to get lane%d pipe_clk, %d\n",
1134                                         id, ret);
1135                         return ret;
1136                 }
1137                 qphy->pipe_clk = NULL;
1138         }
1139
1140         /* Get lane reset, if any */
1141         if (qmp->cfg->has_lane_rst) {
1142                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1143                 qphy->lane_rst = of_reset_control_get(np, prop_name);
1144                 if (IS_ERR(qphy->lane_rst)) {
1145                         dev_err(dev, "failed to get lane%d reset\n", id);
1146                         return PTR_ERR(qphy->lane_rst);
1147                 }
1148         }
1149
1150         generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
1151         if (IS_ERR(generic_phy)) {
1152                 ret = PTR_ERR(generic_phy);
1153                 dev_err(dev, "failed to create qphy %d\n", ret);
1154                 return ret;
1155         }
1156
1157         qphy->phy = generic_phy;
1158         qphy->index = id;
1159         qphy->qmp = qmp;
1160         qmp->phys[id] = qphy;
1161         phy_set_drvdata(generic_phy, qphy);
1162
1163         return 0;
1164 }
1165
1166 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1167         {
1168                 .compatible = "qcom,msm8996-qmp-pcie-phy",
1169                 .data = &msm8996_pciephy_cfg,
1170         }, {
1171                 .compatible = "qcom,msm8996-qmp-usb3-phy",
1172                 .data = &msm8996_usb3phy_cfg,
1173         }, {
1174                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1175                 .data = &ipq8074_pciephy_cfg,
1176         },
1177         { },
1178 };
1179 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
1180
1181 static int qcom_qmp_phy_probe(struct platform_device *pdev)
1182 {
1183         struct qcom_qmp *qmp;
1184         struct device *dev = &pdev->dev;
1185         struct resource *res;
1186         struct device_node *child;
1187         struct phy_provider *phy_provider;
1188         void __iomem *base;
1189         int num, id;
1190         int ret;
1191
1192         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1193         if (!qmp)
1194                 return -ENOMEM;
1195
1196         qmp->dev = dev;
1197         dev_set_drvdata(dev, qmp);
1198
1199         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200         base = devm_ioremap_resource(dev, res);
1201         if (IS_ERR(base))
1202                 return PTR_ERR(base);
1203
1204         /* per PHY serdes; usually located at base address */
1205         qmp->serdes = base;
1206
1207         mutex_init(&qmp->phy_mutex);
1208
1209         /* Get the specific init parameters of QMP phy */
1210         qmp->cfg = of_device_get_match_data(dev);
1211
1212         ret = qcom_qmp_phy_clk_init(dev);
1213         if (ret)
1214                 return ret;
1215
1216         ret = qcom_qmp_phy_reset_init(dev);
1217         if (ret)
1218                 return ret;
1219
1220         ret = qcom_qmp_phy_vreg_init(dev);
1221         if (ret) {
1222                 dev_err(dev, "failed to get regulator supplies\n");
1223                 return ret;
1224         }
1225
1226         num = of_get_available_child_count(dev->of_node);
1227         /* do we have a rogue child node ? */
1228         if (num > qmp->cfg->nlanes)
1229                 return -EINVAL;
1230
1231         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
1232         if (!qmp->phys)
1233                 return -ENOMEM;
1234
1235         id = 0;
1236         for_each_available_child_of_node(dev->of_node, child) {
1237                 /* Create per-lane phy */
1238                 ret = qcom_qmp_phy_create(dev, child, id);
1239                 if (ret) {
1240                         dev_err(dev, "failed to create lane%d phy, %d\n",
1241                                 id, ret);
1242                         return ret;
1243                 }
1244
1245                 /*
1246                  * Register the pipe clock provided by phy.
1247                  * See function description to see details of this pipe clock.
1248                  */
1249                 ret = phy_pipe_clk_register(qmp, child);
1250                 if (ret) {
1251                         dev_err(qmp->dev,
1252                                 "failed to register pipe clock source\n");
1253                         return ret;
1254                 }
1255                 id++;
1256         }
1257
1258         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1259         if (!IS_ERR(phy_provider))
1260                 dev_info(dev, "Registered Qcom-QMP phy\n");
1261
1262         return PTR_ERR_OR_ZERO(phy_provider);
1263 }
1264
1265 static struct platform_driver qcom_qmp_phy_driver = {
1266         .probe          = qcom_qmp_phy_probe,
1267         .driver = {
1268                 .name   = "qcom-qmp-phy",
1269                 .of_match_table = qcom_qmp_phy_of_match_table,
1270         },
1271 };
1272
1273 module_platform_driver(qcom_qmp_phy_driver);
1274
1275 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1276 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
1277 MODULE_LICENSE("GPL v2");