drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 struct qmp_phy_init_tbl {
  76         unsigned int offset;
  77         unsigned int val;
  78         /*
  79          * register part of layout ?
  80          * if yes, then offset gives index in the reg-layout
  81          */
  82         int in_layout;
  83 };
  84
  85 #define QMP_PHY_INIT_CFG(o, v)          \
  86         {                               \
  87                 .offset = o,            \
  88                 .val = v,               \
  89         }
  90
  91 #define QMP_PHY_INIT_CFG_L(o, v)        \
  92         {                               \
  93                 .offset = o,            \
  94                 .val = v,               \
  95                 .in_layout = 1,         \
  96         }
  97
  98 /* set of registers with offsets different per-PHY */
  99 enum qphy_reg_layout {
 100         /* Common block control registers */
 101         QPHY_COM_SW_RESET,
 102         QPHY_COM_POWER_DOWN_CONTROL,
 103         QPHY_COM_START_CONTROL,
 104         QPHY_COM_PCS_READY_STATUS,
 105         /* PCS registers */
 106         QPHY_PLL_LOCK_CHK_DLY_TIME,
 107         QPHY_FLL_CNTRL1,
 108         QPHY_FLL_CNTRL2,
 109         QPHY_FLL_CNT_VAL_L,
 110         QPHY_FLL_CNT_VAL_H_TOL,
 111         QPHY_FLL_MAN_CODE,
 112         QPHY_SW_RESET,
 113         QPHY_START_CTRL,
 114         QPHY_PCS_READY_STATUS,
 115         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 116         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 117         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 118 };
 119
 120 static const unsigned int pciephy_regs_layout[] = {
 121         [QPHY_COM_SW_RESET]             = 0x400,
 122         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 123         [QPHY_COM_START_CONTROL]        = 0x408,
 124         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 125         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 126         [QPHY_FLL_CNTRL1]               = 0xc4,
 127         [QPHY_FLL_CNTRL2]               = 0xc8,
 128         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 129         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 130         [QPHY_FLL_MAN_CODE]             = 0xd4,
 131         [QPHY_SW_RESET]                 = 0x00,
 132         [QPHY_START_CTRL]               = 0x08,
 133         [QPHY_PCS_READY_STATUS]         = 0x174,
 134 };
 135
 136 static const unsigned int usb3phy_regs_layout[] = {
 137         [QPHY_FLL_CNTRL1]               = 0xc0,
 138         [QPHY_FLL_CNTRL2]               = 0xc4,
 139         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 140         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 141         [QPHY_FLL_MAN_CODE]             = 0xd0,
 142         [QPHY_SW_RESET]                 = 0x00,
 143         [QPHY_START_CTRL]               = 0x08,
 144         [QPHY_PCS_READY_STATUS]         = 0x17c,
 145         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 146         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 147         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 148 };
 149
 150 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 151         [QPHY_SW_RESET]                 = 0x00,
 152         [QPHY_START_CTRL]               = 0x08,
 153         [QPHY_PCS_READY_STATUS]         = 0x174,
 154         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 155         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 156         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 157 };
 158
 159 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 160         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 161         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 162         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 163         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 164         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 165         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 166         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 167         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 168         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 169         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 176         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 177         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 178         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 181         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 182         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 188         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 189         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 190         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 191         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 192         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 203 };
 204
 205 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 206         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 207         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 208 };
 209
 210 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 211         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 212         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 213         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 214         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 215         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 216         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 217         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 218         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 219         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 220         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 221 };
 222
 223 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 224         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 225         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 226         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 227
 228         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 229
 230         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 231         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 232         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 233         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 234         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 235 };
 236
 237 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 238         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 239         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 240         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 241         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 242         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 243         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 244         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 245         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 247         /* PLL and Loop filter settings */
 248         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 263         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 264         /* SSC settings */
 265         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 272 };
 273
 274 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 275         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 276         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 277         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 278 };
 279
 280 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 281         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 282         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 283         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 284         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 285         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 286         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 287         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 288         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 289         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 290         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 291 };
 292
 293 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 294         /* FLL settings */
 295         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 296         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 297         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 298         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 299         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 300
 301         /* Lock Det settings */
 302         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 303         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 304         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 305         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 306 };
 307
 308 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 309         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 338         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 349 };
 350
 351 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 352         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 353         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 354         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 355         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 356         QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 357         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 358 };
 359
 360 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 361         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 362         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 363         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 364         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 365         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 366         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 367         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 368 };
 369
 370 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 371         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 372         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 373         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 374         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 375         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 376         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 377         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 378         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 379         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 380         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 381         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 382         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 383         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 384 };
 385
 386 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 414         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 419         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 420         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 421         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 423 };
 424
 425 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 426         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 431 };
 432
 433 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 443 };
 444
 445 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 446         /* FLL settings */
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 452
 453         /* Lock Det settings */
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 458
 459         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 461         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 462         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 463         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 465         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 466         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 467         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 468         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 469         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 470         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 471         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 472         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 473         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 474         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 475         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 476         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 478
 479         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 480         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 481         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 482         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 483         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 484         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 485         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 486         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 487         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 488         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 489         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 490 };
 491
 492 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 493         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 494         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 495         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 496         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 497         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 498         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 499         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 500         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 501         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 514         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 515         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 516         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 517         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 518         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 529 };
 530
 531 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 532         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 534         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 535         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 536         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 537 };
 538
 539 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 540         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 541         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 542         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 546         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 547         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 548         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 549         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 550         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 551 };
 552
 553 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 554         /* FLL settings */
 555         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 556         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 557         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 558         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 559         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 560
 561         /* Lock Det settings */
 562         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 563         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 566
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 569         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 570         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 575         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 581         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 582         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 583         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 584         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 585         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 586
 587         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 588         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 589         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 591         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 595         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 597         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 598
 599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 600         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 601 };
 602
 603
 604 /* struct qmp_phy_cfg - per-PHY initialization config */
 605 struct qmp_phy_cfg {
 606         /* phy-type - PCIE/UFS/USB */
 607         unsigned int type;
 608         /* number of lanes provided by phy */
 609         int nlanes;
 610
 611         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 612         const struct qmp_phy_init_tbl *serdes_tbl;
 613         int serdes_tbl_num;
 614         const struct qmp_phy_init_tbl *tx_tbl;
 615         int tx_tbl_num;
 616         const struct qmp_phy_init_tbl *rx_tbl;
 617         int rx_tbl_num;
 618         const struct qmp_phy_init_tbl *pcs_tbl;
 619         int pcs_tbl_num;
 620
 621         /* clock ids to be requested */
 622         const char * const *clk_list;
 623         int num_clks;
 624         /* resets to be requested */
 625         const char * const *reset_list;
 626         int num_resets;
 627         /* regulators to be requested */
 628         const char * const *vreg_list;
 629         int num_vregs;
 630
 631         /* array of registers with different offsets */
 632         const unsigned int *regs;
 633
 634         unsigned int start_ctrl;
 635         unsigned int pwrdn_ctrl;
 636         unsigned int mask_pcs_ready;
 637         unsigned int mask_com_pcs_ready;
 638
 639         /* true, if PHY has a separate PHY_COM control block */
 640         bool has_phy_com_ctrl;
 641         /* true, if PHY has a reset for individual lanes */
 642         bool has_lane_rst;
 643         /* true, if PHY needs delay after POWER_DOWN */
 644         bool has_pwrdn_delay;
 645         /* power_down delay in usec */
 646         int pwrdn_delay_min;
 647         int pwrdn_delay_max;
 648
 649         /* true, if PHY has a separate DP_COM control block */
 650         bool has_phy_dp_com_ctrl;
 651         /* Register offset of secondary tx/rx lanes for USB DP combo PHY */
 652         unsigned int tx_b_lane_offset;
 653         unsigned int rx_b_lane_offset;
 654 };
 655
 656 /**
 657  * struct qmp_phy - per-lane phy descriptor
 658  *
 659  * @phy: generic phy
 660  * @tx: iomapped memory space for lane's tx
 661  * @rx: iomapped memory space for lane's rx
 662  * @pcs: iomapped memory space for lane's pcs
 663  * @pcs_misc: iomapped memory space for lane's pcs_misc
 664  * @pipe_clk: pipe lock
 665  * @index: lane index
 666  * @qmp: QMP phy to which this lane belongs
 667  * @lane_rst: lane's reset controller
 668  */
 669 struct qmp_phy {
 670         struct phy *phy;
 671         void __iomem *tx;
 672         void __iomem *rx;
 673         void __iomem *pcs;
 674         void __iomem *pcs_misc;
 675         struct clk *pipe_clk;
 676         unsigned int index;
 677         struct qcom_qmp *qmp;
 678         struct reset_control *lane_rst;
 679 };
 680
 681 /**
 682  * struct qcom_qmp - structure holding QMP phy block attributes
 683  *
 684  * @dev: device
 685  * @serdes: iomapped memory space for phy's serdes
 686  * @dp_com: iomapped memory space for phy's dp_com control block
 687  *
 688  * @clks: array of clocks required by phy
 689  * @resets: array of resets required by phy
 690  * @vregs: regulator supplies bulk data
 691  *
 692  * @cfg: phy specific configuration
 693  * @phys: array of per-lane phy descriptors
 694  * @phy_mutex: mutex lock for PHY common block initialization
 695  * @init_count: phy common block initialization count
 696  * @phy_initialized: indicate if PHY has been initialized
 697  * @mode: current PHY mode
 698  */
 699 struct qcom_qmp {
 700         struct device *dev;
 701         void __iomem *serdes;
 702         void __iomem *dp_com;
 703
 704         struct clk_bulk_data *clks;
 705         struct reset_control **resets;
 706         struct regulator_bulk_data *vregs;
 707
 708         const struct qmp_phy_cfg *cfg;
 709         struct qmp_phy **phys;
 710
 711         struct mutex phy_mutex;
 712         int init_count;
 713         bool phy_initialized;
 714         enum phy_mode mode;
 715 };
 716
 717 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 718 {
 719         u32 reg;
 720
 721         reg = readl(base + offset);
 722         reg |= val;
 723         writel(reg, base + offset);
 724
 725         /* ensure that above write is through */
 726         readl(base + offset);
 727 }
 728
 729 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 730 {
 731         u32 reg;
 732
 733         reg = readl(base + offset);
 734         reg &= ~val;
 735         writel(reg, base + offset);
 736
 737         /* ensure that above write is through */
 738         readl(base + offset);
 739 }
 740
 741 /* list of clocks required by phy */
 742 static const char * const msm8996_phy_clk_l[] = {
 743         "aux", "cfg_ahb", "ref",
 744 };
 745
 746 static const char * const qmp_v3_phy_clk_l[] = {
 747         "aux", "cfg_ahb", "ref", "com_aux",
 748 };
 749
 750 /* list of resets */
 751 static const char * const msm8996_pciephy_reset_l[] = {
 752         "phy", "common", "cfg",
 753 };
 754
 755 static const char * const msm8996_usb3phy_reset_l[] = {
 756         "phy", "common",
 757 };
 758
 759 /* list of regulators */
 760 static const char * const msm8996_phy_vreg_l[] = {
 761         "vdda-phy", "vdda-pll",
 762 };
 763
 764 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
 765         .type                   = PHY_TYPE_PCIE,
 766         .nlanes                 = 3,
 767
 768         .serdes_tbl             = msm8996_pcie_serdes_tbl,
 769         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
 770         .tx_tbl                 = msm8996_pcie_tx_tbl,
 771         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
 772         .rx_tbl                 = msm8996_pcie_rx_tbl,
 773         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
 774         .pcs_tbl                = msm8996_pcie_pcs_tbl,
 775         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
 776         .clk_list               = msm8996_phy_clk_l,
 777         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 778         .reset_list             = msm8996_pciephy_reset_l,
 779         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
 780         .vreg_list              = msm8996_phy_vreg_l,
 781         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 782         .regs                   = pciephy_regs_layout,
 783
 784         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
 785         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 786         .mask_com_pcs_ready     = PCS_READY,
 787
 788         .has_phy_com_ctrl       = true,
 789         .has_lane_rst           = true,
 790         .has_pwrdn_delay        = true,
 791         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 792         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 793 };
 794
 795 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 796         .type                   = PHY_TYPE_USB3,
 797         .nlanes                 = 1,
 798
 799         .serdes_tbl             = msm8996_usb3_serdes_tbl,
 800         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
 801         .tx_tbl                 = msm8996_usb3_tx_tbl,
 802         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
 803         .rx_tbl                 = msm8996_usb3_rx_tbl,
 804         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
 805         .pcs_tbl                = msm8996_usb3_pcs_tbl,
 806         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
 807         .clk_list               = msm8996_phy_clk_l,
 808         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 809         .reset_list             = msm8996_usb3phy_reset_l,
 810         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 811         .vreg_list              = msm8996_phy_vreg_l,
 812         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 813         .regs                   = usb3phy_regs_layout,
 814
 815         .start_ctrl             = SERDES_START | PCS_START,
 816         .pwrdn_ctrl             = SW_PWRDN,
 817         .mask_pcs_ready         = PHYSTATUS,
 818 };
 819
 820 static const char * const ipq8074_pciephy_clk_l[] = {
 821         "aux", "cfg_ahb",
 822 };
 823 /* list of resets */
 824 static const char * const ipq8074_pciephy_reset_l[] = {
 825         "phy", "common",
 826 };
 827
 828 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 829         .type                   = PHY_TYPE_PCIE,
 830         .nlanes                 = 1,
 831
 832         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
 833         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
 834         .tx_tbl                 = ipq8074_pcie_tx_tbl,
 835         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
 836         .rx_tbl                 = ipq8074_pcie_rx_tbl,
 837         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
 838         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
 839         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
 840         .clk_list               = ipq8074_pciephy_clk_l,
 841         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
 842         .reset_list             = ipq8074_pciephy_reset_l,
 843         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
 844         .vreg_list              = NULL,
 845         .num_vregs              = 0,
 846         .regs                   = pciephy_regs_layout,
 847
 848         .start_ctrl             = SERDES_START | PCS_START,
 849         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 850         .mask_pcs_ready         = PHYSTATUS,
 851
 852         .has_phy_com_ctrl       = false,
 853         .has_lane_rst           = false,
 854         .has_pwrdn_delay        = true,
 855         .pwrdn_delay_min        = 995,          /* us */
 856         .pwrdn_delay_max        = 1005,         /* us */
 857 };
 858
 859 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
 860         .type                   = PHY_TYPE_USB3,
 861         .nlanes                 = 1,
 862
 863         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
 864         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
 865         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
 866         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
 867         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
 868         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
 869         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
 870         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
 871         .clk_list               = qmp_v3_phy_clk_l,
 872         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
 873         .reset_list             = msm8996_usb3phy_reset_l,
 874         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 875         .vreg_list              = msm8996_phy_vreg_l,
 876         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 877         .regs                   = qmp_v3_usb3phy_regs_layout,
 878
 879         .start_ctrl             = SERDES_START | PCS_START,
 880         .pwrdn_ctrl             = SW_PWRDN,
 881         .mask_pcs_ready         = PHYSTATUS,
 882
 883         .has_pwrdn_delay        = true,
 884         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 885         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 886
 887         .has_phy_dp_com_ctrl    = true,
 888         .tx_b_lane_offset       = 0x400,
 889         .rx_b_lane_offset       = 0x400,
 890 };
 891
 892 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
 893         .type                   = PHY_TYPE_USB3,
 894         .nlanes                 = 1,
 895
 896         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
 897         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
 898         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
 899         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
 900         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
 901         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
 902         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
 903         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
 904         .clk_list               = qmp_v3_phy_clk_l,
 905         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
 906         .reset_list             = msm8996_usb3phy_reset_l,
 907         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 908         .vreg_list              = msm8996_phy_vreg_l,
 909         .num_vregs              = ARRAY_SIZE(msm8996_phy_vreg_l),
 910         .regs                   = qmp_v3_usb3phy_regs_layout,
 911
 912         .start_ctrl             = SERDES_START | PCS_START,
 913         .pwrdn_ctrl             = SW_PWRDN,
 914         .mask_pcs_ready         = PHYSTATUS,
 915
 916         .has_pwrdn_delay        = true,
 917         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 918         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 919 };
 920
 921 static void qcom_qmp_phy_configure(void __iomem *base,
 922                                    const unsigned int *regs,
 923                                    const struct qmp_phy_init_tbl tbl[],
 924                                    int num)
 925 {
 926         int i;
 927         const struct qmp_phy_init_tbl *t = tbl;
 928
 929         if (!t)
 930                 return;
 931
 932         for (i = 0; i < num; i++, t++) {
 933                 if (t->in_layout)
 934                         writel(t->val, base + regs[t->offset]);
 935                 else
 936                         writel(t->val, base + t->offset);
 937         }
 938 }
 939
 940 static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
 941 {
 942         const struct qmp_phy_cfg *cfg = qmp->cfg;
 943         void __iomem *serdes = qmp->serdes;
 944         void __iomem *dp_com = qmp->dp_com;
 945         int ret, i;
 946
 947         mutex_lock(&qmp->phy_mutex);
 948         if (qmp->init_count++) {
 949                 mutex_unlock(&qmp->phy_mutex);
 950                 return 0;
 951         }
 952
 953         /* turn on regulator supplies */
 954         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
 955         if (ret) {
 956                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
 957                 goto err_reg_enable;
 958         }
 959
 960         for (i = 0; i < cfg->num_resets; i++) {
 961                 ret = reset_control_assert(qmp->resets[i]);
 962                 if (ret) {
 963                         dev_err(qmp->dev, "%s reset assert failed\n",
 964                                 cfg->reset_list[i]);
 965                         goto err_rst_assert;
 966                 }
 967         }
 968
 969         for (i = cfg->num_resets - 1; i >= 0; i--) {
 970                 ret = reset_control_deassert(qmp->resets[i]);
 971                 if (ret) {
 972                         dev_err(qmp->dev, "%s reset deassert failed\n",
 973                                 qmp->cfg->reset_list[i]);
 974                         goto err_rst;
 975                 }
 976         }
 977
 978         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
 979         if (ret) {
 980                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
 981                 goto err_rst;
 982         }
 983
 984         if (cfg->has_phy_com_ctrl)
 985                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
 986                              SW_PWRDN);
 987
 988         if (cfg->has_phy_dp_com_ctrl) {
 989                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
 990                              SW_PWRDN);
 991                 /* override hardware control for reset of qmp phy */
 992                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
 993                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
 994                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
 995
 996                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
 997                              USB3_MODE | DP_MODE);
 998
 999                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1000                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1001                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1002                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1003         }
1004
1005         /* Serdes configuration */
1006         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1007                                cfg->serdes_tbl_num);
1008
1009         if (cfg->has_phy_com_ctrl) {
1010                 void __iomem *status;
1011                 unsigned int mask, val;
1012
1013                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1014                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1015                              SERDES_START | PCS_START);
1016
1017                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1018                 mask = cfg->mask_com_pcs_ready;
1019
1020                 ret = readl_poll_timeout(status, val, (val & mask), 10,
1021                                          PHY_INIT_COMPLETE_TIMEOUT);
1022                 if (ret) {
1023                         dev_err(qmp->dev,
1024                                 "phy common block init timed-out\n");
1025                         goto err_com_init;
1026                 }
1027         }
1028
1029         mutex_unlock(&qmp->phy_mutex);
1030
1031         return 0;
1032
1033 err_com_init:
1034         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1035 err_rst:
1036         while (++i < cfg->num_resets)
1037                 reset_control_assert(qmp->resets[i]);
1038 err_rst_assert:
1039         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1040 err_reg_enable:
1041         mutex_unlock(&qmp->phy_mutex);
1042
1043         return ret;
1044 }
1045
1046 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1047 {
1048         const struct qmp_phy_cfg *cfg = qmp->cfg;
1049         void __iomem *serdes = qmp->serdes;
1050         int i = cfg->num_resets;
1051
1052         mutex_lock(&qmp->phy_mutex);
1053         if (--qmp->init_count) {
1054                 mutex_unlock(&qmp->phy_mutex);
1055                 return 0;
1056         }
1057
1058         if (cfg->has_phy_com_ctrl) {
1059                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1060                              SERDES_START | PCS_START);
1061                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1062                              SW_RESET);
1063                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1064                              SW_PWRDN);
1065         }
1066
1067         while (--i >= 0)
1068                 reset_control_assert(qmp->resets[i]);
1069
1070         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1071
1072         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1073
1074         mutex_unlock(&qmp->phy_mutex);
1075
1076         return 0;
1077 }
1078
1079 /* PHY Initialization */
1080 static int qcom_qmp_phy_init(struct phy *phy)
1081 {
1082         struct qmp_phy *qphy = phy_get_drvdata(phy);
1083         struct qcom_qmp *qmp = qphy->qmp;
1084         const struct qmp_phy_cfg *cfg = qmp->cfg;
1085         void __iomem *tx = qphy->tx;
1086         void __iomem *rx = qphy->rx;
1087         void __iomem *pcs = qphy->pcs;
1088         void __iomem *dp_com = qmp->dp_com;
1089         void __iomem *status;
1090         unsigned int mask, val;
1091         int ret;
1092
1093         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1094
1095         ret = qcom_qmp_phy_com_init(qmp);
1096         if (ret)
1097                 return ret;
1098
1099         if (cfg->has_lane_rst) {
1100                 ret = reset_control_deassert(qphy->lane_rst);
1101                 if (ret) {
1102                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
1103                                 qphy->index);
1104                         goto err_lane_rst;
1105                 }
1106         }
1107
1108         ret = clk_prepare_enable(qphy->pipe_clk);
1109         if (ret) {
1110                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1111                 goto err_clk_enable;
1112         }
1113
1114         /* Tx, Rx, and PCS configurations */
1115         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1116         /* Configuration for other LANE for USB-DP combo PHY */
1117         if (cfg->has_phy_dp_com_ctrl)
1118                 qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,
1119                                        cfg->tx_tbl, cfg->tx_tbl_num);
1120
1121         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1122         if (cfg->has_phy_dp_com_ctrl)
1123                 qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,
1124                                        cfg->rx_tbl, cfg->rx_tbl_num);
1125
1126         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1127
1128         /*
1129          * Pull out PHY from POWER DOWN state.
1130          * This is active low enable signal to power-down PHY.
1131          */
1132         qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1133
1134         if (cfg->has_pwrdn_delay)
1135                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1136
1137         /* Pull PHY out of reset state */
1138         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1139         if (cfg->has_phy_dp_com_ctrl)
1140                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1141
1142         /* start SerDes and Phy-Coding-Sublayer */
1143         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1144
1145         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1146         mask = cfg->mask_pcs_ready;
1147
1148         ret = readl_poll_timeout(status, val, !(val & mask), 1,
1149                                  PHY_INIT_COMPLETE_TIMEOUT);
1150         if (ret) {
1151                 dev_err(qmp->dev, "phy initialization timed-out\n");
1152                 goto err_pcs_ready;
1153         }
1154         qmp->phy_initialized = true;
1155
1156         return ret;
1157
1158 err_pcs_ready:
1159         clk_disable_unprepare(qphy->pipe_clk);
1160 err_clk_enable:
1161         if (cfg->has_lane_rst)
1162                 reset_control_assert(qphy->lane_rst);
1163 err_lane_rst:
1164         qcom_qmp_phy_com_exit(qmp);
1165
1166         return ret;
1167 }
1168
1169 static int qcom_qmp_phy_exit(struct phy *phy)
1170 {
1171         struct qmp_phy *qphy = phy_get_drvdata(phy);
1172         struct qcom_qmp *qmp = qphy->qmp;
1173         const struct qmp_phy_cfg *cfg = qmp->cfg;
1174
1175         clk_disable_unprepare(qphy->pipe_clk);
1176
1177         /* PHY reset */
1178         qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1179
1180         /* stop SerDes and Phy-Coding-Sublayer */
1181         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1182
1183         /* Put PHY into POWER DOWN state: active low */
1184         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1185
1186         if (cfg->has_lane_rst)
1187                 reset_control_assert(qphy->lane_rst);
1188
1189         qcom_qmp_phy_com_exit(qmp);
1190
1191         qmp->phy_initialized = false;
1192
1193         return 0;
1194 }
1195
1196 static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode)
1197 {
1198         struct qmp_phy *qphy = phy_get_drvdata(phy);
1199         struct qcom_qmp *qmp = qphy->qmp;
1200
1201         qmp->mode = mode;
1202
1203         return 0;
1204 }
1205
1206 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1207 {
1208         struct qcom_qmp *qmp = qphy->qmp;
1209         const struct qmp_phy_cfg *cfg = qmp->cfg;
1210         void __iomem *pcs = qphy->pcs;
1211         void __iomem *pcs_misc = qphy->pcs_misc;
1212         u32 intr_mask;
1213
1214         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1215             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1216                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1217         else
1218                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1219
1220         /* Clear any pending interrupts status */
1221         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1222         /* Writing 1 followed by 0 clears the interrupt */
1223         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1224
1225         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1226                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1227
1228         /* Enable required PHY autonomous mode interrupts */
1229         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1230
1231         /* Enable i/o clamp_n for autonomous mode */
1232         if (pcs_misc)
1233                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1234 }
1235
1236 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1237 {
1238         struct qcom_qmp *qmp = qphy->qmp;
1239         const struct qmp_phy_cfg *cfg = qmp->cfg;
1240         void __iomem *pcs = qphy->pcs;
1241         void __iomem *pcs_misc = qphy->pcs_misc;
1242
1243         /* Disable i/o clamp_n on resume for normal mode */
1244         if (pcs_misc)
1245                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1246
1247         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1248                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1249
1250         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1251         /* Writing 1 followed by 0 clears the interrupt */
1252         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1253 }
1254
1255 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1256 {
1257         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1258         struct qmp_phy *qphy = qmp->phys[0];
1259         const struct qmp_phy_cfg *cfg = qmp->cfg;
1260
1261         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1262
1263         /* Supported only for USB3 PHY */
1264         if (cfg->type != PHY_TYPE_USB3)
1265                 return 0;
1266
1267         if (!qmp->phy_initialized) {
1268                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1269                 return 0;
1270         }
1271
1272         qcom_qmp_phy_enable_autonomous_mode(qphy);
1273
1274         clk_disable_unprepare(qphy->pipe_clk);
1275         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1276
1277         return 0;
1278 }
1279
1280 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1281 {
1282         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1283         struct qmp_phy *qphy = qmp->phys[0];
1284         const struct qmp_phy_cfg *cfg = qmp->cfg;
1285         int ret = 0;
1286
1287         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1288
1289         /* Supported only for USB3 PHY */
1290         if (cfg->type != PHY_TYPE_USB3)
1291                 return 0;
1292
1293         if (!qmp->phy_initialized) {
1294                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1295                 return 0;
1296         }
1297
1298         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1299         if (ret) {
1300                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1301                 return ret;
1302         }
1303
1304         ret = clk_prepare_enable(qphy->pipe_clk);
1305         if (ret) {
1306                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1307                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1308                 return ret;
1309         }
1310
1311         qcom_qmp_phy_disable_autonomous_mode(qphy);
1312
1313         return 0;
1314 }
1315
1316 static int qcom_qmp_phy_vreg_init(struct device *dev)
1317 {
1318         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1319         int num = qmp->cfg->num_vregs;
1320         int i;
1321
1322         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1323         if (!qmp->vregs)
1324                 return -ENOMEM;
1325
1326         for (i = 0; i < num; i++)
1327                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1328
1329         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1330 }
1331
1332 static int qcom_qmp_phy_reset_init(struct device *dev)
1333 {
1334         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1335         int i;
1336
1337         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1338                                    sizeof(*qmp->resets), GFP_KERNEL);
1339         if (!qmp->resets)
1340                 return -ENOMEM;
1341
1342         for (i = 0; i < qmp->cfg->num_resets; i++) {
1343                 struct reset_control *rst;
1344                 const char *name = qmp->cfg->reset_list[i];
1345
1346                 rst = devm_reset_control_get(dev, name);
1347                 if (IS_ERR(rst)) {
1348                         dev_err(dev, "failed to get %s reset\n", name);
1349                         return PTR_ERR(rst);
1350                 }
1351                 qmp->resets[i] = rst;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int qcom_qmp_phy_clk_init(struct device *dev)
1358 {
1359         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1360         int num = qmp->cfg->num_clks;
1361         int i;
1362
1363         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1364         if (!qmp->clks)
1365                 return -ENOMEM;
1366
1367         for (i = 0; i < num; i++)
1368                 qmp->clks[i].id = qmp->cfg->clk_list[i];
1369
1370         return devm_clk_bulk_get(dev, num, qmp->clks);
1371 }
1372
1373 /*
1374  * Register a fixed rate pipe clock.
1375  *
1376  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1377  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1378  * by the PHY driver for its operations.
1379  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1380  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1381  * Below picture shows this relationship.
1382  *
1383  *         +---------------+
1384  *         |   PHY block   |<<---------------------------------------+
1385  *         |               |                                         |
1386  *         |   +-------+   |                   +-----+               |
1387  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1388  *    clk  |   +-------+   |                   +-----+
1389  *         +---------------+
1390  */
1391 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1392 {
1393         struct clk_fixed_rate *fixed;
1394         struct clk_init_data init = { };
1395         int ret;
1396
1397         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1398             (qmp->cfg->type != PHY_TYPE_PCIE)) {
1399                 /* not all phys register pipe clocks, so return success */
1400                 return 0;
1401         }
1402
1403         ret = of_property_read_string(np, "clock-output-names", &init.name);
1404         if (ret) {
1405                 dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
1406                 return ret;
1407         }
1408
1409         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1410         if (!fixed)
1411                 return -ENOMEM;
1412
1413         init.ops = &clk_fixed_rate_ops;
1414
1415         /* controllers using QMP phys use 125MHz pipe clock interface */
1416         fixed->fixed_rate = 125000000;
1417         fixed->hw.init = &init;
1418
1419         return devm_clk_hw_register(qmp->dev, &fixed->hw);
1420 }
1421
1422 static const struct phy_ops qcom_qmp_phy_gen_ops = {
1423         .init           = qcom_qmp_phy_init,
1424         .exit           = qcom_qmp_phy_exit,
1425         .set_mode       = qcom_qmp_phy_set_mode,
1426         .owner          = THIS_MODULE,
1427 };
1428
1429 static void qcom_qmp_reset_control_put(void *data)
1430 {
1431         reset_control_put(data);
1432 }
1433
1434 static
1435 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1436 {
1437         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1438         struct phy *generic_phy;
1439         struct qmp_phy *qphy;
1440         char prop_name[MAX_PROP_NAME];
1441         int ret;
1442
1443         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1444         if (!qphy)
1445                 return -ENOMEM;
1446
1447         /*
1448          * Get memory resources for each phy lane:
1449          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and
1450          * pcs_misc (optional) -> 3.
1451          */
1452         qphy->tx = of_iomap(np, 0);
1453         if (!qphy->tx)
1454                 return -ENOMEM;
1455
1456         qphy->rx = of_iomap(np, 1);
1457         if (!qphy->rx)
1458                 return -ENOMEM;
1459
1460         qphy->pcs = of_iomap(np, 2);
1461         if (!qphy->pcs)
1462                 return -ENOMEM;
1463
1464         qphy->pcs_misc = of_iomap(np, 3);
1465         if (!qphy->pcs_misc)
1466                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1467
1468         /*
1469          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1470          * based phys, so they essentially have pipe clock. So,
1471          * we return error in case phy is USB3 or PIPE type.
1472          * Otherwise, we initialize pipe clock to NULL for
1473          * all phys that don't need this.
1474          */
1475         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1476         qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
1477         if (IS_ERR(qphy->pipe_clk)) {
1478                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1479                     qmp->cfg->type == PHY_TYPE_USB3) {
1480                         ret = PTR_ERR(qphy->pipe_clk);
1481                         if (ret != -EPROBE_DEFER)
1482                                 dev_err(dev,
1483                                         "failed to get lane%d pipe_clk, %d\n",
1484                                         id, ret);
1485                         return ret;
1486                 }
1487                 qphy->pipe_clk = NULL;
1488         }
1489
1490         /* Get lane reset, if any */
1491         if (qmp->cfg->has_lane_rst) {
1492                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1493                 qphy->lane_rst = of_reset_control_get(np, prop_name);
1494                 if (IS_ERR(qphy->lane_rst)) {
1495                         dev_err(dev, "failed to get lane%d reset\n", id);
1496                         return PTR_ERR(qphy->lane_rst);
1497                 }
1498                 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
1499                                                qphy->lane_rst);
1500                 if (ret)
1501                         return ret;
1502         }
1503
1504         generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
1505         if (IS_ERR(generic_phy)) {
1506                 ret = PTR_ERR(generic_phy);
1507                 dev_err(dev, "failed to create qphy %d\n", ret);
1508                 return ret;
1509         }
1510
1511         qphy->phy = generic_phy;
1512         qphy->index = id;
1513         qphy->qmp = qmp;
1514         qmp->phys[id] = qphy;
1515         phy_set_drvdata(generic_phy, qphy);
1516
1517         return 0;
1518 }
1519
1520 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1521         {
1522                 .compatible = "qcom,msm8996-qmp-pcie-phy",
1523                 .data = &msm8996_pciephy_cfg,
1524         }, {
1525                 .compatible = "qcom,msm8996-qmp-usb3-phy",
1526                 .data = &msm8996_usb3phy_cfg,
1527         }, {
1528                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1529                 .data = &ipq8074_pciephy_cfg,
1530         }, {
1531                 .compatible = "qcom,sdm845-qmp-usb3-phy",
1532                 .data = &qmp_v3_usb3phy_cfg,
1533         }, {
1534                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
1535                 .data = &qmp_v3_usb3_uniphy_cfg,
1536         },
1537         { },
1538 };
1539 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
1540
1541 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
1542         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
1543                            qcom_qmp_phy_runtime_resume, NULL)
1544 };
1545
1546 static int qcom_qmp_phy_probe(struct platform_device *pdev)
1547 {
1548         struct qcom_qmp *qmp;
1549         struct device *dev = &pdev->dev;
1550         struct resource *res;
1551         struct device_node *child;
1552         struct phy_provider *phy_provider;
1553         void __iomem *base;
1554         int num, id;
1555         int ret;
1556
1557         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1558         if (!qmp)
1559                 return -ENOMEM;
1560
1561         qmp->dev = dev;
1562         dev_set_drvdata(dev, qmp);
1563
1564         /* Get the specific init parameters of QMP phy */
1565         qmp->cfg = of_device_get_match_data(dev);
1566         if (!qmp->cfg)
1567                 return -EINVAL;
1568
1569         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1570         base = devm_ioremap_resource(dev, res);
1571         if (IS_ERR(base))
1572                 return PTR_ERR(base);
1573
1574         /* per PHY serdes; usually located at base address */
1575         qmp->serdes = base;
1576
1577         /* per PHY dp_com; if PHY has dp_com control block */
1578         if (qmp->cfg->has_phy_dp_com_ctrl) {
1579                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1580                                                    "dp_com");
1581                 base = devm_ioremap_resource(dev, res);
1582                 if (IS_ERR(base))
1583                         return PTR_ERR(base);
1584
1585                 qmp->dp_com = base;
1586         }
1587
1588         mutex_init(&qmp->phy_mutex);
1589
1590         ret = qcom_qmp_phy_clk_init(dev);
1591         if (ret)
1592                 return ret;
1593
1594         ret = qcom_qmp_phy_reset_init(dev);
1595         if (ret)
1596                 return ret;
1597
1598         ret = qcom_qmp_phy_vreg_init(dev);
1599         if (ret) {
1600                 dev_err(dev, "failed to get regulator supplies\n");
1601                 return ret;
1602         }
1603
1604         num = of_get_available_child_count(dev->of_node);
1605         /* do we have a rogue child node ? */
1606         if (num > qmp->cfg->nlanes)
1607                 return -EINVAL;
1608
1609         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
1610         if (!qmp->phys)
1611                 return -ENOMEM;
1612
1613         id = 0;
1614         pm_runtime_set_active(dev);
1615         pm_runtime_enable(dev);
1616         /*
1617          * Prevent runtime pm from being ON by default. Users can enable
1618          * it using power/control in sysfs.
1619          */
1620         pm_runtime_forbid(dev);
1621
1622         for_each_available_child_of_node(dev->of_node, child) {
1623                 /* Create per-lane phy */
1624                 ret = qcom_qmp_phy_create(dev, child, id);
1625                 if (ret) {
1626                         dev_err(dev, "failed to create lane%d phy, %d\n",
1627                                 id, ret);
1628                         pm_runtime_disable(dev);
1629                         return ret;
1630                 }
1631
1632                 /*
1633                  * Register the pipe clock provided by phy.
1634                  * See function description to see details of this pipe clock.
1635                  */
1636                 ret = phy_pipe_clk_register(qmp, child);
1637                 if (ret) {
1638                         dev_err(qmp->dev,
1639                                 "failed to register pipe clock source\n");
1640                         pm_runtime_disable(dev);
1641                         return ret;
1642                 }
1643                 id++;
1644         }
1645
1646         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1647         if (!IS_ERR(phy_provider))
1648                 dev_info(dev, "Registered Qcom-QMP phy\n");
1649         else
1650                 pm_runtime_disable(dev);
1651
1652         return PTR_ERR_OR_ZERO(phy_provider);
1653 }
1654
1655 static struct platform_driver qcom_qmp_phy_driver = {
1656         .probe          = qcom_qmp_phy_probe,
1657         .driver = {
1658                 .name   = "qcom-qmp-phy",
1659                 .pm     = &qcom_qmp_phy_pm_ops,
1660                 .of_match_table = qcom_qmp_phy_of_match_table,
1661         },
1662 };
1663
1664 module_platform_driver(qcom_qmp_phy_driver);
1665
1666 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1667 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
1668 MODULE_LICENSE("GPL v2");