drivers/phy/qualcomm/phy-qcom-qusb2.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/nvmem-consumer.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/phy/phy.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/reset.h>
  29 #include <linux/slab.h>
  30
  31 #define QUSB2PHY_PLL_TEST               0x04
  32 #define CLK_REF_SEL                     BIT(7)
  33
  34 #define QUSB2PHY_PLL_TUNE               0x08
  35 #define QUSB2PHY_PLL_USER_CTL1          0x0c
  36 #define QUSB2PHY_PLL_USER_CTL2          0x10
  37 #define QUSB2PHY_PLL_AUTOPGM_CTL1       0x1c
  38 #define QUSB2PHY_PLL_PWR_CTRL           0x18
  39
  40 #define QUSB2PHY_PLL_STATUS             0x38
  41 #define PLL_LOCKED                      BIT(5)
  42
  43 #define QUSB2PHY_PORT_TUNE1             0x80
  44 #define QUSB2PHY_PORT_TUNE2             0x84
  45 #define QUSB2PHY_PORT_TUNE3             0x88
  46 #define QUSB2PHY_PORT_TUNE4             0x8c
  47 #define QUSB2PHY_PORT_TUNE5             0x90
  48 #define QUSB2PHY_PORT_TEST2             0x9c
  49
  50 #define QUSB2PHY_PORT_POWERDOWN         0xb4
  51 #define CLAMP_N_EN                      BIT(5)
  52 #define FREEZIO_N                       BIT(1)
  53 #define POWER_DOWN                      BIT(0)
  54
  55 #define QUSB2PHY_REFCLK_ENABLE          BIT(0)
  56
  57 #define PHY_CLK_SCHEME_SEL              BIT(0)
  58
  59 struct qusb2_phy_init_tbl {
  60         unsigned int offset;
  61         unsigned int val;
  62 };
  63
  64 #define QUSB2_PHY_INIT_CFG(o, v) \
  65         {                       \
  66                 .offset = o,    \
  67                 .val = v,       \
  68         }
  69
  70 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
  71         QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE1, 0xf8),
  72         QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE2, 0xb3),
  73         QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE3, 0x83),
  74         QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE4, 0xc0),
  75         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
  76         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
  77         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
  78         QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TEST2, 0x14),
  79         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
  80         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
  81 };
  82
  83 struct qusb2_phy_cfg {
  84         const struct qusb2_phy_init_tbl *tbl;
  85         /* number of entries in the table */
  86         unsigned int tbl_num;
  87         /* offset to PHY_CLK_SCHEME register in TCSR map */
  88         unsigned int clk_scheme_offset;
  89 };
  90
  91 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
  92         .tbl = msm8996_init_tbl,
  93         .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
  94 };
  95
  96 static const char * const qusb2_phy_vreg_names[] = {
  97         "vdda-pll", "vdda-phy-dpdm",
  98 };
  99
 100 #define QUSB2_NUM_VREGS         ARRAY_SIZE(qusb2_phy_vreg_names)
 101
 102 /**
 103  * struct qusb2_phy - structure holding qusb2 phy attributes
 104  *
 105  * @phy: generic phy
 106  * @base: iomapped memory space for qubs2 phy
 107  *
 108  * @cfg_ahb_clk: AHB2PHY interface clock
 109  * @ref_clk: phy reference clock
 110  * @iface_clk: phy interface clock
 111  * @phy_reset: phy reset control
 112  * @vregs: regulator supplies bulk data
 113  *
 114  * @tcsr: TCSR syscon register map
 115  * @cell: nvmem cell containing phy tuning value
 116  *
 117  * @cfg: phy config data
 118  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
 119  */
 120 struct qusb2_phy {
 121         struct phy *phy;
 122         void __iomem *base;
 123
 124         struct clk *cfg_ahb_clk;
 125         struct clk *ref_clk;
 126         struct clk *iface_clk;
 127         struct reset_control *phy_reset;
 128         struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
 129
 130         struct regmap *tcsr;
 131         struct nvmem_cell *cell;
 132
 133         const struct qusb2_phy_cfg *cfg;
 134         bool has_se_clk_scheme;
 135 };
 136
 137 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
 138 {
 139         u32 reg;
 140
 141         reg = readl(base + offset);
 142         reg |= val;
 143         writel(reg, base + offset);
 144
 145         /* Ensure above write is completed */
 146         readl(base + offset);
 147 }
 148
 149 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
 150 {
 151         u32 reg;
 152
 153         reg = readl(base + offset);
 154         reg &= ~val;
 155         writel(reg, base + offset);
 156
 157         /* Ensure above write is completed */
 158         readl(base + offset);
 159 }
 160
 161 static inline
 162 void qcom_qusb2_phy_configure(void __iomem *base,
 163                               const struct qusb2_phy_init_tbl tbl[], int num)
 164 {
 165         int i;
 166
 167         for (i = 0; i < num; i++)
 168                 writel(tbl[i].val, base + tbl[i].offset);
 169 }
 170
 171 /*
 172  * Fetches HS Tx tuning value from nvmem and sets the
 173  * QUSB2PHY_PORT_TUNE2 register.
 174  * For error case, skip setting the value and use the default value.
 175  */
 176 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
 177 {
 178         struct device *dev = &qphy->phy->dev;
 179         u8 *val;
 180
 181         /* efuse register is optional */
 182         if (!qphy->cell)
 183                 return;
 184
 185         /*
 186          * Read efuse register having TUNE2 parameter's high nibble.
 187          * If efuse register shows value as 0x0, or if we fail to find
 188          * a valid efuse register settings, then use default value
 189          * as 0xB for high nibble that we have already set while
 190          * configuring phy.
 191          */
 192         val = nvmem_cell_read(qphy->cell, NULL);
 193         if (IS_ERR(val) || !val[0]) {
 194                 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
 195                 return;
 196         }
 197
 198         /* Fused TUNE2 value is the higher nibble only */
 199         qusb2_setbits(qphy->base, QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
 200 }
 201
 202 static int qusb2_phy_poweron(struct phy *phy)
 203 {
 204         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 205         int num = ARRAY_SIZE(qphy->vregs);
 206         int ret;
 207
 208         dev_vdbg(&phy->dev, "%s(): Powering-on QUSB2 phy\n", __func__);
 209
 210         /* turn on regulator supplies */
 211         ret = regulator_bulk_enable(num, qphy->vregs);
 212         if (ret)
 213                 return ret;
 214
 215         ret = clk_prepare_enable(qphy->iface_clk);
 216         if (ret) {
 217                 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
 218                 regulator_bulk_disable(num, qphy->vregs);
 219                 return ret;
 220         }
 221
 222         return 0;
 223 }
 224
 225 static int qusb2_phy_poweroff(struct phy *phy)
 226 {
 227         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 228
 229         clk_disable_unprepare(qphy->iface_clk);
 230
 231         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 232
 233         return 0;
 234 }
 235
 236 static int qusb2_phy_init(struct phy *phy)
 237 {
 238         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 239         unsigned int val;
 240         unsigned int clk_scheme;
 241         int ret;
 242
 243         dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
 244
 245         /* enable ahb interface clock to program phy */
 246         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 247         if (ret) {
 248                 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
 249                 return ret;
 250         }
 251
 252         /* Perform phy reset */
 253         ret = reset_control_assert(qphy->phy_reset);
 254         if (ret) {
 255                 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
 256                 goto disable_ahb_clk;
 257         }
 258
 259         /* 100 us delay to keep PHY in reset mode */
 260         usleep_range(100, 150);
 261
 262         ret = reset_control_deassert(qphy->phy_reset);
 263         if (ret) {
 264                 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
 265                 goto disable_ahb_clk;
 266         }
 267
 268         /* Disable the PHY */
 269         qusb2_setbits(qphy->base, QUSB2PHY_PORT_POWERDOWN,
 270                       CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
 271
 272         /* save reset value to override reference clock scheme later */
 273         val = readl(qphy->base + QUSB2PHY_PLL_TEST);
 274
 275         qcom_qusb2_phy_configure(qphy->base, qphy->cfg->tbl,
 276                                  qphy->cfg->tbl_num);
 277
 278         /* Set efuse value for tuning the PHY */
 279         qusb2_phy_set_tune2_param(qphy);
 280
 281         /* Enable the PHY */
 282         qusb2_clrbits(qphy->base, QUSB2PHY_PORT_POWERDOWN, POWER_DOWN);
 283
 284         /* Required to get phy pll lock successfully */
 285         usleep_range(150, 160);
 286
 287         /* Default is single-ended clock on msm8996 */
 288         qphy->has_se_clk_scheme = true;
 289         /*
 290          * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 291          * clock scheme is selected. If yes, then disable differential
 292          * ref_clk and use single-ended clock, otherwise use differential
 293          * ref_clk only.
 294          */
 295         if (qphy->tcsr) {
 296                 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
 297                                   &clk_scheme);
 298                 if (ret) {
 299                         dev_err(&phy->dev, "failed to read clk scheme reg\n");
 300                         goto assert_phy_reset;
 301                 }
 302
 303                 /* is it a differential clock scheme ? */
 304                 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
 305                         dev_vdbg(&phy->dev, "%s(): select differential clk\n",
 306                                  __func__);
 307                         qphy->has_se_clk_scheme = false;
 308                 } else {
 309                         dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
 310                                  __func__);
 311                 }
 312         }
 313
 314         if (!qphy->has_se_clk_scheme) {
 315                 val &= ~CLK_REF_SEL;
 316                 ret = clk_prepare_enable(qphy->ref_clk);
 317                 if (ret) {
 318                         dev_err(&phy->dev, "failed to enable ref clk, %d\n",
 319                                 ret);
 320                         goto assert_phy_reset;
 321                 }
 322         } else {
 323                 val |= CLK_REF_SEL;
 324         }
 325
 326         writel(val, qphy->base + QUSB2PHY_PLL_TEST);
 327
 328         /* ensure above write is through */
 329         readl(qphy->base + QUSB2PHY_PLL_TEST);
 330
 331         /* Required to get phy pll lock successfully */
 332         usleep_range(100, 110);
 333
 334         val = readb(qphy->base + QUSB2PHY_PLL_STATUS);
 335         if (!(val & PLL_LOCKED)) {
 336                 dev_err(&phy->dev,
 337                         "QUSB2PHY pll lock failed: status reg = %x\n", val);
 338                 ret = -EBUSY;
 339                 goto disable_ref_clk;
 340         }
 341
 342         return 0;
 343
 344 disable_ref_clk:
 345         if (!qphy->has_se_clk_scheme)
 346                 clk_disable_unprepare(qphy->ref_clk);
 347 assert_phy_reset:
 348         reset_control_assert(qphy->phy_reset);
 349 disable_ahb_clk:
 350         clk_disable_unprepare(qphy->cfg_ahb_clk);
 351         return ret;
 352 }
 353
 354 static int qusb2_phy_exit(struct phy *phy)
 355 {
 356         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 357
 358         /* Disable the PHY */
 359         qusb2_setbits(qphy->base, QUSB2PHY_PORT_POWERDOWN,
 360                       CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
 361
 362         if (!qphy->has_se_clk_scheme)
 363                 clk_disable_unprepare(qphy->ref_clk);
 364
 365         reset_control_assert(qphy->phy_reset);
 366
 367         clk_disable_unprepare(qphy->cfg_ahb_clk);
 368
 369         return 0;
 370 }
 371
 372 static const struct phy_ops qusb2_phy_gen_ops = {
 373         .init           = qusb2_phy_init,
 374         .exit           = qusb2_phy_exit,
 375         .power_on       = qusb2_phy_poweron,
 376         .power_off      = qusb2_phy_poweroff,
 377         .owner          = THIS_MODULE,
 378 };
 379
 380 static const struct of_device_id qusb2_phy_of_match_table[] = {
 381         {
 382                 .compatible     = "qcom,msm8996-qusb2-phy",
 383                 .data           = &msm8996_phy_cfg,
 384         },
 385         { },
 386 };
 387 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
 388
 389 static int qusb2_phy_probe(struct platform_device *pdev)
 390 {
 391         struct device *dev = &pdev->dev;
 392         struct qusb2_phy *qphy;
 393         struct phy_provider *phy_provider;
 394         struct phy *generic_phy;
 395         struct resource *res;
 396         int ret, i;
 397         int num;
 398
 399         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
 400         if (!qphy)
 401                 return -ENOMEM;
 402
 403         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 404         qphy->base = devm_ioremap_resource(dev, res);
 405         if (IS_ERR(qphy->base))
 406                 return PTR_ERR(qphy->base);
 407
 408         qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
 409         if (IS_ERR(qphy->cfg_ahb_clk)) {
 410                 ret = PTR_ERR(qphy->cfg_ahb_clk);
 411                 if (ret != -EPROBE_DEFER)
 412                         dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
 413                 return ret;
 414         }
 415
 416         qphy->ref_clk = devm_clk_get(dev, "ref");
 417         if (IS_ERR(qphy->ref_clk)) {
 418                 ret = PTR_ERR(qphy->ref_clk);
 419                 if (ret != -EPROBE_DEFER)
 420                         dev_err(dev, "failed to get ref clk, %d\n", ret);
 421                 return ret;
 422         }
 423
 424         qphy->iface_clk = devm_clk_get(dev, "iface");
 425         if (IS_ERR(qphy->iface_clk)) {
 426                 ret = PTR_ERR(qphy->iface_clk);
 427                 if (ret == -EPROBE_DEFER)
 428                         return ret;
 429                 qphy->iface_clk = NULL;
 430                 dev_dbg(dev, "failed to get iface clk, %d\n", ret);
 431         }
 432
 433         qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
 434         if (IS_ERR(qphy->phy_reset)) {
 435                 dev_err(dev, "failed to get phy core reset\n");
 436                 return PTR_ERR(qphy->phy_reset);
 437         }
 438
 439         num = ARRAY_SIZE(qphy->vregs);
 440         for (i = 0; i < num; i++)
 441                 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
 442
 443         ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
 444         if (ret) {
 445                 dev_err(dev, "failed to get regulator supplies\n");
 446                 return ret;
 447         }
 448
 449         /* Get the specific init parameters of QMP phy */
 450         qphy->cfg = of_device_get_match_data(dev);
 451
 452         qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
 453                                                         "qcom,tcsr-syscon");
 454         if (IS_ERR(qphy->tcsr)) {
 455                 dev_dbg(dev, "failed to lookup TCSR regmap\n");
 456                 qphy->tcsr = NULL;
 457         }
 458
 459         qphy->cell = devm_nvmem_cell_get(dev, NULL);
 460         if (IS_ERR(qphy->cell)) {
 461                 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
 462                         return -EPROBE_DEFER;
 463                 qphy->cell = NULL;
 464                 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
 465         }
 466
 467         generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
 468         if (IS_ERR(generic_phy)) {
 469                 ret = PTR_ERR(generic_phy);
 470                 dev_err(dev, "failed to create phy, %d\n", ret);
 471                 return ret;
 472         }
 473         qphy->phy = generic_phy;
 474
 475         dev_set_drvdata(dev, qphy);
 476         phy_set_drvdata(generic_phy, qphy);
 477
 478         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 479         if (!IS_ERR(phy_provider))
 480                 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
 481
 482         return PTR_ERR_OR_ZERO(phy_provider);
 483 }
 484
 485 static struct platform_driver qusb2_phy_driver = {
 486         .probe          = qusb2_phy_probe,
 487         .driver = {
 488                 .name   = "qcom-qusb2-phy",
 489                 .of_match_table = qusb2_phy_of_match_table,
 490         },
 491 };
 492
 493 module_platform_driver(qusb2_phy_driver);
 494
 495 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
 496 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
 497 MODULE_LICENSE("GPL v2");